QUASI-CYCLIC LDPC CODING

The invention presented here is applied to the data transmission field, and more specifically, to the communication of data across noisy media, that is, communication media or channels that may introduce errors in the communication.

PRIOR ART

In communication environments it is common for the communication medium or external signals to introduce signal errors. Said errors must be detected and, if possible, corrected in reception so that the correct data may be recovered. Several ways exist for including error detection and correction in the state of the art, one of them being the codification and decodification of the data based on low density parity check codes for correcting errors.

Low density parity check codes (LDPC) are error correction codes that are used in transmitting over noisy transmission channels. These codes introduce a certain redundancy in the message (a larger number of bits is sent than in the original message), but in such a way that at reception it is possible to detect whether there are errors in the message received and correct them.

An LDPC code is a code whose parity matrix is not very dense, that is to say that the majority of its elements are zeros. This type of code was published for the first time at the beginning of the 1960s, by Robert G. Gallagher "Low Density Parity Check Codes," M.I.T. Press, 1963, and was shown to have features very close to the known Shannon limit (theoretical maximum rate for data transmission). However, with the original definition of the codes and the technology of that time, an attainable implementation of adequate complexity was not possible. Recently, thanks to the evolution of integrated circuits and the invention of structured matrices, these codes are once again of great interest.

In the state of the art there are multiple methods for achieving codification and decodification of errors. Some methods are those published in patents US 7,343,548B2 and US 7,203,897B2, both entitled "Method and Apparatus for Encoding and Decoding Data," each of which outlines methods for improving protection when confronted with errors in data transmission. The invention can also be related to standards IEEE802.16e and 802.11n, which present codification and decodification for reducing errors. In any case, the patents and standards mentioned use the double diagonal structure, which is known in the state of the art, while the structure presented in this document is new and allows an implementation with better features without increasing the level of complexity (thus at lower cost) of protection against errors in communicating data over noisy media. It is known in the state of the art that having columns with a Hamming weight equal to or less than 2 in the parity matrix restricts the features of the LDPCs. However, for reasons of complexity of implementation of the codifier, matrices with a double diagonal section H_b1 have been used in the state of the art. The new structure presented in this document, which adds a third diagonal to the section H_b1 of the binary model matrix, allows the total number of columns in the parity matrix with a Hamming weight less than or equal to 2 to be lower, and thus better features can be achieved. This third diagonal was selected in such a way that the increase in the complexity of implementation of the codifier is practicably negligible.

US 2008/0222486 A1 relates to methods and apparatus for encoding and decoding low density parity check (LDPC) codes. This document discloses a novel apparatus and method for encoding data using a low density parity check (LDPC) code capable of representation by a bipartite graph. To encode the data, an accumulate chain of a plurality of low degree variable nodes may be generated. The accumulate chain may then be closed to form a loop twice, once using a low degree variable nodes and once using a higher degree variable which is higher than the low degree variable node, where the higher degree variable node comprises a non-loop-closing edge. In one embodiment disclosed in this document, the plurality of low degree variable nodes may have the same permutation on each edge.

The documents previously presented do not interfere with the novelty nor the inventive superiority of the present invention. Although they are all based on utilization of the LDPC technology, which is known in the state of the art, the invented method and device of this document utilizes a type of quasi-cyclic code (Quasi-Cyclic Low Density Parity Check Code, or QC-LDPC), and applies a parity matrix with a different structure as the central point of the invention.

Throughout this document, a specific nomenclature will be employed to differentiate the elements utilized throughout the description of the invention. A bold capital letter (e.g., A) indicates that the element is a matrix; a bold small letter (e.g., a) indicates that the element is a vector, while a small non-bold letter (e.g., a) indicates that the element is a scalar value. On the other hand, scalar elements that comprise a matrix of the size MxN are indicated in the form a(i,j), where the tuple (i,j) is the position of said element within the matrix, with 0≤i≤M -1 being the row number and 0≤j≤N -1 the column number. The elements that comprise a vector of size M are annotated in the form a(i), with (i) being the position of the element in the vector (0 ≤i≤M -1).

Also, throughout the invention the term "cyclical rotation" will be used, which will be defined below. A cyclical rotation z on a vector a=|a(0), a(1),...,a(M - 2), a(M -1)| consists in cyclically rotating its elements toward the right, obtaining the vector [a((M - z)%M),...,a((M - z - 1)%M)] as the result, with % being the "module" operator. In the same way, a cyclical rotation z applied over a matrix A = [a(0),...,,a(N-1)] operates on its columns, obtaining the matrix [a((N-z)%N),...,a((N-z-1)%N)] as the result. A cyclical rotation can also be defined in the opposite direction (toward the left)so that a cyclical rotation z toward the right is equivalent to a cyclical rotation M -z and N -z respectively for vector and matrix toward the left.

DESCRIPTION OF THE INVENTION

It is therefore the object of the present invention to provide an improved coding of data applying a parity matrix to a block of data and using LDPC codes.

This object is solved by the subject matter of claim 1.

Preferred embodiments are defined by the dependent claims.

In order to achieve the objectives and avoid the drawbacks indicated in above sections, the invention consists of a method and device for communicating data over noisy media. Concretely, the invention presents a method for codifying data used in transmission, its associated codification device, a method for decodifying and its associated decodification device. This group of inventions makes up a unique inventive concept, which will be described below. If the method or device is used in transmission, the equivalent must also be used in reception, and vice versa, so that the data sent can be recovered.

The method for codifying data is applied in transmission and generates parity bits on a block of data in such a way that a code word of N bits is generated from a word of K bits (N>K) that includes protection against errors. Said procedure comprises multiple steps. First a factor b is selected, which is a natural number between 1 and k such that the division of N and K by the factor b will be natural numbers (n=N/b; k=K/b). Below we define a binary model matrix H₀ = [H_a/H_b] of size (n-k) x n as the combination of a submatrix corresponding to the positions of the data bits H_a and a submatrix corresponding to the parity bits H_b, where said second submatrix H_b = [hb₀|Hb₁] is composed of a column vector of n-k positions h_b0 and a matrix H_b1 having a triple diagonal structure, that is, where the elements of the two central diagonals h_b1(i, i), h_b1(i+1, i) 0≤i≤n-k-2 and the diagonal of the last row h_bl(n-k-1,0) are equal to 1, where n-k is the number of rows and columns of the matrix H_b, and the rest of the elements are equal to zero. Afterward, the compact matrix H₁ is generated and from it, the parity matrix H. From there, one takes a block of data and uses the parity matrix H on the block of data to determine the parity bits that correspond to said block. Finally, the parity bits are transmitted together with the block of data.

In one implementation of the method, it is possible to eliminate one or more elements of the code word before they are transmitted, reducing the redundancy in the transmission without seriously harming the capacity for protection against errors. This technique is called "puncturing."' In this case the word transmitted will have a smaller number of bits than the code word obtained with the initial procedure.

The data codification device comprises means for storing the compact matrix H₁ derived from a binary model matrix H₀ = [H_a|H_b] formed as the combination of a submatrix corresponding to the position of the data bits H_a and a submatrix corresponding to the parity bits H_b, where said second submatrix H_b =[hb₀|Hb₁] is composed of a column vector of n-k positions h_b0 and a matrix H_b1 having a triple diagonal structure, that is, where the elements of the two central diagonals h_b1(i, i), h_b1(i+1, i) 0≤i≤n-k-2 and the diagonal of the last row h_b1(n-k-1,0) are equal to 1, where n-k is the number of rows and columns of the matrix H_b, and the rest of the elements are equal to zero; and of a microprocessor that takes the block of data, uses the compact matrix H₁ to generate the parity matrix H, applies the parity matrix H to the block of data to obtain the parity bits corresponding to said block and adds the parity bits to the block of data before they are transmitted.

In one concrete implementation of this device, one or more elements of the code word are eliminated after adding the parity bits to the block of data but prior to transmission by applying the puncturing technique. In this way the word transmitted will have a smaller number of bits than the code word originally generated.

On the other hand, the data decodification method operates at reception and estimates which is the block of data received from a signal vector received from the channel. From a received code word of N bits (which can have errors due to the channel noise) the K-bit data word that the transmitter wanted to send is obtained. This first takes a signal vector from the channel and the binary model matrix H₀ = [H_a/H_b] which is a combination of a submatrix corresponding to the position of the data bits H_a and a submatrix corresponding to the parity bits H_b, where said second submatrix H_b = [hb₀|Hb₁] is composed of a column vector of n-k positions h_b0 and a matrix H_b1 having a triple diagonal structure, that is, where the elements of the two central diagonals h_b1 (i, i), h_b1 (i+1,i) 0≤i≤n-k-2 and the diagonal of the last row h_b1(n-k-1,0) are equal to 1, where n-k is the number of rows and columns of the matrix H_b, and the rest of the elements are equal to zero. Afterward, the compact matrix H₁ is generated and from it, the parity matrix H, and finally the data block is estimated from the vector signal received and the parity matrix H.

If the puncturing technique was used in transmission, the lost data must be recovered at reception. In this case, an indicator value is inserted in the positions eliminated in transmission by the puncturing technique prior to making the estimation of the data block from the signal vector received and the parity matrix.

The data decodification device comprises means for storing the compact matrix H₁ that is derived from the binary model matrix H₀=[H_a/H_b] which is a combination of a submatrix corresponding to the position of the data bits H_a and a submatrix corresponding to the parity bits H_b, where said second submatrix H_b = [hb₀|Hb₁] is composed of a column vector of n-k positions h_b0 and a triple diagonal structure H_b1, that is, one in which the elements of the two central diagonals h_b1(i,i), h_b1(i+1,i) 0≤i≤n-k-2 and the diagonal of the last row h_b1(n-k-1,0) are equal to 1, where n-k is the number of rows and columns of the matrix H_b, and the rest of the elements are equal to zero; a microprocessor that generates the parity matrix H from the compact matrix H₁, applies said parity matrix H to the signal vector received, and estimates the data block received.

If the transmitting device used the puncturing technique, the lost data must be recovered before error correction is done. Therefore, in this implementation and before applying the parity matrix H to the signal vector received, an indicator value is inserted in the positions eliminated in transmission by the puncturing technique.

In one implementation it is possible to use one of the following compact matrices H₁ to obtain 336-bit code words with a codification rate of 1/2. The matrix:

or else this matrix:

In another implementation it is possible to use one of the following compact matrices H₁ to obtain 1920-bit code words with a codification rate of 1/2. The matrix:

or else this matrix:

In another implementation it is possible to use one of the following compact matrices H₁ to obtain 8640-bit code words with a codification rate of 1/2. The matrix:

or else the matrix:

In another implementation it is possible to use the following compact matrix H₁ to obtain 1440-bit code words with a codification rate of 2/3.

In another implementation it is possible to use the following compact matrix H₁ to obtain 6480-bit code words with a codification rate of 2/3:

In another implementation it is possible to use the following compact matrix H₁ to obtain 1152-bit code words with a codification rate of 5/6:

In another implementation it is possible to use the following compact matrix H₁ to obtain 5184-bit code words with a codification rate of 5/6:

One implementation in which the puncturing technique is used starts with an 1152-bit code word and codification rate of 5/6 and applies the following puncturing pattern:

in order to obtain a 1080-bit code word and codification rate of 16/18.

Another implementation in which the puncturing technique is used starts with a code word with 5184 bits and a codification rate of 5/6 and applies the following puncturing pattern

to obtain a code word of 4860 bits and codification rate of 16/18.

Another implementation in which the puncturing technique is used starts with a code word with 1152 bits and a codification rate of 5/6 and applies the following puncturing pattern

to obtain a 1008-bit code word and codification rate of 20/21.

And last, a final implementation in which the puncturing technique is used starts with a 5184-bit code word and codification rate of 5/6 and applies the following puncturing pattern

to obtain a 4536-bit code word and codification rate of 20/21.

Below, in order to facilitate a greater understanding of this descriptive document, is given the description, by way of illustration but not limitation, of one example implementation of the invention. This forms an integral part of the same document.

BRIEF DESCRIPTION OF THE FIGURES

• Figure 1.- Shows the block diagram of the codifier in the transmitter.
• Figure 2.- Shows the block diagram of the decodifier in the transmitter.
• Figure 3.- Shows the two-part graph of the matrix H of the example.
• Figure 4. - Shows the flow diagram of the construction of a structured LDPC code.

DESCRIPTION OF ONE EXAMPLE OF IMPLEMENTATION OF THE INVENTION

Following is the description of one example of implementation of the invention, making reference to the numbering adopted in the figures.

The problem that the invention procedure is intended to solve, from a theoretical point of view, consists of success in optimizing correction of errors in data communication using low-cost hardware implementations and LDPC codes.

An LDPC code is a linear code that operates on blocks of data. The code is defined by its parity matrix H. In this implementation example the codes are binary codes, but it is possible to generalize the invention to codes on any Galois field GF(q), where q is ≥2.

In transmission we have blocks of data composed of K bits. Said data block is designated as u = [u(0),u(1),...,u(K - 1)]. After applying the method of the invention, a word is generated of a linear code v = [v(0),v(1),...,v(N -1)]with N bits (where N<K). Said code is generated through the product v=uG, where G is a binary matrix KxN, generator of the LDPC code. The set of possible codes generated is called set C, and the codification rate of the code will be R=K/N.

Therefore, it is possible to define a code C of codification R as the set of vectors v∈C generated by all the possible 2^K binary vectors by applying the generator matrix G to them. An equivalent definition would be that C is the vectorial space of size N included in the base composed of the K rows of the matrix G. Another alternative form of defining code C is through its parity matrix H, which is the form most used in the state of the art. This matrix, in size (N-K)x N, has as rows the base of the dual space C, and therefore GH^T =0. Any vector of the code satisfies $${\mathrm{vH}}^{\mathrm{T}}=\mathrm{0}$$

(where "T" is the transposition operator).

At the time these codes are utilized from a practical viewpoint, it is preferable to consider the codes as systematic codes, that is, those in which the bits of the code word are between the data bits. Without losing generality, this example is centered on the case where v=[u|p], where p=[p(0),p(1),... p(N-K-1)] is a vector composed of the parity bits, u the data block that is to be transmitted and v the code word actually transmitted (after including the LDPC code).

Below is shown an example of implementation in which the relation between the parity matrix and a code word can be observed. In this example, the code has a codification rate of R=1/2 and is defined by the following parity matrix: $$H=\left[\begin{array}{cc}\begin{array}{ccccc}1& 1& 0& 1& 0\\ 1& 1& 1& 0& 0\\ 1& 1& 1& 0& 1\\ 0& 0& 1& 1& 1\\ 0& 0& 0& 1& 1\end{array}& \begin{array}{ccccc}1& 0& 0& 1& 1\\ 1& 0& 1& 0& 1\\ 0& 1& 0& 1& 0\\ 1& 1& 1& 0& 0\\ 0& 1& 1& 1& 1\end{array}\end{array}\right]$$

In this matrix, the left section corresponds to the K=5 data bits, while the right section corresponds to the N-K=5 parity bits. By applying the equation vH^T =0 to the matrix H the following system of equations is obtained: $$\{\begin{array}{c}u\left(0\right)+u\left(1\right)+u\left(3\right)+p\left(0\right)+p\left(3\right)+p\left(4\right)=0\\ u\left(0\right)+u\left(1\right)+u\left(2\right)+p\left(0\right)+p\left(2\right)+p\left(4\right)=0\\ u\left(0\right)+u\left(1\right)+u\left(2\right)+u\left(4\right)+p\left(1\right)+p\left(3\right)=0\\ u\left(2\right)+u\left(3\right)+u\left(4\right)+p\left(0\right)+p\left(1\right)+p\left(2\right)=0\\ u\left(3\right)+u\left(4\right)+p\left(1\right)+p\left(2\right)+p\left(3\right)+p\left(4\right)=0\end{array}$$

An LDPC code can also be represented in graphic form with a two-part graph called a Tanner graph. In a Tanner graph the vertices or nodes are classified in two separate groups or sets: the "variable nodes", which represent the bits of the code word, and the "check nodes," which represent the parity relationships. Between both sets of nodes are found the possible edges that define the parity equation. In the case of the code defined in the preceding example, its corresponding graph is represented in Figure 3, where we find 10 variable nodes (14) and 5 check nodes (16), united by multiple edges (15). Each check node is united through edges to 6 variable nodes, as represented in the preceding system of equations. It can be observed that the graph has as many control and variable nodes as the corresponding parity matrix has rows and columns, and that an edge is found between the check node i and variable node j when the element h(i,j) of the matrix, that is, the one located in the row i=0,..., N-K-1 and column j=0,..., N-1 is non-zero.

On the other hand, cycles can be defined on LDPC codes, where a cycle of length 2c is defined as the path of 2c length edges that processes c check nodes and c variable nodes in the Tanner graph that represents the code before returning to the same beginning node. To optimize the features of the code, it can be demonstrated that it is of vital importance that the number of short cycles be the minimum possible. The cycle of minimum length is called girth. It is particularly desirable that the girth be greater than 4 in order avoid reducing the features of an iterative decodifier.

In the original description, R. Gallagher presented codes whose parity matrices were generated randomly. In the state of the art it is generally known that in order to obtain good features, near the Shannon limit, the size of the code must be relatively large, and as a consequence of that, the parity matrix must be large. The problem is that matrices that are large and generated randomly cause difficulty in the implementation of both the codifier and decodifier. One way to avoid this difficulty is to use matrices with a regular structure. Following are the necessary steps for generating a regular structure:

1. 1. First, one generates a binary model matrix H₀ of size (n-k) × n where n<N, k<K and R=k/n=K/N. If the Hamming weight of the columns and rows of H₀ is constant, the generated code is called regular LDPC. However, better features can be obtained if the matrix is irregular, that is, if the weights of the columns follow a statistical distribution dependent upon the codification rate and of the channel where the data transmission will finally be done.
2. 2. Once the binary model matrix H₀ has been obtained, the compact matrix H₁ is generated, replacing each element of H₀ that is equal to "1" with a pseudo-random positive whole number 0≤x<b (where b=N/n) and each element equal to "0" with the value -1.
3. 3. To obtain the parity matrix H, the positive elements of H₁ are replaced by an identity submatrix rotated cyclically the number of times indicated by the value of the positive element of H₁ in question, and the elements equal to -1 are replaced by a null submatrix of the same size. The size of these submatrices will also be b x b.

The result is a parity matrix H of size (N-K) x N which defines an LDPC code with codification rate R=K/N. The grade of density (sparseness) of the matrix will depend upon the size of b. Generally, the larger b is, the better the features that are obtained by using an iterative decodifier.

If the cycles of the generated matrix (Tanner graph) turn out to be very short, step 2 (or even step 1 if necessary) should be applied for the purpose of improving these properties.

In order to facilitate the implementation of the codifier, it is necessary to generate the binary model matrix H₀ in a specific form. First, said matrix is divided into two parts H₀ = [H_a|H_b] where the submatrix H_a corresponds to the positions of the data bits and H_b to the parity bits. The first submatrix is generated pseudo-randomly in the way described previously. However, the second section is usually deterministic.

This second section H_b, according to the state of the art and intended to facilitate the design of an efficient codifier, takes one of the following two forms; the first form is $${\mathbf{H}}_0=\left[\begin{array}{cc}{\mathrm{h}}_{b0}& {\mathbf{H}}_{b1}\end{array}\right]=\left[\begin{array}{cc}\begin{array}{c}{h}_b\left(0\right)\\ h_b\left(1\right)\\ \\ \\ \\ h_b\left(n-k-1\right)\end{array}& \begin{array}{ccccc}1& 0& & & 0\\ 1& 1& \ddots & & \\ 0& 1& \ddots & \ddots & \\ & \ddots & \ddots & 1& 0\\ & & \ddots & 1& 1\\ 0& & & 0& 1\end{array}\end{array}\right]$$

where the first section is a pseudo-random column vector having a Hamming weight greater than 2 and H_b1 is a double-diagonal matrix whose elements h_b1(i,j) are equal to "1" when i=j, i=j+1 and equal to "0" in the remaining positions.

The second way of generating H_b is totally double diagonal $${\mathbf{H}}_b=\left[\begin{array}{c}\begin{array}{cccccc}1& 0& & & & 0\\ 1& 1& \ddots & & & \\ 0& 1& \ddots & & & \\ & \ddots & \ddots & \ddots & \ddots & \\ & & \ddots & 1& 1& 0\\ 0& & & 0& 1& 1\end{array}\end{array}\right]$$

where the elements of the submatrix h_b(i,j) are equal to "1" when i=j, i=j+1 and equal to zero in the remaining positions.

Once this base matrix structure has been generated, the compact matrix H₁ is generated, in the form previously described with the sole exception that in the double diagonal part of H_b, the "1"s are replaced by the same positive whole number and the "0"s by "-1." Also, the final parity matrix is obtained by changing the positive wholes by identities rotated cyclically and the negatives by a null submatrix. The procedure can be observed graphically in Figure 4, where block (17) generates the binary model matrix H₀, block (18) generates the compact matrix H₁ , block (19) decides whether the cycles are long enough, and the process goes on to generate the parity matrix H with block 20, or else if the cycles are short, the model matrix (21) or else the base matrix (22) is generated again.

The method and device of the invention together modify the structure of the parity matrix known in the state of the art in order to facilitate the final implementation of the codification and decodification and improve the features. For this, the proposed structure consists in that the section of the binary model H₀ corresponding to the parity bits has the following form: $${\mathbf{H}}_b=\left[\begin{array}{cc}{\mathrm{h}}_{b0}& {\mathbf{H}}_{b1}\end{array}\right]=\left[\begin{array}{cc}\begin{array}{c}{h}_b\left(0\right)\\ h_b\left(1\right)\\ \\ \\ \\ h_{\mathit{bn}}\left(n-k-1\right)\end{array}& \begin{array}{ccccc}1& 0& & & 0\\ 1& 1& \ddots & & \\ 0& 1& \ddots & \ddots & \\ & \ddots & \ddots & 1& 0\\ & & \ddots & 1& 1\\ 1& & & 0& 1\end{array}\end{array}\right]$$

where the structure H_b1 is triple diagonal, that is, in addition to the elements of the two central diagonals h_b1(I,i), h_b1(i+1,i), the element of the diagonal of the last line h_b1 (n-k-1,0) is also equal to "1." The compact matrix is generated in the way described previously except that the element of the last row equal to "1" is replaced by a strictly positive whole w≥0.

A binary model matrix H₀ for r=1/2 with n=24 and k=12 might have the following structure:

A compact matrix H₁ derived from the preceding by a block size N=336 and therefore having an expansion factor b=14 would be the following:

or as preferred, the following matrix can be used as an alternative:

For a different block size we can define a different compact matrix that can derive from the same binary model matrix or from another, different one.

To obtain code words of 1920 bits with a codification rate of 1/2, the following matrix can be used:

or else, preferably, the matrix:

A compact matrix for N=8640 bits with expansion factor 360 derived from a different binary model matrix would be the following:

Another preferential alternative for obtaining code words of 8640 bits with a codification rate of 1/2 is the matrix:

The step from compact matrix to binary model is univocal, but for the opposite step, it is not; that is to say, different compact matrices can be obtained from a binary model matrix. The binary matrix is introduced as a step that facilitates the description of the invention. It is possible to develop a compact matrix directly without going through the binary model matrix. In that case, for that compact matrix, its corresponding binary model matrix can be obtained which, if it is triple diagonal, will be in accord with the method of the invention.

The error correction codes can be "punctured," wherein the technique for puncturing consists in removing elements of the code word so that they will not be transmitted. In place of transmitting a code word v=[v(0),v(1),...,v(N-1)], a word w=[w(0),w(1),..., w(M-1)] will be transmitted, where M<N. The puncturing must be done in a controlled way, so that the necessary redundancy is transmitted in order for the decodifier of the receptor to be able to evaluate the transmitted data. This puncturing is applied to both the data bits and the parity bits. A pattern of puncturing can be defined as the sequence of bits that are to be transmitted as punctured, where said bit pattern can be periodic or aperiodic. In case there is no regularity, said pattern can be described with a vector pp of N positions, indicating with a "1" the bits to be transmitted and with a "0" the bits to be eliminated (punctured). Thanks to the puncturing technique, data communication can be amplified, since less redundancy is being sent. If the Hamming weight of the pattern pp is M, the total system rate of error codification is R=K/M.

For example, if we have a code with R=5/6 and block size N=5184 and we want to perform a puncturing in order to increase the rate to R=16/18, we can use the following puncturing pattern, which will yield a block with N=4860 bits:

In order to achieve implementation of LDPC codes, an electronic device is used, whether it be a program executed on a microprocessor or an FPGA or ASIC hardware implementation. Said device receives a block of data, calculates the parity bits, concatenates them with the information bits and submits them to the following phase of the transmitter to be adequately modulated and transmitted through the corresponding channel. The calculation of the parity bits may be done by means of the product of the generator matrix G or the solution of the system of equations presented previously.

The decodifier of LDPC codes is usually based on an iterative decodifier. A possible decodifier, among several state of the art options, consists of an estimator which, upon receiving the word corresponding to the transmitted code r=v+z, where Z is additive channel noise, makes a noise estimation ẑ such that (r-ẑ)H^T=0. In the case where the system makes use of the puncturing technique, before the decodifier there will be a unit that inserts an indicator in the punctured positions. This indicator serves to direct the decodifier to estimate the proper value in those positions.

Figure 1 shows the block diagram of a typical codifier, where (1) is the data block to be transmitted u=[u(0),u(1),...,u(K-1)], (2) is a memory that contains the representation of the parity matrix H or the generator matrix G, (3) is said matrix, (4) is the block that performs the codification algorithm, (5) is the linear code word obtained from the codification v=[v(0), v(1),..., v(N-1)], (6) is the block that does the puncturing, and (7) is the word obtained after puncturing w = [w(0), w(1),..., w(M - 1)].

Figure 2 shows the block diagram for a decodifier, where (8) represents the received signal from the channel s = [s₀,s₁,..., s_M-1], which will be similar to the word obtained after puncturing but after being affected by the channel noise, (9) represents the block that performs the "depuncturing," obtaining a word (10) r = [r(0), r(1),..., r(N - 1)] with the number of bits in the LDPC code. (11) is the memory that contains either the parity matrix or the generator matrix in the receiver and transmits it (12) to the block that performs the decodifier algorithm (13). The output of this block will be the reconstituted data (14) û=[û(0),û(1),...,û(K-1)].