Continuous-time oversampling pipeline analog-to-digital converter |
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| 申请号 | EP14157548.0 | 申请日 | 2014-03-03 | 公开(公告)号 | EP2779464A3 | 公开(公告)日 | 2015-08-05 |
| 申请人 | Analog Devices Global; | 发明人 | Shibata, Hajime; | ||||
| 摘要 | A converter may include multiple converter stages connected in series. Each converter stage may receive a clock signal and an analog input signal, and may generate an analog output signal and a digital output signal. Each converter stages may include an encoder generating the digital output signal, a decoder generating a reconstructed signal, a delaying converter generating a delayed signal, and an amplifier generating a residue signal, wherein the delayed signal may be a continuous current signal. | ||||||
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