SWITCHING CIRCUIT |
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申请号 | EP15174613.8 | 申请日 | 2015-06-30 | 公开(公告)号 | EP3113358B1 | 公开(公告)日 | 2018-08-29 |
申请人 | IMEC VZW; | 发明人 | ZHANG, Xiaoqiang; INGELS, Mark Maria Albert; | ||||
摘要 | The present invention relates to a conversion circuit (10) comprising - a first input terminal for receiving a digital signal (RFin), - a second input terminal for receiving a bias voltage signal (Vb), - an output terminal for outputting a current, - a first (SW1) and a second (SW2) switch transistor connected to said first input terminal for receiving said digital signal (RFin), - a first (M1) and a second (M2) current source transistor connected to said second input terminal for receiving said bias voltage signal (Vb), whereby said conversion circuit comprises a first branch wherein said first switch transistor is connected to said output terminal via said first current source transistor and a second branch wherein said second current source transistor is connected to said output terminal via said second switch transistor. | ||||||
权利要求 | |||||||
说明书全文 | The present invention is generally related to the field of switching circuits suffering from charge injection, as encountered in digital transmitters, high speed DACs and the like. Nanoscale CMOS has brought many high speed applications to the consumer thanks to the computing power that can be squeezed into modern signal processors. Unfortunately, the intrinsic analog properties of CMOS transistors do not follow the improvements of their digital counterparts. CMOS transistor parameters like output impedance, supply versus threshold ratio or intrinsic gain typically worsen with the advance of the CMOS technological nodes. One example of an important application field relates to digital radio transmitters. Modern communication schemes impose tough requirements on radio transmitters. Transmitters operating at RF have to combine hard requirements such as RF bandwidth, linearity and out-of-band noise while maintaining a high efficiency. As a result, the porting of an analog RF transmitter from one technological node to another is complicated and thus slow and costly. Thus, transmitters need to have the least possible analog circuitry. In addition, it is desirable for radio transmitters to be easily scalable with the advancement of CMOS technologies. To address the problem of analog RF transmitters, a new family of RF transmitters, digital transmitters (also referred to as RF-DACs or Direct Digital RF Modulators, DDRM), has been adopted. The digital transmitters feature a predominantly digital circuitry which is better suited for advanced CMOS technology and which scales much better with the various CMOS technological nodes. In contrast to their analog counterpart, the performance of digital transmitters intrinsically improves with the scaling of CMOS technology. The first digital transmitters were based on a polar architecture, in which a phase modulated local oscillator (LO) signal is fed to a multitude of DDRM units and amplitude modulation is performed by enabling or disabling (switching on or off) these DDRM unit amplifiers and then combining their output power to form a modulated RF analog signal. Later, Cartesian DDRM architectures consisting of two such digital amplitude modulators, for modulating the in-phase (I) and the quadrature (Q) signals with the respective LO phases, were also adopted in digital transmitters. The outputs of these two digital amplitude modulators are summed before being fed to the antenna for transmission. An RF DAC is created by summing the outputs of a multitude of switched current sources. In a traditional high speed DAC a differential operation is typically applied and the current of the unit current source is switched to either the positive or the negative side in order to keep the current in the current source constant. To achieve a low instantaneous amplitude during modulation at the RFDAC output a number of unit cells (current sources) is effectively turned off in order to avoid power waste and to keep a high efficiency of the transmitter. In the paper " Switching activity of the switch SW1 in an RF-DAC unit positioned as in In order to avoid the need for predistortion, it is essential to keep the output impedance variation small relative to the load impedance. Therefore, the unit cell further comprises an additional transistor M3 in cascode to the current source transistor M1, as illustrated in In the implementation shown in Unfortunately, as the rising and falling edges at the source terminal of the current source transistor are not equal and as the settling of the bias node is typically much slower than the switching frequency of the switch, the amounts of charge injected onto and extracted from the decoupling capacitance within one switching sequence are not equal and some residual charge will persist. This residual charge is compensated by the bias source, but due to its limited bandwidth, it may not occur within one switching clock cycle (see US application Hence, there is a need for modifying the RF DAC unit cell so that charge injection is reduced and thus any need for providing complex predistortion is avoided. It is an object of embodiments of the present invention to provide for a RF DAC unit cell that by design is capable of limiting the need for predistortion or even of completely avoiding predistortion. The above objective is accomplished by the solution according to the present invention. In a first aspect the invention relates to a conversion circuit according to independent claim 1. The proposed solution indeed allows for avoiding complex predistortion as the switching circuit for a unit cell now contains two branches so conceived that charge injection into the bias of the first branch is compensated by an inverse charge injection in the second branch. Other advantageous embodiments of the invention are provided in accordance with the dependent claims. For purposes of summarizing the invention and the advantages achieved over the prior art, certain objects and advantages of the invention have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the invention. Thus, for example, those skilled in the art will recognize that the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. The above and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. The invention will now be described further, by way of example, with reference to the accompanying drawings, wherein like reference numerals refer to like elements in the various figures.
The present invention will be described with respect to particular embodiments and with reference to certain drawings but the invention is not limited thereto but only by the claims. Furthermore, the terms first, second and the like in the description and in the claims, are used for distinguishing between similar elements and not necessarily for describing a sequence, either temporally, spatially, in ranking or in any other manner. It is to be noticed that the term "comprising", used in the claims, should not be interpreted as being restricted to the means listed thereafter; it does not exclude other elements or steps. It is thus to be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the scope of the expression "a device comprising means A and B" should not be limited to devices consisting only of components A and B. It means that with respect to the present invention, the only relevant components of the device are A and B. Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures or characteristics may be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure, in one or more embodiments. Similarly it should be appreciated that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. Furthermore, some embodiments described herein include some but not other features included in other embodiments, as would be understood by those in the art. For example, in the following claims, any of the claimed embodiments can be used in any combination. It should be noted that the use of particular terminology when describing certain features or aspects of the invention should not be taken to imply that the terminology is being redefined herein to be restricted to include any specific characteristics of the features or aspects of the invention with which that terminology is associated. In the description provided herein, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description. In the present invention it is proposed to split the single branched traditional unit cell into two branches, which inject charges of opposite sign into the bias node and which are dimensioned (weighed) in such a way that the injected inverse charges effectively neutralize each other. This preferably occurs at an optimal ratio of the two branches. By placing (see The charge injected from the switching at the drain terminal has the opposite sign of the charge injected from switching at the source terminal of the active transistor. It is this observation that has led to the present invention. As this is a serious problem for the DDRM linearity, it is aimed to reduce the charge injected into the bias node by any given unit in the DDRM. Switching activity is inherent to a DDRM and cannot be avoided. This invention reduces the net charge injected into the bias node during the switching activity of the unit by injecting a negative charge into the bias node to compensate for any positive charge injection (and vice versa). This is performed in a clever way by splitting the unit into two sub-units (or two switching branches), which essentially have the same total dimensions, while no extra digital signals (LO or modulated LO) have to be created or provided, thus creating no overhead in area or power consumption. In the proposed solution the unit cell 10 is divided into two weighted smaller sub-units, such that the sum of the sizes of both sub-units correspond to the original unit size. The first sub-unit (in branch 1) is designed in a configuration of a switch transistor SW1 connected to the source terminal of a current source transistor M1, while the other sub-unit in branch 2 has a switch SW2 connected at the drain terminal of the current source transistor M2. The outputs of both sub-units are combined at node RFout, as shown in By sizing the ratio of both sub-units correctly, the charge injected by one sub-unit is compensated by the charge injected by the other sub-unit. This ratio is mainly dominated by the ratio between Cgs1 and Cgd2. The gate-source capacitance Cgs of a MOS transistor is typically larger by a factor of approximately 3 compared to the gate-drain capacitance Cgd of the same transistor. This ratio mainly determines the ratio of the sub-units. If the swing at the source terminal of the current source transistor M1 of the first sub-unit (SW1out) is different from the swing at the drain terminal of the current source transistor M2 of the second sub-unit (SW2out), this also has an impact on the sizing of the sub-units in such a way that a bigger swing requires a smaller capacitor to the gate for a certain charge injection into the bias node. When the sub-units are ideally weighted, opposite charges are injected through the respective Cgs1 and Cgd2 of both sub-units into the bias node, at the same instant in time, resulting in a net zero charge injection. As a result the bias voltage Vb stays constant and the current in the current sources as well (as shown in In another embodiment a transistor M3 in cascode to the drain terminal of M1 and the source terminal of SW2 may be provided, wherein the cascode transistor receives the output current of the two sub-units. Herein, the output current, RFout, of the unit cell is now at the drain terminal of the cascode transistor. The skilled person will readily understand that it is not essential to have a single output terminal RFout. The output terminal may in certain embodiments of the invention be implemented as two separate terminals, one in each branch. In a typical use case, for example in polar-based transmitters, the digital signal is a modulated local oscillator signal. A digital radio transmitter normally contains a multitude of conversion circuits 10 connected in parallel as described above. Usually the digital radio transmitter also comprises a bias circuit 20 to generate the bias voltage signal. The bias circuit comprises a decoupling capacitance Cd at its output. The bias circuit is connected with one or more of the unit cells. Various options can be envisaged. In one embodiment each unit cell is provided with a bias circuit. Alternatively, some of the unit cells or all of them can be connected to a separate bias circuit. Some alternative unit cell implementations are shown in the remaining figures. In Other improvements can be implemented into the unit cell 10 that are also compatible with the idea. For example, in While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. The foregoing description details certain embodiments of the invention. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the invention may be practiced in many ways. The invention is not limited to the disclosed embodiments. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. A computer program may be stored/distributed on a suitable medium, such as an optical storage medium or a solid-state medium supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems. Any reference signs in the claims should not be construed as limiting the scope. |