MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING专利检索- .在FET源侧的电源偏置电压或电流由控制信号持续控制专利检索查询-专利查询网

MEMORY EFFECT REDUCTION USING LOW IMPEDANCE BIASING
申请号	EP14857354	申请日	2014-11-04	公开(公告)号	EP3066753A4	公开(公告)日	2017-06-21
申请人	MARVELL WORLD TRADE LTD;			发明人	SIGNOFF DAVID M; HE MING; LOEB WAYNE A;
摘要	A circuit includes a bias circuit for a biased transistor. The bias circuit includes a master-slave source follower circuit, a reference transistor, and a bias circuit voltage output coupled to the biased transistor and configured to provide a bias voltage. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor. A signal ground circuit may be coupled between the biased transistor and one or more components of the bias circuit that do not generate significant return currents to a power supply ground. A method includes generating a current in a reference transistor according to a first voltage generated using a master source follower circuit, generating a second voltage substantially identical to the first voltage using a slave source follower circuit, and providing the second voltage to a biased transistor. The reference transistor has a transconductance substantially identical to a transconductance of the biased transistor.
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