| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | Decoder, receiver, and electronic device | US15729169 | 2017-10-10 | US09992442B2 | 2018-06-05 | Takeshi Aoki; Munehiro Kozuma; Yoshiyuki Kurokawa |
| A decoder with reduced power consumption is provided. The decoder includes a first circuit and a second circuit for holding data. The second circuit includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor include an oxide semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor. The decoder is configured to provide or stop power supply to the semiconductor device depending on a packet ID of a header portion of the data and to perform data storing or restoring of data between the first circuit and the second circuit. | ||||||
| 2 | SYMBOL DECODER, THRESHOLD ESTIMATION AND CORRELATION SYSTEMS AND METHODS | US13705907 | 2012-12-05 | US20140152485A1 | 2014-06-05 | David Levy |
| A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal. | ||||||
| 3 | DECODER, RECEIVER, AND ELECTRONIC DEVICE | US15729169 | 2017-10-10 | US20180109752A1 | 2018-04-19 | Takeshi AOKI; Munehiro KOZUMA; Yoshiyuki KUROKAWA |
| A decoder with reduced power consumption is provided. The decoder includes a first circuit and a second circuit for holding data. The second circuit includes a first transistor, a second transistor, and a third transistor. The first transistor and the second transistor include an oxide semiconductor in a channel formation region. The third transistor includes silicon in a channel formation region. A gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and a gate of the third transistor is electrically connected to one of a source and a drain of the second transistor. The decoder is configured to provide or stop power supply to the semiconductor device depending on a packet ID of a header portion of the data and to perform data storing or restoring of data between the first circuit and the second circuit. | ||||||
| 4 | Symbol decoder, threshold estimation and correlation systems and methods | US13705907 | 2012-12-05 | US08842026B2 | 2014-09-23 | David Levy |
| A threshold estimate system includes a level quantizer, a correlation mechanism, and a threshold adaptation component. The level quantizer is configured to receive an input signal and to generate a quantization signal from the input signal according to one or more threshold levels. The correlation mechanism is configured to correlate the quantization signal with reference symbols to generate an output signal. The threshold adaptation component is configured to modify the one or more threshold levels according to the output signal and the input signal. | ||||||
| 5 | デコーダ、受信装置および電子機器 | JP2017196670 | 2017-10-10 | JP2018064276A | 2018-04-19 | 青木 健; 上妻 宗広; 黒川 義元 |
| 【課題】デコーダの消費電力を低減すること。 【解決手段】データを保持するための第1の回路および第2の回路を有する。第2の回路は、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、を有する。第1のトランジスタおよび第2のトランジスタは、チャネル形成領域に酸化物半導体を有する。第3のトランジスタは、チャネル形成領域にシリコンを有する。第2のトランジスタのゲートは、第1のトランジスタのソースまたはドレインの一方と電気的に接続され、第3のトランジスタのゲートは、第2のトランジスタのソースまたはドレインの一方と電気的に接続される。デコーダは、データのヘッダ部のパケットIDに応じて半導体装置への電源の供給または遮断を切り替えるとともに、データの退避または復帰を第1の回路と第2の回路との間に行う機能を有する。 【選択図】図4 |
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| 6 | 디코더, 수신 장치, 및 전자 기기 | KR20170131746 | 2017-10-11 | KR20180041069A | 2018-04-23 | AOKI TAKESHI; KOZUMA MUNEHIRO; KUROKAWA YOSHIYUKI |
| 본발명은디코더의소비전력을저감하는것을과제로한다. 데이터를유지하기위한제 1 회로및 제 2 회로를갖는다. 제 2 회로는제 1 트랜지스터, 제 2 트랜지스터, 및제 3 트랜지스터를갖는다. 제 1 트랜지스터및 제 2 트랜지스터는채널형성영역에산화물반도체를갖는다. 제 3 트랜지스터는채널형성영역에실리콘을갖는다. 제 2 트랜지스터의게이트는제 1 트랜지스터의소스및 드레인중 한쪽에전기적으로접속되고, 제 3 트랜지스터의게이트는제 2 트랜지스터의소스및 드레인중 한쪽에전기적으로접속된다. 디코더는데이터의헤더부의패킷 ID에따라반도체장치로의전원공급또는차단을전환함과함께데이터의저장또는복귀를제 1 회로와제 2 회로사이에서수행하는기능을갖는다. | ||||||
| 7 | 센싱 데이터 처리 장치 및 방법 | KR1020160033866 | 2016-03-22 | KR1020170110194A | 2017-10-11 | 김수철; 원영종 |
| 본발명은외부로부터입력된아날로그센싱데이터를증폭시키는증폭회로부, 상기증폭회로부에서증폭된아날로그센싱데이터를디지털센싱데이터로변환시키는아날로그-디지털변환부, 상기디지털센싱데이터를단말기의사운드입력포트로전송가능한사운드파형의데이터파로변조시키는신호변조부를포함하는 MCU; 및상기사운드입력포트에상응하는사운드출력단자를포함하여상기데이터파를상기사운드출력단자를통해상기사운드입력포트로출력하는출력부; 를포함하고, 상기사운드입력포트에입력된데이터파가상기아날로그센싱데이터와대응되는정보값으로변환되어상기단말기에표시되는것을특징으로하는센싱데이터처리장치및 방법에관한것이다. 본발명에따르면, 센싱데이터처리장치가데이터분석부와표시부등을구비한단말기와사운드입력포트를이용해통신하므로센싱데이터처리장치에별도의제어부나저장부, 통신부, 디스플레이등이필요치않아구성이간단해져소형화및 경량화가가능한센싱데이터처리장치및 방법을제공할수 있다. | ||||||
| 8 | 압축된 이미지의 압축률 확인 방법 및 장치 | KR1020080040876 | 2008-04-30 | KR1020090114971A | 2009-11-04 | 김원섭 |
| PURPOSE: A compression rate verifying method and device for a compressed image is provided to verify the compression ratio of the image with the compressed image itself. CONSTITUTION: A compression rate-data size output unit(110) calculates the compression ratio-data size. The compression ratio-data size is included the data size information according to the compression ratio. A compression rate calculator(150) searches the compression ratio value having the same size as the 100% compression ratio based on the compression ratio-data size. A compression rate-data size storage unit(130) stores the calculated compression ratio-data size. | ||||||
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