| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 201 | M-dimension M-PAM trellis code system and associated trellis encoder and decoder | US10835439 | 2004-04-29 | US20050243941A1 | 2005-11-03 | Kofi Anim-Appiah; Nirmal Warke |
| An M-dimension M-PAM trellis code encoder, a method of encoding user bits and a decoder. In one embodiment, the encoder includes: (1) a convolutional encoder portion configured to encode at least two user bits into at least three coded bits and (2) a sublattice selector coupled to the convolutional encoder portion and configured to employ the at least three coded bits to select a particular sublattice of code alphabet elements and further to employ at least two additional user bits to select a particular code alphabet element in the sublattice. | ||||||
| 202 | System and method for mapping information symbols to transmission symbols | US11070879 | 2005-03-03 | US20050226342A1 | 2005-10-13 | Fady Alajaji; Glen Takahara; Norman Beaulieu |
| Systems and methods for performing mapping from information symbols to transmission symbols and corresponding de-mapping operations mapping are provided which employ one of a plurality of mappings for a given signal constellation on the basis of information determined from an analysis of the information symbols. For example, different mappings may be employed for various ranges of non-uniformity, entropy, redundancy, memory in the information symbols. | ||||||
| 203 | Coded modulation device and method | US11076630 | 2005-03-10 | US20050207507A1 | 2005-09-22 | Naoki Mitsutani |
| The present invention realizes a high coding gain employing a non-linear coding and a non-linear mapping. A converter converts one row of data that is inputted from a terminal into plural rows of data. The non-linear encoders non-linearly encode-lower level two rows of data in plural rows of converted data, and outputs them as data of level 1 and level 2 to a non-linear mapping circuit. The non-linear mapping circuit maps the data non-linearly encoded by the non-linear encoders and the uncoded data so that each codeword distance may be optimal. A modulator modulates a carrier wave with two-dimensional data that are mapped by the non-linear mapping circuit. | ||||||
| 204 | Parallel concatenated code with soft-in soft-out interactive turbo decoder | US10897201 | 2004-07-22 | US20050022090A1 | 2005-01-27 | Kelly Cameron; Hau Tran; Ba-Zhong Shen; Christopher Jones |
| A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel. | ||||||
| 205 | Parallel concatenated code with soft-in soft-out interactive turbo decoder | US10897200 | 2004-07-22 | US20050021555A1 | 2005-01-27 | Kelly Cameron; Hau Tran; Ba-Zhong Shen; Christopher Jones |
| A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo−N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo−N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel. | ||||||
| 206 | Parallel concatenated code with soft-in soft-out interactive turbo decoder | US10843606 | 2004-05-11 | US20050015705A1 | 2005-01-20 | Kelly Cameron; Ba-Zhong Shen; Hau Tran; Christopher Jones; Thomas Hughes |
| A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel. | ||||||
| 207 | Variable modulation with LDPC (low density parity check) coding | US10669066 | 2003-09-23 | US20040255221A1 | 2004-12-16 | Ba-Zhong Shen; Hau Thien Tran; Kelly Brian Cameron |
| Variable modulation within combined LDPC (Low Density Parity Check) coding and modulation coding systems. A novel approach is presented for variable modulation encoding of LDPC coded symbols. In addition, LDPC encoding, that generates an LDPC variable code rate signal, may also be performed as well. The encoding can generate an LDPC variable code rate and/or modulation signal whose code rate and/or modulation may vary as frequently as on a symbol by symbol basis. Some embodiments employ a common constellation shape for all of the symbols of the signal sequence, yet individual symbols may be mapped according different mappings of the commonly shaped constellation; such an embodiment may be viewed as generating a LDPC variable mapped signal. In general, any one or more of the code rate, constellation shape, or mapping of the individual symbols of a signal sequence may vary as frequently as on a symbol by symbol basis. | ||||||
| 208 | Satellite communication system utilizing low density parity check codes | US10353224 | 2003-01-28 | US06829308B2 | 2004-12-07 | Mustafa Eroz; Feng-Wen Sun; Lin-Nan Lee; Dan Fraley |
| An approach for reliably communicating over a satellite in support of a communication service including, for example, as direct broadcast satellite and data service, is disclosed. An input message is encoded, yielding a structured Low Density Parity Check (LDPC) coded message. The coded message is modulated according to a high order modulation scheme that has a signal constellation representing more than two symbols per signaling point—e.g., 8-PSK (Phase Shift Keying) and 16-QAM (Quadrature Amplitude Modulation). The system includes a transmitter configured to propagate the modulated signal over the satellite. The above approach is particularly applicable to bandwidth constrained communication systems requiring high data rates. | ||||||
| 209 | Parallel concatenated code with soft-in soft-out interactive turbo decoder | US10843655 | 2004-05-11 | US20040210812A1 | 2004-10-21 | Kelly B. Cameron; Ba-Zhong Shen; Hau Thien Tran; Christopher R. Jones; Thomas Ashford Hughes JR. |
| A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Soloman encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo-N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo-N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel. | ||||||
| 210 | Parallel punctured convolutional encoder | US09605470 | 2000-06-28 | US06598203B1 | 2003-07-22 | Benjamin Tang |
| A parallel punctured convolutional encoder (44) that provides convolutional coding of a stream of digital data bits in a parallel manner for high frequency transmission. The parallel convolutional encoder (44) includes a plurality of one-bit delay devices (46-56) and four XOR gates (78-84). Three consecutive bits are applied to the convolutional encoder (44) in a parallel manner and four polynomial expressions are provided from the XOR gates 78-84 in a parallel manner at each clock cycle, where certain values in the polynomial expressions are provided and certain values are not provided to conform with a particular puncture scheme of a desirable convolutional rate. In an altnerate embodiment, a concatenated Reed-Solomon TCM QAM encoder is provided that operates on parallel lines of digital data for high frequency communications systems. | ||||||
| 211 | Coding scheme for cable modems | US09345054 | 1999-06-30 | US06549584B1 | 2003-04-15 | Alan Gatherer; Murtaza Ali |
| A modem (12) including a least-significant bit convolutional coding scheme is disclosed. In the transmit side of the modem (12), an encoder (28) is included, within which convolutional coders (35I, 35Q) are used to each encode one bit of each symbol applied to a phase and amplitude modulation constellation, preferably the least significant bits, such that the encoded bits select one of a plurality of sub-constellations in the modulated signal. Each of the coders (35, 35′) are arranged as finite state machines, of either thirty-two or sixty-four states. The minimum Hamming distance (dfree) provided by the codes is four, such that the resulting coding gain of the modem is improved over conventional encoding schemes. | ||||||
| 212 | Method and apparatus for forward error correction coding for an AM in-band on-channel digital audio broadcasting system | US09438822 | 1999-11-11 | US06523147B1 | 2003-02-18 | Brian William Kroeger; Branimir Vojcic; Raymond L. Pickholtz; Ashruf El-Dinary |
| A method for digital audio broadcasting comprises the steps of providing a plurality of bits of digital information to be transmitted, interleaving the bits of digital information into a plurality of partitions, forward error correcting the bits of digital information using a combination of pragmatic trellis code modulation and complementary punctured code, and transmitting the bits of digital information. The partitions include a main partition, a backup partition, an upper partition, and a lower partition, wherein the upper partition and lower partition are non-overlapping. The main partition overlaps both of the upper and lower partitions and the backup partition overlaps both of the upper and lower partitions. The interleaved bits comprise a core interleaver and an enhancement interleaver. The forward error correcting is accomplished by representing the bits as independently coded in-phase and quadrature signals, applying a first error correcting code to the in-phase signals, and applying a second error correcting code to the quadrature signals. Receivers for processing the broadcast signals are also provided. | ||||||
| 213 | Multilevel coding with time diversity | US09230650 | 1999-01-28 | US06516037B1 | 2003-02-04 | Lee-Fang Wei |
| A multilevel coded modulation scheme is provided in which a first portion of input data is encoded by a first-level code and a second portion of input data is encoded by an second-level code, the second-level code being such that the overall multilevel code exhibits a desired level of time diversity of at least 2 and the minimum distance of the overall code is not increased by virtue of the presence of the second-level code. | ||||||
| 214 | Method of coding/decoding a digital data stream coded with bitwise interleaving in multiple transmission and reception in the presence of intersymbol interference and corresponding system | US10119097 | 2002-04-09 | US20020186800A1 | 2002-12-12 | Antoine Berthet; Raphael Visoz |
| A method of and a system for coding/decoding a digital data stream coded with bitwise interleaving in multiple transmission and reception. The coding consists in subjecting (A) an initial digital data stream to an outer coding (C0), subjecting (B) the coded digital stream to an interleaving (null), subjecting (C) the interleaved coded digital stream to a layer demultiplexing on null pathways, converting (D) by modulation qm successive bits of each layer into Qm-ary symbol then transmitting (E) each symbol by means of a transmission antenna of an array of antennas nulltamnullmnull1mnullnull. The decoding consists in receiving (F) the digital data stream transmitted nullTEILC0DSmnullmnull1mnullnull on null reception antennas nullrarnullrnull1rnullnull forming an array, subjecting (G) the set of symbols received to an iterative process of equalization and joint multilayer detection, on the basis of an a priori information item (EIDSnullapi), subjecting (H) the first extrinsic information stream (EIDS1) obtained to a deinterleaving (nullnull1), subjecting (I) the second extrinsic information stream obtained (EIDS2) to an outer decoding (C0), subjecting (J) the third extrinsic information stream obtained (EIDS3) to an interleaving (null) so as to generate the a priori information item (EIDSnullapi) and reinjecting (K) the latter into the process (G). Application to radio interfaces. | ||||||
| 215 | Method and apparatus for parallel decoding of turbo encoded data | US09952311 | 2001-09-12 | US20020071505A1 | 2002-06-13 | Kelly B. Cameron; Hau Thien Tran; Ba-Zhong Shen; Christopher R. Jones |
| A method and apparatus for parallel decoding of turbo encoded data. The method includes multiple Soft In Soft Out (SISO) modules arranged in parallel such that each module supplies an input to one SISO and takes an input from another SISO data encoded for multiple parallel SISOs is received by a receiver and decoded in the abovementioned parallel configuration. | ||||||
| 216 | Decoding system and method for digital communications | US09816810 | 2001-03-23 | US20020051498A1 | 2002-05-02 | John S. Thomas; Paul J. Husted |
| A Viterbi decoding system interprets bits in received QAM constellations as many-valued parameters rather than binary valued parameters. It performs the Viterbi algorithm using these many-valued parameters to provide results superior to hard decision decoding. Rather than applying a hard 0-1 function to the QAM data, the system uses a non-stepped linear or curved transfer function to assign values to the bits. In another aspect, a system differentiates between data bits based on their estimated reliability, giving more emphasis to decoding reliable bits than unreliable bits using any of a variety of techniques. By differentiating between god and bad bits and de-emphasizing or ignoring unreliable bits, the system can provide a significant reduction in uncorrectable errors and packet loss. | ||||||
| 217 | Method of normalization of forward metric (alpha) and reverse metic (beta) in a map decoder | US09952212 | 2001-09-12 | US20020048331A1 | 2002-04-25 | Hau Thien Tran; Kelly B. Cameron; Ba-Zhong Shen; Christopher R. Jones |
| A method of normalization of forward metric (alpha) and reverse metric (beta) in a MAP decoder. In a map decoder log values of probabilities may be continually added. This continual addition can overflow limited size registers set aside to hold the alpha or beta values. This overflow may be overcome by subtracting a constant value from all of the alpha or beta values when they have reached a certain value, a process called normalization. Subtracting a constant value however may slow down the computation. Instead of adversely affecting the computation speed however the detection of a constant value may occur on one decoding cycle and the normalization may occur on the succeeding decoding cycle. Additionally instead of using a traditional subtraction circuit a multiplexor type circuit can be used to direct either zeros, in the normalization case, or a most significant bit(s), in the case where the computation were proceeding without normalization, into the register holding the alpha or beta values. Additionally to minimize the impact on the computation by the normalization process, the multiplexor circuit can be set by the previous decoder cycle so that the computation does not have to wait for the multiplexor to be set to normalization or normal computation. | ||||||
| 218 | Differential codec for pragmatic PSK TCM schemes | US09185210 | 1998-11-03 | US06304614B1 | 2001-10-16 | Ayyoob D. Abbaszadeh; Dale D. Fonnesbeck |
| A system including coding and decoding circuits provides for resolution of the phase ambiguities in pragmatic trellis-coded PSK modulation transmissions. An error correcting coder, such as a convolutional encoder, precedes the modulator for reducing the effect of noise in inducing phase errors. A corresponding decoder appears at the reception end of the communication system. A differential encoder and decoder automatically remove the possible phase ambiguities, and operate in conjunction with the error correcting encoder and decoder. Each of the ambiguity-removal differential encoder and the decoder act as an operator upon its input signal. In order that both the error correcting encoder and the ambiguity encoder immediately precede the modulator, the ambiguity removal circuitry is placed between the error correcting encoder, and is constructed as a combination of differential encoder and inverse differential encoder. The use for ambiguity removal of both the differential encoder and the inverse differential encoder operates to remove the phase ambiguity while making the ambiguity operation transparent to the output of the error correction encoder. This retains the benefit of placing the error correcting encoder immediately before the modulator. | ||||||
| 219 | Coded modulation for digital storage in analog memory devices | US08898441 | 1997-07-22 | US06212654B1 | 2001-04-03 | Hui-Ling Lou; Carl-Erik Wilhelm Sundberg |
| Digital data is stored in an analog memory device using coded modulation techniques. The memory device includes a number of memory cells, each capable of storing one of a number of different levels. A given set of b information bits to be stored in the memory device is first coded in a convolutional or block coder to generate a set of coded bits which includes more than b bits. The set of coded bits is then mapped to one or more corresponding levels, and the one or more levels are each stored in a separate cell of the memory device. In a one-dimensional embodiment, the coding may involve applying a rate 1/2 convolutional code to i least significant bits, i=1, 2, . . . , and mapping the resulting b+i coded bits to one of 2b+i distinct levels in a one-dimensional AM signal set. In embodiments of the invention which utilize multidimensional signal sets, a given set of bits is mapped to a signal in an m-dimensional signal set, with or without coding of the bits, and each of the m dimensions of the selected signal is then stored as a level in a separate cell of the analog memory device. The invention increases the storage capacity of the memory device for a given readout error probability, or alternatively improves the error probability for a given storage capacity. Readout performance may be further improved by using a multiple read-and-sum unit to generate a readout value for a given stored level based on a sum or average of several different readouts of the stored level. | ||||||
| 220 | Encoding/decoding system using 16-QAM modulation encoded in multi-level blocks | US08768399 | 1996-12-18 | US06195396B1 | 2001-02-27 | Juing Fang; Pierre Roux; Jean-François Houplain |
| The invention provides a block-encoded modulation scheme using multi-level partitioning techniques. This scheme is made transparent to phase ambiguities of ±&pgr;/2 and of &pgr;, by means of differential encoding and appropriate mapping, it is applicable to 16-QAM modulation, and it has theoretical encoding gain that is optimal for the rate of the code. The decoder associated with this scheme uses the Wagner algorithm which is much less complicated to implement than the Viterbi algorithm or than the Reed-Solomon algorithm. | ||||||
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