| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 181 | Current matrix type digital-to-analog converter incorporating an operational amplifier | EP96106211.4 | 1996-04-19 | EP0739098B1 | 2002-07-31 | Hattori, Shigeo, NEC IC Microcomputer System, Ltd. |
| 182 | Current matrix type digital-to-analog converter incorporating operational amplifier | EP01108084.3 | 1996-04-19 | EP1133061A1 | 2001-09-12 | Hattori, Shigeo, NEC IC Microcomputer Systems, Ltd |
In a digital-to-analog converter including a plurality of constant current sources (21), a plurality of first current switch elements (22) connected between the constant sources and a first output terminal (OUT1), and a plurality of second current switch elements (23) connected between the constant current sources and a second output terminal (OUT2), a reference voltage (VREF) of the constant current sources is generated by an operational amplifier (7). The operational amplifier is disabled in response to a current control signal (PD) to turn OFF all the constant current sources. |
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| 183 | Current addition type D/A converter | EP00124167.8 | 2000-11-07 | EP1130781A2 | 2001-09-05 | Kanamori, Koji |
The current addition type D/A converter of the present invention is equipped with a control circuit to reduce power consumption. A control signal is input from a control terminal (17), the resistance value of a resistor (10) that determines a reference current of a current mirror is multiplied n-fold and thereby the operating current of current cell matrix (1) is reduced to (1/n). On the other hand, the resistance value of a current/voltage conversion resistor (16) is multiplied n-fold so as to compensate the reduction of the operating current and maintain a predetermined D/A conversion rate. Normally, there is no input near an upper limit of the input dynamic range, and therefore there is no inconvenience regarding the conversion rate of the D/A converter even if the operating current is reduced. |
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| 184 | Power saving a/d converter | EP97113793.0 | 1997-08-08 | EP0824291A3 | 2001-08-08 | Suzuki, Kenichi |
An A/D conversion system comprises an A/D converter, a mode selection section (10) for periodically selecting a conversion mode and a standby mode, and a control section (12A) for controlling the A/D converter (12) based on the respective modes. The control section (12A) breaks the current path for the A/D converter during a standby mode. The duration of the standby mode can be specified from outside the system for power saving. |
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| 185 | DIFFERENTIATING BETWEEN INPUT RANGES IN A PASSIVE KEYPAD | EP99924471.8 | 1999-05-21 | EP1086532A1 | 2001-03-28 | KERR, Richard, J.; CLAXTON, Daniel, D. |
| A method and circuit for processing switch closures in a passive network (100) having switches (S1 ... Sn). The passive network (100) generates an output voltage in response to a switch closure. The circuit comprises a comparison circuit (206), coupled to the passive network, for comparing the output voltage to a reference voltage. A decoder (212), coupled to the comparison circuit, decodes the switch closure if the output voltage is within a predetermined range, and does not decode said switch closure if the output voltage is not within the predetermined range. The circuit differentiates between input ranges in a passive network keypad which allows the proper processing of meaningful key presses, while ignoring inadvertent or superfluous key presses, thereby conserving power and processor time. | ||||||
| 186 | Integrierter Schaltkreis mit einem A/D- oder D/A-Wandler mit galvanischer Trennung | EP00109446.5 | 2000-05-03 | EP1052780A2 | 2000-11-15 | Munz, Dieter, Dipl.-Ing. (FH); Günther, Harald, Dipl.-Ing.; Staudt, Michael, Dipl.-Ing. (FH); Thamm, Peter, Dr. |
Die Erfindung betrifft einen integrierten Schaltkreis, welcher einen Analog/Digital-Umsetzer oder einen Digital/Analog-Umsetzer sowie einen mit diesem verbundenen analogen und einen digitalen Signalpfad enthält. Im digitalen Signalpfad des integrierten Schaltkreises ist weiterhin eine Vorrichtung zur Potentialtrennung vorgesehen. |
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| 187 | POWER SAVING FLASH A/D CONVERTER | EP98952327.9 | 1998-10-15 | EP0974198A1 | 2000-01-26 | COOPER, Russell, E. |
| Flash analog-to-digital (A/D) conversion is performed with an n-bit converter using a resistive-divider string in which tap points are taken between each pair of adjacent resistors of the string as one input to each of a respective plurality of 2n-1 comparators. Each of the comparators has a second input in common with all of the other comparators at which an analog input voltage to be converted to digital form is applied. A transition point occurs at one of the tap points at which immediately adjacent ones of the comparators exhibit outputs of different binary states for a given sample of the analog input voltage, signifying the transition point is occurring at the highest-order digital output at which the sampled analog input voltage exceeds a reference voltage. The transition point is detected during each sample, at a location within a group of consecutive ones of the comparators of preselected number considerably less than the total number of comparators in the converter. All of the comparators in the converter except those in the group containing the transition point are deactivated to conserve power during the conversion process for the given sample. | ||||||
| 188 | Drehgeber mit Absolutwert-Positionserfassung | EP92115147.8 | 1992-09-04 | EP0550794B1 | 1997-05-07 | Fleig, Manfred; Heddergott, Harry |
| 189 | Current matrix type digital-to-analog converter incorporating an operational amplifier | EP96106211.4 | 1996-04-19 | EP0739098A2 | 1996-10-23 | Hattori, Shigeo, NEC IC Microcomputer System, Ltd. |
In a digital-to-analog converter including a plurality of constant current sources (21), a plurality of first current switch elements (22) connected between the constant sources and a first output terminal (OUT1), and a plurality of second current switch elements (23) connected between the constant current sources and a second output terminal (OUT2), a reference voltage (VREF) of the constant current sources is generated by an operational amplifier (7). The operational amplifier is disabled in response to a current control signal (PD) to turn OFF all the constant current sources. |
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| 190 | Switchable DAC with current surge protection | EP90308565.2 | 1990-08-03 | EP0417902A1 | 1991-03-20 | Fung, Jimmy; An, Jiu; Campbell David L.; Shyu Steven |
In a CMOS DAC having a plurality of stages a control circuit for selectively switching said DAC between a sleep mode and a normal operating mode with little, if any, surge current resulting therefrom. In the control circuit there is provided control transistors responsive to control signals for applying a reverse biasing potential to a reference voltage transistor and a digital input transistor in each of the stages at a rate such that the rate of change of current in the reference voltage transistor is less than a predetermined magnitude, e.g. less than 5 ma/nsec. when said DAC is switched to its sleep mode and transistor means responsive to control signals for first applying a predetermined forward biasing potential to a bias transistor and thereafter changing said reverse bias potential applied to said reference voltage transistor to a predetermined reference voltage and removing said reverse bias potential from said digital input transistor when said DAC is switched to its normal operating mode. |
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| 191 | SIGNAL PROCESSING DEVICE | EP13743182.1 | 2013-01-25 | EP2796835B1 | 2018-09-12 | SASAKI, Hiroyuki; YAMASHITA, Masaya |
| There is provided a signal processing device comprising a combination unit (3) configured to combine plural element signals based on plural physical quantity signals including signal components in accordance with desired physical quantities, respectively, by the number of times equal to or greater than a number of the plural physical quantity signals, and to output combined signals different from each other; a measuring unit (4) configured to sequentially receive the combined signals output from the combination unit (3); and a computing unit (5) configured to compute signal components based on the desired physical quantities from signals that are generated based on the combined signals sequentially output from the measuring unit. | ||||||
| 192 | REDUCED OVERHEAD ON DIGITAL SIGNAL PROCESSING FOR MOTOR DRIVE APPLICATIONS | EP18155143.3 | 2018-02-05 | EP3361640A1 | 2018-08-15 | RAO, Sesh Mohan; AGRAWAL, Shobhit; LAKSHMI, Priya Kakarla Naga |
In accordance with one or more embodiments, a monostable multivibrator (120) that is communicatively coupled to a host device (110) and an external analog-to-digital converter (130) is provided. The monostable multivibrator (120) receives a chip select signal from the host device (110). The monostable multivibrator (120) also generates, in response to the chip select signal, a conversion start signal to the external analog-to-digital converter (130).
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| 193 | DAC CAPACITOR ARRAY AND ANALOG-TO-DIGITAL CONVERTER, METHOD FOR REDUCING POWER CONSUMPTION OF ANALOG-TO-DIGITAL CONVERTER | EP16898149 | 2016-10-25 | EP3340472A4 | 2018-07-04 | FAN SHUO |
| Embodiments of the present disclosure relate to the technical field of integrated circuits, and in particular, relate to a DAC capacitor array, an analog-to-digital converter, and a method for reducing power consumption of an analog-to-digital converter. The DAC capacitor array includes a plurality of sub-capacitor arrays that are connected in parallel. Each sub-capacitor array includes: a capacitor group, including N capacitors connected in parallel, N being a positive integer; and a primary switch and a plurality of multiplexers; wherein one terminal of each capacitor in the capacitor group is connected to an input terminal of a comparator, and is connected to an input source via the primary switch; and the other terminals of the capacitors in the capacitor group are connected to a plurality of input sources via corresponding multiplexers respectively. The DAC capacitor array is optimized by adjusting the reference voltage to which the capacitors in the DAC capacitor array are connected, which reduces the overall capacitance of the DAC capacitor array. In this way, the size of the SAR analog-to-digital converter is reduced, the power consumption is reduced, and meanwhile the cost of chips may be lowered in manufacture of the chips. | ||||||
| 194 | DAC CAPACITOR ARRAY, SAR ANALOG-TO-DIGITAL CONVERTER AND METHOD FOR REDUCING POWER CONSUMPTION | EP17800998 | 2017-09-23 | EP3322096A4 | 2018-05-30 | FAN SHUO |
| The present invention relates to the field of integrated circuits, and relate to a DAC capacitor array, an SAR analog-to-digital converter and a method for reducing power consumption thereof. The method includes: connecting one terminal of each capacitor in a first capacitor array and a second capacitor array to a first reference voltage via a corresponding primary switch, and connecting the other terminal of each capacitor in the first capacitor array and the second capacitor array to a positive-terminal analog input signal and a negative-terminal analog input signal respectively via a corresponding multiplexer to complete sampling; determining a value of a most-significant bit by comparing an output voltage of the first capacitor array with an output voltage of the second capacitor array, maintaining or adjusting a reference voltage connected to the other terminal of each capacitor in the first capacitor array and the second capacitor array according to the value of the most-significant bit, and determining values of a second-most-significant bit and a least-significant bit by further comparing the output voltage of the first capacitor array with the output voltage of the second capacitor array. According to the embodiments of the present invention, conversion power consumption may be reduced. | ||||||
| 195 | SYSTEMS AND METHODS FOR REDUCING ARTIFACTS AND IMPROVING PERFORMANCE OF A MULTI-PATH ANALOG-TO-DIGITAL CONVERTER | EP16729230.9 | 2016-06-07 | EP3308468A1 | 2018-04-18 | SATOSKAR, Aniruddha; ALLEN, Daniel; SCHNEIDER, Edmund |
| In accordance with embodiments of the present disclosure, a processing system may include multiple selectable processing paths for processing an analog signal in order to reduce noise, increase dynamic range, and mask audio artifacts associated with a change in noise floor. Techniques are employed to transition between processing paths and calibrate operational parameters of the two paths in order to reduce or eliminate artifacts caused by switching between processing paths. | ||||||
| 196 | DUAL-STRING DIGITAL-TO-ANALOG CONVERTERS (DACS), AND RELATED CIRCUITS, SYSTEMS, AND METHODS | EP14714540.3 | 2014-03-12 | EP2974030B1 | 2018-04-18 | PRICE, Burt, L.; SHAH, Dhaval, R.; KOLLA, Yeshwant, Nagaraj |
| Dual-string digital-to-analog converters (DACs), and related circuits, systems, and methods are disclosed. In embodiments disclosed herein, a primary voltage divider of the dual string-DAC is comprised of at least one adjusting circuit. The adjusting circuit is configured to maintain the ideal voltage of a selected resistor node pair across a secondary voltage divider circuit in response to a primary switch unit selecting a selected resistor node pair. In this manner, impedance isolation is not required between a primary voltage divider and the secondary voltage divider circuit of the dual-string DAC. As a result, as non-limiting examples, the area on an integrated circuit (IC) for a dual-string DAC may be decreased, power consumption of the DAC may be decreased, and/or the dual-string DAC may have increased performance by not requiring a settling time. | ||||||
| 197 | INTEGRIERENDER A/D-WANDLER | EP13705721.2 | 2013-02-15 | EP2826147B1 | 2017-04-12 | FELDOTTE, Heinrich; HOLST, Heyko |
| 198 | COMPARATOR TRACKING CONTROL SCHEME WITH DYNAMIC WINDOW LENGTH | EP15779212.8 | 2015-04-06 | EP3132542A1 | 2017-02-22 | HE, Ku; ZHAO, Xin; FEI, Xiaofan |
| A comparator tracking scheme for an analog-to-digital converter (ADC) may implement a dynamic window size by varying, over time, a number of comparators powered up to convert an analog input signal to a digital output signal. A comparator-tracking scheme may be implemented, for example, in a controller coupled to a plurality of comparators in an ADC. For example, the controller may determine a window size for the ADC and determine a window position for the ADC. The controller may then activate comparators of the ADC within a window centered at the window position and having a width of the window size. The controller may determine a window size by analyzing an output of a filter. When the filter output indicates a rapidly changing analog input signal, the controller may dynamically increase a window size of the ADC, which may increase a number of comparators powered on. | ||||||
| 199 | Method and circuit for bandwidth mismatch estimation in an a/d converter | EP14171580.5 | 2014-06-06 | EP2953265B1 | 2016-12-14 | Deguchi, Kazuaki; Verbruggen, Bob; Craninckx, Jan |
| 200 | DYNAMIC COMPRESSION/DECOMPRESSION (CODEC) CONFIGURATION | EP13888501.7 | 2013-06-24 | EP3014774A1 | 2016-05-04 | JIN, Zhonghui; QIAO, Nan |
| The present disclosure is directed dynamic compression/decompression (codec) configuration. In general, a device may include a codec configuration module to determine a configuration for use by the codec based on configuration criteria. The configuration criteria may include, for example, data characteristic information, system condition information and user expectation information. The configuration information may be used to select a codec configuration from one or more available codec configurations. For example, a benchmark module also in the device may determine the available codec configurations. After a codec configuration has been selected, it may be set in the codec. It may also be possible for the codec configuration module to monitor for changes in device operation (e.g., changes in the configuration criteria) and to update the codec configuration based on the monitored changes. | ||||||
