| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 1 | COMMUNICATIONS DEVICE WITH RECEIVER CHAIN OF REDUCED SIZE | US15968927 | 2018-05-02 | US20180323821A1 | 2018-11-08 | Laurent CHABERT; Raphael PAULIN |
| A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna. | ||||||
| 2 | HPA Bypass Switch | US15715507 | 2017-09-26 | US20180097485A1 | 2018-04-05 | Sonny Boy C. Reyes; Jessica G. Lam; Bobby Barnes; Angelica M. Maldonado; Tuyen D. Le; Bernard A. Trumbach; Timothy J. Jasper |
| A switch includes: an HPA bypass switching component that can be in an HPA bypass state and an HPA state and an HPA switching component that can be in the HPA bypass state and the HPA state. When the HPA bypass switching component is in the HPA bypass state, the HPA switching component is in the HPA bypass state. When the HPA bypass switching component is in the HPA bypass state and the transceiver is generating a transceiver transmission signal, the transceiver transmission signal is provided to the antenna and the received transceiver transmission signal is provided to the transceiver. When the HPA bypass switching component is in the HPA state and the high power amplifier is generating an HPA transmission signal, the HPA transmission signal is provided to the antenna and the received HPA signal is provided to the transceiver. | ||||||
| 3 | Extremely High Frequency Dual-Mode Class AB Power Amplifier | US13591061 | 2012-08-21 | US20130265108A1 | 2013-10-10 | Joos Dieter; Wim Philibert; Patrick Reynaert; Dixian Zhao |
| An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design. | ||||||
| 4 | 差動増幅器及び差動増幅器を含む表示ドライバ | JP2014182026 | 2014-09-08 | JP6370647B2 | 2018-08-08 | 樋口鋼児 |
| 5 | Amplifier activation | EP09252519.5 | 2009-10-30 | EP2317644A1 | 2011-05-04 | Teng, Robert Hwat Hian |
An amplifier (100, 300) comprises a main amplification stage (40) and an auxiliary amplification stage (50). An input of the main amplification stage (40) and an input of the auxiliary amplification stage (50) are coupled to a common node (30), and an output of the main amplification stage (40) is coupled to an output node (20). During activation, before power is supplied to the main amplification stage (40), the output node (30) is coupled to a reference voltage (VREF). A quiescent voltage is then established at the common node (30) by coupling power to the auxiliary amplification stage (50). Only then is power coupled to the main amplification stage (40) and the reference voltage (VREF) de-coupled from the output node (20).
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| 6 | Drain Sharing Split LNA | US15887816 | 2018-02-02 | US20190245497A1 | 2019-08-08 | Miles Sanner; Emre Ayranci |
| A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a “common source” configured input FET and a “common gate” configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the gm of the input stage of the amplifier, thus improving the noise figure of the amplifier. | ||||||
| 7 | Low noise amplifier architecture for carrier aggregation receivers | US14839055 | 2015-08-28 | US09831838B2 | 2017-11-28 | Sherif Abdelhalem; Frank Zhang; Abdellatif Bellaouar; Sherif Embabi |
| A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier. | ||||||
| 8 | SWITCHED-CAPACITOR BUFFER AND RELATED METHODS | US15335956 | 2016-10-27 | US20170331366A1 | 2017-11-16 | Ramy Awad |
| A line receiver comprising a switched capacitor circuit and a buffer is described. The buffer may be configured to receive, through the switched capacitor circuit, an analog signal. In response, the buffer may provide an output signal to a load, such as an analog-to-digital converter. The switched capacitor circuit may be controlled by a control circuitry, and may charge at least one capacitive element to a desired reference voltage. The reference voltage may be selected so as to bias the buffer with a desired DC current, and consequently, to provide a desired degree if linearity. The line receiver may further comprise a bias circuit configured to generate the reference voltage needed to bias the buffer with the desired DC current. | ||||||
| 9 | Differential amplifier and display driver including the same | US14845264 | 2015-09-03 | US09722554B2 | 2017-08-01 | Koji Higuchi |
| When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal. | ||||||
| 10 | NOVEL LOW NOISE AMPLIFIER ARCHITECTURE FOR CARRIER AGGREGATION RECEIVERS | US14839055 | 2015-08-28 | US20160173042A1 | 2016-06-16 | Sherif Abdelhalem; Frank Zhang; Abdellatif Bellaouar; Sherif Embabi |
| A low noise amplifier includes a first input transistor coupled to an input signal and a second input transistor coupled to the input signal. The low noise amplifier also includes a first output transistor, coupled between the first input transistor and a first carrier aggregation load, configured to connect the first input transistor to the first carrier aggregation load. Additionally, the low noise amplifier includes a second output transistor, coupled between the first input transistor and a second carrier aggregation load, configured to connect the first input transistor to the second carrier aggregation load. Further, the low noise amplifier includes a third output transistor, coupled between the second input transistor and the second carrier aggregation load, configured to connect the second input transistor to the second carrier aggregation load. Also included are a method of operating a low noise amplifier and an extended carrier low noise amplifier. | ||||||
| 11 | Extremely high frequency dual-mode class AB power amplifier | US13591061 | 2012-08-21 | US08823449B2 | 2014-09-02 | Joos Dieter; Wim Philibert; Patrick Reynaert; Dixian Zhao |
| An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design. | ||||||
| 12 | SEMICONDUCTOR INTEGRATED CIRCUIT | US16020047 | 2018-06-27 | US20190028075A1 | 2019-01-24 | Sho KAMEZAWA; Tohru KANNO |
| A semiconductor integrated circuit including a differential amplifier circuit, a first output circuit, a second output circuit, a selection circuit, and a feedback circuit. The differential amplifier circuit is configured to operate at a first source voltage. The first output circuit is configured to receive an output of the differential amplifier circuit, output a first output, and operate at the first source voltage. The second output circuit is configured to receive an output of the differential amplifier circuit, output a second output, and operate at a second source voltage lower than the first source voltage. The selection circuit is configured to select one of the first output from the first output circuit and the second output from the second output circuit according to an operating phase determined by an external control signal. The feedback circuit is connected between the differential amplifier circuit and the selection circuit. The feedback circuit is configured to feed the selected output back to the differential amplifier circuit. | ||||||
| 13 | SELECTIVE HIGH AND LOW POWER AMPLIFIER SWITCH ARCHITECTURE | US15235521 | 2016-08-12 | US20180048273A1 | 2018-02-15 | Jeremy GOLDBLATT |
| Certain aspects of the present disclosure provide a switch architecture for switching between a low power amplifier and a high power amplifier. One example amplification system includes a high power amplifier and a low power amplifier. The amplification system further includes a first switch coupled between the high power amplifier and an output. The amplification system further includes a second switch coupled between the output and a reference potential. The second switch is further coupled between the low power amplifier and the output and configured to selectively couple the low power amplifier to the output. The amplification system further includes a third switch coupled between the low power amplifier and the second switch. | ||||||
| 14 | DIFFERENTIAL AMPLIFIER AND DISPLAY DRIVER INCLUDING THE SAME | US14845264 | 2015-09-03 | US20160071453A1 | 2016-03-10 | Koji HIGUCHI |
| When the offsets of the first and second differential units have polarities different from each other, the first and second differential units are both set to a normal connection state, i.e., a state in which the input voltage is supplied to the first input terminal of each of the first and second differential units and the output voltage is supplied to the second input terminal of each of the first and second differential units. When the offsets of the first and second differential units have the same polarity, on the other hand, the first differential unit is set to the above normal connection state and the second differential unit is set to a chopping connection state in which the output voltage is supplied to the first input terminal and the input voltage is supplied to the second input terminal. | ||||||
| 15 | Amplifier activation | US13504710 | 2010-10-29 | US08587374B2 | 2013-11-19 | Robert Hwat Hian Teng |
| An amplifier comprises a main amplification stage and an auxiliary amplification stage. An input of the main amplification stage and an input of the auxiliary amplification stage are coupled to a common node, and an output of the main amplification stage is coupled to an output node. During activation, before power is supplied to the main amplification stage, the output node is coupled to a reference voltage (VREF). A quiescent voltage is then established at the common node by coupling power to the auxiliary amplification stage. Only then is power coupled to the main amplification stage and the reference voltage (VREF) de-coupled from the output node. | ||||||
| 16 | Amplifier Activation | US13504710 | 2010-10-29 | US20120218043A1 | 2012-08-30 | Robert Hwat Hian Teng |
| An amplifier comprises a main amplification stage and an auxiliary amplification stage. An input of the main amplification stage and an input of the auxiliary amplification stage are coupled to a common node, and an output of the main amplification stage is coupled to an output node. During activation, before power is supplied to the main amplification stage, the output node is coupled to a reference voltage (VREF). A quiescent voltage is then established at the common node by coupling power to the auxiliary amplification stage. Only then is power coupled to the main amplification stage and the reference voltage (VREF) de-coupled from the output node. | ||||||
| 17 | 差動増幅器及び差動増幅器を含む表示ドライバ | JP2014182026 | 2014-09-08 | JP2016058809A | 2016-04-21 | 樋口鋼児 |
| 【課題】画質不良を生じさせることなくオフセット低減を図ることが可能な差動増幅器及びこの差動増幅器を含む表示ドライバを提供する。 【解決手段】単一の差動増幅器内に互いの出力端同士が接続されている第1及び第2差動部を設け、先ず、第1差動部の第1及び第2入力端に入力電圧を印加した際に得られた出力電圧を第1差動部のオフセットとして得る。次に、第2差動部の第1及び第2入力端に入力電圧を印加した際に得られた出力電圧を第2差動部のオフセットとして得る。ここで、第1及び第2差動部各々のオフセットの極性が互いに異なる場合には、第1及び第2差動部を共に通常の接続状態に設定する。一方、第1及び第2差動部各々のオフセットの極性が同一である場合には、第1差動部を上記のような通常の接続状態とすると共に、第2差動部に対しては、第1入力端に出力電圧を供給し、第2入力端に入力電圧を供給するチョッピング接続に設定する。 【選択図】図4 |
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| 18 | Amplifier activation | EP09252519.5 | 2009-10-30 | EP2317644B1 | 2015-10-28 | Teng, Robert Hwat Hian |
| 19 | EXTREMELY HIGH FREQUENCY DUAL-MODE CLASS AB POWER AMPLIFIER | EP13714313.7 | 2013-04-05 | EP2834916A1 | 2015-02-11 | DIETER, Joos; PHILIBERT, Wim; REYNAERT, Patrick; ZHAO, Dixian |
| An Extremely High Frequency (EHF) dual-mode PA with a power combiner is designed using 40-nm bulk CMOS technology. One of the unit PAs can be switched off for the low power applications. In the design, circuit level optimization and trade-off are performed to ensure the good performance in both modes. The PA achieves a PSAT of 17.4 dBm with 29.3% PAE in high power mode and a PSAT of 12.6 dBm with 19.6% PAE in low power mode. The reliability measurements are also conducted and a lifetime of 80613 hours is estimated based on a commonly used empirical model. The excellent performance (e.g., highest reported PAE) achieved in this design further confirms the scaling of CMOS technology will continue to benefit the mm-wave transceiver design. | ||||||
| 20 | SWITCHED-CAPACITOR BUFFER AND RELATED METHODS | EP17170013.1 | 2017-05-08 | EP3244531A1 | 2017-11-15 | AWAD, Ramy |
A line receiver (100) comprising a switched capacitor circuit (102) and a buffer (108) is described. The buffer (108) may be configured to receive, through the switched capacitor circuit (102), an analog signal. In response, the buffer (102) may provide an output signal to a load (110), such as an analog-to-digital converter. The switched capacitor circuit (102) may be controlled by a control circuitry (112), and may charge at least one capacitive element (106) to a desired reference voltage. The reference voltage may be selected so as to bias the buffer (108) with a desired DC current, and consequently, to provide a desired degree of linearity. The line receiver (100) may further comprise a bias circuit (300) configured to generate the reference voltage needed to bias the buffer (108) with the desired DC current.
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