| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 21 | LOW NOISE AMPLIFIER CIRCUIT | EP17150596.9 | 2017-01-08 | EP3193446A1 | 2017-07-19 | RAMAN, Johan; ROMBOUTS, Pieter |
A semiconductor circuit (200) comprising an input block having a first chopper (CH1) providing a chopped voltage signal (Vin_ch), a first transconductance (G1) converting said chopped voltage signal into a chopped current signal (I_ch), a second chopper (CH2) providing a demodulated current signal (I_demod), a current integrator (CI1) having an integrating capacitor (Cint) providing a continuous-time signal (Vct), a first feedback path comprising: a sample-and-hold block and a first feedback block (G2), the first feedback path providing a proportional feedback signal (Vfb, Ifb) upstream of the current integrator (CI1). The amplification factor is at least 2. Charge stored on the integrating capacitor (Cint) at the beginning of a sample period is linearly removed during one single sampling period (Ts). Each chopper operates at a chopping frequency (fc). The sample-and-hold-block operates at a sampling frequency (fs) equal to an integer (N) times the chopping frequency (fc).
|
||||||
| 22 | Signal processing circuit, resolver digital converter, and multipath nested mirror amplifier | EP14164157.1 | 2014-04-10 | EP2804316A3 | 2015-09-16 | FUNATO, Yoshihiro; KUMAMOTO, Toshio; YOSHIZAWA, Tomoaki; KUROOKA, Kazuaki |
A signal processing circuit includes a chopper amplifier (1) that has a differential amplifier circuit (AMP1) that amplifies differential input signals Vsp(t) and Vsm(t), and an adder circuit (1B) that generates an addition signal Vfil(t) by addition of the chopper output signal Vsub(t) that the chopper amplifier (1) generates. Differential signals inputted into the differential amplifier circuit (AMP1) are interchanged for every first phase period and second phase period, and the adder circuit (1B) generates the addition signal by addition of the chopper output signal in the first phase period and in the second phase period.
|
||||||
| 23 | SWITCHING AMPLIFIERS | EP08849951 | 2008-11-14 | EP2218175A4 | 2014-04-02 | ATTWOOD BRIAN E; TAYLOR WILSON E; HAND LARRY E |
| 24 | Integrated amplifier for driving acoustic transducers | EP10172369.0 | 2010-08-10 | EP2418768A1 | 2012-02-15 | Nicollini, Germano; Guanziroli, Federico; Orio, Massimo; Pinna, Carlo |
The invention relates to an electronic integrated amplifier (100; 200) for driving an acoustic transducer. The amplifier comprises two differential input terminals (10, 11; 20, 21) to receive an input signal (Vin) and a first (12; 22) and a second (GND; 23) output terminal to provide an output signal (Vout) to the transducer. In addition, the amplifier comprises an operational amplifier (OA; OA') having an input end (IN) including differential inputs and an output end (OUT) operatively associated with the first (12; 22) and second (GND; 23) output terminals. A pair of input resistors (R1) connect the two differential input terminals to two (14, 15; 24, 25) intermediate terminals, respectively. A pair of feedback resistors (R2) connect the first (12; 22) and second (GND; 23) output terminals to the two intermediate terminals, respectively. The integrated amplifier also comprises means (C1, C2, Csw1, Csw2) for high-pass filtering the input signal (Vin). Such filtering means is characterized in that it comprises an input element (C1, C2) interposed between said intermediate terminals and the input end (IN) of the operational amplifier (OA; OA'), and a feedback element (Csw1, Csw2) connected between the input end (IN) and the output end (OUT) of the same operational amplifier (OA; OA').
|
||||||
| 25 | Power amplifier | EP11250063.2 | 2011-01-20 | EP2372906A1 | 2011-10-05 | Clifton, John Christopher |
A power amplifier comprises a series stack of power amplifier devices, connected in parallel to the amplifier input for receiving an RF input signal, and having output terminals being connected in series to the amplifier output. An intermediate coupling capacitor is connected between each adjacent pair of power amplifier devices in the series stack of power amplifier devices for DC isolation of said power amplifier devices. This reduces the required DC supply voltage, as well as allowing shorting of individual power amplifier devices in response to variation in the DC supply voltage.
|
||||||
| 26 | 信号処理回路、およびレゾルバデジタルコンバータ | JP2013103150 | 2013-05-15 | JP6363822B2 | 2018-07-25 | 船戸 是宏; 熊本 敏夫; 吉澤 知晃; 黒岡 一晃 |
| 27 | 再構成可能な測定装置及びその制御方法並びに記録媒体 | JP2014172480 | 2014-08-27 | JP2015043981A | 2015-03-12 | KIM JONG-PAL |
| 【課題】アプリケーションにより生体電位測定及びインピーダンス測定の構成を自由に変更できる再構成可能な測定装置及びその制御方法並びに記録媒体を提供する。【解決手段】本発明による再構成可能な測定装置は、入力信号を変調する第1チョッパーと、前記第1チョッパーの出力信号を増幅する増幅器と、前記増幅器の出力信号又は内部信号を復調する第2チョッパーと、測定モードに応じて前記第1チョッパー及び前記第2チョッパーを制御する制御部とを有する。【選択図】図1 | ||||||
| 28 | 信号処理回路、レゾルバデジタルコンバータ、およびマルチパスネステッドミラー増幅回路 | JP2013103150 | 2013-05-15 | JP2014225742A | 2014-12-04 | FUNATO KOREHIRO; KUMAMOTO TOSHIO; YOSHIZAWA TOMOAKI; KUROOKA KAZUAKI |
| 【課題】チョッパアンプの出力を加算処理して、オフセット電圧を除去した信号を生成する場合、その加算処理を行う回路に起因するオフセット電圧が、さらに重畳する。【解決手段】信号処理回路(1)は、差動入力信号(Vsp(t)/Vsm(t))を増幅する差動増幅回路(AMP1)を有するチョッパアンプ(1A)と、チョッパアンプが生成するチョッパ出力信号(Vsub(t))を加算して、加算信号(Vfil(t))を生成する加算回路(1B)と、を備える。差動増幅回路に入力される差動信号は、制御クロック(CLK1)の第1位相期間および第2位相期間毎に入れ替えられ、加算回路は、第1位相期間および第2位相期間におけるチョッパ出力信号を加算して、加算信号を生成する。【選択図】図1 | ||||||
| 29 | Signal detection circuit | JP2008037389 | 2008-02-19 | JP4922204B2 | 2012-04-25 | 田 徹 武 |
| 30 | Signal detecting circuit | JP2008037389 | 2008-02-19 | JP2008236737A | 2008-10-02 | TAKEDA TORU |
| PROBLEM TO BE SOLVED: To provide a signal detecting circuit which sets a decision threshold voltage to an arbitrary value to reduce the influence of an offset component contained in output, thereby assuring a high precision detection. SOLUTION: The signal detecting circuit is provided with: an amplifier 2; a switch unit 1 which supplies signals to the amplifier 2 such that the polarity thereof is reversed between first and second periods; a capacitor 3 connected with a terminal 2a; a capacitor 4 connected with a terminal 2b; a switch S1 connected to the capacitor 4; a comparator 5 connected with the capacitor 3 and the switch S1; a switch S3 connected between an output terminal 5c and an inverting input terminal 5b; a switch S2 connected with a terminal 4b; a switch S4 connected to a non-inverting input terminal 5a; and a threshold voltage source Vref connected between the switch S2 and the switch S4. In the first period, the switch S1 is off, and the switches S2-S4 are on. In the second period, the switch S1 is on, and the switches S2-S4 are off. COPYRIGHT: (C)2009,JPO&INPIT | ||||||
| 31 | GALVANICALLY ISOLATED AMPLIFIERS AND RELATED METHODS | US15811771 | 2017-11-14 | US20180323759A1 | 2018-11-08 | Christian COJOCARU; Igor MILETIC; Tudor LIPAN; Michael SAWIRES |
| A Galvanically Isolated Amplifier (GIA) includes an isolation barrier to galvanically isolate high voltage circuitry from low voltage circuitry. The high voltage circuitry has at least two voltage supply rails, with the voltage supply rail closest to ground potential at a first potential relative to the ground potential. The low voltage circuitry has at least two voltage supply rails, with the voltage supply rail closest to the ground potential at a second potential, the second potential being smaller than the first potential. A Radio Frequency (RF) carrier is digitally Phase Shift Keying (PSK) modulated for transmission across the isolation barrier. The unmodulated RF carrier could also be transmitted across the isolation barrier. PSK modulation could be applied to the RF carrier based on a test waveform to generate a PSK-modulated test signal for transmission while a voltage transient is applied between the high voltage circuitry and the low voltage circuitry. | ||||||
| 32 | Fast settling capacitive gain amplifier circuit | US15600484 | 2017-05-19 | US10044327B2 | 2018-08-07 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
| 33 | RIPPLE REDUCTION METHOD FOR CHOPPER AMPLIFIERS | US15430139 | 2017-02-10 | US20180091103A1 | 2018-03-29 | Matei Nicolae STAN; Pavel-Viorel BRINZOI |
| An electrical circuit comprising a modulating chopper configured to receive a differential input signal at a first frequency and modulate the differential input signal to a second frequency to form a modulated differential signal, a null amplifier coupled to the modulating chopper and configured to amplify the modulated differential signal to form an amplifier output, wherein amplifying the modulated differential signal causes a ripple in the amplifier output, a demodulating chopper coupled to the null amplifier and configured to demodulate the amplifier output to form a demodulated differential signal having a first portion at the first frequency and a second portion at a third frequency, an integrator coupled to the demodulating chopper and configured to integrate the demodulated differential signal to form an integrated differential signal, and an attenuator coupled to the integrator and configured to attenuate the integrated differential signal to compensate for at least part of the ripple. | ||||||
| 34 | FAST SETTLING CAPACITIVE GAIN AMPLIFIER CIRCUIT | US15600484 | 2017-05-19 | US20180076779A1 | 2018-03-15 | Hanqing Wang; Gerard Mora-Puchalt |
| A capacitive gain amplifier circuit includes two sets of Miller capacitors and two output stage differential amplifier circuits. A first set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a first phase that resets the first output stage differential amplifier circuit. The second set of Miller capacitors is used to compensate the first output stage differential amplifier circuit during a second phase that chops a signal being amplified. The second set of Miller capacitors is swapped from one polarity to an opposite polarity of the first output stage differential amplifier circuit during successive second phases. The second output stage differential amplifier circuit includes a set of inputs selectively coupled with the inputs of the first output stage differential amplifier circuit and a set of outputs selectively coupled with the outputs of the first output stage differential amplifier circuit during the second phase. | ||||||
| 35 | Detecting device and electronic apparatus | US14843171 | 2015-09-02 | US09804032B2 | 2017-10-31 | Gakuji Yamamoto |
| A detecting device includes a pyroelectric element that generates charge by a pyroelectric effect in a first detection terminal and a second detection terminal, a chopper amplifier circuit that generates an amplified signal in response to the charge generated in the first detection terminal and the second detection terminal by chopping, and an initialization switch that controls electrical connection between the second detection terminal and a power source for generating an initialized voltage, and the initialization switch is turned on before a start of an amplification operation by the amplifier circuit and is off during the amplification operation. | ||||||
| 36 | LOW NOISE AMPLIFIER CIRCUIT | US15402502 | 2017-01-10 | US20170207761A1 | 2017-07-20 | Johan RAMAN; Pieter ROMBOUTS |
| A semiconductor circuit comprising an input block having a first chopper providing a chopped voltage signal, a first transconductance converting said chopped voltage signal into a chopped current signal, a second chopper providing a demodulated current signal, a current integrator having an integrating capacitor providing a continuous-time signal, a first feedback path comprising: a sample-and-hold block and a first feedback block, the first feedback path providing a proportional feedback signal upstream of the current integrator. The amplification factor is at least 2. Charge stored on the integrating capacitor at the beginning of a sample period is linearly removed during one single sampling period. Each chopper operates at a chopping frequency. The sample-and-hold-block operates at a sampling frequency equal to an integer times the chopping frequency. | ||||||
| 37 | Hot-swap current-sensing system | US14965588 | 2015-12-10 | US09641142B2 | 2017-05-02 | Sudheer Prasad |
| One example includes a hot-swap control system. The system includes a sense resistor network provides a sense voltage in response to an output current. The system also includes a sense control circuit includes a chopper amplifier system arranged in a servo feedback arrangement to generate a monitoring voltage having an amplitude that is associated with the output current based on the sense voltage. A notch filter chopping stage filters out signal ripple in the chopper amplifier system across a unity-gain bandwidth of the chopper amplifier system, and a capacitive compensation network provides stability-compensation of the chopper amplifier system across the unity-gain bandwidth. A transconductance amplifier configured to compare the monitoring voltage with a predetermined reference voltage to generate a control voltage. The system further includes a power transistor configured to conduct the output current to an output based on the control voltage. | ||||||
| 38 | SWITCHED-CAPCITOR BANDGAP REFERENCE CIRCUIT USING CHOPPING TECHNIQUE | US15335367 | 2016-10-26 | US20170115684A1 | 2017-04-27 | Weiwei XU; Prasanna UPADHYAYA; Norman LIU; Xiaoyue WANG |
| A method includes providing a first voltage to a first output node during a first time interval, providing a second voltage to the first output node during a second time interval, and averaging the first and second voltages to provide a reference voltage to a second output node. The first voltage includes a proportional-to-absolute-temperature (PTAT) component, a complementary-to-absolute-temperature (CTAT) component, and a first residual offset component. The second voltage includes the PTAT component, the CTAT component, and a second residual offset component. An apparatus includes a discrete-time circuit to provide the first voltage to the first output node during the first time interval and to provide the second voltage to the first output node during the second time interval, and a filter to average the first and second voltages to provide the reference voltage to the second output node. | ||||||
| 39 | Instrumentation amplifier | US14709057 | 2015-05-11 | US09634626B2 | 2017-04-25 | Shupeng Zhong |
| An instrumentation amplifier includes: a capacitive feedback closed-loop amplifier, an input capacitor charging module, a feedback capacitor discharging module, a noise separation module and a logic controller. The capacitive feedback closed-loop amplifier includes a fully differential operational amplifier, a first input capacitor, a second input capacitor, a first feedback capacitor and a second feedback capacitor. The input capacitor charging module is configured to charge the first input capacitor and the second input capacitor periodically. The feedback capacitor discharging module is configured to discharge the first feedback capacitor and the second feedback capacitor periodically. The noise separation module is configured to separate a noise from a signal using a chopping modulation technology. The logic controller is connected to the input capacitor charging module, the feedback capacitor discharging module and the noise separation module to control the modules to operate. | ||||||
| 40 | Chopper-stabilized instrumentation amplifier for impedance measurement | US12872552 | 2010-08-31 | US09615744B2 | 2017-04-11 | Timothy J. Denison; Wesley A. Santa |
| In general, this disclosure is directed to a mixer amplifier that can be utilized within a chopper stabilized instrumentation amplifier. The chopper stabilized instrumentation amplifier may be used for physiological signal sensing, impedance sensing, telemetry or other test and measurement applications. In some examples, the mixer amplifier may include a current source configured to generate a modulated current at a modulation frequency for application to a load to produce an input signal, an amplifier configured to amplify the input signal to produce an amplified signal, and a demodulator configured to demodulate the amplified signal at the modulation frequency to produce an output signal indicating an impedance of the load. | ||||||
