| 序号 | 专利名 | 申请号 | 申请日 | 公开（公告）号 | 公开（公告）日 | 发明人 |
|---|---|---|---|---|---|---|
| 121 | Frequency detection circuit and data processing apparatus | US10744788 | 2003-12-22 | US07134042B2 | 2006-11-07 | Shinya Shimasaki |
| A frequency detection circuit according to the present invention has a status holding register for storing rise information and fall information about a check target clock and outputting an error detection signal showing frequency abnormality when information showing the next edge (a fall or a rise) from a rise or a fall of the check target clock is not stored, a rise/fall detection circuit for respectively detecting a rise and a fall of the check target clock and outputting a rise detection signal in response to the rise and a fall detection signal in response to the fall, a sampling clock generation circuit for generating sampling clock for storing the information about the check target clock, and an edge detection signal generation circuit for outputting an edge detection signal which is an edge detection result of the check target clock based on the rise detection signal and the fall detection signal. | ||||||
| 122 | Circuit and method for monitoring the status of a clock signal | US11097527 | 2005-03-31 | US20060224910A1 | 2006-10-05 | Gabriel Li; Greg Richmond; Sangeeta Raman |
| A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register. | ||||||
| 123 | Phase-frequency detector with gated reference clock input | US10881879 | 2004-06-30 | US07084670B1 | 2006-08-01 | Hon Kin Chiu |
| A gated phase-frequency detector circuit includes a phase-frequency detector and a multiplexer circuit. The phase-frequency detector is arranged to provide UP and DOWN signals responsive to a reference clock signal and a feedback signal. Further, the phase-frequency detector includes a first flip-flop that provides the UP signal, a second flip-flop that provides the DOWN signal, and a clear logic circuit. One input of the multiplexer circuit is coupled to the output of the first flip-flop, another input of the multiplexer circuit is arranged to receive a logic high signal, and an output of the multiplexer circuit is coupled to the D input of the first flip-flop. The multiplexer circuit is arranged to multiplex the logic high signal and the UP signal responsive to a reference gate signal. If the reference gate signal corresponds to an active level, logic level of the UP signal does not change. | ||||||
| 124 | Systems and methods for clock mode determination utilizing explicit formulae and lookup tables | US11136059 | 2005-05-24 | US07057539B1 | 2006-06-06 | Bruce Eliot Duewer; John Laurence Melanson |
| A system for determining a data converter operating mode includes measurement circuitry operable to measure a master clock frequency of a master clock signal and measure a frequency ratio between a data clock frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing an explicit formula. In a further embodiment, the mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter utilizing a lookup table. In an additional embodiment, the mapping system tests an available set of operating modes, independent of any previous tests, to determine a suitable operating mode for the data converter. | ||||||
| 125 | Frequency lock detector | US11204957 | 2005-08-16 | US20060087352A1 | 2006-04-27 | Sang-Jin Byun; Hyun-Kyu Yu |
| Provided is a frequency lock detector which includes one counter and a clock number difference detector for detecting a clock number difference while not increasing complexity according to the counting number N to compare the frequencies of two clock signals whose phases are not synchronous to each other and determine whether the difference between the frequencies of the two signals is within a desired frequency accuracy. The frequency lock detector includes: a counter for counting the number of clocks of a reference clock signal inputted from outside; a clock number difference detector for detecting a difference between the clock number of the reference clock signal and the clock number of a recovered clock signal whose phase is not synchronous to the phase of the reference clock signal; and a lock determiner for determining a frequency lock based on result values of the counter and the clock number difference detector. | ||||||
| 126 | Signal detect circuit for high speed data receivers | US10609802 | 2003-06-30 | US06879187B2 | 2005-04-12 | Robert X. Jin; Kathy L. Peng; Stephen F. Dreyer |
| In accordance with one embodiment of the present invention, a signal detect circuit may analyze an input signal before passing it on to a receiver. The analysis may be done outside of the data path to avoid affecting the data path speed or adding distortion or jitter. The positive and negative thresholds of the data may be checked to see if the numbers of positive and negative crossings are comparable. Random and bursty noise can be detected since such noise normally does not have comparable positive and negative crossings. | ||||||
| 127 | Method of deriving a frequency of a pulse signal from alternate sources and method of calibrating same | US09701323 | 2001-02-09 | US06590376B1 | 2003-07-08 | Kurt Bammert; Mirko Bulinsky; Michel Schaller |
| A method derives a frequency of a pulse signal from a line frequency. The method includes measuring a period of a line frequency pulse signal having the line frequency using a measured frequency derived from an oscillator frequency. The method further includes determining if the period of the line frequency pulse signal is within a predetermined tolerance limit. The line frequency is used to derive the frequency of the pulse signal when the period is determined to be within the predetermined tolerance limit, and the oscillator frequency is used to derive the frequency of the pulse signal when the period is determined to be outside the predetermined tolerance limit. | ||||||
| 128 | Phase and frequency detector with high resolution | US09506440 | 2000-02-18 | US06194918B1 | 2001-02-27 | Clarence Jörn Niklas Fransson; Mats Wilhelmsson |
| A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal. The second subtractor subtracts, for each second register and its first register, the counter values thereof to generate a frequency representing value. | ||||||
| 129 | Biasing scheme for minimizing output drift in phase comparison and error correction circuits | US200245 | 1998-11-25 | US6087856A | 2000-07-11 | John M. Puvogel |
| A phase comparison and error correction circuit which utilizes one of a plurality of outputs of its phase detector as a biasing voltage for its error correction circuit. | ||||||
| 130 | Frequency detecting circuit | US166960 | 1998-10-06 | US6081137A | 2000-06-27 | Sang-Shin Choi |
| A frequency detecting circuit is provided that includes a level shift detecting unit for generating pulse signals of a certain pulse width at each level shifting of input clock signals and a level detecting unit. The level detecting unit includes a charging unit and a discharging unit. The discharging unit is activated by the pulse signals of the level shift detecting unit to discharge the charges of the charging unit. An inverter having a logic threshold voltage receives electrical signals in accordance with the charged level of the charging unit to output a signal indicative of the frequency of the input clock signals. | ||||||
| 131 | Method and apparatus for testing frequency symmetry of digital signals | US40477 | 1993-03-31 | US5436927A | 1995-07-25 | Gary Brady; David Ellis |
| A first and a second input generating circuits, a first and a second set of counters, and a first and a second comparison circuits are provided to test whether the frequencies of a first and a second periodic digital signal are symmetric. The first and second input generating circuits generate enable inputs for the first and second sets of counters using the first and second digital signals respectively. The first and second sets of counters count the first and second digital signals while the enable inputs are provided. The first comparison circuit monitors the first set of counters, and stops both input generating circuits from providing further enable inputs to both sets of counters, after the first set of counters reaches a predetermined level, thereby stopping both sets of counters from further counting. The second comparison circuit monitors the second set of counters, and issues a control signal indicating the first and second digital signals are symmetric to each other in frequency, if the second set of counters also stops substantially at the predetermined level, i.e. within an acceptable threshold. | ||||||
| 132 | Frequency discriminator of horizontal synchronizing signal for multi-mode monitor | US991862 | 1992-12-15 | US5367266A | 1994-11-22 | Keehyun Kang |
| A frequency discriminator of the horizontal synchronizing signal for a multi-mode monitor has a plurality of filter capacitors connected to horizontal synchronizing signal lines for rejecting noises of a direct current component of the horizontal synchronizing signal. The frequency discriminator also includes a plurality of phase comparator means respectively connected to the filter capacitors for comparing local oscillating frequencies set differently according to each mode with the inputted horizontal synchronizing signal to output one signal representative of the mode of the monitor. | ||||||
| 133 | Circuit for measuring the difference between two successive periods in a waveform | US856420 | 1992-03-23 | US5200656A | 1993-04-06 | Richard D. Gunther |
| An improved time discriminator system that is incorporated on a only a single gallium arsenide chip. The system includes a sensing stage, a ramping stage, a storage stage, a logic stage, and an output stage. An input signal is input to the sensing stage, which determines the length of successive time periods in the signal, and outputs corresponding control signals. The ramping stage generates dual ramping voltages on alternate periods of the input signal, corresponding to the successive period lengths. Values of the ramping voltages are sampled and held by a storage stage. Voltages held by the storage stage are subtracted from each other and amplified in a logic stage. The output stage resamples the signal coming from the logic stage, and outputs an analog signal that is proportional to the time difference between successive periods of the input signal. | ||||||
| 134 | Signal conditioning circuit and method | US286906 | 1988-12-19 | US4912419A | 1990-03-27 | James E. Young |
| An apparatus and method for detecting the period of a frequency signal having a period greater than a minimum period and within a period range. A clock frequency is generated such that when multiplied by the predetermined range the product is less than 2.sup.N and when multiplied by the minimum period of the product is less than 2.sup.N+M. The resulting clock frequency is multiplied by the minimum period to generate an offset number. A counter is preset with the offset number in response to a detected edge transition of the frequency signal. The counter counts at the clock frequency from a complement of the offset number to a final count at a subsequent edge transition. The final count is contained within the first N bits and is related to the period of the frequency signal. | ||||||
| 135 | Method and apparatus for simultaneous instantaneous signal frequency measurement | US37846 | 1987-04-13 | US4791360A | 1988-12-13 | Andre Gagnon; Myles McMillan; P. Michael Gale |
| A method and apparatus for performing simultaneous instantaneous signal frequency measurement using a signal sorter in conjunction with a frequency measurement receiver. Simultaneous signals of similar amplitude are received and successively applied to a plurality of either frequency or time dependent signal modifying circuits, via switching circuitry. Respective ones of the received signals are separated with respect to frequency in one or both of amplitude and time from one another via the signal modifying circuits which can be, for instance low pass and high pass filters, or positive and negative dispersive delay lines. In addition, the received signals are applied to a straight-through signal path for transmitting the signals to the frequency measurement receiver unaltered. Signals output from the signal modifying circuits and the straight-through signal path are successively applied to the frequency measurement receiver for detecting the frequency of respective ones of the separated received signals. | ||||||
| 136 | Malfunction detector for detecting open-circuit condition at DC generator output terminal | US659476 | 1984-10-10 | US4634955A | 1987-01-06 | Hifumi Wada |
| A malfunction detector for detecting an open-circuit condition at the output terminal of a vehicular DC generator is disclosed. The frequency of a signal derived from one of the armature windings of the generator, for instance, at an end or neutral terminal, is compared with the control frequency of the voltage regulator, which may be derived from a field winding of the generator. If the latter is equal to the former, an indication of an open-circuit condition is given. | ||||||
| 137 | Circuit for comparing two or more frequencies | US672478 | 1984-11-16 | US4599580A | 1986-07-08 | Akira Yamaguchi; Hiroshi Shigehara; Hidemi Iseki |
| According to a frequency comparing circuit of the present invention, there is provided a negative switched capacitor circuit having negative equivalent resistance, the value of which is determined according to the reference frequency and the frequency to be compared, and a positive switched capacitor circuit having positive equivalent resistance, the value of which is determined according to the reference frequency. A constant DC voltage is supplied in parallel to one terminal of the two switched capacitor circuits. The respective terminals of the switched capacitor circuits are commonly connected in order to produce the composite current of both output currents of the two switched capacitor circuits. The composite current is integrated by an integrator. Further, there is provided a Schmitt-type oscillating circuit. The oscillating frequency signal from the Schmitt-type oscillating circuit is supplied to the negative switched capacitor circuit. The higher level threshold voltage of the Schmitt-type oscillating circuit is determined according to the composite current of both output currents of the two switched capacitor circuits, thereby adjusting the frequency of the oscillating signal of the Schmitt-type oscillating circuit. The oscillating signal is supplied to the positive switched capacitor circuit. The lower level threshold voltage of the Schmitt-type oscillating circuit is determined according to the composite current of both output currents of the two switched capacitor circuits. Therefore, the frequency of the oscillating signal of the Schmitt-type oscillating circuit is adjusted. | ||||||
| 138 | Remote control circuit employing frequency/direct signal converters | US85334 | 1979-10-16 | US4361837A | 1982-11-30 | Christopher W. Malinowski; Heinz Rinderle |
| A remote control circuit which operates on a frequency basis and essentially with analog signals. The remote control circuit includes at the transmitting end a controlled oscillator, a frequency/direct signal converter and a comparator connected together into a frequency control loop. A transmitter is also provided which is fed by the oscillator of the control loop. A control path including a frequency signal source and a frequency/direct signal converter is provided at the transmitting end and receives its input signal from the frequency signal source. The converter of the control path is connected with the one input of the comparator of the control circuit. At the receiving end there is provided an amplifier, a frequency/direct signal converter and an evaluation circuit. | ||||||
| 139 | Frequency control system | US217404 | 1980-12-17 | US4340864A | 1982-07-20 | Christopher W. Malinowski; Heinz Rinderle |
| A circuit for producing a frequency dependent output signal in response to two a.c. input signals, including a converter unit connected to receive the two a.c. input signals for furnishing an output signal having a d.c. component which varies in dependence on changes in the value of a relationship between the frequencies of the two a.c. input signals, and a frequency generator connected to the converter unit for producing an a.c. output signal whose frequency is a function of the value of such d.c. component. | ||||||
| 140 | Electronic discrimination circuitry for the highest frequency of a plurality of input signals | US105132 | 1979-12-19 | US4321547A | 1982-03-23 | Gordon W. Pickard; Ian Hayward |
| In electronic discrimination circuitry each of a plurality of at least three analog input signals is converted to respective digital pulse output signals and to a number of multi-phase clocking signals equal in number to the plurality of input signals are also generated such that each of the plurality of at least three analog input signals is synchronized in response to a respective one of the multi-phase clocking signals, whereby at least the leading edge of each of the digital output signals is positioned into a time slot corresponding to the multi-phase clocking signals. Selected pairs of the synchronized digital output signals are sequentially compared to determine within each compared pair that digital output signal having a higher frequency and comparing that digital output signal with another digital output signal until the digital output signal having the highest frequency is selected. | ||||||
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