| Document | Document Title |
|---|---|
| US11343534B2 |
Method and device for obtaining motion vector of video image
A video processing method includes performing or skipping following processing based on whether a size of a coding unit is not smaller or is smaller than 8×8. The processing includes dividing the coding unit into sub-blocks each having a fixed size of 8×8, scanning a left neighboring block and determining a reference motion vector of the coding unit, determining a related reference block of a sub-block in the co-located reference image according to the reference motion vector, determining a scaling factor of a motion vector of the related reference block, scaling the motion vector of the related reference block using the scaling factor, determining motion information of the sub-block according to the scaled motion vector, and performing prediction for the coding unit according to the motion information. |
| US11343529B2 |
Calculation of predication refinement based on optical flow
A method of video processing includes determining a first motion displacement Vx(x,y) at a position (x,y) and a second motion displacement Vy(x,y) at the position (x,y) in a video block coded using an optical flow based method, wherein x and y are fractional numbers, where Vx(x,y) and Vy(x,y) are determined based at least on the position (x,y) and a center position of a basic video block of the video block, and performing a conversion between the video block and a bitstream representation of the current video block using the first motion displacement and the second motion displacement. |
| US11343528B2 |
Compound prediction for video coding
Generating a compound predictor block of a current block of video can include generating, for the current block, predictor blocks comprising a first predictor block including first predictor pixels and a second predictor block including second predictor pixels; using at least a subset of the first predictor pixels to determine a first weight for a first predictor pixel of the first predictor pixels; obtaining a second weight for a second predictor pixel of the second predictor pixels, where the second predictor pixel is co-located with the first predictor pixel; and generating the compound predictor block by combining the first predictor block and the second predictor block, where the predictor block includes a weighted pixel that is determined using a weighted sum of the first predictor pixel and the second predictor pixel using the first weight and the second weight, respectively. |
| US11343527B1 |
Usage of converted uni-prediction candidate
Techniques for implementing video processing techniques are described. In one example implementation, a method of video processing includes determining, for a conversion between a current block of a video and a bitstream representation of the video, a modified motion vector set; and performing the conversion based on the modified motion vector set. Due to the current block satisfying a condition, the modified motion vector set is a modified version of a motion vector set associated with the current block. |
| US11343524B2 |
Method for adaptation parameter set reference and constraints in coded video stream
A method of decoding an encoded video bitstream using at least one processor, including: obtaining from the encoded video bitstream a coded video sequence including a picture unit corresponding to a coded picture; obtaining a picture header (PH) network abstraction layer (NAL) unit included in the picture unit; obtaining at least one video coding layer (VCL) network abstraction layer (NAL) unit included in the picture unit; decoding the coded picture based on the PH NAL unit, the at least one VCL NAL unit, and an adaptation parameter set (APS) included in an APS NAL unit obtained from the coded video sequence; and outputting the decoded picture, wherein the APS NAL unit is available to the at least one processor before the at least one VCL NAL unit. |
| US11343520B2 |
Video transmission device and video transmission method
The present disclosure aims to provide a method for detecting a GOP boundary of an encoded bit stream of each layer and associating GOPs of the layers for hierarchical transmission in a video transmission device that transmits a hierarchically encoded bit stream. The present disclosure provides a video transmission device and a video transmission method that detect a GOP head access unit in a base layer of a hierarchically encoded bit stream by analyzing the base layer and detect a head access unit of an enhancement layer of an identical GOP to that of the aforementioned access unit from a decoding time stamp of the access unit by using the relationship between a decoding time stamp of the base layer and a decoding time stamp of the enhancement layer. |
| US11343515B2 |
Image processing apparatus, image processing method, and recording medium
A computer-readable recording medium storing a program that causes a computer to execute a process, the process includes specifying occurrence frequencies of respective gradation values with regard to pixels included in image data and represented by gradation values of a predetermined bit count; extracting a predetermined number of gradation values from a gradation value having a high occurrence frequency in a descending order; generating correspondence information for performing bit conversion of the extracted gradation values into coded values of a bit count in accordance with the predetermined number; and encoding the image data by performing bit conversion of first pixels having any one of the predetermined number of gradation values among the pixels based on the correspondence information, and performing bit conversion of second pixels having any one of gradation values other than the predetermined number of gradation values among the pixels. |
| US11343511B2 |
Content-aware predictive bitrate ladder
Methods, systems, and apparatuses may encode a media content item based on metadata from previous encoding. The encoding may also generate encoding metadata, which may comprise a qualitative or quantitative characterization of the encoded media content item. A prediction engine may, based on this metadata, determine new encoding settings for the same or a different video resolution. The prediction engine may cause an encoded media content item to be stored and may cause encoding of the media content item using the new encoding settings. |
| US11343509B2 |
Mode dependent motion vector difference precision set
A method of processing a video bitstream includes determining a motion precision set based on coding information of a current block. A conversion between a video block and a coded representation of the video block is performed based on the motion precision set. The conversion corresponds to a reconstruction of the current block. In some example aspects, a motion vector difference (MVD) precision of a current block from a motion precision set is determined based on a selected motion precision set and a MVD precision index. A conversion between a video block and a coded representation of the video block using an MVD is performed based on the MVD precision. The MVD represents a difference between a predicted motion vector and an actual motion vector used during motion compensation processing. |
| US11343508B2 |
Method for determining prediction direction, decoder, and computer storage medium
A method for determining a prediction direction is provided. The method is implemented by a decoder. The method includes: acquiring a Direct Mode (DM) in a chroma intra prediction mode of a block to be decoded (S101); and determining an index number of a prediction direction in a DM derived mode based on an offset N and an index number M of a prediction direction in the DM to determine the DM derived mode (S102). |
| US11343503B2 |
Flexible quantization
A digital media encoder/decoder uses a flexible quantization technique that provides the ability to vary quantization along various dimensions of the encoded digital media data, including spatial, frequency sub bands and color channels. The codec utilizes a signaling scheme to signal various permutations of flexible quantization combinations efficiently for primary usage scenarios. When a choice of quantizer is available, the codec efficiently encodes the current quantizer by defining a subset of quantizers and indexes the current quantizer from the set. |
| US11343498B2 |
Method and apparatus for processing video signal
A method of processing video signal according to a present invention comprises determining a transform set for a current block comprising a plurality of transform type candidates, determining a transform type of the current block from the plurality of transform type candidates and performing an inverse transform for the current block based on the transform type of the current block. |
| US11343495B2 |
Methods of simplification of temporal filtering
Systems and methods for implementing temporal filtering are provided. A method includes: applying a temporal filter to a current picture and encoding the current picture after the temporal filter is applied. The applying includes obtaining an exponential function, that includes an exponent with a numerator with at least one first factor and a denominator with at least one second factor, by computing the exponent of the exponential function as fixed-point values or by using at least one lookup table; obtaining a weight of at least one neighboring picture by multiplying a scaling function with the exponential function; obtaining a filtered sample value of the current picture based on a sample value of the current picture and the weight of the at least one neighboring picture; and replacing the sample value of the current picture with the filtered sample value. |
| US11343492B2 |
Method for generating video- and audience-specific encoding ladders
A method including: extracting a set of video features representing properties of a video segment; generating a set of bitrate-resolution pairs based on the set of video features, each bitrate-resolution pair in the set of bitrate-resolution pairs defining a bitrate and defining a resolution estimated to maximize a quality score characterizing the video segment encoded at the bitrate; accessing a distribution of audience bandwidths; selecting a top bitrate-resolution pair in the set of bitrate-resolution pairs; selecting a bottom bitrate-resolution pair in the set of bitrate-resolution pairs; selecting a subset of bitrate-resolution pairs in the set of bitrate-resolution pairs based on the distribution of audience bandwidths, the subset of bitrate-resolution pairs defining bitrates less than the top bitrate and greater than the bottom bitrate; and generating an encoding ladder for the video segment comprising the top bitrate-resolution pair, the bottom bitrate-resolution pair, and the subset of bitrate-resolution pairs. |
| US11343486B2 |
Counterrotation of display panels and/or virtual cameras in a HMD
A head-mounted display (HMD) system may include a HMD with a housing and a pair of display panels, mounted within the housing, that are counterrotated in orientation. A compositor of the HMD system may also be configured to provide camera pose data with counterrotated camera orientations to an executing application (e.g., a video game application), and to resample the frames received from the application, with or without rotational adjustments in the clockwise and counterclockwise directions depending on whether the display panels of the HMD are upright-oriented or counterrotated in orientation. A combined approach may use the counterrotated camera orientations in combination with counterrotated display panels to provide a HMD with optimized display performance. |
| US11343485B1 |
Virtual horizontal stereo camera
An apparatus including a stereo camera and a processor. The stereo camera may comprise a first capture device and a second capture device in a vertical orientation. The first capture device may be configured to generate first pixel data and the second capture device may be configured to generate second pixel data. The processor may be configured to receive the first pixel data and the second pixel data, generate a vertical disparity image in response to the first pixel data and the second pixel data, generate a virtual horizontal disparity image in response to the first pixel data and the vertical disparity image and detect objects by analyzing the vertical disparity image and the virtual horizontal disparity image. An analysis of the virtual horizontal disparity image may enable the processor to detect the objects not detected in the vertical disparity image alone. |
| US11343483B2 |
Display device
A display device comprises a display panel including a plurality of pixels; and a timing controller performing an operation for displaying an image on the display panel, wherein the timing controller includes a second image data converter generating output image data by converting luminance of an object depending on a disparity of the object included in a left eye image and a right eye image for reducing power consumption of a display device by using depth map information of image data is proposed. |
| US11343482B2 |
Suggested viewport indication for panoramic video
A suggested viewport indication is generated and sent for use in a panoramic video. In one example, a method includes receiving encoded video including viewport metadata, decoding the video, extracting the viewport metadata, generating a viewport of the decoded video based on the viewport metadata, and buffering the generated viewport for display. |
| US11343479B2 |
Control method for position detecting device, position detecting device, and projector
A control method for a position detecting device including a first adjusting step of emitting detection light to a jig for adjustment disposed on a screen and adjusting the detection light to first detection light such that the detection light is emitted to a specific range of the jig for adjustment and a step of setting, in a state in which the detection light has been adjusted to the first detection light, a region including the jig for adjustment as a non-detection area where a detecting section does not detect the detection light as the reflected light from an obstacle, wherein the position detecting device including a light emitting section configured to emit the detection light and the detecting section. |
| US11343478B2 |
Method of controlling a display system including a plurality of projectors and control device
A method of controlling a display system including the steps of projecting, by a plurality of group-belonging projectors, an image in one display area corresponding to one projector group to thereby display one composite image corresponding to the one projector group out of a plurality of composite images corresponding one-to-one to a plurality of projector groups in the one display area, estimating, by a control device, brightness of the plurality of composite images, identifying, by the control device, a dark image which is the darkest and a first adjustment target image different from the dark image from the plurality of composite images based on a result of the brightness estimation, and controlling, by the control device, at least one projector in the projector group corresponding to the first adjustment target image to thereby approximate brightness of the first adjustment target image to brightness of the dark image. |
| US11343476B2 |
Display apparatus
A display apparatus comprises a light source device, an image data processing module, a light modulating device and an image synthesizing device. The light source device is configured to emit first light and second light. The image data processing module is configured to receive original image data of an image to be displayed, wherein the original image data of the image to be displayed is based on image data within a second color gamut range and comprises original control signal values of m colors of each pixel; the second color gamut range covers a first color gamut range and has a portion that exceeds the first color gamut range. The image data processing module is further configured to map the original control signal values of the m colors into m corrected control signal values corresponding to the first light and n corrected control signal values corresponding to the second light. |
| US11343464B2 |
Medical video processing system
When one or multiple video files that correspond to at least a part of preset sections are read out from a storage unit, a length of time of a section overlap, which represents a time slot that overlaps the section among from one or more time slots over which the read video file(s) are recorded, is calculated, and the video file(s) that corresponds to the time code contained in the section overlap having been subjected to calculation are clipped and stored in a predetermined storage area, the medical video processing system can carry out, when the length of time of the section overlap (for example, 32 minutes and 10 seconds) exceeds a predetermined length of time (for example 30 minutes), a shortening process that shortens the length of time of the video file(s) to be stored in the predetermined storage area, down to a predetermined length of time or shorter. |
| US11343454B2 |
Imaging systems and methods for performing pixel binning and variable integration for analog domain regional feature extraction
Imaging circuitry may include circuits for implementing feature extraction in the analog domain. The imaging circuitry may include pixels configured to generate pixel values. The pixel values may then be weighted using variable charge integration times, variable resistors in the readout path, and/or variable switch on times in the readout path. The weighted pixels values may be binned and combined to obtain an output neuron voltage for at least one layer in a neural network. Performing feature extraction in the analog domain for each layer of results in the neural network saves power and area by avoiding the need to move data around to conventional digital memories. |
| US11343452B2 |
Solid-state imaging device, method of driving the same, and electronic apparatus
A solid-state imaging device includes a pixel array unit in which a plurality of imaging pixels configured to generate an image, and a plurality of phase difference detection pixels configured to perform phase difference detection are arranged, each of the plurality of phase difference detection pixels including a plurality of photoelectric conversion units, a plurality of floating diffusions configured to convert charges stored in the plurality of photoelectric conversion units into voltage, and a plurality of amplification transistors configured to amplify the converted voltage in the plurality of floating diffusions. |
| US11343448B2 |
Method of operating an HDR pixel circuit achieving high precision
A method of operating an HDR pixel circuit includes: establishing a calibration full-well capacity of a photodiode according to a first predetermined voltage level; over-charging both the photodiode and a floating diffusion node; dissipating the charges of the floating diffusion node and the charges on the photodiode so that the charges on the photodiode are substantially equal to the calibration full-well capacity; transferring the charges on the photodiode to the floating diffusion node; and sensing a voltage on the floating diffusion node to generate a calibration signal related to the calibration full-well capacity. |
| US11343445B2 |
Systems and methods for implementing personal camera that adapts to its surroundings, both co-located and remote
A computerized system comprising a processing unit and a memory, the system operating in connection with a real-time video conference stream containing a video of a user, wherein the memory embodies a set of computer-executable instructions, which cause the computerized system to perform a method involving: receiving the real time video conference stream containing the video of the user; detecting and separating the background in the received real time video conference stream from the user; and replacing the separated background with a background received from a system of a second user or with a pre-recorded background. |
| US11343443B2 |
Unmanned aerial vehicle and multi-ocular imaging system
An unmanned aerial vehicle (UAV) includes a vehicle body and a multi-ocular imaging assembly. The multi-ocular imaging assembly includes at least two imaging devices disposed in and fixed to the vehicle body. |
| US11343441B2 |
Imaging device and apparatus
Provided is an imaging device and an apparatus that can obtain an appropriate captured image that allows recognition of an object even when a flicker phenomenon is occurring.Provided is an imaging device including a detection unit that detects a blinking object or an object lit by a blinking illuminator, a tracking unit that performs tracking on the detected object, an estimation unit that estimates period information of the blinking, on the basis of a plurality of imaging frames of the tracked object, and a signal generation unit that generates a timing signal for capturing the object, on the basis of the estimation result. |
| US11343434B2 |
Image processing apparatus and control method for same
An image processing apparatus, comprises: an image-obtaining unit configured to obtain a visible image and an infrared image; a luminance obtaining unit configured to obtain a luminance of the visible image; a determining unit configured to determine, based on the luminance obtained by the luminance obtaining unit, a combining ratio between the infrared image and the visible image for generating a combined image obtained by combining the infrared image with the visible image; a combining unit configured to combine the infrared image with the visible image based on the combining ratio determined by the determining unit; and a correcting unit configured to correct the combining ratio such that an amount of change in the combining ratio does not exceed a threshold value, in a case where the amount of change in the combining ratio exceeds the threshold value. |
| US11343431B2 |
Vehicle camera telemetry system
A vehicle camera telemetry system has a remotely mountable camera apparatus which has a stem having a magnet for magnetic affixation to a metallic body of a vehicle in use. The apparatus further comprises a camera device connected from the distal end of the stem by an adjustable coupling. The stem may further be telescopic for length adjustment so as, for example, extend the length of the stem from less than 22 cm to greater than 29 cm. The camera device has an image sensor and a wireless transmitter for transmitting image data obtained therefrom to a connected mobile device using a wireless connection, such as Wi-Fi or Bluetooth. As such, in use, the camera apparatus may be affixed to various parts of a vehicle and/or an associated trailer, caravan or the like. |
| US11343429B2 |
Microvideo system, format, and method of generation
The present disclosure provides systems and methods that use and/or generate image files according to a novel microvideo image format. For example, a microvideo can be a file that contains both a still image and a brief video. The microvideo can include multiple tracks, such as, for example, a separate video track, audio track, and/or one or more metadata tracks. As one example track, the microvideo can include a motion data track that stores motion data that can be used (e.g., at file runtime) to stabilize the video frames. A microvideo generation system included in an image capture device can determine a trimming of the video on-the-fly as the image capture device captures the microvideo. |
| US11343428B2 |
Imaging apparatus and recording medium operating in a first mode or a second mode based on determined brightness of an image
An imaging apparatus includes an imaging device and a processor. The processor is configured to determine brightness of an image when the imaging apparatus is operating in a second operation mode. The processor is configured to increase imaging sensitivity of the imaging device when the processor determines that the brightness is darker than or equal to a first brightness. The processor is configured to cause the imaging apparatus to operate in a first operation mode when the processor determines that the brightness is darker than or equal to a second brightness darker than the first brightness after the processor increases the imaging sensitivity. |
| US11343427B2 |
Imaging device, imaging system, and imaging method
An imaging device according to the present disclosure includes: an imaging unit configured to perform an imaging operation; a data generator configured to generate first power supply voltage data corresponding to a first power supply voltage; and a flag generation section configured to generate a flag signal for the first power supply voltage by comparing the first power supply voltage data and first reference data. The first power supply voltage is supplied to the imaging unit. |
| US11343426B2 |
Notifying apparatus, image capturing apparatus, notifying method, and storage medium for making a notification of motion blur
There is provided a notifying apparatus. A detecting unit detects a motion amount of an object from an image obtained through first shooting, the first shooting being carried out repeatedly at predetermined intervals of time. A converting unit converts the motion amount into a motion blur amount that will arise in second shooting, on the basis of the predetermined intervals of time and an exposure time used in the second shooting. A determining unit determines whether or not to make a motion blur notification on the basis of a predetermined notification condition. A notifying unit makes a notification of motion blur on the basis of the motion blur amount when it has been determined that the motion blur notification is to be made. |
| US11343425B2 |
Control apparatus, control method, and storage medium
A control apparatus 220 controls the in-focus positions of a plurality of image capturing apparatuses that perform image capturing from a plurality of directions in order to generate a virtual-viewpoint image. Specifically, the control apparatus 220 obtains an image capture parameter related to image capturing by one or more image capturing apparatuses included in an image capturing apparatus group 100. The control apparatus 220 controls on the basis of the obtained image capture parameter, the in-focus position of a target image capturing apparatus corresponding to the image capture parameter such that the distance from the target image capturing apparatus to the in-focus position of the target image capturing apparatus is shorter than the distance from the target image capturing apparatus to a point of interest. |
| US11343424B1 |
Image capturing method and electronic device
An image capturing method is provided. The method includes: shooting a monitoring scene at the same time through multiple image capturing devices to capture multiple images corresponding to multiple focal lengths at a same time point; recognizing a target area of each of the captured images according to multiple focal sections; keeping multiple target sub-images in the target areas of the images, in which multiple object images in the target sub-images are all focused; directly generated a single reconstructed image corresponding to the time point according to the target sub-images; and outputting the reconstructed image. |
| US11343420B1 |
Systems and methods for eye-based external camera selection and control
Presented in the present disclosure are system and methods embodiments that allow a user to wear a contact lens that provide a virtual framework for the user to retrieve information from one or more remote cameras and implement remote camera control via eye movement tracked by one or more motion sensors embedded within the contact lens. The remote camera control may include, but not limited to, pan, tilt, and zoom control. A user may activate projection of content captured from a remote camera and control the remote camera via an established communication link. The communication link may be a direct link or indirect link via one or more intermediate devices, e.g., a server and/or an accessory device. This unique way of projection activation and camera control by tracking eye movement provides a convenient and secure way for remote camera control without involvement of hands or voices. |
| US11343419B2 |
Full-screen image display and optical assembly thereof
A full-screen image display and an optical assembly thereof are provided. The full-screen image display includes a first display module and a second display module. The first display module is an organic LED display, a liquid crystal display or an LED display for providing a first image, and the second display module is an LED display for providing a second image. The first display module and the second display module are adjacent or connected to each other, and the first image and the second image are combined to form a continuous image. The second display module includes a circuit substrate, an image display unit disposed on the circuit substrate, and a plurality of electronic units disposed on the circuit substrate. The image display unit includes a plurality of LED chips disposed on the circuit substrate, and the second image is provided by the LED chips. |
| US11343415B1 |
Multi-camera alignment in a rollable display device
According to one embodiment, a method, computer system, and computer program product for operating a flexible device equipped with one or more cameras to visually capture a target area is provided. The present invention may include identifying a bending profile and a holding pattern of a flexible device, and individually aligning one or more cameras of the flexible device to visually capture a target area designated by a user based on the bending profile and the holding pattern of the flexible device. The present invention may further include identifying one or more of the flexible device's cameras as compromised based on visual quality falling below a threshold, and disabling the compromised devices or recommending a new holding pattern or new bending profile to a user that would allow the cameras to capture the target area. |
| US11343414B2 |
Vehicular camera with thermal compensating means
A vehicular camera is configured to be disposed at a vehicle. The camera includes a circuit board and a lens holder having a lens barrel accommodating a lens. The circuit board has circuitry disposed at a circuit board substrate. The circuitry includes an imager disposed at a first side of the circuit board substrate. The circuit board substrate has a coefficient of thermal expansion (CTE) that is different from the CTE of the lens holder. The circuit board substrate is attached at the structure of the lens holder via a fastener that passes through an oversized hole in the circuit board substrate, with a cross dimension of the oversized hole being greater than a corresponding cross dimension of the fastener. The vehicular camera, via movement of the fastener within the oversized hole, allows for temperature-induced expansion or contraction of the lens holder relative to the circuit board substrate. |
| US11343411B2 |
Imaging apparatus including circuitry that causes the display of an image corresponding to raw data and with characteristics determined by selected setting information
[Object] To quickly and correctly reproduce an image intended by a photographer, a cinematographer, and the like on the occasion of post-production.[Solving Means] The development apparatus includes: an imaging unit that performs shooting and generates RAW data; a first conversion unit that converts the generated RAW data into image data by interpolation; an acquisition unit that acquires an exposure index value corresponding to an illuminance of a shooting environment; a first correction unit that corrects a value of the image data based on the exposure index value; and an output unit that associates the RAW data and the acquired exposure index value with each other and outputs the associated RAW data and exposure index value. |
| US11343405B1 |
Methods and systems for adding one or more new images to an input document
The present disclosure discloses methods and systems for adding one or more new images to an input document having one or more pages. The method includes receiving an input document from a user. Upon receiving the input document, a user interface having an option for adding one or more new images to the input document is provided to the user for selection. Once selected, one or more keywords are identified based on the content of the input document. Based on the identified keywords, one or more new images are searched via one or more sources and displayed to the user for selection. The user provides his input to add the selected images to a pre-defined area in the input document. Subsequently, the selected images are added to the pre-defined area of the input document, resulting in an output document, for further processing. |
| US11343402B2 |
Semi-transparent embedded watermarks
A watermark image may be generated that includes a first set of encoded pixels each of which is assigned a first transparency value and a second set of encoded pixels each of which is assigned a second transparency value, the second transparency level being different from the first transparency level. The encoded pixels may be distributed among a set of blank pixels such that each encoded pixel neighbors one or more blank pixels in the watermark image, and in particular at least two blank pixels in the watermark image. Herein, each blank pixel may be assigned the second transparency value. The watermark image may be overlaid and blended over a background source image to create an encoded source image. A decoder system may recover encoded information from the encoded source image. |
| US11343395B2 |
Apparatus and non-transitory computer readable medium
An apparatus includes a processor. The processor is configured to identify a user who is operating the apparatus provided with the processor and execute display control involving controlling display of a notification related to a process executed by the apparatus on a display device provided in the apparatus in accordance with whether or not the identified user is a commander who has given a command for executing the process. |
| US11343394B2 |
Information processing apparatus, method and non-transitory computer readable medium
An information processing apparatus includes a providing unit, an obtaining unit, and an informing unit. The providing unit provides a certain service to a user. The obtaining unit obtains identification information included in receivable radio waves. The informing unit provides information how a user is able to use the service provided by the providing unit if a place where the user is positioned is not a place where the service is available. The place where the user is positioned is estimated by the identification information obtained by the obtaining unit. |
| US11343391B2 |
Image processing apparatus, control method for image processing apparatus, and storage medium
Provided is an image processing apparatus including a display operation unit, the image processing apparatus including: a memory; and a processor in communication with the memory, wherein the processor is configured to: display a predetermined operation screen for selectively displaying at least one of a plurality of buttons each for specifying processing to be executed; and execute, based on display, on the predetermined operation screen, of a button having an attribute in which processing corresponding to the button is started in response to a user operation on the button, a preparation operation for a processing unit corresponding to the button. |
| US11343389B2 |
Writing IPV4 or IPV6 information into an NFC tag attached to an image forming apparatus
When a plurality of types of IP addresses is enabled in an information processing apparatus, the information processing apparatus selects an Internet Protocol (IP) address to be written to a near field communication (NFC) tag. Then, the information processing apparatus generates tag information based on the selected IP address, and writes the generated tag information to the NFC tag. |
| US11343387B2 |
Electronic device, imaging device, image reproduction method, image reproduction program, recording medium with image reproduction program recorded thereupon, and image reproduction device
An electronic device includes: a communication unit that performs communication with an external device; and a control unit that issues a command to the external device via the communication unit, on the basis of at least one of capacity of the external device, and capacity of the electronic device. |
| US11343386B2 |
Scan system operable by a web application linked with a message sharing system, image processing apparatus, method, and program storage medium
A web application of a scan system provides confirmation data associated with a scan data destination to a post source of a scan-related message through a message sharing system. An image processing apparatus transmits scan data and the input confirmation data to the web application. When the input data transmitted from the image processing apparatus is stored as the confirmation data in the storage, the web application posts the scan data to the destination associated with the confirmation data using the message sharing system. |
| US11343384B1 |
System and method for providing customized merchandise at entertainment venues
A system for providing customized merchandise to a user at an entertainment venue via a user computer device has a machine readable tag encoding an address, and a fulfillment computer having a printer. The machine readable tag is located at the entertainment venue. A computer memory of the fulfillment computer stores executable code that enables the fulfillment computer to perform a process having the following steps: receiving a request from the user computer device generated by capturing the machine readable tag with a camera of the user computer device; uploading at least one photograph from the user computer device; collecting payment for the customized merchandise; printing the selected photograph on the selected style of the customized merchandise; and delivering the customized merchandise to the user. |
| US11343379B2 |
Web widget that facilitates telephone calls with customer-support agents and other customer-support services
A system and method for providing customer-support services to a user of a website through a web widget. When the user accesses a web page containing the web widget, a call is automatically made from the web widget to a customer-support system. In response to the call, the system obtains status information from the customer-support system indicating whether customer-support agents are available to take telephone phone calls. If the status information indicates customer-support agents are available to take telephone calls, the web widget provides a call-related interface to the user, wherein the call-related interface is configured to facilitate a telephone call with a customer-support agent. If the status information indicates customer-support agents are not available to take telephone calls, the web widget provides a non-call-related interface to the user, wherein the non-call-related interface is configured to facilitate an alternative channel of customer support that does not involve a telephone call. |
| US11343376B1 |
Computerized system and method for robocall steering
Disclosed are systems and methods for robocall steering over voice-hosted traffic networks. The disclosed framework provides novel systems and methods for increasing the accuracy and efficiency in tracking, identifying, blocking and preventing robocalls and robocallers. The disclosed systems and methods provide mechanisms for identifying and removing unwanted voice traffic from networks. The disclosed systems and methods analyze voice traffic over a predetermined period of time (e.g., 1 day or 30 days, for example), and leverage this information into a “know your customer” (KYC) score. This score enables incoming calls to be routed, controlled and/or blocked as they are communicated over voice networks. |
| US11343374B1 |
Message aggregation and comparing
Techniques for detecting spam accounts in a system are described. The system may analyze speech characteristics of communication content (e.g., telephone call content, VoIP content, audio messaging, etc.) to determine whether multiple devices or user profiles are associated with overlapping communications. The system may also analyze text transcriptions of communication content to determine whether multiple devices or user profiles are associated with overlapping communications. If so, the system may mitigate, such as throttling service, disabling accounts, and the like. |
| US11343373B1 |
Machine intelligent isolation of international calling performance degradation
The disclosed system identifies international calling performance issues of a wireless telecommunication network. The system receives network traffic data for international calls including information about call attempts to a country. The system categorizes the country into a major category and a minor category based on the call attempts information. For a subset of countries, and for each key performance indicator in a subset of selected key performance indicators, the system monitors performance using an anomaly detection model to identify an anomaly in network performance, determines an actual value of the key performance indicator for the detected anomaly, and computes a variation value of the determined actual value based on a predicted range of values. The system ranks countries using the computed variation values, to indicate problematic parts of the wireless telecommunication network. |
| US11343370B1 |
Screen interface for a mobile device apparatus
In various embodiments, different mobile phone apparatuses are provided, comprising: a touchscreen a near field communication interface; at least one non-transitory memory storing instructions; and one or more processors in communication with the touchscreen, the near field communication interface, and the at least one non-transitory memory, wherein the one or more processors execute the instructions to initiate various capabilities and/or functionalities in connection with a screen displayed on the touchscreen. |
| US11343364B2 |
Mobile terminal including display subjectable to bending deformation
A mobile terminal comprises a display unit that may be subjected to bending deformation in a first direction, and a rolling plate attached to a rear surface of the display unit, enabling bending deformation to correspond to bending deformation of the display unit, wherein the rolling plate includes a plurality of support bars extended in a second direction vertical to the first direction and arranged in parallel in the first direction, and an expanded side portion arranged at an end portion of the plurality of support bars, and the expanded side portion includes a guide bump engaged with its adjacent expanded side portion. Since the rolling plate supporting the display unit is not twisted by rotation, the display unit may maintain a flat state. |
| US11343359B2 |
Data transmission and reception method in vehicle network, and apparatus for the same
An operation method of a first communication node in an Ethernet-based vehicle network is provided. A frame n is generated including a data unit n, and a first indicator indicating that a size of a data unit n+1 to be transmitted via a frame n+1 after determining that the frame n is different from a size of the data unit n. The frame n is transmitted to a second communication node and the frame n+1 is generated including the data unit n+1. The frame n+1 is then transmitted to the second communication node. The transmission rate of the data unit n is different from the transmission rate of the data unit n+1, and n is a natural number. |
| US11343354B2 |
Increasing user engagement during computing resource allocation queues for cloud services
In various examples, upon receiving an indication from a launcher application that a user desires to engage with a cloud gaming or computing service, and determining that a desired computing resource requested for such engagement is unavailable for allocation, one or more interactive content items may be presented in association with a display of the user's local computing device. User actuation of an interactive content item may cause presentation of an options window. One option may cause presentation of an additional content item in the background so it may be viewed after engagement. Another option may cause display of an additional content item, such as in place of the interactive content item or in a web browser external to the launcher application. This option may also cause cancellation of the user request for the allocation and removal of the user request from a queue. |
| US11343349B2 |
Deployment ready techniques for distributed application clients
A Rules-Based Just-In-Time (RBJIT) content streaming engine collects information such as behavior, usage, movement, and preferences about a user, any groups that the user is associated with, and the set of all users in general. Based on this information, the RBJIT may preferentially select multimedia content and content suggestions for user display, increasing the likelihood that the surfaced content will be of interest to a user. In this way, browsing time for a user on a device with a limited form factor is reduced and network bandwidth is conserved by not surfacing content that the user ultimately will not view. |
| US11343344B1 |
Proxy server entity transfer modes
A proxy server is augmented with the capability of taking transient possession of a received entity for purposes of serving consuming devices. This capability supplements destination forwarding and/or origin server transactions performed by the proxy server. This capability enables several entity transfer modes, including a rendezvous service, in which the proxy server can (if invoked by a client) fulfill a client's request with an entity that the proxy server receives from a producing device contemporaneous with (or shortly after) the request for that entity. It also enables server-to-server transfers with synchronous or asynchronous destination forwarding behavior. It also enables a mode in which clients can request different representations of entities, e.g., from either the near-channel (e.g., the version stored at the proxy server) or a far-channel (e.g., at origin server). The teachings hereof are compatible with, although not limited to, conventional HTTP messaging protocols, including GET, POST and PUT methods. |
| US11343342B2 |
Dynamic optimization of request parameters for proxy server
Systems and methods of task implementation are extended as provided herein and target the web crawling process through a step of submitting a request by a customer to a web crawler. The systems and methods allow a more complex request for a web crawler to be defined in order to receive more specific data. In one aspect, a method for data extraction and gathering from a Network by a Service provider infrastructure include the following steps: checking the parameters of a request received from a User's Device, adjusting the request parameters according to pre-established Scraping logic, selecting a Proxy according to the criteria of the pre-established Scraping logic, sending the adjusted request to the Target through the selected Proxy, checking metadata received from the Target, and forwarding the data to the User's device. |
| US11343338B2 |
Analyzing website performance
Techniques are described herein for determining an impact of slow performing webpages on a website. For example, a detection system may be provided to determine timing distributions for webpages by analyzing timing measurements for different timing metrics. The detection system may determine ranges of the timing distributions for slow and fast group of users of the website. The detection system may analyze user interactions of slow and fast group of users on the website. The detection system may further determine impacts of poor performing webpages on the website's performance based on the analysis of the user interactions on the webpages. The detection system may classify the impacts the webpages of the website and display the classifications to a website provider for identifying network operation(s) contributing to poor performance of the webpages. |
| US11343336B1 |
Automatically syndicating licensed third-party content across enterprise webpages
Methods, apparatus, and processor-readable storage media for automatically syndicating licensed third-party content across enterprise webpages are provided herein. An example computer-implemented method includes generating, in connection with licensed third-party content, one or more licensed third-party content syndication files comprising a set of fields related to enterprise product information, licensed third-party content format information, license-related governance information, and enterprise webpage-based distribution information; processing at least a portion of the licensed third-party content using the one or more licensed third-party content syndication files; and automatically syndicating the at least a portion of the licensed third-party content, in accordance with the processing, across multiple user interfaces associated with one or more enterprise webpages, using at least one application programming interface. |
| US11343332B2 |
Method for seamless migration of session authentication to a different stateful diameter authenticating peer
A method and system that migrates a subscriber session from a first authentication, authorization, and accounting (AAA) authentication server to a second AAA authentication server, where the first AAA authentication server is stateful. The method includes receiving an authenticate session request from a client application, sending (505) the authenticate session request to the first AAA authentication server, detecting (511) connectivity failure with the first AAA authentication server, and sending (513) a reauthentication required message to the client application. |
| US11343331B2 |
Collaboration techniques between parties using one or more communication modalities
In one embodiment, a collaboration node prioritizes each modality of communication accessible by at least a first user and a second user based on one or more communication characteristics in a collaboration profile, monitors communication characteristics of a communication session conducted in a first modality of communication between the first user and the second user, and determines a second modality of communication accessible to the first user and the second user having a higher priority than the first modality of communication based on the collaboration profile and the communication characteristics for the communication session. The collaboration node further notifies at least one of the first user or the second user when the second modality of communication has the higher priority than the first modality of communication. |
| US11343330B2 |
Secure access to individual information
A facility for accessing information relating to a person is described. In a reader device, the facility accesses first credentials stored in a first storage device, second credentials stored in a second storage device, and third credentials stored in the reader device. In the reader device, the facility uses a combination of the first credentials, second credentials, and third credentials to decrypt information relating to the person stored in the first storage device. |
| US11343324B2 |
5G internet of things data delivery
A wireless transmit/receive unit (WTRU) may establish one or more protocol data unit (PDU) sessions via a radio access network (RAN) node. The WTRU may transition to an inactive state. The WTRU may send a connection resume message to a RAN node that indicates a request to resume the established plurality of PDU sessions via the RAN node. The WTRU may receive a message from the RAN node. For example, the RAN node may send a message indicating a subset of the plurality of PDU sessions that are available upon resuming a connection with the RAN node. The WTRU may deactivate at least one established PDU session of the plurality of PDU sessions based on the received message from the RAN node that indicates at least one established PDU session not being included in the subset of the plurality of PDU sessions that are available. |
| US11343323B2 |
Augmented reality objects registry
Various embodiments provide for a registry for augmented reality (AR) objects, which can provide AR objects to a client device to support various software or hardware applications. For instance, some embodiments provide for an AR object registry that facilitates or enables registration of one or more AR objects in association with one or more locations across a planet. |
| US11343322B2 |
Virtual edge node as a service
Systems and methods for virtualizing edge node functionality as a service for handling content delivery are described herein. An edge node receives a packet and determines if it associated with an established session and if it should be offloaded for processing. An offload status indicator and/or session context information can be added to the offloaded packet and it is transmitted to a subsequent edge node. |
| US11343314B1 |
Stream-based logging for distributed storage systems
Generally described, aspects of the present application correspond to maintaining a message stream for a network-based data store, which stream includes messages reflecting modifications to the data store. Messages within the stream may be used to revert a state of the data store to a prior point in time reflected within the messages of the stream, such as by “rewinding” operations on the data store by use of the messages within the stream. Messages in the stream may further be used to asynchronously update a replica of the data store. |
| US11343307B2 |
Virtual network function (VNF) resource management in a software defined network (SDN)
A Network Function Virtualization (NFV) Software Defined Network (SDN) controls NFV resources consumed by Virtual Network Functions (VNFs). An NFV Infrastructure (NFVI) executes SDN application VNFs, SDN controller VNFs, and SDN data-machine VNFs. The NFVI responsively transfers SDN Key Performance Indicators (KPIs). A VNF control system processes the KPIs to generate and transfer NFV control data to lighten one of the SDN VNFs. The NFVI lightens the one SDN VNF responsive to the NFV control data by increasing access to NFVI hardware for the one SDN VNF. |
| US11343304B2 |
System and method for sharing electronic data using a mobile device
A system and method is provided for sharing electronic data on a personal computing device using a connected mobile electronic device. An exemplary system includes a client module installed on a mobile device that identifies a list of data sharing services installed on the mobile device, at least one data sharing service configured to share data to a remote device, and transmit the list indicating to a computing device. Moreover, an agent module installed on the computing device selects one or more electronic files to be shared by the mobile device and selects the one of the data sharing services for sharing the selected electronic files. The agent module can then transmit the selected electronic files to the mobile device for data sharing using the selected data sharing service. |
| US11343301B2 |
Managing jitter buffer length for improved audio quality
A technique for managing real-time communications includes generating, during a communication session between at least a first computing device and a second computing device over a computer network, multiple audio factors of the communication session, each of the audio factors being susceptible to degradation in a way that affects audio quality of the communication session. The technique further includes combining the audio factors to produce an overall measure of audio quality and taking remedial action to improve the overall measure of audio quality by adjusting a setting on the first computing device. |
| US11343300B2 |
Systems and methods for adaptive switching between multiple content delivery networks during adaptive bitrate streaming
Systems and methods for adaptive switching between multiple content delivery networks during adaptive bitrate streaming. In one embodiment, an adaptive content delivery network switching device includes a processor, a network interface, and a memory connected to the processor, where the memory contains a content delivery network switching application and, the content delivery network switching application directs the processor to receive content from a first content delivery network, determine a minimum performance threshold based on playback variables from the received content, receive new content from a second content delivery network if the minimum performance threshold is not satisfied. |
| US11343299B2 |
Method and system for real time measuring quality of video call service
Provided is a method of measuring quality of a video call between a transmitting terminal including processing circuitry and a receiving terminal, the method including processing, by the processing circuitry, original frames included in an original video based on a video call service; replacing, by the processing circuitry, real-time video frames acquired from a camera for a video call with a receiving terminal with at least a portion of the original frames; and transmitting, by the processing circuitry, the portion of the original frames to the receiving terminal as frames for the video call with the receiving terminal through the video call service. |
| US11343298B2 |
Video stream management for remote graphical user interfaces
Embodiments enable display updates other than a video stream in a graphical user interface (GUI) to be rendered, encoded, and transmitted exclusive of the video stream. A virtual machine generates a GUI that includes an encoded video stream and other display updates. A virtual graphics processing unit (VGPU) stack associated with the VM renders the other display updates of the GUI to a framebuffer. The rendered display updates are encoded and transmitted to a client for display. The encoded video stream, or a modified (e.g., reduced bit rate) version of the encoded video stream, may be transmitted to the client, such that the client can display the encoded video stream within the GUI. For example, the encoded video stream may be selectively transmitted to the client based on the performance capabilities of the client. |
| US11343294B2 |
Information processing apparatus and non-transitory computer readable medium storing information processing program
An information processing apparatus includes an extraction unit that extracts a worker who participates in cooperative work and has performed work regarding remaining work along with a person in charge of the remaining work in a case where the person in charge of the remaining work in the cooperative work does not participate in the cooperative work, and a request unit that requests the worker extracted by the extraction unit to be in charge of the remaining work. |
| US11343291B2 |
Online conference user behavior
One embodiment provides a method, including: identifying, using a processor, a behavior of a user in a conferencing application; classifying, based on the identified behavior, the user as an aggressive contributor or an acquiescent contributor; and performing, based on the classification, a function. Other aspects are described and claimed. |
| US11343290B2 |
Methods and systems for facilitating context-to-call communications between communication points in multiple communication modes
Methods and systems for facilitating communication sessions between multiple communication points. The method includes receiving a communication request from a first user device associated with a first user, through a first communication point. The first communication point may be enabled with a context-to-call (C2C) feature. The method further includes determining a first communication mode selected by the first user device through the first communication point. The method includes identifying a second communication mode selected by a second user device associated with a second user. The method further includes processing the communication request based, at least in part, on a matching between the first communication mode and the second communication mode. The method further includes transmitting the communication request from the first user device to the second user device. The method includes initiating a communication session based on the processing step. |
| US11343277B2 |
Methods and systems for detecting spoofing of facial recognition in connection with mobile devices
Described are methods, systems, and medias for detecting spoofing of biometric identity recognition and/or validating an identity recognition match by using the camera of a mobile device, processing the user's face image or set of images at a first and second distance to generate first and second data representations, processing the first data representation into a predictive model, and comparing the data representation with the predictive model. |
| US11343276B2 |
Systems and methods for discovering and alerting users of potentially hazardous messages
This disclosure generally revolves around providing users with advance warning that a message that they have received may be suspicious. The user may not be aware of known threats, may not recognize threats in real time, or may not be aware of new threats, and therefore may unintentionally interact with a hazardous message. A security awareness system, on the other hand, is aware of known threats and may become aware of new threats more quickly than users can be trained to identify them. The system may notify the user when one of these threats are found in their messages. The disclosure further provides systems and methods for updating the security awareness training for users for new threats that appear. |
| US11343275B2 |
Detecting potential domain name system (DNS) hijacking by identifying anomalous changes to DNS records
Systems and methods are described for scanning or monitoring of Domain Name System (DNS) records of an entity for identifying anomalous changes to the DNS records that may be indicative of possible DNS hijacking. According to one embodiment, DNS monitoring engine running on a network security appliance protecting a private network, or implemented as a cloud-based service can be used for monitoring DNS records of the entity. Any modification in the monitored DNS record(s) can be detected within a pre-defined or configurable time-frame. The detected modification can be determined to be anomalous or not, by assigning a criticality value based on current value and previous value of one or more fields of the DNS record, one or more attributes of the DNS record and one or more derived attributes based on the DNS record. |
| US11343274B2 |
Non-spoofable privacy indicator showing disabling of sensors on a network-connected client device
Systems and methods are disclosed herein for activating a sensor of a client device by toggling, at the client device, a position of a switch that connects the sensor to a power source of the client device to an on position. The client device receives user input corresponding to a privacy mode. In response to receiving the user input, the client device disables the sensor by toggling the position of the switch that connects the sensor to the power source to an off position, and enables a privacy indicator by toggling a position of a switch that connects the privacy indicator to a power source to an on position. |
| US11343270B1 |
Systems and methods for post-quantum cryptography optimization
Systems, apparatuses, methods, and computer program products are disclosed for post-quantum cryptography (PQC). An example method includes receiving data. The example method further includes retrieving policy information associated with the data. The example method further includes generating a set of policy attributes about the data based on the data and the policy information. Subsequently, the example method includes generating a risk profile data structure based on the set of policy attributes. The risk profile data structure may be indicative of a vulnerability of the data in a PQC data environment. |
| US11343264B2 |
System and method for determining the confidence level in attributing a cyber campaign to an activity group
A system and method is provided for determining the confidence level in attributing a cyber campaign to an activity group. The system and method allows for determining information gaps that need to be filled in order to perform attribution with higher degree of confidence. The system and method is able to extract quantitative data from the campaign intrusion set data and perform a multi-stage analysis and comparison with quantitative data extracted from threat intelligence feeds/platforms and/or vendor intelligence reports. This allows for identifying an activity groups that may be attributed for the campaign with the associated level of confidence. |
| US11343263B2 |
Asset remediation trend map generation and utilization for threat mitigation
The present disclosure relates to methods, systems, and computer program products for generating an asset remediation trend map used in remediating against an attack campaign. The method comprises receiving attack kill chain data. The attack kill chain data comprises steps for executing an attack campaign on one or more assets associated with a computing device. The method further comprises parsing the attack kill chain data to determine one or more attack execution operations for executing the attack campaign on the one or more assets associated with the computing device. The method determines based on the parsing, one or more remediation operations corresponding to the one or more attack execution operations. In addition, the method sequences the one or more remediation operations to form an asset remediation trend map. In one implementation, the asset remediation trend map indicates steps for remediating the attack campaign. |
| US11343258B2 |
Methods and systems for identifying a compromised device through its managed profile
Methods and devices for determining whether a mobile device has been compromised. The mobile device has a managed portion of memory and an unmanaged portion of memory, a managed profile and an unmanaged profile, and the managed profile includes files stored in the managed portion of memory and the unmanaged profile includes files stored in the unmanaged portion of memory. The managed profile is governed by a device policy set by a remote administrator. File tree structure information for the managed profile of the mobile device is obtained that details at least a portion of a tree-based structure of folders and files in the managed portion of memory. It is determined from the file tree structure information that the mobile device has been compromised and, based on that determination, an action is taken. |
| US11343257B2 |
Extended domain platform for nonmember user account management
A device including a processor and a memory, in which the memory includes executable instructions for detecting that a first user has invited a second user to a communication session, wherein the first user is associated with a first user account registered to a first domain platform and the second user is not associated with any of user accounts registered to the first domain platform, the first domain platform defining a first user privilege granted to the user accounts registered to the first domain platform; causing a second user account associated with the second user to be created and registered to a second domain platform, the second domain platform being different from the first domain platform and defining a second user privilege granted to user accounts registered to the second domain platform; and granting the second user account the second user privilege. |
| US11343247B1 |
Local delegation of remote key management service
In general, techniques are described for proxying, with a locally-deployed computing device, service requests from one or more with customer devices to a remote data encryption and key management service and assuming, by the local computing device, the service functions of the remote service in the event of a remote service failure. For example, customer devices at a location may be configured to communicate service requests to the local computing device rather than to a remote service. The local computing device obtains one or more encryption keys or other security objects and stores the security objects to local storage. In response to determining a disruption in the remote service due to, e.g., network connectivity failure, the local computing device may assume the functionality of the remote service for a limited time by performing data encryption operations, responsive to requests received at the local computing device from the customer devices. |
| US11343242B2 |
Dynamic connection across systems in real-time
Establishing a dynamic connection across systems is provided. The method comprises receiving user login credentials from a user from a first device and authenticating the user login credentials in connection with a user account. A session is created in response to successful authorization of the user login credentials, wherein the session comprises a session state that tracks user activity and any changes to a user account during the session, and the first device is bound to the session state and saved as a known device. Upon detecting activity of the user on a second device, a quick response code is created for the user. When the user inputs the quick response code from the second device, the second device is bound to the session state and logged into the session with the session state preserved. |
| US11343237B1 |
Methods for managing a federated identity environment using security and access control data and devices thereof
Methods, non-transitory computer readable media, network traffic manager apparatuses, and systems that assist with managing a federated identity environment includes performing one or more first access control checks on a client upon receiving a request to access one or more web applications. A new signature including data associated with the performed one or more access control checks is generated. Next, the client is redirected to a first server with the generated signature to determine when to authorize the client to access the requested one or more web applications. The client is granted access to the requested one or more web applications when the client is determined to be authorized to access the requested one or more web applications based on one or more second access control checks enforced on the client using the generated signature, and wherein data associated with the enforced one or more second access control checks is included in a response signature. |
| US11343234B2 |
Multi-domain extension to cloud security
Presented herein are methodologies for implementing multi-domain cloud security and ways to partition end-points in data center/cloud network topologies into hierarchical domains to increase security and key negotiation efficiency. The methodology includes receiving, from a first endpoint, at a cloud security protocol stack, a packet encrypted in accordance with a cloud security key negotiated between the first endpoint and a second endpoint; extracting a cloud security globally unique domain-id from the packet; querying a cloud security domain repository using the cloud security globally unique domain-id as an index to identify a first cloud security domain, among a plurality of cloud security domains, to which the first endpoint and the second endpoint belong; and selecting the first cloud security domain to process the packet. |
| US11343218B2 |
Systems and methods for enabling users of a social networking system to assist each other in making connections with other users
A disclosed computer-implemented method may include (1) receiving, from a participant of a discovery service of a social networking system, a request for a friend of the participant to assist the participant in making connections with other participants of the discovery service, (2) identifying at least one set of information that is associated with the discovery service and that is designated as private to the participant, and (3) providing the friend of the participant with access to at least a portion of the set of information via a recommendation interface that enables the friend of the participant to make recommendations to the participant regarding the set of information to assist the participant in making connections with other participants of the discovery service. Various other methods, systems, and computer-readable media are also disclosed. |
| US11343216B2 |
System and method for promoting user engagement
Systems and methods for promoting user engagement with messaging, such as advertising are presented. Specific marketing communications may be evaluated by measuring user responsiveness, such as the respective times at which advertising and other messages may be sent to a user and at which a user may respond, and using these measurements to determine a relative value of the advertising and other messages based on a time decay analytical approach. This approach may include sending an electronic communication to a user interface at a first time for display, sending an electronic message, such as an e-mail or text message to the user at a second time, sending a physical mailing to the user at a third time, receiving a user response at a fourth time, determining the time that elapsed between the fourth time and each of the first, second and third times, and assigning a relative value to each of these messaging events. |
| US11343213B2 |
Method for generating reputation value of sender and spam filtering method
A method for generating a reputation value of a sender includes: obtaining non-spam logs in a specified period; calculating an initial reputation value of a target sender according to sender identifications and recipient identifications of the non-spam logs as well as the number of emails sent by senders of the non-spam logs; calculating a transferred reputation value of the target sender according to the sender identifications of the non-spam logs and the number of the emails sent by the senders of the non-spam logs; and calculating a current reputation value of the target sender according to the initial reputation value and the transferred reputation value of the target sender. The method can accurately calculate the reputation value of the sender without relying on an email sending history of the sender, thereby effectively preventing the reputation value of the sender from being increased by cheating. |
| US11343208B1 |
Automated relevant subject matter detection
One example method of operation may include identifying, via a bot, a query to retrieve content information in a content sharing forum, transmitting the query with the content information to a number of other bots, and each of the number of bots are associated with respective different content sharing forums, creating a number of queries based on the query, transmitting the number of queries to a respective number of caches associated with the respective different content sharing forums to identify whether relevant information associated with the number of queries is available for retrieval, receiving a number of results based on the number of queries, ranking the number of results to determine relevancy of the number of results, selecting the higher ranked results of the number of results, and creating one or more messages in the content sharing forum with at least one of the higher ranked results and links to the higher ranked results. |
| US11343206B2 |
Redundant infrastructure for industrial automation distributed control systems
To facilitate redundancy in a distributed control system architecture used in an industrial automation environment, a user workstation is connected to multiple enterprise access switches. Separate physical connections established between an application server and the enterprise access switches are configured into a single virtual interface for the application server to provide physical media redundancy between the application server and the enterprise access switches. Redundancy switches are connected to the enterprise access switches and to a first LAN and a second LAN, and are assigned unique IP addresses but communicate using a same default gateway IP address to serve as redundant default gateways. The redundancy switches are configured with a redundancy protocol that enables transmission of duplicate data packets over the first LAN and the second LAN. Redundant industrial controllers are connected to both the first LAN and the second LAN, wherein the redundant industrial controllers utilize non-swapping IP addresses. |
| US11343203B2 |
Hierarchical switching fabric and deadlock avoidance method for ultra high radix network routers
This invention discloses a hierarchical switching fabric and deadlock avoidance method for ultra high radix network routers. The hierarchical switching fabric comprises a network-on-chip and K multi-port components. The multi-port component comprises a port module configured to receive packets by a high speed serializer/deserializer, code and format the packets, send the packets to a corresponding hyper packet module after coding and format conversion, and send the packets sent by the hyper packet module to the network; and the hyper packet module configured to perform protocol processing for the received data link level packets, discard illegal packets, forward legitimate packets to the network-on-chip, perform data error correcting, format conversion and channel mapping for the packets received from the network-on-chip, and send the packets to the corresponding port module. |
| US11343200B2 |
System and method for supporting multi-tenancy in an application server, cloud, or other environment
In accordance with an embodiment, described herein is a system and method for supporting multi-tenancy in an application server, cloud, on-premise, or other environment, which enables categories of components and configurations to be associated with particular application instances or partitions. Resource group templates define, at a domain level, collections of deployable resources that can be referenced from resource groups. Each resource group is a named, fully-qualified collection of deployable resources that can reference a resource group template. A partition provides an administrative and runtime subdivision of the domain, and contains one or more resource groups. Each resource group can reference a resource group template, to bind deployable resources to partition-specific values, for use by the referencing partition. A tenant of the application server or cloud environment can be associated with a partition, or applications deployed therein, for use by that tenant. |
| US11343199B2 |
Resource reservation management device and resource reservation management method
[Problem] When a resource reserved in a resource sharing system become unavailable, the reservation is efficiently reset.[Solution] A resource sharing system 10 shares resources 30 with a plurality of users 20 (user terminals). A resource reservation management device 42 includes: a reservation setting unit 402 that accepts a reservation request for the resource 30 from the user 20, and sets a reservation on a predetermined resource 30 in the resource sharing system 10; and a reservation changing unit 404 that resets the reservation to another resource 30 in the resource sharing system 10 in case the predetermined reserved resource 30 becomes unavailable. if the other resource 30 has insufficient resource capacity, the reservation changing unit 404 resets the reservation to the other resource 30 based on a reservation changing policy defining which reservation is preferentially reset out of the reservation to be reset. |
| US11343198B2 |
Reliable, out-of-order transmission of packets
Provided are systems and methods for reliable, out-of-order transmission of packets. In some implementations, provided is an apparatus configured to communicate with a network and a host device. The apparatus may receive messages from the host device at a send queue, where each message includes destination information. The apparatus may further determine, using the destination information and an identify of the send queue, a transport context associated with a destination on the network. The apparatus may further, for each message and using the transport context, generate a packet including the message and transmit the packet over the network. The apparatus may further monitor status for each transmitted packet. |
| US11343196B2 |
Packet relaying apparatus and packet relaying method
A packet processing apparatus sets, for each TS as a gate state of each of a first gate and a second gate, a priority state, a normal state, and a mixed state and sets a predetermined TS associated with a cyclic pattern of the first packet to the priority or the mixed state. The apparatus allocates, when an amount of output delay of the first packet that is in the mixed state in the predetermined TS is within an allowable amount, the first packet and the second packet to the predetermined TS. The apparatus sets output timing of the first packet allocated in the predetermined TS to the priority state and sets output timing of the second packet allocated in the predetermined TS to the normal state. |
| US11343194B1 |
Communication device and data collection system
A communication device and a data collection system that, when lower connection devices are connected to a communication device, improve efficiency of communication between the communication device and an upper connection device. There is an acquirer that acquires data from the lower connection devices, and a transmission setter that sets a transmission period, which is a time interval in which the data acquired by the acquirer from the lower connection devices is compiled and the compiled data is transmitted to the upper connection device as transmission data, to be equal to or longer than a communication period that is the longest among communication periods of the lower connection devices. Further, there is a transmitter that transmits the transmission data to the upper connection device with the transmission period that is set by the transmission setter. |
| US11343188B2 |
Systems and methods for maintaining consistency between interfaces of locally sourced packets
In one embodiment, a method includes performing, by a router, a destination address lookup of an IP packet in a Forwarding Information Base (FIB) and identifying, by the router, an equal cost multi-path (ECMP) object from the destination address lookup. The ECMP object includes a plurality of paths for forwarding the IP packet to a destination associated with a destination address. The method further includes determining, by the router, a source interface associated with the IP packet, determining, by the router, that the source interface matches an egress interface associated with a path among the plurality of paths, and communicating, by the router, the IP packet based on the path to the destination using the egress interface. |
| US11343180B2 |
Network service access and data routing based on assigned context
The present technology discloses methods, systems, and non-transitory computer-readable media for defining, for a network primitive in a network domain, whether the network primitive can receive data carrying an assigned context associated from one or more source nodes through a software-defined wide area network (SDWAN) fabric overlay; advertising a capability of the network primitive, the capability stating whether the network primitive can receive the data carrying the assigned context; and controlling selective transmission of the data carrying the assigned context from the one or more source nodes to the network primitive through the SDWAN fabric overlay based on the capability of the network primitive to receive the data carrying the assigned context. |
| US11343175B2 |
Packet forwarding
The present disclosure relates to packet forwarding including: determining, according to a forwarding table, an outgoing interface aggregation group corresponding to an incoming interface having received a packet, wherein the forwarding table indicating a relationship between the incoming interface and the outgoing interface aggregation group; selecting, when the outgoing interface aggregation group includes at least one outgoing interface which belongs to the same NUMA node as the incoming interface, a first outgoing interface for sending the packet from the at least one outgoing interface, wherein the NUMA node being non-uniform memory access architecture node; and sending the packet through the first outgoing interface. |
| US11343171B2 |
Using a flappiness metric to limit traffic disruption in wide area networks
In one embodiment, a device in a network obtains tunnel flappiness metrics associated with a particular tunnel in the network exhibiting flapping. The device makes, based on the tunnel flappiness metrics, a prediction that the particular tunnel is going to flap. The prediction is made using a machine learning model. The device proactively reroutes, based on the prediction, traffic from the particular tunnel onto an alternate tunnel, prior to the particular tunnel flapping. The device evaluates performance of the alternate tunnel, after proactively rerouting the traffic from the particular tunnel onto the alternate tunnel. |
| US11343170B2 |
Repeater for packet transmitting in mesh network
A repeater configured to be connected to a network is provided. The repeater includes an uplink wireless transmission interface, a downlink wireless transmission interface, and a processing unit. The uplink wireless transmission interface is configured to establish an external wireless connection with the network. The downlink wireless transmission interface is configured to perform data transmission with the uplink wireless transmission interface and has an external wireless transmission function. The processing unit is configured to turn off the external wireless transmission function of the downlink wireless transmission interface when the connection between the uplink wireless transmission interface and the network is disconnected. |
| US11343169B2 |
Duplicating PDCP PDUs for a radio bearer
For duplicating PDCP PDUs for a radio bearer, methods, apparatus, and systems are disclosed. One apparatus includes a processor and a transceiver for communicating with a network. The processor establishes a radio bearer to communicate with the network, the radio bearer including a PDCP entity, first and second RLC entities associated with said PDCP entity, and first and second logical channels associated with said first and second RLC entities, respectively. The processor receives a control signal from the network and submits a PDCP data PDU in the PDCP entity to the first RLC entity for transmission. In response to the first control signal, the processor submits the PDCP data PDU to the second RLC entity for transmission. The processor indicates to one of the first and second RLC entities to discard a duplicate PDCP data PDU corresponding to a successfully delivered PDCP data PDU. |
| US11343165B1 |
Method, apparatus and computer program product for improving dynamic retry of resource service
Methods, apparatuses and computer program products for implementing dynamic retry of a resource service in a network system are provided. An example method may include: transmitting a first service request to the resource service, determining a first service availability indicator, calculating a first service availability estimate associated with the resource service based on the first service availability indicator, and determining whether to transmit a second service request based on the first service availability estimate. The example method may be repeated by an example apparatus continuously for each transmitted service request. |
| US11343161B2 |
Intelligent distributed multi-site application placement across hybrid infrastructure
A method of deploying a network service across multiple data centers, each having a cloud management server running a cloud computing management software to provision virtual infrastructure resources thereof for a first tenant among a plurality of tenants, includes maintaining for each data center static inventory data that indicate virtual infrastructure resources that are available thereat to the first tenant, identifying, in response to a network service request for the first tenant, a virtual network function associated with the network service, generating commands to deploy the virtual network function based on a descriptor of the virtual network function, selecting one of the data centers in which the virtual network function is to be deployed based on the descriptor of the virtual network function and the static inventory data of each data center, and issuing the commands to the selected data center to deploy the virtual network function. |
| US11343159B2 |
Policy declarations for cloud management system
Methods, apparatus, systems and articles of manufacture are disclosed related to policy declarations for cloud management system. An example computer readable storage device includes instructions that, when executed, cause processor circuitry to at least identify a proposed change to a state of a network. The example instructions, when executed, also cause the processor circuitry to, in response to identifying the proposed change, determine whether the proposed change will cause the state of the network to violate a policy, the policy including a query plan describing characteristics to evaluate the proposed change. In some examples, the instructions, when executed, cause the processor circuitry to, when the proposed change will cause the state of the network to violate the policy, execute an application programming interface call to a cloud service provider to cause the cloud service provider to prevent violation of the policy by executing an action associated with the proposed change. |
| US11343156B2 |
Compute intensive stream processing with context data routing
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for routing events of an event stream in a stream processing system. One of the methods includes receiving, by a router, an event stream of events; identifying, for each event, by the router, a respective partition of context data that includes context data related to the event and providing the event to a respective local modeler that stores the partition of context data identified for the event in operational memory of the local modeler; processing, by each local modeler, events received from the router and aggregating information associated with each event to generate aggregated information; providing, by one or more of the local modelers, to a central modeler, the respective aggregated information; and determining, by the central modeler, a plurality of parameters of a machine learning model using the received aggregated information. |
| US11343149B2 |
Self-training classification
Systems, methods, and related technologies for self-training classification are described. In certain aspects, a plurality of device classification methods with associated models are accessed. Each of the classification methods have an associated reliability level. The models of classification methods with a higher reliability level than other classifications methods are used to train the models associated with lower reliability level. The trained models and associated classification methods are thus improved. |
| US11343147B2 |
Methods, systems, articles of manufacture and apparatus to coordinate a node level adaptation
Methods, apparatus, systems and articles of manufacture are disclosed to coordinate node level adaptations. An example apparatus includes an adaptation support determiner to determine if an adaptation in an adaptation message is supported by a first device, an extractor to, in response to the determination that the adaptation in the adaptation message is supported by the first device, calculate a start-time for the first device based on (a) a transit duration of the adaptation message, (b) an execution duration of the adaptation in the adaptation message, and (c) a timestamp of when the second device sent the adaptation message, and an initiate a timer value for the first device and the second device, the timer value being a function of the start-time. The example apparatus further includes an installer to, in response to the timer value satisfying a threshold, execute the adaptation to reduce disruptions in the CPS. |
| US11343144B2 |
Downlink performance optimizations in wireless networks
Techniques for wireless optimizations are provided. A first set of values for a set of network benchmarks is received from a sensor device, where the set of network benchmarks define network performance dimensions, and include a number of retries needed to successfully transmit data. A second set of values for the set of network benchmarks is received from a wireless access point. The first set of values is mapped against the second set of values in an n-dimensional space, and an outlier dimension is identified, based on analyzing the mapped first and second sets of values. The wireless access point is then reconfigured, based on the identified outlier dimension. |
| US11343143B2 |
Using a flow database to automatically configure network traffic visibility systems
A method for configuring a network monitoring device is provided. A plurality of flow records is received. The plurality of flow records is analyzed according to user-specified criteria to identify one or more network traffic patterns. A plurality of network entities associated with the one or more identified network traffic patterns is identified. A managed object including the identified plurality of network entities is generated. |
| US11343140B2 |
Methods and apparatus to scale application deployments in cloud computing environments
An example apparatus includes a deployment monitor to initiate a modification of a number of virtual machines deployed in the computing environment. The virtual machines including a first virtual machine to execute a first component of an application deployed in the computing environment. A dependents identifier is to identify an information dependency of a second virtual machine on information from the first virtual machine. The second virtual machine is to execute a second component of the application. An updater is to update the information dependency based on a scaling status of the first virtual machine. The information dependency in the configuration information including a reference to the first virtual machine. |
| US11343139B2 |
Device provisioning using a supplemental cryptographic identity
A device provisioning service provisions a network-connected device to access one or more service systems using a supplemental cryptographic identity of the network-connected device. An initial enrollment record (associated with an initial cryptographic identity) and a supplemental enrollment record are stored in a device provisioning service. An identity issuance request is received from the network-connected device at the device provisioning service. The identity issuance request includes the initial cryptographic identity. The supplemental cryptographic identity is requested from a supplemental cryptographic identity issuer identified in the initial enrollment record based on the identity issuance request. The requested supplemental cryptographic identity is received at the device provisioning service from the supplemental cryptographic identity issuer. The network-connected device is provisioned to access the one or more service systems according to the supplemental enrollment record. The supplemental cryptographic identity is communicated to the network-connected device. |
| US11343133B2 |
Virtual SNMP trap receiver
A virtualized trap receiver that virtualizes Simple Network Management Protocol (SNMP) agents and trap receivers over a set of virtual machines is provided. The virtualized trap receiver receives trap messages regarding a particular application running on one or more application servers. The virtualized trap receiver processes the received trap messages at one or more virtual machines. The virtualized trap receiver responds to a query by a network manager regarding an operation of the particular application on the application servers based on the processed trap messages. |
| US11343132B2 |
Radio transmission device, radio reception device, radio communication device, radio communication system, radio transmission method, control circuit, and recording medium
A radio transmission device includes: a known signal generating unit that generates a first known signal and a second known signal mapped in such a manner that subcarriers for transmitting a first signal not being 0 do not overlap with each other in symbols of one time band; an IDFT unit that converts the first known signal and the second known signal from a frequency domain signal into a time domain signal; a GI inserting unit that inserts a guard interval into the first known signal and the second known signal converted into time domain signals; a transmission antenna that transmits the first known signal in which the guard interval is inserted; and a transmission antenna that transmits the second known signal in which the guard interval is inserted. |
| US11343130B2 |
Apparatus and method for sending and receiving broadcast signals
A broadcast signal receiver includes a tuner for tuning a broadcast signal, a reference signal detector for detecting pilots from the tuned broadcast signal, a de-framer for de-framing a signal frame of the broadcast signal and deriving service data based on a number of carriers of the signal frame, and a decoder for performing error correction process on the derived service data. |
| US11343125B2 |
Multiplexer with embedded equalization
There is provided a method including receiving, by a multiplexer, input signals having a first rate, applying, by an equalizer in the multiplexer, equalization on the input signals passed through respective signal paths in the multiplexer, and outputting, by the multiplexer, an output signal comprising a selected signal of equalized versions of the input signals produced by the equalization, the output signal having a second rate greater than the first rate. There is further provided a device that includes a multiplexer and a signal driver having an input connected to the output of the equalizer. The multiplexer includes a plurality of inputs to receive respective input signals, an output to provide an output signal selected from among the input signals, and an equalizer to apply equalization on the input signals that are passed through the multiplexer, the equalization to provide the selected signals as equalized signals at the output of the multiplexer. |
| US11343119B2 |
Distributed control system and communication control method therefor
In the present invention, device information is collected while real-time performance and high-speed performance of control-related normal communication are maintained. The distributed control system has: a central processing device; a central communication device; multiple terminal communication devices each having at least one controlled device connected thereto; an information storage device; and a network having a tree structure comprising multiple communication paths between the central communication device and the terminal communication devices, between the terminal communication devices, and between the terminal communication devices and the information storage device. The network is provided with a first communication path for connecting the upstream-side communication port of a terminal communication device with the downstream-side communication port of a terminal communication device and for connecting the upstream-side communication port of a terminal communication device with the normal communication port of the central communication device; and a second communication path for connecting between the downstream-side communication ports of terminal communication devices positioned at edges of the network and for connecting the downstream-side communication ports of the terminal communication devices with the device information communication port of the information storage device. |
| US11343114B2 |
Group management in a messaging service
A messaging system may receive a plurality of messages in a first conversation among a plurality of conversations. It may be determined that a first message in the first conversation comprises information identifying a first group and authorizing the first group to participate in the first conversation. An association between the first group and the first conversation may be stored in at least one database. Data associated with the first group comprising information identifying a plurality of users in the first group may be retrieved from the at least one database. At least a subset of the first conversation may be sent to a plurality of messaging applications associated with the plurality of users based on the retrieved data. |
| US11343112B2 |
Multicast transfer system and multicast transfer method
Implementations are directed to performing path switching quickly and efficiently when path switching is required in a multicast transfer system. In a multicast transfer system, a multicast group for transmitting the same packet from a sender (transmitting apparatus) to a plurality of receivers (receiving apparatuses) is formed. A transfer apparatus holds transfer destination data in which a group identifier for identifying a multicast group is associated with copy transfer destination information (multicast segment) for specifying another transfer apparatus to be used as a packet transfer destination when the packet is received. In copy transfer destination information, a plurality of other transfer apparatuses can be registered by adding a priority, and a plurality of group identifiers can be associated with a single piece of copy transfer destination information. |
| US11343110B2 |
Phantom object reporting in a power-and-ground router
A method to report a phantom object for a structure in a power-and-ground (PG) router is disclosed. The method includes generating the structure of a PG network based on a spec received as input, identifying a violation of a design rule for the structure, and changing the structure to remove the violation of the design rule. The method further includes generating a report of the violation and the changing, generating a phantom object based on the changing, and outputting the report and the phantom object. |
| US11343108B2 |
Generation of composite private keys
A system and method for the generation of composite private keys are provided. First and second bitstreams are retrieved from an addressable cryptographic table by deriving addresses in the addressable cryptographic table from an initial instruction, accessing first and second bit values stored at addresses belonging to the derived addresses in the addressable cryptographic table, and outputting the first bit values as the first bitstream and the second bit values as the second bitstream. The first bitstream is concatenated with data from the first bitstream to form a data stream having a desired length and the second bitstream is concatenated with data from the second bitstream to form a selector stream having the desired length. A first composite encryption key having a length longer than the first and second bitstreams is formed by selecting values of the data stream identified by corresponding bit values of the selector stream. |
| US11343106B2 |
Systems and methods for accelerated certificate provisioning
Embodiments described herein provide systems and methods to prevent, or provide a countermeasure, to a co-existence attack, for example, that may occur in a Security Credential Management System (SCMS) where both regular butterfly key (RBK) protocol and unified butterfly key (UBK) protocol are supported. Embodiments described herein provide, support, employ, or implement hardware acceleration for a Hardware Security Module (HSM), for example, for cryptographic operations (e.g., block ciphers, digital signature schemes, and key exchange protocols). |
| US11343097B2 |
Dynamic segmentation of network traffic by use of pre-shared keys
Dynamic segmentation of network traffic through the use of Pre-Shared Keys (PSKs). Each defined network segment uses a different pre-shared key and a message authentication code (MAC)-signing algorithm to sign data packets with segment-specific MACs. As such, only those computer hosts/nodes that are in the network segment (i.e., have been assigned the same pre-shared key for generating and decoding the MAC signed data packets) are capable or reading the segment's network traffic. By implementing segment-specific MAC signed data packets, the present invention allows for confidential data transmission absent the need to encrypt the actual contents/data being transmitted. |
| US11343096B2 |
System, method, and computer program product for performing hardware-backed password-based authentication
A system, method, and computer program product are provided for performing hardware-backed password-based authentication. In operation, a system receives a request to access software utilizing password-based authentication. Further, the system receives a password for the password-based authentication. The system computes a hash utilizing the password and a hardware-based authenticator associated with hardware of the system. Moreover, the system verifies that the hash computed utilizing the password and the hardware-based authenticator is correct for accessing the software. |
| US11343095B2 |
Cryplet binding key graph
The disclosed technology is generally directed to secure transactions. In one example of the technology, a first enclave to be used for executing a cryptlet binary of a first cryptlet is identified. The first enclave may be a secure execution environment that stores an enclave private key, and the first cryptlet may be associated with at least a first counterparty. A cryptlet binding that is associated with the first cryptlet may be generated, and may include counterparty information that is associated with at least the first counterparty. Cryptlet binding information may be provided to a cryptlet binding key graph, and a location of a first hardware security module (HSM) that stores a key that is associated with the first counterparty may be received from the cryptlet binding key graph. |
| US11343090B2 |
Device ID for memory protection
There is disclosed in one example a computing system, including: a processor; a memory; and a memory encryption engine (MEE) including circuitry and logic to: allocate a protected isolated memory region (IMR); encrypt the protected IMR; set an access control policy to allow access to the IMR by a device identified by a device identifier; and upon receiving a memory access request directed to the IMR, enforce the access control policy. |
| US11343078B2 |
System and method for secure input at a remote service
A method and system for secure input at a remote service are provided. In a method conducted at a secure input device, a hash operation is performed on a data structure including shared data, the shared data having been obtained from a remote service via an encrypted payload. User input for secure entry at the remote service is received and encoded by performing an operation on corresponding symbols of the user input and an output of the hash operation to output an encoded message, the user input and the encoded message having the same length. The encoded message is output for entry at the remote service. |
| US11343076B2 |
Method and apparatus for determining a propagation delay and/or a distance between multiple transceivers, particularly for a vehicle-entry and/or starting system
A method and apparatus for determining a propagation delay and/or a distance between a plurality of transceivers, in particular between transceivers outside and/or as part of a motor vehicle, wherein the transceivers are each designed: to generate identical codes in a plurality of these transceivers, using a calculation method known to them, from at least one starting value transmitted, in particular, from one of the transceivers to the further transceivers, to transmit one or more messages from at least one of the transceivers to one or more further ones of the transceivers, which messages each contain at least one of the codes, to determine at least one propagation delay and/or at least one distance between at least two of the transceivers, in particular from the propagation delay and/or transmission times of the one or more messages. |
| US11343073B2 |
Apparatus and method for achieving distributed consensus based on decentralized byzantine fault tolerance
Disclosed herein are an apparatus and method for achieving distributed consensus based on decentralized Byzantine fault tolerance. The apparatus may include one or more processors and an execution memory for storing at least one program that is executed by the one or more processors, wherein the program is configured to receive delegate request messages, each including a first transaction for requesting distributed consensus proposed by a client, and determine congress candidate nodes forming a consensus quorum, to be consensus nodes based on the delegate request messages, generate a prepare message that includes a second transaction for obtaining consent to results of determination of the consensus nodes, and send the prepare message to the consensus nodes, and receive commit messages, each including an electronic signature of a corresponding consensus node, from the respective consensus nodes, and broadcast a reply message indicative of results of verification of the electronic signatures. |
| US11343068B2 |
Secure multi-party learning and inferring insights based on encrypted data
Respective sets of homomorphically encrypted training data are received from multiple users, each encrypted by a key of a respective user. The respective sets are provided to a combined machine learning model to determine corresponding locally learned outputs, each in an FHE domain of one of the users. Conversion is coordinated of the locally learned outputs in the FHE domains into an MFHE domain, where each converted locally learned output is encrypted by all of the users. The converted locally learned outputs are aggregated into a converted composite output in the MFHE domain. A conversion is coordinated of the converted composite output in the MFHE domain into the FHE domains of the corresponding users, where each converted decrypted composite output is encrypted by only a respective one of the users. The combined machine learning model is updated based on the converted composite outputs. The model may be used for inferencing. |
| US11343063B2 |
User terminal and radio communication method
A user terminal is disclosed including a transmitting/receiving section that performs transmission and reception by Time Division Duplex (TDD) by using a DL/UL frequency band pair that has a UL frequency band and a DL frequency band configured in a frequency direction in a carrier; and a control section that performs control to switch between a first DL/UL frequency band pair and a second DL/UL frequency band pair, and performs the transmission and the reception. In another aspect, a radio communication method of a user terminal is also disclosed. |
| US11343061B2 |
Ethernet transceiver with PHY-level signal-loss detector
An Ethernet transceiver includes physical-layer (PHY) circuitry and a signal-loss detector. The PHY circuitry is configured to receive a signal from a peer transceiver, to process the received signal in a series of digital PHY-level processing operations, and to output the processed signal for Medium Access Control (MAC) processing. The signal-loss detector is configured to receive, from the PHY circuitry, a digital version of the received signal, and to detect a signal-loss event based on an amplitude of the digital version of the received signal. |
| US11343060B2 |
Zero division duplexing mimo radio with adaptable RF and/or baseband cancellation
An intelligent backhaul radio is disclosed, which can operate by zero division duplexing for use in PTP or PMP topologies, providing for significant spectrum usage benefits among other benefits. Specific system architectures and structures to enable active cancellation of multiple transmit signals at multiple receivers within a MIMO radio are disclosed. Further disclosed aspects include the adaptive optimization of cancellation parameters or coefficients. |
| US11343057B2 |
Transmission of phase tracking reference signals (PT-RS) for bandwidth parts
Technology for a user equipment (UE) operable to decode a resource mapping pattern of a phase tracking reference signal (PT-RS) received from a base station in a wireless network is disclosed. The UE can decode control signaling received in a downlink from the base station. The control signaling can indicate a resource mapping pattern for a PT-RS. The UE can identify the resource mapping pattern for the PT-RS based on the control signaling received from the base station. The UE can encode one or more PT-RS for transmission to the base station in an uplink in accordance with the resource mapping pattern for the PT-RS. |
| US11343056B2 |
Data transmission method, sending device, and receiving device
Embodiments of this application provide example data transmission methods. One example method includes: receiving, by a receiving device, first data on a first time-frequency resource, and receiving second data on a second time-frequency resource. When the first time-frequency resource and the second time-frequency resource have an overlapped target frequency domain resource in frequency domain, the receiving device can then use a first DMRS mapped to a target frequency domain resource of the first time-frequency resource to demodulate the second data mapped to a target frequency domain resource of the second time-frequency resource. |
| US11343051B2 |
Integrated circuit for controlling radio communication
Provided is a radio communication device which can prevent interference between SRS and PUCCH when the PUCCH transmission bandwidth fluctuates and suppress degradation of CQI estimation accuracy by the band where no SRS is transmitted. The device includes: an SRS code generation unit (201) which generates an SRS (Sounding Reference Signal) for measuring uplink line data channel quality; an SRS arrangement unit (202) which frequency-multiplexes the SRS on the SR transmission band and arranges it; and an SRS arrangement control unit (208) which controls SRS frequency multiplex so as to be uniform in frequency without modifying the bandwidth of one SRS multiplex unit in accordance with the fluctuation of the reference signal transmission bandwidth according to the SRS arrangement information transmitted from the base station and furthermore controls the transmission interval of the frequency-multiplexed SRS. |
| US11343050B2 |
Wireless communication apparatus
A data unit that requires a receipt acknowledgement response in a plurality of transmitted data units is suitably selected.A wireless communication apparatus includes a control unit. The control unit controls transmission of receipt acknowledgement requests for a plurality of transmitted data units. Further, the receipt acknowledgement request whose transmission is controlled by the control unit is a receipt acknowledgement request including information, the information identifying a data unit that requires a receipt acknowledgement response in the plurality of transmitted data units and specifying the identified data unit. |
| US11343038B2 |
Electronic device, wireless communication method and computer readable medium
The present disclosure relates to an electronic device, a wireless communication method, and a computer readable medium. The electronic device includes a processing circuitry. The processing circuitry is configured to generate a discovery reference signal for an unlicensed band. The discovery reference signal contains a primary synchronization signal, a secondary synchronization signal and a channel state information reference signal. |
| US11343032B2 |
Frequency spreading for high-performance communications
Methods and systems are provided for using frequency spreading during communications, in particular communications in which multiple carriers (or subcarriers) are used. The frequency spreading may comprise generating a plurality of spreading data vectors based on transmit data, such as by application of a spreading matrix to portions of the transmit data. Each spreading data vector may comprise a plurality of elements, for assignment to the multiple subcarriers. The receive-side device may then apply frequency de-spreading, to obtain the original transmit data. The frequency de-spreading may comprise use of the same spreading matrix on data extracted from received signals, which (the data) may correspond to the plurality of spreading data vectors. |
| US11343028B2 |
Method whereby terminal transmits ACK/NACK in wireless communication system, and device therefor
Provided are a method whereby a terminal transmits an acknowledgement/not-acknowledgement (ACK/NACK) with a primary cell and a secondary cell aggregated, and a device for supporting the method. The method comprises: receiving data by a downlink subframe of a secondary cell; and transmitting an ACK/NACK for the data by an uplink subframe of a primary cell, wherein: the time interval between the downlink subframe and the uplink subframe is determined by a first hybrid automatic repeat request (HARQ) timing or a second HARQ timing; the first HARQ timing is an HARQ timing which is applied when the primary cell is used alone; and the second HARQ timing is an HARQ timing which is additional to the first HARQ timing. |
| US11343027B2 |
Method for mapping physical hybrid automatic repeat request indicator channel
A method for mapping a physical hybrid automatic repeat request indicator channel (PHICH) is described. The method for mapping a PHICH includes determining an index of a resource element group transmitting a repetitive pattern of the PHICH, according to a ratio of the number of available resource element groups in a symbol in which the PHICH is transmitted and the number of available resource element groups in a first or second OFDM symbol, and mapping the PHICH to the symbol according to the determined index. In transmitting the PHICH, since efficient mapping is performed considering available resource elements varying with OFDM symbols, repetition of the PHICH does not generate interference between neighbor cell IDs and performance is improved. |
| US11343025B2 |
Chain broadcasting in vehicle-to-everything (V2X) communications
The subject matter described herein is directed towards a technology that increases the reliability of transmitting information, and extends the coverage of a vehicle-to-everything (V2X) network by propagating received information in a multiple-stage chain communication in a wireless communication system. A transmitting device transmits a communication message with repetition data indicating number of times the communication message is to be retransmitted in the wireless communication system. A receiving device determines from the repetition data that the communication message is intended to be retransmitted, modifies (e.g., decrements) the repetition data, and retransmits the communication message in association with the modified repetition data. |
| US11343020B2 |
Data compression method and device
A radio communication method and device are provided. The method includes: performing a compression processing on uplink control information to be transmitted in a target time unit, wherein the compression processing includes a compression processing performed on Coding Block Group (CBG)-based feedback response information included in the uplink control information; and transmitting the uplink control information after the compression processing in the target time unit. |
| US11343016B2 |
Measurement resource indication method and related device
A measurement resource indication method applied to a communication system supporting various signal measurements includes: receiving, by a user device, first measurement resource indication information from a network device, the first measurement resource indication information being used for indicating that a first signal measurement reuses part or all of measurement resources of a second signal measurement; wherein the second signal measurement is a signal measurement configured with the measurement resources, and the first signal measurement is a signal measurement not configured with any measurement resource. |
| US11343013B2 |
Facilitating outer loop link adaptation in advanced networks
Facilitating facilitate enablement of a smart HARQ feedback to support outer loop link adaptation in advanced networks (e.g., 4G, 5G, 6G, and beyond) is provided herein. Operations of a method can comprise sending, by a first device comprising a processor, a data packet to a second device. The method also can comprise receiving, by the first device, negative acknowledgement data from the second device. The negative acknowledgement data can indicate that the second device fails to support a modulation and coding protocol of the data packet. |
| US11343008B2 |
Extended spectrum TDMA signal switching cable tap box
A method of proprietary TDMA (Time-Division Multiple Access) data modulated signals nonlinear signal splitting (switching) system is disclosed. Said TDMA system operates over distribution CATV infrastructure and in ES (extended spectrum) that is usually allocated above in the frequency band comparing to one defined in the CATV DOCSIS standard. Said system is meant to increase data throughput capacity over existing CATV based systems targeting primarily ES (Extended Spectrum band) by means of TDMA approach. The purpose of the RF switches based tap box is to connect specific device to which TDMA packet is relayed to. This approach reduces excessive losses that are present in standard tap boxes by disconnecting other devices, which are not receiving or sending related TDMA data packets. The described method introduces switch control receiver concept that allows for configuration of various operation modes such as regular switched TDMA, amplified and broadcast modes. |
| US11343007B2 |
Time synchronization method and device
A time synchronization method includes receiving, by a receive-end device, a first timestamp and a first header signal sent by a transmit-end device, where the first timestamp indicates a first moment at which a first channel medium conversion module sends the first header signal, and a second moment at which the receive-end device receives the first header signal. The method further includes sending a second header signal to the transmit-end device, where a third moment at which the receive-end device sends the second header signal. The method further includes receiving a fourth timestamp sent by the transmit-end device, where the fourth timestamp indicates a fourth moment at which the transmit-end device receives the second header signal. The method further includes synchronizing time with the transmit-end device based on the first moment, the second moment, the third moment, and the fourth moment. |
| US11343006B2 |
Methods and apparatus to facilitate local time-based digital audio measurement
Example methods, apparatus, systems and articles of manufacture to facilitate local time-based digital audio measurement are disclosed. Example methods disclosed herein include a hello ping may be received from a media player. The media player may be associated with a location based on the hello ping. The media player may be associated with a time offset based on the location. A configuration file may be generated to include the location and the time offset. The configuration file may be sent to the media player. |
| US11343002B2 |
Apparatus, measurement system for testing an apparatus and methods for operating the same
An apparatus comprises an antenna array comprising a plurality of antennas. The apparatus comprises a communication interface for receiving a control signal. The apparatus is configured to form a first radio frequency beam in accordance with a predetermined test case independent from the control signal using the antenna array. The apparatus is configured to form a second radio frequency beam that is different from the predetermined test case responsive to instructions contained in the control signal. |
| US11342998B2 |
Linearized optical digital-to-analog modulator
In a system for converting digital data into a modulated optical signal, an electrically controllable device having M actuating electrodes provides and optical signal that is modulated in response to binary voltages applied to the actuating electrodes. A digital-to-digital converter provides a mapping of input data words to binary actuation vectors for M bits and supplies the binary actuation vectors as M bits of binary actuation voltages to the M actuating electrodes, where M is larger than the number of bits in each input data word. The digital-to-digital converter maps each digital input data word to a binary actuation vector by selecting a binary actuation vector from a subset of binary actuation vectors available to represent each of the input data words. |
| US11342996B1 |
Methods for capacity provisioning in wide area networks using optical bypassing
Systems and methods are provided for determining an optical bypass for an inter-regional wide area network (WAN) for regions of server facilities of a cloud service provider. In particular, the optical bypass connects non-adjacent regional server centers of the WAN by eliminating needs of data conversions at intermediate regional server centers. The determining the optical bypass includes receiving a WAN topology data, capacity and demand information about the WAN. The determining includes an objective function to maximize a number of network resources to free up by determining a revised data flow and bandwidth allocations by introducing the optical bypass in the WAN. The disclosed technology transmits the determined data traffic flow and resource allocation information of the optical bypass, causing a network traffic enforcers to reconfigure the WAN. |
| US11342993B2 |
Systems, methods, and devices for spur and noise suppressed photonic links
Systems, methods, and devices are disclosed for implementing photonic links. Methods include transmitting light using an optical emitter, splitting, using an input coupler, the light into a first path and a second path, the first path being provided to a modulator, and the second path being provided to a phase shifter, and combining, using an output coupler, an output of the modulator and an output of the phase shifter. Methods further include identifying a modulator phase angle that reduces a third order distortion at an output of the output coupler, applying a first bias voltage to a modulator to maintain the identified modulator phase angle, and applying a control signal to the phase shifter to maintain a phase difference between an output of the modulator and an output of a phase shifter. |
| US11342992B2 |
Visual impairment detector for free-space optical communication systems
Novel tools and techniques are provided for implementing visual impairment detection for free-space optical communication (“FSOC”) systems. In various embodiments, a computing system might receive, either from a camera or from a database, images (and/or videos) of an optical field of view (“FOV”) of the camera, the optical FOV comprising an optical beam(s) of a first FSOC system; might autonomously analyze the captured images (and/or videos) to determine whether an object(s) is moving within proximity to an optical beam(s) of the first FSOC system, to perform at least one of reactive learning or proactive learning regarding potential interruption of the optical beam(s) of the first FSOC system, and/or to determine one or more preventative measures to prevent interruption of the optical beam(s) of the first FSOC system; and might autonomously initiate one or more first tasks and/or the one or more preventative measures, based on the analysis. |
| US11342987B2 |
Satellite edge networks
Systems, apparatuses, methods, and software are described herein that provide enhanced satellite communication nodes. In one example, a parent communication node is configured to establish a satellite edge network over at least a satellite communication pathway with a child communication node remotely located from a geographic location of the parent node. The child communication node is configured to communicate over at least the satellite communication pathway to establish a connection to the satellite edge network and route communications of a local communication interface to the satellite edge network. |
| US11342984B2 |
Wireless device system
A system is described where antenna beam steering techniques are implemented to optimize time and frequency channel resources in wireless communication systems where repeaters are used. Beam steering modes of the antenna systems in the repeaters as well as the nodes are optimized to improve system capacity and load balancing. Client devices in a wireless LAN system can be configured to work as repeaters, with the repeaters containing a beam steering capability. The beam steering capability can be implemented in one or multiple nodes and repeaters in the communication system. |
| US11342980B2 |
Methods and apparatuses for uplink transmission prioritization
A method performed by a UE for Uplink (UL) transmission prioritization is provided. The method includes receiving an RRC message; detecting a beam failure event on an SpCell; and performing operations in response to detecting the beam failure event. The operations include transmitting a preamble to the SpCell; receiving an RAR message from the SpCell; determining whether a first UL resource is enabled for transmission of a BFR report according to whether the first UL resource is indicated by the RAR message and whether the RRC message is configured with an indication; and transmitting the BFR report on the first UL resource after determining that the first UL resource is enabled for the transmission of the BFR report. A UE using the method is also provided. |
| US11342979B2 |
Scalable process for indicating beam selection
Methods, systems, and devices for wireless communication are described. In wireless systems supporting multiple-input, multiple-output (MIMO) transmissions, devices may implement beam-forming to improve reliability of communications. A user equipment (UE) may select a set of beams, and corresponding beam indices, for communication based on reference signals received from a base station. The UE may determine values corresponding to each of the beam indices using a scalable set of tables. For example, the UE may select a subset of the tables based on the number of selected beams, and may determine the values based on these tables. In this way, the UE may efficiently store sets of tables for multiple different configurations. The UE may sum the corresponding values to obtain a combination index value, and may transmit the combination index value to the base station. The base station may determine the selected beams based on this combination index value. |
| US11342969B2 |
Simplified detection for spatial modulation and space-time block coding with antenna selection
Methods and systems that can enable antenna selection (AS) and data bits in transmitted spatially modulated (SM) streams to be detected at a receiver using different detection methods. In example embodiments, encoding for an AS stream is done separately at a transmitter than encoding for data streams, enabling a receiver to use one type of detection for AS bits and a reduced complexity type of MIMO detection for the data bits. |
| US11342968B2 |
Optimized multi-beam antenna array network with an extended radio frequency range
A system, in a radio frequency (RF) transmitter device, dynamically selects one or more reflector devices along a non-line-of-sight (NLOS) radio path based on a defined criteria. Further, the dynamically selected one or more reflector devices are controlled based on one or more conditions. In an RF receiver device, communicates with the dynamically selected one or more reflector devices comprising an active reflector device. The active reflector device comprises at least a first antenna array and a second antenna array. The first antenna array transmits a first set of beams of RF signals to at least the RF transmitter device and the RF receiver device. The second antenna array receives a second set of beams of RF signals from at least the RF transmitter device and the RF receiver device. |
| US11342966B2 |
Information indicating and determining method and apparatus, and computer storage medium
The present application discloses an information indicating and determining method and apparatus, and a computer storage medium, being used for indicating QCL group information of a DMRS port, enabling a terminal to determine the QCL group information of the DMRS port. The embodiments of the present application provide an information indicating method, comprising: determining QCL group information of a demodulation reference signal DMRS port; and notifying a terminal of the QCL group information. |
| US11342956B2 |
Wireless two-way communication in complex media
In an embodiment, a circuit includes a resonant portion, a plurality of switches, a first impedance, an amplifier, and a demodulator. The resonant portion includes a single RF coil and is configured for transmission/reception at about the same frequency. The switches include first, second, and third switches. The first switch includes an input in communication with a power source and an output in communication with ground. The second switch includes an input between the power source and the first switch and an output in communication with a resonant portion input. The third switch includes an input in communication with a resonant portion output and an output in communication with ground. The first impedance is between the resonant portion output and the third switch input. The amplifier includes an input between the first impedance and the third switch input. The demodulator includes an input in communication with the amplifier output. |
| US11342953B2 |
Controller device for a motor vehicle, and motor vehicle
A controller device for a motor vehicle, in particular for an autonomously operable motor vehicle, having a controller for operating the motor vehicle, and a protective device for protecting the controller from electromagnetic interference fields or interfering signals. The protective device has a receiver device for acquiring electromagnetic interference fields or interfering signals, a processing device for providing information about an electromagnetic interference field or interfering signal acquired by the receiver device, and a control unit that evaluates the acquired field and/or interference signal as a function of the acquired information. |
| US11342941B2 |
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 4096-symbol mapping, and bit interleaving method using same
A bit-interleaved coded modulation (BICM) reception device and a BICM reception method are disclosed herein. The BICM reception device includes a demodulator, a bit deinterleaver, and a decoder. The demodulator performs demodulation corresponding to 4096-symbol mapping. The bit deinterleaver performs group-unit deinterleaving on interleaved values. The interleaved values are generated after the demodulation. The decoder restores information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving. The deinterleaved values corresponds to a LDPC codeword having a length of 64800 and a code rate of 3/15. |
| US11342932B2 |
Machine spectral data compression
A data compression process reduces the amount of machine spectral data transmitted over a network while maintaining the details of spectral peaks used for machine health analysis. The data compression process also provides for the calculation of various types of spectral parameters, such as spectral band parameters, with negligible loss of accuracy. |
| US11342925B2 |
Signal generation circuit and method, and digit-to-time conversion circuit and method
A signal generating electric circuit, a signal generating method, a digit-to-time converting electric circuit and a digit-to-time converting method. The signal generating electric circuit includes: a first generating electric circuit configured for, based on a first frequency control word and a reference time unit, generating a periodic first output signal; and a second generating electric circuit configured for, based on a second frequency control word and the reference time unit, generating a periodic second output signal. The first frequency control word includes a first integer part and a first fractional part, the second frequency control word includes a second integer part and a second fractional part, the first integer part is equal to the second integer part, the first fractional part and the second fractional part are not equal, and a period of the first output signal and a period of the second output signal are not equal. |
| US11342923B1 |
Circuit and method for random edge injection locking
A circuit for facilitating random edge injection locking of an oscillator comprises a clock signal and a digitally controlled delay line, where the digitally controlled delay line is configured to delay the clock signal, thereby generating a delayed clock signal. The circuit further comprises an edge selector configured to generate a phase select signal with a random pulse sequence. Moreover, the circuit comprises a pulse generator downstream to the digitally controlled delay line configured to generate injection pulses from the delayed clock signal for at least two phases of the oscillator based on the phase select signal. |
| US11342922B1 |
Direct bi-directional gray code counter
A bi-directional Gray code counter includes a first set of logic circuitry configured to receive an input having a first sequence of bits representing a first value. The first set of logic circuitry is further configured to convert the first sequence of bits to a second sequence of bits representing the first value. The bi-directional Gray code counter further includes a second set of logic circuitry and third second set of logic circuitry. The second set of logic circuitry is configured to compare the second sequence of bits to a bit index pattern. The third set of logic circuitry is configured to transition one bit in the first sequence of bits from a first state to a second state to form a third sequence of bits representing a second value. The one bit is transitioned in response to the second sequence of bits being compared to the bit index pattern. |
| US11342921B1 |
Single flux quantum buffer circuit
A circuit can include a first Josephson junction (JJ), a second JJ, and a third JJ coupled in parallel using superconducting inductors. The first JJ, the second JJ, and the third JJ can be biased using one or more JJ-based current sources. |
| US11342920B1 |
Pulse selector system
One example includes a pulse selector system. The pulse selector system includes an input Josephson transmission line (JTL) configured to propagate an input reciprocal quantum logic (RQL) pulse received at an input based on a bias signal. The RQL pulse includes a fluxon and an antifluxon. The system also includes an escape Josephson junction coupled to an output of the input JTL. The escape Josephson junction can be configured to pass a selected one of the fluxon and the antifluxon of the RQL pulse and to trigger in response to the other of the fluxon and the antifluxon of the RQL pulse to block the other of the fluxon and the antifluxon of the RQL pulse. The system further includes an output JTL configured to propagate the selected one of the fluxon and the antifluxon as a unipolar pulse to an output based on the bias signal. |
| US11342919B1 |
Complementary asynchronous single flux quantum circuits
A single flux quantum (SFQ) cell may include SFQ circuitry to implement a logic function that generates logic values of a set of outputs based on logic values of a set of inputs. The SFQ circuitry may instantaneously update logic values of the set of outputs in response to changes in logic values of the set of inputs. The SFQ circuitry may include at least one SFQ non-destructive set-reset flip-flop. |
| US11342918B2 |
Network-on-chip (NOC) with flexible data width
Techniques described herein may relate to providing a programmable interconnect network (e.g., a programmable network-on-chip (NOC)). A method may include determining a transmission parameter, bonding one or more channels of an interconnect network based at least in part on the transmission parameter, and power-gating any unused channels after the bonding. |
| US11342917B2 |
Electronic control device and circuit reconfiguration method
An electronic control device includes: a logic circuit for reconfiguring a plurality of arithmetic circuits including a first circuit and a second circuit; a reconfiguration controller that reconfigures the arithmetic circuits and checks the reconfigured arithmetic circuits based on reconfiguration commands; and a process controller that transmits the reconfiguration commands to the reconfiguration controller and instructs the arithmetic unit to execute operations, in which when a first reconfiguration command is received, the reconfiguration controller reconfigures and checks the first circuit, when the check of the first circuit by the reconfiguration controller is completed, the process controller instructs the first circuit to execute an operation, the process controller transmits a second reconfiguration command to the reconfiguration controller and instructs the reconfiguration controller to start to reconfigure the second circuit until the execution of a predetermined process of the first circuit is completed after completion of the reconfiguration of the first circuit. |
| US11342914B2 |
Integrated circuit having state machine-driven flops in wrapper chains for device testing
Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output pre-selected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit. |
| US11342913B2 |
Reverse current switch
Provided is a reverse current switch. The reverse current switch includes: a comparison unit including a first input end, a second input end, and a first output end; and a switch resistance unit, where a first end of the switch resistance unit is connected to the first input end, a second end of the switch resistance unit is connected to the second input end, and a third end of the switch resistance unit is connected to the output end of the comparison unit, and the switch resistance unit is controlled by a voltage of the first output end. This reverse current switch has a simple structure and can implement working under low voltage conditions. |
| US11342911B2 |
Gate driver bootstrap circuits and related methods
Gate driver bootstrap circuits and related methods are disclosed. An example gate driver stage includes a first terminal and a second terminal, the first terminal to be coupled to a capacitor, the capacitor and the second terminal to be coupled to a gate terminal of a power transistor, a gate driver coupled to the first terminal and the second terminal, and a bootstrap circuit coupled to the first terminal, the second terminal, and the gate driver, the bootstrap circuit including a control stage circuit having an output and a first transistor having a first gate terminal and a first current terminal, the first gate terminal coupled to the output, the first current terminal coupled to the first terminal. |
| US11342909B2 |
Semiconductor integrated circuit and control method of semiconductor integrated circuit
According to the present embodiment, a semiconductor integrated circuit is a semiconductor integrated circuit that drives a switching element including a first field-effect transistor and a second field-effect transistor connected to the first field-effect transistor in anti-series, and includes a driving circuit and a control circuit. The driving circuit turns on or off the first and second field-effect transistors. The control circuit controls the driving circuit in accordance with a control signal input from one signal input terminal. |
| US11342908B2 |
Method of operating H-bridge circuits and corresponding driver device
An H-bridge circuit includes a supply voltage node, a first pair of transistors and a second pair of transistors. First transistors in each pair have the current paths therethrough included in current flow lines between the supply node and, respectively, a first output node and a second output node. Second transistors in each pair have the current paths therethrough coupled to a third output node and a fourth output node, respectively. The first and third output nodes are mutually isolated from each other and the second and fourth output nodes are mutually isolated from each other. The H-bridge circuit is operable in a selected one of a first, second and third mode. |
| US11342906B2 |
Delay circuits, and related semiconductor devices and methods
Devices for generating a delay output signal are disclosed. A device may include a first delay circuit and a second delay circuit coupled in series between a first node and a second node in a delay path for the device, and having a third node therebetween. The device may also include a third circuit coupled to the third node and configured to charge the third node responsive to detecting a signal has passed through the first node and the third node. Associated semiconductor devices and methods are also disclosed. |
| US11342898B2 |
Band pass filter
Aspects of this disclosure relate to a band pass filter that includes LC resonant circuits coupled to each other by a capacitor. A bridge capacitor can be in parallel with series capacitors, in which the series capacitors include the capacitor coupled between the LC resonant circuits. The bridge capacitor can create a transmission zero at a frequency below the passband of the band pass filter. The LC resonant circuits can each include a surface mount capacitor and a conductive trace of the substrate, and an integrated passive device die can include the capacitor. Band pass filters disclosed herein can be relatively compact, provide relatively good out-of-band rejection, and relatively low loss. |
| US11342895B2 |
Systems and methods for modifying an audio playback
An audio system and method for modifying an audio playback including configuring an audio playback device, the audio playback device comprising a plurality of far-field audio inputs; generating the audio playback via the audio playback device; receiving, via at least one far-field audio input of the plurality of far-field audio inputs, a content-agnostic audio input from a first position within an environment; and, modifying the audio playback in response to the content-agnostic audio input. |
| US11342892B2 |
Amplifier and signal processing circuit
The present technology relates to an amplifier and a signal processing circuit that can reduce deterioration of signal quality. A voltage-to-time converter (VTC) integrates error information included in an output pulse width modulation (PWM) signal that is a PWM signal to be output to an outside of a device, so as to convert the error information into error time information. A delay unit generates a plurality of delayed signals using an input PWM signal that is a PWM signal input from the outside of the device. A signal selection unit selects a delayed signal according to the error time information from the plurality of delayed signals and outputs the output PWM signal. The present disclosure can be applied to, for example, an audio player. |
| US11342891B2 |
Amplifier circuit
An amplifier circuit (1) includes a FET (10) having a source terminal (S1), a drain terminal (D1), and a gate terminal (G1), a FET (20) having a source terminal (S2), a drain terminal (D2), and a gate terminal (G2) and coupled in parallel with the FET (10), a FET (30) having a source terminal (S3) coupled to the drain terminals (D1 and D2), a drain terminal (D3), and a gate terminal (G3) and cascoded with the FETs (10 and 20), and feedback circuits (21 and 22) configured to feed back to the gate terminal (G2) a high frequency signal outputted from the source terminal (S2) or the drain terminal (D2). |
| US11342890B2 |
Reducing supply to ground current
An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator. |
| US11342889B2 |
Power amplifier system
A power amplifier system is disclosed that includes a power amplifier having a first signal input, a first signal output, second signal input, and a second signal output. The power amplifier system further includes cross-coupled bias circuitry having a first transistor with a first collector coupled to the first signal input, a first base coupled to the second signal input, and a first emitter coupled to a fixed voltage node, a second transistor with a second collector coupled to the second signal input, a second base coupled to the first signal input, and a second emitter coupled to the fixed voltage node. |
| US11342884B2 |
Crystal oscillator and phase noise reduction method thereof
A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a bias circuit coupled to an output terminal of the crystal oscillator core circuit, a pulse wave buffer coupled to the output terminal of the crystal oscillator core circuit, and a phase noise reduction circuit coupled to the output terminal of the crystal oscillator core circuit. The crystal oscillator core circuit may generate a sinusoidal wave. The bias circuit may provide a bias voltage of the sinusoidal wave. The pulse wave buffer may generate a pulse wave according to the sinusoidal wave. The phase noise reduction circuit may generate a reset signal including at least one reset pulse for resetting the bias voltage. In addition, the reset signal is generated without calibrating the at least one reset pulse to a zero-crossing point of the sinusoidal wave. |
| US11342881B2 |
Systems and methods for controlling fan motors with variable frequency drives
A fan assembly is provided. The fan assembly includes a fan, a motor that is coupled to the fan, and a variable frequency drive (VFD) that is coupled to the motor. The motor includes a maximum rated speed that is greater than a maximum structural speed limit of the fan, and the VFD includes a current output limit configured to limit an operational speed of the motor to be less than or equal to the maximum structural speed limit of the fan. |
| US11342866B2 |
Method for operating a pressure control device, and pressure control device for carrying out the method
A method for operating a pressure control device in a vehicle, in particular in a motor vehicle, wherein current is supplied by an energy source of the vehicle for operating the pressure control device, as a result of which the pressure control device carries out at least one pressure control function, for which at least two actuators of the pressure control device are actuated, wherein at least one current required at maximum for actuating the actuator is determined for each actuator and current budget management for actuating the actuators and/or for carrying out the pressure control functions is performed by the determined currents required at maximum. In addition, the invention relates to a pressure control device for carrying out the method. |
| US11342856B2 |
Power converter controller with stability compensation
A switched mode power converter has an energy transfer element that delivers an output signal to a load. A power switching device coupled to the primary side of the energy transfer element regulates a transfer of energy to the load. A secondary controller is coupled to receive a feedback signal and output a pulsed signal in response thereto. A primary controller is coupled to receive the pulsed signal and output a drive signal in response thereto, the drive signal being coupled to control switching of the power switching device. A compensation circuit generates an adaptively compensated signal synchronous with the pulsed signal. The adaptively compensated signal has a parameter that is adaptively adjusted in response to a comparison of the feedback signal with a threshold reference signal. The parameter converges towards a final value that produces a desired level of the output signal. |
| US11342845B2 |
Method for switching a bi-directional voltage converter
Various embodiments include a method for operating a bidirectional voltage converter with an input-side half-bridge, an output-side half-bridge, and a bridge branch having a bridge inductance, comprising: determining an actual mean bridge current value flowing through the bridge branch during a respective subsequent switching cycle T1 of the transistor switches in a respective current switching cycle T0; determining switch-on time points and switch-on durations of the respective transistor switches for the respective subsequent switching cycle T1; and switching on the respective transistor switches at the respective ascertained switch-on time points and for the respective ascertained switch-on durations in the respective subsequent switching cycle T1. |
| US11342842B2 |
Pulse frequency modulation and frequency avoidance method and implementation for switching regulators
Embodiments relate to a switching regulator having a dual mode control. The switching regulator includes an error amplifier configured to receive an output voltage of a power source, and to generate an error voltage based on a difference between the output voltage of the power source and a reference voltage. The switching regulator additionally includes a PFM controller configured to receive the error voltage from the error amplifier, and to generate a clock signal having a switching frequency based on a difference between the error voltage and a modulation voltage. Moreover, the switching regulator includes a PWM controller configured to receive the clock signal and an error signal determined based on a load current sensed at an output of the power source, and to generate a control signal to control the power source. |
| US11342841B2 |
Method for controlling resonance-type power converter, resonance-type power converter, and DC-DC converter
The present disclosure includes by controlling at least either one of a switching frequency of a switching element (S) or a duty ratio indicating an ON period of the switching element, securing delay time from voltage at both ends of the switching element reaches zero voltage by resonance of the resonant circuit (L0, C0) in an OFF state of the switching element until the switching element is turned on, and turning on the switching element within the delay time. |
| US11342840B2 |
Switching device and leakage current control method
A switching device includes a first switch and a threshold voltage adjustment circuitry. The first switch is configured to be selectively turned on according to an enable signal, in order to connect a first pin to a second pin. The threshold voltage adjustment circuitry is configured to adjust a voltage level of a bulk terminal of the first switch according to the enable signal and a voltage provided from a power source. In response to the voltage being de-asserted, the threshold voltage adjustment circuitry is further configured to cut off a signal path between the bulk terminal and the power source. |
| US11342837B2 |
Short-circuit determination device and switching power supply device
A short-circuit determination device is provided in a switching power supply device. The switching power supply device converts a power supply voltage applied between an upper power supply line and a lower power supply line and outputs the power supply voltage to a load through an intermediate node. The switching power supply device includes a plurality of upper switching elements and a lower switching element. Each of the plurality of upper switching elements has an electrical conduction terminal and a control terminal. The electrical conduction terminals are connected in series between the upper power supply line and the intermediate node. The control terminals are driven at a same level as each other. The lower switching element has an electrical conduction terminal connected between the lower power supply line and the intermediate node. The lower switching element and the plurality of upper switching elements are connected in series. |
| US11342836B2 |
Overvoltage protection for active clamp flyback converter
An apparatus including: a switching converter having a main switch configured to provide power to a transformer, an auxiliary switch configured to provide a release path for leakage inductance energy of the transformer, and a clamp capacitor coupled in series with the auxiliary switch; and a control circuit configured to control the main switch to be off and the auxiliary switch to operate to discharge the clamp capacitor when in an over-voltage protection mode. A method of controlling the switching converter can include: controlling the main switch to be off; and controlling the auxiliary switch to operate to discharge the clamp capacitor when in an over-voltage protection mode. |
| US11342834B2 |
Multi-mode working control method for AC-DC power supply
The present disclosure provides a control method for an AC-DC conversion circuit. The method includes: calculating working information of an AC-DC conversion circuit according to at least one circuit parameter information of an input voltage, an input current, an output voltage, and an output current of the AC-DC conversion circuit; comparing the working information of the AC-DC conversion circuit with a preset working range to obtain an actual switching frequency or an actual switching period of the AC-DC conversion circuit. The AC-DC conversion circuit can meet requirements of Total Harmonic Distortion (THD), Power Factor (PF), efficiency and Electromagnetic Interference (EMI) and the like by adjusting the working information of the AC-DC conversion circuit through the preset working range. |
| US11342831B2 |
Homopolar turbine
In one embodiment, a turbine includes a shaft and a turbine stage coupled to the shaft. The turbine stage includes a turbine blade. The turbine further includes a housing surrounding the turbine stage and a magnet located within the housing. The turbine is operable to receive an exhaust gas, generate a magnetic field using the magnet, and generate, by rotating the turbine blade, a current along the turbine blade in a radial direction toward the shaft. The turbine is further operable to ionize the exhaust gas between a tip of the turbine blade and the housing to form a plasma and electrically connect, using the plasma, the tip of the turbine blade to the housing. |
| US11342829B2 |
Ocean current and tidal power electric generator
Embodiments of an apparatus for generating electric power from flowing seawater are disclosed. Embodiments form fluid channels having magnetic fields through which seawater will flow. Electrodes are arranged with respect to the fluid channels and connected together such that electric power is generated as seawater flows through the channels. |
| US11342828B2 |
Methods and systems for controllably moving multiple moveable stages in a displacement device
Aspects of the invention provide methods and systems for moving a plurality of moveable stages relative to a stator. The stator comprises a plurality of coils shaped to provide pluralities of coil trace groups where each coil trace group comprises a corresponding plurality of generally linearly elongated coil traces which extend across a stator tile. Each moveable stage comprises a plurality of magnet arrays. Methods and apparatus are provided for moving the moveable stages relative to the stator, where a magnet array from a first moveable stage and a magnet array from a second moveable stage both overlap a shared group of coil traces. For at least a portion of the time that the magnet arrays from the first and second moveable stages overlap the shared group of coil traces, currents are controllably driven in the shared coil trace group based on the positions of both the first and second moveable stages. The positions of the first and second moveable stages may be ascertained by feedback. |
| US11342824B2 |
Method for producing a rotor for an electrical machine, in particular of a motor vehicle, and rotor and motor vehicle
A method produces a rotor having at least one laminated core for an electrical machine, in which method at least one partial region of the rotor is provided with a plastic by injection molding. The method provides at least one disk following the laminated core in the axial direction of the rotor, by which disk the partial region is at least to a large extent delimited in the axial direction of the rotor; and by the injection molding, injects the plastic into the partial region via at least one through-opening in the disk leading into the partial region. |
| US11342818B2 |
Encoder, motor and controlling method of encoder
A controlling method of an encoder includes: detecting a rotation angle of a rotor of a motor coupled to the encoder to generate a first counting trigger signal and a second counting trigger signal so as to perform a turn number counting procedure; determining whether a period that an operating voltage of a driving circuit of the motor is smaller than a threshold voltage exceeds a preset time; and when the period exceeds the preset time, controlling a switching unit of the encoder to allow a battery of the encoder to provide a backup voltage to the encoder such that the encoder enters a low power processing procedure. |
| US11342817B2 |
Touch sensor unit
The disclosure provides a manufacturing method of a touch sensor unit that includes a tubular insulator housing a plurality of electrodes, and the plurality of electrodes housed in the tubular insulator are prevented from being fixed in a short-circuited state by the resin flowing into the tubular insulator. The manufacturing method of the touch sensor unit includes: a first process of disposing an end of a sensor holder, a resistor, connection wires, and a separator, which are included in a mold part provided at an end of the touch sensor unit, in a mold; and a second process of supplying molten resin into the mold in a state where the tubular insulator housing linear electrodes is pressed from an outer side of the sensor holder in the mold. In the second process, the tubular insulator is pressed within a range where the tubular insulator and an insertion protrusion overlap. |
| US11342815B2 |
Exchangeable temperature detection unit for a stator of an electric motor
A temperature detection unit for a stator of an electric motor, includes a plate, a support element, at least two feet, and at least two temperature sensors, wherein the temperature sensors are arranged one on each of the feet. |
| US11342805B2 |
Stator, motor, and electric power steering device
A stator comprises: a stator core placed in a circular ring shape around a central axis that extends vertically, onto which coil wires are wound; a first support member placed over the stator core; and a second support member placed over the first support member, the first support member having receiving grooves for guiding the coil wires coming out of the stator core, wherein the receiving grooves are grooves that open to the top and extend in a direction along the top surface of the first support member, the second support member having through-holes that axially support the coil wires, wherein the second support member at least partially overlaps the receiving grooves of the first support member in an axial view. |
| US11342802B2 |
Consequent-pole type rotor, electric motor, compressor, blower, and air conditioner
A rotor includes a rotor core including a magnet insertion hole and an opening and a permanent magnet inserted in the magnet insertion hole and forming a first magnetic pole. The rotor satisfies L1 |
| US11342794B2 |
Inductive charging device and method for monitoring an inductive charging device
The invention relates to an inductive charging device for a vehicle and to a method for monitoring an inductive charging device for a vehicle, wherein a metal object is detected in each case. The method has the steps of: carrying out a passive metal object detection, MOD, while a battery of a vehicle (1) is inductively charged by generating an electromagnetic field in order to induce a charge current (I2) in a receiving coil structure (2) of the vehicle (1); and carrying out an active MOD at points in time at which no inductive charging process is being carried out. |
| US11342792B2 |
System and method for inductive charging of portable devices
An electronic device having an inductive power transfer system is disclosed. The electronic device includes an inductive coil for inductive power transfer using an alternating magnetic field and a permanent magnet for creating a separable magnetic attachment between the electronic device and a second device having an inductive coil. The permanent magnet is positioned substantially at the geometric center of the inductive coil to align the inductive coil with the inductive coil in the second device. The permanent magnet has substantially flat first and second surfaces substantially parallel to the inductive coil, and the permanent magnet is manufactured to have an electrical resistivity to impede eddy current generation in the permanent magnet and heating of the permanent magnet by the alternating magnetic field during inductive power transfer. |
| US11342789B2 |
Detecting hot socket conditions in utility electricity meters
Various embodiments disclosed herein provide techniques for detecting hot socket conditions in an electrical system. A hot socket application executing on a utility electricity meter acquires, via a power line communications (PLC) modem, first signal readings associated with a utility electricity meter. The hot socket application acquires, via a radio frequency (RF) transceiver, second signal readings associated with the utility electricity meter. The hot socket application performs one or more operations on the first signal readings and the second signal readings to determine whether a hot socket condition is present. The hot socket application performs a remedial operation in response to determining that the one or operations indicate that the hot socket condition is present. |
| US11342787B2 |
Controller circuit for photovoltaic module
A controller circuit for a PV module includes a receiver circuit and a mode control and power conversion circuit. The receiver circuit receives a first signal from a transmitter circuit associated with the PV module. The receiver circuit changes a second signal from a first state to a second state based the first signal. The mode control and power conversion circuit receives a DC string voltage from a string of PV cells associated with the PV module, receives the second signal from the receiver circuit, switches from a first mode to a second mode in response to the second signal being changed to the second state, converts the DC string voltage to a standby voltage in the second mode, and provides the standby voltage to DC power lines between the PV module and a DC-to-AC inverter in the second mode. |
| US11342781B2 |
Power management circuit and power management method for triboelectric nanogenerator
The present disclosure discloses a power management circuit and a power management method for a triboelectric nanogenerator. The power management circuit includes a pulse current control switch, an intermediate energy storage element, and a target energy storage element, wherein the pulse current control switch is configured to instantaneously connect two electrode layers of the triboelectric nanogenerator to generate a transient pulse current, after movement of two relative moving components of the triboelectric nanogenerator generates static charges induced between the two electrode layers; the intermediate energy storage element is configured to store electric energy of the transient pulse current, and the target energy storage element is configured to store the electric energy output from the intermediate energy storage element. |
| US11342778B2 |
Electronic device for controlling communication connection with input device and method of controlling same
An electronic device is provided. The electronic device includes a housing including an inner space, a hole formed through the housing to the internal space, a stylus pen insertable into the internal space through the hole, wherein the stylus pen includes a first wireless communication circuit and a wireless charging receiver circuit, a wireless charging transmitter circuit positioned inside the housing and configured to provide charging to the wireless charging receiver circuit when the stylus pen is inserted into the inner space, a second wireless communication circuit positioned inside the housing, at least one processor operatively connected to the wireless charging transmitter circuit and the second wireless communication circuit, and at least one memory operatively connected to the at least one processor, wherein when executed, cause the at least one processor to detect whether the stylus pen is inserted into the inner space, start to provide charging for a first duration. |
| US11342774B2 |
Power conversion circuit, and charging apparatus and system
The invention provides a charging circuit, comprising a power conversion circuit, and an information collection and signal control circuit. The power conversion circuit is coupled to a voltage source and configured to provide a charging current to a battery. The power conversion circuit comprises a plurality of switch elements, and at least two storage elements, the at least two storage elements are selectively coupled to the voltage source and the output port through the plurality of switch elements. The information collection and signal control circuit is configured to collect information from the voltage source and battery, and control the plurality of switch elements to have the power conversion circuit work under different charging modes. |
| US11342772B2 |
Precharge controller
A precharge controller includes a main contactor, a capacitor, a precharge contactor, a current sensor, and a control unit. When starting a power supply from a battery to load, the control unit starts precharging by closing the precharge contactor when a detected current is equal to a preset value or lower, determines completion of precharging when the detected current once equal to or exceeded a first threshold value falls to a second threshold value or lower, and closes the main contactor. |
| US11342767B2 |
Multi-voltage charging terminal access port
A multi-voltage charging terminal access port includes at least one housing, a first charging terminal within the housing and configured to receive a first charging voltage, a second charging terminal within the housing and configured to receive a second charging voltage that is different from the first charging voltage, a first movable cover plate mounted within the housing, the first movable cover plate including a first access hole and being movable between a first position in which the first access hole is laterally offset from the first charging terminal to obstruct access to the first charging terminal and a second position in which the first access hole is aligned with the first charging terminal to allow access to the first charging terminal. |
| US11342766B2 |
Shopping cart charging device and charging system, escalator, shopping cart
A shopping cart charging device, a charging system, an escalator and a shopping cart is disclosed. The shopping cart charging device includes a charging electrode configured to be disposed on a wheel of a shopping cart. The charging electrode is configured to allow electrical connection with a power supply electrode disposed on an escalator, so as to charge the shopping cart. |
| US11342765B2 |
Terminal, power adapter and method for handling charging anomaly
A terminal, a power adapter, and a method for handling a charging anomaly are provided. The terminal includes a battery and a charging interface. The terminal forms a charging loop with the power adapter via the charging interface. The terminal also includes a communication unit, an anomaly detection unit, and an anomaly handling unit. The communications unit receives charging parameter information from the power adapter. The handling detection unit determines whether an anomaly occurs on the charging loop according to the charging parameter information. When the anomaly occurs on the charging loop, the anomaly handling unit controls the charging loop to enter into a protection state. Therefore, the security of the charging process is improved. |
| US11342761B2 |
Battery fleet charging system
A battery fleet charging system for charging two or more battery packs simultaneously, at independently controlled charge rates. The present invention can intelligently distribute the available charge power among multiple batteries, either symmetrically or asymmetrically, as specified by a controller that specifies and regulates the charge voltage. |
| US11342756B2 |
Microinverter systems and subsystems
An alternating current (AC) module system includes branch circuits and a main service panel to receive power from the branch circuits. A photovoltaic (PV) supervisor is located between the branch circuits and the panel. The PV supervisor aggregates the power from the branch circuits. The PV supervisor also performs a nonredundant operational function for one or more of the branch circuits. The PV supervisor includes a gateway device to permit control of the operational functions. |
| US11342754B2 |
Integrated electrical panel
The system includes one or more busbars couple to an AC line, branch relays each coupled to a busbar and to a respective circuit breaker, and current sensors each corresponding to at least one respective branch relay of the plurality of branch relays. The system also includes a deadfront arranged in front of the plurality of branch relays, and including openings corresponding to the branch relays allowing an electrical terminal of each branch relay to protrude forward through a respective opening. A circuit breaker is engaged with each respective branch relay, on the deadfront to create an array of branch circuit breakers. The combination of relay and circuit breaker allows each branch circuit to be controllable. The relays may include current sensors, such as a shunt, used to determine a branch circuit current and control the relay. Control circuitry manages the relay on-off operation and monitors branch circuit operation. |
| US11342751B2 |
Power management system for customer connected to power network and having load apparatus and power storage apparatus
A long-term predictor predicts long-term predicted power indicating temporal changes in consumed power of a customer using a long-term prediction model. A short-term predictor predicts short-term predicted power indicating temporal changes in the consumed power of the customer immediately after a current time, using a short-term prediction model, based on temporal changes in the consumed power of the customer immediately before the current time. A controller controls charging and discharging of a power storage apparatus at intervals based on the long-term predicted power and the short-term predicted power. The controller predicts temporal changes in charging power, discharging power, and charged electric energy of the power storage apparatus, and when the charged electric energy is predicted to reaches a lower limit due to discharging of the power storage apparatus, the controller charges power from the power network to the power storage apparatus in advance. |
| US11342749B1 |
Integration of a power flow control unit
A power flow control unit has one or more impedance injection units. The impedance injection unit has high current drivers and capacitors forming a capacitor bank, and a cooling plate. The cooling plate is thermally coupled to the high current drivers and thermally decoupled from the capacitor bank. Bus bars connect the impedance injection units in series with a power transmission line. The power flow control unit is configurable to inject into the power transmission line a reactive power of at least one MVAr (mega volt-ampere reactive). |
| US11342748B2 |
Dynamic voltage and reactive power controller for non-synchronous power generation plants
Systems and methods for improved anomaly detection for rotating machines. An example method may include determining that power generation is to be performed based on a voltage instead of a power factor; receiving a command voltage; receiving a measured voltage value from a first location in a power generation network; determining that the measured voltage value from the first location is less than the command voltage value; determining that a current value associated with a transmission line at the third location is less than a threshold current value; determining that a reactive power of a power generation component at a third location is less than a maximum reactive power of the component; and increasing, based on the determination that the reactive power of the component at the third location is less than a maximum reactive power of the component, the reactive power of the component. |
| US11342746B2 |
Managing queue distribution between critical datacenter and flexible datacenter
Systems include one or more critical datacenter connected to behind-the-meter flexible datacenters. The critical datacenter is powered by grid power and not necessarily collocated with the flexible datacenters, which are powered “behind the meter.” When a computational operation to be performed at the critical datacenter is identified and determined that it can be performed more efficiently or advantageously at a flexible datacenter, the computational operation is instead obtained by the flexible datacenters for performance. The critical datacenter and flexible datacenters preferably share a dedicated communication pathway to enable high-bandwidth, low-latency, secure data transmissions. A queue system may be used to organize computational operations waiting for distribution to either the critical datacenter or the flexible datacenter. |
| US11342735B2 |
Solid-state line disturbance circuit interrupter
The invention relates to a novel approach for the protection of electrical circuits from ground faults and parallel and series arc faults in a fully solid-state circuit configuration. Solid-state circuits and methods of use are described that provide the key functions of low-voltage DC power supply, mains voltage and current sensing, fault detection processing and high voltage electronic switching. |
| US11342730B1 |
Ceiling enclosure for wireless equipment
A ceiling enclosure that includes a main body, swing down panel and enclosure door. There are pivot ear retention legs extending from the main body. There are latch pin legs extending from the main body. The swing down panel is adapted to mount devices to the swing down panel. The swing down panel includes pivot ears extending from the swing down panel to attach to pivot ear retention legs and includes latch pin retention legs extending from the swing down panel to attach to latch pin legs. |
| US11342727B1 |
Semiconductor laser diode on tiled gallium containing material
In an example, the present invention provides a gallium and nitrogen containing structure. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates having one or more epitaxially grown layers. The structure has a first handle substrate coupled to each of the substrates. The orientation of a reference crystal direction for each of the substrates are parallel to within 10 degrees or less. The structure has a first bonding medium provided between the first handle substrate and each of the substrates. |
| US11342725B2 |
Light emission apparatus
A light emission apparatus includes a transistor comprising a control terminal, a first channel terminal, and a second channel terminal, wherein the control terminal is configured to receive a modulation signal, the first channel terminal is configured to generate a driving signal according to the modulation signal, and the second channel terminal is coupled to a fixed voltage; and a load comprising: a first terminal; a second terminal, wherein the first terminal is coupled to the first channel terminal of the transistor and the second terminal is coupled to the fixed voltage; a laser diode configured to emit a light according to the driving signal; and a first capacitor coupled to the laser diode, configured to isolate a DC current on the first terminal of the transistor. |
| US11342722B2 |
Laser systems and methods
Laser systems and methods are disclosed. One laser system comprises: a plurality of laser resonators, each resonator being operable to discharge an input laser beam; a relay assembly including at least one curved reflective surface that redirects each input laser beam, and reduces a beam size of the redirected beam; a galvo including a curved reflective surface that receives each redirected beam, and outputs a combined laser beam at power level greater than a power level of each laser input beam; and a coupling assembly that reduces spherical aberrations in the combined laser beam, and directs the combined laser beam into an optical fiber. In this system, the combined laser beam may have a maximum beam parameter product lower than a minimum beam parameter product of the optical fiber. Related systems and methods are also disclosed. |
| US11342720B2 |
Snap button fastener providing electrical connection
Embodiments are generally directed to a snap button fastener providing electrical connection. An embodiment of a fastener includes a first mechanical part, the first mechanical part including at least a stud portion, the first mechanical part including a first electrical connector; a second mechanical part, the second mechanical part including at least a socket portion with a spring element and the socket portion, the second mechanical part including a second electrical connector. The stud portion of the first mechanical part and the socket portion of second mechanical part, if separated, are to interlock upon the application of a first force towards each other, and, if interlocked, to separate upon the application of a second force away from each other. The first electrical connector and the second electrical connector are to be electrically connected when the first mechanical part and the mechanical part are interlocked, and first electrical connector and the second electrical connector are to be disconnected when the first mechanical part and second mechanical part are separated. |
| US11342718B2 |
Latch for telecommunications connector
A connector assembly (10) is disclosed in which a main body (12) and a latch member (30) are provided. In one aspect, the latch member (30) is formed as a spring and has a first portion (32) with a locking rib structure (38) that can be depressed towards the main body (12) to allow the connector assembly (10) to be inserted through a front side (102a) or a back side (102b) of an opening (102) in a panel (100). After insertion, the first portion (32) can then be released such that a retention structure (18) of the main body (12) and the locking rib structure (38) engage opposite ends of an opening (102) to secure the connector assembly (10) within the opening (102). The same connector (10) assembly (10) can be used with openings (102, 202, 302) of different sizes without modification. |
| US11342715B2 |
Electrical connector with socket and header having mating shielding parts
In a connector, each of housings of a socket and a header serving as connector parts includes: a terminal holder extending in a first direction and includes a terminal section of the associated connector part; and a side wall connector extending in a second direction intersecting the first direction, and connected to one end of the terminal holder of the associated connector part in the first direction. The shield member includes a first portion on the side wall connector, and a second portion aligned with the terminal holder of the connector part in the second direction. The socket and the header are inserted into each other in a third direction intersecting the first and second directions. The second portion of at least one of the shield members includes a shield bent portion with a curved portion curving toward the other connector part to be inserted. |
| US11342713B2 |
Reversible USB receptacle having high-frequency transmission properties
A reversible USB receptacle having high-frequency transmission properties, including a shielding middle plate (50), first and second terminal groups (30, 40) respectively located at upper and lower sides of the shielding middle plate (50), and an insulating body (20) making first and second terminal groups (30, 40) and the shielding middle plate (50) be formed into one piece, the insulating body (20) including a base and (21) a butting tongue portion (22) extending forward from the base (21), first and second terminal groups (30, 40) respectively including contact portions (35, 45) exposed on upper and lower surfaces of the butting tongue portion (22), retaining portions (36, 46) formed by extending backward from the contact portions (35, 45), and welding pins (37, 47) formed by extending from the retaining portions, wherein first and second terminal groups (30, 40) further include bent portions (381, 481) formed by oppositely bending from front end edges of contact portions (35, 45), and material strip connecting portions (382, 482) extending from ends of bent portions beyond front end of the shielding middle plate (50), and the material strip connecting portions (382, 482) are embedded in the insulating body (20). The present disclosure can achieve high-frequency transmission and prevent the front end of the terminal from warping. |
| US11342709B2 |
Cable connector having a latching lever
A cable connector, especially an IDC (Insulation Displacement Connector) connector, has an insulating body and an abutment bridge. The insulating body includes a housing and locking elements integrally manufactured with the housing. The locking elements include a lever and a bearing axle. The lever is doubly connected to the housing. A bearing axle of the locking element is designed to be inserted into a bearing recess of the abutment bridge. |
| US11342704B2 |
Signal connector positioning structure and signal line fabrication method
A signal connector positioning structure comprises a connector, a connecting component, a conductive connecting component, and a insulating component; the connector has a first opening, a second opening, and a first fixing structure; the connecting component has a first connection port and a first fixing component; the conductive connecting component has an opening; the insulating component has an opening; the conductive connecting component penetrates through the insulating component; wherein, the first fixing structure and the first fixing component are removably fastened in a screwed manner. |
| US11342697B2 |
Dual-level pad card edge self-guide and alignment of connector
A card, e.g. a printed circuit board (PCB), has one or more conductive layers and one or more non-conductive layers disposed and alternating upon one another to form a stack. One or more of the conductive layers has one or more wiring elements within the conductive layer. The PCB/card has one or more card edges. The PCB also has a plurality of dual-level pad structures on each of one or more of the card edges. The dual-level pad structures each have an upper level, a lower level, and two or more walls. The lower level is a conductive pad with conductive surface. At least one of the conductive pads electrically connects to one or more of the wiring elements and/or one or more vias. In each of the dual-level pad structures, the walls and upper level may be made of an electrically non-conductive, insulating, or dielectric material or may be covered with a conductive material that electrically connects to conductive surface. There are different non-limiting embodiments of the structures and methods of making the structures. |
| US11342695B2 |
Cable connection apparatus, connection assembly, and method for manufacturing connection assembly
A cable connection apparatus, a connection assembly, and a method for manufacturing the connection assembly are provided. The cable connection apparatus includes: a back plate and a connection member. The back plate includes a plate body and a ground layer. The plate body defines a through hole and a plurality of shielding holes. The plurality of shielding holes are defined at a periphery of the through hole. The ground layer is arranged on each of two opposite sides of the plate body and is connected to each of the plurality of shielding holes. The connection member abuts against or connects to a surface of a side of the back plate arranged with the ground layer. The connection member is arranged with a signal pin, and the signal pin is received in the through hole. |
| US11342694B2 |
Terminal and board connector
A terminal (11) to be mounted into a housing (20) mounted on a circuit board (40) includes a terminal contact portion (12) to be disposed in a forwardly open receptacle (21) of the housing (20), an inserting portion (14) to be inserted into a terminal insertion hole (24) penetrating through a rear wall (22) of the receptacle (21) in a front-rear direction, and a board connecting portion (16) to be drawn out rearward from the terminal insertion hole (24) and connected to the circuit board (40). The inserting portion (14) includes a first press-fit portion (31) projecting in a first direction intersecting the circuit board (40) and to be press-fit to an inner wall of the terminal insertion hole (24) and a second press-fit portion (33) projecting in a second direction intersecting the first direction and to be press-fit to the inner wall of the terminal insertion hole (24). |
| US11342692B2 |
Modular junction boxes
Modular junction boxes are disclosed. In one embodiment, a junction box for convenient modular industrial wiring is provided having a plurality of walls defining a first internal space of the junction box and at least one open face, a first connection area located on a first external face of the junction box having a first opening for receiving at least three electrical wires, a bus bar stack located in the first internal space of the junction box, a removable junction device having at least one contact support being mechanically and electrically attachable to the bus bar stack, and wherein when the junction device is attached to the bus bar stack, the junction device is electrically connected through the at least one contact support to one of at least three input openings of the bus bar stack. |
| US11342690B2 |
Fixing structure of splice part
A fixing structure of a splice part includes a plurality of electrical wires each having a splice part and mutually connected and a sheet material to which the splice part is fixed. The fixing structure of the splice part is considered to have a portion of the plurality of electrical wires fixed to the sheet material in addition to the splice part. |
| US11342687B1 |
Endfire antenna structure on an aerodynamic system
An endfire antenna structure is disclosed that is for use on aerodynamic systems. The antenna structure includes a first layer of patterned metal, a second layer of patterned metal, and a stack of material layers that includes the first layer of patterned metal and the second layer of patterned metal. The first layer of patterned metal includes a plurality of parallel slots etched through the metal. The second layer of patterned metal includes a tapered radio frequency (RF) feedline having a narrow end coupled to an input/output (I/O) antenna connection. The second layer of patterned metal is aligned over the first layer of patterned metal such that the tapered RF feedline has a length that extends across the plurality of parallel slots. The stack of material layers is flexible such that the stack of material layers is configured to wrap at least partially around the fuselage of an aerodynamic system. |
| US11342686B2 |
Film antenna and display device comprising same
A film antenna according to an embodiment of the present invention includes a dielectric layer, and a plurality of radiation patterns commonly arranged on an upper surface of the dielectric layer and forming a phased array. Directivity and gain property of a signal may be improved. The film antenna may be applied to a display device including a mobile communication device capable of transmitting and receiving in 3G or higher, for example, 5G of high-frequency band, to improve radiation properties and optical properties such as transmittance. |
| US11342685B2 |
Antenna module and mobile terminal
An antenna module and a mobile terminal are provided. The mobile terminal includes a shell including opposite upper and lower edges and opposite first and second side edges. First to fourth antennas are sequentially provided on the upper edge, and the first side edge is provided with a fifth antenna close to the upper edge. Sixth to eighth antennas are sequentially provided on the lower edge, and the second side edge is provided with a ninth antenna close to the lower edge. The first to ninth antennas form antenna groups respectively operating in communication frequency bands of 2G to 4G, GPS, WIFI2.4G, and WIFI5G, and an 8*8 MIMO antenna group operating in a 5G communication frequency band. The antenna module can operate in the 2G to 4G, GPS, and WIFI frequency bands, and have the 8*8 MIMO antenna and the antenna respectively operating in the 5G and WIFI5G frequency bands. |
| US11342684B2 |
Dual edge-fed slotted waveguide antenna for millimeter wave applications
Examples disclosed herein relate to a dual edge-fed Slotted Waveguide Antenna (SWA). The SWA has a plurality of antenna sections having a plurality of radiating slots and configured to radiate one or more transmission signals through the plurality of radiating slots, in which the plurality of antenna sections are symmetric about a termination region between the plurality of antenna sections. The SWA also has a plurality of distributed feed networks coupled to the plurality of antenna sections and configured to serve as a feed to the plurality of antenna sections, in which each of the plurality of distributed feed networks is a corporate feed structure comprising a plurality of transmission lines and further configured to propagate the one or more transmission signals through the plurality of transmission lines. Other examples disclosed herein relate to a radar system for use in an autonomous driving vehicle. |
| US11342682B2 |
Frequency-selective reflector module and system
Examples disclosed herein relate to a reflector device, having a first conductive layer of substrate, a dielectric layer of substrate, and a second conductive layer patterned with a first and a second set of frequency selective elements configured to reflect an incident electromagnetic radiation beam into a plurality of reflected beams at phase angles different from that of the incident electromagnetic radiation beams. |
| US11342679B1 |
Low profile monocone antenna
A monocone antenna with an impedance matching section that may allow a reduction in physical size of the cone while maintaining similar performance as a standard monocone antenna. Alternatively, the present disclosure may provide a monocone antenna with an impedance matching section that may allow operation at a lower frequency while maintaining the same physical size as a standard monocone antenna. Further, the present disclosure may provide a monocone antenna with an impedance matching section that may allow a reduction in physical size and operation at a lower frequency relative to a standard monocone antenna. |
| US11342677B2 |
Balanced dipole unit and broadband omnidirectional collinear array antenna
The present invention provides a balanced dipole unit and a broadband omnidirectional collinear array antenna formed by the balanced dipole unit. Balanced dipole unit circuits in the balanced dipole unit are symmetrically distributed on two sides of a circuit carrier, and a feeder and a ground wire in the balanced dipole unit are also symmetrically distributed, so that the balanced dipole unit has a completely symmetrical structure. A principle of the symmetrical structure is the same as a differential design principle and a self-balancing principle in the circuit design, thereby reducing current coupling between the balanced dipole units and eliminating the need of using an additional choke circuit when a broadband omnidirectional collinear array antenna is formed by the balanced dipole unit. |
| US11342676B2 |
Antenna
To improve a gain of an antenna. An antenna 1 includes a dielectric layer 6, a conductive ground layer 7 bonded to the layer 6 and including active slots 7c-7f aligned at regular intervals, aligned active elements 9c-9f formed facing the active slots 7c-7f, respectively, first passive elements 9b, 9a aligned with and extending from one end of a row of the active elements 9c-9f, second passive elements 9g, 9h aligned with and extending from the other end of the row, a feed line 4a formed on a side opposite to the layer 7 with respect to the layer 6, to be electromagnetically coupled to the active elements 9c-9f via the active slots 7c-7f. The second passive elements 9g, 9h are arranged in line symmetry with the first passive elements 9b, 9a with respect to a line 9z passing through the center of the row and perpendicular to the row. |
| US11342671B2 |
Dual-band antenna topology
An example dual-band antenna includes a substrate and a primary radiator disposed on the substrate and connected to a transmission line for driving the primary radiator, where the primary radiator, when driven via the transmission line, has a first resonant frequency. The dual-band antenna also includes a secondary radiator disposed on the substrate and unconnected to the primary radiator, where the primary radiator, when driven via the transmission line, induces a current in the secondary radiator such that the secondary radiator has a second resonant frequency different from the first resonant frequency. |
| US11342669B2 |
Antenna structure and wireless communication device using same
An antenna structure with wide radiation bandwidth in a reduced physical space includes a housing and a feed portion. The housing defines at least one gap and a slot that divides the housing into two or more radiation portions. The antenna structure further includes a middle-high band reflector (MHR). The MHR is connected to a side frame of the housing and extends along a direction parallel to one radiation portion. The MHR can also be positioned apart from one radiation portion. One end of the MHR is connected to a back board of the housing, the feed portion being electrically connected to one radiation portion. The back board and portions of the side frame without radiation portions are connected to form a system ground plane for grounding the antenna structure. |
| US11342668B2 |
Cellular communication systems having antenna arrays therein with enhanced half power beam width (HPBW) control
Antenna arrays include a first plurality of radiating elements in a first column thereof, which are responsive to a first plurality of RF feed signals derived from a first radio, and a second plurality of radiating elements in a second column thereof, which are responsive to a second plurality of RF feed signals derived from a second radio. A power divider circuit is provided, which is configured to drive a first one of the radiating elements at a first end of the second column of radiating elements with a majority of the energy associated with a first one of the first plurality of RF feed signals, and drive a first one of the radiating elements at a first end of the first column of radiating elements with a non-zero minority of the energy associated with the first one of the first plurality of RF feed signals. |
| US11342663B2 |
Antenna apparatus
An antenna apparatus includes: a first dipole antenna pattern; a feed line electrically connected to the first dipole antenna pattern; and a first ground plane disposed rearward of the first dipole antenna pattern and spaced apart from the first dipole antenna pattern; wherein the first ground plane forms a step-type cavity, and width of a rear portion of the step-type cavity is different from a width of a front portion of the step-type cavity. |
| US11342662B2 |
Device and method for switching communications
There is described a device for switching communications comprising a circuit board as well as first, second, and third antennas. The first antenna is coupled to the circuit board, and the first antenna is focused on a first direction and based on a first wireless technology. The second antenna is coupled to the circuit board, and the second antenna is focused on a second direction and based on the first wireless technology, in which the second direction is different from the first direction. The third antenna is coupled to the circuit board, and the third antenna is focused on a third direction and based on a second wireless technology, in which the second wireless technology is different from the first wireless technology. The second antenna may operate as a shield for the third antenna. |
| US11342660B2 |
Electronic device including antenna
An electronic device is provided. The electronic device includes a housing including a front plate, a rear plate facing away from the front plate, and a side member attached to the front plate or integrated with the rear plate, and surrounding a space between the front and rear plates, an antenna device disposed inside the housing and including stacked first to fourth layers, and a wireless communication circuit electrically coupled to the antenna element. The first layer includes a ground, the second layer includes at least one antenna element and a dielectric adjacent to the at least one antenna element, the third layer includes a first area with a first periodic structure of first conductive cells and a second area at least partially surrounded by the first area, and the fourth layer includes a third area with a second periodic structure of second conductive cells and a fourth area at least partially surrounded by the third area. |
| US11342658B2 |
Repeater
A repeater includes a first surface-side antenna, a second surface-side antenna, and a transceiver. Each of the first surface-side antenna and the second surface-side antenna includes a first conductor and a second conductor opposed to each other in a first axis, one or more third conductors positioned between the first conductor and the second conductor and extending in the first axis, a fourth conductor connected to the first conductor and the second conductor and extending in the first axis, and a feeding line electromagnetically connected to any one of the third conductors. The first conductor and the second conductor are capacitively connected through the third conductor. The feeding line of the first surface-side antenna is connected to the feeding line of the second surface-side antenna through the transceiver. |
| US11342652B2 |
5G MMW dual-polarized antenna unit, antenna array and terminal device
A 5G MMW dual-polarized antenna unit, an antenna array and a terminal device are disclosed. The 5G MMW dual-polarized antenna unit comprises a substrate and two feeder assemblies disposed in the substrate, wherein a square radiation patch conductive with the feeder assemblies is disposed on a top surface of the substrate, and a ground layer and feeder ports conductive with the feeder assemblies are disposed on a bottom surface of the substrate; each feeder assembly comprises an impedance transformation micro-strip line, and the two impedance transformation micro-strip lines are perpendicular to each other; and a short-circuit structure allowing the radiation patch to be conductive with the ground layer is disposed in the substrate and is located an intersection of extension lines of the two impedance transformation micro-strip lines. The 5G MMW dual-polarized antenna unit effectively improves the antenna performance and satisfies application requirements of 5G communication terminals in this waveband. |
| US11342647B2 |
Free-form dual dual-conductor integrated radio frequency media
A free-from radio frequency (RF) media includes a substrate having a first dielectric layer formed thereon and a second dielectric layer on an upper surface of the first dielectric layer. A first conductive layer is formed on an upper surface of the first dielectric layer and has a first overall profile. A second conductive layer having a second overall profile is formed on an upper surface of the second dielectric layer such that the second dielectric layer is interposed between the first and second conductive layers. The first overall profile of the first conductive layer is different from the second overall profile of the second conductive layer. |
| US11342638B2 |
Electrochemical cell unit, energy storage module and method for the assembly thereof
The invention relates to an electrochemical cell unit for storing electrical energy, in which the electrochemical cell unit includes at least two lithium-ion pouch cells, a planar element for orienting the at least two lithium-ion pouch cells, and a cell carrier. The at least two lithium-ion pouch cells are provided in the cell carrier and are in electrical contact. The at least two lithium-ion pouch cells also have a first and a second terminal lug. The planar element is provided, preferably centrally, in the cell carrier and in addition, is sandwiched between the at least two lithium-ion pouch cells, at least some portions of the planar element being in contact with the pouch cells. |
| US11342635B2 |
Electrode plate and electrode assembly using the same
An electrode assembly includes a cathode electrode plate, an anode electrode plate, and a separator disposed between the cathode electrode plate and the anode electrode plate. At least one of the cathode electrode plate and the anode electrode plate is an electrode plate which includes a current collector and a first conductive connector. The current collector includes an insulating layer having opposite side surfaces, a first conductive layer, a second conductive layer, and two electrode active substance layers. The first conductive layer and the second conductive layer are arranged on opposite side surfaces, and the two electrode active substance layers are coated onto the first conductive layer and the second conductive layer. The first conductive connector electrically connects the first conductive layer and the second conductive layer. The electrode assembly is formed by coiling the cathode electrode plate, the separator, and the anode electrode plate. |
| US11342633B2 |
Current collecting system for battery module, battery module, and vehicle
A current collecting system for a battery module, a battery module including the same, and a vehicle are disclosed. According to an exemplary embodiment of the present invention, the current collecting system includes a first current collecting plate and a second current collecting plate stacked to be insulated from each other, wherein the first current collecting plate is connected to the battery cells of the first group through a plurality of first connectors, respectively, and the second current collecting plate is connected to the battery cells of the second group through a plurality of second connectors, respectively, and wherein a minimum distance between two first connectors in the first current collecting plate and a minimum distance between two second connectors in the second current collecting plate are greater than a distance between any pair of neighboring connectors. |
| US11342630B2 |
Catholytes for solid state rechargeable batteries, battery architectures suitable for use with these catholytes, and methods of making and using the same
Provided herein are electrochemical cells having a solid separator, a lithium metal anode, and a positive electrode catholyte wherein the electrochemical cell includes a nitrile, dinitrile, or organic sulfur-including solvent and a lithium salt dissolved therein. Also set forth are methods of making and using these electrochemical cells. |
| US11342628B2 |
Battery pack array frames with integrated fastener housings
A battery pack includes a support structure, an array frame including a fastener housing, and a fastener received through the fastener housing for mounting the array frame to the support structure. The array frame may be mounted to the support structure using a top-down approach that includes inserting a fastener through a fastener housing of the array frame. |
| US11342622B2 |
Battery pack
Disclosed is a battery pack comprising: a plurality of battery cells, each including an upper surface through which a pair of electrode terminals are protruded, a lower surface facing the upper surface, and a pair of long side surfaces and a pair of short side surfaces among surfaces connecting the upper surface and the lower surface, the long side surfaces having a relatively large area, and the short side surfaces having a relatively small area; and a cell frame that receives the battery cells, exposes the upper surfaces of the battery cells, and includes side plates for supporting the short side surfaces of the plurality of battery cells and end plates positioned at opposite ends to support the long side surfaces of the battery cells, wherein the end plates include protrusions protruding in a direction opposite to a direction in which the end plates faces long side surfaces of the battery cells at the opposite ends; and a recess located between the protrusions, depressed in a direction of long side surfaces of the battery cells, and providing an extra space for swelling. |
| US11342621B2 |
Battery pack
A battery pack includes a battery module having a plurality of battery cells; a lower plate on which the plurality of battery modules are placed; a support member coupled to the lower plate to support the battery module; and a mounting nut coupled to the lower plate and coupled to the support member so that the battery module is fastened by means of a bolt, wherein the battery module is in contact with the support member. |
| US11342617B2 |
Urethane based adhesives for securing and sealing battery pack enclosure assemblies
This disclosure details exemplary battery pack designs for use in electrified vehicles. An exemplary battery pack may include a multi-piece enclosure assembly and an urethane based adhesive. The urethane based adhesive may function as both a fastener for securing the enclosure assembly components together and as a seal for blocking the ingress of moisture into the interior of the battery pack. Associated battery pack assembly methods are also disclosed. |
| US11342614B2 |
Battery cell and battery pack using same
A battery cell includes an exterior can, an electrode body accommodated in the exterior can, a heat insulator disposed on at least a part of the outer surface of the side wall of the exterior can, and an insulative film covering the heat insulator and an entire of the outer surface of the side wall of the exterior can. |
| US11342613B2 |
Battery module with improved heat dissipation, battery pack including the battery module and vehicle including the battery pack
A battery module increases heat dissipation by causing electronic cooling to occur at a breakdown voltage or higher, a battery pack including the battery module and a vehicle including the battery pack. The battery module includes a battery cell assembly having a plurality of battery cells and lead junction parts in which respective leads of the battery cells are joined to each other includes a thermoelectric device in which a heat absorbing portion is located on surfaces of the battery cells which are located at both outsides among the battery cells in the battery cell assembly, which correspond to a side surface of the battery cell assembly; and a constant voltage device configured to divert a current of the battery module to the thermoelectric device when an overcharge of the battery module occurs, to electronically cool the battery module when the overcharge of the battery module occurs. |
| US11342610B2 |
Accumulator arrangement
An accumulator arrangement for a hybrid or electric vehicle may include a plurality of battery cells stacked in a stacking direction to form at least one battery block, and a housing including a support frame limiting the housing towards an outside on four sides. The support frame may include at least two longitudinal members and at least two cross members perpendicularly aligned with one another. At least one longitudinal member of the at least two longitudinal members may be configured to conduct a coolant. The at least one battery block may abut against at least one of (i) the at least one longitudinal member and (ii) at least one of the at least two cross members to transfer heat. A plurality of connection points of the at least one longitudinal member, through which the coolant is flowable, may be configured on an outside of the support frame. |
| US11342609B2 |
Counter-flow heat exchanger for battery thermal management applications
A heat exchanger for thermal management of battery units made-up of plurality of battery cells or battery cell containers housing one or more battery cells is disclosed. The heat exchanger has a main body portion defining at least one primary heat transfer surface for surface-to-surface contact with a corresponding surface of at least one of the battery cells or containers. A plurality of alternating first and second fluid flow passages are formed within the main body portion each defining a flow direction, the flow direction through the first fluid flow passages being generally opposite to the flow direction through the second fluid flow passages providing a counter-flow heat exchanger. |
| US11342607B2 |
Battery module, battery pack comprising battery module and vehicle comprising battery pack
A battery module includes a battery cell assembly having a plurality of battery cells, a sensing assembly which covers a front and rear of the battery cell assembly when mounted thereto, a module case which receives the battery cell assembly and the mounted sensing assembly, and a thermally conductive adhesive interposed between an upper inner surface of the module case and an upper side of the battery cell assembly. The sensing assembly includes a first busbar frame assembly positioned at the front of the battery cell assembly, a second busbar frame assembly positioned at the rear of the battery cell assembly, and a sensing wire which connects the first and second busbar frame assemblies and runs across the upper side of the battery cell assembly in a diagonal direction. The thermally conductive adhesive is disposed on two sides of the sensing wire. |
| US11342604B2 |
Battery module in which cooling and assembly structure is simplified, and manufacturing method therefor
A battery module includes a plurality of can-type secondary batteries; a cooling tray formed in a container shape and having an accommodation space capable of accommodating the plurality of can-type secondary batteries; a heatsink having a hollow structure in which a coolant flows, the heatsink being disposed in contact with an outer surface of the cooling tray; and a thermally conductive adhesive solution filled in the accommodation space of the cooling tray, wherein the plurality of can-type secondary batteries are arranged such that a lower portion thereof is immersed in the thermally conductive adhesive solution. |
| US11342599B2 |
Semiconductor device and electronic device
A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged. |
| US11342598B2 |
Inductive power transfer apparatus and electric autocycle charger including the inductive power transfer apparatus
An inductive charging apparatus includes a primary conductor with at least one node for creating a magnetic field and at least one intermediate resonant circuit including a first coil for receiving inductive power from the node, a second coil operable in use to be driven by current from the first coil to generate a magnetic field for power transfer, and a tuning capacitor coupled to the first and second coils for resonance therewith. |
| US11342592B2 |
All-solid battery
An all-solid battery includes a positive-electrode layer having a positive-electrode current collector and a positive-electrode mixture layer, a negative-electrode layer having a negative-electrode current collector and a negative-electrode mixture layer, and a solid electrolyte layer. The positive-electrode mixture layer contains a positive-electrode active material and a solid electrolyte. The solid electrolyte layer is disposed between the positive-electrode mixture layer and the negative-electrode mixture layer. In the positive-electrode mixture layer, the active material volume proportion is larger and the porosity is smaller in a portion closer to the positive-electrode current collector than in a portion far from the positive-electrode current collector. |
| US11342589B2 |
Calcium salt for calcium batteries
Disclosed is a calcium salt, Ca(HMDS)2, where HMDS is the hexamethyldisilazide anion (also known as bis(trimethylsilyl)amide), enables high current densities and high coulombic efficiency for calcium metal deposition and dissolution. These properties facilitate the use of this salt in batteries based on calcium metal. In addition, the salt is significant for batteries based on metal anodes, which have higher specific energies than batteries based on intercalation anodes, such as LiC6. In particular, a calcium based rechargeable battery includes Ca(HMDS)2 salt and at least one solvent, the solvent suitable for calcium battery cycling. The at least one solvent can be diethyl ether, diisopropylether, methyl t-butyl ether (MTBE), 1,3-dioxane, 1,4-dioxane, tetrahydrofuran (THF), tetrahydropyran, glyme, diglyme, triglyme or tetraglyme, or any mixture thereof. |
| US11342585B2 |
Gel polymer electrolyte composition and lithium secondary battery including the same
The present invention relates to a gel polymer electrolyte composition for a lithium secondary battery, a gel polymer electrolyte prepared by polymerizing the same, and a secondary battery including the gel polymer electrolyte, and particularly, to a gel polymer electrolyte composition for a lithium secondary battery, which includes a lithium salt, a non-aqueous organic solvent, an ionic liquid, an oligomer having a specific structure, a flame retardant, and a polymerization initiator, a gel polymer electrolyte formed by polymerizing the gel polymer electrolyte composition in an inert atmosphere, and a lithium secondary battery in which flame retardancy and high-temperature stability are improved by including the gel polymer electrolyte. |
| US11342583B2 |
Electrolyte composition, electrolyte membrane, electrode, cell and method for evaluating electrolyte composition
The present invention provides an electrolyte composition that provides better charging/discharging performance when used in a cell than a conventional electrolyte composition. The present invention relates to an electrolyte composition containing an alkali metal salt, at least one polymer selected from the group consisting of a polyether polymer, a (meth)acrylic polymer, a nitrile polymer, and a fluoropolymer, and an ion dissociation accelerator. The composition has an alkali metal salt concentration of 1.8 mol/kg or higher. |
| US11342582B2 |
Lithium-ion-conducting composite material, comprising at least one polymer and lithium-ion-conducting particles
A lithium-ion-conducting composite material is provided that includes at least one polymer and lithium-ion-conducting particles. The interfacial resistance for the lithium-ion conductivity between the polymer and the particles is reduced as a result of a surface modification of the particles and therefore the lithium-ion conductivity is greater than for a comparable composite material wherein the interfacial resistance between the polymer and the particles is not reduced. |
| US11342578B2 |
Method for manufacturing solid electrolyte membrane for all solid type battery and solid electrolyte membrane manufactured by the method
A solid electrolyte membrane and method of preparing, including a plurality of polymer filaments arranged crossed as a 3-dimensional structure in the form of a net of nonwoven fabric-like shape, and a plurality of inorganic solid electrolytes inserted and uniformly distributed in the structure. By this structural feature, a large amount of solid electrolyte particles are uniformly distributed and filled in the electrolyte membrane, contact between the particles is good, and ionic conduction paths are sufficiently provided. Additionally, the durability of the solid electrolyte membrane is improved by the 3-dimensional structure, and the flexibility and strength increase. The nonwoven fabric composite solid electrolyte membrane has an effect in preventing inorganic solid electrolyte particle from being disconnected therefrom. |
| US11342577B2 |
Lithium metal battery including phase transformation layer facing lithium metal negative electrode
Provided is provided a lithium metal battery which includes a composite solid electrolyte membrane interposed between a lithium metal negative electrode and a positive electrode, wherein the composite solid electrolyte membrane includes: a phase transformation layer containing a plasticizer and a lithium salt; a porous polymer sheet layer; and a solid polymer electrolyte layer, the phase transformation layer, the porous polymer sheet layer and the solid polymer electrolyte layer stacked successively, and the phase transformation layer is disposed in such a manner that it faces the lithium metal negative electrode. The lithium metal battery shows reduced resistance at the interface with an electrode and increased ion conductivity, has improved safety, and provides improved energy density of an electrode. |
| US11342574B2 |
Fuel cell stack
An opening is formed in an accommodating case of a fuel cell stack. Flat cables are led out of the accommodating case through the opening. The flat cables pass through a grommet covering the opening. The grommet is positioned by a seal plate (positioning member) attached to the accommodating case. |
| US11342570B2 |
Method for operating a fuel cell arrangement and also a corresponding fuel cell arrangement
The invention relates to a method for operating a fuel cell arrangement which has a fuel cell for providing electrical energy in an electric circuit that has a circuit which is electrically connected to the fuel cell via a DC-DC converter, and a battery. It is provided that in at least one mode of operation of the fuel cell arrangement, following a start-up of the fuel cell, the battery is electrically disconnected from the circuit, and the DC-DC converter is operated in non-switched mode in order to supply at least one electrical consumer in the circuit with electric current provided by the fuel cell. The invention further relates to a fuel cell arrangement. |
| US11342567B2 |
High energy density redox flow device
Redox flow devices are described including a positive electrode current collector, a negative electrode current collector, and an ion-permeable membrane separating said positive and negative current collectors, positioned and arranged to define a positive electroactive zone and a negative electroactive zone; wherein at least one of said positive and negative electroactive zone comprises a flowable semi-solid composition comprising ion storage compound particles capable of taking up or releasing said ions during operation of the cell, and wherein the ion storage compound particles have a polydisperse size distribution in which the finest particles present in at least 5 vol % of the total volume, is at least a factor of 5 smaller than the largest particles present in at least 5 vol % of the total volume. |
| US11342562B2 |
Binder solution for all-solid-state batteries, electrode slurry including the binder solution, and method of manufacturing all-solid-state battery using the electrode slurry
The present disclosure relates to a binder solution for all-solid-state batteries. The binder solution includes a polymer binder, a first solvent, and an ion-conductive additive, wherein the ion-conductive additive includes lithium salt and a second solvent, which is different from the first solvent. |
| US11342561B2 |
Protective polymeric lattices for lithium anodes in lithium-sulfur batteries
A disclosed battery may include an anode, a polymeric network disposed over one or more exposed surfaces of the anode, a cathode positioned opposite to the anode, an electrolyte at least partially dispersed throughout the cathode, and a separator. The anode may include an alkali metal that can release alkali ions during operational discharge-charge cycling of the battery. The polymeric network may include carbonaceous materials grafted with fluorinated polymer chains cross-linked with each other. The fluorinated polymer chains may produce an alkali-metal containing fluoride in response to operational cycling of the battery. Formation of the alkali-metal containing fluoride may suppress alkali metal dendrite formation from the anode such that lithium is consumed to form lithium fluoride rather than forming lithium-containing dendritic structures. The separator may be positioned between the anode and the cathode. |
| US11342560B2 |
Electrode coating liquid composition, electrode for power storage device manufactured using the electrode coating liquid composition, and power storage device having the electrode
An electrode coating liquid composition that contains an electrode active material, a conductive auxiliary, a dispersant, and a binding agent. The dispersant contains cellulose fibers that satisfy (a)-(c). A total amount of the dispersant and the binding agent is 0.5 mass % or more and 15 mass % or less with respect to 100 mass % of the solid content of the electrode coating liquid composition. (a) the number average width of the shortest widths is 2 nm or more and 200 nm or less. (b) the aspect ratio is 7.5 or more and 75 or less. (c) cellulose I crystals are included and the crystallinity thereof is 70% or more and 95% or less. |
| US11342558B2 |
Surface modification
An electrochemically active material comprising a surface is provided, wherein the surface comprises an oligomer. A method of functionalising the surface with the oligomer is also provided. |
| US11342557B2 |
Positive electrode active material for lithium rechargeable battery, method of producing the same, and lithium rechargeable battery including the same
A surface of a LiCoO2-based positive electrode active material to have a rock salt crystal structure is provided. Specifically, a positive electrode active material for a lithium rechargeable battery is provided, including: a core particle containing lithium cobalt oxide doped with aluminum (Al); and a coating layer positioned on a surface of the core particle and containing a cobalt(Co)-based compound having a rock salt crystal structure. A method of producing the positive electrode active material is also provided using a solid-phase method. The positive electrode active material can be applied to a positive electrode, lithium rechargeable battery, battery module, battery pack, and the like. |
| US11342554B2 |
Anode, and electrochemical device and electronic device comprising same
The present application relates to an anode, and an electrochemical device and an electronic device comprising the same. Embodiments of the present application provided an anode comprising: a current collector, a first anode structure layer and a second anode structure layer. The first anode structure layer comprises a first framework material and the second anode structure layer comprises a second framework material, wherein the first anode structure layer is disposed between the current collector and the second anode structure layer, and the first framework material has a higher oxidation-reduction potential for lithium ion or electronic conductivity than the second framework material. When the anode with double-layer structure provided by the present application is charged, the space utilization ratio of the anode can be enhanced, the rate capability of the electrochemical device can be enhanced, the formation of lithium dendrites may be inhibited, and the volume change amount of the anode can be reduced, thereby enhancing the safety performance and cycle performance of the electrochemical device. |
| US11342553B2 |
Methods for prelithiation of silicon containing electrodes
The present application describes a method of forming an energy storage device that directly adds a lithium layer (such as a lithium foil or otherwise deposited lithium) into the cell stack during cell assembly for prelithiating. The method includes providing a silicon-based anode, providing a cathode, positioning a separator between the anode and the cathode, and disposing a lithium layer between the silicon-based anode and the separator, such that the lithium layer is in contact with the anode. |
| US11342550B2 |
Electrode body for lead-acid battery, lead-acid battery using the same, and method of manufacturing electrode body for lead-acid battery
The weight and size of a lead-acid battery is reduced and the energy density per mass by forming base members of components of the lead-acid battery is improved by using aluminum or aluminum alloy and forming multiple plating layers on a surface of each base member. In order to prevent formation of pinholes in the multiple plating layers, the surface of the base member 22 is subjected to flattening processing, a solder plating layer with a film thickness of 10 μm or more is formed, or many layers of group 4 metals with similar chemical properties are laminated. Moreover, in a positive electrode plate and a negative electrode plate, an active material layer 24 is formed on the outermost lead plating layer by an electrolytic formation treatment to improve the charging and discharging efficiencies of the lead-acid battery and to greatly reduce fall-off the active material layer 24. |
| US11342546B2 |
Method of infusing sulfur and resulting composition
A method utilizing microwave energy to incorporate sulfur onto carbon, prepare cathode material for lithium sulfur battery applications, and the compositions resulting therefrom is disclosed. |
| US11342541B2 |
Method of fabricating light emitting display panel using solvent vapor compensation reservoir
A method of fabricating a light emitting display panel. The method includes providing a substrate having a display area and a peripheral area, the substrate including a pixel definition layer for defining a plurality of subpixel apertures for a light emitting layer in the display area; attaching a solvent vapor compensation reservoir to the peripheral area of the substrate, the solvent vapor compensation reservoir having one or more ink droplet receiving grooves configured to receive an ink droplet and a connection layer, the solvent vapor compensation reservoir removably attached to the peripheral area of the substrate through the connection layer; dispensing ink droplets into the plurality of subpixel apertures and the one or more ink droplet receiving grooves; drying the ink droplets dispensed into the plurality of subpixel apertures and the one or more ink droplet receiving grooves; and removing the solvent vapor compensation reservoir from the substrate. |
| US11342540B2 |
AMOLED display panel that includes a diffusion film, display panel production method, and display apparatus
A display panel includes an AMOLED light-emitting board and a light filter layer disposed on a cathode surface of the AMOLED light-emitting board. The light filter layer includes a color light filter and a diffusion film. The color light filter includes a red light filter component, a green light filter component, a blue light filter component, and a BM. The diffusion film is disposed on a surface of the color light filter, or is disposed on each light filter component in the color light filter. The diffusion film is configured to enable ambient light passing through the diffusion film to be incident on the cathode surface of the AMOLED light-emitting board in a direction that is not perpendicular to the cathode surface of the AMOLED light-emitting board. |
| US11342539B2 |
Display panel aligned with window and display device having the same
A display device includes a window; a display panel including: a flat portion corresponding to the display area, and a bending portion extending from the flat portion and at which the display panel is bendable; a circuit substrate connected to the display panel at the bending portion; and a protection film disposed facing the window with the display panel therebetween. The window and the display panel each include a first side surface corresponding to the bending portion, and remaining side surfaces except for the first side surface, and the remaining side surfaces of the window and the display panel are respectively aligned with each other to define a total planar area of the window being equal to a total planar area of the flat portion. |
| US11342538B2 |
Organic EL display device having reflection transmission portion, and electronic apparatus
An organic EL display device of the present disclosure includes a substrate, a lens layer including a lens, a light-emitting layer containing an organic light-emitting material, a reflection portion disposed between the substrate and the light-emitting layer, and having light reflecting properties for reflecting light generated in the light-emitting layer, and a reflection transmission portion disposed between the light-emitting layer and the lens layer, and having light reflecting properties and translucency, and moreover causing resonance of light, which is generated in the light-emitting layer, between the reflection portion and the reflection transmission portion. |
| US11342536B2 |
Display device having peripheral area protrusions
A display device includes: a display layer having a display area including a plurality of pixel areas and a peripheral area at least partially surrounding the display area; and a cover layer disposed on the display layer to encapsulate the display area. The cover layer includes: a light blocking portion overlapping the display area and the peripheral area and including a plurality of openings to transmit light from the plurality of pixel areas and to block light in the peripheral area; a first protrusion disposed on the light blocking portion in the peripheral area and surrounding the display area; and an overcoating layer covering the display area and contacting a lateral surface of the first protrusion. |
| US11342534B2 |
Encapsulation film
The present application relates to an encapsulation film, a method for producing the same, an organic electronic device comprising the same, and a method for preparing an organic electronic device using the same, which allows forming a structure capable of blocking moisture or oxygen introduced into an organic electronic device from the outside, and can prevent occurrence of bright spots of the organic electronic device. |
| US11342533B2 |
OLED display panel and preparation method thereof
An organic light emitting diode (OLED) display panel and preparation method thereof, which includes an array substrate, an organic light emitting layer, and an encapsulation layer. The encapsulation layer includes organic-inorganic functional layer. Through disposing the organic-inorganic functional layer, the overall thickness of the encapsulation thin film can be reduced while ensuring the encapsulation effect, and the bending performance of the OLED device can be improved. Further, a mask plate is not required in the encapsulation process, thereby can effectively save production cost. |
| US11342532B2 |
Display panel, display device, and manufacturing methods thereof
A display panel and manufacturing methods thereof are provided. In one example, the display panel includes a flexible substrate having a display area and a non-display area, a dam structure located in the non-display area and disposed around the display area, one or more grooves disposed on the non-display area between the display area and the dam structure, and an organic encapsulation layer. In some examples, the organic encapsulation layer covers each of the display area, at least a portion of the non-display area, and the one or more grooves. Accordingly, a display device comprising the display panel is also provided. Thus, a flatness of the organic encapsulation layer may be improved and peeling may be reduced between the organic encapsulation layer and a substrate on which the organic encapsulation layer is disposed, thereby improving an overall quality of the finished display panel. |
| US11342528B2 |
Organic electroluminescent device and method of manufacturing the same
An organic electroluminescent device includes, in order, a first electrode, a light-emitting layer, a resistive layer, and a second electrode. The resistive layer has a specific resistance within a range of 1×104 Ω·cm or greater and 5×106 Ω·m or less and includes a mixed material including two or more of zinc oxide, gallium oxide, and silicon dioxide and having a composition ratio within a predetermined range. |
| US11342525B2 |
Display device
A display device is provided. The display device includes a plurality of pixels; a first base; an organic light emitting element on the first base and in each of the pixels; a second base facing the first base; and a filling pattern layer between the organic light emitting elements and the second base, the filling pattern layer including a first pattern portion and a second pattern portion alternately arranged along a same direction in a plan view, wherein the first pattern portion is in each of the pixels, the second pattern portion is at a boundary of each of the pixels and contacts the first pattern portion, and a refractive index of the second pattern portion is smaller than that of the first pattern portion. |
| US11342524B2 |
Light emitting element, light emitting device, and apparatus for producing light emitting element
A light-emitting element is provided to improve light emission efficiency of a light-emitting element. The light-emitting element includes: a first electrode; a second electrode; a quantum dot layer provided between the first electrode and the second electrode, in which quantum dots are layered; and a hole-transport layer provided between the quantum dot layer and the first electrode, wherein the hole-transport layer includes a plurality of layers each containing a different material, the plurality of layers of the hole-transport layer each have an ionization potential increasing from the first electrode toward the quantum dot layer, and, among the plurality of layers of the hole-transport layer, a layer in contact with the quantum dot layer is higher in ionization potential than the quantum dot layer. |
| US11342522B2 |
White-light QLED component, backlight module and illumination apparatus
A white-light QLED component, comprising: a transparent substrate, an anode layer, a HI layer, a HT layer, an emission layer, an ET layer, and a cathode layer. The emission layer is incorporated with a plurality of yellow QDs and a plurality of blue QDs, wherein the yellow QDs and the blue QDs have a mixing ratio in a range between 1:4 and 1:8. Experimental data have revealed that, a color temperature of a white light radiated from the white-light QLED component is modulatable by adjusting the weight percent of the yellow QDs in the emission layer, such that the QLED component can be decided to provide a cold white light, a pure white light or a warm white light. It can also control the white-light QLED component to optionally emit cold white light, pure white light or warm white light by modulating a bias voltage. |
| US11342511B2 |
Azoline ring-containing compound, electron transport/injection layer material containing the same, and organic electroluminescent element using the same
An object is to provide an azoline ring-containing compound which achieves characteristics required for an organic EL element, such as a driving voltage, a quantum efficiency, and element lifetime in a well-balanced manner, and particularly can obtain a high quantum efficiency, for example, in a case where the azoline ring-containing compound is used for the organic EL element. The above object is achieved by an azoline ring-containing compound represented by the following general formula (1). In formula (1), φ represents an m-valent group derived from an aromatic hydrocarbon having 6 to 40 carbon atoms or the like, Y represents —O—, —S—, or >N—Ar, R1 to R5 each represent a hydrogen atom or an alkyl having 1 to 4 carbon atoms, and L represents a phenylene group or the like. |
| US11342509B2 |
Organic electroluminescent materials and devices
A compound including a first ligand LA selected from the following group: is disclosed. |
| US11342505B2 |
Organic compounds and organic electroluminescent device including the same
The present disclosure relates to a novel organic compound and an organic electroluminescent device including the same. More specifically, the present disclosure relates to a deuterated organic compound and an organic electroluminescent device including at least one organic layer made of the deuterated organic compound. Thus, the organic electroluminescent device exhibits a longer lifetime, lower voltage implementation, and improved luminous efficiency. |
| US11342499B2 |
RRAM devices with reduced forming voltage
Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer. |
| US11342497B2 |
Magnetic memory using spin-orbit torque
Spin-orbit-torque (SOT) segments are provided along the sides of free layers in magnetoresistive devices that include magnetic tunnel junctions. Current flowing through such SOT segments injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used as an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction in order to improve the efficiency of the switching current applied to the magnetoresistive device. |
| US11342495B2 |
Magnetic memory devices for reducing electrical shorts between magnetic tunnel junction patterns
Magnetic memory devices may include a substrate, a metal pattern extending in a first direction on the substrate, a magnetic tunnel junction pattern on the metal pattern, and an anti-oxidation layer between the metal pattern and the magnetic tunnel junction pattern. The magnetic tunnel junction pattern may include a first magnetic pattern, a tunnel barrier pattern, and a second magnetic pattern. |
| US11342494B2 |
Piezoelectric actuator and piezoelectric actuating plate thereof
A piezoelectric actuator for a miniature fluid transportation device is provided and includes a piezoelectric actuating plate and a piezoelectric element. The piezoelectric actuating plate includes a suspension plate, an outer frame, and brackets. The suspension plate has a first thickness. The outer frame is arranged around the suspension plate and has a third thickness. Each of the brackets is connected between the suspension plate and the outer frame and has a fourth thickness. The third thickness is larger than the first thickness, and the first thickness is larger than the fourth thickness. The suspension plate, the outer frame and the brackets are constructed to form different stepped structures to minimize the thickness of the brackets, enhance the elasticity of the brackets. Thus, displacement of the suspension plate in the vertical direction is enhanced and the transportation efficiency of the miniature fluid transportation device is intensified. |
| US11342489B2 |
Method of surface-mounting components
A method of connecting a plurality of electronic components to a flexible circuit board comprises: providing a carrier substrate carrying the electronic components, each of the electronic components having at least one electrical contact coated with electrically conductive adhesive; and applying the carrier substrate to the flexible circuit board such that the electronic components are adhered to the flexible circuit board in electrical contact therewith via the conductive adhesive. The electronic components may comprise LEDs and there may be provided one or more optical layers over the flexible circuit board. |
| US11342488B2 |
Light emitting diode chip and light emitting diode device
A light emitting diode chip including an epitaxy stacked layer, first and second electrodes and a first reflective layer is provided. The epitaxy stacked layer includes first-type and second-type semiconductor layers and a light-emitting layer. The first and second electrodes are respectively electrically connected to the first-type and second-type semiconductor layers. An orthogonal projection of the light-emitting layer on the first-type semiconductor layer is misaligned with an orthogonal projection of the first electrode on the first-type semiconductor layer. The first reflective layer is disposed on the epitaxy stacked layer, the first and second electrodes. An orthogonal projection of the first reflective layer on the second-type semiconductor layer is misaligned with an orthogonal projection of the second electrode on the second-type semiconductor layer. Furthermore, a light emitting diode device is also provided. |
| US11342484B2 |
Metal oxide semiconductor-based light emitting device
An optoelectronic semiconductor light emitting device configured to emit light having a wavelength in the range from about 150 nm to about 425 nm is disclosed. In embodiments, the device comprises a substrate having at least one epitaxial semiconductor layer disposed thereon, wherein each of the one or more epitaxial semiconductor layers comprises a metal oxide. Also disclosed is an optoelectronic semiconductor device for generating light of a predetermined wavelength comprising a substrate and an optical emission region. The optical emission region has an optical emission region band structure configured for generating light of the predetermined wavelength and comprises one or more epitaxial metal oxide layers supported by the substrate. |
| US11342478B2 |
Sapphire collector for reducing mechanical damage during die level laser lift-off
In a Sapphire Collector (SC), one or more features, both structural and parametric, are included for capturing the die-size sapphire chips that are removed from a semiconductor structure during die-level laser lift-off (LLO). These features are designed to increase the likelihood that each sapphire chip is securely captured by the Sapphire Collector immediately after it is released from the semiconductor structure. |
| US11342476B2 |
Optical device and method for manufacturing the same
An optical device includes a substrate, a light receiving component, an encapsulant, a coupling layer and a light shielding layer. The light receiving component is disposed on the substrate. The encapsulant covers the light receiving component. The coupling layer is disposed on at least a portion of the encapsulant. The light shielding layer is disposed on the coupling layer. |
| US11342474B2 |
Method for preparing avalanche photodiode
A method for preparing an avalanche photodiode includes preparing a mesa on a wafer, growing a sacrificial layer on an upper surface of the wafer and a side surface of the mesa, removing the sacrificial layer in an ohmic contact electrode region of the wafer, preparing an ohmic contact electrode in the ohmic contact electrode region of the wafer, removing the sacrificial layer in a non-mesa region of the wafer, growing a passivation layer on the upper surface of the wafer and the side surface of the mesa, removing the passivation layer on the upper surface of the mesa of the wafer and the passivation layer in the non-mesa region of the wafer corresponding to the ohmic contact electrode region, and removing the sacrificial layer on the upper surface of the mesa of the wafer. |
| US11342472B2 |
Temperature insensitive optical receiver
A device may include: a highly doped n+ Si region; an intrinsic silicon multiplication region disposed on at least a portion of the n+ Si region, the intrinsic silicon multiplication having a thickness of about 90-110 nm; a highly doped p− Si charge region disposed on at least part of the intrinsic silicon multiplication region, the p− Si charge region having a thickness of about 40-60 nm; and a p+ Ge absorption region disposed on at least a portion of the p− Si charge region; wherein the p+ Ge absorption region is doped across its entire thickness. The thickness of the n+ Si region may be about 100 nm and the thickness of the p− Si charge region may be about 50 nm. The p+ Ge absorption region may confine the electric field to the multiplication region and the charge region to achieve a temperature stability of 4.2 mV/° C. |
| US11342465B2 |
Method of forming oxide semiconductor field effect transistor
An oxide semiconductor field effect transistor (OSFET) includes a first insulating layer, a source, a drain, a U-shaped channel layer and a metal gate. The first insulating layer is disposed on a substrate. The source and the drain are disposed in the first insulating layer. The U-shaped channel layer is sandwiched by the source and the drain. The metal gate is disposed on the U-shaped channel layer, wherein the U-shaped channel layer includes at least an oxide semiconductor layer. The present invention also provides a method for forming said oxide semiconductor field effect transistor. |
| US11342464B2 |
Semiconductor device comprising first and second insulating layer each has a tapered shape
A semiconductor device includes an oxide semiconductor layer including a crystalline region over an insulating surface, a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode layer over the gate insulating layer in a region overlapping with the crystalline region. The crystalline region includes a crystal whose c-axis is aligned in a direction substantially perpendicular to a surface of the oxide semiconductor layer. |
| US11342461B2 |
Thin film transistor, method for producing same and display device
A TFT includes an oxide semiconductor layer including a conductive region electrically connected to a source electrode, a conductive region electrically connected to a drain electrode, a channel region being an oxide semiconductor region that overlaps a gate electrode, and at least one resistive region being an oxide semiconductor region provided between the channel region and a conductive region adjacent to the channel region. |
| US11342460B2 |
Thin film transistor, method for fabricating the same, array substrate, display panel and display device
A thin film transistor, a method for fabricating the same, an array substrate, a display panel, and a display device are provided. The thin film transistor includes a substrate, and an active layer on the substrate, wherein the active layer includes a poly-silicon layer and has a channel region and two electrode connection regions respectively on two sides of the channel region, and the channel region includes a plurality of lightly drain doping segments, which are spaced apart along from one of the electrode connection regions to the other electrode connection region, and channel segments located between the lightly drain doping segments. |
| US11342456B2 |
Ferroelectric semiconductor device including a ferroelectric and manufacturing method thereof
A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer. |
| US11342455B2 |
Minimization of silicon germanium facets in planar metal oxide semiconductor structures
A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions. |
| US11342453B2 |
Field effect transistor with asymmetric gate structure and method
Disclosed is a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a replacement metal gate (RMG) structure that includes a first section, which traverses a semiconductor body at a channel region in a first-type well, and a second section, which is adjacent to the first section and which traverses the semiconductor body at a drain drift region in a second-type well. The RMG structure includes, in both sections, a first-type work function layer and a second-type work function layer on the first-type work function layer. However, the thickness of the first-type work function layer in the first section is greater than the thickness in the second section such that the RMG structure is asymmetric. Thus, threshold voltage (Vt) at the first section is greater than Vt at the second section and the LDMOSFET has a relatively high breakdown voltage (BV). Also disclosed are methods for forming the LDMOSFET. |
| US11342452B2 |
MOSFET, having a semiconductor base substrate with a super junction structure, method of manufacturing the MOSFET, and power conversion circuit having the MOSFET
A MOSFET includes: a semiconductor base substrate having an n-type column region and a p-type column region, the n-type column region and the p-type column region forming a super junction structure; and a gate electrode formed by way of a gate insulation film. Assuming a region of the semiconductor base substrate which provides a main operation of the MOSFET as an active region, a region of the semiconductor base substrate maintaining a withstand voltage of the MOSFET as an outer peripheral region, and a region of the semiconductor base substrate disposed between the active region and the outer peripheral region as an active connecting region, out of the active region, the active connecting region, and the outer peripheral region of the semiconductor base substrate, the crystal defects are formed only in the active region and the active connecting region. |
| US11342447B2 |
Sputtering target for insulating oxide film, method for forming insulating oxide film, and method for producing field-effect transistor
A sputtering target for an insulating oxide film, the sputtering target including a sintered body including a lanthanum oxide and at least one selected from the group consisting of a beryllium oxide, a magnesium oxide, a calcium oxide, a strontium oxide, and a barium oxide, wherein lanthanum has highest molar ratio among elements other than oxygen contained in the sintered body. |
| US11342446B2 |
Nanosheet field effect transistors with partial inside spacers
A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib. |
| US11342444B2 |
Dielectric spacer to prevent contacting shorting
A method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ILD to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. A portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. The method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ILD being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. The contact plug is between opposite portions of the contact spacer. |
| US11342443B2 |
Process of forming an electronic device including a transistor structure
An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties. |
| US11342442B2 |
Semiconductor product comprising a heteroepitaxial layer grown on a seed area of a nanostructured pedestal
A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed. |
| US11342441B2 |
Method of forming a seed area and growing a heteroepitaxial layer on the seed area
A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed. |
| US11342438B1 |
Device with heteroepitaxial structure made using a growth mask
A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed. |
| US11342437B2 |
Semiconductor device and method for fabricating the same
A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material. |
| US11342432B2 |
Gate-all-around integrated circuit structures having insulator fin on insulator substrate
Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin. |
| US11342431B2 |
Thin film transistor and manufacturing method thereof, array substrate and display device
A thin film transistor and a manufacturing method thereof, an array substrate and a display device are provided. The thin film transistor is formed on a substrate and includes: an active layer on the substrate, the active layer including a source region, a drain region, and a channel region between the source region and the drain region; a first gate electrode on a side of the active layer away from the substrate; and a second gate electrode on a side of the first gate electrode away from the substrate, wherein a thickness of the first gate electrode is smaller than a thickness of the second gate electrode. |
| US11342429B2 |
Memory first process flow and device
A semiconductor device and method of making the same are disclosed. The semiconductor device includes a memory gate on a charge storage structure formed on a substrate, a select gate on a gate dielectric on the substrate proximal to the memory gate, and a dielectric structure between the memory gate and the select gate, and adjacent to sidewalls of the memory gate and the select gate, wherein the memory gate and the select gate are separated by a thickness of the dielectric structure. Generally, the dielectric structure comprises multiple dielectric layers including a first dielectric layer adjacent the sidewall of the memory gate, and a nitride dielectric layer adjacent to the first dielectric layer and between the memory gate and the select gate. Other embodiments are also disclosed. |
| US11342427B2 |
3D directed self-assembly for nanostructures
A method for forming a device includes receiving a substrate having nano-channels positioned over the substrate. A gate is formed all around a cross-section of the nano-channels, and the nano-channels extend in a direction parallel to a working surface of the substrate in a manner such that first nano-channels are positioned vertically above second nano-channels in a vertical stack. The method includes depositing a polymer mixture on the substrate that fills the open spaces around the nano-channels, causing self-assembly of the polymer mixture resulting in forming polymer cylinders extending parallel to the working surface of the substrate and perpendicular to the nano-channels, and metalizing the polymer cylinders sufficient to create an electrical connection to terminals of the nano-channels. |
| US11342425B2 |
Semiconductor device having needle-shape field plate trenches and needle-shaped gate trenches
A semiconductor device includes: a semiconductor substrate; a plurality of needle-shaped field plate trenches and a plurality of needle-shaped gate trenches formed in the semiconductor substrate and interspersed with one another; a first dielectric layer above the semiconductor substrate; a gate interconnect structure including electrically conductive lines separated from the semiconductor substrate by the first dielectric layer and first conductive vias extending through the first dielectric layer to connect the electrically conductive lines to gate electrodes in the needle-shaped gate trenches; and a field plate interconnect structure electrically isolated from the gate interconnect structure and including second conductive vias that extend through the first dielectric layer and connect to field plates in the needle-shaped field plate trenches. |
| US11342422B2 |
Method of manufacturing semiconductor device and associated memory device
A method of manufacturing a semiconductor device is disclosed. The method includes providing a substrate including a channel region for conducting current; shaping the substrate to form a protruding plane, a bottom plane and a side plane connected between the protruding plane and the bottom plane for the channel region; forming an oxide layer covering the channel region; forming a ferroelectric material strip, extending in a first direction, on a protruding plane of the oxide layer; and forming a gate strip, extending in a second direction orthogonal with the first direction, on the ferroelectric material strip and a side plane and a bottom plane of the oxide layer. |
| US11342421B1 |
Recessed access device and manufacturing method thereof
A method of manufacturing a recessed access device includes the following operations. A first trench is formed in a substrate. A first gate oxide layer is formed on an inner surface of the first trench. A sacrificial layer is formed in a bottom of the first trench, in which a portion of the first gate oxide layer above the sacrificial layer is exposed from the first trench. The portion of the first gate oxide layer is removed to expose a sidewall of the first trench. The sidewall of the first trench is oxidized to form a second gate oxide layer within the substrate, in which the second gate oxide layer is in contact with the first gate oxide layer. The sacrificial layer is removed to form a second trench. |
| US11342420B2 |
Heterojunction devices and methods for fabricating the same
Current conducting devices and methods for their formation are disclosed. Described are vertical current devices that include a substrate, an n-type material layer, a plurality of p-type gates, and a source. The n-type material layer disposed on the substrate and includes a current channel. A plurality of p-type gates are disposed on opposite sides of the current channel. A source is disposed on a distal side of the current channel with respect to the substrate. The n-type material layer comprises beta-gallium oxide. |
| US11342417B2 |
Semiconductor structure of trench transistors and manufacturing method thereof
A structure of trench transistors includes the following elements. A substrate serves as a drain of the structure of trench transistors. An epitaxial layer is disposed on the substrate. A plurality of trenches are disposed in the epitaxial layer. A plurality of gate insulator layers are respectively disposed on the inner surfaces of the trenches. A plurality of gates are respectively disposed on the gate insulator layers. A plurality of first base regions are respectively disposed in the epitaxial layer between the adjacent trenches, and have a first depth from the top surface of the epitaxial layer. A plurality of second base regions are respectively disposed in the epitaxial layer adjacent to the sidewalls of the trenches, and each has a second depth from the bottom surface of the first base region. A plurality of sources are respectively disposed in the first base region beside the sidewalls of the trenches. |
| US11342416B2 |
Semiconductor device
A semiconductor device is provided, including: a semiconductor substrate; a first-conductivity-type drift region provided in the semiconductor substrate; a gate trench portion extending in a predetermined extending direction in a plane of the upper surface of the semiconductor substrate; a mesa portion provided in contact with the gate trench portion in an array direction orthogonal to the extending direction; a first-conductivity-type accumulation region provided above the drift region and in contact with the gate trench portion, and having a higher doping concentration than the drift region; a second-conductivity-type base region provided above the accumulation region and in contact with the gate trench portion; and a second-conductivity-type floating region provided below the accumulation region and in contact with the gate trench portion, and provided in a part of the mesa portion in the array direction. |
| US11342415B2 |
Semiconductor devices and method of manufacturing the same
A semiconductor device, includes: gate electrodes spaced apart from each other and on a substrate; channel structures penetrating the gate electrodes, each of channel structures including a channel layer, a gate dielectric layer between the channel layer and the gate electrodes, a channel insulating layer filling between the channel layers, a channel pad on the channel insulating layer; and separation regions penetrating the gate electrodes, and spaced apart from each other, wherein the gate dielectric layer extends upwardly, further than the channel layer upwardly such that a portion of an inner side surface of the gate dielectric layer contacts the channel pad, the channel pad includes a lower pad on an upper end of the channel layer and the inner side surface of the gate dielectric layer, and having a first recess between the inner side surfaces of the gate dielectric layer; and an upper pad having a first portion in the first recess and a second portion extending from the first portion in a direction, parallel to an upper surface of the substrate on the first portion. |
| US11342413B2 |
Selective liner on backside via and method thereof
A method includes providing a structure having a substrate, a fin, source/drain (S/D) features, an isolation structure adjacent to sidewalls of the fin, one or more channel layers over a first dielectric layer and connecting the S/D features, and a gate structure engaging the one or more channel layers. The method further includes thinning down the structure from its backside until the fin is exposed and selectively etching the fin to form a trench that exposes surfaces of the S/D features, the first dielectric layer, and the isolation structure. The method further includes forming a silicide feature on the S/D features and depositing an inhibitor on the silicide feature but not on the surface of the first dielectric layer and the isolation structure, depositing a dielectric liner layer on the surfaces of the isolation structure and the first dielectric layer but not on the inhibitor, and selectively removing the inhibitor. |
| US11342411B2 |
Cavity spacer for nanowire transistors
A transistor structure includes a base and a body over the base. The body comprises a semiconductor material and has a first end portion and a second end portion. A gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. A source is in contact with the first end portion and a drain is in contact with the second end portion. A first spacer material is on opposite sides of the gate electrode and above the first end portion. A second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. The second spacer material is below and in contact with a bottom surface of the source and the drain. |
| US11342409B2 |
Isolation regions in integrated circuit structures
Disclosed herein are isolation regions in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC component may include: a first region including silicon; a second region including alternating layers of a second material and a third material, wherein the second material includes silicon and germanium, the third material includes silicon, and individual ones of the layers in the second region has a thickness that is less than 3 nanometers; and a third region including alternating layers of the second material and the third material, wherein individual ones of the layers in the third region has a thickness that is greater than 3 nanometers, and the second region is between the first region and the third region. |
| US11342408B2 |
Metal-insulator-metal structure and methods of fabrication thereof
The present disclosure is directed to a method of fabrication a semiconductor structure. The method includes providing a substrate and forming a bottom electrode over the substrate, wherein a terminal end of the bottom electrode has a tapered sidewall. The method also includes depositing an insulating layer over the bottom electrode and forming a top electrode over the insulating layer, wherein a terminal end of the top electrode has a vertical sidewall. |
| US11342404B2 |
Organic light emitting diode display device including etch stop layer
An organic light emitting diode display including: a substrate; a TFT on the substrate; a planarization layer on the TFT; a pixel electrode on the planarization layer, wherein the pixel electrode includes upper and lower layers including a transparent conductive oxide and an intermediate layer including silver; an etch stop layer on the pixel electrode, wherein an upper surface of the pixel electrode is exposed by the etch stop layer; a partition on the etch stop layer, wherein the upper surface of the pixel electrode is exposed by the partition; an organic emission layer on the upper surface of the pixel electrode where the upper surface of the pixel electrode is exposed by the etch stop layer and the partition; and a common electrode on the organic emission layer and the partition, wherein the etch stop layer covers an edge and a side surface of the pixel electrode. |
| US11342399B2 |
Array substrate, driving method thereof, fabrication method thereof, and display apparatus
An array substrate may include a dielectric layer (1), a plurality of pixel units (2) on the dielectric layer (1), auxiliary light emitting elements (3), and a fingerprint recognition layer (4) on a side of the dielectric layer (1) opposite from the pixel units (2). Each of the pixel units (2) may comprise transparent display elements (21). The fingerprint recognition layer (4) may comprise fingerprint recognition elements (41). The fingerprint recognition elements (41) may be configured to receive light emitted by the auxiliary light emitting elements (3) and reflected by a touch control body (10) to identify fingerprint information. |
| US11342393B2 |
Method for manufacturing OLED light emitting device, OLED light emitting device and OLED display device
The present disclosure relates to a method for manufacturing an OLED light emitting device, an OLED light emitting device, and an OLED display device. The method for manufacturing an OLED light emitting device according to an embodiment of the present disclosure includes forming a pixel defining layer on a substrate, wherein the pixel defining layer comprises a lyophilic material or a lyophobic material and the pixel defining layer comprises a plurality of openings which are spaced apart from each other; forming an anode layer on the substrate and in each opening; adding a preset solvent having a property opposite to that of the lyophilic material or the lyophobic material of the pixel defining layer in an OLED film layer ink; and ink-jet printing the OLED film layer ink on the anode layer and in each opening to form an OLED film layer. |
| US11342392B2 |
Display panel and manufacturing method thereof
A display panel and a manufacturing method thereof are disclosed. The display panel includes: a base substrate; a first sub-pixel disposed on the base substrate and including a first light-emitting device configured to emit visible light for display operation; a second a light-emitting device overlapped with the first light-emitting device in a direction perpendicular to the base substrate and configured to emit infrared light; and a first photosensitive device disposed on the base substrate and configured to sense light obtained after the infrared light is reflected. |
| US11342390B2 |
Display panel, display device and a method for manufacturing a display panel
Provided are a display panel, a display device and a method for manufacturing a display panel. The display panel includes a display area including a first display area and a second display area. The second display area is multiplexed as a sensor reserved area. The second display area includes a light transmitting area and a light emitting area. The first display area is provided with a plurality of organic light emitting units. The light emitting area of the second display area is provided with a plurality of Micro LEDs. The second display area is further provided with a wall structures disposed in gaps between the plurality of Micro LEDs and the plurality of organic light emitting units and gaps between adjacent ones of the plurality of Micro LEDs. |
| US11342388B2 |
Organic light-emitting display apparatus comprising quantum dots
An organic light-emitting display apparatus includes a substrate; a pixel electrode over the substrate; a pixel-defining layer including an opening that exposes at least a portion of the pixel electrode; an intermediate layer, which is over the portion of the pixel electrode exposed by the opening and includes an organic emission layer; a counter electrode over the intermediate layer; and an encapsulating structure, which is over the counter electrode and includes at least one inorganic layer and at least one organic layer, and the at least one organic layer includes quantum dots and is in the opening. |
| US11342386B2 |
Array substrate and display device each having a data line connecting sub-pixels of different colors
An array substrate and a display device are provided. The array substrate includes at least one data line and a plurality of sub-pixel groups arranged in an array along a first direction and a second direction. At least one sub-pixel group includes two rows of sub-pixels, one row of the two rows of sub-pixels includes a first color sub-pixel and a second color sub-pixel, and the other row of the two rows of sub-pixels includes a third color sub-pixel; the first color sub-pixel, the second color sub-pixel and the third color sub-pixel in each sub-pixel group are connected to a same data line of the at least one data line. |
| US11342385B2 |
Pixel arrangement structure, display substrate, display device, and mask plate group
A pixel arrangement structure, a display substrate, a display device, and a mask plate group. The pixel arrangement structure includes multiple minimum repeat units arranged in an array; each minimum repeat unit includes a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel; a first connecting line between the centers of the first color sub-pixel and the second color sub-pixel extends along a first direction, and a second connecting line between the centers of the first color sub-pixel and the third color sub-pixel extends along a second direction; the orthographic projection of the first color sub-pixel on a first straight line falls into the orthographic projection of the third color sub-pixel on the first straight line, and the orthographic projection of the first color sub-pixel on a second straight line falls into the orthographic projection of the second color sub-pixel on the second straight line. |
| US11342384B2 |
Pixel arrangement, manufacturing method thereof, display panel, display device and mask
A pixel arrangement including: first groups of sub-pixels arranged in a first direction, each of the first groups including first sub-pixels and third sub-pixels arranged alternately; and second groups of sub-pixels arranged in the first direction, each of the second groups including third sub-pixels and second sub-pixels arranged alternately. The first groups and the second groups are alternately arranged in a second direction perpendicular to the first direction. The first groups and the second groups are arranged to form third groups of sub-pixels arranged in the second direction and fourth groups of sub-pixels arranged in the second direction. The third groups and the fourth groups are alternately arranged in the first direction. Each of the third groups includes first sub-pixels and third sub-pixels arranged alternately. Each of the fourth groups includes third sub-pixels and second sub-pixels arranged alternately. |
| US11342376B2 |
Light emitting diode, display substrate and transfer method
Provided are a light emitting diode, a display substrate and a transfer method. The transfer method includes: preparing a transfer substrate and the display substrate respectively, wherein the transfer substrate includes a plurality of light emitting diodes arranged in a matrix; aligning the transfer substrate with the display substrate, wherein first magnetic layers of the light emitting diodes on the transfer substrate correspond to second magnetic layers of the sub-pixels on the display substrate one by one; and driving the transfer substrate to approach the display substrate, so that the light emitting diodes on the transfer substrate are positioned to fall onto the sub-pixels of the display substrate by action of magnetic attraction forces generated by the first magnetic layers and the second magnetic layers. |
| US11342374B2 |
Mechanisms for forming image-sensor device with deep-trench isolation structure
An image-sensor device is provided. The image-sensor device includes a semiconductor substrate and a radiation-sensing region in the semiconductor substrate. The image-sensor device also includes a doped isolation region in the semiconductor substrate and a dielectric film extending into the doped isolation region from a surface of the semiconductor substrate. A portion of the doped isolation region is between the dielectric film and the radiation-sensing region. |
| US11342373B2 |
Manufacturing method of image sensing device
A method for manufacturing an image sensing device includes forming an interconnection layer over a front surface of a semiconductor substrate. A trench is formed to extend from a back surface of the semiconductor substrate. An etch stop layer is formed along the trench. A buffer layer is formed over the etch stop layer. An etch process is performed for etching the buffer layer. The buffer layer and the etch stop layer include different materials. |
| US11342370B2 |
Solid-state image pickup device and method of making the same
A solid-state image pickup device includes a semiconductor substrate in which photoelectric conversion units are arranged. An insulator is disposed on the semiconductor substrate. The insulator has holes associated with the respective photoelectric conversion units. Members are arranged in the respective holes. A light-shielding member is disposed on the opposite side of one of the members from the semiconductor substrate, such that only the associated photoelectric conversion unit is shielded from light. In the solid-state image pickup device, the holes are simultaneously formed and the members are simultaneously formed. |
| US11342368B2 |
Image sensors for distance measurement
An image sensor includes a semiconductor substrate including a first surface and a second surface and further includes a well region and a first floating diffusion region that are each adjacent to the first surface. The image sensor includes a first vertical transmission gate and a second vertical transmission gate isolated from direct contact with each other and each extend from the first surface of the semiconductor substrate and in a thickness direction of the semiconductor substrate through at least a portion of the well region. The image sensor includes a first storage gate between the first vertical transmission gate and the first floating diffusion region and on the first surface of the semiconductor substrate. The image sensor includes a first tap transmission gate between the first storage gate and the first floating diffusion region and on the first surface of the semiconductor substrate. |
| US11342361B2 |
Display device
A display device includes a substrate including a pixel area and a peripheral area located outside the pixel area; pixels located in the pixel area; power supply lines configured to provide an operating power to the pixels; and a plurality of data fanout wires configured to provide data signals to the pixels, wherein, in at least a portion of the peripheral area, the power supply lines and the plurality of data fanout wires are arranged on a same layer. |
| US11342360B2 |
Array substrate and display device
According to an aspect, an array substrate includes a first scan line, a second scan line, and a signal line. A semiconductor film has a coupling portion coupling one end of a first linear portion to one end of a second linear portion. Another end of the first linear portion of the semiconductor film and another end of the second linear portion of the semiconductor film are coupled to the signal line. In a plan view, the semiconductor film is disposed between the first scan line and the second scan line, the first linear portion intersects two first gate electrodes, and the second linear portion intersects two second gate electrodes. |
| US11342359B2 |
Display panel and electronic device
The present application proposes a display panel, including a display area and a non-display area surrounding the display area, wherein the display panel includes: a plurality of metal traces and a plurality of color resist blocks located in the display area; and a test key located in the non-display area, wherein the test key includes a plurality of color resist patterns and a plurality of metal patterns, each of the color resist patterns corresponds to a corresponding one of the color resist blocks, each of the metal patterns corresponds to one of the metal traces, and each of the color resist patterns is disposed correspondingly between adjacent ones of the metal patterns. |
| US11342357B2 |
Semiconductor device
A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions. |
| US11342353B2 |
Semiconductor memory device having three-dimensional structure and method for manufacturing the same
A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction. |
| US11342351B2 |
Three-dimensional semiconductor device
A three-dimensional semiconductor device includes an upper substrate, a gate-stacked structure on the upper substrate, the gate-stacked structure including gate electrodes stacked within a memory cell array region, while being spaced apart from each other in a direction perpendicular to a surface of the upper substrate, and extending into an extension region adjacent to the memory cell array region to be arranged within the extension region to have a staircase shape, and at least one through region passing through the gate-stacked structure within the memory cell array region or the extension region, the at least one through region including a lower region and an upper region wider than the lower region. |
| US11342350B2 |
Semiconductor memory device with improved operation speed
A semiconductor memory device is provided. The semiconductor memory device includes a memory cell array disposed on a substrate, a bit line connected to the memory cell array, a peripheral circuit disposed between the memory cell array and the substrate, the peripheral circuit including a transistor, a conductive line disposed between the memory cell array and the transistor, a lower connection structure connecting the conductive line and the transistor, and two or more upper connection structures connecting the bit line and the conductive line, the two or more upper connection structures being spaced apart from each other. |
| US11342348B2 |
Non-volatile semiconductor memory device and manufacturing method thereof
This non-volatile semiconductor memory device includes a memory cell array including NAND cell units formed in a first direction vertical to a surface of a semiconductor substrate. A local source line is electrically coupled to one end of the NAND cell unit formed on the surface of the substrate. The memory cell array includes: a laminated body where plural conductive films, which are to be control gate lines of memory cells or selection gate lines of selection transistors, are laminated sandwiching interlayer insulating films; a semiconductor layer that extends in the first direction; and an electric charge accumulating layer sandwiched between: the semiconductor layer and the conductive film. The local source line includes a silicide layer. The electric charge accumulating layer is continuously formed from the memory cell array to cover a peripheral area of the silicide layer. |
| US11342341B2 |
Integrated circuit layout, method, structure, and system
A method of generating an IC layout diagram includes positioning a first active region between second and third active regions, intersecting the first active region with first through fourth gate regions to define gate locations of first and second anti-fuse bits, aligning first and second conductive regions between the first and second active regions, thereby intersecting the first conductive region with the first gate region and the second conductive region with the fourth gate region, and aligning third and fourth conductive regions between the first and third active regions, thereby either intersecting the third and fourth conductive regions with the first and third gate regions, or intersecting the third and fourth conductive regions with the second and fourth gate regions. At least one of positioning or intersecting the first active region, or aligning the first and second or third and fourth conductive regions is executed by a processor. |
| US11342340B2 |
Layout of static random access memory periphery circuit
A static random access memory (SRAM) periphery circuit includes a first n-type transistor and a second n-type transistor that are disposed in a first well region of first conductivity type, the first well region occupies a first distance in a row direction equal to a bitcell-pitch of an SRAM array. The SRAM periphery circuit includes a first p-type transistor and a second p-type transistor that are disposed in a second well region of second conductivity type. The second well region occupies a second distance in the row direction equal to the bitcell-pitch of the SRAM array. The second well region is disposed adjacent to the first well region in the row direction. |
| US11342333B2 |
Semiconductor device
A semiconductor device includes a semiconductor substrate having a cell region and a dummy region surrounding the cell region, a plurality of memory pillar structures, and a supporting layer. The memory pillar structures are on the cell region. The supporting layer is over the semiconductor substrate, interconnecting the memory pillar structures, and having a plurality of first and second opening patterns on the cell region. A first number of the memory pillar structures surround each of the first opening patterns, and a second number of the memory pillar structures surround each of the second opening patterns. The first opening patterns are different from the second opening patterns, the first number is different from the second number, and at least one of the first opening patterns and at least one of the second opening patterns are on a central portion of the cell region. |
| US11342331B2 |
Semiconductor device including an air spacer and a method for fabricating the same
A semiconductor device is provided including a substrate including a trench. A first conductive pattern is disposed within the trench. The first conductive pattern has a width smaller than a width of the trench. A first spacer extends along at least a portion of a side surface of the first conductive pattern and the trench. A second spacer at least partially fills the trench adjacent to the first spacer. An air spacer is provided including a first portion between the first spacer and the second spacer, and a second portion disposed on the second spacer and the first portion. A width of the second portion of the air spacer is greater than a width of the first portion of the air spacer. |
| US11342329B2 |
Semiconductor memory device and method of fabricating the same
A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer. |
| US11342327B2 |
Stacked transistor layout
An apparatus is provided which comprises: a first transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor body, a second transistor body comprising one or more semiconductor materials and having a length comprising a source region and a drain region with a channel region therebetween, wherein the second transistor body is over the first dielectric layer and wherein the length of the second transistor body is non-parallel to the length of the first transistor body, and a gate coupled with the channel regions of both the first transistor body and the second transistor body. Other embodiments are also disclosed and claimed. |
| US11342325B2 |
Integration of multiple fin structures on a single substrate
Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures. |
| US11342321B2 |
Manufacturing method of package on package structure
A manufacturing method of a package-on-package structure includes at least the following steps. A plurality of conductive bumps of a first package is attached to a tape carrier. A second package is coupled to the first package opposite to the plurality of conductive bumps. When coupling the second package, the plurality of conductive bumps are deformed to form a plurality of deformed conductive bumps, and a contact area between the tape carrier and the respective deformed conductive bump increases. |
| US11342318B2 |
Optical communication apparatus
There is provided an optical communication device capable of minimum suppressing inter-signal interference of inductors mounted to enable a transmission signal to be transmitted and received with a high frequency. The optical communication device comprises a sub-package as a subassembly in each of a plurality of signal channels. The sub-package includes a substrate on which an optical semiconductor and an IC are flip-chip connected. The optical semiconductor includes a pair of photodiodes receiving a differential optical signal and outputting a differential current signal. The IC includes a transimpedance amplifier converting the differential current signal from the optical semiconductor to a voltage signal. The optical semiconductor has a pair of inductors formed for each of the pair of photodiodes and a ground wiring formed so as to surround the formed pair of inductors. |
| US11342316B2 |
Semiconductor package
A semiconductor package includes a first substrate, a second substrate, a conductive component, an electronic component and a passive component. The conductive component is disposed between the first substrate and the second substrate, wherein the first substrate and the second substrate are separated from each other by an interval. The electronic component and the passive component are disposed within the interval. |
| US11342311B2 |
LED-filaments and LED-filament lamps utilizing manganese-activated fluoride red photoluminescence material
An LED-filament comprising: a partially light-transmissive substrate; a plurality of blue LED chips mounted on a front face of the substrate; first broad-band green to red photoluminescence materials and a first narrow-band manganese-activated fluoride red photoluminescence material covering the plurality of blue LED chips and the front face of the substrate; and second broad-band green to red photoluminescence materials covering the back face of the substrate. The LED-filament can further comprise a second narrow-band manganese-activated fluoride red photoluminescence material on the back face of the substrate in an amount that is less than 5 wt % of a total red photoluminescence material content on the back face of the substrate. |
| US11342308B2 |
Semiconductor device and manufacturing method for semiconductor device
A semiconductor device is provided with a first semiconductor chip and a second semiconductor chip that are arranged so as to oppose each other. The first semiconductor chip has a first connecting portion provided in a first hole portion, and the second semiconductor chip has an electrically conductive second connecting portion that is composed of a concave metal film formed on the front surface of a second electrode portion, the side surface of a second hole portion, and the front surface of a second protective film. The first electrode portion and the second electrode portion are electrically connected via the first connecting portion and the second connecting portion. |
| US11342306B2 |
Multi-chip wafer level packages
Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip. |
| US11342305B2 |
Microelectronic assemblies with communication networks
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die. |
| US11342298B2 |
Die stack arrangement comprising a die-attach-film tape and method for producing same
A device includes a base substrate with a sensor component arranged thereon; a spacer layer on the base substrate, wherein the spacer layer is structured in order to predefine a cavity region, in which the sensor component is arranged in an exposed fashion on the base substrate, and a DAF tape element (DAF=Die-Attach-Film) on a stack element, wherein the DAF tape element mechanically fixedly connects the stack element to the spacer layer arranged on the base substrate and to obtain the cavity region. |
| US11342295B2 |
Electronic assembly, package structure having hollow cylinders and method of fabricating the same
A package structure includes at least one semiconductor die, a plurality of hollow cylinders, an insulating encapsulant, a redistribution layer and through holes. The plurality of hollow cylinders is surrounding the at least one semiconductor die. The insulating encapsulant has a top surface and a bottom surface opposite to the top surface, wherein the insulating encapsulant encapsulates the at least one semiconductor die and the plurality of hollow cylinders. The redistribution layer is disposed on the top surface of the insulant encapsulant and over the at least one semiconductor die. The through holes are penetrating through the plurality of hollow cylinders. |
| US11342294B2 |
Semiconductor device and method of forming protrusion e-bar for 3D SiP
A semiconductor device has a first substrate and a semiconductor die disposed over the first substrate. A second substrate has a multi-layered conductive post. The conductive post has a first conductive layer and a second conductive layer formed over the first conductive layer. The first conductive layer is wider than the second conductive layer. A portion of the conductive post can be embedded within the second substrate. The second substrate is disposed over the first substrate adjacent to the semiconductor die. An encapsulant is deposited around the second substrate and semiconductor die. An opening is formed in the second substrate aligned with the conductive post. An interconnect structure is formed in the opening to contact the conductive post. A discrete electrical component is disposed over a surface of the first substrate opposite the semiconductor die. A shielding layer is formed over the discrete electrical component. |
| US11342290B2 |
Semiconductor device
A semiconductor device includes a lead frame, a transistor, and an encapsulation resin. The lead frame includes a drain frame, a source frame, and a gate frame. The drain frame includes drain frame fingers. The source frame includes source frame fingers. The drain frame fingers and the source frame fingers are alternately arranged in a first direction and include overlapping portions as viewed from a first direction. In a region where each drain frame finger overlaps the source frame fingers as viewed in the first direction, at least either one of the drain frame fingers and the source frame fingers are not exposed from the back surface of the encapsulation resin. |
| US11342289B2 |
Vertical power plane module for semiconductor packages
The present disclosure relates to a semiconductor package, that may include a package substrate, a base die arranged on and electrically coupled to the package substrate, and at least one power plane module arranged on the package substrate at a periphery of the base die. The power plane module may include a top surface and a bottom surface, and at least one vertical interleaving metal layer electrically coupled at the bottom surface to the package substrate. The semiconductor package may further include a semiconductor device including a first section disposed on the base die, and a second section disposed on the power plane module, wherein the second section of the semiconductor device may be electrically coupled to the at least one vertical interleaving metal layer at the top surface of the power plane module. |
| US11342284B2 |
Semiconductor chip
A chip is provided. The chip is provided with a circuit block. The circuit block includes a first transistor and a second transistor. The first transistor is divided into a plurality of first sub-transistors connected in parallel. The second transistor is divided into a plurality of second sub-transistors connected in parallel. The first sub-transistors and the second sub-transistors are disposed in a first row and a second row of the circuit block in a staggered manner. The first transistors disposed in the first row and the second row respectively receive a first input signal through different signal lines. The second transistors disposed in the first row and the second row respectively receive a second input signal through different signal lines. |
| US11342283B2 |
Package substrate and semiconductor package including the same
Provided a package substrate including an insulation substrate, a conductive layer provided in the insulation substrate, upper pads provided on an upper surface of the insulation substrate and electrically connected to the conductive layer, lower pads provided on a lower surface of the insulation substrate and electrically connected to the conductive layer, and at least one trench provided at a portion of the insulation substrate adjacent to at least one of the upper pads and configured to block stress, which is generated by an expansion of the insulation substrate, from spreading to the at least one of the upper pads. |
| US11342282B2 |
Semiconductor device package including a reinforcement structure on an electronic component and method of manufacturing the same
A semiconductor device package includes an electronic component, an electrical contact and a reinforcement layer. The electronic component has a first conductive layer on a first surface of the electronic component. The electronic component has a through-silicon-via (TSV) penetrating the electronic component and electrically connected to the first conductive layer. The electrical contact is disposed on the first surface of the electronic component and electrically connected to the first conductive layer. The reinforcement layer is disposed on the first surface of the electronic component. |
| US11342280B2 |
Module and method for manufacturing the same
A module includes: a substrate having a main surface and a side surface; an electronic component mounted on the main surface; a sealing resin that covers the main surface and the electronic component; and a shield film that covers a surface of the sealing resin and the side surface of the substrate. The sealing resin includes: a resin component containing an organic resin as a main component; and a granular filler containing an inorganic oxide as a main component. On a surface of the sealing resin, which is in contact with the shield film, parts of some grains of the filler are exposed from the resin component, a surface of the resin component includes a nitrogen functional group, and the shield film is formed of a metal that is a passivation metal and a transition metal or an alloy containing the metal. |
| US11342279B2 |
Semiconductor device and amplifier having bonding wire and conductive member
A semiconductor device includes a ground plane, a capacitor disposed on the ground plane and having a first top surface, a semiconductor chip disposed on the ground plane and having a second top surface, a bonding wire connecting the first top surface and the second top surface, and a conductive member disposed on the ground plane. The conductive member is electrically connected to the ground plane. The bonding wire extends in a first direction in a planar view normal to the ground plane. The conductive member is positioned apart from the bonding wire in a second direction orthogonally intersecting in the planar view with the first direction. |
| US11342273B2 |
Package structure of integrated passive device and manufacturing method thereof, and substrate
Disclosed are a package structure of an integrated passive device and a manufacturing method thereof and a substrate. The method includes: providing an organic frame having a chip embedding cavity and a metal pillar, laminating at least one layer of first dielectric on an upper surface of the organic frame, and processing the first dielectric by photolithography to form an opening correspondingly above the chip embedding cavity; mounting an electronic component in the chip embedding cavity through the opening, the electronic component including an upper and lower electrodes; laminating and curing a second dielectric into the chip embedding cavity and on an upper surface of the first dielectric, thinning the first and second dielectrics to expose the upper and lower electrodes, upper and lower surfaces of the metal pillar; performing metal electroplating to form a circuit layer communicated with the upper and lower electrodes and the metal pillar. |
| US11342272B2 |
Substrate structures, and methods for forming the same and semiconductor package structures
A substrate structure, a method for manufacturing the same and a semiconductor package structure including the same are provided. The substrate structure includes a substrate, a first electronic component, a second electronic component and a plurality of metal layers. The first electronic component is disposed within the substrate. The second electronic component is disposed within the substrate and arranged in a horizontal direction with the first electronic component. The metal layers are disposed above an upper surface of the substrate. The number of metal layers above the first electronic component is greater than the number of metal layers above the second electronic component. |
| US11342271B2 |
Electronic components for soft, flexible circuitry layers and methods therefor
A flexible circuitry layer may comprise a conductive mesh including a circuitry trace; and an interfacing component, comprising: a flexible substrate; a terminal electrically connected to the circuitry trace; and a connector configured to be detachably connected to an external device. |
| US11342270B2 |
Fan-out package with rabbet
A system integrating a fan-out package, including a first semiconductor die, with a second semiconductor die. In some embodiments the fan-out package includes the first semiconductor die, a mold compound, covering the first semiconductor die on at least two sides, and an electrical contact, on a lower surface of the first semiconductor die. The fan-out package may have a rabbet along a portion of a lower edge of the fan-out package. |
| US11342269B2 |
Package structure with reinforcement structures in a redistribution circuit structure and manufacturing method thereof
A package structure includes an insulating encapsulation, at least one semiconductor die, a redistribution circuit structure, and first reinforcement structures. The at least one semiconductor die is encapsulated in the insulating encapsulation. The redistribution circuit structure is located on the insulating encapsulation and electrically connected to the at least one semiconductor die. The first reinforcement structures are embedded in the redistribution circuit structure. A shape of the package structure includes a polygonal shape on a vertical projection along a stacking direction of the insulating encapsulation and the redistribution circuit structure, and the first reinforcement structures are located on and extended along diagonal lines of the package structure. |
| US11342268B2 |
Semiconductor devices and methods of manufacturing semiconductor devices
In one example, an electronic assembly comprises a first semiconductor device and a second semiconductor device. Each of the first semiconductor device and the second semiconductor devices comprises a substrate comprising a top surface and a conductive structure, an electronic component over the top surface of the substrate, a dielectric material over the top surface of the substrate and contacting a side of the electronic component, a substrate tab at an end of substrate and not covered by the dielectric material, wherein the conductive structure of the substrate is exposed at the substrate tab, and an interconnect electrically coupled to the conductive structure at the substrate tab of the first semiconductor device and the conductive structure at the substrate tab of the second semiconductor device. Other examples and related methods are also disclosed herein. |
| US11342265B2 |
Apparatus including a dielectric material in a central portion of a contact via, and related methods, memory devices and electronic systems
An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed. |
| US11342263B2 |
Semiconductor device including dummy patterns and peripheral interconnection patterns at the same level
A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure. |
| US11342261B2 |
Integrated circuit with an interconnection system having a multilevel layer providing multilevel routing tracks and method of manufacturing the same
Integrated circuit comprising an interconnection system comprising at least one multilevel layer comprising first parallel electrically conductive lines, the multilevel layer comprising at least three levels forming a centerline level, an upper extension line level, and a lower extension line level the levels providing multilevel routing tracks in which the lines extend. |
| US11342259B2 |
Electronic module, electronic device, manufacturing method for electronic module, and manufacturing method for electronic device
An electronic module includes an electronic part including a bottom surface and lands, the bottom surface including a first region and a third region surrounding the first region, the first lands being disposed in the third region, a printed wiring board including a main surface and second lands, the main surface including a second region and a fourth region surrounding the second region, the main surface facing the bottom surface of the electronic part, the second lands being disposed in the fourth region, solder bonding portions respectively bonding the first lands to the second lands, and a resin portion containing a cured product of a thermosetting resin and being in contact with the solder boding portions. A recess portion is provided in the second region. The resin portion is not provided in the recess portion. |
| US11342258B2 |
On-die capacitor
According to the disclosed embodiments, an on-die capacitor utilized in energy-harvest based circuits is provided. In the disclosed design, the harvester is coupled to the on-die capacitor, thus there is no need to provide power interfaces and semi-conductor devices external to the IC. The disclosed design of the on-die capacitor would reduce the overall size and cost of the IC. |
| US11342255B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor package device includes an interposer die having a semiconductor substrate and a plurality of through-silicon-vias (TSVs) extending through the semiconductor substrate. The semiconductor package device also includes a first semiconductor die spaced apart from the interposer die, a first redistribution layer disposed on a first side of the interposer die and electrically coupling the interposer die with the first semiconductor die, and a second redistribution layer on a second side of the interposer die opposite the first side. Each of the plurality of TSVs includes a sidewall tapering from a first end near the second redistribution layer to a second end near the first redistribution layer. |
| US11342254B2 |
Multi-dielectric structure in two-layer embedded trace substrate
Certain aspects of the present disclosure generally relate to an embedded trace substrate having at least two different dielectric layers with different dielectric materials and methods for fabricating the same. One example embedded trace substrate generally includes a first metal layer; a first dielectric layer disposed below the first metal layer and comprising a first dielectric material; a second dielectric layer disposed below the first dielectric layer and comprising a second dielectric material, wherein the second dielectric material of the second dielectric layer is stiffer than the first dielectric material of the first dielectric layer; and a second metal layer disposed below the second dielectric layer. |
| US11342249B2 |
Semiconductor device
The semiconductor device of the present embodiment includes a lead frame having a projection portion, the projection portion having an upper face and a side face, a semiconductor chip provided above the projection portion, and a bonding material provided between the projection portion and the semiconductor chip, the bonding material being in contact with the upper face and the side face, the bonding material bonding the lead frame and the semiconductor chip. |
| US11342241B2 |
Power module
A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches, first ends of which are coupled to the first conductor; and a plurality of second switches, first ends of which are coupled to second ends of the first switches through the third conductor, and second ends of the second switches are coupled to the second conductor, wherein projections of minimum envelope areas of the first and second switches on the first reference plane have a second overlap area, and the first and second overlap areas have an overlap region. Heat sources of the power module are evenly distributed and its parasitic inductance is low. |
| US11342240B2 |
Semiconductor device
A transistor chip (2) has an active region (7). A first seal material (5) covers a central portion of the active region (7) and does not cover a peripheral portion of the active region (7). A second seal material (6) covers the peripheral portion of the active region (7). Thermal conductivity of the first seal material (5) is higher than thermal conductivity of the second seal material (6). Permittivity of the second seal material (6) is lower than permittivity of the first seal material (5). |
| US11342239B2 |
Semiconductor package
The invention provides a semiconductor package, which may include a connection structure including one or more redistribution layers. A semiconductor chip is disposed on the connection structure and has an active surface on which a connection pad electrically connected to the redistribution layer is disposed and an inactive surface opposite to the active surface. An encapsulant is disposed on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant such that one exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is disposed on the encapsulant and covers the one exposed surface of the conductor pattern layer. |
| US11342235B2 |
Semiconductor devices including scribe lane and method of manufacturing the semiconductor devices
A semiconductor device includes a substrate including a first part and a second part, a memory cell disposed on the first part, an insulation layer disposed on the first part and the second part, the insulation layer covering the memory cell, a portion of the insulation layer on the second part including a stepped sidewall, and a first pattern group disposed on the second part and in the portion of the insulation layer and the substrate. A first sidewall of the semiconductor device corresponds to the stepped sidewall including an upper sidewall, a lower sidewall and a connecting surface connecting the upper sidewall to the lower sidewall. The lower sidewall disposed under the upper sidewall is closer to the substrate than the upper sidewall, and has surface roughness different from surface roughness of the upper sidewall. |
| US11342231B2 |
Integrated circuit device with low threshold voltage
A method of manufacturing a semiconductor device is provided. A substrate is provided. The substrate has a first region and a second region. An n-type work function layer is formed over the substrate in the first region but not in the second region. A p-type work function layer is formed over the n-type work function layer in the first region, and over the substrate in the second region. The p-type work function layer directly contacts the substrate in the second region. And the p-type work function layer includes a metal oxide. |
| US11342230B2 |
Homogeneous densification of fill layers for controlled reveal of vertical fins
In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer. |
| US11342226B2 |
Hybrid wafer dicing approach using an actively-focused laser beam laser scribing process and plasma etch process
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with an actively-focused laser beam laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits. |
| US11342225B2 |
Barrier-free approach for forming contact plugs
A method includes etching a dielectric layer of a substrate to form an opening in the dielectric layer, forming a metal layer extending into the opening, performing an anneal process, so that a bottom portion of the metal layer reacts with a semiconductor region underlying the metal layer to form a source/drain region, performing a plasma treatment process on the substrate using a process gas including hydrogen gas and a nitrogen-containing gas to form a silicon-and-nitrogen-containing layer, and depositing a metallic material on the silicon-and-nitrogen-containing layer. |
| US11342222B2 |
Self-aligned scheme for semiconductor device and method of forming the same
Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer. |
| US11342220B2 |
Structure manufacturing method and manufacturing device, and light irradiation device
There is provided a structure manufacturing method, including: preparing a wafer at least whose surface comprises Group III nitride crystal in a state of being immersed in an etching solution containing peroxodisulfate ions; and irradiating the surface of the wafer with light through the etching solution; wherein the group III nitride crystal has a composition in which a wavelength corresponding to a band gap is 310 nm or more, and during irradiation of the light, the surface of the wafer is irradiated with a first light having a wavelength of 200 nm or more and less than 310 nm under a first irradiation condition, and is irradiated with a second light having a wavelength of 310 nm or more and less than a wavelength corresponding to the band gap under a second irradiation condition controlled independently of the first irradiation condition. |
| US11342219B2 |
Chemical mechanical polishing topography reset and control on interconnect metal lines
A semiconductor structure is provided. The semiconductor structure include a substrate and a first dielectric layer having at least one via over the substrate. The first dielectric layer includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The semiconductor structure further includes a second dielectric layer containing at least one first conductive line overlying the first portion of the first dielectric layer and at least one second conductive line overlying the second portion of the first dielectric layer. The at least one first conductive line includes a first conductive portion and a conductive cap, and the at least one second conductive line including a second conductive portion having a top surface coplanar with a top surface of the conductive cap. |
| US11342218B1 |
Single crystalline silicon stack formation and bonding to a CMOS wafer
Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers. |
| US11342217B1 |
Method for improving HDP filling defects through STI etching process
The present disclosure provides a method for improving HDP filling defects through an STI etching process, comprises a wafer uniformly distributed with pixel areas and logical areas, and dividing the wafer into quadrants 1 to 4; placing the second quadrants in an etching chamber in a manner of facing to a cantilever of an etching machine; etching the wafer to form STI areas with the same depth in the pixel areas and the logical areas of the quadrants 1 to 4; removing the wafer from the etching machine and covering the STI areas of the pixel areas with a photoresist; placing the wafer on an electrostatic chuck of the etching chamber again, and enabling any quadrant except the second quadrant to face to the cantilever; continuously etching the STI areas of the logical areas of the quadrants 1 to 4 to form deep STI areas. |
| US11342213B2 |
Apparatus and method of micro-devices transfer
A method of micro-devices transfer comprising following steps of: providing a flexible carrier including a plurality of grooves which are designed in positions corresponding one-to-one to a plurality of target surface portions of an outer surface of a target member, each of the grooves has an opening in a first surface of the flexible carrier; applying at least one external force to the flexible carrier such that the opening of each of the grooves is enlarged; placing a plurality of micro-devices in the grooves respectively; releasing the at least one external force such that the micro-devices are held by the grooves of the flexible carrier and auto-aligned in positions corresponding one-to-one to the target surface portions of the outer surface of the target member; aligning and bonding the micro-devices to the target surface portions of the outer surface of the target member; and removing the flexible carrier. |
| US11342207B2 |
Micro LED transfer head
A micro LED transfer head is proposed. The micro LED transfer head includes: a holding member including a holding region that holds a micro LED by means of vacuum holding force and a non-holding region that does not hold the micro LED; and a porous member provided on top of the holding member and having arbitrary pores, wherein the holding region includes: a first holding region; and a second holding region provided above the first holding region, formed to have a larger opening area than the first holding region, and communicating with the first holding region and the porous member, whereby the micro LED transfer head selectively transfers the micro LED. |
| US11342204B2 |
Method and apparatus for cleaning semiconductor wafers
The present disclosure provides a method and a cleaning apparatus for cleaning semiconductor wafers. The cleaning apparatus includes a plurality of cleaning tanks, a dipping tank, a first robot hand, a second robot hand, and at least one drying chamber. The plurality of cleaning tanks is configured to clean a plurality of wafers held by a cassette by cleaning agents. The plurality of wafers is cleaned in the plurality of cleaning tanks through a batch process. The dipping tank is configured to rinse the plurality of wafers by a replacement agent. The at least one drying chamber is configured to dry the wafer taken by the second robot hand with single wafer process. |
| US11342195B1 |
Methods for anisotropic etch of silicon-based materials with selectivity to organic materials
Improved process flows and methods are provided that use a cyclic dry process to transfer a pattern from a patterned organic layer to an underlying silicon-containing layer. The cyclic dry process disclosed herein includes a deposition step, an etch step and a purge step, which may be repeated a number of cycles to progressively etch the exposed portions of the silicon-containing layer. Unlike conventional pattern transfer processes, the cyclic dry process described herein anisotropically etches the silicon-containing layer with high selectivity to the patterned organic layer. In doing so, the disclosed process improves pattern transfer performance and avoids problems typically seen in conventional pattern transfer processes such as, e.g., CD enlargement, CD distortion and/or complete loss of photoresist. |
| US11342192B2 |
Substrate processing method and storage medium
A technique for making etching amounts uniform in selectively etching SiGe layers formed on a wafer with respect to at least one of an Si layer, an SiO2 layer, and an SiN layer is provided. In an etching process where SiGe layers in a wafer W in which the SiGe layers and Si layers are alternately stacked and exposed in a recess are removed by side etching, ClF3 gas and HF gas are simultaneously supplied to the wafer W. Accordingly, it is possible to make the etching rates for respective SiGe layers uniform, and it becomes possible to obtain a uniform etching amount for respective SiGe layers. |
| US11342191B2 |
Structure manufacturing method, structure manufacturing apparatus and intermediate structure
There is provided a structure manufacturing method, including: preparing an etching target with at least one surface comprising group III nitride; then in a state where the etching target is immersed in an etching solution containing peroxodisulfate ions; irradiating the surface of the etching target with light through the etching solution, and generating sulfate ion radicals from the peroxodisulfate ions and generating holes in the group III nitride, thereby etching the group III nitride, wherein in the etching of the group III nitride, the etching solution remains acidic during a period for etching the group III nitride by making the etching solution acidic at a start of etching the group III nitride, and the etching is performed, with a resist mask formed on the surface. |
| US11342188B2 |
Methods for doping high-k metal gates for tuning threshold voltages
A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric. |
| US11342186B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device wherein a hydrogen concentration distribution has a first hydrogen concentration peak and a second hydrogen concentration peak and a donor concentration distribution has a first donor concentration peak and a second donor concentration peak in a depth direction, wherein the first hydrogen concentration peak and the first donor concentration peak are placed at a first depth and the second hydrogen concentration peak and the second donor concentration peak are placed at a second depth deeper than the first depth relative to the lower surface is provided. |
| US11342185B2 |
Wafer bonding method and structure thereof
Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers. |
| US11342184B2 |
Method of forming multiple patterned layers on wafer and exposure apparatus thereof
An exposure apparatus for transferring a pattern of a reticle onto a wafer is provided. The exposure apparatus includes an illumination module, a reticle stage, a projection module, a wafer stage, and a control unit. The control unit is configured to calculate an alignment setting of the reticle. The wafer includes a first layer and a second layer disposed on the first layer. The first layer includes a first alignment parameter. The second layer includes a second alignment parameter. The control unit obtains a first weighting factor predetermined according to a property of the first layer, and a second weighting factor predetermined according to a property of the second layer. The alignment setting of the reticle is calculated according to the first alignment parameter, the first weighting factor, the second alignment parameter, and the second weighting factor. |
| US11342181B2 |
Semiconductor devices and methods of manufacture
A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes. |
| US11342177B2 |
Treatment to control deposition rate
A treatment, structure and system are provided that modify the deposition process of a material that can occur over two differing materials. In an embodiment the deposition rates may be adjusted by the treatment to change the deposition rate of one of the materials to be more in line with the deposition rate of a second one of the materials. Also, the deposition rates may be modified to be different from each other, to allow for a more selective deposition over the first one of the materials than over the second one of the materials. |
| US11342175B2 |
Multi-reflecting time of flight mass analyser
A mass spectrometer comprising: a multi-reflecting time of flight (MRTOF) mass analyser or mass separator having two gridless ion mirrors 2 that are elongated in a first dimension (Z-dimension) and configured to reflect ions multiple times in a second orthogonal dimension (X-dimension) as the ions travel in the first dimension; the spectrometer configured to operate in: (i) a first mode for ions having a first rate of interaction with background gas molecules in the mass analyser or separator, such that the ions are reflected a first number of times between the ion mirrors 2; and (ii) a second mode for ions having a second, higher rate of interaction with background gas molecules in the mass analyser or separator, such that ions are reflected a second, lower number of times between the ion mirrors 2. |
| US11342173B2 |
Electrospray interface device and associated methods
Apparatus, systems, and methods in accordance with various aspects of the applicant's teachings provide for improved interfaces for providing a sample flow from a sample conduit (e.g., an analytical conduit or capillary), including those used in sample separation techniques such as CE and HPLC, to an ESI source for ionization thereby. |
| US11342171B2 |
Method for producing gaseous ammonium for ion-molecule-reaction mass spectrometry
Method for obtaining gaseous ammonium (NH4+) from an ion source, the ion source comprising a first area (1) and a second area (2) in a fluidly conductive connection, comprising the steps of a) introducing N2 and H2O into the first area (1) and second area (2) of the ion source; b) applying an ionization method to the mixture of N2 and H2O in the first area (1); c) applying at least one electric field or adjusting pressure conditions or a combination of applying at least one electric field and adjusting pressure conditions promoting flow of ions from the first area (1) to the second area (2) and inducing reactions of the ions in the second area (2); d) conducting NH4+ out of the ion source. Ion Molecule Reaction-Mass Spectrometry instrument implementing this method for producing NH4+ and then conducting NH4+ to the reaction region. |
| US11342166B2 |
Confinement ring for use in a plasma processing system
An apparatus for confining plasma within a plasma processing chamber is provided. The plasma processing chamber includes a lower electrode for supporting a substrate and an upper electrode disposed over the lower electrode. The apparatus is a confinement ring that includes a lower horizontal section extending between an inner lower radius and an outer radius of the confinement ring. The lower horizontal section includes an extension section that bends vertically downward at the inner lower radius, and the lower horizontal section further includes a plurality of slots. The confinement ring further includes an upper horizontal section extending between an inner upper radius and the outer radius of the confinement ring and a vertical section that integrally connects the lower horizontal section with the upper horizontal section. The extension section of the lower horizontal section is configured to surround the lower electrode when installed in the plasma processing chamber. |
| US11342165B2 |
Plasma processing method
In a plasma processing method, a position in height direction of an upper surface of a focus ring surrounding an edge of a substrate mounted on a supporting table in a chamber of a plasma processing apparatus is set such that the position in height direction of the upper surface of the focus ring mounted on a mounting region of the supporting table is lower than a reference position that is a position in a height direction of an upper surface of the substrate. Plasma is generated in the chamber to perform plasma processing on the substrate in a state where the position in the height direction of the upper surface of the focus ring is maintained. A negative DC voltage is applied to the focus ring in a state where the position in height direction of the upper surface of the focus ring is maintained during the plasma generation. |
| US11342158B2 |
Charged particle beam system
There is provided a charged particle beam system capable of determining the type of each cartridge precisely. An electron microscope that embodies the charged particle beam system includes a discriminator for determining the type of each cartridge based on the range or distance measured by a laser range finder. Plural cartridges are received in a magazine. The laser range finder measures the range to a selected one of the plural cartridges which is placed in a measurement position. A first cartridge of a first type included in the plural cartridges has a first measurement surface at a first distance to the laser range finder when placed in the measurement position. A second cartridge of a second type has a second measurement surface at a second range to the laser range finder when placed in the measurement position. |
| US11342156B2 |
Charged particle beam apparatus, sample alignment method of charged particle beam apparatus
A charged particle beam apparatus includes a sample stage on which a sample is mounted, a control device that controls to drive the sample stage, a linear scale that detects a position of the sample stage, laser position detection means for detecting the position of the sample stage, an optical microscope that observes the sample mounted on the sample stage, and a barrel that irradiates the sample mounted on the sample stage with an electron beam, and generates a secondary electron. Image data of a first correction sample mounted on the sample stage is acquired by the optical microscope, and position data of the sample stage is detected by the laser position detection means. The sample stage is positioned with respect to the barrel based on the image data acquired by the optical microscope and the position data of the sample stage detected by the laser position detection means. |
| US11342149B2 |
Integrated electro-mechanical actuator
The present invention provides an integrated electro-mechanical actuator and a manufacturing method for manufacturing such an integrated electro-mechanical actuator. The integrated electro-mechanical actuator comprises an electrostatic actuator gap between actuator electrodes and an electrical contact gap between contact electrodes. An inclination with an inclination angle is provided between the actuator electrodes and the contact electrodes. The thickness of this electrical contact gap is equal to the thickness of a sacrificial layer which is etched away in a manufacturing process. |
| US11342146B2 |
System and method for energy monitoring
A system and method for monitoring energy use in an electronic device. In one embodiment, an energy monitoring system includes a processor and an energy monitor module. The energy monitor module includes instructions that when executed cause the processor to receive values of measured parameters of a pulse signal that controls the switching of energy to an energy storage device in a switch mode power supply that provides power to an electronic device. The instructions also cause the processor to determine, based on the values of measured parameters, attributes of operation of the electronic device powered by the energy source during an interval corresponding to the measured parameters. The instructions further cause the processor to generate, based on the attributes of operation, a control signal that causes the electronic device to change the loading of the power supply by the electronic device. |
| US11342141B2 |
Coupler for arc flash detection systems
A system including ruggedized optic fiber cable assembly for use with an arc detection relay to protect electrical components from faults resulting in an arc flash. The cable assembly includes a pair of ruggedized ST connectors located at opposite ends of a ruggedized optical fiber cable. The cable includes an optical fiber core surrounded by a transparent gel layer and a transparent jacket surrounding the gel layer. Each ST connector includes a boot formed of a resilient material to provide shock absorption for the portion of the optical fiber cable extending through it. An accessory electronic cable is also provided, as are couplers, adapters for mounting the couplers onto walls, and sleeves with air pockets to enhance the ruggedness of the cable at points of stress, e.g., bends. |
| US11342139B1 |
Key structure
A key structure includes a keycap, a base plate, a first scissors-type connecting element, a second scissors-type connecting element and a reinforced connecting rod. The first and second scissors-type connecting elements are arranged between the keycap and the base plate. The first scissors-type connecting element includes a first inner frame and a first outer frame. The second scissors-type connecting element includes a second inner frame and a second outer frame. The keycap is movable upwardly or downwardly relative to the base plate along a specified path with the assistance of the first and second scissors-type connecting elements. The reinforced connecting rod includes a hollow rectangular main body. The first outer frame has a first extension structure. The second outer frame has a second extension structure. Moreover, two opposite sides of the hollow rectangular main body are respectively received within the first extension structure and the second extension structure. |
| US11342138B1 |
Switch device
The invention provides a switch device including a shell, an operating member, a spring, a movable conductor, a first pin, a second pin, two resistors, and two connecting conductors. The operating member is partially exposed out of the shell, and the movable conductor is displaced when the operating member is operated. One side of the shell is provided with the first pin and the spring, another side is provided with the second pin. The resistors are connected with the second pin and have different resistance values. The connecting conductors are arranged between the two pins. The first pin contacts with the movable conductor. The connecting conductors without disposal of any crossover part therebetween and respectively connected with the resistors. The connecting conductors are arranged at intervals along a displacement path of the movable conductor which contacted one connecting conductor before and after displacement and forming two conductive paths. |
| US11342137B2 |
Motor control center subunit having moveable line contacts and method of manufacture
A system and method for connecting supply power to motor control components includes use of a motor control center subunit with moveable supply power contacts. After a motor control center subunit is secured into a motor control center compartment, the supply power contacts may be advanced to engage supply power buses. For disconnection, the supply power contacts may be retracted and isolated from the buses before physical removal of the subunit. |
| US11342135B2 |
Device for switching an electrical load circuit operated with high voltage from a voltage source
The invention relates to a device for connecting and disconnecting an electrical load circuit, operated at high voltage by a voltage source, in a transportation means that is electrically driven by a drive operated at low voltage. According to the invention, a contact stud (6) is connected to the push rod (11) of a linear drive (2) and the contact stud (6) can be moved into at least two positions in a switch housing (4), wherein the switch housing (4) has, on its internal wall, at least two contact rings (5), one of which is connected to the voltage source (7) and the other is connected to the consumer circuit (8). |
| US11342133B1 |
Key structure
A key structure includes a circuit board, a triggering part and an elastic element. The elastic element includes an upper support portion, a lower support portion, an upper elastic portion and a lower elastic portion. The lower support portion is located beneath the upper support portion and connected to a peripheral region of the circuit board. The upper elastic portion is connected between the triggering part and the upper support portion. The lower elastic portion is connected between the upper support portion and the lower support portion. The lower elastic portion includes a first section and a second section connected to each other. The first section is connected to the upper support portion. The second section is connected to the lower support portion. There is a vacant space between the second section and the circuit board. |
| US11342128B2 |
Electrolytic capacitor
The electrolytic capacitor has a conductive sheet with a central portion defined by a peripheral edge, a first tail extending out from the peripheral edge in a first direction, and a second tail extending out from the peripheral edge in a second direction. The second direction is opposite the first direction. The first tail and the second tail each have a free end with a first recess at the free. |
| US11342123B2 |
Multi-layered ceramic electronic component
A multilayer ceramic electronic component includes a ceramic body including a dielectric layer and a plurality of internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, and an external electrode formed outside the ceramic body. The external electrode includes an electrode layer, and a thickness T1 of the electrode layer corresponding to a central region of the ceramic body in a thickness direction is 5 μm or more and 30 μm or less, a thickness T2 of the electrode layer corresponding to a region in which an outermost internal electrode is located is 5 μm or more and 15 μm or less, and a thickness T3 of the electrode layer corresponding to a corner portion of the ceramic body is 0.1 μm or more and 10 μm or less. |
| US11342122B2 |
Electronic component assembly and method for manufacturing the same
An electronic component assembly includes an electronic component and a mounting board. The electronic component includes a stacked body, a pair of external electrodes provided on both end surfaces of the stacked body, and an insulating layer entirely covering a first main surface of the stacked body. The mounting board includes a board main body having a mounting surface, and land electrodes on the mounting surface. The first main surface of the electronic component faces the mounting surface of the mounting board, and the pair of external electrodes are mounted on the land electrodes with solder. Both end portions of the insulating layer in the length direction of the electronic component are located on the outer side relative to both end surfaces of the stacked body at least in a cross section taken at the center in the width direction. |
| US11342114B2 |
Leakage transformer
A leakage transformer includes a secondary coil wound around a leg member of a core, and a primary coil wound around the leg member outside of the secondary coil. Between the primary coil and the secondary coil, (i) spacers of non-magnetic members and (ii) bypass cores that are magnetic members to induce therein a portion of magnetic flux generated in the core are arranged. The bypass cores are arranged with gaps therebetween in a direction of the internally induced magnetic flux. A total value of the gaps between the bypass cores is determined in accordance with a target value of leakage inductance. A maximum value of the gaps between the bypass cores is less than or equal to a value obtained by multiplying a minimum value of gaps between the bypass cores and each of the primary coil and the secondary coil by a positive coefficient less than one. |
| US11342111B2 |
Ignition coil for internal combustion engine and manufacturing method thereof
A first filler resin is disposed to cover at least an outer peripheral side of a secondary spool and a secondary coil. The second filler resin is filled inside a case and seals a cover sealant which includes a primary coil, secondary spool, a secondary coil, a center core, an outer core and the first filler resin. The connector protrudes to an outside of the case. The case has a fixing portion. The second filler resin has a lower elasticity than the first filler resin. The ignition coil is manufactured by filling the first resin inside the case, and filling the second resin after the first resin is cured. |
| US11342110B2 |
Inductor
An inductor includes a body including an internal coil having first and second end portions and an encapsulant encapsulating the internal coil and containing magnetic particles. First and second external electrodes are on external surfaces of the body and electrically connected to the internal coil. A first metal expansion portion encloses the first end portion while coming into direct contact with the first end portion of the internal coil, and may be between the body and the first external electrode. A second metal expansion portion encloses the second end portion while coming into direct contact with the second end portion of the internal coil, and may be between the body and the second external electrode. |
| US11342109B2 |
Coil component and electronic device
In an exemplary embodiment, a coil component includes: a drum core 10 that includes a winding shaft 12 and flange parts 14a, 14b; a coil 40 that includes a winding part 42 and a pair of lead parts 44a, 44b led out from the winding part 42 toward a side face 22 of the flange part 14a and then bent onto the flange part 14a along the side face 22; and a pair of external electrodes 60a, 60b provided on the outer face 17a of the flange part 14a, and connected to the pair of lead parts 44a, 44b; wherein the shortest distance L4 between the side face 22 and the outermost periphery of the winding part 42 is shorter than the shortest distance L3 between a side face 24, opposite the side face 22, of the flange part 14a, and the outermost periphery of the winding part 42. |
| US11342108B2 |
Stackable near-field communications antennas
Techniques regarding one or more NFC antennas that can comprise vertically stacked coils of electrically conductive material are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise can a first substrate layer that can comprise a first coil of electrically conductive material that can be wound in a first direction. The apparatus can also comprise a second substrate layer that can comprise a second coil of electrically conductive material that can be wound in a second direction opposite the first direction. The first substrate layer can be stacked onto the second substrate layer. Also, the first coil of electrically conductive material can be operably coupled to the second coil of electrically conductive material through an interconnection via to form an NFC antenna. |
| US11342101B2 |
Magnetism booster assembly
A magnetism booster assembly including a sleeve having a first face, a second face, and an outer periphery surface extending between the first face and the second face. The sleeve defines a central bore extending from the first face to the second face. The sleeve also defines a pocket spaced apart from the central bore and having an opening in the first face. The magnetism booster assembly also includes a magnet positioned within the pocket. |
| US11342098B2 |
Cable with a fabric sleeve and its method of manufacture
A fabric wrapped cable is formed by positioning adhesive on opposed layers of fabric. A cable is positioned between those layers and the layers are attached by attaching the adhesive of one layer to the adhesive of the other layer. In forming the wrapped cable in such a manner, the cable is provided with at least one wing. |
| US11342094B2 |
Aluminum alloy wire, aluminum alloy strand wire, covered electrical wire, and terminal-equipped electrical wire
An aluminum alloy contains equal to or more than 0.005 mass % and equal to or less than 2.2 mass % of Fe, and a remainder of Al and an inevitable impurity. In a transverse section of the aluminum alloy wire, a surface-layer void measurement region in a shape of a rectangle having a short side length of 30 μm and a long side length of 50 μm is defined within a surface layer region extending from a surface of the aluminum alloy wire by 30 μm in a depth direction, and a total cross-sectional area of voids in the surface-layer void measurement region is equal to or less than 2 μm2. |
| US11342091B2 |
Systems and methods for storing spent nuclear fuel
Systems and methods for storing spent nuclear fuel below grade that afford adequate ventilation of the spent fuel storage cavity. In one aspect, the invention is a system comprising: a shell forming a cavity for receiving a canister of spent nuclear fuel, at least a portion of the shell positioned below grade; and at least one inlet ventilation duct extending from an above grade inlet to a below grade outlet at or near a bottom of the cavity; the inlet ventilation duct connected to the shell so that the cavity is hermetically sealed to ingress of below grade fluids. In another aspect, the invention is a method comprising: providing a below grade hole; providing a system comprising a shell forming a cavity for receiving a canister of spent nuclear fuel, at least a portion of the shell positioned below grade, and at least one inlet ventilation duct extending from an inlet to an outlet at or near a bottom of the cavity, the inlet ventilation duct connected to the shell; positioning the apparatus in the hole so that the inlet of the inlet ventilation duct is above grade and the outlet of the inlet ventilation duct into the cavity is below grade; filling the hole with engineered fill; and lowering a spent fuel canister into the cavity. |
| US11342090B2 |
Binder permeated ionizing radiation shielding panels, method of construction of ionizing radiation shielding panels and an x-ray inspection system employing such panels
An ionizing radiation shielding panel comprising a core layer, a first layer on a first side of the core layer and a second layer on a second side of the core layer, opposite to the first side. The core layer comprises radiation attenuation material which may be particles of barite. The first and second layers each comprise a permeable reinforcement structure and each of the first, second and core layers are permeated with a binder. In the construction of the panel, the binder is infected into a mould containing the other constituents of the panel. The ionizing radiation shielding panel can be used in the housing of an x-ray inspection apparatus. |
| US11342086B2 |
Fuel channel isotope irradiation at full operating power
A fuel bundle surrogate for the irradiation of a target material, having a plurality of tube sheaths, each tube sheath being parallel to a longitudinal center axis of the fuel bundle surrogate, a plurality of end caps, a pair of end plates, wherein the end plates are disposed at opposing ends of the plurality of tube sheaths, and a first target comprised of a first target material suitable for producing the isotope by way of a neutron capture event, wherein the first target is disposed in a first tube sheath, and wherein the first tube sheath of the plurality of tube sheaths comprises an elongated thickened wall portion and a pair of annular end portions, each annular end portion being disposed on a corresponding end of the thickened wall portion and having a wall thickness that is less than a wall thickness of the thickened wall portion. |
| US11342083B2 |
Integrated nuclear reactor architecture limiting the stress applied to the integrated mechanisms
A nuclear reactor (10) includes a vessel (12) containing a primary liquid, a core (14) comprising nuclear fuel and arranged in the internal volume of the vessel (12), at least one primary pump generating a main primary flow (56) of primary liquid in the vessel (12), at least one control member (16) for controlling the reactivity of the core (14), at least one movement mechanism (18) for moving the control member (16), arranged in the internal volume of the vessel (12) and linked to the control member (16), and a pressurizer (20) situated in a top portion of the vessel (12). The movement mechanism (18) comprises an electrical actuator and a transmission mechanism. The electrical actuator is completely immersed in the primary fluid and situated outside the main primary flow (56). |
| US11342078B2 |
Blood vessel status evaluation method and blood vessel status evaluation device
A blood vessel status evaluation method and a blood vessel status evaluation device are provided. The method includes: obtaining at least one angiography image corresponding to a target user; analyzing the angiography image by a first deep learning model to select a target image from the angiography image; analyzing the target image by at least one second deep learning model to determine a blood vessel type of the target user and divide a target blood vessel pattern in the target image into a plurality of scoring segments; and analyzing an output of the second deep learning model by a third deep learning model to obtain a blood vessel status of the target user. |
| US11342077B2 |
Medical information processing apparatus and medical information processing method
A medical information processing apparatus according to an embodiment includes: a display controlling unit configured to display, in a time series, events of diagnosis and treatment actions performed on a subject during a designated display period; a tallying unit configured to tally, as an index value, numerical values either extracted or calculated on the basis of information about the events, for each of tally units obtained by dividing the display period into sections arranged in a time series; and a calculating unit configured to calculate a piece of context information relatively indicating one selected from between the diagnosis and treatment actions and a state of the subject in each of the tally units, by comparing the index values tallied for the tally units with one another, and to further display the pieces of context information so as to be kept in association with the events. |
| US11342073B2 |
Transmitted display casting for medical devices
Medical devices may have the ability to connect through a secure gateway to a network, including both local and external networks. According to the described system, a connection component of the medical device may include a wireless connection dongle system using a wireless adapter, such as a dongle, that is inserted into and/or otherwise coupled to the medical device and that transmits or casts information wirelessly, such as via real-time streaming, to a separate receiving display. The communication may be facilitated by another dongle inserted into and/or otherwise coupled to the receiving display that receives the casted display screen. This transmitted casting capability provides the ability to connect the medical device, such as a peritoneal dialysis machine, to other display devices to duplicate the screen of the medical device on one or more larger or more easily accessible displays via secure one-way communication. |
| US11342063B2 |
Information processing apparatus, information processing method, and program
In one example embodiment, an information processing apparatus, for an observed image associated with an observation target object (e.g., a section of biological tissue), associates and stores position information and observation magnification information. In this embodiment, the information processing apparatus causes a display device to: (i) display an image associated with the observation target object; (ii) indicate the first positional information of the first observed image; and (iii) indicate the first observation magnification information of the first observed image. |
| US11342061B2 |
Emotional wellness management support system and methods thereof
An emotional wellness management system and methods of managing emotional wellness, to help people interactively and iteratively manage and improve their daily processes of emotional wellness. The system comprises storage coupled to a controller for capturing, storing, retrieving, processing, updating and displaying information related to a user's psychological condition comprising user affects, influencers, and actions. A user interface device, coupled to the controller, configured to have a plurality of interactive interfaces to capture user inputs of states of user affects and influencers, provides action links for accessing resources in the user interface device, also providing visual feedback. The controller is configured to interface with at least one controller from a support network via a communication link, and able to capture, store, retrieve, process, update and display information related to user's psychological condition. The controllers from the support network are able to communicate with each other via a communication link. |
| US11342059B2 |
Surgical product supply system and method
A surgical product supply system includes a cart having a first compartment and a second compartment. The first compartment has first, second, third and fourth walls. The first and second walls are constructed of radio-reflective material and the third and fourth walls are constructed of a radio-absorptive material. The first compartment has a first storage area. A first RFID antenna array is attached to the first wall and is positioned within the first storage area. The first RFID antenna array includes a first plurality of RFID antennas. A second RFID antenna array is attached to the second wall and is positioned within the first storage area. The second RFID antenna array includes a second plurality of RFID antennas. The first RFID antenna is offset relative to the second RFID antenna such that opposing central axes of the first and second RFID antennas are not colinear. |
| US11342058B2 |
Systems and methods for processing sensor data
Systems and methods for processing sensor data are provided. In some embodiments, systems and methods are provided for calibration of a continuous analyte sensor. In some embodiments, systems and methods are provided for classification of a level of noise on a sensor signal. In some embodiments, systems and methods are provided for determining a rate of change for analyte concentration based on a continuous sensor signal. In some embodiments, systems and methods for alerting or alarming a patient based on prediction of glucose concentration are provided. |
| US11342054B2 |
System using NFC-enabled medicine packaging to establish a no-login, authenticated and contextualized two-ways data flow between a patient and a pharmaceutical manufacturer
A system and method to establish a no-login authenticated and contextualized two-ways data flow between a medicine user and the pharmaceutical manufacturer. Near Field Communication (NFC) technology, enabling short-range communication between two compatible devices is utilized via a writeable NFC tag carried by a medication package. The writeable NFC tag includes medication information, anti-counterfeiting information, as well as data about the patient and the prescription. The NFC tag may be read by a user device associated with the patient, enabling the user device to merge this data with the patient's feedback, send this rich flow in a secure way to the manufacturer, who in turn is now able to provide rich contextual guidance to the patient. |
| US11342052B2 |
Alert optimizer
An alert optimizer subsystem for a HIT system modifies, reconciles, and/or prioritizes candidate clinical alerts. The optimized alerts may be filtered, prioritized, enriched, and/or formatted so that the alerts are more relevant and/or more actionable for a system user. |
| US11342050B2 |
Monitoring users to capture contextual and environmental data for managing adverse events
A computer system monitors users to capture contextual and environmental data for managing adverse events of those users. A level of risk for occurrence of an adverse event from performing a medical related activity is determined based on the medical related activity, a medical profile, and a risk profile of the user. The user is monitored to capture environmental and contextual information for the adverse event. The captured information is stored to associate the captured information with the adverse event. In response to occurrence of the adverse event, the user is prompted to provide information pertaining to conditions surrounding the adverse event. The stored information for the adverse event is updated with the user-provided information, and is transmitted to a provider associated with the medical related activity. Embodiments of the present invention further include a method and program product for managing adverse events in substantially the same manner described above. |
| US11342049B2 |
Systems and methods for preparing a product
A system, apparatus, and/or method is disclosed for producing a personal care product. An identity of a considered chemical composition may be input into a model (e.g., a machine learning model). The identity of the considered chemical composition may include ingredients. Each of the ingredients of the considered chemical composition may be associated with a value of a chemoinformatic property of chemoinformatic properties of the considered chemical composition. A value of the property of the considered chemical composition may be determined via the model. The value may be based on the identity of the considered chemical composition. The property of the considered chemical composition may be affected by an interaction of at least two of the ingredients of the considered chemical composition. A personal care product comprised of the considered chemical composition may be produced. |
| US11342048B2 |
Systems and methods for genomic annotation and distributed variant interpretation
A computer-based genomic annotation system, including a database configured to store genomic data, non-transitory memory configured to store instructions, and at least one processor coupled with the memory, the processor configured to implement the instructions in order to implement an annotation pipeline and at least one module filtering or analysis of the genomic data. |
| US11342044B2 |
System and method for prioritization of bit error correction attempts
System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit. |
| US11342041B2 |
Apparatuses, systems, and methods for probabilistic data structures for error tracking
Apparatuses, systems, and methods for probabilistic data structures for error tracking. A memory device may include an error code correction (ECC) circuit which determines if data read from a memory array includes an error. If it does, the row address associated with the read data is provided to an error tracking circuit. The error tracking circuit may use probabilistic data structures, such as multiple count values, each indexed by different hash values of the row address. The count values may be used to determine if a given row address is repeatedly associated with errors. The memory may store these identified problem addresses in a data storage structure for example for diagnostic and/or repair purposes. |
| US11342040B2 |
Memory system
A memory system includes a non-volatile memory having a plurality of memory cells and a memory controller. The memory controller is configured to generate a histogram indicating, with respect to each of a plurality of threshold voltage levels for multi-level cell (MLC) reading, a number of memory cells at the threshold voltage level, based on data read from the plurality of memory cells using a plurality of reference read voltages, estimate a plurality of read voltages for MLC reading of the plurality of memory cells as estimation values by inputting the histogram into a read voltage estimation model, determine, through MLC reading of the plurality of memory cells using a plurality of sets of read voltages, a set of read voltages for MLC reading as observation values, and update one or more parameters of the read voltage estimation model based on the estimation values and the observation values. |
| US11342039B2 |
Word line characteristics monitors for memory devices and associated methods and systems
Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to monitor word line characteristics. In one embodiment, the memory device includes a memory array including a word line (e.g., a local word line) and a word line driver coupled thereto. When the memory device activates the word line driver, the memory device may generate a diagnostic signal in response to the word line voltage reaching a threshold. Further, the memory device may generate a reference signal to compare the diagnostic signal with the reference signal. In some cases, the memory device may generate an alert signal based on comparing the diagnostic signal with the reference signal if the diagnostic signal indicates a symptom of degradation in the word line characteristics. The memory device may implement certain preventive and/or precautionary measures upon detecting the symptom. |
| US11342038B2 |
Nonvolatile memory including on-die-termination circuit and storage device including the nonvolatile memory
A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode. |
| US11342035B1 |
Memory apparatus and method of operation using one pulse smart verify
A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses. |
| US11342032B2 |
Memory controller, memory system, and method of operating memory system
Provided herein may be a memory controller, a memory system, and a method of operating the memory system. The memory controller may control the operation of a memory device. The memory controller may include a read request buffer, a command generator, and a read request monitor. The read request buffer may be configured to receive a read request from a host. The command generator may be configured to receive the read request from the read request buffer and generate a read command based on the received read request. The read request monitor may be configured to receive read request information about the read request from the read request buffer and determine, based on a stream ID of the read request, whether the read request is a sequential read request. |
| US11342031B2 |
Circuit and method for process and temperature compensated read voltage for non-volatile memory
An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation. |
| US11342028B2 |
Concurrent programming of multiple cells for non-volatile memory devices
Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells. |
| US11342027B1 |
Systems for adaptively determining read threshold voltage using meta information
Embodiments adaptively determine a read retry threshold voltage for a next read operation using meta information collected from previous failed read data. A controller obtains meta information associated with a read operation on a select page, the meta information including a read threshold voltage set. The controller determines a mathematical model for estimating a checksum value for data associated with a next read operation, using a set function of the read threshold voltage set and a set checksum value. The controller determines a set of parameters by performing polynomial regression on the mathematical model. The controller estimates a next read threshold voltage for the next read operation based on the set of parameters. |
| US11342025B2 |
Non-volatile memory device
A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage. |
| US11342020B2 |
Variable resistive memory device and method of operating the same
A variable resistive memory device includes a memory cell array and a control circuit block. The memory cell array includes a plurality of memory cells that are connected between a global word line and a global bit line. The control circuit block is positioned on at least one of edge portions of the memory cell array. The memory cell array is classified into a first group with the memory cells that are adjacent to the control circuit block and a second group with the memory cells that are remote in relation to the control circuit block. The second group is farther from the control circuit block than the first group. The control circuit block includes a write control unit that generates a control signal for writing on the memory cell in the first group in a different way compared to writing on the memory cell in the second group. |
| US11342019B2 |
Compensation word line driver
Memory systems are provided. In an embodiment, a memory device includes a word line driver coupled to a plurality of word lines, a recycle multiplexer coupled to a plurality of bit lines and a plurality of bit line bars, a memory cell array, and a compensation word line driver. The memory cell array includes a first end adjacent the word line driver, a second end away from the word line driver, and a plurality of memory cells. The compensation word line driver is disposed adjacent the second end of the memory cell array and coupled to the plurality of word lines. The recycle multiplexer is configured to selectively couple one or more of the plurality of bit lines or one or more of the plurality of bit line bars to the compensation word line driver. |
| US11342016B2 |
Read circuit for magnetic tunnel junction (MTJ) memory
In some embodiments, the present application provides a memory device. The memory device includes a first read bias transistor, a first pull-up read-enable transistor, an MTJ memory cell, a first pull-down read-enable transistor, and a first non-linear resistance device. The first non-linear resistance device is coupled in series and between the first pull-up read-enable transistor and the first read bias transistor. The first non-linear resistance device is configured to provide a first resistance when applied a first voltage and a second resistance greater than the first resistance when applied a second voltage smaller than the first voltage. |
| US11342014B1 |
Driver leakage control
Embodiments herein relate to column select circuitry of a memory device. Specifically, the column select circuitry includes a pre-header circuit coupled to a pre-driver circuit. The pre-header circuit is configured to couple a gate of a transistor of a main column select driver circuit of the column select circuitry to a first voltage supply during operation and a second voltage supply when in a standby state. A voltage of the second voltage supply is greater than a voltage of the first voltage supply. The voltage of the second power supply applied to the gate of the transistor of the main column select driver circuit reduces current leakage through the transistor and enables a reduction in a size of the column select circuitry. |
| US11342013B2 |
Memory system and operating method to set target command delay time to merge and process read commands
Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to the embodiments of the present disclosure, the memory system may execute a read operation by setting a command delay time for determining whether to merge and process read commands, for each of a plurality of time periods, and may set a target command delay time, from among the command delay times set for each of the plurality of time periods, to be used for determining whether to merge and process a subsequent read command with one or more prior read commands based on the execution result of the read operation for each of the plurality of time periods. |
| US11342010B2 |
Managing bit line voltage generating circuits in memory devices
Systems, methods, circuits, and apparatus including computer-readable mediums for managing bit line voltage generating circuits in memory devices are provided. An example bit line voltage generating circuit is configured to provide a stable clamping voltage to at least one bit line connecting memory cells in the memory device. The bit line voltage generating circuit includes an operational amplifier configured to receive a reference voltage, a feedback voltage, and a compensation current and output an output voltage, and an output transistor configured to provide a terminal voltage as the feedback voltage and the output voltage as a target voltage that is associated with the clamping voltage. The operational amplifier is configured to be unbalanced such that the terminal voltage is smaller than the reference voltage, and the compensation current is configured to compensate the operational amplifier such that the clamping voltage is substantially constant and independent from PVT (Process-Voltage-Temperature) effect. |
| US11342009B2 |
Cell module equalization and precharge device and method
A device and a method for equalizing and precharging a cell module, which may form a circuit for performing a corresponding operation by a converter unit by selectively connecting the converter unit and one or more cell modules by controlling a conduction state of a switching unit based on an operation which the converter intends to perform. |
| US11342008B2 |
Method and apparatus for accessing to data in response to power-supply event
The invention relates to a method, and an apparatus for accessing to data in response to a power-supply event. The method, performed by a flash controller, includes steps for: repeatedly detecting whether a voltage supplied to the flash controller is lower than a first threshold; and issuing a program command to a flash module for programming data into the flash module and performing a supervision procedure when the voltage is lower than the first threshold. The supervision procedure includes steps for: repeatedly detecting whether the voltage is lower than a second threshold during a time period when issuing the program command to the flash module until transmitting the data to the flash module completely; and cancelling the program command when the voltage is lower than the second threshold. |