| Document | Document Title |
|---|---|
| US11095517B2 |
Method and system for secure zero touch device provisioning
A customer premises device may include a memory configured to store day 0 configuration instructions, a first network interface to couple to an out-of-band orchestration and management path, a second network interface operatively coupled to a customer network, and at least one processor configured to automatically and without user input execute the day 0 configuration instructions. The at least one processor is configured to establish and maintain a secure tunnel connection with a security gateway device via the out-of-band orchestration and management path and to establish a connection with a configuration platform on the provider network via the secure tunnel connection. Orchestration instructions for configuring one or more VNFs are received from the configuration platform via the tunnel connection. The at least one processor is further configured to receive VNF management instructions via the secure tunnel connection, wherein the VNF management instructions include one of: updates, reconfigurations, or patches. |
| US11095513B2 |
Scalable controller for hardware VTEPs
For a virtual distributed network environment employing physical forwarding elements that includes both software forwarding elements and third party devices serving as hardware forwarding elements, a scalable method for synchronizing configuration data of logical forwarding elements that are distributed across the various physical forwarding elements is provided. The method generates and updates the configuration data at a set of central controllers and then distributes the configuration data to the physical forwarding elements. The method delivers the updated configuration data to some of the physical forwarding elements by (i) determining a delta/differential between the updated configuration data held at the central controller and the obsolete configuration data held at those physical forwarding elements and (ii) delivering the determined differential configuration data to the physical forwarding elements. |
| US11095506B1 |
Discovery of resources associated with cloud operating system
A discovery application on a computing system is provided. The discovery application receives a user input, which is for discovery of resources associated with a cloud operating system of a cloud computing system. The user input includes an authentication credential and account information associated with the cloud operating system. Based on the received input, the discovery application executes a discovery pattern comprising operations for the discovery of resources. The cloud operating system includes a group of services to access such resources. At least one of the operations corresponds to an API call to an API endpoint associated with a service of the group of services. The discovery application receives a response to the API call from the cloud operating system. The response includes a payload of information associated with the resources. The discovery application updates, based on the received response, one or more configuration items in a configuration management database. |
| US11095504B2 |
Initializing network device and server configurations in a data center
A system for configuring a data center includes a fabric management server coupled to a management switch. A provisional Software Defined Networking (SDN) controller executing on the fabric management server can discover physical servers coupled to the management switch, receive network interface configuration information from the physical servers, and use the discovered network interface configuration information to determine a configuration for switches and servers coupled to an IP fabric. The configuration can be migrated to a full functionality SDN controller. |
| US11095499B2 |
Broadband watchdog
A method includes determining that data out of a peripheral device has been interrupted. In response, control signals are transmitted that cause power to not be supplied to the peripheral device and then cause power to be supplied to the peripheral device. If the peripheral device is determined to not be outputting data, whether data into the peripheral device has been restored is determined. If it is not, control signals are transmitted that cause power to not be supplied to a router and then cause power to be supplied to the router. If the router is determined to be outputting data, control signals are transmitted that cause power to not be supplied to a wireless access point that is coupled to the modem and then cause power to be supplied to the wireless access point. Whether the wireless access point is outputting data is determined. |
| US11095495B2 |
Multi-result lookups
Methods, systems, and computer readable mediums for network hardware table management including obtaining, by a network device table manager of a network device, a first feature table entry published by a first feature; obtaining, by the network device table manager, a second feature table entry published by a second feature; making a first determination that the first feature table entry and the second table feature entry each comprise a common prefix; and based on the first determination, adding a first combined feature table entry to a combined feature table, the first combined feature table entry comprising the common prefix, a first feature action of the first feature table entry and a second feature action of the second feature table entry. |
| US11095494B2 |
Methods and systems for implementing a cache model in a prefetching system
The present invention relates to systems and methods of enhancing prefetch operations. One potential method comprises fetching an object from a page on a web server. The method may further include storing, at a proxy server, caching instructions for the fetched object. The proxy server may be connected with the client and the object is cached at the client. Furthermore, the method may include identifying a prefetchable reference to the fetched object in a subsequent web page and using the caching instructions stored on the proxy server to determine if a fresh copy of the object will be requested by the client. Further, the method may include, based on the determination that the object will be requested, sending a prefetch request for the object using an If-Modified-Since directive, and transmitting a response to the If-Modified-Since directive prefetch request to a proxy client. The proxy client may then either serve the response to the client or a copy of the object stored at the proxy client, depending on the request for the object from the client. |
| US11095490B2 |
Orthogonal precoding for sidelobe suppression
A transmitter of a DFT-based communications system including an orthogonal precoder for transforming modulated data symbols using a unitary transform, wherein the data 5 symbols are mapped to subcarriers of the transmitter and the computational complexity of the transform is linear with respect to the number of the subcarriers. |
| US11095489B2 |
System and method for controlling combined radio signals
A method for controlling a combined waveform, representing a combination of at least two signals having orthogonal frequency multiplexed signal components, comprising: receiving information defining the at least two signals; transforming the information defining each signal to a representation having orthogonal frequency multiplexed signal components, such that at least one signal has at least two alternate representations of the same information, and combining the transformed information using the at least two alternate representations, in at least two different ways, to define respectively different combinations; analyzing the respectively different combinations with respect to at least one criterion; and outputting a respective combined waveform or information defining the waveform, representing a selected combination of the transformed information from each of the at least two signals selected based on the analysis. |
| US11095487B1 |
Operating a wireline receiver with a tunable timing characteristic
A method of operating a wireline receiver. The receiver may include a front-end comparator and a feedback controller. The method may include providing, by the front-end comparator, a symbol signal by processing a received electrical input signal according to a tunable timing characteristic of the front-end comparator. The method may further include adapting, by the feedback controller, the processing of the input signal to match a predetermined processing criterion by tuning the timing characteristic based on the symbol signal. |
| US11095485B2 |
Frequency-domain IQ mismatch estimation
An electrical system includes a transceiver with an IQ estimator and an IQ mismatch corrector. The electrical system also includes an antenna coupled to the transceiver. The IQ estimator is configured to perform frequency-domain IQ mismatch analysis to determine an IQ mismatch estimate at available frequency bins of a baseband data signal. The IQ mismatch corrector is configured to correct the baseband data signal based on the IQ mismatch estimate. |
| US11095481B2 |
Channel estimation method, base station, user equipment, and system
Embodiments of the present invention relate to a channel estimation method, a base station, user equipment UE, and a system. The method includes: setting up, by a base station, a connection to user equipment UE; and sending, to the UE, notification information indicating that the UE is in a radio remote scenario, where the notification information is used to instruct the UE to perform channel estimation by using a channel estimation algorithm applicable to the radio remote scenario, and the channel estimation algorithm is used to perform channel estimation on a signal that is obtained after downlink signals from multiple radio remote units RRUs are superposed. The UE can perform channel estimation by using the appropriate channel estimation algorithm, to effectively improve accuracy of the channel estimation, thereby effectively improving a downlink data throughput of the UE. |
| US11095480B2 |
Traffic optimization using distributed edge services
Some embodiments provide a novel method for configuring managed forwarding elements (MFEs) to handle data messages for multiple logical networks that are implemented in a data center at the MFEs and to provide gateway service processing (e.g., firewall, DNS, etc.). A controller, in some embodiments, identifies logical networks implemented in the datacenter and MFEs available to provide gateway service processing and assigns gateway service processing for each logical network to a particular MFE. The MFEs, in some embodiments, receive data messages from endpoints in the logical networks that are destined for an external network. In some embodiments, the MFEs identify that the data messages require gateway service processing before being sent to the external network. The MFEs, in some embodiments, identify a particular MFE that is assigned to provide the gateway service processing for logical networks associated with the data messages. |
| US11095477B2 |
Fixed network packet sending method and system
A method includes receiving, by an access gateway device, a fixed network packet included in a first fixed network session. The fixed network packet includes fixed network session characteristic information useable to identify the fixed network packet. The method further includes sending, by the access gateway device, the fixed network packet to a user plane function network element based on information of a first interface corresponding to the fixed network session characteristic information. The first interface is an interface between the access gateway device and the user plane function network element. The method further includes receiving, by the user plane function network element, the fixed network packet. |
| US11095475B2 |
Communication failure detection device
There is provided a communication failure detection device configured to detect a communication failure of a two-wire CAN communication device that makes communication between nodes according to a CAN protocol. Each of the nodes is provided with two signal detection circuits configured to detect signals on the two communication lines. Each node makes communication for failure dentification to output signals of predetermined patterns onto the two communication lines when an execution condition is satisfied in response to the occurrence of a protocol error of CAN communication. Each node then performs failure identification to identify the type of a failure based on a combination of the signals respectively detected by the two signal detection circuits during the communication for failure identification. |
| US11095474B2 |
Packet data protocol
A communication device configured to communicate according to a data protocol in which data is carried in packets over a serial data link and the communication device is arranged: to form packets for transmission over the link in such a way that every packet commences with a first bit value; and between transmitting successive packets to continuously transmit a second bit value opposite to the first bit value over the link. |
| US11095471B2 |
Home-automation system and method for constituting the topology of a home-automation system
The invention relates to a home-automation system and a method for constituting the topology of a home-automation system comprising a plurality of central control units, the method being executed by a user terminal (T) connected to the at least one home-automation system and comprising the following steps: receiving (ECTT3, ECTT4) from at least one central control unit (U1, U2) among the plurality of central control units (U1, U2) at least one message (MDL1, MDL2) comprising a list (DL1, DL2) comprising at least one home-automation device with which said central control unit is capable of communicating; selecting (ECTT6) at least one combination of at least one device in connection with one central control unit among the plurality of control units (U1, U2) for which the communicated device list (DL) comprises the selected device, with a view to connecting at least one device to said central control unit; and sending (ECTT7) a connection message (MR) to the at least one central control unit (U) selected in step ii so as to trigger a connection of the at least one device (D) to said central control unit (U). |
| US11095466B2 |
Packet transmission control method and packet transmission circuit
A packet transmission control method used in a packet transmission circuit is provided that includes the steps outlined below. A packet receiving circuit, processing circuits and a packet sending circuit of the packet transmission circuit are kept in a non-operation status. The packet receiving circuit is woken up to the operation status to receive the packet stream and is restored to the non-operation status. The processing circuits are woken up to an operation status respectively according to an operation order thereof to receive, transmit and process the packet stream within a respective process time period and are restored to the non-operation status after the packet stream is processed. The packet sending circuit is woken up to the operation status to transmit the packet stream processed by the processing circuits to an external device and is restored to the non-operation status after the packet stream is transmitted. |
| US11095465B2 |
Control of power delivery to a DC-powered device
A DC-powered device controller (101), comprising a DC-power unit (102) configured to be electrically connected via a wired power line (105) to an external DC-power supply device (104), a control unit (112) connected with the DC-power unit and configured to receive from a DC-voltage monitoring unit (108) response signals indicative of a current voltage amount of the DC-power and to receive, from a mark-event timer unit (110), an extended-mark-time signal when a measured mark-event time exceeds a predetermined mark-event duration threshold, and to enable delivery of the currently received DC-power to an external electrical load unit (106) in event of either one of a) detecting that the current response signal is indicative of the currently received voltage amount falling into an operating voltage interval, and b) detecting that the extended-mark-time signal has been received. |
| US11095462B2 |
Systems and methods for storing and sharing transactional data using distributed computer systems
A computer system that interfaces with a blockchain is provided. The computer system receives match data for a match between a first data transaction request that is associated with a first identifier and a second data transaction request that is associated with a second identifier. A first blockchain transaction is generated based on the match data and stored to a blockchain. At least one further blockchain transaction is generates that splits the match into two different transactions—one between the first identifier and an intermediary and the second between the intermediary. These are recorded to the blockchain via the further blockchain transactions. |
| US11095456B2 |
Distributed tiered data exchanges within a blockchain network
Distributed tiered data exchanges within a distributed trust/blockchain network are provided for. A continual and ongoing data asset transfer being conducted via a distributed ledger of the distributed trust/blockchain network is leveraged for the purpose of establishing and conducting other continuous and ongoing data asset transfers using the same distributed ledger of the distributed trust/blockchain network. The tiered nature of the asset transfers/distributions means that one distributed ledger can be established and used to conduct multiple different continuous and ongoing data assets transfers between the initial data asset transfer entities and/or other entities. As such, through the use of one distributed ledger of a distributed trust/blockchain network, a single data asset request made by a first entity (i.e., data asset transferee) may be used to make multiple different data asset distributions/transfers to one or many different entities. |
| US11095455B2 |
Recursive token binding for cascaded service calls
The present disclosure describes techniques that improve upon the use of authentication tokens as a means of verifying a user identity. Rather than facilitating the issuance of authentication tokens as bearer tokens, whereby any user may present an authentication token to a secure service provider for access to secure service, this disclosure describes techniques for generating recursive authentication tokens that are digitally signed by an Identity Service Provider (IDP) and the entity that purports to present the authentication token to the service provider. Additionally, a recursive token application is described that is configured to nest preceding authentication tokens that trace back to an initial secure service request. For example, a recursive authentication token received by a second service provider may include, nested therein, the first service provider recursive authentication token and a preceding client recursive authentication token that is associated with the initial secure service request. |
| US11095454B2 |
Releasing secret information in a computer system
A method, apparatus, computer system, and computer program product for releasing secret information. A client on a computer system performing an attestation to a server on another computer system. The client receives an authorization that authorizes releasing the secret information. The client releases the secret information from a co-processor on the computer system using the authorization received from the server. |
| US11095452B2 |
Out-of-band authentication in group communications
System, method, and computer program product for authenticating a message among a groups of computing devices communicating over an unsecured channel, based on an out-of-band (OOB) authenticated channel which may be used to send a short message to all receivers. |
| US11095451B2 |
Optimal data storage configuration in a blockchain
A blockchain of transactions may be referenced for various purposes and may be later accessed by interested parties for ledger verification and information retrieval. One example method of operation may include assigning one blockchain block to one group member node among a group of blockchain nodes, storing the one blockchain block in the one group member node, assigning a verification of the one blockchain block to one or more verification blockchain nodes which are part of the group of blockchain nodes, and storing the verification of the one blockchain block in each of the one or more verification blockchain nodes. |
| US11095444B2 |
Method and computer for cryptographically protecting control communication in and/or service access to IT systems, in particular in connection with the diagnosis and configuration in an automation, control or supervisory system
Automatically and dynamically ascertaining by means of autoconfiguration whether used or activated and usable cipher suites and/or key lengths are sufficiently strong for current cryptographic protection of the control communication and/or other service access by virtue of 1) “cipher-suite”-based/-specific information available in the network/system being called up to ascertain reference cipher suites and/or 2) block chain information available in the network/system, containing data records referred to as “proof of work” for solving complex computation tasks, being called up or ascertained, with the ascertainment of block chain difficulty parameters as key length estimation parameters to ascertain appropriate reference key lengths, in particular reference minimum key lengths required for cryptoalgorithms, and 3) the ascertained reference cipher suites and/or the reference key lengths ascertained by the key length estimation parameters being compared with the used or activated and usable cipher suites and/or key lengths. |
| US11095438B1 |
Database encryption key management
Methods and systems are described for enhanced-security database encryption via cryptographic software, where key management is carried out, without exporting or exposing cleartext keys, using an independent key manager coupled to a cryptographic hardware security module (HSM). |
| US11095437B2 |
Key data processing method and apparatus, and server
A parent cryptographic key associated with a blockchain object is obtained. A number of parties (N) to share control over the blockchain object is obtained. N child cryptographic keys are generated based on the parent cryptographic key by applying a predetermined algorithm to the parent cryptographic key, wherein N is an integer greater than or equal to 2, and wherein the N child cryptographic keys are collectively configured to enable reconstruction of the parent cryptographic key. |
| US11095435B2 |
Keystroke dynamics anonimization
A keystroke dynamics anonymization technique that includes: receiving a plain-text password from a computer user; providing at least the plain-text password as a seed to a pseudorandom mapping function; applying the pseudorandom mapping function to keycodes that are produced by the computer responsive to keystrokes of the computer user, to map the keycodes to a set of mapped, anonymized keycodes; and providing the set of mapped, anonymized keycodes to a keystroke dynamics algorithm, to enable the keystroke dynamics algorithm to (a) learn a keystroke dynamics model of the computer user, and (b) authenticate an identity of the computer user. |
| US11095433B2 |
On-chain governance of blockchain
An example operation may include one or more of receiving a request to modify a governance policy of a blockchain, identifying a principal identity that controls the governance policy, determining an allowable combination of signatures of the principal identity required for modifying the governance policy based on a graph data structure storing signature policies for endorsing modifications to governance policies, and modifying the governance policy of the blockchain based on the request in response to an allowable combination of signatures being received. |
| US11095432B2 |
System for processing data based on blockchain and operating method thereof
Provided is a blockchain management apparatus comprising at least one hardware processor configured to implement a block generation order control unit which prevents a block generation node of a plurality of blockchain nodes from generating a new block of a blockchain in response to a determining, by the blockchain management apparatus, that the new block is a block generated by the block generation node within a unit section, wherein the unit section corresponds to a preset number of blocks measured from a current block corresponding to a current block height of the blockchain, and the blockchain management apparatus manages a permission-based blockchain network including the plurality of blockchain nodes. |
| US11095429B2 |
Circuit concealing apparatus, calculation apparatus, and program
At least any one of input keys KA0, KA1, KB′0, and KB′1 is set so that the input keys KA0, KA1, KB′0, and KB′1 which satisfy KA1−KA0=KB′1−KB′0=di are obtained, and an output key Kig(I(A), I(B)) corresponding to an output value gi(I(A), I(B)) is set by using the input keys KA0, KA1, KB′0, and KB′1, where input values of a gate that performs a logical operation are I(A), I(B)∈{0, 1}, an output value of the gate is gi(I(A), I(B))∈{0, 1}, an input key corresponding to the input value I(A) is KAI(A), and an input key corresponding to the input value I(B) is KB′I(B). |
| US11095413B2 |
Base station, user equipment and related methods
The present disclosure provides a method for obtaining supplementary system information, and a corresponding user equipment and a base station. A method in the user equipment according to the present invention comprises: sending a leader sequence to a base station to request supplementary system information; and receiving a reply message from the base station in response to sending of the leader sequence. |
| US11095411B2 |
Demodulation reference signal design for vehicle-to-vehicle communication
Various features described herein relate to DM-RS design for a control channel and a data channel that maybe used for vehicular communications. In an aspect, a UE may determine a base DM-RS sequence associated with a control channel for V2V communication. The UE may further determine a DM-RS sequence based on the base DM-RS sequence and an identity of the UE, and transmit a plurality of DM-RS symbols within the control channel in a subframe using the DM-RS sequence. In another aspect, a UE may generate a plurality of DM-RS sequences, each DM-RS sequence maybe generated for a corresponding DM-RS symbol of a plurality of DM-RS symbols associated with a data channel for V2V communication based on a DM-RS symbol number of the corresponding DM-RS symbol. The UE may transmit the plurality of DM-RS symbols within the data channel in a subframe using the plurality of DM-RS sequences. |
| US11095408B2 |
Generating reference signal(s) using Zadoff-Chu sequence(s)
Disclosed is a reference signal transmission method and a device. The method includes converting, by a sending device, a frequency domain reference signal from frequency domain to time domain, to generate a time domain reference signal. The frequency domain reference signal includes a reference signal sequence mapped to a frequency domain resource. The reference signal sequence is determined based on a Zadoff-Chu (ZC) sequence, and a length value of the ZC sequence is selected from at least two length values. The method includes sending, by the sending device, the time domain reference signal. According to the reference signal transmission method, one ZC sequence is selected from at least two ZC sequences with different lengths to generate the reference signal sequence, so that the generated reference signal sequence is characterized by a low PAPR and an low RCM, and is used to generate a reference signal, to improve data transmission performance. |
| US11095404B2 |
Multiplexing downlink control information of same aggregation level by coding together
Certain aspects of the present disclosure relate to a technique for multiplexing downlink control information (DCI) signals for multiple user equipments (UEs) at an aggregation level (AL) by coding the DCI signals together in a control channel and transmitting the control channel. In an exemplary method, a BS multiplexes a first plurality of downlink control information (DCI) signals for a first plurality of user equipments (UEs) at a first aggregation level (AL) coded together in a first control channel and transmits the control channel. |
| US11095400B2 |
Configuration of repetition factors for transmitting feedback data for 5G or other next generation network
Configuring channel state information configuration parameters can reduce user equipment uplink feedback information. The user equipment can send the uplink feedback information to the network node by adapting the repetition factor based on one or more criteria. The repetition factor can be determined by the user equipment and/or a network node associated with the user equipment. Thus, reducing the frequency of reporting uplink feedback information can reduce power usage, signal interference, and increase battery life. |
| US11095399B2 |
Robust telemetry repeater network system and method
A robust network telemetry repeater system exploits the repeater structure of data propagation and transmission and reception bi-directionality to increase network robustness. For example, multiple perceived receive attempts are created with no additional overhead. The system can be configured whereby nodes “hear” the transmissions of both adjacent and non-adjacent nodes forming implicit acknowledgement (“Acks”), and originating nodes can retransmit until implicit acknowledgments (“Acks”) are “heard,” indicating a successful link relay. Implicit acknowledgment can be applied to bidirectional networks, and bidirectional action can enable all nodes in the network to know the status of all other nodes. |
| US11095397B2 |
Apparatus and method for encoding and decoding using polar code in wireless communication system
A pre-5th generation (5G) or 5G communication system supports higher data rates beyond 4th-generation (4G) communication system such as long term evolution (LTE) is provided. A method for operating a first device in a wireless communication system includes generating a first bit sequence, generating a second bit sequence including at least one of the first bit sequence, at least one cyclic redundancy check (CRC) bit, at least one frozen bit, or at least one parity check (PC) bit, generating a transmission bit sequence by performing a polar encoding and a rate matching for the second bit sequence, and transmitting, to a second device, the transmission bit sequence. A length of the transmission bit sequence is equal to or greater than a sum of a length of the first bit sequence, a number of the at least one CRC bit and a number of the at least one PC bit. |
| US11095393B2 |
Outer loop link adaptation adjustment method and apparatus
The present disclosure relates to outer loop link adaptation adjustment methods and apparatus. In one example method, a base station obtains at least one piece of channel quality information of a terminal device, determines, based on the at least one piece of channel quality information of the terminal device and channel quality ranges of a plurality of clusters in a cell, a target cluster to which the terminal device belongs, updates a signal to interference plus noise ratio (SINR) error adjustment amount of the target cluster and a channel quality fluctuation parameter of the cell based on the at least one piece of channel quality information of the terminal device, and finally determines an initial value of an outer loop link adaptation (OLLA) adjustment amount of the terminal device based on the SINR error adjustment amount of the target cluster and the channel quality fluctuation parameter of the cell. |
| US11095384B2 |
Re-timing a packetized radio flow to clean noise induced by packet delay variation of a packet network
Techniques are described to provide for re-timing a packetized radio flow to clean noise induced by packet delay variation of a packet network. In one example, a method includes receiving, at a first node of a fronthaul network, a Radio over Ethernet (RoE) frame transmitted by a second node in which the RoE frame comprises a Common Public Radio Interface (CPRI) bit stream associated with a first radio device, a sequence number, and a first time stamp. The method may further include generating a second time stamp by the first node upon obtaining the RoE frame; calculating an induced delay value based, at least in part, on the first time stamp and the second time stamp; calculating a re-timing value based on a re-timing interval and the induced delay value; and transmitting the CPRI bit stream to a second radio device based on the re-timing value. |
| US11095383B2 |
Method for exchanging time synchronization packet and network apparatus
A method for exchanging a clock synchronization packet performed by a network apparatus, including: exchanging a clock synchronization packet with a first clock source, where the network apparatus includes a boundary clock; determining a first time deviation of the boundary clock relative to the first clock source according to the clock synchronization packet exchanged with the first clock source, where the boundary clock avoids performing an operation of calibrating a time of a local clock of the boundary clock according to the first time deviation; and sending a clock synchronization packet to a first slave clock of the boundary clock, where the clock synchronization packet includes a first timestamp, a value of the first timestamp is equal to a first corrected value, and the first corrected value is a value obtained by the boundary clock by correcting the time of the local clock by using the first time deviation. |
| US11095381B2 |
Legacy time division multiplexing (TDM) service support in a packet network and on a packet network element
A network element includes at least two Time Division Multiplexing (TDM) modules each including a TDM client interface, TDM processing circuitry, and circuit emulation circuitry; and a packet switch fabric connected to the at least two TDM modules and configured to output a packet interface, wherein a protected TDM service through the at least two TDM modules is provided as a single packetized TDM stream via the packet interface from the packet switch fabric. |
| US11095379B2 |
Data processing unit and information processing device
A data processing unit includes a processing circuit that is configured to process data based on a value of a first parameter, a first operator that is selectively set to one of a first state and a second state that are physically identified, a second operator that is set to a physical state indicating the value of the first parameter, and a processor that is configured to set the value of the first parameter indicated by the physical state of the second operator in the processing circuit in a case where the first operator is in the first state at a time of activating the data processing unit, and set a value of the first parameter supplied from the information processing device in the processing circuit in a case where the first operator is in the second state at the time of activating the data processing unit. |
| US11095370B2 |
Symmetrical supervisory optical circuit for a bidirectional optical repeater
A bidirectional optical repeater having two unidirectional optical amplifiers and a supervisory optical circuit connected to optically couple the corresponding two optical paths through the repeater. In an example embodiment, the supervisory optical circuit is symmetrical in the sense that it enables the two optical input/output port pairs of the repeater to be interchangeable and functionally equivalent at least with respect to two supervisory wavelengths and some in-band and/or out-of-band wavelengths. This symmetry can advantageously be used, e.g., to improve the installation process directed at installing such optical repeaters in an undersea cable system. For example, a single directional orientation of the optical repeaters does not need to be maintained throughout the cable system, which can significantly reduce the risk and/or cost of installation errors. |
| US11095364B2 |
Frequency division multiple access optical subcarriers
A network or system in which a hub or primary node may communicate with a plurality of leaf or secondary nodes. The hub node may operate or have a capacity greater than that of the leaf nodes. Accordingly, relatively inexpensive leaf nodes may be deployed to receive data carrying optical signals from, and supply data carrying optical signals to, the hub node. One or more connections may couple each leaf node to the hub node, whereby each connection may include one or more spans or segments of optical fibers, optical amplifiers, optical splitters/combiners, and optical add/drop multiplexer, for example. Optical subcarriers may be transmitted over such connections, each carrying a data stream. The subcarriers may be generated by a combination of a laser and a modulator, such that multiple lasers and modulators are not required, and costs may be reduced. As the bandwidth or capacity requirements of the leaf nodes change, the number of subcarriers, and thus the amount of data provided to each node, may be changed accordingly. Each subcarrier within a dedicated group of subcarriers may carry OAM or control channel information to a corresponding leaf node, and such information may be used by the leaf node to configure the leaf node to have a desired bandwidth or capacity. |
| US11095362B2 |
Mitigating interference in radio systems
Mitigating interference in 5G new radio systems may include establishing a path loss range associated with a satellite earth station, and receiving a path loss value associated with a mobile device. The method further includes determining whether the path loss value is within the path loss range, and sending a message to the mobile device to change an operation of the mobile device in response to determining that the path loss value is within the path loss range. |
| US11095361B2 |
Dynamic geographical spectrum sharing
Methods, apparatuses, computer-readable mediums for storing software, and systems for dynamic geographical spectrum sharing (DGSS) by Earth exploration satellite services (EESS) are described herein. Using DGSS mechanisms described herein, electromagnetic spectrum may be shared by sensors onboard Earth exploration satellites and wireless networks, such as 5G networks. The DGSS mechanisms may include mechanisms for determining an instantaneous field of view (IFOV) and mechanisms for modifying transmission characteristics while network antennas and power radiated by such antennas are within a window encompassing the IFOV. For example, when the IFOV of a satellite sensor for measuring atmospheric water includes a 5G antenna, the power of the 5G antenna may be reduced, the 5G antenna may be prevented from utilizing a segment of the electromagnetic spectrum, etc. The DGSS mechanisms may also determine actual out of band emissions for a specific pixel associated with the IFOV and improve pixel location determinations. |
| US11095358B2 |
System and method for beam switching and reporting
Methods, apparatuses, and computer-readable mediums associated with a user equipment (UE) and a base station are provided for herein. In aspects, a UE may receive, from a base station, a beam modification command indicating at least one beam index for communicating through at least one beam on a channel and indicating the channel corresponding to the at least one beam. In an aspect, each beam index of the at least one beam index indicating at least a direction for communicating through a corresponding beam of the at least one beam, where the beam modification command may be received in a MAC CE. The UE may communicate, with the base station, through the at least one beam corresponding to the at least one beam index on the channel. |
| US11095352B2 |
Method and apparatus for handling IDC problems in NR in a wireless communication system
A method and apparatus are disclosed. In an example from the perspective of a User Equipment (UE), the UE determines whether a beam associated with a reference signal of a cell has an In-Device Coexistence (IDC) problem. The UE determines whether to include information associated with the reference signal in a report based on whether the beam associated with the reference signal has the IDC problem. The UE transmits the report to a network node. |
| US11095350B1 |
Digital beamforming for cellular technology applications
Embodiments of the present disclosure relate to cellular technology applications of beamforming performed in the digital domain. In one aspect, an RF system for performing digital beamforming on a per-carrier basis is disclosed, where different phase and/or amplitude adjustments are applied to signals of different frequency ranges (i.e., to different carrier signals). In another aspect, an RF system for performing digital beamforming on a per-antenna basis is disclosed, where different phase and/or amplitude adjustments are applied to signals transmitted from or received by different antennas. In some embodiments, an RF system may be configured to implement both digital beamforming on a per-carrier basis and digital beamforming on a per-antenna basis. The RF systems disclosed herein allow implementing programmable beamforming in the digital domain in a manner that is significantly less complex than conventional implementations. |
| US11095349B2 |
Electronic device for selecting antenna to support designated radio communication among plurality of antennas
An electronic device includes antennas, first radio frequency front ends (RFFEs) configured to pre-process a an RF signal having a frequency belonging to a first frequency band, second RFFEs connected to the antennas, respectively, wherein at least one of the second RFFEs is configured to pre-process an RF signal having a frequency belonging to a second frequency band different from the first frequency band, switches selectively connecting the first RFFEs to the respective antennas, a communication processor operatively coupled to the first RFFEs, the second RFFEs and the switches, and a memory storing instructions that, when executed, cause the processor to select a first antenna to support radio communication using the first frequency band among the antennas and control the switches to connect one of the first RFFEs to the first antenna and to open a connection between a remainder of the first RFFEs and a remainder of the antennas. |
| US11095343B2 |
Method and device for feeding back and receiving channel information, and computer storage medium
Provided are a method and device for feeding back and receiving channel information. The method comprises: determining a candidate resource set, selecting M resources from the candidate resource set, and transmitting at least one of indication information or channel state information of the selected M resources to a first communication node, where M is a positive integer; a selection criterion for selecting the M resources from the candidate resource set is determined in at least one of following manners: a selection criterion or a selection criterion set is agreed with the first communication node, and a selection criterion or a selection criterion set is obtained according to received indication information transmitted by the first communication node, and the selection criterion set comprises at least one selection criterion. |
| US11095341B2 |
Method and device for transmitting signal
Disclosed in an embodiment of the invention are a method and device for transmitting a signal. The method comprises: a first device determining, according to a base parameter set and/or an operating frequency band used to transmit signals, the number of wave beams used to transmit the signals, or determining a number of the transmitted signals N, where N is a positive integer; and the first device transmitting, according to the number of wave beams or the number of the transmitted signals N, the signals with a second device. The method and device of the embodiment of the invention can flexibly determine, according to a transmission characteristic between a terminal device and a network, the number of wave beams used to transmit signals, or determine the number of the transmitted signals, thereby obtaining better beamforming gain. |
| US11095329B1 |
Filter and amplification circuit for outputting ultra-wide band (UWB) radio frequency (RF) signals with a high spurious-free dynamic range, test system and methods
Disclosed is a filter and amplification circuit including a first switch with a single input and multiple outputs, a second switch with multiple inputs and a single output, and signal paths (each with an amplifier and band pass filter) between the outputs of the first switch and the inputs of the second switch, respectively. During filtering, the input of the first switch receives a radio frequency (RF) signal and filtering is performed through a combination of a selected signal path (which is active and has its amplifier enabled) and non-selected signal paths (which are passively coupled to the selected signal path and have their amplifiers disabled). Isolation is provided by the switches (e.g., solid-state switches) and the amplifiers, ensuring that the filtered RF signal at the single output of the second switch has a desired high spurious-free dynamic range (SFDR). Also disclosed are a test system and associated methods. |
| US11095328B2 |
Wireless user signal reception based on multiple directions-of-arrival
A wireless access point serves dynamic direction-of-arrival reception. An access point radio wirelessly receives a wireless signal that transports time-domain data. Access point circuitry determines uplink utilization for the access point radio. The circuitry transforms the time-domain data into frequency-domain data. The circuitry filters the frequency-domain data for one direction-of-arrival responsive to the uplink utilization. The circuitry synthesizes the time-domain data from the filtered frequency-domain data. The radio wirelessly receives another wireless signal that transports additional time-domain data. The circuitry determines a higher uplink utilization for the access point radio. The circuitry transforms the additional time-domain data into additional frequency-domain data. The circuitry filters the additional frequency-domain data for multiple directions-of-arrival responsive to the higher uplink utilization. The circuitry synthesizes the additional time-domain data from the filtered additional frequency-domain data. |
| US11095317B2 |
Efficiently decodable QC-LDPC code
A base matrix of a rate-adaptive irregular QC-LDPC code is provided, the base matrix being formed by columns and rows having entries representing circulant submatrices. The columns of the base matrix are divided into at least one or more higher weight first columns and lower weight second columns and the rows of the base matrix are divided into first high weight rows corresponding to the high rate mother code and second low weight rows corresponding to the extension part related to the lower rate codes. A first submatrix formed by an intersection of entries of the second columns and entries of the first and the second rows is divided into first quadratic submatrices, wherein at most one entry in each column of each first submatrix and/or at most one entry in each row of each first submatrix is labelled. |
| US11095316B2 |
Controller and operating method for performing read operation to read data in memory device
A controller is provided to include a processor reading data from a memory device, and a decoder receiving the data and decoding the data, the data being represented with check nodes and variable nodes. The decoder includes a check unit calculating syndrome values, a calculation unit receiving the decision values of the variable nodes and calculating flipping function values, a setting unit receiving the flipping function values and generating a candidate vector by dividing the flipping function values into groups and selecting at least some maximum values from the groups, the setting unit setting a flipping function threshold value, and a flipping unit receiving the flipping function threshold value, comparing the flipping function values of the variable nodes with the flipping function threshold value, and flipping a decision value of a target variable node having a greater flipping function value than the flipping function threshold value. |
| US11095315B1 |
Intelligent error correction in a storage device
Dynamically adjusting an error correction effort level of a storage device, including: receiving, from a storage array controller, an error correction effort level to perform when attempting to read data from the storage device; identifying that an attempt to read the data resulted in an error; and determining whether an amount of error correction effort level required to attempt to correct the error exceeds the error correction effort level to perform when attempting to read data from the storage device. |
| US11095312B2 |
Polar code encoding/decoding method and encoding/decoding apparatus
Embodiments of polar encoding/decoding methods and apparatuses are described. CRC encoding is performed on an information block to obtain a CRC encoded block with a length of B, where a CRC length is Lcrc, an information block length is K, and B=K+Lcrc. The CRC encoded block is interleaved. Lpc CRC bits in the interleaved encoded block are located between bits of the information block. Each CRC bit of the Lpc CRC bits is located after all bits checked by using the CRC bit. Lpc is an integer greater than 0 and less than Lcrc. The interleaved encoded block is mapped to information bits. A frozen bit is set to an agreed fixed value. Polar encoding is performed on the information bits and the frozen bit to obtain a polar encoded codeword to improve performance of a CA-polar code. |
| US11095302B2 |
Frequency delta sigma modulation signal output circuit, physical quantity sensor module, and structure monitoring device
A frequency delta sigma modulation signal output circuit includes a phase modulation circuit that outputs a phase modulation signal based on a delay signal obtained by delaying a signal to be measured, in synchronization with the signal to be measured, and a frequency ratio digital conversion circuit that generates a frequency delta sigma modulation signal using a reference signal and the phase modulation signal. |
| US11095296B2 |
Phase modulator having fractional sample interval timing skew for frequency control input
An example method in accordance with some embodiments includes: determining an output frequency control word (FCW) having a plurality of bits, the output FCW being configured to control an oscillator, the oscillator including a plurality of capacitor banks, the plurality of capacitor banks respectively corresponding to the plurality of bits of the output FCW; storing the output FCW in a clocked delay cell; providing an input clock to the clocked delay cell, wherein the input clock is provided to delay the output FCW by an amount of delay; and, in accordance with the input clock, releasing the delayed output FCW from the clocked delay cell, and respectively applying the plurality of bits of the delayed output FCW to the plurality of capacitor banks of the oscillator. |
| US11095294B2 |
Phase-locked loop and method for calibrating voltage-controlled oscillator therein
A phase-locked loop (PLL) and a method for calibrating a VCO therein are provided. The PLL comprises a frequency-phase detector, a charge pump, a loop filter, a VCO, a divider and a calibration circuit. The calibration circuit is used to acquire a frequency of an output signal of the VCO, to calibrate the frequency of the output signal according to an expected frequency, and to acquire frequency control parameters of the VCO at the current signal frequency. The amplitude and gain of the output signal are kept constant according to the amplitude control parameters and gain control parameters. The PLL can meet the demands on frequencies of multiple protocols and can adaptively look up and stabilize the suitable frequency. It solves the issue that the amplitude of the output signal of the VCO is not constant when the PLL operates in a large frequency range. |
| US11095293B1 |
Low-power fractional analog PLL without feedback divider
An integrated circuit device is provided. In some examples, the integrated circuit device includes a first re-timer configured to receive a reference clock signal and a voltage controlled oscillator (VCO) output signal, and the first re-timer is configured to provide a first re-timed clock signal in response to the reference clock signal and the VCO output signal. A multiplexer receives the first re-timed clock signal and provides a feedback clock signal. A phase frequency detector receives the feedback clock signal and the reference clock signal and provides an error signal in response to the feedback clock signal and the reference clock signal. A VCO receives a voltage signal based on the error signal, and the VCO is configured to provide the VCO output signal in response to the voltage signal. |
| US11095290B2 |
Clock recovery method and clock recovery module
A clock recovery method for recovering a clock signal from a data signal is described, wherein the data signal comprises a symbol sequence. The clock recovery method comprises the following steps: The data signal is received. At least two partial clock timings of a partial clock signal that is based on the data signal are determined. The number of symbols between the at least two partial clock timings is determined. Clock timings of the clock signal are determined based on the at least two partial clock timings and the number of symbols. Further, a clock recovery module is described. |
| US11095289B2 |
Time of flight sensing unit having reconfigurable OR logic
An electronic device includes at least one photodetection block, where the at least one photodetection block includes a plurality of macropixels arranged into an array. Each macropixel includes an array of photodiodes, with logic circuitry coupled to outputs of the array of photodiodes and configured to generate a detection signal as a function of logically combining the outputs of the array of photodiodes. Each macropixel has associated therewith selection circuitry configured to selectively pass the detection signal to output combining logic or to output combining logic of at least one neighboring macropixel of the plurality thereof. The output combining logic has inputs coupled to the selection circuitry and to the selection circuitry of the at least one neighboring macropixel, and is configured to generate an output detection signal as a function of logically combining outputs of the selection circuitry and the selection circuitry of the at least one neighboring macropixel. |
| US11095282B2 |
Methods and apparatus to implement current limit test mode
Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node. |
| US11095280B2 |
Efficient IGBT switching
Embodiments of the invention provide IGBT circuit modules with increased efficiencies. These efficiencies can be realized in a number of ways. In some embodiments, the gate resistance and/or voltage can be minimized. In some embodiments, the IGBT circuit module can be switched using an isolated receiver such as a fiber optic receiver. In some embodiments, a single driver can drive a single IGBT. And in some embodiments, a current bypass circuit can be included. Various other embodiments of the invention are disclosed. |
| US11095279B2 |
Generalized pulse width modulation technique for specific inter-harmonics control of the inverters
This disclosure provides a PSR-PWM technique for high power active front-end inverters to damp a specific inter-harmonic that may cause relative sub-synchronous resonance in power system. Due to the strong interaction between wind power converters, photovoltaic converters, FACTS devices and HVDC transmission, low-frequency oscillations occur from a few Hz to dozens of Hz, or even high-frequency oscillations ranging from about 300-2000 Hz. Meanwhile, low-frequency oscillations ranging from 0.6 Hz to 7 Hz occur in the power supply systems of many electric locomotives. Even in the case of large-scale train outage, low-frequency oscillation will lead to abnormal locomotive dispatching system; in addition, the power grid voltage disturbance and flicker caused by a large number of high-power are furnaces and other nonlinear loads in the industrial field with a passband inter-harmonic frequency ranging from 0.05 Hz-90 Hz and so on are detected. |
| US11095278B2 |
Comparator, solid-state imaging device, electronic apparatus, and driving method
A comparator includes: a first amplifying unit that includes a differential pair configured with a pair of transistors which are first and second transistors, and amplifies a difference of signals input to each of the gate electrodes of the first and second transistors, to output; a second amplifying unit that amplifies the signal output from the first amplifying unit; a third transistor that connects the first transistor to a power source voltage; a fourth transistor that connects the second transistor to the power source voltage; a fifth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the third transistor; and a sixth transistor that connects a connection point of gate electrodes of the third transistor and the fourth transistor to a drain of the fourth transistor. |
| US11095277B2 |
Cable voltage drop compensation
A voltage source device includes a voltage converter configured to generate a supply voltage at an output node of the voltage converter. A current source is configured to apply a current to a first output terminal of the voltage source device in order to detect a cable voltage drop. A compensation circuit is configured to generate a feedback signal based on a voltage at the first output terminal. The supply voltage is generated based on the feedback signal. |
| US11095272B2 |
Flip-flop cell
An integrated circuit includes a semiconductor substrate and a plurality of circuit elements in or on the substrate. The circuit elements are defined by standard layout cells selected from a cell library. The circuit elements including a plurality of flip-flops. Each flip-flop has a data input terminal, a data output terminal, a clock input terminal, and a clock output terminal. A first one of the flip-flops directly abuts a second flip-flop such that the clock output terminal of the first flip-flop electrically connects with the clock input terminal of the second flip-flop. |
| US11095268B2 |
RF filter
An RF filter is disclosed. In an embodiment, the RF filter includes series-interconnected basic elements, each basic element having an electroacoustic resonator and impedance converters interconnected in series between the basic elements, wherein the impedance converters are impedance inverters and/or admittance inverters, and wherein the resonators of the basic elements are either only series resonators or only parallel resonators. |
| US11095265B2 |
Matching circuit and communication device
A matching circuit includes first and second ports, an autotransformer, and first and second capacitors. The autotransformer includes a first terminal coupled to a first port, a second terminal coupled to a second port, and a common terminal coupled to a reference potential, and includes a series parasitic inductor and a parallel parasitic inductor. The first capacitor is coupled in shunt to the second terminal, and defines a low pass filter together with the series parasitic inductor. The second capacitor is coupled in series between the first port and the first terminal, and defines a high pass filter together with the parallel parasitic inductor. |
| US11095263B2 |
Signal amplifier with calibrated reference
A signal amplifier for use in a power converter includes a variable reference generator coupled to generate a reference signal in response to a dimming control signal. A variable gain circuit is coupled to receive the reference signal, the gain signal, and a feedback signal representative of an output of the power converter. The variable gain circuit is coupled to output a first adjusted signal in response to the reference signal and the gain signal. The variable gain circuit is coupled to output a second adjusted signal in response to the feedback signal and the gain signal. An auxiliary amplifier is coupled to output the gain signal in response to the first adjusted signal and a set signal. |
| US11095261B2 |
Amplification interface, and corresponding measurement system and method for calibrating an amplification interface
An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs. |
| US11095260B2 |
Amplifier with low drift biasing
An amplifier includes an input transistor, an input terminal, a first current source, a cascode transistor, and a second current source. The input transistor is coupled to the input terminal. The first current source is coupled to the input transistor and is configured to provide a bias current to the input transistor that is proportional to absolute temperature. The cascode transistor is coupled to the input transistor. The second current source is coupled to the cascode transistor and is configured to provide a bias current to the cascode transistor that is complementary to absolute temperature. |
| US11095259B2 |
Trans-impedance amplifier, chip, and communications device
An integrated circuit, comprising an amplifier comprising a pair of inputs configured to receive a differential signal, a first resistor, a second resistor, wherein the first resistor and the second resistor are coupled in series with each other and coupled to a first input of the pair of inputs, a third resistor, a fourth resistor, wherein the third resistor and the fourth resistor are coupled in series with each other and coupled to a second input of the pair of inputs, and a first capacitor comprising a first end coupled to a first point between the first resistor and the second resistor, and a second end coupled to a second point between the third resistor and the fourth resistor, a second capacitor disposed between the first input and an output of the amplifier; and a third capacitor disposed between the second input and the output. |
| US11095258B2 |
Class AB amplifier and operational amplifier
A second main electrode of a first transistor is connected to a first main electrode of a sixth transistor, a second main electrode of the sixth transistor is connected to a first main electrode of a fifth transistor at a first node, a second main electrode of the fifth transistor is connected to a second main electrode of a second transistor, a control electrode of the fifth transistor is connected to the second main electrode of the fifth transistor, a second main electrode of a third transistor is connected to a first main electrode of a fourth transistor at a second node, and a control electrode of the fourth transistor is connected to the control electrode of the fifth transistor. A gain control amplifier controls a voltage supplied to a control electrode of the sixth transistor such that the first node and the second node are equal in voltage. |
| US11095256B2 |
Semiconductor device
A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch. |
| US11095254B1 |
Circuits and methods to reduce distortion in an amplifier
A device to reduce distortion in an amplifier includes an input transistor configured to generate a voltage based on an input signal. The device further includes a diode connected transistor that is configured to sink the current. The diode connected transistor includes an output terminal, and a control terminal, where the output terminal is coupled to a control terminal. The device further includes a current source circuit that coupled to the control terminal. The device additionally includes an impedance element that coupled to the output terminal at a first node and to the control terminal and the current source circuit at a second node. |
| US11095253B2 |
Analog to analog converter with quantized digital controlled amplification
Methods and systems for power amplification of time varying envelope signals are disclosed herein. In one embodiment, a plurality of signals with constant envelope generated from the decomposition of the quantized version of a time varying envelope signal are individually amplified and then summed to form a desired time-varying envelope signal. Amplitude, phase and frequency characteristics of one or more of the constituent signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time varying envelope signal. In another embodiment, a time-varying envelope signal is decomposed into in-phase and quadrature components that are quantized and decomposed into a plurality of quasi constant or constant envelope constituent signals. The constituent signals are amplified, and then summed to construct an amplified version of the original time-varying envelope signal. The signal amplifiers may be Class A, B, AB, C, D, Class F or Class S amplifiers to provide high amplification efficiency. |
| US11095249B2 |
Photovoltaic management and module-level power electronics
A photovoltaic (PV) system includes module-level power electronic (MLPE) devices that produce energy. The PV system includes a gateway to receive and send data to MLPE devices. The gateway also connects the PV system with a network, such as a local area network, that allows access to the Internet. The gateway provides functionality within the PV system to perform various processes to improve operation of MLPE devices. |
| US11095245B2 |
Apparatus for controlling inverter to drive motor
An apparatus for controlling an inverter to drive a motor includes: a current control processor generating a voltage command for generating d/q axis current detection values, which are obtained by measuring current supplied to the motor, to follow a d/q axis current command for driving the motor, the current control processor converting the voltage command, which is sampled according to a sampling frequency generated based on a voltage vector phase of the voltage command, into a voltage vector corresponding to a point on each vertex and each side of a hexagon in a voltage vector diagram to apply a resulting value to the inverter driving the motor; and a sample frequency computing processor computing the sampling frequency based on the voltage vector phase of the voltage command and a reference number of sampling times during one rotation period of the motor. |
| US11095242B2 |
Control device for controlling the current of a rotating field machine of a motor vehicle, current control method, drive unit and motor vehicle
A control device for controlling the current of a rotating field machine of a motor vehicle, includes a current controller for determining a fundamental of an output voltage for a respective operating point, a controller for modulating the output voltage by driving a rectifier of the control device based on a pulse pattern optimized offline for the respective operating point, and a current sensor for sampling a harmonics-impacted output current, resulting from the pulse pattern that is used, of the rectifier and for returning the sampled output current to the current controller. Sampling times for sampling the output current are optimized offline in a manner specific to the pulse pattern and are predetermined as those times at which a deviation between the harmonics-impacted output current and a fundamental of the output current is less than a predetermined threshold value. |
| US11095236B2 |
Detection of the type of an electric motor for the configuration of a variable speed drive
A method for configuring a variable speed drive in charge of power supply of an electric motor. The method comprises the application of a sequence of motor voltages to the electric motor by the variable speed drive and the obtaining, in parallel, of measurements of motor current. The method then determines a feature of the electric motor on the basis of the measurements of motor current and determines a type of electric motor at least as a function of the feature. The variable speed drive is then set up on the basis of the determined type of electric motor. |
| US11095233B2 |
Electric power conversion apparatus, motor drive unit and electric motion power steering apparatus
An electric power conversion apparatus includes a first inverter electrically connected to one end of each of phase windings of a motor, and a second inverter electrically connected to the other end of each of the phase windings, and a neutral point potential setting circuit electrically connected to the first inverter to set a potential of a neutral point in the first inverter when the first inverter is determined to be in an abnormal state. |
| US11095231B2 |
Multilevel power converter
A multilevel power converter has at least one phase module with a plurality of modules connected between positive and negative DC voltage connections. The phase module has a first phase module branch connected to the positive DC voltage connection, and a second phase module branch connected to the negative DC voltage connection. Each of the modules has at least two electronic switching elements and an electric energy storage unit. A third phase module branch connects the first phase module branch to the second phase module branch. A switching device connects an AC voltage connection of the multilevel power converter to a first connection node between the first phase module branch and the third phase module branch in a first switch position and connects the AC voltage connection to a second connection node between the third phase module branch and the second phase module branch in a second switch position. |
| US11095229B1 |
High switching frequency direct AC to AC converter
A direct AC to AC converter includes a modulation stage, a transformer and a de-modulation stage. The modulation stage is configured to convert an AC input voltage with a first frequency into a bipolar PWM voltage with a second frequency, wherein the second frequency is higher than the first frequency. The transformer has a primary winding and secondary winding, wherein the primary winding is coupled to the modulation stage to receive the bipolar PWM voltage. The de-modulation stage is coupled to the secondary winding of the transformer and configured to convert the voltage across the secondary winding of the transformer into an AC output voltage with the first frequency. |
| US11095228B2 |
Integrated self-driven active clamp
An active clamp circuit includes an active clamp capacitor coupled in series with an active clamp switch and an active clamp controller circuit to receive an active clamp switch current that passes through the active clamp switch and to control the active clamp switch based on the received active clamp switch current. The active clamp controller circuit is configured to enable the active clamp switch based on a first amplitude comparison, the first amplitude comparison being based on the active clamp switch current. The active clamp controller circuit is configured to disable the active clamp switch based on a second amplitude comparison and a third amplitude comparison, the second amplitude comparison and the third amplitude comparison being based on the active clamp switch current. |
| US11095227B2 |
Interleaved LLC resonant converter
An LLC converter includes a plurality of resonant circuits that each include a plurality of capacitors connected to a DC input voltage, a switching circuit including a plurality of switches connected to the DC input voltage, a plurality of transformers each including a plurality of primary windings and a plurality of secondary windings, and a plurality of synchronous rectifiers each connected to one of the plurality of secondary windings. The plurality of primary windings of each of the plurality of transformers includes a first primary winding and a second primary winding. Series-connected first primary windings are connected to a first resonant circuit of the plurality of resonant circuits, and series-connected second primary windings are directly connected to a second resonant circuit of the plurality of resonant circuits. Currents from each of the plurality of secondary windings are equal or substantially equal. |
| US11095224B2 |
Current equalization circuit, current equalization array circuit, and multiphase converter
In a current equalization circuit, where a first inductor is connected to a first resistor, a second inductor is connected to both the first inductor and a second resistor, the input end of the first resistor and the input end of the second resistor are respectively connected to a first input end and a second input end of an error detection sub-circuit, a first output end of the error detection sub-circuit is connected to a first error adjustment sub-circuit, a second output end of the error detection sub-circuit is connected to a second error adjustment sub-circuit, the first error adjustment sub-circuit adjusts an input current of the first inductor based on a voltage signal from the error detection sub-circuit, and the second error adjustment sub-circuit adjusts an input current of the second inductor based on a voltage signal from the error detection sub-circuit. |
| US11095222B2 |
High efficiency converter
A high efficiency converter is provided. The converter can be used in applications requiring fast transient response under a first loading condition, and high efficiency under a second loading condition. The converter converts one or more input voltages via two or more conversion paths. Each of the two or more conversion paths corresponds to a different loading condition which indicates a magnitude of a load driven by the converter (e.g., heavy or light), and a target transient response of the load (e.g., fast or slow). A conversion path for a heavy or fast loading condition converts an input voltage directly to a target output voltage. A conversion path for a light or slow loading condition includes a two-stage architecture. |
| US11095217B2 |
Ripple injection circuit and electronic device equipped with this circuit
A ripple injection circuit equipped with: a capacitor that passes a frequency component of an input voltage or a frequency component of an output voltage and that generates a first ripple voltage having a first ripple component; and an integration circuit that integrates a comparison result signal and that generates a second ripple voltage having a second ripple component. The first ripple component and the second ripple component are added to a feedback voltage. |
| US11095216B2 |
On-chip dual-supply multi-mode CMOS regulators
A method, an apparatus, and a computer program product are provided. The apparatus may be a regulator circuit. The regulator circuit includes a first voltage regulator to regulate a first input voltage to the first voltage regulator, the first voltage regulator including a P-type metal-oxide-semiconductor (PMOS), and a second voltage regulator to regulate a second input voltage to the second voltage regulator, the second voltage regulator including an N-type metal-oxide-semiconductor (NMOS). In an aspect, the first voltage regulator is coupled to the second voltage regulator. |
| US11095213B2 |
Reconfigurable switched capacitor DC-DC converter for head-wearable hearing devices
The present disclosure relates to a head-wearable hearing device comprising a switched capacitor DC-DC converter. Said switched capacitor DC-DC converter comprises a plurality of individually controllable semiconductor switches and a plurality of flying capacitors. A controller is connected to respective control terminals of the plurality of individually controllable semiconductor switches to configure first and second converter sections to form first and second converter topologies, respectively. |
| US11095210B2 |
Mitigation of touch current in handheld electrical tools
An arrangement (100) of an electrical power tool for reducing a touch current is disclosed. The arrangement comprises a filter (101) configured to reduce electrical interference, a voltage booster (102) configured to rectify and increase an alternating current into a direct current, a motor comprising a motor drive (104) configured to power the electrical power tool, and a choke impedance (103) arranged between the voltage booster and the motor drive such that an input of the choke impedance is connected to the voltage booster and an output of the choke impedance is connected to the motor drive. |
| US11095205B2 |
Method and device for on-line monitoring DC-bus capacitor
The method: determines, within the switching cycle, when current is not provided to the DC-bus capacitor, determines, for each switching cycle, the sector of a reference vector, active vectors durations and null voltage vectors durations, determines from the determined durations, sampling instants, samples the currents through the three phases and the DC-bus voltage at the determined sampling instants, determines, from the phase currents sampled at the determined sampling instants, the current flowing through the DC-bus capacitor during the active vectors, estimates the capacitance value and/or the equivalent series resistance value of the DC-bus capacitor, compares the capacitance value and/or the equivalent series resistance value to a threshold and determines if the DC-bus capacitor reaches its end of life according to the comparison result. |
| US11095204B2 |
Voltage regulator adapted for changing loads
A circuit is disclosed. The circuit includes a power supply node and a system configured to receive current from the power supply node at a regulated voltage and to generate one or more control signals indicating an anticipated change in the current. The circuit also includes a voltage regulator configured to provide the current to the power supply node and to drive the power supply node with the regulated voltage, where the value of the regulated voltage is based at least in part on the one or more control signals. |
| US11095201B2 |
Drive device and method for controlling drive device
A drive device includes a first gate driver circuit that controls operations of the first transistor by outputting a first control signal to a control terminal of the first transistor; a second gate driver circuit that controls operations of the second transistor so that the first transistor and the second transistor are turned on/off in a complementary manner, by outputting a second control signal to the control terminal of the second transistor; and a first charge pump circuit that applies the first negative power supply voltage to the first negative power supply wiring, by generating the first negative power supply voltage having a polarity opposite to that of the first positive power supply voltage with reference to a potential of the output terminal, based on the first control signal. |
| US11095200B2 |
Actuator
An actuator (1) is provided A substrate (15) held by a support (2) is provided with a total of six power supply electrodes (153) electrically connected respectively to both ends of a first coil (61) of a first magnetic drive circuit (6) that vibrates a movable body (3) in an X direction, both ends of a second coil (71) of a second magnetic drive circuit (7) that vibrates the movable body (3) in a Y direction, and both ends of a third coil (81) of a third magnetic drive circuit (8) that vibrates the movable body (3) in the X direction. An opening (110) that exposes the six power supply electrodes (153) is formed in a cover (11). |
| US11095192B1 |
System for cooling an electric motor
This disclosure pertains to a system for cooling an electric motor including a rotor which is connected to an output shaft, a stator disposed about the rotor, a casing in which the stator and rotor are disposed, and a cooling assembly. The cooling assembly includes an inlet configured to deliver coolant into the casing and directly onto the stator to cool the stator and an outlet configured to remove the coolant from the casing. The stator is a major source of heat within the electric motor and applying coolant directly to onto the stator is an effective method of cooling the motor. |
| US11095187B2 |
Rotary electric machine
A rotary electric machine includes a stator, a rotor, a case having two or more seat portions on which portions of a stator core are seated, and a reinforcement plate disposed on the top surface of the stator core. The stator core includes two or more attachment portions that are seated and fixed on the seat portions. The reinforcement plate is less likely to flex in the axial direction than the steel sheets, and is fixed on the top surface of the stator core so as to extend over at least two of the attachment portions. |
| US11095181B2 |
Rotary electric machine
A stator for a rotary electric machine includes a core extending along an axis and having a series of axially extending passages arranged circumferentially about the axis. A plurality of teeth are provided with each tooth including an axially extending inner surface defining a passage and a projection extending therein. Retention devices secure each tooth to the stator. Each retention device includes a resilient member having a base extending within one of the passages of the stator and an arm extending from the base and within the passage of one of the teeth. The arm including an enlarged portion for engaging the projection to pull the tooth into engagement with the core. |
| US11095179B2 |
Thermosetting resin composition, stator coil obtained using same, and rotating electric machine
A thermosetting resin composition of the present disclosure includes an epoxy resin (1) containing a curing agent, and inorganic particles (2) having a rutile-type crystal structure and an average particle diameter of 500 nm or less. Further, a stator coil of the present disclosure includes a coil conductor (6), and an insulating layer (7) obtained by winding an insulating tape around the coil conductor (6), impregnating the insulating tape with the thermosetting resin composition, and molding the impregnated insulating tape by heating and pressurizing. In addition, a rotating electric machine of the present disclosure includes a stator core (4) having a slot (10), in which the stator coil (5) is accommodated. According to the present disclosure, it is possible to obtain a thermosetting resin composition capable of achieving improvement in machine life through suppression of partial discharge and miniaturization and high output of the machine through improvement of a dielectric-breakdown electric field property, a stator coil obtained through use of the thermosetting resin composition, and a rotating electric machine. |
| US11095176B2 |
Aluminum form-wound coil and winding structure, and stator for a generator of a wind turbine, and method for producing a stator
A form-wound coil for a stator of a generator of a gearless wind power installation. The form-wound coil comprises an electrical conductor, wherein the electrical conductor has a plurality of turns and also a first end and a second end. The first end has a first connecting part for connection to a connecting element and the second end has a second connecting part for connection to a further connecting element and the electrical conductor comprises aluminum or is substantially composed of aluminum. A connecting element for connecting a connecting part of a form-wound coil to a connecting part of a further form-wound coil. A winding structure for a stator and also to a stator and to a method for producing a stator. |
| US11095173B2 |
Stator for rotating electric machine, and rotating electric machine
A stator core of a rotary electric machine includes: an outer core that is an annular back yoke portion; and an inner core in which a plurality of teeth are radially arranged and inner side end portions of the teeth adjacent to each other in a circumferential direction are connected to each other in the circumferential direction by connection portions and which is fitted to an inner side of the outer core, each connection portion has a hole penetrating in an axial direction, each connection portion is split into a plurality of sections by the hole, a width in a radial direction of the one connection portion at a portion of the connection portion that has a smallest width in the radial direction is equal to or greater than ¼ and less than ½ of a sheet thickness of each of sheets. |
| US11095172B2 |
Electric machine
The invention relates to an electric machine (10) comprising a stator (11) which comprises a plurality of slots (14) and is adjacent to an air gap (17). The electric machine (10) further comprises a first material (15) having a first electrical conductivity, wherein the first material (15) in each case fills the slots (14) partially, and a second material (16) having a second electrical conductivity that is lower than the first electrical conductivity. The second material (16) exclusively fills an edge region (20) of the slots (14) and the edge region (20) is located in the slots (14) on the side facing the air gap (17). The first material (15) in the slots (14) is electrically conductively interconnected on a first side of the stator (11). The invention furthermore provides an electric machine (10) having a rotor (12). |
| US11095165B2 |
RF power harvester
An RF power harvester comprising a dielectric substrate, having a first major surface and a second major surface, opposite to the first major surface; a connection for a rectifier on the first major surface; an antenna carried on the substrate for harvesting electrical power from a radio frequency electromagnetic field. The antenna comprising a first track of conductive material, carried on the first major surface and comprising a first end adjacent an edge of the substrate, a second end for connection to the rectifier, a first series of line sections between the first end and the second end and a first plurality of meanders, wherein a first line section of the series provides the first end and each subsequent line section is connected to its preceding line section by a meander and is of greater length than its preceding line section. |
| US11095163B2 |
Non-contact power reception apparatus for non-contact charging and electronic settlement performed in a single portable terminal
A non-contact power reception apparatus is provided, in which a power reception coil for a charging system and a loop antenna for an electronic settlement system are mounted on a battery pack and a cover case of a portable terminal such that the power reception coil is arranged in the center thereof and the loop antenna is disposed outside the power reception coil, so that a mode of receiving a wireless power signal and a mode of transmitting and receiving data are selectively performed, thereby preventing interference from harmonic components and enabling non-contact charging and electronic settlement using a single portable terminal. A jig for fabricating a core to be mounted to the non-contact power reception apparatus is provided. |
| US11095161B2 |
Power transmission apparatus, wireless power transfer system, and power transmission method
According to one embodiment, power transmission circuitry configured to generate a magnetic field by AC current flowing through a coil, and to transmit AC power by coupling the magnetic field with a coil of a power reception apparatus, wherein a frequency of the AC current is higher than a frequency of AC power supply to the power transmission apparatus; and control circuitry configured to change a frequency of the AC current in accordance with a first order of first to n-th frequencies during a power transmission of the power transmission circuitry, wherein the first order comprises each of the first to n-th frequencies one time. |
| US11095160B2 |
Non-contact power supply device
A power transmission device 2 in a non-contact power supply device 1 has: a transmission coil 14 that supplies power to a power reception device 3; and a power supply circuit 10 that supplies AC voltage having a switching frequency at which the transmission coil 14 does not resonate, to the transmission coil 14. A power reception device 3 has: a resonance circuit 20 having a reception coil 21 that receives power from the power transmission device 2 and a resonance capacitor 22 connected in parallel to the reception coil 21; a rectification circuit 24 that rectifies power output from the resonance circuit 20; and a coil 23 connected in series to the reception coil 21, between the resonance circuit 20 and the rectification circuit 24. |
| US11095158B2 |
H-bridge gate control apparatus
An apparatus includes a first switch and a second switch connected in series between a first voltage bus and a second voltage bus, wherein a common node of the first switch and the second switch is connected to a first terminal of a first coil magnetically coupled to a second coil, and a third switch and a fourth switch connected in series between the first voltage bus and the second voltage bus, wherein a common node of the third switch and the fourth switch is coupled to a second terminal of the first coil, and wherein a gate of the first switch is controlled by a first signal derived from a signal on the common node of the third switch and the fourth switch, and a gate of the third switch is controlled by a second signal derived from a signal on the common node of the first switch and the second switch. |
| US11095152B2 |
Energy storage modeling and control
Systems and methods for optimal planning and real-time control of energy storage systems for multiple simultaneous applications are provided. Energy storage applications can be analyzed for relevant metrics such as profitability and impact on the functionality of the electric grid, subject to system-wide and energy storage hardware constraints. The optimal amount of storage capacity and the optimal operating strategy can then be derived for each application and be prioritized according to a dispatch stack, which can be statically or dynamically updated according to data forecasts. Embodiments can consist of both planning tools and real-time control algorithms. |
| US11095147B2 |
Voltage supply unit and method for regulating energy states of a battery
A voltage supply unit is provided with a first output adapted to supply a first voltage to a first load and provided with a second output adapted to supply a second voltage to a second load. The voltage supply unit includes a first battery stack, a second battery stack and an electronic control unit, wherein the electronic control unit is adapted to regulate the energy state of the first battery stack to a first energy state, and to regulate the energy state of the second battery stack to a second energy state, where the first energy state differs from the second energy state. Power characteristics of the voltage supply unit can be optimized by allowing the energy states of the first and the second battery stacks to differ. |
| US11095145B2 |
Refrigerator
A refrigerator includes: an inner casing having a storage chamber defined therein; a middle plate surrounding an outer surface of the inner casing; a thermal-insulating material disposed between the inner casing and the middle plate; a module mounting casing fixed to the middle plate and having a top opening and an inserting opening; a cabinet cover to cover the top opening and to define a top appearance of the refrigerator; and a wireless charging module mounted on the module mounting casing through the inserting opening, wherein the wireless charging module includes an coil part for wirelessly-charging a battery of a mobile device placed on the cabinet cover. |
| US11095140B1 |
Large-format battery managment system
A battery system with a large-format Li-ion battery powers attached equipment by discharging battery cells distributed among a plurality of battery packs. The discharging of the battery cells is controlled in an efficient manner while preserving the expected life of the Li-ion battery cells. Each battery pack internally supports a battery management system and may have identical components, thus supporting an architecture that easily scales to higher power/energy. Battery packs may be added or removed without intervention with a user, where one of battery packs serves as a master battery pack and the remaining battery packs serve as slave battery packs. When the master battery pack is removed, one of the slave battery packs becomes the master battery pack. Charging and discharging of the battery cells is coordinated by the master battery pack with the slave battery packs over a communication channel such as a controller area network (CAN) bus. |
| US11095139B2 |
Adaptive battery charging
In an embodiment, adaptive charging of a battery is disclosed. In an embodiment, a device is disclosed comprising: a battery; at least one sensor configured to sense an outward pressure exerted by the battery; a monitoring module configured to monitor the outward pressure of the battery and at least one of a temperature, an age, a manufacturer, a state of charge, an impedance, and number of charging cycles of the battery; a control module configured to select a charging profile for the battery based on at least one of the sensed and/or monitored battery related variables; and a charging module configured to charge the battery according to a charging profile selected by the control module. |
| US11095137B2 |
Wireless power transmission device for vehicle
A wireless power transmission device for a vehicle is provided. A wireless power transmission device for a vehicle comprises: a magnetic field shielding sheet having a plate shape and a predetermined area, at least one wireless power transmission antenna disposed on a first surface of the magnetic field shielding sheet, and a wireless communication antenna formed in an antenna pattern on at least one surface of a circuit board, wherein the circuit board is disposed on a second surface of the magnetic field shielding sheet which is a surface opposite to the first surface. |
| US11095136B2 |
Battery pack and charging assembly
A battery pack is detachably connectable to an electric tool or a charger and includes a housing, a cell group, a first voltage monitoring module, a control module, a second voltage monitoring module and a protection module. The cell group includes a plurality of cells electrically connected to each other. The first voltage monitoring module monitors at least one of the voltage of each cell or the total voltage of the cell group. The second voltage monitoring module monitors the voltage of each cell to detect whether the cells are in an overvoltage state. The protection module is electrically connected to the second voltage monitoring module and when the second voltage monitoring module monitors that any one of the cells is in the overvoltage state, cuts off a charging path formed between the battery pack and the charger. |
| US11095134B2 |
Method of producing a modular battery storage system, modular battery storage system, and battery management system therefor
A modular battery storage system includes energy storage modules. A switch is assigned to individual energy storage modules, by which the respective energy storage module can be activated and deactivated. The energy storage modules can connect to one another by the switches such that the individual voltages of activated energy storage modules can be added up to form a total voltage. A method of operating the battery storage system ascertains at least one power value for each of the energy storage modules, the power value being characteristic of the power capacity of the energy storage module. A total voltage is generated by at least two energy storage modules being activated with a time overlap but over activation periods of different length. One of the activation periods of different length is assigned to each of the at least two energy storage modules depending on the ascertained at least one power value. |
| US11095128B2 |
Voltage balance correction circuit
A voltage balance correction circuit includes multiple voltage correction circuits that correspond one-to-one to multiple electricity storage cells connected in series, and a control circuit that is configured to control the multiple voltage correction circuits based on voltages of the multiple electricity storage cells. The multiple voltage correction circuits include first coils that are connected to the electricity storage cells in parallel, respectively, field-effect transistors that are configured to turns on/off connections of the first coils with the electricity storage cells, respectively, under control of the control circuit, and second coils that are magnetically respectively coupled with the first coils. In the multiple voltage correction circuits, the second coils are connected in parallel. |
| US11095125B2 |
Device and method for harvesting energy from a power line magnetic field
An energy harvesting device (CTH) installed in an electrical distribution system (EDS) for powering ancillary electrical devices (AD) used in the distribution system. The device includes a first voltage regulator circuit (CC) configured to produce a voltage matched to a power curve of a current transformer (CT) to which the device is electrically coupled. The device also includes a second and separate voltage regulator circuit (SVR) which continuously operates to maximize the amount of electrical energy recovered from the current transformer. |
| US11095124B2 |
Method for compensating feed-in currents in a wind park
A wind farm for feeding a total electric current into an electrical supply network at a network connection point is provided. The wind farm has at least one wind power installation designed as a compensation wind power installation and an active compensation unit to generate a compensating component current having a modulated compensation proportion. At least one wind power installation without compensation is configured to generate a non-compensating component current without a modulated compensation proportion. The compensating component current and the non-compensating component current are superposed to form the total electric current to be fed in in a farm network that connects the wind power installations. The compensating component current is generated so that the total current to be fed in influences an occurring reference current or an occurring reference voltage to achieve a prescribed current form for the reference current or a prescribed voltage form for the reference voltage. |
| US11095122B2 |
DC-DC converter control apparatus and DC-DC converter control method
A DC-DC converter control apparatus, installed in a vehicle including parallel-connected first and second DC-DC converters and in-vehicle devices configured to operate on an electric power that is output from at least one of the first and second DC-DC converters, is configured to control the first and second DC-DC converters, and includes a processor. The processor is programmed to monitor an operational status of at least one predetermined device that is included in the in-vehicle devices; when the at least one predetermined device is not in operation, set at least a controlled target value of an output voltage of the first DC-DC converter to a target voltage for operating the in-vehicle devices; and, when at least one of the at least one predetermined device is in operation, set controlled target values of output voltages of both the first and second DC-DC converters to the target voltage. |
| US11095119B2 |
Corrosion mitigation for an external connector of an electronic device
A voltage of a first pin that is one of several pins of an external connector of a system is measured, while the first pin is un-driven except for being pulled to ground through a first resistance, and a second pin of the external connector is being used as a power supply rail of the system. The measured voltage is compared to a short circuit threshold and in response to that threshold being exceeded, the power supply voltage on the second pin is reduced. In such an embodiment, no test stimulus needs to be applied to any of the pins of the external connector. Other embodiments are also described and claimed. |
| US11095118B2 |
Controlled holdup discharge for improved component reliability
A method of controlling discharge of a holdup capacitor in a power system having a voltage source, a holdup capacitor and a load. The method including operably connecting the voltage source to the load, monitoring a first voltage of the voltage source, and if the first voltage of the voltage source drops below a selected threshold, directing energy from the holdup capacitor to the load via a first path, and directing energy from the holdup capacitor to the load via a second path if a selected condition is satisfied. |
| US11095117B2 |
DC-DC converters having DIN rail mounts
Example DC-DC power distribution systems include electronic communication device(s), a circuit breaker DIN rail adapted to receive a circuit breaker for providing electrical protection to the one or more electronic communication devices, and a DC-DC converter including a housing having a DIN rail mount, a voltage input and a voltage output. The DC-DC converter includes a DC-DC voltage converter circuit coupled between the voltage input and the voltage output, and a controller electrically coupled with the DC-DC voltage converter circuit. The DC-DC converter is mounted on the circuit breaker DIN rail via the DIN rail mount of the DC-DC converter housing, and the controller is configured to control the DC-DC voltage converter circuit to convert a DC voltage at the voltage input to a different DC voltage at the voltage output to supply power to the one or more electronic communication devices. |
| US11095112B2 |
Driving protection circuit, operating circuit and control method
A driving protection circuit is coupled to a load via an input/output pin. A signal generator circuit is configured to generate a driving signal. An input/output circuit transmits the driving signal to the input/output pin according to an enable signal. A counter circuit adjusts the count value when the enable signal is at a predetermined level. A detection circuit detects the voltage level of the input/output pin to generate a detection signal. When the count value is equal to a predetermined value, a control circuit determines whether the level of the detection signal is the same as the level of the driving signal. When the level of the detection signal is not the same as the level of the driving signal, the control circuit sends an error signal to turn off power to the load. |
| US11095108B2 |
Point of use protective wiring device
The present invention is directed to protective wiring devices, and more particularly, to a protective wiring device that meets the prevailing electrical codes and is convenient for a homeowner to reset after it has tripped. |
| US11095104B2 |
Chord organizer
A cord organizer has a flexural board with a back, a front, a width, a length and a thickness. A frontal surface has rectangular facets separated by open-ended elongate slots, and each open-ended elongate slot is coextensive with an open-ended elongate chamber forming a cord retainer, which is recessed within the thickness. When the flexural board is angularly flexed the rectangular facets fan out and each of the open-ended elongate slots are widened, therein widening access to each of the open-ended elongate chambers; and while widened the cord retainers are individually fitted with a sectional length of a cord. When the flexural board is released it returns to its relaxed state, wherein the cord retainers envelop and restrain each of the cords on the flexural board. |
| US11095100B1 |
Apparatus for transporting and dispensing wire or cable from a barrel pack
An apparatus for the movement of a barrel pack containing spooled wire or cable. The apparatus comprising a frame, a handle attached to the frame, a plurality of wheels rotatably attached to the frame, securing structures attached to the frame, the securing structures securing the barrel pack to the frame and a footage counting assembly attached to the handle. The footage counting assembly counts the amount of footage of wire or cable passing through the footage counting assembly. |
| US11095098B2 |
Power supply cabinet
The present application provides a power supply cabinet, comprising a first power supply region and a second power supply region including at least one slot for receiving a first power supply module and a second power supply module respectively, a mode switching unit for outputting a mode signal to the first power supply module and the second power supply module, and a position setting unit for outputting a position signal to the first power supply module and the second power supply module. Input sides of the first power supply module and the second power supply mode are electrically connected to a first power supply and a second power supply. The power supply cabinet selectively operates in a first power supply mode (e.g. N+N mode) or a second power supply mode (e.g. N+1 mode) depending on the mode signal or types of the power supplies. |
| US11095088B1 |
Multi-pass coaxial molecular gas laser
A multi-pass coaxial molecular gas laser is described in both symmetrical and asymmetrical configuration. An anode vessel receives lasing gas and the gas flows through one or more plasma channels to a cathode vessel which receives the gas and redirects it in the closed system. A second anode vessel may alternatively be provided to double length of the plasma channel and increase surface area exposure of the optical beam to the energized gas. Non-laminar gas flow may be created using spiral nozzles at the entrance of the optical resonator. |
| US11095085B2 |
System and method for laser system having non-planar thin disc gain media
The present disclosure relates to a laser system. The laser system may have at least non-flat gain media disc. At least one pump source may be configured to generate a beam that pumps the non-flat gain media disc. A laser cavity may be formed by the pump source and the non-flat gain media disc. An output coupler may be included for receiving and directing the output beam toward an external component. |
| US11095076B2 |
Cable connector
A cable connector includes a cable having wire pairs and contacts in contact pairs. The contacts of the contact pairs may be simultaneously crimped to the corresponding wires by a crimp tool. Pair holders hold the contact pairs with an overmolded body molded around supporting bases of the contacts of the contact pair to fix relative positions of the contacts. The cable connector includes a pair shield having shield elements forming shield pockets receiving wire pairs, contact pairs, and pair holders. The cable connector includes a retainer having a retainer cavity that receives the wire pairs and the pair shield. The retainer includes a contact support to support the pair holders and the contact pairs. The cable connector includes an outer shell having an outer shell cavity that receives the retainer and provides electrical shielding for the contact pairs. |
| US11095075B2 |
Electrical device with a plug connector having a flexible section
An electrical device including a plug connector. The plug connector includes a first flexible substrate having a plurality of signal contacts, the first flexible substrate extending from a terminating end to a mating end and configured to be flexible between the terminating end and mating end. A second flexible substrate extends in parallel spaced relation to the first flexible substrate to form a cavity between the first flexible substrate and second flexible substrate. The second flexible substrate having a plurality of signal contacts. The second flexible substrate extends from a terminating end to a mating end and configured to be flexible between the terminating end and mating end. The plug connector includes a rigid section disposed in the cavity at the mating end, the first flexible substrate moves in relation to the rigid section. |
| US11095073B2 |
Locking clip
A locking clip for plug housings has a rear wall and side parts formed on the rear wall. The locking clip has a U-shaped cross-section. The side parts each have a mounting receptacle, by which the locking device can be pivotably mounted on the plug housing. The locking device has an embossment directed toward the plug housing in the region of each mounting receptacle. Thus, the locking device is not supported on the plug body over the full surface, and therefore a lower-wear locking operation is ensured. A system includes a first plug housing and a second plug housing and a locking clip. The locking clip is pivotably mounted on the first plug housing by mounting pins. The locking clip can be locked on the second plug housing on locking pins. The locking clip touches the plug housings only at the mounting pins and at the locking pins. |
| US11095072B2 |
Coaxial connector having torque-limiting compression ring
A connector is provided for attachment to a coaxial cable. The connector includes, in one embodiment, a body and a compression ring. The body has a cable receiving end being configured to receive the end of the coaxial cable. The compression ring includes a forward sleeve portion and a rearward outer ring portion attached to one another by a plurality of tabs. The forward sleeve portion is configured to couple to the cable receiving end of the body. The plurality of tabs are configured to shear so as to separate the rearward outer ring portion from the forward sleeve portion when a torque for rotating the compression ring relative to the body exceeds a desired torque. |
| US11095071B2 |
Connector, electronic component, and electronic device
A connector is configured to connect a first electronic component and a second electronic component, and includes: an enclosure, where a through-hole is disposed on the enclosure; a pin assembly disposed in the enclosure, the pin assembly is movable relative to the enclosure; a flexible printed circuit board, where one end of the flexible printed circuit board is connected to the pin, and the other end is configured to be connected to a circuit board in the first electronic component; a plug structure configured to be detachably connected to the second electronic component; and a driving assembly, where when the second electronic component is connected to the plug structure, the driving assembly is able to drive the pin assembly to move relative to the enclosure in a direction close to the through-hole, so that the pin extends out of the through-hole and is connected to the second electronic component. |
| US11095065B2 |
Combination structure of socket of power supply device
A power supply device includes a housing having a socket opening, and a pair of sliding grooves are formed on the socket opening. A guiding piece is formed at a bottom of each sliding groove, and the guiding piece includes a positioning section and a guiding section. A power socket passes through the sliding grooves along the guiding section, and one side of the power socket is abutted against the positioning section so as to contact the socket opening. A cover plate is provided with a pair of clips corresponding to the sliding grooves, and the clips are inserted into the pair of sliding grooves and abutted against a side of the power socket for positioning the power socket. |
| US11095063B2 |
Terminal metal fitting and engagement structure of terminal metal fitting and housing
A terminal metal fitting (10) includes a tubular box portion (11) receiving a counterpart terminal; a lock hole (14) formed through a wall (11a) of the box portion (11) and receiving the lock projection (25); a terminal spring (16) extending from an inner wall surface of the box portion (11) to press and contact to the counterpart terminal; and a supporting point portion (15) formed at a portion around the lock hole (14) to have a cantilevered-shape. The supporting point portion (15) serves as a supporting point (15a) when the terminal spring (16) contacts to the counterpart terminal. |
| US11095062B2 |
Connector assembly
A connector assembly includes a system connector having a system housing and a system bracket coupled with the system housing. The system bracket includes plural system power contact receptors that receive plural system power contacts. The plural system power contacts are separate from each other by one or more extensions coupled with the system bracket. A module connector is coupled with the system connector. The module connector includes a module housing and a module bracket coupled with the module housing. The module bracket includes plural module power contact receptors that receive plural module power contacts. Each of the plural module power contacts are separated from each other by one or more extensions coupled with the module bracket. Each of the plural system power contacts of the system bracket are configured to mate with one of the plural module power contacts of the module bracket as plural power contact assemblies. |
| US11095061B2 |
Electrical plug connector
An electrical plug connector for a coaxial or triaxial cable, wherein the cable includes an internal conductor, a first shielding conductor surrounding the internal conductor and extending coaxially with it, and optionally a second shielding conductor surrounding the first shielding conductor. The plug connector has a connector body, which includes an internal conductor contact element designed as a plug, socket, or coupling, for contacting with the internal conductor, an internal shield contact element provided for contacting with the first shielding conductor, and optionally an external shield contact element provided for contacting with the second shielding conductor. The connector body is configured such that the contact elements in the mounted condition of the plug connector are arranged on the cable such that a maximum diameter of the connector body is less than or equal to the outer diameter of the cable or only slightly larger than the outer diameter of the cable. |
| US11095060B2 |
Bottom layer mount for USB connector
In embodiments, a USB connector may include a plurality of pins on a front surface and a plurality of pins on a top surface. The pins may be oriented and positioned on the USB connector such that the USB connector may be mounted to the bottom layer of a PCB. Corresponding pins of the USB connector may be conductively connected and may be mated with corresponding pins of the PCB. |
| US11095055B2 |
Terminal block and terminal block assembly for medium to high voltage applications
Systems and method are described for a terminal block that can include an insulating block that is composed of an electrically insulating material. The insulating structure can have a first via extending between a first and second opening in the insulating block. A second via can extend between a third and fourth opening in the insulating block. A distance between the first and second openings may be less than a distance between the third and fourth openings. A first electrical conducting element can extend between the first and second openings. A second electrical conducting element can extend between the third and fourth openings. The first and second electrical conducting elements can be separated from one another by a portion of the insulating block. |
| US11095054B2 |
Conductor terminal and method of assembling a conductor terminal
A conductor terminal with at least one spring force terminal connection for the connection of an electrical conductor via spring force clamping. The spring force terminal connection has a clamping spring. The conductor terminal has a housing and an actuating lever which is pivotably mounted in a pivoting plane in the housing for actuating the clamping spring. The actuating lever is formed with at least one clamping spring actuator element and at least one control element. The clamping spring actuator element actuates the clamping spring and the control element has at least one handle portion for manually actuating the actuating lever. The control element and the clamping spring actuator element have mutually corresponding fastening elements, via which the control element and the clamping spring actuator element are form-fittingly and/or force-fittingly connected to one another. |
| US11095053B1 |
Tool-less terminal block
A tool-less terminal block includes an insulated base, a turning part, a conductive terminal and a spring clamp. The insulated base has a cavity and a slot communicating to the cavity; the turning part is pivotally coupled to the insulated base; the conductive terminal is fixed to the bottom of the slot; the spring clamp is accommodated in the cavity and disposed at the top of the conductive terminal, and the spring clamp has a movable elastic arm pressing the conductive terminal to seal the slot, and the movable elastic arm has a link rod fixed to the turning part and operable together with the turning part. When the turning part is turned to a released position, the link rod is pulled by the turning part to drive the movable elastic arm away from the conductive terminal to open the slot, so as to provide a convenient use. |
| US11095051B2 |
Clamp with a conductive bridge mechanism
A clamp is provided, including: the first clamp body, provided with a first jaw; a conductive bridge mechanism, for electrically connecting to an electrode and comprising a reciprocating assembly, an elastic engaging element, and an operable portion. The elastic engaging element is provided between the reciprocating assembly and the operable portion and is independent and separated from the reciprocating assembly. The elastic engaging element can be operated to move towards the reciprocating assembly. The reciprocating assembly can be mutually engaged and positioned with the elastic engaging element. When the elastic engaging element is positioned at a third position, the reciprocating assembly can be engaged by the elastic engaging element and thus be positioned at a second position so as to allow the first jaw to be electrically connected to the electrode; when the elastic engaging element is operated and positioned at a fourth position, the reciprocating element is not stopped by the elastic engaging element and can thus be automatically positioned at the first position and not electrically connected to the first jaw. |
| US11095046B2 |
Antenna structure
An antenna structure includes a substrate, a first polarization antenna group, and a second polarization antenna group. The substrate is defined with a first axis and a second axis. The first polarization antenna group and the second polarization antenna group are disposed on the substrate. The first polarization antenna group includes a first dipole antenna, a second dipole antenna, and a first wire. The first wire is separate from and coupled to the first dipole antenna and the second dipole antenna. The second polarization antenna group includes a third dipole antenna, a fourth dipole antenna, and a second wire. The second wire is separate from and coupled to the third dipole antenna and the fourth dipole antenna. |
| US11095043B2 |
Electronically-controlled polarization of antenna arrays
A system and method is provided in which a single-pole-double-throw switch controls whether a circular loop transmits a right-hand circular polarized signal or a left-hand circular polarized signal. The single-pole-double-throw switch is shielded from the circular loop by a metallic ground plane. An annulus of dielectric insulates the circular loop from the metallic ground plane. |
| US11095040B2 |
Antenna and mimo antenna
An antenna includes a ground plane, a first resonator connected to a feeding point for which the ground plane serves as a reference, a second resonator configured to receive power from the first resonator through electromagnetic coupling or magnetic coupling in a contactless manner, at least one director located away from the first resonator and the second resonator, and wherein the ground plane located at a side opposite to the director with respect to the second resonator is used as a reflector, or the antenna further comprises a reflector located at the side opposite to the director with respect to the second resonator. |
| US11095039B2 |
Communication apparatus
A communication apparatus (1) includes a radio wave radiation source (10), a phase control plate (11) disposed near the radio wave radiation source, and a polarization control plate (12) disposed to be substantially parallel to the phase control plate (11). In the phase control plate (11), a phase of a transmitted electromagnetic wave differs according to a distance from a first representative point on the phase control plate (11). In the polarization control plate (12), a polarization state change given to a transmitted electromagnetic wave at a reference point differs according to an angle formed between a representative line connecting a second representative point on the polarization control plate (12) to an edge of the polarization control plate (12), and a reference line connecting the second representative point to the reference point on the polarization control plate (12). |
| US11095036B1 |
Coupled-slot airfoil antenna
Antennas for radiating radio frequency energy that are integrated into a structure are provided. In particular, one or more nonconductive slots are formed in one or more convex layers or surfaces of a structure. Moreover, each nonconductive slot can be associated with one or more feeds. In at least some embodiments, the structure is an airfoil with a first convex surface joined to a second convex surface along an edge, and the at least one nonconductive slot extends from a point in the first surface or a layer of the structure including the first surface across the edge to a point in the second surface or a layer of the structure including the second surface. |
| US11095034B2 |
Antenna, peripheral circuit, antenna system, and signal processing method
The antenna in the embodiments provided includes: a first-layer antenna, a second-layer antenna, a first probe, a second probe, a first connector, and a second connector. An annular microstrip patch is attached to each of main bodies of the first-layer antenna and the second-layer antenna. The annular microstrip patch attached to the first-layer antenna is provided with a first feeding network and a second feeding network therein. The first-layer antenna is connected to the first probe and the second probe by using the first feeding network and the second feeding network respectively. The first-layer antenna is connected to the first connector and the second connector. A position of the first connector corresponds to a position where the first probe is connected to the first-layer antenna. A position of the second connector corresponds to a position where the second probe is connected to the first-layer antenna. |
| US11095033B2 |
Antenna apparatus and terminal
An antenna apparatus includes a radiator and two feeding branch circuits, where a first feeding branch circuit includes a first feedpoint and a first filter circuit electrically coupled between the first feedpoint and the radiator, and where the first feedpoint is configured to feed a first signal of a first frequency band. A second feeding branch circuit includes a second feedpoint and a second filter circuit electrically coupled between the second feedpoint and the radiator, with the second feedpoint configured to feed a second signal of a second frequency band. The first filter circuit is configured to allow the first signal to pass through and ground the second signal. The second filter circuit is configured to allow the second signal to pass through and ground the first signal. |
| US11095031B2 |
Lossy antenna arrays with frequency-independent beamwidth
An ultra wide band (UWB) antenna includes: (i) an array of antenna elements spaced from a central axis; and (ii) a network of lossy feedlines respectively communicatively coupled to the array of antenna elements. Each lossy feedline is periodically loaded with a resistance that is capacitively coupled to ground. Respective lengths of each lossy feedlines are selected to increase with an increase in distance from the central axis to achieve frequency independence of a radiated beamwidth from the UWB antenna. |
| US11095029B2 |
Antenna device
An antenna device includes first antenna units, second antenna units, first switching circuits and second switching circuits. The first antenna units generate radio frequency (RF) signals operating at a first frequency. The second antenna units generate RF signals operating at a second frequency. The first frequency is larger than the second frequency. The first switching circuits selectively enable at least one of the first antenna units. Each of the first switching circuits includes a first switch element and a second switch element. The first switch element is connected in parallel with an inductor. The second switch element is connected in parallel with another inductor. The second switching circuits selectively enable at least one of the second antenna units. |
| US11095027B2 |
Compressed closed circuit circularly polarized omni-directional antenna
Compressed closed circuit circularly polarized (CLCP) omni-directional antennas and methods of fabrication are described. Such an antenna reduces the size of conventional circularly polarized antennas while also allowing increased axial ratio. An antenna comprises a plurality of conductive elements at an angle of between 5 and 52 degrees spaced radially around a multi-element feed system. The multi-element feed system may be made from a PCB and fed from a coaxial cable. The plurality of conductive elements may contain between 2 and 8 individual conductive elements. Each element in the plurality of conductive elements is a closed loop. The antenna may be covered by a protective housing which may also further reduce the size of the antenna. |
| US11095026B2 |
Communication device with extended grounding structure to enhance antenna performance
The disclosure provides a communication device including a ground plane, an antenna and an extended grounding structure. The ground plane has a first side and a second side opposite to each other. The antenna is disposed at the first side and has a first feeding end. The extended grounding structure is disposed at the second side and includes a connection portion and a symmetrical structure. The symmetrical structure is electrically connected to the ground plane via the connection portion, wherein the symmetrical structure is symmetrical along a symmetry axis, and an extension line of the symmetry axis passes through the first side and the second side. The disclosure can effectively prevent antenna efficiency from being degraded due to an insufficient size of the ground plane, so as to significantly enhance communication quality. |
| US11095025B2 |
Radome wall for communication applications
A radome wall for communication in a frequency band of from 17 to 31 GHz for use on commercial aircraft includes a multilayer structure having an alternating arrangement of force-absorbing solid cover layers and sheer-rigid core layers. The radome wall includes at least four of the cover layers, of which two form outer sides of the radome wall, the cover layers and the core layers being made of a dielectric material. |
| US11095016B2 |
Vehicle roof having conductive coating for wireless communication
A vehicle and a method for enhancing wireless communication for the vehicle are provided. The vehicle includes a glass panel that is disposed on a roof of the vehicle and an electrically conductive coating applied to the glass panel. The conductive coating is electrically connected to an electrically conductive portion of a vehicle body. The method for enhancing wireless communication for the vehicle includes coating a glass panel of a vehicle roof with an electrically conductive coating and electrically connecting the conductive coating to an electrically conductive portion of a vehicle body. |
| US11095013B1 |
Integrated Tera-Hertz slide screw tuner
A waveguide low profile slide-screw impedance tuner, for high tuning range (GAMMA) and seamless on-wafer integration, uses spring-loaded control of gold-plated alumina (Al2O3) tuning probe, controlling amplitude and phase of the reflection factor using miniature high precision piezo-electric actuators. This ensures the highest possible passive reflection factor GAMMA at THz frequencies. The tuner is integrated on appropriately modified commercially available THz waveguide wafer probes. |
| US11095012B2 |
Methods for conductively coating millimeter waveguides
A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core. |
| US11094992B2 |
Battery
The present application relates to the field of energy storage device production technology, in particular, to a battery comprising a battery body and a flange portion; the battery body includes a first side face protruding from a surface of the battery body; the flange portion is arranged outside the battery body and includes a protrusion segment connected to the battery body, the protrusion segment protruding away from the battery body. The present application ensures the amount of glue at the valley bottom of the side as much as possible, so that the adhesive force here is improved, the tightness of the valley bottom is ensured and the problem of opening the flange portion when transporting, using, or storing is reduced as much as possible. |
| US11094986B2 |
Power storage unit
A power storage unit 1 in which a power storage element is housed in a metal case and which is to be attached to a vehicle via a metal bracket includes a holder that holds the power storage element within the metal case, a bracket receiving portion that is provided in the holder and is to be engaged with the bracket and transmit the load of the holder and the power storage element to the bracket, and a connection piece that is provided in the metal case and is to come into contact with the bracket and electrically connect the metal case to the bracket. |
| US11094984B1 |
Swelling resistant pouch batteries
Systems, methods, and computer-readable media are disclosed for swelling resistant pouch batteries. In one embodiment, an example battery may include a pouch having an aluminum layer with a first portion and a second portion, and at least one cell that is partially positioned within the pouch. The at least one cell may include an anode, a separator, a cathode, and an electrolyte. Example pouch batteries may include a circuit electrically coupled to the cathode and to the first portion of the aluminum layer, where the circuit is configured to cause a electric potential difference at the aluminum layer with respect to the anode, and a first electrical contact electrically coupled to the first portion of the aluminum layer. |
| US11094981B2 |
Pouch-shaped battery case for secondary batteries capable of discharging gas
Disclosed herein is a pouch-shaped battery case, including an electrode assembly, an outer coating layer, a metal barrier layer, and an inner adhesive layer sequentially stacked with one another, a first adhesive layer interposed between the outer coating layer and the metal barrier layer, a second adhesive layer interposed between the metal barrier layer and the inner adhesive layer, an upper case and a lower case sealed to one another by thermal fusion at outer edges thereof, such that the electrode assembly is mounted between the upper case and the lower case, and a gas discharge member providing gas communication between an inside and an outside of the pouch-shaped battery case, the gas discharge member being disposed within a fused portion of the pouch-shaped battery case that is formed by the inner adhesive layer of the upper case and the lower case being thermally fused to one another. |
| US11094980B2 |
Molten air rechargeable batteries
The present disclosure relates to rechargeable electrochemical battery cells (molten air batteries). The cells use air and a molten electrolyte, are quasi-reversible (rechargeable) and have the capacity for multiple electrons stored per molecule and have high intrinsic electric energy storage capacities. The present disclosure also relates to the use of such in a range of electronic, transportation and power generation devices, such as greenhouse gas reduction applications, electric car batteries and increased capacity energy storage systems for the electric grid. |
| US11094977B2 |
Battery thermal management system with passive battery pack cooling
According to one embodiment, a battery module includes an output connector, several battery cells that are coupled to the output connector and are at least partially submerged within a liquid coolant. The battery cells are configured to provide battery energy to a load via the output connector and are configured to draw power from an external power supply to charge the battery cells via the output connector. While the battery cells provide the battery energy or draw power, the battery cells generate heat that is transferred into the liquid coolant, thereby causing at least some of the liquid coolant to turn into vapor extracting the heat. The battery module also includes a condenser that is positioned above the battery cells and is configured to condense the vapor back into liquid coolant. |
| US11094973B2 |
Embedded sensors for in-situ cell monitoring of batteries
The disclosed principles provide for techniques for the 3D fabrication of sensing systems that are embedded inside battery cells and provide cell parameter data for a comprehensive and an robust battery management system. The disclosed principles provide for online and real-time monitoring of battery state-of-health down to the individual cell level of each battery using embedded sensors on one or more of the internal layers of a cell, such as the dielectric separators found in such battery cells. The implementation of the disclosed principles in individual battery cells therefore provides an increased likelihood to mitigate catastrophic failures in batteries. In addition, the disclosed fabrication processes for printing sensors directly on one or more of the components or layers within each individual battery cell, significantly reduce manufacturing steps required by conventional battery management systems. The disclosed principles also provided for a unique silica-based ink for use in the 3D printing of such embedded cell sensing components. |
| US11094972B2 |
Battery pack and manufacturing method therefor
A battery pack and a method for manufacturing the same, and more particularly, to a battery pack includes a top cap having a hook protrusion for protecting a PCB connected to a pouch-type battery cell and a method for manufacturing the same. |
| US11094971B2 |
Method and system for battery binding
A method for battery binding that is to be implemented by a service end electronic device includes obtaining a carrier identifier corresponding to a carrier device. The method further includes sending the carrier identifier to a battery device via near-field communication for storage in the battery device. |
| US11094970B2 |
Cooling for battery-integrated power electronics system
Method for providing cooling of a power electronics system which is integrated in a battery module, in which method the battery module has a battery housing, containing a large number of energy storage units and the power electronics system which is integrated adjacent thereto and includes a printed circuit board which is populated with power semiconductor switches, and a thermally conductive element which creates thermal contact between the respective energy storage units and the power electronics system. Cooling of the power electronics system is achieved by the thermally conductive element which renders possible transfer of thermal energy from the power electronics system to the energy storage units. At least one side of the battery housing is coupled to a cooling system. A surface area of the thermally conductive element is connected to a respective energy storage unit and is contacted by way of a respective curved portion. |
| US11094969B2 |
Battery pack and data transmission method between the battery pack and electrical device
A battery pack includes a housing, a battery cell group accommodated in the housing, a plurality of battery pack connection terminals coupled to the connection terminals of an electrical device, including a battery pack positive power terminal electrically connected to a positive pole of the battery cell group, a battery pack negative power terminal electrically connected to a negative pole of the battery cell group, a first battery pack terminal to transmit a first type of data, and a second battery pack terminal to transmit a second type of data. Also, a data transmission method between the battery pack and the electrical device enables data collection for data analysis while ensuring normal operation of the battery pack and the electrical device. |
| US11094967B2 |
Integrated system and method for desulfating and communicating the condition of a battery
An integrated system for desulfating and communicating a condition of a battery includes a desulfator that can be connected to the battery to sense one or more of a voltage across a positive terminal and a negative terminal of the battery, a current of the battery, and a temperature of the battery; the desulfator further including a source of desulfation energy that can be connected to the battery for delivering pulsation energy at predetermined frequencies and durations; and a system control for actuating the source of desulfation energy, and connected to receive data indicative of a real-time condition of the battery from the sensed one or more of the voltage across the positive and the negative terminals of the battery, the current of the battery, and the temperature of the battery, and transmit the data indicative of the real-time condition of the battery. |
| US11094965B2 |
Non-aqueous electrolytic solution for lithium ion secondary cell
Provided is a non-aqueous electrolytic solution for a lithium ion secondary cell that can reduce the initial resistance of the lithium ion secondary cell and can suppress the increase in resistance when the lithium ion secondary cell is allowed to stand at high temperature. The non-aqueous electrolytic solution for a lithium ion secondary cell disclosed herein includes a light metal salt represented by the following formula (I) and a silyl sulfate compound represented by the following formula (II). The content of the light metal salt in the non-aqueous electrolytic solution for a lithium ion secondary cell is 0.1% by mass or more and 1.5% by mass or less. The content of the silyl sulfate compound in the non-aqueous electrolytic solution for a lithium ion secondary cell is 0.1% by mass or more and 5.0% by mass or less (each symbol in the formulas is as defined in the specification). |
| US11094962B2 |
Method for controlling a regeneration process of a lithium-ion battery cell that comprises an anode, a cathode and a regeneration electrode
The present invention relates to a method for controlling a regeneration procedure of a lithium battery cell (1) which comprises an anode (2), a cathode (3) and the regeneration electrode (4). The method comprises: detecting a current availability of cyclable lithium in the anode (2); detecting a current availability of cyclable lithium in the cathode (3); passing a first current (I1) between the anode (2) and the regeneration electrode (4) until the actual availability of cyclable lithium in the anode (2) corresponds to a targeted availability of cyclable lithium in the anode (2); and passing a second current (I2) between the cathode (3) and the regeneration electrode (4) until the current availability of cyclable lithium in the cathode (3) corresponds to a targeted availability of cyclable lithium in the cathode (3). |
| US11094960B2 |
Secondary battery and manufacturing method thereof
A secondary battery having improved safety and a manufacturing method thereof, which can suppress a voltage drop, heat generation, and/or ignition due to a minute short between a positive electrode plate and a negative electrode plate by preventing or substantially preventing an electrode assembly from moving within a laminate exterior case due to drop impact and/or collision are provided. A secondary battery includes: an electrode assembly including a first electrode plate, a second electrode plate, and a separator between the first electrode plate and the second electrode plate; a pouch exterior case including a planar long side region and a short side region to surround the electrode assembly; and adhesives in a dot array configuration at an outermost portion of the electrode assembly facing the planar long side region of the pouch exterior case. |
| US11094959B2 |
Method of manufacturing secondary battery
A method of manufacturing a secondary battery is provided. According to the manufacturing method, laser light includes first peak light applied to a first irradiation position located on a cover body, second peak light applied to a second irradiation position located between the first irradiation position and a connecting surface, and third peak light applied to the connecting surface. The first peak light is higher in intensity than the second peak light and the third peak light. The third peak light is higher in intensity than the second peak light. |
| US11094957B2 |
Flow battery
A flow battery includes a first liquid containing a first electrode mediator, a first electrode, a first active material, and a first circulator that circulates the first liquid between the first electrode and the first active material. The first electrode mediator includes at least one benzene derivative that is at least one selected from the group consisting of 1,4-di-tert-butyl-2,5-dimethoxybenzene, 1,4-dichloro-2,5-dimethoxybenzene, 1,4-difluoro-2,5-dimethoxybenzene, and 1,4-dibromo-2,5-dimethoxybenzene. |
| US11094954B2 |
Electrode, membrane electrode assembly, electrochemical cell, stack, fuel cell, vehicle and flying object
An electrode of an embodiment includes a catalyst layer having pores. A mode diameter of the pores is 10 μm or more and 100 μm or less. The catalyst layer may have a thickness of 0.05 μm or more and 3.0 μm or less. A value of the mode diameter of the pores may three times or more a value of a thickness of the catalyst layer. |
| US11094952B2 |
Carbon dioxide removal from anode exhaust of a fuel cell by cooling/condensation
A system for removing carbon dioxide from anode exhaust gas that has been compressed to form pressurized anode exhaust vapor includes a feed/effluent heat exchanger configured to cool the anode exhaust vapor to a first predetermined temperature and partially condense carbon dioxide in the anode exhaust vapor; a first vapor-liquid separator configured to receive an output of the feed/effluent heat exchanger and separate liquid carbon dioxide from uncondensed anode exhaust vapor; a feed/refrigerant heat exchanger configured to receive the uncondensed anode exhaust vapor from the first vapor-liquid separator, cool the uncondensed anode exhaust vapor to a second predetermined temperature, and condense carbon dioxide in the uncondensed anode exhaust vapor; a second vapor-liquid separator configured to receive an output of the feed/refrigerant heat exchanger and separate liquid carbon dioxide to form hydrogen rich, uncondensed anode exhaust vapor. |
| US11094951B2 |
Multiple injection fuel cell
Fuel cell batteries are provided, and in particular hydrogen fuel cell batteries composed of at least one stack of cells. The battery is divided into at least two groups of cells able to be supplied with hydrogen separately. In a first phase, only the first group of cells and not the second is supplied; unconsumed hydrogen may however flow between the two groups via at least one evacuation manifold connected to the cells of the two groups. In a second phase, the supply to the two groups is reversed, unconsumed hydrogen still being able to flow between the two groups via the evacuation manifold. In a third phase, after a series of alternations of the two first phases, the two groups are first simultaneously supplied, then a purge valve of the evacuation manifold is opened then closed. |
| US11094945B2 |
Thermal battery electrolyte materials
An electrolyte composition can be capable of becoming molten when heated sufficiently. The electrolyte can include at least one lithium halide salt; and at least one lithium non-halide salt combined with the at least one lithium halide salt so as to form an electrolyte composition capable of becoming molten when above a melting point about 350° C. A lithium halide salt includes a halide selected from F and Cl. A first lithium non-halide salt can be selected from the group consisting of LiVO3, Li2SO4, LiNO3, and Li2MoO4. A thermal battery can include the electrolyte composition, such as in the cathode, anode, and/or separator region therebetween. The battery can discharge electricity by having the electrolyte composition at a temperature so as to be a molten electrolyte. |
| US11094938B2 |
Aqueous secondary battery
The object of the present invention is to provide an electric power storage device using an aqueous electrolytic solution that is safe even if the device is damaged while being used and the electrolytic solution leaks out from the battery housing. Specifically, the object of the present invention is to provide a secondary battery having both excellent safety and excellent cycle characteristics. The present invention is an aqueous secondary battery, wherein at least either of the positive electrode or the negative electrode comprises a compound (I) having a naphthalenediimide structure or a perylenediimide structure as an active material. |
| US11094937B2 |
Negative electrode and secondary battery including the same
The present invention relates to a negative electrode and a secondary battery including the same, and particularly, to a negative electrode which includes a current collector; a first active material layer disposed on the current collector and including at least one concave portion exposing a portion of the current collector; a stress-relaxing portion disposed in the concave portion; and a second active material layer disposed on the first active material layer and the stress-relaxing portion and separated from the current collector, and a secondary battery including the same. |
| US11094933B2 |
Polysiloxane binders
Electrodes for rechargeable batteries that include silicon and a binder are provided. Binders for use with silicon electrodes are provided, including polysiloxane binders that can be prepared prior to preparation of the electrode, or provided as monomers to be cure-polymerized at the time of the curing of the electrode. |
| US11094929B2 |
Energy storage device, an electrode for an energy storage device, and a method of fabricating the electrode
An electrode for an energy storage device and a method of fabricating such electrode. The electrode includes a plurality of layers of active material defining a layer material structure; and an interlayer material disposed between each adjacent pairs of layer of the active material. The interlayer material is arranged to facilitate a transportation of ions along and/or across the plurality of layers of active material during a charging or a discharging operation of the energy storage device. |
| US11094928B2 |
Wound-type cell and electrochemical device
A wound-type cell and an electrochemical device are provided. The wound-type cell includes a negative electrode. The negative electrode includes a negative electrode current collector and a negative electrode active material layer. The negative electrode is composed of a double-sided coated area of the negative electrode active material layer, where surfaces of both sides of the negative electrode current collector are coated with the negative electrode active material layer, and an uncoated area where surfaces of the negative electrode current collector are not coated with the negative electrode active material layer. |
| US11094921B2 |
Electrode for electrochemical device and method for manufacturing the same
The present disclosure relates to an electrode for an electrochemical device and a method for manufacturing the same. More particularly, the present disclosure relates to an electrode having a small difference in porosity along the thickness direction of the electrode, and a method for manufacturing the same. |
| US11094916B2 |
Display device and method for manufacturing the same
A display device includes a display module and an anti-reflection member. The display module includes a display panel having a light emitting element and a sensing layer disposed on the display panel to sense touch. The anti-reflection member is disposed on the display module to reduce reflectance of light that is incident from the outside. One side of the display module has a first shape that gradually decreases in thickness outward, and one side of the anti-reflection member, which corresponds to the one side of the display module, has a second shape that gradually decreases in thickness outward. |
| US11094914B2 |
Display panel and manufacturing method thereof, display device
A display panel has a first non-display area between an opening area and a display area. The display area surrounds the first non-display area. The opening area penetrates the display panel. The display panel includes a substrate, a first functional layer, and a light-emitting functional layer. The first functional layer has a protruding portion at a warped position and has a first opening penetrating the first functional layer at the warped position. The first opening extends into the protruding portion to form a cavity having bottom and side surfaces. An included angle θ formed between the bottom surface and at least a part of the side surface satisfies 0<θ≤90°. A light-emitting functional layer located at a side of first functional layer away from substrate includes a common layer in first non-displaying and display areas and is split at protruding portion. |
| US11094912B2 |
Flexible display apparatus
A flexible display apparatus includes a substrate, a thin film encapsulation layer, a plurality of spacers, and at least one layer of a blocking dam in the non-display region. The substrate includes a display region having a plurality of pixels and a non-display region adjacent to the display region. The thin film encapsulation layer is over the substrate. The spacers are between the substrate and the thin film encapsulation layer and are arranged around a pixel region. A different arrangement of spacers are in a center region and an edge region of the display region. The different arrangement may correspond to at least one of a size and a number of the spacers. |
| US11094911B2 |
Organic light emitting diode display panel and packaging method thereof
Provided are an organic light emitting diode display panel and packaging method thereof. The organic light emitting diode display panel is provided with an adhesive layer on a passivation layer corresponding to a position of a sealant. When packaging the organic light emitting diode, the sealant on a cover plate is adhered corresponding to a position of the adhesive layer. The adhesive layer has a good bonding force with the sealant and also has a good bonding force with the passivation layer. Thus, water vapor does not easily enter the organic light emitting diode element, which will not reduce the performance of the organic light emitting diode element to improve a service life of organic light emitting diode element and to possess a good reliability performance. |
| US11094908B2 |
Lighting apparatus using organic light emitting diode
An organic light emitting diode comprises an anode; an organic layer disposed on the anode and including a plurality of phosphorescent light emitting layers; and a cathode disposed on the organic layer, wherein a phosphorescent light emitting layer having a highest degree of horizontal orientation of a dopant among the plurality of phosphorescent light emitting layers is disposed to be adjacent to the cathode, and wherein the anode includes a short reduction pattern which implements a narrow path. |
| US11094899B2 |
Method for manufacturing field effect transistor and method for manufacturing wireless communication device
Provided is a method for manufacturing a field-effect transistor, the method including the steps of: forming a gate electrode on the surface of a substrate; forming a gate insulating layer on the gate electrode; forming a conductive film containing a conductor and a photosensitive organic component by a coating method on the gate insulating layer; exposing the conductive film from the rear surface side of the substrate with the gate electrode as a mask; developing the exposed conductive film to form a source electrode and a drain electrode; and forming a semiconductor layer by a coating method between the source electrode and the drain electrode. This method makes it possible to provide an FET, a semiconductor device, and an RFID which can be prepared by a simple process, and which have a high mobility, and have a gate electrode and source/drain electrodes aligned with a high degree of accuracy. |
| US11094897B2 |
Flexible display device
Disclosed is a flexible display device including: a housing comprising an accommodating chamber, a first opening is formed at one end of accommodating chamber; a flexible display screen accommodated in the accommodating chamber, the flexible display screen includes a substrate, a first infrared receiving circuit formed on one side of the substrate, and an anode formed on a side of the first infrared receiving circuit away from the substrate; a hole through are formed on the anode, orthographic projections of the hole, onto the substrate cover an orthographic projection of the first infrared receiving circuit onto the substrate; an infrared transmitting circuit arranged in the first opening; a reel is arranged in the accommodating chamber; a control circuit signal-connected with the first infrared receiving circuit. |
| US11094894B2 |
Method for manufacturing a display motherboard
The present disclosure provides a display motherboard and a method for manufacturing the same, a display substrate and a method for manufacturing the same, and a display device, and belongs to the field of display technology. In the method for manufacturing the display motherboard of the present disclosure, the display motherboard includes a plurality of display substrate areas each including a sub display area and a sub bending area; and the method for manufacturing the display motherboard includes: forming an adhesive force variable back film material having a first adhesive force on a flexible underlying substrate; removing the back film material in positions above the sub bending areas; and treating the remaining back film material to form a back film having a second adhesive force, wherein the second adhesive force is greater than the first adhesive force. |
| US11094892B2 |
Display device and method of manufacturing the same
A display device in which damage and carbonization of a display substrate is substantially minimized and a method of manufacturing the display device are provided. A display device includes: a substrate including a first area having a first thickness and a second area having a second thickness which is different from the first thickness; a display layer at the first area of the substrate; and a functional member on the display layer at the first area. The first area and the second area are arranged along a first direction, the substrate includes a protruding portion at the second area, and the protruding portion includes a side portion having an inclination of about 5 degrees or more with respect to the first direction toward a second direction which intersects the first direction. |
| US11094891B2 |
Organic electroluminescent materials and devices
A dual host system for OLEDs that contains hole-transporting indolocarbazole and electron-transporting indolocarbazole exhibiting superior performance in the OLEDs is disclosed. |
| US11094888B2 |
Organic electroluminescent device using aryl amine derivative containing heterocycle
An organic electroluminescent device including: an anode, a cathode, an emitting layer formed of an organic compound and interposed between the cathode and the anode, and two or more layers provided in a hole-injecting/hole-transporting region between the anode and the emitting layer; of the layers which are provided in the hole-injecting/hole-transporting region, a layer which is in contact with the emitting layer containing a compound represented by the formula (1); and of the layers which are provided in the hole-injecting/hole-transporting region, a layer which is interposed between the anode and the layer which is in contact with the emitting layer containing an amine derivative represented by the formula (2). |
| US11094887B2 |
Fluorene-based compound, organic light-emitting device using same and method for preparing same
The present specification relates to a fluorene-based compound of Formula 1, a coating composition comprising the fluorene-based compound of Formula 1, an organic light emitting device using the same, and a manufacturing method thereof. |
| US11094884B2 |
Rapid metal oxide layer-specific photonic treatment using UV LED for fabrication of flexible perovskite structures
Methods of forming a perovskite-containing film comprising depositing one or more metal oxide layers onto a substrate; and irradiating each metal oxide layer with a UV LED light source after deposition to sinter and/or anneal a target metal oxide in the one or more metal oxide layers without damaging the underlying substrate or perovskite material. The LED light source can be selected to emit a narrow spectral width of pulsed radiation. The radiation emitted can consist essentially of wavelengths within 20 nm of the wavelength of maximum absorbance (λmax) of the target metal oxide, that is, wavelength from UV LED can be λmax±20 nm, to achieve layer-specific annealing and sintering of metal oxide charge transport layer. The target metal oxide can include tin oxide in the electron transport layer or nickel oxide in the hole transport layer. Perovskite-containing films formed from the methods described herein are also disclosed. |
| US11094880B2 |
Resistive random access memory structure and method for manufacturing the same
A resistive random access memory structure includes a bottom electrode; a variable resistance layer disposed on the bottom electrode; a top electrode disposed on the variable resistance layer; a protection layer surrounding the variable resistance layer, wherein a top surface of the protection layer and a top surface of the top electrode are coplanar; and an upper interconnect structure disposed on the top electrode, wherein the upper interconnect structure is electrically connected to the top electrode and directly contacts a sidewall of the protection layer. |
| US11094878B2 |
Short circuit reduction in magnetic tunnel junctions
A spin-transfer torque magneto-resistive random access memory (STT-MRAM) device is provided. The STT-MRAM device includes a substrate, a dielectric layer and a magnetic tunnel junction (MTJ) stack. The substrate includes a conductor and a landing pad. The MTJ stack includes a reference layer element, a free layer assembly and a barrier layer element. The reference layer element is lined with redeposited metal and is disposed on the landing pad within the dielectric layer. The free layer assembly includes a free layer element, a hard mask layer element disposed on the free layer element, redeposited metal lining sidewalls of the free and hard mask layer elements and dielectric material lining the redeposited metal. The barrier layer element is interposed between and has a same width as the reference layer element and the free layer assembly. |
| US11094874B2 |
Piezoelectric vibration device
A piezoelectric vibration device is provided that includes a piezoelectric transformer, a flexible board and a case. The flexible board includes an element-mounting terminal connected to an outer electrode of the piezoelectric transformer, and an external connection terminal connected to a wiring board. The case has a securing member that secures the case to the wiring board and a ceiling. When the piezoelectric vibration device is mounted on the wiring board, the securing member defines a space between the ceiling and the wiring board to accommodate the piezoelectric transformer and the flexible board. Moreover, the piezoelectric transformer is suspended to the ceiling of the case by a holding member. This configuration provides a piezoelectric vibration device with which degradation of characteristics due to causes such as displacement of the piezoelectric vibrator or fluctuations in the pressing force applied by lead terminals is minimized. |
| US11094871B2 |
Light-emitting device, light-emitting module and method for manufacturing the same
A light-emitting module 1 includes a light-emitting element, a mounting board, a module board, an anode connection member, a cathode connection member, and a metal ribbon. The light-emitting element includes an anode electrode and a cathode electrode. The mounting board includes an anode pad, a cathode pad and a heat radiating pads, each of which is electrically independent. The anode electrode and the anode pad are connected. The cathode electrode and the cathode pad are connected. The module board includes an anode terminal, a cathode terminal and a heat sink. The anode connection member connects the anode pad and the anode terminal. The cathode connection member connects the cathode pad and the cathode terminal. The metal ribbon connects the heat radiating pads and the heat sink. |
| US11094865B2 |
Semiconductor device and semiconductor device package
A semiconductor device according to the embodiment may include a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer; a first bonding pad disposed on the light emitting structure and electrically connected to the first conductivity type semiconductor layer; a second bonding pad disposed on the light emitting structure and spaced apart from the first bonding pad, and electrically connected to the second conductivity type semiconductor layer; and a reflective layer disposed on the light emitting structure and disposed between the first bonding pad and the second bonding pad. According to the semiconductor device of the embodiment, each of the first bonding pad and the second bonding pad includes a porous metal layer having a plurality of pores and a bonding alloy layer disposed on the porous metal layer. |
| US11094861B2 |
Display device
Provided is a display device. The display device includes a substrate having a sub-pixel area. In some examples, the substrate may have or define a plurality of sub-pixel areas. A light-emitting diode (LED) and a thin-film transistor for driving the LED are disposed in the sub-pixel area. An extended light path layer is disposed on the substrate and is configured to surround the sub-pixel area. Accordingly, it is possible so as to improve the luminous efficiency of the display device. |
| US11094860B2 |
Wafer-level solid state transducer packaging transducers including separators and associated systems and methods
Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein. |
| US11094853B2 |
Passive micro light-emitting diode matrix device with uniform luminance
A passive micro light-emitting diode matrix device with uniform luminance includes a micro light-emitting diode matrix including a plurality of micro light-emitting matrices, each of which includes a first layer, a plurality of light-emitting layers disposed on the first layer, a plurality of second layers disposed on the light-emitting layers, respectively, a plurality of first inner electrode layers disposed on the second layers, respectively, and a second inner electrode layer which is disposed on the first layer, and which includes a first portion and a second portion having a plurality of through holes to accommodate said light-emitting layers, respectively. |
| US11094850B2 |
Light emitting device and lighting apparatus having enhanced optical and electrical characteristics by diffusion barrier layer
A light emitting device includes a substrate; a light emitting structure disposed on the substrate; a first insulation layer disposed on the light emitting structure; a second insulation layer disposed on the first insulation layer; a first electrode and a second electrode electrically connected to the light emitting structure; a first pad electrically connected to the first electrode; and a second pad electrically connected to the second electrode. |
| US11094846B1 |
Monolithic nanocolumn structures
The array of gallium-nitride (GaN) nanocolumns have quantum wells in a polar c-plane or in a semi-polar plane to emit light directed to ends of the nanocolumns and an interstitial filler material with light emitted in the nanocolumns being guided to exit from an end of the nanocolumns. |
| US11094834B2 |
Junction field effect transistor (JFET) structure and methods to form same
A junction field effect transistor (JFET) structure includes a doped polysilicon gate over a channel region of a semiconductor layer. The doped polysilicon gate has a first doping type. A raised epitaxial source is on the source region of the semiconductor layer and adjacent a first sidewall of the doped polysilicon gate, and has a second doping type opposite the first doping type. A raised epitaxial drain is on the drain region of the semiconductor layer and adjacent a second sidewall of the doped polysilicon gate, and has the second doping type. A doped semiconductor region is within the channel region of the semiconductor layer and extending from the source region to the drain region, and a non-conductive portion of the semiconductor layer is within the channel region to separate the doped semiconductor region from the doped polysilicon gate. |
| US11094832B2 |
Semiconductor devices
A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region. |
| US11094830B2 |
Semiconductor device
A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer. |
| US11094815B2 |
Semiconductor device and power conversion apparatus
An object of the present invention is to provide a highly reliable semiconductor device by preventing precipitation of an oxide to prevent peeling of a resin layer. The semiconductor device includes: a resin layer provided so that at least a part of the resin layer extends on a front surface of a semiconductor layer on an outer peripheral side with respect to an outer peripheral end of a field insulating film; and a floating well region spaced apart from a termination well region in a surface layer of the semiconductor layer, the floating well region formed to be in contact with an outer peripheral end of the field insulating film to extend to the outer peripheral side with respect to the outer peripheral end of the field insulating film. |
| US11094813B2 |
Compound semiconductor device, method of manufacturing compound semiconductor device, and amplifier
A compound semiconductor device includes a semiconductor multilayer structure including an electron transit layer and an electron supply layer of a compound semiconductor; a source electrode, a gate electrode, and a drain electrode that are disposed above the semiconductor multilayer structure and are aligned in a first direction; a first insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the drain electrode, and has a tensile stress; a second insulating film that is formed on the semiconductor multilayer structure between the gate electrode and the source electrode, and has a compressive stress; and a protective film that is formed between the first insulating film and the semiconductor multilayer structure, and between the second insulating film and the semiconductor multilayer structure. |
| US11094811B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts. |
| US11094809B2 |
Power module and reverse-conducting IGBT
A power module which includes a power semiconductor module chip, a driver chip and a charge storage element. The power semiconductor module chip is configured by forming an IGBT having a trench gate structure including a dummy trench gate, and a freewheeling diode for returning excess carrier of the emitter of the IGBT to the collector of the IGBT, in the same chip. The drive chip is used for driving the IGBT on/off. The power module is configured by packaging the power semiconductor module chip and the drive chip. The charge storage element that is connected between the gate and emitter of a dummy IGBT which can be pseudo-formed in order that the dummy trench gate be used in screening examinations. |
| US11094805B2 |
Lateral heterojunction bipolar transistors with asymmetric junctions
Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness. |
| US11094801B2 |
Oxide isolated fin-type field-effect transistors
According to an embodiment of the present invention, a semiconductor structure includes a semiconductor substrate and a plurality of fins located on the semiconductor substrate. The plurality of fins each independently includes a bottom fin portion, a top fin portion layer, and an isolated oxide layer located in between the bottom fin portion and the top fin portion layer in the y-direction parallel to the height of the plurality of fins. The isolated oxide layer includes a mixed oxide region located in between oxidized regions in an x-direction perpendicular to the height of the plurality of fins. |
| US11094798B2 |
Vertical FET with symmetric junctions
An embodiment of the invention may include a method of forming a semiconductor structure, and the resulting semiconductor structure. The method may include removing a gate region from a layered stack located on a source/drain layer. The layered stack includes a first spacer located on the source drain layer, a dummy layer located on the first spacer, and a second spacer located on the dummy layer. The method may include forming a channel material above the source/drain layer in the gate region. The method may include forming a top source/drain on the channel material. The method may include forming a hardmask surrounding the top source/drain. The method may include removing a portion of the layered stack that is not beneath the hardmask. |
| US11094794B2 |
Air spacer structures
The present disclosure generally relates to semiconductor structures and, more particularly, to air spacer structures and methods of manufacture. The structure includes: a plurality of gate structures comprising active regions; contacts extending to the active regions; a plurality of anchor structures between the active regions; and air spacer structures adjacent to the contacts. |
| US11094789B2 |
Thin film transistor and method for manufacturing the same, array substrate, and display device
Embodiments of the present disclosure disclose a thin film transistor, a method for manufacturing a thin film transistor, an array substrate, and a display device. The thin film transistor includes a source electrode and a drain electrode, each of the source electrode and the drain electrode including a metal substrate and a conductive layer covering the metal substrate. An adhesion between the conductive layer and a photoresist material is larger than an adhesion between the metal substrate and the photoresist material. The metal substrate and the conductive layer are both formed on a base substrate, an orthographic projection of the conductive layer on the base substrate covers an orthographic projection of the metal substrate on the base substrate, and. an area of the orthographic projection of the conductive layer on the base substrate is larger than an area of the orthographic projection of the metal substrate on the base substrate. |
| US11094786B2 |
Semiconductor device
A semiconductor device of embodiments includes a silicon carbide layer including an element region and a termination region around the element region, the termination region having first straight-line portions extending in a first direction, second straight-line portions extending in a second direction, and corner portions between the first straight-line portions and the second straight-line portions, the termination region including a second-conductivity-type second silicon carbide region having a dot-line shape with first dot portions and first space portions surrounding the element region, an occupation ratio of the first dot portions is larger in the corner portions than in the first straight-line portions, and a second-conductivity-type third silicon carbide region having a dot-line shape with second dot portions and second space portions surrounding the second silicon carbide region, an occupation ratio of the second dot portions is lager in the corner portions than in the first straight-line portions. |
| US11094783B2 |
Semiconductor device having a silicon oxide film with a gradual downward inclination and method of manufacturing semiconductor device
A semiconductor device includes: a diffusion layer of a second conductivity type provided on an upper layer portion of a semiconductor layer of a first conductivity type; a polysilicon added structure to be provided on the diffusion layer with a first silicon oxide film therebetween; a second silicon oxide film provided to have contact with an end surface of the polysilicon added structure, and having a gentle downward inclination from the end surface of the polysilicon added structure; and a third silicon oxide film provided on the diffusion layer with a predetermined distance from the end surface of the polysilicon added structure, and covered by the first silicon oxide film, wherein the first silicon oxide film is raised at a portion covering the third silicon oxide film, and constitutes a silicon oxide film with a gentle step-like surface layer formed of the portion raised and the second silicon oxide film. |
| US11094782B1 |
Gate-all-around integrated circuit structures having depopulated channel structures
Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons. |
| US11094781B2 |
Nanosheet structures having vertically oriented and horizontally stacked nanosheets
A nanosheet semiconductor structure and method for forming the same, where the nanosheet semiconductor structure includes a substrate and a nanosheet stack comprising vertically oriented nanosheets. A gate structure contacts and wraps around the vertically oriented nanosheets. A source layer and a drain layer are each disposed adjacent to the nanosheet stack. An inner spacer is disposed in contact with a bottom surface of the nanosheet stack. The method includes forming an alternating pattern of first spacers and second spacers on a semiconductor stack. The first spacers and one or more underlying portions of the semiconductor stack are removed thereby forming a plurality of trenches each adjacent to one or more of the second spacers. The plurality of trenches defines a plurality of vertically oriented nanosheets. A plurality of sacrificial spacers are formed each in contact with one or more vertically oriented nanosheets of the plurality of vertically oriented nanosheets. |
| US11094780B2 |
Lateral superjunction transistor device and method for producing thereof
A transistor arrangement and a method are disclosed. The transistor arrangement includes: a plurality of first semiconductor regions of a first doping type and a plurality of second semiconductor regions of a second doping type, the first semiconductor regions and the second semiconductor regions being arranged alternatingly in a vertical direction of a semiconductor body; a source region adjoining the plurality of first semiconductor regions; a drain region adjoining the plurality of second semiconductor regions and arranged spaced apart from the source region in a first lateral direction; and a plurality of gate regions each of which adjoins at least one of the plurality of second semiconductor regions and is arranged between the source region and the drain region. At least one of the first and semiconductor regions, but less than each of the first and second semiconductor regions has a doping dose that varies in the first lateral direction. |
| US11094778B2 |
Capacitor with high work function interface layer
A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer. |
| US11094775B2 |
Tiled electronic device having a plurality of display panels and a flexible substrate
A tiled electronic device includes a plurality of display panels, and at least one of the display panels includes a flexible substrate, a pixel, and two signal wires. The flexible substrate has a display portion and a bent portion connected to the display portion. The pixel is disposed on the display portion. The signal wires are disposed on the flexible substrate, and electrically connected to the pixel. Each of the signal wires has a first segment disposed on the display portion, and a second segment disposed on the bent portion. The two first sections have a first pitch, and the two second sections have a second pitch. The first pitch is different than the second pitch. |
| US11094771B2 |
Display device with first and second initialization lines
A display device includes a substrate including a pixel area and a peripheral area, a plurality of pixels disposed in the pixel area of the substrate, a first initialization line disposed in the peripheral area of the substrate, the first initialization line being configured to provide a first initialization voltage to the plurality of pixels, and a second initialization line disposed in the peripheral area of the substrate, the second initialization line being configured to provide a second initialization voltage to the plurality of pixels. At least a portion of the first initialization line may overlap with the second initialization line. |
| US11094768B2 |
Electroluminescence display capable of improving an aperture ratio
An electroluminescence display includes a plurality of sub-pixels, each of the plurality of sub-pixels including a light emission region, and a first circuit region and a second circuit region disposed on respective sides of the light emission region. Power supply lines are configured to supply a first power to at least one of the second circuit regions of the sub-pixels arranged at odd-numbered row and the first circuit regions of the sub-pixels arranged at an even-numbered row. A sensing line is configured to supply an initialization voltage or a sensing voltage to at least one of the first circuit regions of the sub-pixels arranged at the odd-numbered row and the second circuit regions of the sub-pixels arranged in the even-numbered row. |
| US11094763B2 |
Organic EL device with alternately lined source drain electrodes
This organic-EL display apparatus comprises: a substrate with a drive circuit comprising a thin-film transistor (TFT), a planarizing layer to cover the drive circuit, and an organic light-emitting element formed upon the surface of the planarizing layer facing the opposite direction from the drive circuit. The surface of the planarizing layer has an arithmetic average roughness of 50 nm or less. The TFT comprises a drain electrode, a source electrode, and a semiconductor layer that includes regions to be a channel of TFT and partially overlaps with the source and drain electrodes. Respective parts of a first conductor layer forming the drain electrode and a second conductor layer forming the source electrode are arranged in an alternating manner along a prescribed direction, and the region to be the channel is sandwiched between the part of the first conductor layer and the part of the second conductor layer. |
| US11094762B2 |
Display device and method for manufacturing the same
Disclosed is a display device. In accordance with the display device, before an organic stack of a light-emitting diode is formed, a sticker is attached to a substrate, while a camera hole-forming portion and a margin area around the same are present, to form the organic stack, and the sticker and components on top of the sticker, such as the organic stack, are removed, so that the edge of the organic stack can be aligned without any additional process using separate masks and the reliability of the display device can be improved due to the provision of the organic stack at a location spaced apart from the camera hole by the margin area. |
| US11094761B2 |
Organic light emitting display device and method of fabricating thereof
An organic light emitting display device and a method of fabricating thereof are discussed. The organic light emitting display device according to an example of the invention comprises a first substrate; a plurality of first bank layers arranged along a first direction and a second direction on the first substrate to define a plurality of pixels; a plurality of second bank layers disposed along the first direction on the first bank layers to divide columns of pixels having different colors; a plurality of third bank layers disposed along the second direction on the first bank layers; and an organic light emitting diode in each pixel, the organic light emitting diode including an organic light emitting layer, wherein the third bank layer is made of a same material as the second bank layer and the width of the third bank layer is smaller than that of the second bank layer. |
| US11094760B2 |
Method for forming light emitting element pattern and display device using the same
A method for forming a light emitting element pattern according to an embodiment of the inventive concept includes forming a pattern layer having an opening on a target material, forming a light emitting element pattern on the target material in correspondence to the opening, and removing the pattern layer. Here, the pattern layer includes a first pattern layer disposed on the target material, a second pattern layer disposed on the first pattern layer, and a third pattern layer disposed on the second pattern layer. The second pattern layer has an undercut portion recessed from edges of the third pattern layer. |
| US11094757B2 |
Display device
A display device including a first sensor part that includes a first trunk portion, a first branch portion connected to the first trunk portion and extending in a direction different from a first direction and a second direction, a second branch portion spaced apart from the first branch portion, and a bridge connecting the first branch portion to the second branch portion. A second sensor part includes a second trunk portion extending in the second direction, and a third branch portion disposed between the first branch portion and the second branch portion. |
| US11094751B2 |
Display panel, method for fabricating the same, and display device
The disclosure provides a display panel, a method for fabricating the same, and a display device. The display panel includes a plurality of pixel elements distributed in an array, each of which includes a plurality of sub-pixel elements, wherein there is a photon crystal film layer arranged on a light exit side of the pixel elements in the display panel, and the photon crystal film layer includes photon crystal areas corresponding to the respective sub-pixel elements in a one-to-one manner; and there are a plurality of micro-holes structures arranged uniformly in each photon crystal area, and apertures of the micro-hole structures in the respective photon crystal areas match colors of light to be displayed at the sub-pixel elements corresponding to the photon crystal areas. |
| US11094748B2 |
Pixel arrangement structure
A pixel arrangement structure is disclosed. The structure includes multiple first pixel rows and multiple second pixel rows arranged alternately. Wherein each of the first pixel rows includes multiple first sub-pixels and multiple second sub-pixels disposed alternately and at intervals, and each of the second pixel rows includes multiple third sub-pixels disposed at intervals. Wherein the first sub-pixel and the second sub-pixel adjacent to the third sub-pixel form a virtual triangle, the third sub-pixel is disposed in the virtual triangle formed by the first sub-pixel and the second sub-pixel adjacent to the third sub-pixel. Applying the pixel arrangement structure to an OLED display panel can improve the resolution, reduce the fabrication difficulty, increase the pixel area, and improve the brightness and life of the OLED display panel. |
| US11094746B2 |
Imaging device
An imaging device includes: pixels arranged one-dimensionally or two-dimensionally, each of the pixels including an electrode that is electrically connected to the other pixels, a charge capturing unit that is separated from the other pixels, and a photoelectric conversion layer that is located between the electrode and the charge capturing unit, the photoelectric conversion layer being continuous among the pixels. The photoelectric conversion layer contains semiconductor carbon nanotubes, and one of a first substance and a second substance, the first substance having an electron affinity larger than that of the semiconducting carbon nanotubes, the second substance having a ionization energy smaller than that of the semiconductor carbon nanotubes. |
| US11094745B2 |
Variable resistance memory device and method of fabricating the same
A variable resistanvce memory device may include a plurality of first conductive lines extending in a first direction, a plurality of second conductive lines extending in a second direction, a plurality of memory cells, each memory cell at a respective intersection, with respect to a top down view, between a corresponding one of the first conductive lines and a corresponding one of the second conductive lines, each memory cell comprising a variable resistance structure and a switching element sandwiched between a top electrode and a bottom electrode, and a first dielectric layer filling a space between the switching elements of the memory cells. A top surface of the first dielectric layer is disposed between bottom and top surfaces of the top electrodes of the memory cells. |
| US11094743B2 |
Magnetic memory device
According to one embodiment, a magnetic memory device includes a first memory cell which includes a first stacked structure including a magnetic layer, and a second memory cell which is provided on the first memory cell and includes a second stacked structure including a magnetic layer, wherein each of the first stacked structure and the second stacked structure has a structure in which a plurality of layers including a predetermined layer are stacked, and the predetermined layer included in the first stacked structure and the predetermined layer included in the second stacked structure have different thicknesses. |
| US11094742B2 |
Method for producing a photo-emitting and/or photo-receiving device with a metal optical separation grid
A method for producing a photo-emitting and/or photo-receiving device with a metal optical separation grid, comprising at least: producing at least one photo-emitting and/or photo-receiving component, wherein at least one first metal electrode of the photo-emitting and/or photo-receiving component covers side flanks of at least one semiconductor stack of the photo-emitting and/or photo-receiving component and extends to at least one emitting and/or receiving face of the photo-emitting and/or photo-receiving component; treating at least one face of the first metal electrode located at the emitting and/or receiving face, rendering wettable said face of the first metal electrode; producing of the metal optical separation grid on at least one support; fastening of the metal optical separation grid against said face of the first metal electrode by brazing; removing the support. |
| US11094738B2 |
Photoelectric detector, manufacturing method thereof, and detection device
The embodiments of the present disclosure provide a photoelectric detector, a method for manufacturing the photoelectric detector, and a detection device. The method for manufacturing the photoelectric detector includes: forming a thin film transistor array layer on a base substrate; forming an organic layer on a side of the thin film transistor array layer facing away from the base substrate; and patterning the organic layer to form a first via hole which enables a signal transmission layer in the thin film transistor array layer to be exposed; and depositing a photoelectric conversion device in the first via hole. |
| US11094737B2 |
Flat panel detector
A flat panel detector includes: a substrate, a gate line and a read signal line define a detection region, a detection unit includes a first photoelectric converter, a thin film transistor and a second photoelectric converter, the first photoelectric converter and the second photoelectric converter are on two side of the thin film transistor and connected with it; a gate electrode layer of the thin film transistor is connected with the gate line, and a source electrode or a drain electrode of the thin film transistor is connected with the read signal line; a gap region is between the second photoelectric converter and at least one selected from a group consisting of the gate line defining the detection unit, the read signal line defining the detection unit and the thin film transistor, and an orthographic projection of the first photoelectric converter on the substrate at least covers the gap region. |
| US11094726B2 |
Pixel and method of controlling the same
A global shutter pixel includes a first transistor and a first switch series-connected between a first node of application of a potential and an internal node of the pixel. A control terminal of the first transistor is coupled to a floating diffusion node of the pixel. At least two assemblies are coupled to the internal node, where each assembly is formed of a capacitor series-connected with a second switch coupling the capacitor to the internal node. A second transistor has a control terminal connected to the internal node and a first conduction terminal coupled to an output node of the pixel. The pixel operation is controlled to store an initialization voltage from the floating diffusion on one of the capacitors and a pixel integration voltage from the floating diffusion on another of the capacitors. |
| US11094724B2 |
Touch screen panel for sensing touch using TFT photodetectors integrated thereon
A touch screen panel using a thin film transistor (TFT) photodetector includes a touch panel including at least one unit pattern for sensing light reflected by a touch by using a TFT photodetector including an active layer formed of amorphous silicon or polycrystalline silicon on an amorphous transparent material, and a controller configured to scan the at least one unit pattern and read touch coordinates as a result of the scanning. |
| US11094721B2 |
Method for manufacturing array substrate including forming via holes having different widths using single patterning process
The present disclosure provides a method for manufacturing an array substrate, an array substrate, and a display device. The method for manufacturing the array substrate includes: forming a light-shielding layer and a buffer layer in sequence on a base substrate; forming an active layer on the buffer layer, and forming a first via hole in the active layer; forming an interlayer dielectric layer on the active layer; forming a second via hole in the interlayer dielectric layer at a position corresponding to the first via hole and a third via hole in the buffer layer at a position corresponding to the first via hole by a single patterning process; forming a source/drain electrode layer on the interlayer dielectric layer, in which the source/drain electrode layer is electrically connected to the light-shielding layer through the second via hole, the first via hole and the third via hole in sequence. |
| US11094719B2 |
Method of manufacturing display panel, display panel, and display device
A method of manufacturing a display panel, the display panel, and a display device are provided. The method includes forming a first via hole within a gate insulating layer and a dielectric layer of the display panel, forming an auxiliary electrode within the first via hole and on the dielectric layer, forming an inorganic insulating layer on the auxiliary electrode, and forming a cathode on the inorganic insulating layer. The cathode, the inorganic insulating layer, and the auxiliary electrode form a capacitance. The method maintains stability of a cathode voltage of the display panel, thereby improving uniformity of brightness of the display panel. |
| US11094713B2 |
Three-dimensional memory device with source contacts connected by an adhesion layer and methods for forming the same
A three-dimensional (3D) memory device includes a memory stack over a substrate. The memory stack includes interleaved conductor layers and insulating layers. The 3D memory device also includes channel structures extending vertically in the memory stack. The 3D memory device further includes a source structure extending in the memory stack. The source structure includes first and second source contacts separated by a support structure. The source structure also includes an adhesion layer. At least a portion of the adhesion layer is between the first and second source contacts and conductively connects the first and second source contacts. |
| US11094712B2 |
Three-dimensional memory device with support structures in slit structures and method for forming the same
Embodiments of structure and methods for forming a three-dimensional (3D) memory device are provided. In an example, a 3D memory device includes a stack structure and at least one source structure extending vertically and laterally and dividing the stack structure into a plurality of block regions. The stack structure may include a plurality of conductor layers and a plurality of insulating layers interleaved over a substrate. The at least one source structure includes at least one support structure extending along the vertical direction to the substrate, the at least one support structure being in contact with at least a sidewall of the respective source structure. |
| US11094709B2 |
Method of manufacturing semiconductor device
A hole is formed to pass through preliminary first mold layers and preliminary second mold layers to form first mold layers and mold layers respectively that are alternately stacked in a vertical direction, perpendicular to a lower structure, on the lower structure. The first mold layers are partially etched along a side surface of the hole to form recess regions and recessed first mold layers. Third mold layers are formed in the recess regions to form interlayer insulation layers so that each of the interlayer insulation layers includes a corresponding third mold layer and a corresponding recessed first mold layer that are positioned at the same level in the vertical direction. A first dielectric layer is formed in the hole to cover the third mold layers and the second mold layers stacked on each other. Information storage patterns are formed on the first dielectric layer. |
| US11094707B2 |
NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells. |
| US11094704B2 |
Method of forming a three-dimensional memory device and a driver circuit on opposite sides of a substrate
A method of forming a device structure includes forming a memory-level structure including a three-dimensional memory device over a front side surface of a semiconductor substrate, forming memory-side dielectric material layers over the memory-level structure, bonding a handle substrate to the memory-side dielectric material layers, thinning the semiconductor substrate while the handle substrate is attached to the memory-side dielectric material layers, forming a driver circuit including field effect transistors on a backside semiconductor surface of the semiconductor substrate after thinning the semiconductor substrate, and removing the handle substrate from the memory-side dielectric material layers. |
| US11094702B1 |
One-time programmable memory device including anti-fuse element and manufacturing method thereof
A memory device includes a transistor, an anti-fuse element, a gate via, and a bit line. The transistor includes two source/drain regions. The anti-fuse element is connected to one of the source/drain regions of the transistor. The anti-fuse element includes a channel and a gate structure above the channel. The gate via is above the gate structure of the anti-fuse element. A lateral distance between a center of the gate via and a sidewall of the channel is less than a width of the gate via. The bit line is connected to another of the source/drain regions of the transistor. |
| US11094699B1 |
Apparatuses including stacked horizontal capacitor structures and related methods, memory devices, and electronic systems
An apparatus includes fin structures comprising individual levels of a conductive material having elongated portions extending in a first horizontal direction, first conductive lines extending in a second horizontal direction transverse to the first horizontal direction, and second conductive lines extending in a vertical direction transverse to each of the first horizontal direction and the second horizontal direction. At least portions of the first conductive lines are aligned vertically. The apparatus also includes horizontal capacitor structures comprising the conductive material of the fin structures and access devices proximate intersections of the first conductive lines and the second conductive lines. The access devices comprise the conductive material of the fin structures. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed. |
| US11094692B2 |
Semiconductor structure having active regions with different dopant concentrations
A semiconductor structure includes a first semiconductor substrate, a second semiconductor substrate, a depletion layer, an isolation structure, a first gate structure, and a second gate structure. The first and second semiconductor substrates respectively have a first active region and a second active region overlapping the first active region. The depletion layer is disposed between the first active region and the second active region. The isolation structure surrounds the first and second active regions. The first gate structure is disposed in the second active region. The second gate structure is disposed in the second active region. The second active region has a portion between the first gate structure and the second gate structure. |
| US11094691B2 |
Semiconductor device
A semiconductor device includes a semiconductor substrate, and the semiconductor substrate is divided into an IGBT region, a diode region, and a MOSFET region. A drift layer of n−-type is provided in the semiconductor substrate. The drift layer is shared among the IGBT region, the diode region, and the MOSFET region. In the semiconductor substrate, the diode region is always disposed between the IGBT region and the MOSFET region to cause the IGBT region and the MOSFET region to be separated from each other without being adjacent to each other. |
| US11094686B2 |
Integrated circuit including multi-height standard cell and method of designing the same
An integrated circuit includes a semiconductor substrate, first through third power rails, and first through fourth clock gate lines. The first power rail through third power rails are formed above the semiconductor substrate, and extend in a first direction and arranged sequentially in a second direction perpendicular to the first direction. The first through fourth clock gate lines are formed above the semiconductor substrate, and extend in the second direction to pass through a first region between the first power rail and the second power rail and a second region between the second power rail and the third power rail. The first clock gate line and the second clock gate line are arranged to be adjacent to each other in the first direction, and the third clock gate line and the fourth clock gate line are arranged to be adjacent to each other in the first direction. |
| US11094685B2 |
Static random access memory device
A semiconductor device including a static random access memory (SRAM) device includes a first SRAM array including a first plurality of bit cells arranged in a matrix; a second SRAM array including a second plurality of bit cells arranged in a matrix; and a plurality of abutting dummy cells disposed between the first SRAM array and the second SRAM array. Each of the plurality of abutting dummy cells includes a plurality of dummy gate electrode layers and a plurality of dummy contacts. The semiconductor device further includes a first-type well continuously extending from the first SRAM array to the second SRAM array. The first-type well is in direct contact with portions of the plurality of dummy contacts. |
| US11094682B2 |
Package structure and method of fabricating the same
A package structure includes a package component, a stacked die package, a plurality of optical fibers and a heat spreading structure. The stacked die package is disposed on and electrically connected to the package component. The stacked die package includes a first semiconductor die and a plurality of second semiconductor dies. The first semiconductor die has a plurality of first bonding elements. The second semiconductor dies are disposed on the first semiconductor die and have a plurality of second bonding elements, wherein the plurality of first bonding elements and the plurality of second bonding elements are facing one another and bonded together through hybrid bonding. The plurality of optical fibers is attached to the plurality of second semiconductor dies of the stacked die package. The heat spreading structure is disposed on the package component and surrounding the stacked die package. |
| US11094681B2 |
Photocoupler and packaging member thereof
A photocoupler of an embodiment includes a packaging member, a first and a second MOSFET, a semiconductor light receiving element, a semiconductor light emitting element, a first wiring part, and a sealing resin layer. The input terminal includes a first and a second lead. The output terminal includes a third and a fourth lead. The first conductive region includes a signal input part and a bend part. The fourth conductive region includes a signal input part and a bend part. The semiconductor light receiving element is joined to the first and second MOSFETs astride a gap part. The semiconductor light emitting element is joined onto a light receiving region. The first wiring part connects the source electrode of the first MOSFET and the source electrode of the second MOSFET. |
| US11094677B2 |
Micro LED display device and manufacturing method thereof
A micro LED display device including a display substrate, a plurality of conductive pad pairs and a plurality of micro light emitting elements is provided. The display substrate has a first arranging area, a splicing area connected to the first arranging area, and a second arranging area connected to the splicing area, wherein the splicing area is located between the first arranging area and the second arranging area. The conductive pad pairs are disposed on the display substrate in an array with the same pitch. The micro light emitting elements are disposed on the display substrate and are electrically bonded to the conductive pad pairs. A manufacturing method of the micro LED display device is also provided. |
| US11094674B2 |
Memory scaling semiconductor device
A semiconductor device is disclosed including a memory module formed from a pair of semiconductor dies mounted face to face to each other at the wafer level, mechanically resulting in the die pair having a minimum warpage. An electronic component may be bonded to an exposed surface of one of the semiconductor dies. |
| US11094669B2 |
Wafer level molded PPGA (pad post grid array) for low cost package
A method to fabricate a land grid array wafer level chip scale package is described. A silicon die is provided. A dielectric layer is deposited on the silicon die. An opening is etched through the dielectric layer to a metal pad on the silicon die. At least one redistribution layer is formed over the dielectric layer and contacting the metal pad. At least one copper post is formed on the at least one redistribution layer and forms a land grid array. The wafer is sawed partially through on scribe lines to form cuts exposing sides of the silicon die. Thereafter, a molding compound is applied over the at least one redistribution layer and in the cuts wherein the molding compound encapsulates top and side surfaces of the silicon die. |
| US11094666B2 |
Bonding wire, semiconductor package including the same, and wire bonding method
A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad. |
| US11094665B2 |
Chip package structure
A chip package structure, comprises a first chip having a plurality of first chip joints at a lower side thereof; a circuit board below the first chip; an upper side of the circuit board being arranged with a plurality of circuit board joints; in packaging, the first chip joints being combined with the circuit board joints of the circuit board so that the first chip is combined to the circuit board by a way of ACF combination or convex joint combination; and wherein in the ACF combination, ACFs are used as welding points to be combined to the pads at another end so that the chip is combined to the circuit board; and wherein in the convex pad combination, a convex pad is combined with a flat pad by chemically methods or physical methods; and these pads are arranged on the circuit board and the first chip. |
| US11094664B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes an electrode having a flat part and a non-flat part made up of a concave part, a joint layer being made of a sintered body of metal crystal grains provided on the flat part and the non-flat part of the electrode, and a semiconductor element being joined to the electrode with the joint layer therebetween, wherein the joint layer has a first region sandwiched between the non-flat part and the semiconductor element and a second region sandwiched between the flat part and the semiconductor element, and either one of the first region and the second region having a larger film thickness has a filling rate of the metal crystal grains smaller than the other one of the first region and the second region having a smaller film thickness. The present invention enhances reliability of a joint layer made of a sintered body of metal crystal grains. |
| US11094663B2 |
Method for transient liquid-phase bonding between metal materials using a magnetic force
Disclosed is a method for transient liquid-phase bonding between metal materials using a magnetic force. In particular, in the method, a magnetic force is applied to a transient liquid-phase bonding process, thereby shortening a transient liquid-phase bonding time between the metal materials, and obtaining high bonding strength. To this end, an attractive magnetic force is applied to a ferromagnetic base while a repulsive magnetic force is applied to a diamagnetic base, thereby to accelerate diffusion. This may reduce a bonding time during a transient liquid-phase bonding process between two bases and suppress formation of Kirkendall voids and voids and suppress a layered structure of an intermetallic compound, thereby to increase a bonding strength. |
| US11094662B1 |
Semiconductor assembly and method of manufacturing the same
The present disclosure provides a semiconductor assembly. The semiconductor assembly includes a first device, a second device, and an interconnect structure configured to electrically coupled the first device and the second device. The second device is stacked on the first device. The interconnect structure includes a first leg, a second leg, and a cross member connecting the first leg to the second leg, wherein the first leg penetrates through the cap dielectric layer and the second device and contacts a first conductive feature of the first device, and a second leg penetrates through the cap dielectric layer and contacts a second conductive feature of the second device. |
| US11094660B2 |
Semiconductor package
A semiconductor package includes: a connection structure having first and second surfaces opposing each other and including a redistribution layer; a semiconductor chip disposed on the first surface of the connection structure and having connection pads connected to the redistribution layer; an encapsulant disposed on the first surface of the connection structure and encapsulating the semiconductor chip; a passivation layer disposed on the second surface of the connection structure and having a plurality of first and second openings exposing, respectively, first and second regions of the redistribution layer; and a plurality of underbump metal layers connected to the first region of the redistribution layer through the plurality of first openings, respectively. |
| US11094656B2 |
Packaged semiconductor device with electroplated pillars
In a described example, a device includes an overcoat layer covering an interconnect; an opening in the overcoat layer exposing a portion of a surface of the interconnect; a stud on the exposed portion of the surface of the interconnect in the opening; a surface of the stud approximately coplanar with a surface of the overcoat layer; and a conductive pillar covering the stud and covering a portion of the overcoat layer surrounding the stud, the conductive pillar having a planar and un-dished surface facing away from the stud and the overcoat layer. |
| US11094654B2 |
Package structure and method of manufacturing the same
A package structure and a method of manufacturing the same are provided. The package structure includes a substrate, a redistribution layer (RDL) structure, a first die, an encapsulant and a plurality of conductive terminals. The RDL structure is disposed on and electrically connected to the substrate. A width of the RDL structure is less than a width of the substrate. The first die is disposed on the substrate and the RDL structure. The first connectors of the first die are electrically connected to the RDL structure. The second connectors of the first die are electrically connected to the substrate. A first pitch of two adjacent first connectors is less than a second pitch of two adjacent second connectors. The encapsulant is on the substrate to encapsulate the RDL structure and the first die. The conductive terminals are electrically connected to the first die through the substrate and the RDL structure. |
| US11094653B2 |
Bonded assembly containing a dielectric bonding pattern definition layer and methods of forming the same
A bonded assembly and a method of forming a bonded assembly includes providing a first semiconductor die including a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, providing a second semiconductor die including a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, forming a dielectric bonding pattern definition layer including bonding pattern definition openings therethrough over the second bonding pads, and bonding the second bonding pads to the first bonding pads, where the first metal pads expand through the bonding pattern definition openings and are bonded to a respective one of the second bonding pads. |
| US11094652B1 |
Configurable radio transceiver and method thereof
A radio frequency integrated circuit includes a transmitter integrated on a die, the transmitter circuit being controlled by a first logical signal and configured to receive a to-be-transmitted signal and output a first voltage at a first internal node; a receiver integrated on the die. The receiver circuit is controlled by the first logical signal and a second logical signal and configured to output a receive signal. A first pad, a second pad, and a first inductor integrated on the die, the first pad being connected to the first internal node, the second pad being connected to the second internal node, and the first inductor being placed across the first internal node and the second internal node. |
| US11094651B1 |
Vertically-aligned and conductive dummies in integrated circuit layers for capacitance reduction and bias independence and methods of manufacture
Vertically-aligned and conductive dummies in integrated circuit (IC) layers reduce capacitance and bias independence. Dummies are islands of material in areas of metal and semiconductor IC layers without circuit features to avoid non-uniform polishing (“dishing”). Conductive diffusion layer dummies in a diffusion layer and conductive polysilicon dummies in a polysilicon layer above the diffusion layer reduce bias dependence and nonlinear circuit operation in the presence of an applied varying voltage. ICs with metal dummies vertically aligned in at least one metal layer above the polysilicon dummies and diffusion dummies reduce lateral coupling capacitance compared to ICs in which dummies are dispersed in a non-overlapping layout by a foundry layout tool. Avoiding lateral resistance-capacitance (RC) ladder networks created by dispersed dummies improves signal delays and power consumption in radio-frequency (RF) ICs. |
| US11094650B1 |
Semiconductor arrangement and method of making
A semiconductor arrangement is provided. The semiconductor arrangement includes a first portion and a vertically conductive structure. The first portion includes a first dielectric layer and a first guard ring in the first dielectric layer. The first guard ring includes, in the first dielectric layer, a first metal layer coupled to a first via. The first portion includes a vertical conductive structure passing through the first dielectric layer and proximate by the first guard ring. |
| US11094649B2 |
Semiconductor package structure and method for manufacturing the same
Present disclosure provides a semiconductor package structure, which includes a redistribution layer (RDL) structure, an electronic device, a first reinforcement structure, a second reinforcement structure, and an encapsulant. The RDL structure has a passivation layer and a patterned conductive layer disposed in the passivation layer. The electronic device is disposed on the RDL structure. The first reinforcement structure is disposed on the RDL structure and has a first modulus. The second reinforcement structure is disposed on the first reinforcement structure and has a second modulus substantially less than the first modulus. The encapsulant is disposed on the RDL structure and encapsulates the electronic device, the first reinforcement structure and the second reinforcement structure. |
| US11094647B2 |
Methods and apparatus to eliminate wafer bow for CVD and patterning HVM systems
A method and apparatus for forming a backside coating on a substrate to counteract stresses from a previously deposited film is disclosed. In one embodiment, a method for flattening a bowed substrate includes providing a substrate having a film stack formed on a first major surface thereof, wherein the substrate comprises a bowed orientation, and forming a coating a second major surface of the substrate, wherein the coating is configured to counter stresses produced by the film stack and flattens the substrate from the bowed orientation. |
| US11094646B2 |
Methods of manufacturing an integrated circuit having stress tuning layer
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component. |
| US11094645B2 |
Semiconductor device and method of manufacturing a semiconductor device
An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein. |
| US11094643B2 |
Determining overlay of features of a memory array
Methods, apparatuses, and systems related to determining overlay of features of a memory array are described. An example method includes forming a plurality of contacts on a working surface and selectively forming a first portion of a layer of conductive lines and a second portion of the layer of conductive lines in contact with the contacts. The first portion of the layer of conductive lines formed over the working surface is separated from the second portion of the layer of conductive lines formed over the working surface by a gap. The method includes determining an overlay of at least one of the contacts formed over the working surface in the gap relative to one of the conductive lines formed over the working surface. |
| US11094642B2 |
Package structure
A package structure including a semiconductor die, a redistribution layer, a plurality of antenna patterns, a die attach film, and an insulating encapsulant is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The redistribution layer is located on the active surface of the semiconductor die and electrically connected to the semiconductor die. The antenna patterns are located over the backside surface of the semiconductor die. The die attach film is located in between the semiconductor die and the antenna patterns, wherein the die attach film includes a plurality of fillers, and an average height of the die attach film is substantially equal to an average diameter of the plurality of fillers. The insulating encapsulant is located in between the redistribution layer and the antenna patterns, wherein the insulating encapsulant encapsulates the semiconductor die and the die attach film. |
| US11094638B2 |
Semiconductor device
A semiconductor device includes a semiconductor chip including a semiconductor substrate with a top surface electrode deposited on a top surface of the semiconductor substrate. An insulating film selectively covers edges of a top surface of the top surface electrode, and a plating layer covers the top surface of the top surface electrode exposed to an opening of the insulating film. A metal wiring plate includes a junction part located over the insulating film and the plating layer, and provided with a groove recessed upward from a bottom surface of the junction part. A solder part fills the groove so as to bond the plating layer and the bottom surface of the junction part together. A boundary between the insulating film and the plating layer is encompassed within the groove. |
| US11094634B2 |
Semiconductor package structure comprising rigid-flexible substrate and manufacturing method thereof
A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures. The circuit layer is disposed over a surface of the flexible core, and electrically connected with the interconnection structures. |
| US11094631B2 |
Graphene layer for reduced contact resistance
A method includes forming a trench within a dielectric layer, the trench comprising an interconnect portion and a via portion, the via portion exposing an underlying conductive feature. The method further includes depositing a seed layer within the trench, depositing a carbon layer on the seed layer, performing a carbon dissolution process to cause a graphene layer to form between the seed layer and the underlying conductive feature, and filling a remainder of the trench with a conductive material. |
| US11094629B2 |
3D power device and system
A three-dimensional (3D) power device having a plurality of layers that are stacked on top of each other and insulated from each other by interlayers, the plurality of layers comprising a lower layer comprising electrical and thermal conductors; a group III-Nitride based device layer formed above the lower layer, the group III-Nitride based device layer comprising at least one group III-Nitride based power device; a control layer formed above the group III-Nitride based device layer, the control layer comprising at least one control device; and a redistribution layer in between the group III-Nitride based device layer and the control layer, the current redistribution layer comprising a metal pattern being provided for laterally redistributing electrical currents and/or heat. |
| US11094615B2 |
Semiconductor apparatus including leads and bonding wires
A semiconductor device, a drain electrode terminal supporting the semiconductor device and connected directly to a drain electrode pad, a source electrode terminal connected to a source electrode pad, and a gate electrode terminal are provided, wherein the source electrode terminal includes a wire post, a first lead extending from one end of the wire post, and a second lead extending from another end of the wire post, wherein the source electrode pad and the wire post of the source electrode terminal are connected to each other through a plurality of bonding wires, and wherein the semiconductor device, a surface, supporting the semiconductor device thereon, of the drain electrode terminal, the wire post of the source electrode terminal, the bonding wires, and part of the gate electrode terminal are covered with a mold resin. |
| US11094614B2 |
Semiconductor chip contact structure, device assembly, and method of fabrication
A semiconductor device structure may include a semiconductor device, disposed at least in part in a semiconductor substrate, and a first insulator layer, disposed on a surface of the semiconductor device, and comprising a first contact aperture, disposed within the first insulator layer. The semiconductor device structure may also include a first contact layer, comprising a first electrically conductive material, disposed over the insulator layer, and being in electrical contact with the semiconductor device through the first contact aperture, and a second insulator layer, disposed over the first contact layer, wherein the second insulator layer further includes a second contact aperture, displaced laterally from the first contact aperture, by a first distance. The semiconductor device structure may further include a second contact layer, comprising a second electrically conductive material, disposed over the second insulator layer, and electrically connected to the semiconductor device through the first and second contact aperture. |
| US11094610B2 |
Semiconductor power module
Provided is a semiconductor power module including: a first electrode on which a plurality of element arrays each including a plurality of semiconductor elements arranged in an X direction, are arranged in a Y direction; a first main wiring connected to the respective element arrays mounted on the first electrode; a first sensor mounted on a first detection target element as one of the semiconductor elements, which is least influenced by synthetic inductance of the first main wiring among the semiconductor elements of the plurality of element arrays mounted on the first electrode; a first control terminal disposed on the first electrode; and a control board configured to control a current flowing through the first detection target element based on a detection result of the first sensor obtained via the first control terminal. |
| US11094607B2 |
Heatsink retainer assembly
A heatsink retainer assembly, and components of the heatsink retainer assembly, are described. The heatsink retainer assembly includes one or more heatsink anchors mounted on a heatsink retention wire between several stops. The anchors include channels to receive the retention wire such that the anchors can slide over the retention wire between the stops. The stops retain the anchors on the retention wire. The anchors can be inserted into respective mounting holes of a carrier substrate by pressing the anchors into the mounting holes on a side of the carrier substrate carrying a heat source. A heatsink can be mounted on the heat source and the retention wire can extend over the heatsink to retain the heatsink against the heat source when the anchors are secured to the carrier substrate. Other embodiments are described and claimed. |
| US11094606B2 |
Bonded body, insulated circuit board with heat sink, and heat sink
An aluminum alloy member is made of an aluminum alloy having a Mg concentration set in a range of 0.4 mass % or more and 7.0 mass % or less and a Si concentration set to less than 1 mass %, the aluminum alloy member and a copper member are bonded to each other through solid-phase diffusion, and a compound layer made up of a first intermetallic compound layer that is disposed on the aluminum alloy member side and made of a θ phase of an intermetallic compound of Cu and Al, a second intermetallic compound layer that is disposed on the copper member side and made of a γ2 phase of an intermetallic compound of Cu and Al, and a Cu—Al—Mg layer provided between the first intermetallic compound layer and the second intermetallic compound layer is provided in a bonding interface between the aluminum alloy member and the copper member. |
| US11094605B2 |
Systems and methods for supporting a component
Interconnectors, interconnector assemblies, and methods for supporting components are provided. An interconnector as disclosed connects a supported component to another component or assembly securely and accurately, even where the supported component and the other component have different expansion or contraction characteristics. The interconnector includes a plurality of support elements disposed in an array. Each support element includes a support surface at a free end of the support element. The areas of the support surfaces decrease with distance from a center of the array. In a completed assembly, the free ends of the support elements in the array are joined to the supported component. |
| US11094604B2 |
System and method to enhance solder joint reliability
A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value. |
| US11094595B2 |
Memory arrays and methods used in forming a memory array comprising strings of memory cells
A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions that have horizontally-elongated trenches there-between. Sacrificial material is formed in the trenches. Vertical recesses are formed in the sacrificial material. The vertical recesses extend across the trenches laterally-between and are longitudinally-spaced-along immediately-laterally-adjacent of the memory-block regions. Bridge material is formed in the vertical recesses to line and less-than-fill the vertical recesses and form bridges there-from that have an upwardly-open cup-like shape. The sacrificial material in the trenches is replaced with intervening material that is directly under the bridges. Additional methods and structures independent of methods are disclosed. |
| US11094592B2 |
Semiconductor devices and systems comprising memory cells and a source
A method of forming a semiconductor device comprises forming sacrificial structures and support pillars. The sacrificial structures comprise an isolated sacrificial structure in a slit region and connected sacrificial structures in a pillar region. Tiers are formed over the sacrificial structures and support pillars, and a portion of the tiers are removed to form tier pillars and tier openings, exposing the connected sacrificial structures and support pillars. The connected sacrificial structures are removed to form a cavity, a portion of the cavity extending below the isolated sacrificial structure. A cell film is formed over the tier pillars and over sidewalls of the cavity. A fill material is formed in the tier openings and over the cell film. A portion of the tiers in the slit region is removed, exposing the isolated sacrificial structure, which is removed to form a source opening. The source opening is connected to the cavity and a conductive material is formed in the source opening and in the cavity. Semiconductor devices and systems are also disclosed. |
| US11094591B2 |
Semiconductor structure and fabrication method thereof
Semiconductor structures and fabrication methods are provided. An exemplary semiconductor structure includes a semiconductor substrate having a plurality of cell regions. Each of the cell regions includes a device region, a protection region surrounding the device region and an isolation region surrounding the device region and the protection region. The semiconductor structure also includes a device structure on the semiconductor substrate in the device region; a protection ring structure on the semiconductor substrate in the protection region; an isolation structure on the semiconductor substrate in the isolation region; a passivation layer on the protection ring structure, the device structure and the isolation structure; and a trench passing through the passivation layer in the isolation region. |
| US11094589B2 |
Multicolor self-aligned contact selective etch
Methods of forming and processing semiconductor devices which utilize the selective etching of aluminum oxide over silicon oxide, silicon nitride, aluminum oxide or zirconium oxide are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. |
| US11094587B2 |
Use of noble metals in the formation of conductive connectors
In one embodiment, a conductive connector for a microelectronic component may be formed with a noble metal layer, acting as an adhesion/wetting layer, disposed between a barrier liner and a conductive fill material. In a further embodiment, the conductive connector may have a noble metal conductive fill material disposed directly on the barrier liner. The use of a noble metal as an adhesion/wetting layer or as a conductive fill material may improve gapfill and adhesion, which may result in the conductive connector being substantially free of voids, thereby improving the electrical performance of the conductive connector relative to conductive connectors without a noble metal as the adhesion/wetting layer or the conductive fill material. |
| US11094586B2 |
Semiconductor device including interconnections having different structures and method of fabricating the same
A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material. |
| US11094582B2 |
Selective deposition method to form air gaps
A method for depositing a film to form an air gap within a semiconductor device is disclosed. An exemplary method comprises pulsing a metal halide precursor onto the substrate and pulsing an oxygen precursor onto a selective deposition surface. The method can be used to form an air gap to, for example, reduce a parasitic resistance of the semiconductor device. |
| US11094580B2 |
Structure and method to fabricate fully aligned via with reduced contact resistance
Techniques are provided to fabricate semiconductor devices. For example, a method includes forming a lower level interconnect line having a first hardmask layer thereon and embedded in a lower level dielectric layer. The first hardmask layer is removed to form a first opening having a first width in the lower level dielectric layer. The sidewalls of the lower level dielectric layer are etched in the first openings to form a second opening having a second width. The second width is greater than the first width. An upper level interconnect line is formed on the lower level interconnect line. |
| US11094575B2 |
Simultaneous bonding approach for high quality wafer stacking applications
In some embodiments, the present disclosure relates to a method for bonding a first wafer to a second wafer. The method includes aligning a first wafer with a second wafer, so the first and second wafers are vertically stacked and have substantially planar profiles extending laterally in parallel. The method further includes bringing the first and second wafers into direct contact with each other at an inter-wafer interface. The bringing of the first and second wafers into direct contact includes deforming the first wafer so that the first wafer has a curved profile and that the inter-wafer interface is localized to a center of the first wafer. The second wafer maintains its substantially planar profile throughout the deforming of the first wafer. The method further includes deforming the first wafer and/or the second wafer to gradually expand the inter-wafer interface from the center to an edge of the first wafer. |
| US11094574B2 |
Substrate supporting device and plasma processing apparatus
According to one embodiment, a substrate supporting device is a substrate supporting device that supports a substrate in a processing container of a plasma processing apparatus, the substrate supporting device including an electrostatic chuck including a placing plate containing at least a ceramic and having the substrate electrostatically attracted by the placing plate, a lift pin configured to be storable inside the electrostatic chuck and which delivers the substrate to and from the electrostatic chuck, and a cover containing at least a ceramic of a same type as the placing plate and configured to be attachable to and detachable from the lift pin. |
| US11094569B2 |
Substrate processing apparatus
A substrate processing apparatus according to an embodiment includes a cassette placing section, a processing unit, a transfer area, and an image capturing unit. On the cassette placing section, a cassette accommodating a plurality of substrates is placed. The processing unit washes or etches a peripheral portion of each substrate taken out from the cassette. The transfer area is interposed between the cassette placing section and the processing unit, and the substrate is transferred therein. The image capturing unit is disposed in the transfer area to capture an image of the substrate processed by the processing unit. The image includes both of (i) a peripheral portion of an upper surface or a lower surface of the substrate and (ii) an end face of the substrate. |
| US11094561B2 |
Semiconductor package structure
A semiconductor package structure includes a molding compound, a micro pin extending through the molding compound, and a die surrounded by the molding compound. The micro pin has a top surface, a bottom surface, and a sidewall extending from the bottom surface to the top surface of the micro pin. The sidewall of the micro pin has a first portion and a second portion. The first portion of the sidewall is adjacent to the bottom surface of the micro pin and free of the molding compound. The second portion of the sidewall is adjacent to the top surface of the micro pin and in contact with the molding compound. |
| US11094556B2 |
Method of manufacturing semiconductor devices using directional process
In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data. |
| US11094554B2 |
Polishing process for forming semiconductor device structure
A method for forming a semiconductor device structure is provided. The method includes providing a wafer over a polishing platen. The wafer includes a metal layer and a dielectric layer. The metal layer covers the dielectric layer and fills an opening of the dielectric layer. The method also includes polishing the wafer using a first operation to thin down the metal layer. The first operation has a first polishing selectivity of the metal layer to the dielectric layer. The method further includes polishing the wafer using a second operation to further thin down the metal layer until the dielectric layer is exposed. The second operation has a second polishing selectivity of the metal layer to the dielectric layer. The second polishing selectivity is different from the first polishing selectivity. The first operation and the second operation are performed in-situ on the polishing platen. |
| US11094550B2 |
Etching method and etching apparatus
An etching method include: etching a silicon-containing film or a metal-containing film formed on a substrate; and heating the substrate by temporarily irradiating the substrate with electromagnetic waves during the etching. |
| US11094548B2 |
Apparatus for cleaning substrate and substrate cleaning method
An apparatus for cleaning a substrate has a holding unit 60 that holds a substrate W; a rotated unit 30 connected to the holding unit 60; a rotating unit 35 that is provided on a peripheral outer side of the rotated unit 30 and rotates the rotated unit 30; and a cleaning unit 10, 20 that physically cleans the substrate W held by the holding unit 60. |
| US11094546B2 |
Method for selectively depositing a metallic film on a substrate
A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed. |
| US11094545B2 |
Self-aligned insulated film for high-K metal gate device
A method forming a gate dielectric over a substrate, and forming a metal gate structure over the semiconductor substrate and the gate dielectric. The metal gate structure includes a first metal material. The method further includes forming a seal on sidewalls of the metal gate structure. The method further includes forming a dielectric film on the metal gate structure, the dielectric film including a first metal oxynitride comprising the first metal material and directly on the metal gate structure without extending over the seal formed on sidewalls of the metal gate structure. |
| US11094544B2 |
Methods of forming self-aligned vias
Processing methods comprising selectively orthogonally growing a first material through a mask to provide an expanded first material are described. The mask can be removed leaving the expanded first material extending orthogonally from the surface of the first material. Further processing can create a self-aligned via. |
| US11094542B2 |
Selective deposition of etch-stop layer for enhanced patterning
Methods, systems, and computer programs are presented for selective deposition of etch-stop layers for enhanced patterning during semiconductor manufacturing. One method includes an operation for adding a photo-resist material (M2) on top of a base material (M1) of a substrate, M2 defining a pattern for etching M1 in areas where M2 is not present above M1. The method further includes operations for conformally capping the substrate with an oxide material (M3) after adding M2, and for gap filling the substrate with filling material M4 after the conformally capping. Further, a stop-etch material (M5) is selectively grown on exposed surfaces of M3 and not on surfaces of M4 after the gap filling. Additionally, the method includes operations for removing M4 from the substrate after selectively growing M5, and for etching the substrate after removing M4 to transfer the pattern into M1. M5 adds etching protection to enable deeper etching into M1. |
| US11094541B2 |
Anti-reflective coating materials
In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure. |
| US11094538B2 |
Method of forming graphene
Provided is a method of forming graphene. The method of forming graphene includes treating a surface of a substrate placed in a reaction chamber with plasma while applying a bias to the substrate, and growing graphene on the surface of the substrate by plasma enhanced chemical vapor deposition (PECVD). |
| US11094536B2 |
Method of manufacturing semiconductor elements
A method of manufacturing semiconductor elements includes: disposing a semiconductor layer made of a nitride semiconductor on a first wafer; and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge of the first wafer and the first region of the first wafer in each of a plurality of first directions parallel to respective m-axes of the semiconductor layer is smaller than a second distance between the edge of the first wafer and the first region of the first wafer in each of a plurality of second directions parallel to respective a-axes of the semiconductor layer. |
| US11094532B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
There is provided a technique that includes forming a film containing silicon, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times, the cycle including: forming a first layer containing silicon, carbon, and nitrogen by performing a set a predetermined number of times, the set including: supplying a first precursor, which contains at least two Si—N bonds and at least one Si—C bond in one molecule, to the substrate; and supplying a second precursor, which contains nitrogen and hydrogen, to the substrate; and forming a second layer by supplying an oxidant to the substrate, to thereby oxidize the first layer. |
| US11094530B2 |
In-situ curing of color conversion layer
A method of fabricating a multi-color display includes dispensing a photo-curable fluid that includes a color conversion agent over a display having a backplane and an array of light emitting diodes electrically integrated with backplane circuitry of the backplane, activating a plurality of light emitting diodes in the array of light emitting diodes to illuminate and cure the first photo-curable fluid to form a color conversion layer over each of the first plurality of light emitting diodes to convert light from the plurality of light emitting diodes to light of a first color, and removing an uncured remainder of the first photo-curable fluid. This process is repeated with a fluid having different color conversion components for another color. |
| US11094529B2 |
Substrate processing apparatus and substrate processing method
A substrate processing apparatus includes a substrate holder, and a discharge head for peripheral area from which a fluid is discharge toward a surface peripheral area of the substrate held on the substrate holder. The discharge head for peripheral area includes multiple nozzles, and a support part that supports the nozzles integrally. The nozzles include a processing liquid nozzle from which a processing liquid is discharged toward the surface peripheral area, and a gas nozzle from which gas is discharged toward the surface peripheral area. The gas nozzle is placed upstream of a rotative direction of the substrate relative to the processing liquid nozzle. |
| US11094523B2 |
Processing method for wafer
A processing method for a wafer having a chamfered portion on an outer circumference thereof includes a step of irradiating a laser beam of a transmission wavelength to the wafer along an outer circumferential edge of the wafer at a position on an inner side of a predetermined distance from the outer circumferential edge of the wafer to form an annular modified region having a depth from a front face of the wafer to a finish thickness, a step of irradiating a laser beam of a transmission wavelength to the wafer on an outer circumferential portion of the wafer to radially form a plurality of modified regions having the depth from the front face of the wafer to the finish thickness on the outer circumferential portion of the wafer, and a step of grinding a back face of the wafer to thin the wafer to the finish thickness. |
| US11094521B2 |
Dual mode mass spectrometer
Disclosed herein is an ion analysis instrument comprising a Time of Flight (“TOF”) mass analyser comprising a reflectron. The instrument is operable in at least a first mode and a second mode, wherein in said first mode ions are caused to turn around at a first point in the reflectron and wherein in said second mode ions are caused to turn around at a second point in the reflectron such that the distance traveled by ions within the Time of Flight mass analyser is greater in the second mode than the distance traveled by ions within the Time of Flight mass analyser in the first mode. In this way, the operating modes can be selectively optimised for the analysis of ions of different masses. |
| US11094520B2 |
Multiple gas flow ionizer
An ionizer includes a probe having multiple coaxially aligned conduits. The conduits may carry liquids, and nebulizing and heating gases at various flow rates and temperatures, for generation of ions from a liquid source. An outermost conduit defines an entrainment region that transports and entrains ions in a gas for a defined distance along the length of the conduits. In embodiments, various voltages may be applied to the multiple conduits to aid in ionization and to guide ions. Depending on the voltages applied to the multiple conduits and electrodes, the ionizer can act as an electrospray, APCI, or APPI source. Further, the ionizer may include a source of photons or a source of corona ionization. Formed ions may be provided to a downstream mass analyser. |
| US11094516B2 |
Mass spectrometer, mass spectrometry method, and mass spectrometry program
A device that performs MSn analysis including: a mass window group setting information input receiver that receives input of information concerning the number of mass window groups, the number of mass windows, and a mass-to-charge ratio width of each of the mass windows; a mass window group setter that sets a first mass window group and a second mass window group, in which a mass-to-charge ratio at a boundary of adjacent mass windows differs from a mass-to-charge ratio at a boundary of mass windows in the first mass window group; a product-ion scan measurement section that performs, for each of the first and second mass window groups, an operation of performing scan measurement of product ions by use of the plurality of mass windows in sequence to acquire pieces of product-ion scan data; and a product-ion spectrum generator that generate a product-ion spectrum by integrating pieces of product-ion scan data. |
| US11094512B2 |
Plasma processing apparatus and plasma processing method
According to one embodiment, a plasma processing apparatus includes a processing chamber, a sample stage that is disposed inside the processing chamber and electrically divided into a plurality of regions on which a sample is placed, an electromagnetic wave introduction unit that introduces electromagnetic waves into the processing chamber, and a bias power applying unit that applies bias power to the sample stage, in which the bias power applying unit is configured to include a first radio frequency power applying unit that applies first radio frequency power to a first region out of the plurality of electrically divided regions of the sample stage, a second radio frequency power applying unit that applies second radio frequency power to a second region out of the plurality of electrically divided regions of the sample stage, and a phase adjuster that controls the first radio frequency power applying unit and the second radio frequency power applying unit to shift the phases of the first radio frequency power and the second radio frequency power by a predetermined amount. |
| US11094511B2 |
Processing chamber with substrate edge enhancement processing
Embodiments of the present disclosure generally provide an apparatus and methods for processing a substrate. More particularly, embodiments of the present disclosure provide a processing chamber having an enhanced processing efficiency at an edge of a substrate disposed in the processing chamber. In one embodiment, a processing chamber comprises a chamber body defining an interior processing region in a processing chamber, a showerhead assembly disposed in the processing chamber, wherein the showerhead assembly has multiple zones with an aperture density higher at an edge zone than at a center zone of the showerhead assembly, a substrate support assembly disposed in the interior processing region of the processing chamber, and a focus ring disposed on an edge of the substrate support assembly and circumscribing the substrate support assembly, wherein the focus ring has a step having a sidewall height substantially similar to a bottom width. |
| US11094504B2 |
Resonator coil having an asymmetrical profile
Embodiments herein are directed to a resonator for an ion implanter. In some embodiments, a resonator may include a housing, and a first coil and a second coil partially disposed within the housing. Each of the first and second coils may include a first end including an opening for receiving an ion beam, and a central section extending helically about a central axis, wherein the central axis is parallel to a beamline of the ion beam, and wherein an inner side of the central section has a flattened surface. |
| US11094501B2 |
Secondary charged particle imaging system
A secondary charged particle imaging system comprising: a backscattered electron detector module, wherein the backscattered electron detector module is rotatable between a first angular position and a second angular position about an axis. |
| US11094493B2 |
Emitter structures for enhanced thermionic emission
In one embodiment, a system includes a cathode and a thermionic emitter installed at least partially within the cathode tube of the cathode. The thermionic emitter is in a shape of a hollow cylinder. The hollow cylinder includes an outer surface and an unsmooth inner surface. The outer surface is configured to contact an inner surface of the cathode tube. The unsmooth inner surface includes a plurality of structures that provide an increase in surface area over a smooth surface. |
| US11094492B2 |
Fuses, vehicle circuit for electric vehicle and electric vehicle
The present utility model relates to a fuse, a vehicle circuit for an electric vehicle, and an electric vehicle. The fuse has a longitudinal direction and a transverse direction, and includes: a bushing, having a through-hole cavity extending in the longitudinal direction and for accommodating quartz sand; a fuse body, accommodated in the through-hole cavity and having a plurality of openings spaced apart from each other in the transverse direction; and two contact blades, positioned at two ends of the through-hole cavity and each soldered to the fuse body by a conductive plate. An arc extinguishing medium layer is provided on the fuse body. A side edge of the arc extinguishing medium layer contacts edges of any two adjacent openings of the plurality of openings so as to cause the arc extinguishing medium layer to be close to a minimum transverse spacing between the two opening edges. |
| US11094487B2 |
Current interrupt device based on thermal activation of frangible glass bulb
Embodiments described herein relate generally to a current interrupt device (CID) including a frangible bulb that is configured to be thermally triggered. In some embodiments, the CID includes a breaking contact electrically coupled to a fixed contact and held in electrical contact by the frangible bulb. In some embodiments, the frangible bulb is configured to break at a temperature threshold. In some embodiments, the breaking contact is configured to bend, rotate and/or otherwise deform about a hinge point in order to become electrically disconnected from the fixed contact when the frangible bulb breaks. In some embodiments, opening the electrical circuit between the breaking contact and the fixed contact may prevent overcharging, overvoltage conditions, overcurrent conditions, thermal runaway, and/or other catastrophic failure events. |
| US11094482B2 |
Control devices having independently suspended buttons for controlled actuation
A control device includes a button assembly having one or more buttons and a button carrier that includes a plurality of resilient, independently deflectable spring arms. The control device may be configured as a wall-mounted keypad to control a load control device, or as a thermostat to control a temperature regulation appliance. The button carrier may be configured to prevent interference between the buttons during operation of the control device. The button assembly may be captured between a faceplate of the control device and a housing that is attached to a rear side of the faceplate. The control device may include one or more button retainers that are attached to the buttons and that are configured to align respective outer surfaces of the buttons relative to each other, and relative to the faceplate of the control device, when the buttons are in respective rest positions. |
| US11094476B2 |
Structural super-capacitor composite and method of making same
Multi-layer modular capacitors adapted to be electrically coupled to each other and formed into a structural piece that is electrically coupled to an electrical device requiring a power supply. |
| US11094474B2 |
Photoelectric conversion element, dye-sensitized solar cell, metal complex dye, dye composition, and oxide semiconductor electrode
A photoelectric conversion element includes a conductive support, a photoconductor layer including an electrolyte, a charge transfer layer including an electrolyte, and a counter electrode, in which the photoconductor layer has semiconductor fine particles carrying a metal complex dye represented by a specific formula. |
| US11094472B2 |
Method for producing electrode for aluminum electrolytic capacitor
Provided is a method for producing an electrode for an electrolytic capacitor, the method comprising: a hydration step in which an aluminum electrode is immersed in a hydration treatment solution having a temperature of 80° C. or higher; and a chemical conversion step in which the aluminum electrode is subjected to chemical conversion treatment up to a formation voltage of at least 400 V. The hydration treatment solution contains a hydration inhibitor. The thickness of a hydrated film formed in the hydration step satisfies the following condition, 0.6≤t2/t1≤1, wherein t1 is the average thickness of the hydrated film formed in a depth range of up to 100 μm from the surface of the aluminum electrode, and t2 is the average thickness s of the hydrated film formed in a deep portion at least 100 μm from the surface of the aluminum electrode. |
| US11094466B2 |
Multi-layered ceramic electronic component
A multi-layered ceramic electronic component has a ceramic body including dielectric layers and a plurality of internal electrodes opposing each other with the dielectric layers interposed therebetween. External electrodes are disposed on an exterior of the ceramic body and are electrically connected to the internal electrodes. Each external electrode includes an electrode layer electrically connected to internal electrodes, and a conductive resin layer arranged on the electrode layer. The conductive resin layer extends to first and second surface of the ceramic body, and a ratio of a thickness (Tb) of the conductive resin layer extending onto the first surface and the second surface of the ceramic body to a length (Lm) of a length direction margin portion of the ceramic body satisfies 2 to 29%. |
| US11094464B2 |
Electronic component
An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction. |
| US11094454B2 |
Noise reduction unit
A noise reduction unit includes a conductor having a winding portion and a ring-shaped core which is made of a magnetic material and is inserted through the winding portion, and a housing which houses the conductor and the ring-shaped core. An inner wall surface of the housing is formed with a recess configured to receive a part of the winding portion located on an outer circumferential surface of the ring-shaped core. The conductor is housed in the housing so that the part of the winding portion is received in the recess. |
| US11094451B2 |
Electronic component and method for manufacturing electronic component
An electronic component comprises: a magnetic core having a flat base and a core, the flat base having a top, a bottom, and first and second opposite sides, the core is on the top; a winding having an edgewise coil including a wound flat wire and the core, the winding having two non-wound flat wires extending therefrom; and a magnetic exterior body covering the core and the edgewise coil. The two non-wound flat wires extend along the top, the first side, the bottom and then the second side, and the two non-wound flat wires are non-adhesively positioned around the flat base. The two non-wound flat wires on the bottom are externally exposed electrodes. The second side inclines towards the core. The two ends of the two non-wound flat wires are embedded into the magnetic exterior body to fix the two non-wound flat wires to the magnetic exterior body. |
| US11094450B2 |
Core component
A core component is disclosed. In an embodiment, the core component includes at least one edge that has a transition, wherein the transition is asymmetrical. |
| US11094448B2 |
Inductor and inductor module having the same
An inductor includes: a body in which a plurality of insulating layers on which a plurality of coil patterns are arranged are stacked; and first and second external electrodes disposed on an external surface of the body, wherein the plurality of coil patterns are connected to each other through a coil connection portion and form a coil having both ends connected to the first and second external electrodes through a coil withdrawal portion, and wherein the coil connection portion is configured as a material having a higher thermal expansion coefficient than that of the insulating layers. |
| US11094447B2 |
Chip inductor and method for manufacturing the same
A chip inductor includes a sealing body having a mounting surface and a coil conductor sealed in an interior of the sealing body, wherein the coil conductor includes a first coil end exposed from the mounting surface of the sealing body, a second coil end exposed from the mounting surface of the sealing body, and a spiral portion of spiral form connected to the first coil end and the second coil end and routed along a normal direction of the mounting surface of the sealing body from the first coil end and the second coil end. |
| US11094445B2 |
Electrical equipment having an assembly with a cylindrical bellow for pressure and volume compensation
An oil filled electrical equipment includes an assembly for oil filling and hermetically sealing the electrical equipment. The assembly includes a cylindrical bellow mounted on a plate of the electrical equipment with one or more fittings. The bellow provides pressure and volume compensation in the electrical equipment. The bellow includes a cylinder with a plurality of convolutions for expanding and contracting to provide the compensation. The bellow further includes two covers attached with the cylinder at two ends of the cylinder. Each cover includes a cylindrical part that is open at a first end and closed at a second end. The first end terminates at a circular face for mounting the cover on a convolution at a corresponding end of the cylinder. The second end includes an opening for oil filling and hermetically sealing the electrical equipment, and mounting the bellow on the plate. |
| US11094441B2 |
Magnetization of a hollow shaft
The present invention discloses an apparatus for magnetizing a ferromagnetic, electrically conductive hollow shaft, the apparatus comprising: an electrically conductive rod-like element for generating one or a plurality of magnetic fields by means of an internal contact device arranged thereon and used for contacting with an inner contact region on an inner side of the hollow shaft; an external contact device for contacting with an outer contact region on an outer side of the hollow shaft; and a current source for generating a current pulse through the rod-like element, the internal contact device and the external contact device and also through the hollow shaft between the inner and outer contact regions; wherein a first pole of the current source is connected to or adapted to be connected to at least one current supply contact point of the rod-like element and a second pole of the current source is connected to or adapted to be connected to the external contact device, and wherein an electrical polarity of the first pole is opposite to the electrical polarity of the second pole. The invention further discloses a corresponding method. |
| US11094440B2 |
Linearly enhanced circular magnetic field actuator
An apparatus may include a rotatable permanent magnet exhibiting a magnetic field. Alternatively, the actuation apparatus may include a set of coils configured to generate a rotatable magnetic field. The apparatus may further include a magnetic shape memory (MSM) element including MSM material and having a long axis, where the MSM element is configured to contract locally in a first part in response to local exposure to a first component of the magnetic field that is substantially perpendicular to the long axis and to not contract locally in a second part that is exposed to a second component of the magnetic field that is not substantially perpendicular to the long axis. The apparatus may include a first fixed magnet positioned at a first end of the MSM element and a second fixed magnet positioned at a second end of the MSM element. |
| US11094437B2 |
Non-corrosive soft-magnetic powder
The invention relates to a soft-magnetic powder comprising a core of a soft-magnetic material and a coating, the coating comprising an insulation treatment compound and an inhibitor, the inhibitor being: (e) a carboxylic acid with the general formula (I) wherein R1 is a single bond or C1-C6-alkylene, R2 to R6 are each independently H, OH, —X—COOH, C1-C6-alkyl, C2-C6-alkenyl, C2-C6-alkynyl, C3-C7-cycloalkyl, C6-C12-aryl, COOR7, OR8, or two adjacent groups R2 to R6 together form a ring, X is a single bond or C1-C6-alkylene; R7, R8 are C1-C20-alkyl; or a salt of the carboxylic acid, and/or (f) a compound of the general formula (II) (R9—O—)(R10—O—)(R11—O—)PO (II) wherein R9 to R11 independently of each other indicate C1-C20-alkyl, C2-C20-alkenyl, C2-C6-alkynyl, C3-C7-cycloalkyl, C6-C12-aryl, unsubstituted or substituted with one or more groups selected from OH and NH2, or R9 to R11 are each independently a polydiol moiety having a molecular weight MW of 500 to 30000 g/mol which is optionally capped at the end by —C1-C20-alkyl and/or at the connection to O atom bonding to P by C1-C20-alkylene, or R10, R11 are each independently H. The invention further relates to a process for producing the soft-magnetic powder and an electronic component comprising the soft-magnetic powder. |
| US11094432B2 |
Communication cable and crimping member
A twisted pair cable includes a twisted portion in which two communication wires are twisted each other and an untwisted portion in which the two communication wires are untwisted. The terminal is connected to a tip part of the untwisted portion. A crimping member includes a barrel portion crimped to an end part of the twisted portion on the side of the untwisted portion and a non-crimping portion extending from the barrel portion toward the untwisted portion and not crimped to the twisted pair cable. The non-crimping portion includes a facing portion facing the two communication wires in the untwisted portion and rising portions rising from both end part in a direction orthogonal to a longitudinal direction of the untwisted portions in the facing portion. The rising portions surround the two communication wires together with the facing portion. |
| US11094431B2 |
Methods and systems for securely accessing and managing aggregated submarine cable system information
Aggregated, submarine cable system information is securely stored, accessed and managed. Security is assured through the use of multi-factor authentication that is compliant with National Institutes of Standards And Technology and US. Government Defense Federal Acquisition Regulation requirements. Further, real-time audit logs are generated as end-users access controlled unclassified information. |
| US11094430B2 |
Electric wire conductor, covered electric wire, and wiring harness
An electric wire conductor having both flexibility and a space-saving property. Also provided are a covered electric wire and a wiring harness containing the electric wire conductor. An electric wire conductor contains a wire strand containing a plurality of elemental wires twisted together. The electric wire conductor has a flat portion in which a cross section intersecting an axial direction of the wire strand has a flat shape. Assuming a conductor cross-sectional area of the flat portion as s mm2 and a vacancy ratio defined as a ratio of vacancies not occupied by the elemental wires in a cross section of the flat portion as v %, the conductor cross-sectional area and the vacancy ratio satisfies v>0.29 s+2.0. The covered electric wire contains electric wire conductor and an insulator covering the conductor. The wiring harness contains the covered electric wire. |
| US11094428B2 |
Shielded cables
The present invention relates to a cable, suitable for both electrical and data transmission, comprising at least one shield layer, comprising a metal layer directly adhering onto the polymeric layer. |
| US11094427B2 |
Electrical field grading material and use thereof in electrical cable accessories
Electrical field grading material which comprises a non-polar elastomeric polymer, a phyllosilicate filler and a carbon black filler, wherein any carbon black filler present in the electric field grading material has a dibutyl phthalate (DBP) absorption number from 30 to 80 ml/100 g. The above material may be used in electrical cable accessories, particularly electrical cable joints or terminations for medium or high voltage cable. The electrical field grading material according to the present invention has varioresistive properties, particularly a significant variation of electrical conductivity as a function of the applied voltage within a reduced voltage range, so as to guarantee a high value of conductivity above a critical value of the electrical field, and therefore to ensure an even distribution of the electrical field lines within the material. |
| US11094420B1 |
System and method of maintaining social distancing guidelines with nearby persons
A system and method of maintaining social distancing guidelines with nearby persons allows a user to receive a notification when other people enter within a perimeter around them. A wearable device, especially a belt, equipped with infrared (IR) sensors detects heat signatures of nearby objects. The wearable device subsequently relays this information to the user's mobile electronic device, immediately notifying the user of persons within the predefined radius. The wearable device further differentiates between different distinctly human heat signatures, using artificial intelligence to determine whether a nearby person has the elevated internal temperature that could be attributed to COVID-19, or if the person within the preset radius is asymptomatic. In this way, users may be alerted to dangers approaching from all sides. Users are participants in the global effort to reduce human exposure and help in reducing the distribution of cases to manageable levels. |
| US11094410B2 |
Method and system for automated personal training
Example embodiments may relate to a system, method, apparatus, and computer readable media configured for monitoring a user performing an exercise and generating a avatar of the user and a virtual shadow, wherein the virtual shadow illustrates proper form of the exercise. The example embodiments may further be configured for determining an amount of overlap between the virtual avatar and the virtual shadow, and generating a feedback score based on the amount of overlap. |
| US11094409B2 |
Application unlock using a connected physical device and transfer of data therebetween
According to one embodiment, a system includes a medical device configured to provide a function to a user, communicate via a wireless communication channel with one or more other devices, and send a signal to shift a medical device application from a locked state to an unlocked state. The system also includes a computing device having wireless communication channels and a processor and logic integrated with and/or executable by the processor. The logic is configured to cause the computing device to communicate with the medical device, execute the medical device application, and shift from the locked state to the unlocked state in response to receiving the signal from the medical device. Core functionality of the medical device application is disabled when the medical device application is in the locked state, and some functionality applicable to the medical device is enabled when the medical device application is in the unlocked state. |
| US11094407B2 |
Electronics miniaturization platform for medication verification and tracking
A drug delivery form includes a drug and electronics. The electronics includes memory(ies) having drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The electronics includes communication circuitry configured to read data from and write data to the drug delivery form information. An apparatus includes memory(ies) having computer readable code, and processor(s). The processor(s) cause the apparatus to perform operations including communicating with a drug delivery form including a drug and drug delivery form information, including information about the drug and about at least part of a supply chain from manufacture of the drug delivery form to a current location in the supply chain. The processor(s) cause the apparatus to perform reading data from or writing data into the drug and drug delivery form information. |
| US11094398B2 |
Methods for calculating corrected amplicon coverages
Methods, systems, and computer-readable media are disclosed for calculating corrected amplicon coverages. One method includes: mapping a plurality of reads of a plurality of amplicons based on amplified target regions of a sample suspected of having one or more genetic abnormalities to a reference sequence that includes one or more nucleic acid sequences corresponding to the amplified target regions; calculating amplicon coverages and total reads, wherein amplicon coverages is a number of reads mapped to an amplicon, and total reads is a number of mapped reads; and calculating corrected amplicon coverages based on the calculated amplicon coverages and calculated total reads by applying a batch effect correction. |
| US11094393B1 |
Apparatus and method for clearing memory content
Aspects of the present disclosure relate to systems and methods for issuing and executing a clear content command within a memory. Certain embodiments provide a method for the memory to receive a clear content command configured to clear content stored on the memory in a first set of memory cells of the plurality of memory cells of the plurality of memory banks. Certain embodiments provide a method of implementing within a DRAM memory the clear command by reusing existing refresh mechanism with minimal or no additional transistors or other hardware within the sense amplifier circuitry of the memory. |
| US11094392B2 |
Testing of fault detection circuit
A system-on-chip includes first and second devices. An interconnect segment couples between the first and second devices. A bridge is coupled between the first and second devices and coupled to the interconnect segment. At least one of the bridge or interconnect segment include first and second multiplexers, a monitor circuit, and exclusive-OR logic. The first multiplexer has first and second multiplexer inputs and a first multiplexer output. The second multiplexer has third and fourth multiplexer inputs and a second multiplexer output. The monitor circuit has a first and second monitor circuit outputs. The first monitor circuit output is coupled to the second multiplexer input and the second monitor circuit output is coupled to the fourth multiplexer input. The exclusive-OR logic has first and second exclusive-OR logic inputs. The first exclusive-OR logic input couples to the first multiplexer output and the second exclusive-OR logic input couples to the second multiplexer output. |
| US11094390B2 |
Semiconductor memory devices and methods of operating semiconductor memory devices
A semiconductor memory device comprises a memory cell array including segments disposed at corresponding intersections of row and column blocks, each row block including dynamic memory cells coupled to word-lines and bit-lines, a row decoder that activates a first word-line of a first row block in response to a row address, determines whether the first row block is a master block based on a first fuse information and a second row block is mapped as a slave to the master block, activates a second word-line of the second row block, and outputs a row block information signal, and a column decoder accessing a portion of first memory cells coupled to the first word-line or a portion of second memory cells coupled to the second word-line based on a column address, the row block information signal and a second fuse information. |
| US11094388B1 |
Anti-fuse device and program method using the same
An anti-fuse device includes an anti-fuse array and a biasing circuit. The anti-fuse array includes an anti-fuse cell that has a gate node, a gate oxide layer and a source-drain node. The biasing circuit is coupled to the anti-fuse array and is configured to bias the gate node of the anti-fuse cell with a first bias voltage during a program operation, and bias the source-drain node of the anti-fuse with a second bias voltage during the program operation. A voltage level of the first bias voltage is lower than a voltage level of the second bias voltage, and a voltage difference between the first bias voltage and the second bias voltage is higher than a gate oxide breakdown voltage of the gate oxide layer. |
| US11094386B1 |
Device, system, and method to verify data programming of a multi-level cell memory based on one of temperature, pressure, wear condition or relative position of the memory cell
Techniques and mechanisms for verifying the programming of a multi-bit cell of a memory array. In an embodiment, program verification is performed based on a signal, other than a word line voltage, which includes an indication of a reference voltage that is to be a basis for evaluating a currently programmed threshold voltage of a memory cell. A determination that the particular indication is to be communicated with the signal is made based on a detected state of the memory device which includes the memory cell. In another embodiment, the detected state includes one of a thermal condition at the memory array, a pressure condition at the memory array, a wear condition of the memory array, or a relative position of the cell with respect to one or more other cells of the memory array. |
| US11094380B2 |
Semiconductor memory device
A semiconductor memory device includes a memory block, a plurality of bit lines, a plurality of select gate lines, a plurality of word lines, and a controller. The memory block includes a plurality of memory strings, each memory string including a selection transistor and a plurality of memory cells. The plurality of bit lines are arranged in the first direction and connected to the respective memory strings. The plurality of select gate lines are arranged in the second direction and connected to gates of the respective selection transistors of the memory strings. The plurality of word lines are arranged in the third direction and connected to gates of the respective memory cells of the memory strings. The controller is configured to perform an erase operation in a unit of the memory block, and perform a sequence of erase verify operations. |
| US11094378B2 |
Resistance variable memory device including stacked memory cells
A resistance variable memory device may include a plurality of tiles in which memory cells are arranged. The first to third level of the word lines may be sequentially stacked on the plurality of tile regions with the decoding circuits along rows of the tile regions. A first level of the bit lines may be interposed between the first level of the word lines and the second level of the word lines. A first level of the bit lines may be extended along columns of the tile regions. The second level of the bit lines may be interposed between the second level of the word lines and the third level of the word lines. The second level of the bit lines may be extended along the columns of the tile regions. The first and third levels of the word lines at a selected row of a selected tile region among the tile regions and the second level of the bit lines at a selected column of the selected tile region may be controlled by a decoding circuit of the selected tile region. The second level of the word line at the selected row of the selected tile region and the first level of the bit line at the selected column of the selected tile region may be controlled by another decoding circuit of another tile region. |
| US11094374B1 |
Write data processing circuits and methods associated with computational memory cells
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines. |
| US11094371B2 |
Memory device for processing operation and method of operating the same
A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO. |
| US11094369B1 |
Semiconductor memory device and operating method thereof
A semiconductor memory device includes a cell array including a plurality of word lines; a plurality of address storing circuits, each of the plurality of address storing circuits suitable for storing a sampling address as a latch address, a valid bit indicating whether the latch address is valid, and a valid-lock bit indicating whether the latch address is accessed more than a certain number of times, each of the plurality of address storing circuits further suitable for outputting the latch address as a target address according to the valid bit and valid-lock bit; and a row control circuit suitable for refreshing one or more word lines based on the target address in response to a refresh command. |
| US11094364B2 |
Data storage device and operating method thereof
A data storage device includes a nonvolatile memory device including a plurality of memory blocks; and a device controller configured to control the nonvolatile memory device such that, when a first refresh scan command is received from a host device, a first refresh scan operation for the plurality of memory blocks is performed and then a first refresh scan result for the first refresh scan operation is transmitted to the host device, and when a first refresh operation command is received from the host device, a first refresh operation for the nonvolatile memory device is performed. |
| US11094361B2 |
Transistorless memory cell
In some embodiments, the present disclosure relates to an integrated circuit. The integrated circuit has an operative magnetic tunnel junction (MTJ) device configured to store a data state. The operative MTJ device is coupled to a bit-line. A regulating access apparatus is coupled between the operative MTJ device and a first word-line. The regulating access apparatus has one or more regulating MTJ devices that are configured to control a current provided to the operative MTJ device. |
| US11094360B2 |
Storage device, electronic component, and electronic device
A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region. |
| US11094355B1 |
Memory chip or memory array for wide-voltage range in-memory computing using bitline technology
A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines. |
| US11094353B2 |
Multiple location load control system
A load control device may include a semiconductor switch, a control circuit, and first and second terminals adapted to be coupled to a remote device. The load control device may include a first switching circuit coupled to the second terminal, and a second switching circuit coupled between the first terminal and the second terminal. The control circuit may be configured to render the first switching circuit conductive to conduct a charging current from an AC power source to a power supply of the remote device during a first time period of a half-cycle of the AC power source, and further configured to render the first and second switching circuits conductive and non-conductive to communicate with the remote device via the second terminal during a second time period of the half-cycle of the AC power source. |
| US11094346B2 |
Systems and methods for adaptive streaming of multimedia content
The disclosed computer-implemented method includes determining that audio quality is to be adjusted for a multimedia streaming connection over which audio data and video data are being streamed to a content player. The audio data is streamed at a specified audio quality level and the video data is streamed at a specified video quality level. The method also includes determining that a specified minimum video quality level is to be maintained while adjusting the audio quality level. Still further, the method includes dynamically adjusting the audio quality level of the multimedia streaming connection while maintaining the video quality level of the multimedia streaming connection at at least the specified minimum video quality level. Various other methods, systems, and computer-readable media are also disclosed. |
| US11094344B2 |
Hard disk drive with magnetic-disk substrate
A hard disk drive includes a doughnut-shaped magnetic-disk substrate having a circular hole provided in the center. The doughnut-shaped magnetic-disk substrate includes a pair of main surfaces, and an outer circumferential end surface and an inner circumferential end surface each including a side wall surface and a chamfered surface that is formed between each main surface and the side wall surface. A measurement point is provided on the outer circumferential end surface every 30 degrees in the circumferential direction with reference to a center of the substrate, and when a curvature radius of a shape of a portion between the side wall surface and the chamfered surface is determined at each measurement point, a difference in the curvature radius between neighboring measurement points is 0.01 mm or less. |
| US11094342B2 |
Disk device
According to one embodiment, in a disk device, a first pattern cut out from a burst region at a certain servo track by a first length and with a first start position, does not match a second pattern cut out from the burst region at an adjacent servo track by the first length and with an arbitrary second start position including first timing. The burst region at the servo tracks includes a first burst pattern including a first magnetized portion where a first value is recorded and a second magnetized portion where a second value reverse to the first value in polarity is recorded, the second magnetized portion being adjacent to the first magnetized portion in a down track direction. A width of the first magnetized portion in the down track direction and a width of the second magnetized portion in the down track direction are different from each other. |
| US11094338B1 |
SOT film stack for differential reader
The present disclosure generally relates to spin-orbital torque (SOT) differential reader designs. The SOT differential reader is a multi-terminal device comprising a first seed layer, a first spin hall effect (SHE) layer, a first interlayer, a first free layer, a gap layer, a second seed layer, a second SHE layer, a second free layer, and a second interlayer. The gap layer is disposed between the first SHE layer and the second SHE layer. The materials and dimensions used for the first and second seed layers, the first and second interlayers, and the first and second SHE layers affect the resulting spin hall voltage converted from spin current injected from the first free layer and the second free layer, as well as the ability to tune the first and second SHE layers. Moreover, the SOT differential reader improves reader resolution without decreasing the shield-to-shield spacing (i.e., read-gap). |
| US11094332B2 |
Low-complexity tonality-adaptive audio signal quantization
The invention provides an audio encoder for encoding an audio signal so as to produce therefrom an encoded signal, the audio encoder including: a framing device configured to extract frames from the audio signal; a quantizer configured to map spectral lines of a spectrum signal derived from the frame of the audio signal to quantization indices, wherein the quantizer has a dead-zone, in which the input spectral lines are mapped to quantization index zero; and a control device configured to modify the dead-zone; wherein the control device includes a tonality calculating device configured to calculate at least one tonality indicating value for at least one spectrum line or for at least one group of spectral lines, wherein the control device is configured to modify the dead-zone for the at least one spectrum line or the at least one group of spectrum lines depending on the respective tonality indicating value. |
| US11094329B2 |
Neural network device for speaker recognition, and method of operation thereof
Provided are a neural network device and a method of operation thereof. The neural network device for speaker recognition may include: a memory configured to store one or more instructions; and a processor configured to generate a trained second neural network by training a first neural network, for separating a mixed voice signal into individual voice signals by executing the one or more instructions, generate a second neural network by adding at least one layer to the trained first neural network, and generate a trained second neural network by training the second neural network, for separating the mixed voice signal into the individual voice signals and for recognizing a speaker of each of the individual voice signals. |
| US11094328B2 |
Conferencing audio manipulation for inclusion and accessibility
Various embodiments herein each include at least one of systems, methods, and software for conference audio manipulation for inclusion and accessibility. One embodiment, in the form of a method that may be performed, for example, on a server or a participant computing device. This method includes receiving a voice signal via a network and modifying an audible characteristic of the voice signal that is perceptible when the voice signal is audibly output. The method further includes outputting the voice signal including the modified audible characteristic. |
| US11094326B2 |
Ensemble modeling of automatic speech recognition output
One embodiment of the present invention sets forth a technique for performing ensemble modeling of ASR output. The technique includes generating input to a machine learning model from snippets of voice activity in the recording and transcriptions produced by multiple automatic speech recognition (ASR) engines from the recording. The technique also includes applying the machine learning model to the input to select, based on transcriptions of the snippet produced by at least one contributor ASR engine of the multiple ASR engines and at least one selector ASR engine of the multiple ASR engines, a best transcription of the snippet from possible transcriptions of the snippet produced by the multiple ASR engines. The technique further includes storing the best transcription in association with the snippet. |
| US11094325B2 |
Device and method for processing voice command for vehicle
A device for processing a voice command for a vehicle includes: a communication module to transmit a voice command received from a user to a voice recognition server, and to receive a recognized voice command from the voice recognition server; a controller identifying objects displayed on a screen of a touch display, and classifying the recognized voice command into a control command and a touch-based command; a control command processing module to perform a control operation corresponding to the control command; and a touch-based command processing module for selecting an object corresponding to the touch-based command from the touch display. |
| US11094323B2 |
Electronic device and method for processing audio signal by electronic device
An electronic device is disclosed. The electronic device comprises: multiple microphones for receiving audio signals generated by multiple sound sources; a communication unit for communicating with a voice recognition server; and a processor for determining the direction in which each of the multiple sound sources is located with reference to the electronic device, on the basis of the multiple audio signals received through the multiple microphones, determining at least one target sound source among the multiple sound sources on the basis of the duration of the determined direction of each of the sound sources, and controlling the communication unit such that the communication unit transmits, to the voice recognition server, an audio signal of a target sound source from which a predetermined voice is generated among the at least one target sound source. |
| US11094319B2 |
Systems and methods for generating a cleaned version of ambient sound
While a media content item is emitted by a second electronic device that is remote from the first electronic device, the first electronic device receives data that includes: timing information, offset information that indicates a difference between an initial position of the media content item and a current playback position of the media content item, and an audio stream that corresponds to the media content item. The first electronic device detects ambient sound that includes sound corresponding to the media content item emitted by the second electronic device. The first electronic device generates a cleaned version of the ambient sound by using the timing information and the offset information to align the audio stream with the ambient sound and performing a subtraction operation to substantially subtract the audio stream from the ambient sound. |
| US11094318B1 |
Providing an automated summary
Methods, systems, and apparatus, including computer programs encoded on computer storage media for summarizing a call. One of the methods includes generating text corresponding to processing audio produced during an interaction between two participants by executing natural language processing logic. The method includes identifying one or more topics by providing the generated text to a machine learning system, the machine learning system trained to identify topics based on text. The method also includes generating a summary of the interaction based on the one or more topics and the text. |
| US11094317B2 |
System and method for personalized natural language understanding
An electronic device for training a machine learning model includes at least one memory and at least one processor coupled to the at least one memory. The at least one processor is configured to train a classification layer of the model. To train the classification layer, the at least one processor is configured to receive, by the classification layer, one or more language contexts from an utterance encoder layer and to classify, by the classification layer, at least one portion of an utterance into an information type among a plurality of information types. The at least one processor may be further configured to jointly train a slot filling layer and an intent detection layer of the model. |
| US11094315B2 |
In-car communication control device, in-car communication system, and in-car communication control method
A determination unit (7) determines whether or not a specific passenger in a car has spoken, on the basis of sound data collected in the car. A control unit (8) activates an in-car communication function, when it is determined by the determination unit (7) that the specific passenger has spoken. |
| US11094313B2 |
Electronic device and method of controlling speech recognition by electronic device
An electronic device for adjusting a speech output rate (speech rate) of speech output data. |
| US11094310B2 |
Signal processor, noise canceling system, signal processing method, and program
According to the present disclosure, an additional sound generating unit detects, as a noise frequency, a frequency of a noise at a control point and generates an additional sound signal including signal components with additional frequencies different from the noise frequency. A canceling signal generating unit generates a canceling signal that cancels the noise at the control point. An emission unit outputs a control sound signal, generated by adding the additional sound signal to the canceling signal, to a loudspeaker and makes the loudspeaker emit the control sound. |
| US11094309B2 |
Audio processing techniques for semantic audio recognition and report generation
Example methods, apparatus and articles of manufacture to determine semantic information for audio are disclosed. Example apparatus disclosed herein are to process an audio signal obtained by a media device to determine values of a plurality of features that are characteristic of the audio signal, compare the values of the plurality of features to a first template having corresponding first ranges of the plurality of features to determine a first score, the first template associated with first semantic information, compare the values of the plurality of features to a second template having corresponding second ranges of the plurality of features to determine a second score, the second template associated with second semantic information, and associate the audio signal with at least one of the first semantic information or the second semantic information based on the first score and the second score. |
| US11094308B2 |
Keyboard device
A keyboard device includes white keys, black keys adjacent to the white keys, and guides that are arranged between the white keys and the black keys and restrict operation by coming into contact with the white keys and the black keys. The keyboard device may further include a housing that covers parts of the white keys and the black keys, and the guide may be arranged in the region covered by the housing. The keyboard device may further include caps that are provided between the guides and the white keys and the guides and the black keys, and that have a lower Young's modulus than the guides. |
| US11094304B2 |
Mute holder
A mute holder for a music stand includes a mute supporting plate having a plurality of mute supporting through holes for holding mutes, a non-continuous flat bottom edge, and a curved front edge forwardly extended from the flat bottom edge; a locking mechanism having a half-circular locking ring having one end attached on the flat bottom edge of the mute supporting plate and an opposite free end pivotably rotated with respect to the flat bottom edge of the mute supporting plate to lock the free end thereon and to release from the passes supporting plate; wherein the locking mechanism further includes a locking screw passing through the half-circular locking ring and to be biased against the music stand for locking thereon. |
| US11094299B2 |
Locking bridge assembly
A bridge body for a bridge assembly for a stringed instrument. The bridge body includes a plurality of saddle regions arranged in the bridge body, each of the saddle regions configured to accommodate a saddle, two receiving passages that pass through the bridge body from an upper side of the bridge body to a lower side of the bridge body, and upper recessed contact surfaces respectively arranged at upper ends of the receiving passages. |
| US11094295B2 |
Automated adjustment of head up display image in a vehicle
Devices, methods and computer program products that facilitate automated adjustment of size or configuration of head up display image in a vehicle. A device can include a memory and a processor that executes computer executable modules. The computer executable modules can include: a head up display that generates an image visible to a driver of a vehicle within an eye box, a detection module that determines position of the driver's eyes or head relative to position of the eye box, and an adjustment module that adjusts size or configuration of the image within the eye box in response to the determined driver's eye or head position. |
| US11094294B2 |
Movement based graphical user interface
A system or a method may be provided that may detect a movement or activity of a user via the user's mobile and/or wearable devices. The system may adjust the display interface based on the user's detected movement or activity. When a user is very active (biking or jogging), the user may have very limited amount of time or attention to interact with a display interface. The movement or activity of the user may be detected by a motion detection device installed on the mobile device or on the wearable device. When the user is active, the display interface may adjust to enlarge the information to make it easier for the user to view, read, or interact with. The system may also select and display important information, without other peripheral information (less important information) when the user is active. |
| US11094291B2 |
Method and device for detecting ambient light and terminal
A method and device for detecting ambient light on a terminal are provided. The method includes: switching, by a terminal comprising a display screen and light sensor arranged under the display screen, when detection of ambient light is requested, a display frame rate of the display screen from a first frame rate to a second frame rate, the first frame rate being greater than the second frame rate, detecting, by the light sensor, during a time interval where the second frame rate is applied, the ambient light that passes through a space gap between display units of the display screen to the light sensor, and obtaining, by the terminal, ambient brightness information based on the ambient light detected. |
| US11094290B2 |
Screen and electronic device
A screen includes a main body display module and multiple auxiliary display units. By dividing a lighting functional coordination area of a main body display module into a lighting sub-area and a coordination sub-area out of the lighting sub-area, and arranging auxiliary display units in the coordination sub-area, the light transmission of the lighting sub-area is no longer interfered by the peripheral auxiliary display units, and thus the lighting effect is improved. In addition, the display effect of the auxiliary display units disposed in the coordination sub-area in a working state can be matched with a display content of a main display area, so that the influence of the lighting functional coordination area on the overall display effect of a screen is reduced. |
| US11094289B2 |
Color correction apparatus, display apparatus, and color correction method
An adjustment is performed on input gradation values, and 1st-stage gradation values are obtained. When a color expressed by a set of the input gradation values is a single color of any one of R, G, and B, the 1st-stage gradation value is set to 0. Further, correction is performed for R, G, and B according to one-dimensional lookup tables, respectively, and correction is performed for W according to one-dimensional lookup tables. Further, a contribution amount of the gradation values obtained through correction of the former and the gradation values obtained through correction of the latter to output gradation values is changed according to a color expressed by a set of the 1st-stage gradation values. |
| US11094284B2 |
Rearranging columns and rows of two-dimensional image pixel data
An image processing device and image processing method that reduce the probability that the power consumption of two processing systems will be maximized simultaneously. Such image processing device includes an image processing circuit, a conversion circuit receiving a first pixel data array outputted from the image processing circuit and converting the first pixel data array into a second pixel data array by converting an arrangement of pieces of pixel data included in the first pixel data array pixel by pixel, the first pixel data array being an aggregate of a plurality of pieces of pixel data, the pieces of pixel data being pieces of data corresponding to a plurality of pixels, each of the pieces of pixel data having a plurality of bits, an aggregate of the pixels forming a pixel array, and a processing unit processing the second pixel data array outputted from the conversion circuit. |
| US11094281B2 |
Spliced display device, configuration method thereof, display server and control method thereof
A spliced display device and a configuration method thereof, and a display server and a control method thereof are provided. The configuration method may be applied to a spliced display device, and the spliced display device includes a plurality of displays spliced together in an array. The configuration method includes: receiving display control information sent by a display server in a preset protocol format, wherein the display control information at least includes position setting information; and configuring the plurality of displays according to the display control information. |
| US11094280B2 |
Level shifter and display device using the same
The present disclosure relates to a level shifter and a display device using the same, and the level shifter includes a first transistor configured to increase a voltage of an output signal, a second transistor configured to lower a voltage of the output signal, a first driver configured to vary a gate voltage of the first transistor in response to a first Vgs signal being varied within a transition time of the output signal, and a second driver configured to vary a gate voltage of the second transistor in response to a second Vgs signal being varied within a transition time of the output signal. |
| US11094278B2 |
Display apparatus including a substrate with first and second regions including respective first and second circuit portions with different dimensions
An area of a region arranged on one side of a display region in a direction in which scanning lines extend is reduced. A display apparatus has a scanning line driving circuit and a plurality of scanning lines. The scanning line driving circuit is provided in a region arranged along a side portion on the positive side in the X-axis direction in a display region of a substrate. The scanning line driving circuit includes a plurality of transfer circuits connected to the plurality of scanning lines, respectively. Among the plurality of transfer circuits, the shape of one transfer circuit is different from the shape of another transfer circuit arranged on the negative side of the one transfer circuit in the Y-axis direction. |
| US11094274B2 |
Circuit device, electro-optical device, and electronic apparatus
A circuit device includes a transfer gate, a charge compensation circuit, and a control circuit. The control circuit controls the charge compensation circuit. The charge compensation circuit discharges charge from an output node of the transfer gate when a voltage of an input signal to the transfer gate is in a first voltage range at a timing at which the transfer gate is turned off. The charge compensation circuit injects charge into the output node of the transfer gate when a voltage of the input signal to the transfer gate is in a second voltage range lower than that in the first voltage range at a timing at which the transfer gate is turned off. |
| US11094272B2 |
Display driver and semiconductor apparatus
A display driver according to the present invention includes a withstand voltage protection part that precharges an output node of a polarity changeover switch circuit that switches a polarity of a drive signal supplied to a display device from an electric potential of a positive polarity (a first electric potential to a third electric potential) to an electric potential of a negative polarity (the third electric potential to a second electric potential) or vice versa to the third electric potential immediately before the polarity switching. |
| US11094261B2 |
Pixel circuit, compensation assembly, display apparatus and driving method thereof
A pixel circuit includes a driving sub-circuit and a photosensitive detection circuit. The driving sub-circuit is coupled to a self-luminescent device. The driving sub-circuit is configured to drive the self-luminescent device to emit light. The photosensitive detection circuit is configured to detect a luminance of the self-luminescent device, and transmit an electrical signal for characterizing the luminance of the self-luminescent device to a signal readout terminal. |
| US11094259B2 |
Display device and driving method of the same
A display device includes a display panel includes a plurality of pixels driven by a first power voltage and a second power voltage. A display panel driving circuit is configured to receive image data from an external device, output a first voltage control signal for generating an analog supply voltage based on an on-pixel ratio (OPR) of the image data, and output a second voltage control signal for generating the first power voltage and the second power voltage. A DC-DC conversion circuit is configured to generate the analog supply voltage based on the first voltage control signal and generate the first power voltage and the second power voltage based on the second voltage control signal. |
| US11094255B2 |
Driver for LED display
A method, a digital driving circuit and a LED display where images to be displayed in successive frames are converted from an n-bit digital image to a (m+1)-bit digital image, where m |
| US11094254B2 |
Display device and method for driving same
The present invention discloses a current-driven display device employing an internal compensation scheme and capable of displaying a favorable image with no occurrence of a bright point not included in the original display content. A voltage Vg at a gate terminal of a drive transistor M1 is initialized in a pixel circuit 15 of an organic EL display device before a voltage of a data signal line Dj is written to a holding capacitor C1 via the drive transistor M1 in a diode-connected state. At this time, an initialization voltage Vini is supplied to the gate terminal via a first initialization transistor M4 and a threshold compensation transistor M3. In this manner, a path for initializing the gate terminal of the drive transistor M1 is formed by the first initialization transistor M4 and the threshold compensation transistor M3 connected in series to each other, thereby preventing a voltage reduction at the gate terminal due to leakage current in an off-state transistor. |
| US11094253B2 |
Pixel driving circuit, method for driving the same, array substrate and display device
A pixel driving circuit, array substrate, display device and method for driving the pixel driving circuit are provided, the circuit includes: a control terminal and a first terminal of a driving switch circuit are respectively coupled to a first terminal of a data input switch circuit and an anode of a light-emitting device, and two terminals of a storage capacitor are respectively coupled to the control terminal of the driving switch circuit and the anode of the light-emitting device, two terminals of an intrinsic capacitor are respectively coupled to a cathode and the anode of the light-emitting device, a first terminal and a second terminal of a reset switch circuit are respectively coupled to the anode and the cathode of the light-emitting device, a capacitance of the intrinsic capacitor is greater than or equal to a preset multiple of a capacitance of the storage capacitor. |
| US11094251B2 |
Coding for avoiding motion artifacts
A method includes representing dots of an image to be displayed within a field by a digital image code. The field is divided into sub-fields which are further divided into a first and second time interval which respectively comprise a first and a second number of equally long time slots. Time slots are assigned to each bit of the digital image code according to each bit's significance. Successive time slots of the first time interval are assigned to one of the bits of the image code and successive time slots of the second time interval are assigned to a different one of the bits of the image code. Within the duration of at least one sub-field, each rows is selected twice for respectively writing a first bit of the image code during the first time interval and writing a second bit of the image code during the second time interval. |
| US11094245B2 |
Shift register, driving method thereof, gate driving circuit and display device
Embodiments of the present disclosure propose a shift register, a driving method thereof, a gate driving circuit, and a display device. The shift register includes: an inputting sub-circuit, an outputting sub-circuit, a resetting sub-circuit, a pulling-down sub-circuit, a pulling-down controlling sub-circuit, and a voltage regulating sub-circuit. The voltage regulating sub-circuit is coupled to a pulling-down node, a pulling-down controlling node, a second clock signal terminal, a third clock signal terminal, a first voltage signal terminal and a second voltage signal terminal, and is configured to regulate a voltage at the pulling-down controlling node based on a first voltage signal from the first voltage signal terminal and a second voltage signal from the second voltage signal terminal, under a control of the second clock signal from the second clock signal terminal, a third clock signal from the third clock signal terminal, and the voltage at the pulling-down node. |
| US11094240B1 |
Device and method for image processing in display driver
A display driver comprises image processing circuitry and driver circuitry. The image processing circuitry is configured to receive spatial distribution information of a physical quantity related to a display panel. The image processing circuitry is further configured to generate output voltage data by processing input pixel data associated with subpixels of the pixel. The drive circuitry is configured to drive the display panel based on the output voltage data. |
| US11094236B1 |
Dynamic modification of digital signage based on device edge analytics and engagement
Techniques and systems are described for dynamic modification of digital signage based on device edge analytics and engagement. For instance, the described techniques enable content output of a signage device to be dynamically modified based on different environmental conditions, such as human behaviors indicating likely interest in an instance and/or type of content. Further, different types of sensor data are utilized to automatically detect such behaviors, such as via sensor mounted to and/or adjacent a signage device. |
| US11094231B2 |
Metal poster with relief printed frame
A metal poster is formed with an integral frame which is relief printed on the obverse face of a sheet metal plate with layers of UV curable inks. Image indicia imprinted on the plate is surrounded by the relief printed frame. The ink layers extend into selvage areas of the plate. The selvage areas are folded over to the rear face of the sheet metal plate to provide the frame with relief printed rounded peripheral edges. |
| US11094229B2 |
Liquid crystal panel, display, and exhibition device
A liquid crystal panel and a liquid crystal display are disclosed. The panel includes an array substrate, a filter substrate, and a liquid crystal layer. The filter substrate includes a filter sheet. The liquid crystal panel is partitioned into a transparent section and a color section, and the filter sheet includes a transparent photoresist corresponding to the transparent section, and a color photoresist corresponding to the color section. An exhibition device for showcasing products is also disclosed. The exhibition device includes a showcase, a lamp inside the showcase, and at least an above-described liquid crystal display and panel framed in one of the showcase's side wall. The lamp provides illumination to the transparent section and the showcased products may be viewed through the transparent section. The transparent section may also show static messages describing the showcased products. The color section presents dynamic messages demonstrating the showcased products. |
| US11094228B2 |
Information processing device, information processing method, and recording medium
To provide an information processing device, an information processing method, and a recording medium capable of appropriately presenting necessary information while maintaining scenery.An information processing device including: a communication unit configured to receive sensor data detected by a sensor for grasping a surrounding situation; and a control unit configured to perform control to generate a control signal for displaying an image including appropriate information on a display unit installed around the sensor, in accordance with at least one of an attribute of a user, a situation of the user, or an environment detected from the sensor data, generate a control signal for displaying a blending image that blends into surroundings of the display unit on the display unit in a case where information presentation is determined to be unnecessary, and transmit the control signal to the display unit via the communication unit. |
| US11094224B2 |
Separable identification assembly
An identification assembly is provided having a tag assembly and a bracket assembly, the tag assembly comprising a front plate rotatably fixed to a tag body. In accordance with embodiments, the front plate has two identification surfaces and the tag body has one identification surface, and the tag assembly is configured to removably receive the bracket assembly. |
| US11094219B2 |
Portable computing device having a color detection mode and a game mode for learning colors
A system and method for assisted-learning with a portable computing device that includes a color detection mode and a game mode. |
| US11094214B1 |
Online-based microcourses for learning core subjects
An online educational system for learning the core subjects of mathematics, social science, the sciences and English in a supportive curriculum via a universal learning design model is provided. The system breaks each subject down into sub-modules and bundles the courses for the sub-module, allowing a user to logically progress therethrough, although the user can select courses in any desired order. Each course is presented in visual, audio-visual or audio only fashion and can include sign language and text to speech functions. A user can take electronic notes within a course, can user portions of a course to create a POWERPOINT-type presentation for others, and can e-mail a teacher for questions with content specific information inserted into the e-mail to the teacher to provide specific subject matter content. |
| US11094207B2 |
Cockpit display of traffic information (CDTI) assisted visual separation employing a vertical situation display
Systems and methods directed to improvements in the presentation of CAVS procedures on an aircraft display system over what is conventionally available are provided. The provided systems and methods employ a vertical situation display (VSD), thereby presenting additional relevant visual approach information, such as a vertical distance between the ownship and the target aircraft, descent rates of the ownship and the target and an alerting function for the user-selected CAVS range. The provided systems and methods also capably receive and process user selections of target aircraft from both the lateral display and the VSD. |
| US11094204B2 |
Unmanned aerial vehicle flight path efficiency through aerodynamic drafting
A method includes: retrieving an initial flight path for a first unmanned aerial vehicle (UAV), the initial flight path being from a geographical point A to a geographical point B; generating a projected initial energy consumption of the first UAV for completion of a flight along the initial flight path; retrieving a flight path of a second UAV; generating a projected revised energy consumption of the first UAV for completion of a flight along an altered flight path, the altered flight path being a flight path from point A to point B where the first UAV aerodynamically drafts the second UAV for at least a portion of the altered flight path; comparing the projected revised energy consumption to the projected initial energy consumption to determine which of the projected revised energy consumption and the projected initial energy consumption is lower. |
| US11094202B2 |
Systems and methods for geo-fencing device communications
Systems and methods for UAV safety are provided. An authentication system may be used to confirm UAV and/or user identity and provide secured communications between users and UAVs. The UAVs may operate in accordance with a set of flight regulations. The set of flight regulations may be associated with a geo-fencing device in the vicinity of the UAV. |
| US11094198B2 |
Lane determination method, device and storage medium
This application discloses a lane determining method performed at a computing device. The computing device obtains image information of a road surface image collected by a vehicle; identifies first lane information of at least one first lane of the road surface from the image information, the first lane information including a location relationship between a travelling lane in which the vehicle is located in the road surface and the at least one first lane, and a feature of the first lane; performs feature matching between the feature of the at least one first lane and a feature of at least one second lane in a map in which the road surface is located, the feature of the at least one second lane obtained from the map; and determines a target lane of the vehicle in the map corresponding to the travelling lane in the map in accordance with the feature matching result. |
| US11094195B2 |
Dynamic predictive systems for vehicle traffic management
Methods, systems and computer readable media are provided for traffic management between a first vehicle and a second vehicle. A navigation system of the second vehicle may receive position and route information describing a route that the first vehicle is projected to follow. The navigation system of the second vehicle may determine a geographical area, wherein the geographical area encompasses locations determined to be reachable by the second vehicle within a specified time interval. The navigation system of the second vehicle may generate a warning when the route of the first vehicle and the geographical area of the second vehicle intersect with each other. |
| US11094194B2 |
Operation management system and operation management program
Operation management systems, methods, and programs obtain a travel plan including a scheduled point and a scheduled time associated with the scheduled point, and obtain a travel track record including a travel point of a vehicle and a travel time associated with the travel point. The systems, methods, and programs obtain, when a delay has occurred in the travel plan, a cause of the delay based on the travel track record and the travel plan, and output the obtained cause of the delay. |
| US11094193B2 |
Real-time vehicle-based data gathering
A real-time vehicle-based data gathering system includes: a vehicle management server to transmit a request to a plurality of vehicles, the request including geolocation information and microcode, wherein a respective vehicle of the plurality of vehicles is configured to execute the microcode when in a location corresponding to the geolocation information, the microcode to cause the respective vehicle to: execute a data gathering task using sensors in the respective vehicle, and transmit a response to the vehicle management server when the data gathering task is complete; and a data stream processor to receive responses from the plurality of vehicles, the responses including real-time sensed data acquired from the plurality of vehicles. |
| US11094187B2 |
Sum stream for actual states and control signals of a distributed control system
Sensors of a control system transmit detected cyclical actual states of a technical industrial process to a common central unit via a first protected connection of a first open communication network once within a specified time window. The central unit transmits cyclical control signals commensurate with the actual states to multiple actuators via a second protected connection of a second open communication network once within the specified time window. Each sensor supplies the actual state detected by the sensor to the first open communication network within a respective transmitter-side sub-region within the time window. The central unit receives the transmitted actual states within a respective corresponding receiver-side sub-region within the time window. The transmitter-side sub-regions of the sensors are specified such that the receiver-side sub-regions are disjointed from one another. |
| US11094185B2 |
Community security monitoring and control
Systems, methods, and software for monitoring and controlling a security system for a structure are provided herein. An exemplary method may include receiving sensor data from at least one first peripheral, the sensor data associated with at least one of activity inside and activity outside of a structure; determining a critical event based in part on the sensor data; creating an alert based in part on the critical event; getting user preferences associated with at least one of a user and a base unit; determining a response based in part on the alert and user preferences; and activating at least one of a second peripheral and a service based in part on the response. |
| US11094184B2 |
Forgetting-to-carry prevention assistance method, terminal device, and forgetting-to-carry prevention assistance system
A forgetting-to-carry prevention assistance method assists, in a terminal device, a user in preventing forgetting to carry a personal item. The forgetting-to-carry prevention assistance method includes acquiring a destination for the user; detecting the personal item that exists around the user; and in a case where the personal item associated with a category of the destination is not detected, notifying information on the personal item that is not detected. |
| US11094183B1 |
Rex cooling master
The Rex Cooling Master is a multi-components advanced technology device Created to eliminate vehicular heatstroke or any other potential death related to intense temperatures in vehicles.The cooling Master uses its multiple components in effort to alter the vehicle's climate system, it keeps a steady cooling temperature and uses other features to ensure the safety of the passengers, especially for children, and pets. The device is composed in five (5) components:A) Base: Connected to the vehicle, and receives info-signals from other components and carries-out commands. B) Sensors & cameras: scans for sound waves and visual movements, then sends the data to the base. C) Portable controller: receives notifications and sends commands to the base. D) Screen monitor: home emergency controller, sends commands to the base. E) Wireless connection: ensures permanent connectivity between components and sends commands to the base. |
| US11094177B2 |
Haptic garment and method thereof
A haptic garment, such as a haptic glove, is provided. The haptic glove is operative to measure haptic properties of a skin of a user wearing the haptic glove, using haptic sensors, to transmit a representation of the measured haptic properties to another haptic garment, e.g., another haptic glove worn by another user, to receive a representation of measured haptic properties of a skin of the other user from the other haptic glove, and, in response to detecting contact between the haptic glove and the other haptic glove, to render the received representation of the haptic properties of the skin of the other user within an area of contact between the haptic glove and the other haptic glove using haptic actuators. The representations of measured haptic properties are exchanged via communications modules comprised in the haptic gloves. |
| US11094173B1 |
Baccarat gaming methods and systems
Systems and methods for providing a wagering game associated with the game of Baccarat which includes generating game outcomes for one to N games in a single game session. |
| US11094171B2 |
AI wager odds adjuster
A method and system for using artificial intelligence (AI) to assess and adjust the betting odds for live game wagers before they are presented to users based correlations between various parameters and user betting behavior, and to adjust the betting odds while the betting window is open based on how users are currently betting compared to expected user betting behavior. |
| US11094170B2 |
Gaming machine using multiple triggers to determine an award from a subset of displayed awards
A gaming system includes at least one input device adapted to receive a physical item associated with a monetary value that establishes a credit balance, an input indicative of a wager drawn on the credit balance for a wagering game, and a cashout input that initiates a payout from the credit balance. In response to a wager input, a wagering game is initiated that includes the spinning and stopping of a set of bonus reels through a plurality of bonus spins populating a bonus array with bonus symbols. The bonus reels comprise a combination of symbols reducing display processing requirements and improve mapping random numbers to displayed symbols for display during bonus spins having reduced durations. When completed, an award is determined based according to values associated with less than all of the bonus symbols displayed in a bonus outcome array. |
| US11094169B2 |
Electronic gaming machine and method for providing a plurality of game outcomes and evaluating patterns of game outcomes to provide additional awards
An electronic gaming machine includes a processor configured to control a display device to display a matrix of game positions, initiate a plurality of games, and control the display device to display each game of the plurality of games in an associated game position of the matrix of game positions. The processor is also configured to determine an outcome of each game, where each outcome is a qualifying outcome or a non-qualifying outcome, as well as to evaluate the matrix of game positions to determine whether a qualifying pattern is formed in the matrix by at least two qualifying outcomes. In response to the qualifying pattern being formed, the processor is also configured to provide an award to a player of the electronic gaming machine. Each outcome may be individually evaluated to provide one or more additional awards to the player as well. |
| US11094168B2 |
Fraud detection system in a casino
A fraud detection system which detects fraud in a game of performing collection and redemption of chips in accordance with a win or lose result includes a camera which captures an image of chips contained in a chip tray of a dealer, an image analyzing apparatus which analyses the image captured by the camera to detect an amount of the chips contained in the chip tray, a card distribution device which determines a win or lose result of a game, and a control device which compares the win or lose result of the game and the amount of the chips contained in the chip tray before and after collection and redemption of the chips to detect fraud. |
| US11094166B2 |
System, device, and method to detect unusual activity in electronic records
A system can be capable of receiving and storing electronic records associated with adjustments to an electronic resort wallet from a gaming device and/or other funds transfers using another device. Where the electronic record includes information such as an identifier of the gaming device, a player ID, a timestamp, a transaction amount, and a transaction type. The system may further be capable of using rules to group related electronic records into a set of related electronic records. The system may also be capable of reviewing a set of related electronic records to determine if the related records indicate unusual activity, and in response to detecting unusual activity, causing the system to trigger an alert. |
| US11094161B2 |
System and method for cashless exchange at table games
A system includes a memory storing player positioning information associated with a table gaming environment and a smart table configured to use RFID-enabled chips and RFID sensors configured to detect the presence of RFID-enabled chips, including a dealer scratchpad area. The system also includes a processor configured to (a) detect presence of a player at a player position, (b) receive, from a player computing device, a request to buy into the wagering game for a buy-in value using a funds source from a digital wallet accessed from the player computing device, (c) display, to a dealer, a confirmation that the player is entitled to receive the buy-in value, (d) detect, from the at least one RFID sensor, a chip value within the scratchpad area, (e) compare the chip value to the buy-in value, and (f) display, to the dealer, a confirmation that the chip value matches the buy-in value. |
| US11094158B2 |
Mobile system for dispensing medication
The subject technology provides at least a method of medication management. The subject technology receives, at a mobile device via a network interface, information regarding a medication order from a server. The subject technology sends, with the mobile device via a short range wireless interface, an indication of the medication order to a medication dispensing device, the indication causing the medication dispensing device to provide access to a medication corresponding to the medication order. Further, the subject technology sends, with the mobile device via the network interface, dispense information to the server, the dispense information corresponding to the medication provided by the medication dispensing device. |
| US11094154B2 |
System and method for integrating and adapting security control systems
A system for controlling access to one or more enclosed areas comprises at least one access card reader and controller powered via a Power-over-Ethernet (PoE) interface, each access card reader and controller being capable of controlling access through a particular entrance to a particular enclosed area and an access control server in communication with the at least one access card reader and controller, the access control server being capable of controlling the operation of the at least one access card reader and controller, and a signal converter disposed between the access card reader and the access control server. In a network mode of operation, the access control server is configured to perform authentication of a card identifier (ID) received from the at least one access card reader and controller and to signal the at least one access card reader and controller to unlock a door at the particular entrance to the particular enclosed area when the access control server has successfully authenticated the received card ID. In a standalone mode of operation, the at least one access card reader and controller is configured to perform local authentication of a received card ID independently of the access control server and to unlock a door at the particular entrance to the particular enclosed area when the at least one access card reader and controller has successfully authenticated the received card ID. |
| US11094152B2 |
System and method for applying over-locks without requiring unlock codes
The disclosure generally relates to a system and method for managing distributed encrypted combination over-locks from a remote location. In an exemplary embodiment, the invention is a distributed management system for self-storage facilities that allow for vacant units to be secured with over-locks without requiring unlock codes, and which allow the over-locks to be removed by customers without human or manual intervention from the self-storage facility, where an API is used to facilitate communications between a lock management system and a property management system. |
| US11094149B2 |
Locking and unlocking system, server used for locking and unlocking system and method for executing locking and unlocking system
A locking and unlocking system includes a portable terminal and a server. The portable terminal includes a first reception unit configured to receive authentication information used for locking and unlocking of a vehicle or a facility from the server, and a first transmission unit configured to transmit a signal requesting the locking or the unlocking to a device provided in the vehicle or the facility. The signal includes the authentication information. The server includes an acquisition unit configured to acquire schedule information including a date when the vehicle or the facility is reserved and first identification information of a user, from another server configured to perform schedule management, and a second transmission unit configured to transmit the authentication information to the portable terminal of the user, based on the schedule information. |
| US11094143B2 |
Trailer mode determination device and method using gradient
A trailer mode determination device and method using a gradient is provided that a trailer mode determination method includes: calculating longitudinal acceleration-based gradient of a vehicle and determining whether a calculated value is valid; calculating clutch torque-based gradient and determining whether the calculated value is valid; determining whether the longitudinal acceleration-based gradient is greater than or equal to a predetermined reference gradient; determining whether vehicle speed and vehicle speed change amount are greater than or equal to predetermined values; calculating a difference between the longitudinal acceleration-based gradient (d1) and the clutch torque-based gradient (d2) when the vehicle speed and vehicle speed change amount are greater than or equal to a predetermined value; determining whether gradient difference (d1−d2) exceeds a predetermined normal range; and determining a trailer is mounted and a trailer mode is switch on when the gradient difference (d1−d2) exceeds the normal range. |
| US11094130B2 |
Method, an apparatus and a computer program product for video encoding and video decoding
The embodiments relate to a method, and a technical equipment for implementing the method. The method comprises generating a bitstream defining a presentation, the presentation comprising an omnidirectional visual media content; and indicating in the bitstream a definition for an external media to be overlaid on the omnidirectional visual media content during rendering; wherein the definition comprises at least an overlay placement information for the external media on the omnidirectional visual media content. The embodiments also relate to a method and technical equipment for decoding the bitstream. |
| US11094128B2 |
Utilizing virtual reality and hi-definition camera technology to allow passengers to experience flight path
Disclosed embodiments are directed at devices, methods, and systems for rendering a customizable 3D virtual environment of an outside world surrounding an airplane. The 3D virtual environment is rendered on a personal electronic device (e.g., a VR headset) and is composed from high-resolution image data received from a plurality of cameras mounted externally to the airplane. A seatback computer coupled to the personal electronic device receives data corresponding to the 3D virtual environment of the outside world from the airplane's compute server, which performs the tasks of analyzing the high-resolution image data to compose the 3D virtual environment. Further, the 3D virtual environment can be customized to a passenger's preferences based on gesture-based interactions of a passenger with the 3D virtual environment. The gesture-based interactions of a passenger are received by a sensor coupled to the personal electronic device. |
| US11094127B2 |
Systems and methods for presenting perspective views of augmented reality virtual object
Examples of the disclosure describe systems and methods for sharing perspective views of virtual content. In an example method, a virtual object is presented, via a display, to a first user. A first perspective view, based on a position of the virtual object and a first position of the first user, of the virtual object is determined. The virtual object is presented, via a display, to a second user, wherein the virtual object is presented to the second user according to the first perspective view. An input is received from the first user. A second perspective view, based on the input from the first user, of the virtual object is determined. The virtual object is presented, via a display, to the second user, wherein presenting the virtual object to the second user comprises presenting a transition from the first perspective view to the second perspective view. |
| US11094123B2 |
Visual localisation
In an embodiment of the invention there is provided a method of visual localization, comprising: generating a plurality of virtual views, wherein each of the virtual views is associated with a location; obtaining a query image; determining the location where the query image was obtained on the basis of a comparison of the query image with said virtual views. |
| US11094118B2 |
Device panel capabilities and spatial relationships
Aspects of the disclosure provide a system having a memory area associated with a computing device and a processor. The processor executes to classify device panel descriptors and location descriptors according to associated device instances. The processor generates device panel objects using the classified device panel descriptors and location descriptors. A schema comprising device panel locations and adjacency relationship information is populated for the computing device based on the generated device panel objects. The processor provides the populated schema as dynamic device properties to one or more operations executing on the computing device. |
| US11094115B2 |
Generating clothing patterns of garment using bounding volumes of body parts
A method and a device for displaying clothing patterns determine attributes of bounding volumes for each body part, to which a body type and an orientation of a 3D avatar are reflected, based on locations of feature points extracted from data of the 3D avatar, determine initial locations of the clothing patterns by placing arrangement points on the bounding volumes depending on the attributes of the bounding volumes for each body part, and drape the clothing patterns to the 3D avatar depending on the initial locations. |
| US11094114B2 |
Satellite SAR artifact suppression for enhanced three-dimensional feature extraction, change detection, and visualizations
Systems and methods for satellite Synthetic Aperture Radar (SAR) artifact suppression for enhanced three-dimensional feature extraction, change detection, and/or visualizations are described. In some aspects, the described systems and methods include a method for suppressing artifacts from complex SAR data associated with a scene. In some aspects, the described systems and methods include a method for creating a photo-realistic 3D model of a scene based on complex SAR data associated with a scene. In some aspects, the described systems and methods include a method for identifying three-dimensional (3D) features and changes in SAR imagery. |
| US11094108B2 |
Three dimensional scene inpainting using stereo extraction
Systems and methods for rendering three-dimensional (3D) scenes having improved visual characteristics from a pair of 2D images having different viewpoints. The 3D scene is created by obtaining a first two-dimensional (2D) image of a scene object from a first viewpoint, obtaining a second 2D image of the scene object from a second viewpoint that is different than the first viewpoint, creating a depth map from the first and second 2D images, creating a 3D scene from the depth map and the first and second 2D images, detecting regions of the initial 3D scene with incomplete image information, reconstructing the detected regions of the 3D scene, determining replacement information and modify the reconstructed regions, and rendering the 3D scene with the modified reconstructed regions from a plurality of viewpoints. |
| US11094106B2 |
Simulation system, processing method, and information storage medium for changing a display object in response to a movement of a field of view
A simulation system includes a processor including hardware. The processor performs: a virtual space setting process of setting a virtual space in which a plurality of objects are arranged; a virtual camera control process of controlling a virtual camera corresponding to a point-of-view of a user wearing a head mounted display; and a display process of generating an image as viewed from the virtual camera in the virtual space as a display image on the head mounted display. In the virtual space setting process, the processor arranges at least one information display object in a line-of-sight direction of the user, and in the display process, when it is determined that a given change condition is satisfied by a change in the point-of-view of the user, the processor performs a change process of a display mode of the information display object. |
| US11094104B2 |
Information processing device, information processing method and non-transitory computer readable medium
An information processing device has a computation unit for determining an optimal solution of an external force that minimizes a difference between a surface image of an elastic body captured from at least one direction, and a rendering image as observed from the direction which is generated from a three-dimensional model of the elastic body elastically deformed by an unobserved external force. |
| US11094102B2 |
Write out stage generated bounding volumes
Systems, apparatuses and methods may provide for technology that optimizes tiled rendering for workloads in a graphics pipeline including tessellation and use of a geometry shader. More particularly, systems, apparatuses and methods may provide a way to generate, by a write out fixed-function stage, one or more bounding volumes based on geometry data, as inputs to one or more stages of the graphics pipeline. The systems, apparatuses and methods may compute multiple bounding volumes in parallel, and improve the gamer experience, and enable photorealistic renderings at full speed, (e.g., such as human skin and facial expressions) that render three-dimensional (3D) action more realistically. |
| US11094101B2 |
Integration of 3rd party geometry for visualization of large data sets system and method
A system provides the ability to import large engineering 3D models from a primary 3D rendering software into a secondary 3D rendering software that does not have the tools of the resources to render the larger 3D model on its own. The system uses a plugin to combine 3D data from the two software sources, and then return the combined 3D data to the secondary 3D rendering software. Components of the system can be remote or cloud based, and the system facilitates video streaming of 3D rendered models that can be manipulated on any computer capable of supporting a video stream. |
| US11094097B2 |
Information processing apparatus and information processing method
The present technique relates to an information processing apparatus, an information processing method, and a program that can make an improvement in terms of communication regarding a plurality of users viewing the same content. Data of content is acquired, and a first visual field image corresponding to a visual field of a first user is cut out from a content image based on the data of the content. In addition, visual field information representing a visual field of a second user viewing the content image is acquired. Furthermore, in a display apparatus, the first visual field image is displayed, and the visual field of the second user is displayed based on the visual field information of the second user. The present technique can be applied to, for example, a case where a plurality users views content, such as a spherical image and a free viewpoint image. |
| US11094086B2 |
Method and apparatus for coding image data
A method for coding an image comprising a plurality of pixels. For at least one pixel of the plurality, a differential value is calculated from a value of the pixel and at least one surrounding pixel value, which occurs in the proximity of the pixel in the image. A quantizer is selected from a plurality of quantizers, and the differential value is assigned to a quantizer value by means of the selected quantizer. The quantizer value is assigned to a bit sequence by means of a coding. Thereby, the coding is based on an averaging of incidences of values the individual quantizers of the plurality can assume for pixel value differences respectively. Furthermore, a method is provided for transmitting an image comprising of a plurality of pixels to a receiver, an apparatus for coding an image comprising of a plurality of pixels and a system for transmitting image data. |
| US11094084B2 |
Image processing method
An image processing method includes receiving an image source, and detecting whether the image source is a high dynamic range (HDR) image. If the image source is the HDR image, reading a first image adjustment value, and performing color adjustment to the image source according to the first image adjustment value. |
| US11094075B1 |
Systems and methods utilizing a machine learning model for generating defocus blur effects
In one embodiment, a system may access a training sample that includes training images and corresponding training depth maps of a scene, with the training images being associated with different predetermined viewpoints of the scene. The system may generate elemental images of the scene by processing the training images and the training depth maps using a machine-learning model. The elemental images are associated with more viewpoints of the scene than the predetermined viewpoints associated with the training images. The system may update the machine-learning model based on a comparison between the generated elemental images of the scene and target elemental images that are each associated with a predetermined viewpoint. The updated machine-learning model is configured to generate elemental images of a scene of interest based on input images and corresponding depth maps of the scene of interest from different viewpoints. |
| US11094074B2 |
Identification of transparent objects from image discrepancies
A computing system is provided. The computing system includes a visible light camera, a thermal camera, and a processor with associated storage. The processor is configured to execute instructions stored in the storage to receive, from the visible light camera, a visible light image for a frame of a scene and receive, from the thermal camera, a thermal image for the frame of the scene. The processor is configured to detect image discrepancies between the visible light image and the thermal image and, based on the detected image discrepancies, determine a presence of a transparent object in the scene. The processor is configured to, based on the detected image discrepancies, output an identification of at least one location in the scene that is associated with the transparent object. |
| US11094071B1 |
Efficient parallel computing method for box filter
An efficient parallel computing method for a box filter, includes: step 1, with respect to a given degree of parallelism N and a radius r of the filter kernel, establishing a first architecture provided without an extra register and a second architecture provided with the extra register; step 2, building a first adder tree for the first architecture and a second adder tree for the second architecture, respectively; step 3, searching the first adder tree and the second adder tree from top to bottom, calculating the pixel average corresponding to each filter kernel by using the first adder tree and the second adder tree, respectively, and counting resources required to be consumed by the first architecture and the second architecture, respectively; and, step 4, selecting one architecture consuming a relatively small resources from the first architecture and the second architecture for computing the box filter. |
| US11094070B2 |
Visual multi-object tracking based on multi-Bernoulli filter with YOLOv3 detection
The disclosure discloses a visual multi-object tracking based on multi-Bernoulli filter with YOLOv3 detection, belonging to the fields of machine vision and intelligent information processing. The disclosure introduces a YOLOv3 detection technology under a multiple Bernoulli filtering framework. Objects are described by using anti-interference convolution features, and detection results and tracking results are interactively fused to realize accurate estimation of video multi-object states with unknown and time-varying number. In a tracking process, matched detection boxes are combined with object tracks and object templates to determine new objects and re-recognize occluded objects in real time. Meanwhile, under the consideration of identity information of detected objects and estimated objects, identity recognition and track tracking of the objects are realized, so that the tracking accuracy of the occluded objects can be effectively improved, and track fragments are reduced. Experiments show that the disclosure has good tracking effect and robustness, and can widely meet the actual design requirements of systems such as intelligent video monitoring, human-machine interaction and intelligent traffic control. |
| US11094066B2 |
System and method for extracting a region of interest from volume data
The present disclosure relates to a system and method for extracting a region of interest. Image data in a first sectional plane may be acquired. The image data in the first sectional plane may include at least one first slice image and one second slice image. A first region of interest (ROI) in the first slice image may be determined. A second ROI in the second slice image may be determined. A first volume of interest (VOI) may be determined based on the first ROI, the second ROI, and characteristic information of the image data in the first sectional plane. |
| US11094059B2 |
Vulnerable plaque identification method, application server thereof, and computer readable medium
The present disclosure publishes a vulnerable plaque identification method. The method includes: receiving an angiocarpy image sent by a terminal device; transforming the angiocarpy image in an original Cartesian coordinate system into a polar coordinate system to form a polarization image; constructing a faster RCNN architecture and accomplishing a training; inputting the polarization image into the faster RCNN architecture accomplished the training to identify the polarization image, and outputting the image with the marked vulnerable plaques; feed backing the image with the marked vulnerable plaques to the terminal device. The present disclosure also publishes an application server and a computer readable medium. The vulnerable plaque identification method, the application server, and the computer readable medium can quickly and correctly conform the position of the vulnerable plaque. |
| US11094058B2 |
Systems and method for computer-aided phenotyping (CAP) using radiologic images
Systems and methods for analyzing pathologies utilizing quantitative imaging are presented herein. Advantageously, the systems and methods of the present disclosure utilize a hierarchical analytics framework that identifies and quantify biological properties/analytes from imaging data and then identifies and characterizes one or more pathologies based on the quantified biological properties/analytes. This hierarchical approach of using imaging to examine underlying biology as an intermediary to assessing pathology provides many analytic and processing advantages over systems and methods that are configured to directly determine and characterize pathology from underlying imaging data. |
| US11094056B2 |
Defect inspection method for sensor package structure
A defect inspection method for a sensor package structure includes: using an image capture device to separately focus on and take pictures of at least three to-be-inspected regions of the sensor package structure along a height direction, so as to respectively obtain a defect image from one of the to-be-inspected regions, wherein the defect images are aligned with each other along the height direction and have different grayscale values; determining the defect image having a maximum grayscale value as a reference defect image, and defining any of the remaining defect images as a to-be-confirmed defect image; multiplying the maximum grayscale value by a predetermined grayscale ratio to obtain a predicted grayscale value, and confirming whether a difference between the to-be-confirmed and predicted grayscale values falls within an error range. |
| US11094055B2 |
Anomaly detection system
An image analysis system including an image gathering unit that gathers a high-altitude image having multiple channels, an image analysis unit that segments the high-altitude image into a plurality of equally size tiles and determines an index value based on at least one channel of the image where the image analysis unit identifies areas containing anomalies in each image. |
| US11094054B2 |
Inspection apparatus, inspection system, and inspection method
An inspection apparatus includes a reading device and a processor. The reading device is configured to read printed matter with an image that is printed on a printing medium based on a source image to generate a read image. The processor is configured to generate a reference image based on the source image, determine whether an inspection is to be executed based on a size of the source image and a size of the printing medium, and compare the reference image with the read image to inspect quality of the printed matter in response to a determination that the inspection is to be executed. |
| US11094043B2 |
Generation of high dynamic range visual media
Devices, systems and methods for generating high dynamic range images and video from a set of low dynamic range images and video using convolution neural networks (CNNs) are described. One exemplary method for generating high dynamic range visual media includes generating, using a first CNN to merge a first set of images having a first dynamic range, a final image having a second dynamic range that is greater than the first dynamic range. Another exemplary method for generating training data includes generating sets of static and dynamic images having a first dynamic range, generating, based on a weighted sum of the set of static images, a set of ground truth images having a second dynamic range greater than the first dynamic range, and replacing at least one of the set of dynamic images with an image from the set of static images to generate a set of training images. |
| US11094039B1 |
Fusion-adaptive noise reduction
Devices, methods, and computer-readable media describing an adaptive approach for image selection, fusion, and noise reduction, e.g., to generate low noise and high dynamic range (HDR) images with improved motion freezing in a variety of capturing conditions. An incoming image stream may be obtained from an image capture device, wherein the image stream comprises a variety of differently-exposed captures, e.g., EV0 images, EV− images, EV+ images. When a capture request is received, a set of rules may be used to evaluate one or more capture conditions associated with the images from the incoming image stream and determine which two or more images to select for a fusion operation. The fusion operation may be designed to adaptively fuse the selected images, e.g., in a fashion that is determined to be optimal from a noise variance minimization standpoint. A fusion-adaptive noise reduction process may further be performed on the resultant fused image. |
| US11094038B1 |
Variable scaling ratio systems and methods
An electronic device may include an electronic display to display an image based on scaled image data and variable scaling circuitry to generate the scaled image data. Generating the scaled image data may include receiving input pixel values in a first resolution and determining multiple tap point locations based on a scaling ratio to be applied to the input pixel values. Generating the scaled image data may also include determining weighting coefficients based on a scaling curve and the tap point locations, and weighting the input pixel values based on the weighting coefficients. The variable scaling circuitry may generate the scaled image data at a second resolution based on the aggregation of the weighted input pixel values. |
| US11094037B2 |
Semiconductor device, image processing system, image processing method and computer readable storage medium
A semiconductor device includes an image data acquisition circuit which acquires a plurality of first captured image data and a plurality of second captured image data at a first time and a second time, an adjustment region determination circuit which detects a target object from the plurality of first captured image data, and determines an adjustment region by estimating a position of the target object at the second time, a color adjustment circuit configured to determine a color adjustment gain based on the adjustment region, and perform color balance adjustment processing on the plurality of second captured image data based on the color adjustment gain, and an image synthesis circuit configured to synthesize the plurality of second captured image data so that overlapping regions included in a plurality of images of the plurality of second captured image data overlap each other. |
| US11094036B2 |
Task execution on a graphics processor using indirect argument buffers
The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processer in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processer in response to passing the data structure to the second programming interface command. |
| US11094032B2 |
Out of order wave slot release for a terminated wave
Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit. |
| US11094031B2 |
GPU resource usage display and dynamic GPU resource allocation in a networked virtualization system
An architecture for implementing a mechanism for displaying GPU resource usage and dynamically allocating GPU resources in a networked virtualization system is provided. The mechanism compares an initial allocation of GPU resources to virtual machines supported by one or more nodes of the networked virtualization system to a current GPU resource usage by the virtual machines. Based at least in part on the comparison and workloads processed by the virtual machines, the mechanism may reallocate GPU resources to one or more of the virtual machines. A virtual machine is reassigned to a different vGPU profile if reassignment is likely to achieve a more efficient allocation of GPU resources to the virtual machine. A user interface indicating GPU resource usage relative to GPU resource allocation may also be generated and displayed. |
| US11094025B2 |
Systems and methods for processing recorded data for storage using computer-aided dispatch information
Computer-implemented methods and systems for processing recorded data for storage is provided. An auditable device, such as a digital video camera, stores a set of recorded data. The auditable device also stores auditable event entries that represent auditable events detected by the auditable device. One type of auditable event is the receipt of information from a computer-aided dispatch (CAD) system that indicates an event. The auditable device marks at least one subset of the set of recorded data based on the auditable event entries, and uploads the marked at least one subset of the set of recorded data to an evidence management system. |
| US11094023B2 |
Controlling access to a vault server in a multitenant environment
A computer-implemented method includes: receiving, by a computing device, a vault access request for vault credentials stored by a vault server; verifying, by the computing device, whether a source of the vault access request originated from a multitenant application server; preventing, by the computing device, access to the vault server and the vault credentials when the source of the vault access request has not been verified as originating from the multitenant application server; obtaining, by the computing device, vault credentials from a vault server based on verifying that the source of the vault access request originated from the multitenant application server; and executing, by the computing device, a multitenant application task using the vault credentials. |
| US11094019B2 |
Associating off-line transactions with on-line visitor web sessions
Methods, system, and computer program products for associating off-line transactions involving a product with visitors to a web-site. Data relating to an off-line transaction and data relating to visitors to a web-site is received in a computer. The computer determines a score for each visitor based on a number of page views relating to a product in the transaction. A subset of visitors may be determined based on the scores. A likely candidate may then be selected from the subset of visitors using matching methods that compare e-mail addresses, IP addresses, geographic proximities, and times of event occurrences of the transaction to those of the visitor web sessions. The visitor having the strongest match may be identified as a likely candidate, and a web session generated by the likely candidate associated with the off-line transaction for analytics analysis of web marketing and web-site design effectiveness. |
| US11094017B1 |
Visualizing investment changes using augmented reality
A method implemented on an augmented reality (AR) device includes accessing a user's investment strategy and selecting a material object. The material object and investment controls are displayed on a display screen of the AR device. The user alters the investment strategy using the investment controls. Alternative replacement objects are generated based on changes that the user makes to his or her investment strategy. One or more replacement objects are projected onto the display to represent an alternative material object that the user can afford based on the changed investment strategy. |
| US11094006B1 |
System for communicating with a financial institution to manage disbursements over a communication network
Disclosed is a system and a method for communicating with a financial institution over a communication network to manage payments of payee initiated by a sender. The system includes a database for storing plurality of modules, a central server for monitoring and updating the plurality of modules, a processing unit processes the plurality of modules. The plurality of modules includes a notification module, a payee module and a payment process module. The notification module allows the sender to send a payment summary to each payee. The payee module allows the payee to upload payee's details in the central server, to select a mode of payment to receive the payment, to input banking details of the financial institution. The payment process module processes the payment as per the mode selected by the payee in the payee module, further processes the payment via cheque mode if the payee fails to update the mode of payment in a pre-defined duration. |
| US11094005B2 |
System and method for determining social statements
Systems and methods are disclosed for providing a social statement for an account holder of a financial institution. In one example embodiment, the method includes receiving, by one or more computer processors, account holder financial data associated with the account holder, and receiving, by the one or more computer processors, account holder social data associated with one or more social networking profiles of the account holder. The method further includes associating, by the one or more computer processors, the account holder social data with the account holder financial data. In addition, the method includes identifying peer financial data associated with a peer group, and creating a social statement based at least in part on the account holder financial data, the account holder social data, and the peer financial data. Further, the method includes providing the social statement to the account holder. |
| US11094001B2 |
Immersive virtual entertainment system
Aspects of the subject disclosure may include, for example, a method that includes generating a virtual venue for the virtual reality space, wherein the generating the virtual venue including replicating an architecture of a venue associated with the event and generating a plurality of virtual stores for the virtual venue, wherein each virtual store is associated with each participant of the plurality of participants, accessing a plurality of cameras and a plurality of microphones associated with the event, generating the virtual reality space based on the plurality of participants, the virtual venue, the plurality of microphones, and the plurality of cameras, generating a plurality of images for each participant of the plurality of participants according to each profile for each participant of the plurality of participants to participate in the event, and presenting the virtual reality space to user equipment in a virtual reality format. Other embodiments are disclosed. |
| US11094000B2 |
Method and system for image transaction, electronic device and storage medium
Embodiments of the present disclosure provide a method and system for image transaction, an electronic device and a storage medium. The method for image transaction is applied to a transaction server in a system for image transaction. The system comprises an image purchasing terminal and the transaction server. The image purchasing terminal is a terminal logged in with a purchase account. The method comprises: sending transaction interface information to the image purchasing terminal, wherein the transaction interface information comprises data of at least one thumbnail to be displayed by the image purchasing terminal, and each thumbnail corresponds to one original image; receiving a purchase request that is sent by the image purchasing terminal for requesting purchase of a target original image; and completing a transaction of the target original image based on the purchase request. |
| US11093997B2 |
Systems and methods for utilizing vehicle connectivity in association with payment transactions
Disclosed are exemplary embodiments of systems and methods for utilizing vehicle connectivity to facilitate payment account transactions. One exemplary method includes requesting product data for a merchant, receiving the product data from the merchant, displaying the product data to a user at a vehicle, and receiving a selection of a product therefrom by the user. The method then includes creating an order object for the selected product and appending a vehicle signature, for the vehicle, to the order object. The vehicle signature may include a condition of the vehicle, a sound or vibration of the vehicle, and/or a vehicle identifier modified by an operator. The method then further includes matching the order object to a transaction object for the selected product based on the vehicle signature, and transmitting a purchase order to the merchant for the selected product, based on the order object and the transaction object. |
| US11093989B2 |
Method of customizing articles of footwear
A method of manufacturing articles of footwear that includes steps of providing articles to a customer, receiving evaluations of one or more structural characteristics of the articles and making new customized articles for the customer based on the evaluations of one or more structural characteristics. The method can be conducted as a cycle that is repeated each time the customer buys a new pair of footwear. |
| US11093986B2 |
Personalized delivery time estimate system
A personalized delivery estimate system is described. A commercial transaction is generated between a seller and a buyer for an item in an online marketplace. Historical transactions of buyers and sellers in the online marketplace are stored in a storage device. A personalized delivery time estimate is computed for the buyer of the commercial transaction using seller information, buyer information, and item information with the historical transactions of buyers and sellers in the online marketplace. |
| US11093983B1 |
Systems and methods for backend fulfillment of a sales product
Embodiments of the present disclosure are directed to systems and methods where an enrollment team is trained to get the customer set up on the systems, a second welcome call is placed within a predetermined amount of time to the customer to further solidify the deal, using social media groups that require customers to “check in” to encourage customers to participate in the groups, using purposeful placement of key information and announcements in the groups, welcoming new members to the group and providing strategies to encourage and lift up those customers are participating the most and live streams are hosted directly within the groups and posting the livestream schedule in the groups. |
| US11093982B1 |
Determine regional rate of return on home improvements
A facility for estimating a home improvement rate of return for a geographic area is described. The facility accesses information about homes in the geographic area including sale prices and data describing home improvements performed on the homes, such that some of the sale prices are associated with homes having a home improvement of a particular type. The facility obtains automatic valuations for the homes based on the homes' attribute values, and calculates the differences between the automatic valuations and the sale prices. The facility analyzes the differences and the home improvement data and, based on the analysis, estimates a rate of return of the particular type of home improvement. |
| US11093981B2 |
Smart broadcasting device
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for broadcasting audio. In one aspect, the method includes receiving, from a server by a smart broadcasting device associated with a service client, an audio broadcast instruction; in response to receiving the audio broadcast instruction, downloading an audio file corresponding to the audio broadcast instruction, wherein the audio file comprises a marketing content related to services provided by the server to the service client associated with the smart broadcasting device; and broadcasting, by the smart broadcasting device, the audio file by using a speaker of the smart broadcasting device. |
| US11093980B2 |
Fine print builder
A method, apparatus, and computer program product are disclosed to improve generation of fine print for promotions. The method includes receiving identifying information that identifies one or more locations and either a product or service, transmitting the identifying information, and receiving, based on the identifying information, information including a set of relevant fine print clause data structures. The method further includes displaying, by a user interface, one or more fine print clauses from the relevant fine print clause data structures and generating, using a processor, a configured fine print data structure based on the displayed fine print clauses and input received via the user interface. Finally, the method includes transmitting the configured fine print data structure. A corresponding apparatus and computer program product are also provided. |
| US11093969B2 |
Cross-domain contextual targeting without any in-domain labelled data
A computer-implementation method for dataless contextual targeting includes the following steps. First, automatically crawling noisy labeled corpora from one or more sites using a category mapping from first categories to second categories. Second, applying one or more statistical methods to automatically mine representative keywords for each of the first categories from the noisy labeled corpora. Applying dataless classification learning to induce a text classifier with the automatically mined representative keywords and unlabeled web pages as input. |
| US11093968B2 |
Audience proposal creation and spot scheduling utilizing a framework for audience rating estimation
An audience proposal creator determines a target cost per thousand (CPM) baseline and a demographics CPM baseline for a deal offering audience spots, determines deal constraints based on a target CPM reduction goal, a demographics CPM cap, and the established parameters, and generates rates by selling title for each selling title-weeks for a duration of pending deal, and for each network of a plurality of networks based on the constraints. Target and demo audience rating estimates are acquired based on the target and demo applicable to the advertiser for the plurality of networks, and a distribution of the audience spots generated across the plurality of selling title-weeks, and networks based on the target audience rating estimates, a budget for the pending deal, the generated rates, and available inventory per selling title-weeks, and a proposal generated based on the distribution. An audience processor schedules audience spots across one or more networks for selling title-weeks based on the distribution. |
| US11093967B1 |
Determining whether to maintain information describing a group of online system users specified by a third-party system based on revenue from content selection based on the group and objectives for presentation of selected content
An online system receives information describing a target group of online system users from a third party system and stores the information describing the target group. The online system subsequently uses the target group to select content for presentation to one or more users. For example, users included in the target group are identified as eligible to be presented with content items. Content items are associated with objectives satisfied when a specified interaction with the content item, or with an object associated with the content item, is received. Based on revenue obtained by the online system from presenting content based on the target group as well as interactions satisfying objectives associated with various presented content, the online system determines a monetization value for the target group. Based on the monetization value, the online system determines whether to continue storing the information describing the target group. |
| US11093966B2 |
Systems, methods and articles for audience delivery optimization
Systems, methods and articles for providing optimized scheduling of a log of spots to be delivered to consumers. The optimized scheduling allows content providers to autonomously satisfy contracts and increase revenue. An audience delivery optimizer system receives an initial log, generates an optimized log, and returns the optimized log so that content can be delivered to consumers according to the optimized log. The audience delivery optimizer system may use historical ratings data and may implement an algorithm to accurately project future delivery. The audience delivery optimizer system may evaluate and optimize a log that spans a particular period of time, such as a day, a week, a month, etc. The audience delivery optimizer system may evaluate over-performing contracts and under-performing contracts and may then optimize the placement of spots based on such evaluations. The audience delivery optimizer system may track liability or other metrics over determined periods (e.g., quarterly). |
| US11093964B1 |
Promotion processing system for generating a digital offer based upon unpurchased item parts of a multi-part promotion and related methods
A promotion processing system may include a point-of-sale (POS) terminal associated with a retailer and a promotions. The promotions server may be configured to store a multi-part promotion corresponding to item parts, cooperate with the POS terminal to determine whether less than all of the item parts for the multi-part promotion has been purchased, and generate a digital offer associated with unpurchased item parts. The promotions server may also be configured to accept user selection of one of applying the digital offer toward another item and a charitable donation. |
| US11093961B2 |
Systems and methods for on demand local commerce
Systems and methods for on demand local commerce are described. One example embodiment includes a device gathering location information and product interest associated with clients and client devices. The system may use location information in determining that the first plurality of client devices are within a first geographic area during a first time period, and may further use the interest information in calculating an interest level for a first product. A threshold may be identified and used in determining that the interest level for the first product exceeds the threshold. When the calculated interest level exceeds the threshold, a local commerce action is initiated. In various embodiments, the local commerce action may be a live on demand auction at a particular location, an offer associated with a geofenced area, a sales location recommendation to a merchant, or any other such local commerce action. |
| US11093959B2 |
Systems and methods for improving the liquidity and distribution network for luxury and other illiquid items
Systems and methods for improving the liquidity and distribution network for luxury and other illiquid items are provided. These systems and methods preferably include the trading of futures and options contracts, which will provide the liquidity and distribution network for luxury items. Possible embodiments of these systems and methods include the trading of futures and options contracts for diamonds and wine. Another embodiment of this invention preferably includes generating indexes for diamond prices, wine prices, luxury item prices, housing values, mortgage prepayments, privately-held companies or for anything with from sufficiently liquid points of value. Another embodiment of this invention preferably includes a centralized data base for retrieving closing and current auction prices for determining the value of, and best method for the auctioning of various items. The data provided by this data base would improve liquidity by creating greater price transparency. |
| US11093956B2 |
Methods and apparatus to determine the probability of presence
Methods, apparatus, systems and articles of manufacture are disclosed for determining a probability of presence for a user of a first device at a second media presentation with a second device. The probability of presence is determined by accessing a demographic impression from a database proprietor for the first device for a first media presentation, where the first device is registered with the database proprietor. Accessing a non-demographic impression from a second device, not registered with the database proprietor, for the second media presentation, where the non-demographic impression has one shared data item with the demographic impression. And determining the probability of presence for the user of the first device to be exposed to the non-demographic impression from the second device, based on the demographic impression, the non-demographic impression and the shared data item. |
| US11093950B2 |
Customer activity score
Aspects of the subject technology relate to methods and systems for calculating a customer activity score (CAS). In some aspects, a method of the subject technology includes steps including aggregating behavior information for each of a plurality of utility customers, the behavior information including historic consumption data for at least one consumable resource, and calculating, and using the behavior information, a customer activity score (CAS) for one or more of the utility customers. In some aspects, the method can also include steps for generating customer content for at least one of utility customers based on a corresponding CAS value. In some aspects, systems and computer-readable media are provided. |