| Document | Document Title |
|---|---|
| US10164829B1 |
Incremental update of the data plane of a hardware forwarding element
A method of incremental updating of a network forwarding element that includes (i) a set of data plane circuits with a set of ingress buffers and a group of configurable packet processing stages and (ii) a set of control plane circuits comprising a set of direct memory access (DMA) buffers. Configuration data for reconfiguring the data plane packet processing stages is loaded into the DMA buffers while the packet processing stages are processing the packets. The ingress buffers are configured to (i) pause sending the packets to the processing stages and (ii) continue storing the incoming packets while sending the data plane packets to the processing stages is paused. The configuration data is loaded from the DMA buffers into the packet processing stages. The ingress buffers are configured to resume sending the data packet plane packets to the packet processing stages. |
| US10164828B2 |
Geospatial based management of configuration profiles
A system, method and program product for managing profiles for devices in a network. A computer system is disclosed having a configuration management system for managing configuration profiles for a set of devices within a network, and includes: a boundary definition system that employs a computerized process for defining a plurality of geospatial boundaries; a device manager that employs a computerized process for interfacing with remote agents associated with respective devices to recognize when a device has migrated into a new geospatial boundary; and a profile management system that employs a computerized process for uploading an updated configuration profile to the remote agent in response to the device being migrated to the new geospatial boundary. |
| US10164827B2 |
Information processing system and information processing method
An information processing system includes a storage unit that stores association information that is obtained by associating identifying information of a plurality of second communication networks that are interconnected via a first communication network with identifying information of a virtual device that exists in the second communication network; a first specifying unit that specifies according to the association information a second communication network in which a target virtual device exists, in a case in which the first specifying unit acquires a request for a setting change to the target virtual device; a second specifying unit that specifies a physical server on which the target virtual device runs from among physical servers that exist in the specified second communication network; and a setting unit that performs the setting change to the target virtual device that runs on the specified physical server. |
| US10164823B2 |
Protection method and system for multi-domain network, and node
In the field of network communications, a protection method for a multi-domain network, wherein the multi-domain network comprises a first domain and a second domain and the two domains are interconnected by node B and C, includes: after failure of a first link between the two nodes is detected, node C disconnects a first protection path with the first domain, connects a first sub-path of the first protection path and a path that is within a second domain to form a new protection path for bearing a service across the multi-domain network, and sending, on the first sub-path, a first failure monitoring message that carries first maintenance information to node A, where the first maintenance information is the same as second maintenance information carried in a second failure monitoring message; the second failure monitoring message is a message that is sent on the first protection path by node B to node A and is used to monitor a failure of the first protection path. |
| US10164822B2 |
Flatnet failover control
Failover controllers help maintain user-perceived continuous connectivity for users of a geographically dispersed flat network when part of that network becomes unavailable, even though flat network packets are not WAN-routable. One such controller has local and remote flat network ports, at least one WAN port, and failover capability to WAN(s) utilizing encapsulation when the flat network is partially or fully unavailable. The failover procedure uses a packet origin table built automatically from incoming packets and from double-tunneled ARP requests. A monitor indicates whether the flat network is fully available (up) or not fully available (down). Controller software updates the packet origin table, and directs packets between ports depending on flatnet status, the packet origin table's content, and any packet handling enhancements such as load balancing, affinity enforcement, quality of service maintenance, packet traffic shaping, packet policy application, firewall operation, reverse firewall operation, encryption/decryption, and/or compression/decompression. |
| US10164821B2 |
Stream computing event models
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for classifying events in a stream computing system using hierarchical analytic models. One of the methods includes receiving, by a stream computing system, data representing the values of one or more data attributes of an event in a stream of events. The values of each of the one or more data attributes are evaluated according to respective attribute-specific and class-specific criteria of a hierarchical analytic model in a predetermined order defined by the model. When a first value of a first data attribute satisfies one or more particular criteria for a first class, the first class of the plurality of classes is assigned to the event. |
| US10164817B2 |
Methods and apparatuses for signal translation in a buffered memory
According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal. |
| US10164816B2 |
Device and method for transmitting data
A method for transmitting data, wherein along a transmission path: (i) a modulated carrier signal is generated based on the data to be transmitted, the carrier signal having a carrier frequency within a given transmission channel, which is comprised of a number of frequencies, and (ii) the modulated carrier signal is amplified to a transmission signal, wherein along a compensation path: (i) the modulated carrier signal is filtered, whereby the frequency components within the transmission channel are removed, and at least one of a phase, an amplitude, and/or a delay of the filtered signal is modified thereby generating a compensation signal, and wherein the compensation signal is subtracted from the transmission signal thereby generating a compensated transmission signal, and wherein the compensated transmission signal is transmitted. Also a respective data transmission device is disclosed. |
| US10164815B2 |
Extremely precise frequency estimation apparatus and method for single receiver
A frequency estimation apparatus and method for a single receiver. The frequency estimation apparatus for the single receiver includes: a coarse frequency estimation unit estimating a coarse frequency by calculating an average of frequency estimation values for each single pulse; a direct current domain transformation unit transforming a reception signal into a direct current domain based on the coarse frequency; a fine frequency estimation unit estimating a fine frequency by applying regression analysis to a pulse train in the direct current domain of the coarse frequency; and an extremely fine frequency estimation unit estimating an extremely fine frequency by compensating an error of the coarse frequency with the fine frequency. |
| US10164813B2 |
Transmission apparatus
A transmission apparatus includes a data-block generating unit that generates and outputs a data block including fixed sequence symbols whose signal values are formed of a fixed sequence and data symbols, a pilot-block generating unit that generates and outputs a pilot block including the fixed sequence symbols and pilot symbols that are fixed symbols known on a reception side, and an output control unit to which the data block and the pilot block are inputted, which controls whether the data block or the pilot block is outputted. |
| US10164812B2 |
Method for determining reserved tones and transmitter for performing PAPR reduction using tone reservation
A method of determining reserved tones to be used for reduction of a peak to average power ratio (PAPR) of a signal includes: randomly selecting carrier indices for the reserved tones and generating a kernel signal based on the randomly selected carrier indices; calculating a comparison reference average value of the kernel signal, comparing the calculated comparison reference average value with a prestored comparison reference average value, and preliminarily determining carrier indices of the reserved tones based on the comparison; randomly re-arranging an order of the preliminarily determined carrier indices of the reserved tones; and calculating the comparison reference average value while changing each of the re-arranged indices of the reserved tones, and finally determining carrier indices for which the calculated comparison reference average value becomes the smallest value as carrier indices of the reserved tones. |
| US10164811B2 |
Method for determining reserved tones and transmitter for performing PAPR reduction using tone reservation
A method of determining reserved tones for reduction of a peak to average power ratio (PAPR) includes: selecting carrier indices for the reserved tones and generating a kernel signal based on the selected carrier indices; calculating a comparison reference average value of the kernel signal, selecting one of the calculated comparison reference average value and a prestored comparison reference average value, and preliminarily determining carrier indices of the reserved tones based on the selection; re-arranging an order of the preliminarily determined carrier indices; calculating a comparison reference average value of a kernel signal generated, whenever each of the re-arranged carrier indices is changed to another carrier index, to generate a plurality of comparison reference average values, and finally determining carrier indices of the reserved tones which generates a kernel signal having the smallest comparison reference average value among the comparison reference average values as the indices of the reserved tones. |
| US10164809B2 |
Circuits for efficient detection of vector signaling codes for chip-to-chip communication
In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer. |
| US10164808B2 |
Test instrument for testing devices internally performing signal conversions
A test instrument measures performance of a transponder without direct access to a line interface of the transponder. The test instrument learns parameters of internal signal conversion processes of the transponder and measures performance of the transponder based on the learned parameters. |
| US10164802B1 |
Full bridge decision feedback equalizer
A decision feedback equalizer (DFE) is provided. The DFE includes an analog front end, configured to receive a digital communication signal having amplitude modulation greater than two-level, and to output a feedforward signal based on the digital communication signal. The DFE includes a summing block, configured to receive the feedforward signal, a plurality of delayed data decisions as digital signals, and a plurality of adapted coefficients. The summing block is configured to produce an analog feedback signal as an analog subtraction from the feedforward signal of each of the plurality of delayed data decisions multiplied by a corresponding one of the plurality of adapted coefficients. The DFE includes a delay chain configured to produce the plurality of delayed data decisions based on the analog feedback signal, each of the plurality of delayed data decisions having two or more bits, corresponding to the amplitude modulation being greater than two-level. |
| US10164799B2 |
Method, apparatus, and system for correcting channel of remote radio unit
The present disclosure relates to a remote radio unit (RRU), which is connected to a baseband unit (BBU) and an antenna, comprising: a service transmit channel configured to transmit a first correction signal through the antenna, and a standing wave detecting circuit associated with the service transmit channel, wherein: a working frequency of the standing wave detecting circuit is consistent with the service transmit channel, and the standing wave detecting circuit is capable of detecting a standing wave ratio of the service transmit channel and is configured to receive a correction signal looped back by the antenna, and send the correction signal looped back by the antenna to the BBU, wherein the correction signal looped back by the antenna comprises a portion of the first correction signal reflected by the antenna and is used for a calculation of a correction coefficient of the service transmit channel. |
| US10164796B2 |
Flexible flow table with programmable state machine
A network switch for network communications includes an embedded programmable state machine to monitor data flows through the switch. The programmable state machine is configured to retain selectable states of selectable data packet fields. Programmable switch logic operative with the programmable state machine is configured to output one or more potential actions to be taken based on a selectable computation of detected selectable states. The programmable state machine can be implemented with either table lookups or flexible logic. |
| US10164791B2 |
Electrical connector having metallic bracket accommodating pre-assembled metallic plate and upper and lower terminal modules
An electrical connector includes: an upper and lower terminal modules each including plural terminals; a metallic plate secured between the upper and lower modules; a metallic bracket accommodating the secured metallic plate and upper and lower terminal modules; and an insulative body insert-molding the metallic bracket with the secured metallic plate and upper and lower terminal modules to form a tongue exposing the terminals of each of the upper and lower terminal modules. The metallic bracket contacts the metallic plate and borders the tongue. |
| US10164790B2 |
Method for implementing an industry internet field broadband bus
The invention relates to a method for implementing an industry internet field broadband bus, and in the method according to the invention, a bus controller and respective bus terminals transmit data in their respective time slices to thereby ensure timely and temporally determinist data transmission. Thus the embodiments of the invention implement a high-performance, highly reliable, and highly real-time method for implementing an industry internet field broadband bus. Moreover a transmission medium of the two-wire data transmission network can be a twisted pair or a shielded twisted pair so that the method according to the embodiment of the invention can be applicable to a traditional industry control facility using a bus, and thus can be highly universally applicable. |
| US10164786B2 |
Industry internet field broadband bus architecture system
The invention relates to an industry internet field broadband bus architecture system based on the two-wire data transmission network widely used in the traditional industry control system, so that the system can provide high-performance Ethernet communication without modifying original wiring and topologies, thus providing a high-performance, highly reliable, highly real-time, and highly secured solution to switching an industry control system field layer network from a traditional field bus to an industry Ethernet bus. |
| US10164774B2 |
Securing a directed acyclic graph
A method and apparatus for securing a directed acyclic graph (DAG) is described. In one embodiment, an algorithm enables encryption of a DAG given a start node (an entrypoint), the node key for that node, and a path to traverse in the graph. A unique and cryptographically random key is generated for each node (sometimes referred herein as a unique node key). The node key encrypts the node it is generated for and also any edges exiting the node. The node key is stored on the incoming edge to the node (the edge from its parent node) encrypted with the node key of the parent node. Storing the keys on the edges of the DAG instead of on nodes of the DAG enables efficient querying of the DAG and the ability for a node to have multiple parents that may change without affecting the node's relationship with the non-changing parents. |
| US10164770B1 |
Pipelined data cryptography device and method
Apparatus, methods, and other embodiments associated with mitigating time delays through a data cryptography device are disclosed. In one embodiment, a method includes receiving input data to be processed on a sector-by-sector basis through a data cryptography device. The input data is organized as multiple commands of the input data, with each command including multiple sectors of the input data, and with each sector including multiple blocks of the input data. The input data is processed through the device to generate encrypted or decrypted sectors of data while mitigating time delays through the device. Time delay mitigation is accomplished by pipeline processing the blocks for each sector through the device, pipeline processing the sectors for each command through the device, and pipeline processing the commands through the device. The encrypted or decrypted sectors of data generated by the device are then output by the device. |
| US10164767B2 |
Device for generating transmission clock of sink and transmission method using generated transmission clock
A semiconductor device for generating a transmission clock in a sink without a reference clock and a method of transmitting data from the sink to a source by use of the generated transmission clock are provided. The sink may include: a receiver configured to generate a digital control oscillator code by using a phase difference between a reception clock of a data signal received from a source and a recovered clock and configured to recover data from the data signal by using the recovered clock recovered by the generated digital control oscillator code; and a transmitter configured to generate a transmission clock by the digital control oscillator code having the recovered clock locked to the reception clock and configured to transmit return data to the source by using the transmission clock when a return data request identifier is received from the source. |
| US10164766B1 |
Advanced synchronization schemes for NFC card emulation mode, peer-to-peer mode and RFID tag design
A start-up control for a transmitter (TX) output driver is implemented to prevent the stick state problem when the TX driver is not toggling. TX output driver is set in a high impedance (HZ) mode when data zero is delivered from the digital base band (DBB) and set in an enhanced mode to deliver a stronger signal when data one is delivered from the DBB. The transmitter comprises a dual-loop PLL to synchronize the TX output pulse and the carrier. The dual-loop PLL is composed of a relaxation oscillator, a 1st Loop, and a 2nd Loop. The 1st loop is a voltage-controlled oscillator comprising the relaxation oscillator and an operational transconductance amplifier. The 2nd loop is a loop comprising a phase frequency detector, a charge pump, a loop filter and the VCO of the 1st loop. |
| US10164764B2 |
Inter-vehicle communication system and inter-vehicle communication method
In an inter-vehicle communication system, a first terminal included in a first vehicle includes a first control unit that receives a first relative phase between a third vehicle and a second vehicle transmitted by a second terminal included in the second vehicle and calculates, based on the received first relative phase and a second relative phase between the first vehicle and the second vehicle, a third relative phase between the first vehicle and the third vehicle, and the second terminal includes a second control unit that transmits the first relative phase to the first vehicle. |
| US10164761B2 |
Using decision feedback phase error correction
Methods and systems are provided for using error related feedback during signal processing. During handling of an input signal, each of a plurality of sub-carriers in the input signal is processed, and error-related information for each one of the plurality of sub-carriers is determined based on the processing. Aggregate error-related information is generated based on error-related information of each of one of the plurality of sub-carriers, and subsequent processing of at least one of the sub-carriers is adjusted based on the aggregate error-related information. The error-related information may comprise phase error-related information. Adjustments to subsequent processing of one or more of the sub-carriers may be determined based on processing-related information corresponding to different stages during processing of each of the plurality of sub-carriers. |
| US10164760B1 |
Timing excursion recovery
Systems and methods are disclosed for detecting and compensating for timing excursions in a data channel. If a signal contains discontinuities in phase, a detector of the channel may lose lock on the signal, resulting in the channel incorrectly adjusting a sampling phase toward a following symbol or previous symbol. This is referred to as a cycle slip, where the integer alignment of the sampling of a signal contains a discontinuity over the duration of a sector, preventing decoding of the signal. A circuit may be configured to detect a cycle slip during processing of a signal at a data channel based on timing error values, and when the signal fails to decode, shift an expected sampling phase of a detector for a subsequent signal processing attempt. Shifting the expected sampling phase can cause the channel to adjust the sampling phase in the correct direction, thereby preventing a cycle slip. |
| US10164756B2 |
Self-interference cancellation antenna systems and methods
The present application describes systems and methods of performing self-interference cancellation. According to an embodiment, the method sends a transmit signal through a circulator to substantially isolate the transmit signal from a receiver, with at least a portion of the transmit signal entering a receive path towards the receiver. The method also generates a reflected signal from an antenna. The reflected signal is at substantially less power than an incident power to the antenna. The reflected signal includes a transmitter carrier signal and a transmitter noise. The method also routes a received signal from the antenna to the receiver, and routes the reflected signal through a phase shifter in the receive path. Further, the method combines the reflected, phase shifted transmitter noise with the received signal in the receive path to cancel the portion of the transmit signal that entered the receive path towards the receiver. |
| US10164755B2 |
Transmission point indication in coordinated multi-point system
Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for transmission point indication in a coordinated multipoint (CoMP) system. A user equipment (UE) may receive common reference signal (CRS) parameters associated with individual base stations of a CoMP measurement set. The UE may also receive a transmission point index corresponding to a first base station of the CoMP measurement set that is scheduled for communications with the UE. A mapping module of the UE may produce a physical downlink shared channel (PDSCH) mapping pattern based on the CRS parameters associated with the scheduled base station. |
| US10164754B1 |
Method and apparatus for detecting spurious control information
In order to support low latency and bursty internet data traffic, the 3GPP LTE wireless communication system uses dynamic allocation. To keep the allocation overhead lower, the system is designed such that the client terminal must perform a number of decoding attempts to detect resource allocations. During course of the decoding attempts a false resource allocation may be decoded by the client terminal. The false detection may lead to multiple issues for the performance efficiency of the client terminal and the overall communication system. A method and apparatus are disclosed than enable the detection of false resource allocation. This in turn improves the performance and efficiency of the client terminal and the wireless communication system. |
| US10164745B2 |
Systems and methods for cross-channel scheduling of high efficiency (HE) multi-user (MU) frame transmission
Embodiments described herein provide a method for cross-channel scheduling of high efficiency (HE) multi-user (MU) frame transmission. In some embodiments, channel information and client station information may be obtained for data transmission. An MU frame containing a data field of a first type and two data fields of a second type may be configured to carry scheduling information relating to one or more channels for the data transmission. It may be determined that a current scheduling setting of the two data fields of the second type leads to unbalanced payload between the one or more channels. The two data fields of the second type may then be adjusted for a balanced channel mapping, and the data field of the first type may be adjusted to reflect the balanced channel mapping. Data based on the adjusted data field of the first type and the adjusted two data fields of the second type may be transmitted via the one or more channels. |
| US10164743B2 |
Data processing apparatus and method for use in an interleaver suitable for multiple operating modes
A data processing apparatus maps input symbols to be communicated onto a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processor includes an interleaver memory which reads-in the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals. The interleaver memory reads-out the data symbols on to the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on to the sub-carrier signals. The set of addresses are generated from an address generator which comprises a linear feedback shift register and a permutation circuit. |
| US10164740B2 |
Signal multiplexing apparatus using layered division multiplexing and signal multiplexing method
An apparatus and method for multiplexing signals using layered division multiplexing are disclosed. A signal multiplexing apparatus according to an embodiment of the present invention includes a combiner configured to combine a core layer signal and an enhanced layer signal at different power levels to generate a multiplexed signal, a power normalizer configured to reduce power of the multiplexed signal to power corresponding to the core layer signal, and a time interleaver configured to perform interleaving applied to both the core layer signal and the enhanced layer signal. |
| US10164737B2 |
SPC sensor interface with partial parity protection
A sensor system is configured to communicate at least partially protected sensor data over a communication interface. The sensor system includes a sensor element and a communication interface communicatively coupled to the sensor element. The sensor element is configured to provide sensor data in the digital domain. The communication interface is configured to generate a data package for transmission over the communication interface from the sensor data. The data package includes a data grouping comprising one or more nibbles related to the sensor data. The data package further includes a nibble indicia based on at least a portion of selected nibbles within the data grouping. |
| US10164733B2 |
Integrated physical coding sublayer and forward error correction in networking applications
Method and apparatus for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. The method includes performing a first forward error-correcting (FEC) sub-function on the data in the PCS transmit structure. The method further includes transmitting the data on one or more physical medium attachment (PMA) lanes to a PCS receive structure. The method also includes performing a second FEC sub-function on the data in the PCS receive structure. |
| US10164730B2 |
Signal processing method and base station
Embodiments of the present invention provide a signal processing method and a base station. By using respective sparse characteristics of a user signal and an interference signal, the user signal and the interference signal are iteratively recovered, that is, the interference signal is first fastened, and the user signal is recovered; and then the user signal is fastened, and the interference signal is recovered. In this way, an iteration cycle is repeated until the recovered user signal and the recovered interference signal meet a preset condition, thereby effectively improving interference cancellation performance, achieving relatively good interference suppression. |
| US10164728B2 |
Method and apparatus for generic mapping procedure GMP and method and apparatus for generic mapping procedure GMP demapping
Embodiments of the present invention disclose a method for generic mapping procedure (GMP) mapping, which includes: first the information about a adjusted time slot to be occupied by a second GMP block container is carried in the GMP overhead of a first GMP block container; then, the size of the second GMP block container is adjusted in accordance with the inforamtion; eventually, a client signal is mapped into the adjusted second GMP block container adopting a GMP scheme. This GMP mapping method, when working with a corresponding demapping method, provides lossless mapping and demapping of client signals during the process of bandwidth adjusting. |
| US10164725B2 |
Method of measuring time difference between detection times, and device for performing the method
A method of measuring a time difference between detection times includes receiving, from a first sensor, first information associated with a first detection time at which a first biosignal is detected, receiving, from a second sensor, second information associated with a second detection time at which a second biosignal is detected, and measuring a time difference between the first and the second detection times based on the first information and the second information. |
| US10164724B2 |
Microwave combiner and distributer for quantum signals using frequency-division multiplexing
A technique relates to a superconducting microwave combiner. A first filter through a last filter connects to a first input through a last input, respectively. The first filter through the last filter each has a first passband through a last passband, respectively, such that the first passband through the last passband are each different. A common output is connected to the first input through the last input via the first filter through the last filter. |
| US10164723B2 |
Adaptive augmented reality satellite acquisition
Satellite acquisition, for enabling a user device to engage in satellite communications, may be implemented using augmented reality (AR). An AR display may be presented to a user, and the user may use the AR display to point the user device toward a desired satellite. The process may include offsetting the position of a satellite icon representing the desired satellite in the AR display if acquisition is unsuccessful and thus indicating that the user device should be pointed to the offset position. In the case of a non-geosynchronous earth-orbit (non-GEO) satellite, such as a low-earth-orbit (LEO) satellite, the position of the satellite icon representing such a non-GEO satellite may be compensated for satellite movement during a satellite acquisition attempt. |
| US10164722B1 |
Dynamic signal filter in multi-antenna system
A processing device tracks a frequency hopping sequence implemented by a personal area network (PAN) transmitter in a user device and identifies a set of filter coefficients corresponding to a first frequency of a plurality of frequencies in the frequency hopping sequence, wherein the PAN transmitter is currently transmitting a PAN signal at the first frequency. The processing device configures a tunable notch filter with the set of filter coefficients to cause the filter to remove at least a portion of a PAN component at the current frequency from a combined signal received at a wireless local area network (WLAN) receiver in the user device, the combined signal comprising a WLAN component attributable to a received WLAN signal and the PAN component attributable to the PAN signal. |
| US10164721B2 |
Calibration systems and methods
A calibration system for calibrating a radio frequency, RF, device comprising a plurality of signal paths, each signal path comprising at least an amplifier and an antenna element, comprises a measurement system for driving the signal paths with a predetermined test signal and measuring an output of the signal paths in response to the test signal, a determination module for determining a first signal path, of which the antenna element provides the lowest output of all antenna elements, and a correction factor calculator for calculating based on output of the first signal path a correction factor for the further signal paths such that with the applied correction factor the output of all signal paths is equal within a predetermined acceptance interval. |
| US10164720B2 |
Method and apparatus for reciprocity calibration between base stations
Embodiments of the present invention provide a method and an apparatus for reciprocity calibration between base stations, which relate to the communications field, and can improve precision of reciprocity calibration between base stations. The method includes: obtaining, by each base station by means of calculation, a precoding vector corresponding to a selected subcarrier of the base station; sending, by all the base stations to UE by using the selected subcarriers of the base stations, downlink user-dedicated reference signals that are mutually orthogonal between cells corresponding to the base stations; obtaining, by each base station, an inter-base station calibration compensation coefficient of the selected subcarrier of the base station; and adjusting, by each base station, a self-calibration matrix of the selected subcarrier according to the inter-base station calibration compensation coefficient of the selected subcarrier of the base station. |
| US10164719B2 |
Transmission apparatus, transmission method, and transmission system
A transmission apparatus includes a communication unit, including input/output terminals and two coupling electrodes. An input/output circuit of the communication unit is configured to function interchangeably. The two coupling electrodes are arranged along the longitudinal direction of the transmission medium, when coupled to the transmission medium. When the length from one coupling electrode of the two coupling electrodes to one end of the transmission medium in the longitudinal direction thereof is an electrical length in a range of (2n·90±45)° of the electrical signal and the length from another coupling electrode of the two coupling electrodes to another end of the transmission medium in the longitudinal direction thereof is an electrical length in a range of ((2n+1)·90±45)° of the electrical signal while the two coupling electrodes are coupled to the transmission medium, the communication unit transmits and receives the electrical signal to and from another transmission apparatus. |
| US10164718B2 |
Transmission apparatus, transmission method, and transmission system
A transmission apparatus (10) includes a communication device (30), comprising two input/output terminals (20a, 20b), and a terminal line (40) connected to the first input/output terminal (20a) and having an electrical length of substantially 90°. By the second input/output terminal (20b) electrically coupling with a transmission medium (50) comprising a conductor or a dielectric, a high frequency signal or electric power is transmitted to another transmission apparatus coupled electrically to the transmission medium (50). |
| US10164717B2 |
Optical signal transmission device and electronic apparatus using same
A rotary joint includes a fixed unit and a rotating unit arranged substantially orthogonal to a center axis and facing one another, as well as a substantially cylindrical light guide member arranged therebetween. A light-emitting device and a light-receiving device are provided on each of the units. The light guide member is configured such that an amount of the light from the light-emitting device on the fixed unit that is received by the light-receiving device on the rotating unit and an amount of the light from the light-emitting device on the rotating unit that is received by the light-receiving device on the fixed unit both exceed a prescribed minimum amount regardless of rotational positions of the rotating unit. |
| US10164715B2 |
Adaptive demapper
An adaptive demapper adaptively demaps an input symbol. An input symbol is received and demapped in a hard-output demapper to generate a current detected symbol corresponding to a constellation point on a current constellation closest to the input symbol. A corrected inverse of a current noise power estimate is determined by updating a previous noise power estimate based on a difference between the input symbol and the current detected symbol. In a soft-output demapper, a log likelihood ratio corresponding to the current detected symbol is determined based on the corrected inverse of the current noise power estimate. The constellation point in the current constellation corresponding to the current detected symbol is then updated to generate an updated constellation based on a difference between the constellation point and the received input symbol. |
| US10164714B2 |
Methods and arrangements for generating a waveform for frequency shift keying communications
Embodiments may provide a way of communicating via an electromagnetic radiator, or light source, that can be amplitude modulated such as light emitting diode (LED) lighting and receivers or detectors that can determine data from light received from the amplitude modulated electromagnetic radiator. Some embodiments may provide a waveform in the form of chips at a chipping clock frequency that switch a light source between on and off states to communicate via light sources that can be amplitude modulated such as LED lighting. Some embodiments may provide a method of transmitting the waveform via modulated LED lighting. Some embodiments are intended for indoor navigation via photogrammetry (i.e., image processing) using self-identifying LED light anchors. In many embodiments, the data signal may be communicated via the light source at amplitude modulating frequencies such that the resulting flicker is not perceivable to the human eye. |
| US10164713B2 |
Optical transmitter, optical modulator module, and optical transmission system
An optical transmitter includes: a driving circuit that includes drivers each corresponding to a configuration bit of an input electrical data sequence; a MZ optical modulator that includes a first phase shifter provided in an arm and a second phase shifter provided in an arm; first capacitance elements that are electrically connected between the driving unit and the first phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a first multilevel signal to be supplied to the first phase shifter; and second capacitance elements that are electrically connected between the driving circuit and the second phase shifter, each include an electric capacity weighted in response to a bit number of the configuration bit, and generate a second multilevel signal to be supplied to the second phase shifter. |
| US10164712B2 |
Phased-array radio frequency receiver
A method of RF signal processing comprises receiving an incoming RF signal at each of a plurality of antenna elements that are arranged in a first pattern. The received RF signals from each of the plurality of antenna elements are modulated onto an optical carrier to generate a plurality of modulated signals that each have at least one sideband. The modulated signals are directed along a corresponding plurality of optical channels with outputs arranged in a second pattern corresponding to the first pattern. A composite optical signal is formed using light emanating from the outputs of the plurality of optical channels. Non-spatial information contained in at least one of the received RF signals is extracted from the composite signal. |
| US10164710B2 |
Optical transceiver for secure data transmission
We disclose a multichannel optical transceiver having a first optical channel used for client-data transmission over an optical fiber and a second optical channel that enables secure transport of encryption keys over the same optical fiber. In an example embodiment, the first channel uses a first carrier wavelength at which the optical fiber supports a single guided mode. The second channel uses a second carrier wavelength at which the optical fiber supports multiple guided modes. The secure transport of encryption keys can be achieved, e.g., by scrambling the encryption-key data over multiple space-division-multiplexed optical signals transmitted by way of the multiple guided modes. The securely transported encryption keys can then be used to enable the client data transmitted using the first optical channel to be encrypted to frustrate or prevent eavesdropping along the fiber length. |
| US10164708B1 |
Methods for determining receiver coupling efficiency, link margin, and link topology in active optical cables
A method for determining receiver coupling efficiency includes varying optical power inputted into a half active optical cable to determine a maximum optical power at which the TIA squelches and determining a receiver coupling efficiency by calculating a ratio of a threshold optical power to the maximum optical power at which the TIA squelches. A method of determining link loss in a channel includes varying optical power of a light source to determine the maximum optical power at which the TIA squelches and determining the link loss in the channel by subtracting the maximum optical power from the threshold optical power. A method of determining link topology includes selecting a pattern of optical powers and matching a pattern of squelched and non-squelched outputs with the pattern of optical power. An active optical cable includes memory storing a value related to an initial link loss of the active optical cable. |
| US10164707B2 |
Optical dispersion compensation in the electrical domain in an optical communications system
A compensation function mitigates a substantial portion of the dispersion imparted to a communications signal by an optical communications system. A digital input signal is digitally processed using the compensation function to generate a predistorted signal. An amplitude and a phase of an optical signal are modulated using a pair of orthogonal signal components to generate a predistorted optical signal for transmission. In one implementation, the pair of orthogonal signal components are components of the predistorted signal. In another implementation, the predistorted signal is processed using a non-linear compensator to generate a further distorted signal and the pair of orthogonal signal components are components of the further distorted signal. In that implementation, the non-linear compensator is configured to substantially compensate for nonlinearities in one or both of an optical modulator of a transmitter of the system and an optical-to-electrical converter of a receiver of the system. |
| US10164705B1 |
Methods and systems for controlling operation of satellite data units of an aircraft
In an example, a method for communicating over a satellite network is described. The method includes determining a first availability score for a first satellite data unit (SDU) of an aircraft based on first operational parameters comprising whether the first SDU is (i) reporting valid data, (ii) capable of providing data-link services, and (iii) capable of providing voice services, determining a second availability score for a second SDU of the aircraft based on second operational parameters comprising whether the second SDU is (i) reporting valid data, (ii) capable of providing data-link services, and (iii) capable of providing voice services, comparing the first availability score for the first SDU with the second availability score for the second SDU, and based on comparing the first availability score with the second availability score, controlling one of the first SDU and the second SDU to be an active SDU. |
| US10164701B2 |
Antenna allocation method and terminal
An antenna allocation method and a terminal for modems to receive a signal with a good antenna includes allocating a first antenna to a first modem; and if it is determined that the first modem satisfies a preset state, allocating the first antenna to any one of N−1 modems other than the first modem. |
| US10164700B2 |
Fault detection method and fault detection device for external antenna
A fault detection method and a fault detection device for external antennas, where the method comprises generating a first detection signal and transmitting the first detection signal using a main antenna, detecting whether a diversity antenna receives the first detection signal, acquiring a signal strength difference between the signals received by the main antenna and the diversity antenna, respectively, determining that the diversity antenna is faulty when the signal strength difference is not less than a first threshold, determining that the main antenna is faulty when the signal strength difference is not larger than a second threshold, and determining that the main antenna and the diversity antenna are faulty when the signal strength difference is larger than the second threshold and less than the first threshold. |
| US10164697B2 |
Resource allocation techniques for beamforming training
Various embodiments may be generally directed to resource allocation techniques for beam forming training. In one embodiment, for example, an apparatus may comprise logic for an access point (AP), at least a portion of the logic implemented in circuitry coupled to the memory, the logic to identify one or more resources available to support beamforming operations in a time interval, enable the AP to use the one or more resources in the time interval to interact with one or more allowed classes of station (STA) to perform one or more beamforming operations, and generate a frame for wireless transmission comprising a set of indicator bits encoded with an indication of the one or more resources. Other embodiments are described and claimed. |
| US10164696B2 |
Terminal device, base station device, communication method, and integrated circuit
A terminal device transmits an RI determined by the terminal device, the RI corresponding to PDSCH transmission and corresponding to the number of layers, transmits capability information including first information, second information, third information, and/or fourth information, and receives fifth information, wherein the first information indicates a UE category corresponding to a first maximum number of the layers, the second information indicates a first bandwidth class, the third information indicates a second maximum number of the layers, the fourth information indicates a third maximum number of the layers, the fifth information indicates a fourth maximum number of the layers, and a fifth maximum number of the layers assumed for determining a bit width for the RI is given by referring to any one of the first maximum number of the layers, the second maximum number of the layers, and the fourth maximum number of the layers. |
| US10164695B2 |
Tone block and spatial stream allocation
A method is described. A block allocation that indicates a plurality of contiguous tone blocks of a wireless local area network communication channel is selected for a multi-user, multiple input multiple output (MU-MIMO) orthogonal frequency division multiple access (OFDMA) data unit. A contiguous tone block corresponds to a respective device set having at least one communication device. Respective spatial stream allocations are selected, for at least some of the blocks, that indicate a number of spatial streams for the corresponding block of the data unit. The number of streams of a block is equal to a number of communication devices of the device set that corresponds to the block. A first field is encoded and transmitted to indicate the selected block allocation and the selected spatial stream allocations. A second field is encoded and transmitted to indicate a respective device identifier for each communication device of the respective device sets. |
| US10164689B2 |
Distributed antenna system to transport first cellular RF band concurrently with Ethernet or second cellular RF band
Embodiments described herein relate to a host unit for a distributed antenna system. The host unit includes a first radio access network (RAN) interface module to communicate with a RAN node. The host unit also includes a distribution module configured to distribute transport signals between one or more downstream RJ45 connectors and the first RAN interface module. One or more non-permanent connectors are included to couple the distribution module to a second RAN interface module and one or more upstream RJ45 jacks. The one or more upstream RJ45 jacks are configured to pass Ethernet signals therethrough. The distribution module is configured to couple a downlink portion of the first transport signals and either a downlink portion of the second transport signals or a downlink Ethernet signal from one of the upstream RJ45 jacks to a first twisted pair cable connected to one of one or more downstream RJ45 jacks. |
| US10164688B2 |
Actuator assisted alignment of connectible devices
A first electronic device is positionable between one or more contact positions and an aligned position with respect to a second electronic device. One or more actuators of the first electronic device are activated in response to one or more sensors of the first electronic device determining that the first electronic device and second electronic device are misaligned. Activation of the actuator may result in the first electronic device moving to the aligned position. In some implementations, the actuator may move the first electronic device toward the aligned position when activated. In other implementations, the actuator may overcome static friction to put the first electronic device in motion when activated and when the first electronic device is in motion one or more alignment mechanisms may overcome the kinetic friction to move the first electronic device to the aligned position. |
| US10164677B2 |
Gesture detection to pair two wearable devices and perform an action between them and a wearable device, a method and a system using heat as a means for communication
The present disclosure relates to devices and methods for initiating execution of actions and for communicating information to a user, and more particularly, to initiating execution of predefined actions in wearable devices and communication devices based on gestures made with the wearable devices and/or heat applied to a surface of the wearable devices. According to an aspect, the method relates to, in the wearable device, detecting a first, in the first wearable device predefined, gesture of the first wearable device, broadcasting a first signal comprising information associated with the first gesture, receiving, from a second wearable device, a second signal comprising information associated with a second gesture and initiating execution of a, in the first wearable device predefined, first action based on the first signal and the second signal. |
| US10164676B2 |
Electronic device case
An electronic device cover for use as a carrying case is described. The device can be a personal cell phone. The cover can be worn as an arm band or wristband carrying case. For example, the cell phone case/cover can have attached double bands connected from the edge of the cover flap to the bottom of the case. The flap can attach to the case through a small band attached at the top and the bottom of the cover flap. |
| US10164675B2 |
Wideband digital distributed communications system(s) (DCS) employing programmable digital signal processing circuit for scaling supported communications services
Wideband digital distributed communications systems (DCSs) employing reconfigurable digital signal processing circuit for scaling supported communications services are disclosed. The DCS includes a head-end unit that includes front end downlink signal processing circuit to receive and distribute downlink communications signals for communications services (i.e., communications bands) to remote units. The remote units also include front end uplink signal processing circuits to receive uplink communications signals to be distributed to the head-end unit. The front end signal processing circuits are either equipped with broadband filters, or such filters are eliminated, to allow the DCS to be scaled to pass added communications bands. The front end processing circuits include analog-to-digital conversion (ADC) circuits for converting received analog communications signals into digital communications signals so that the digital communications signals can be processed by digital signal processing circuit that can flexibly be configured and reconfigured to support the added communications bands. |
| US10164663B2 |
Method of operating decoder for reducing computational complexity and method of operating data storage device including the decoder
A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node. |
| US10164661B2 |
Data processing device and data processing method
The present technology relates to a data processing device and a data processing method, which are capable of securing excellent communication quality in data transmission using an LDPC code. In group-wise interleave, an LDPC code in which a code length N is 64800 bits and an encoding rate r is 7/15, 9/15, 11/15, or 13/15 is interleaved in units of bit groups of 360 bits. In group-wise deinterleave, a sequence of the LDPC code that has undergone the group-wise interleave is restored to an original sequence. For example, the present technology can be applied to a technique of performing data transmission using an LDPC code. |
| US10164659B2 |
QC-LDPC coding methods and apparatus
Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value. |
| US10164658B2 |
Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. |
| US10164656B2 |
Bit flipping algorithm for providing soft information during hard decision hard decoding
A method for using a first decoder operating in a hard decision hard decoding mode to generate soft information for a second decoder operating in a hard decision soft decoding mode includes: generating a look-up table (LUT) linking a number of failed check nodes to a log-likelihood ratio (LLR) value; in a first iteration of the first decoder, inputting the number of failed check nodes to the LUT table to generate an LLR value; and outputting the LLR value to the second decoder. |
| US10164652B2 |
A/D conversion device
A first mode in which to output analog electricity quantities of objects one by one independently to an A/D converter, a second mode in which to output none of the analog electricity quantities of the objects, a third mode in which to output none of the analog electricity quantities of the objects and cause the output to the A/D converter to be resistor, and a fourth mode in which to output to the A/D converter a plurality of the analog electricity quantities of the objects at the same time, are caused to be generated, thus acquiring the A/D conversion values of the objects individually when in the first mode, and detecting an anomaly of the A/D converter itself or a device connected to the A/D converter when in the second mode to the fourth mode. |
| US10164648B2 |
Phase error detection in phase lock loop and delay lock loop devices
A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin. |
| US10164647B2 |
Digital phase locked loop for low jitter applications
A phase locked loop circuit is disclosed. The phase locked loop circuit includes a ring oscillator. The phase locked loop circuit also includes a digital path including a digital phase detector. The phase locked loop circuit further includes an analog path including a linear phase detector. Additionally, the phase locked loop circuit includes a feedback path connecting an output of the ring oscillator to an input of the digital path and an input of the analog path. The digital path and the analog path are parallel paths. The digital path provides a digital tuning signal the ring oscillator that digitally controls a frequency of the ring oscillator. The analog path provides an analog tuning signal the ring oscillator that continuously controls the frequency of the ring oscillator. |
| US10164644B2 |
Clock synchronization between time calibration boards
Methods, devices and computer-readable mediums for clock synchronization are provided. The methods include receiving a synchronizing clock in a unit clock cycle of a measuring clock, calibrating position information of a rising edge of the synchronizing clock in the unit clock cycle, determining a phase difference between the measuring clock and the synchronizing clock in the unit clock cycle based on the calibrated position information, and compensating a photon time in the unit clock cycle with the determined phase difference as a time compensation value. |
| US10164642B2 |
Circuits, apparatuses, and methods for frequency division
Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit. |
| US10164641B2 |
Magnetoelectric computational devices
Embodiments of the present invention relate generally to logic devices, and more particularly, to magnetoelectric magnetic tunneling junction computational devices. Aspects of the disclosed technology include a stand-alone voltage-controlled magnetoelectric device that satisfies essential requirements for general logic applications, including nonlinearity, gain, concatenability, feedback prevention, and a complete set of Boolean operations based on the majority gate and inverter. Aspects of the present disclosed technology can eliminate the need for any auxiliary FETs to preset or complicated clocking schemes and prevents the racing condition. |
| US10164640B1 |
Method and device to speed-up leakage based PUF generators under extreme operation conditions
Disclosed is a physical unclonable function generator circuit and method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells, wherein each of the plurality of bit cells comprises at least two inverters, at least one floating capacitor, at least two dynamic nodes, wherein the at least one floating capacitor is coupled between a first inverter at a first dynamic node and a second inverter at a second dynamic node; a PUF controller coupled to the PUF cell array, wherein the PUF controller is configured to charge the first dynamic nodes through the respective first inverters in the plurality of bit cells; and a finite state machine coupled to the PUF cell array configured to determine voltage levels on the second dynamic nodes through the respective second inverters in the plurality of bit cells to determine first logical states of the plurality of bit cells at at least one sampling time and generate a PUF signature. |
| US10164637B2 |
Level shifter for voltage conversion
A device and method for shifting voltage levels within a circuit are provided. An aspect of the disclosure provides a level shifting circuit for shifting a first logic domain to a second logic domain. In particular, the level shifting circuit can receive an input signal having a first logic domain with a first high voltage and a first low voltage. The level shifting circuit can receive inputs corresponding to a second high voltage and a second low voltage from the second logic domain. The level shifting circuit can concurrently switch the first high voltage and first low voltage at the input to the second high voltage and the second low voltage to produce a level-shifted version of the input signal at the output. The level shifting circuit can also have a plurality of guard transistors that prevent overvoltage of the circuit components. |
| US10164635B2 |
Low voltage transmitter with variable output swing
Described herein are apparatus, system, and method for improving output signal voltage swing of a voltage mode transmitter (Tx) driver. The Tx driver may use a single power supply which is the same as the power supply of the core processor. The apparatus comprises: a voltage mode driver coupled to an output node; a switching current source, coupled to the output node, to increase voltage swing of a signal on the output node, wherein the signal is driven by the voltage mode driver; and a bias generator to bias the switching current source. |
| US10164633B2 |
On-chip impedance network with digital coarse and analog fine tuning
System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network. |
| US10164631B2 |
Holographic proximity switch
A vehicle switch is provided that includes a substrate. A holographic film is positioned on the substrate. A first light source and a second light source are configured to emit a light onto the film and a proximity switch assembly is positioned on the substrate. The holographic film is configured to create a projected image above the holographic film. |
| US10164625B2 |
Semiconductor switching element driver circuit with operation based on temperature
A driver circuit (101) is connected to a control terminal of a semiconductor switching element (1). The driver circuit (101) includes an input circuit (3) connected to an input terminal (50), and an output control circuit (4) connected to the input circuit (3). A pulse signal output from the output control circuit (4) is input to a dead time adjustment circuit (13). The dead time adjustment circuit (13) includes a delay circuit which can delay the rising edge and the falling edge of the pulse signal output from the output control circuit (4) on the basis of signals from temperature analog output circuits (11) and (12). An output from the dead time adjustment circuit (13) is input to the drive circuit (5). The drive circuit (5) outputs a drive signal to an output terminal (51) of the driver circuit (101). |
| US10164624B2 |
Apparatuses for reducing off state leakage currents
Apparatuses for reducing leakage currents during an off state for transistors is described herein. An example apparatus includes a switch having an input node and an output node. The switch is configured to couple a signal on the input to the output node when the switch is in an on state and is further configured to decouple the input and output nodes when the switch is in an off state. The switch includes first and second transistors, and further includes third and fourth transistors. A drain electrode of the first transistor is coupled to a source electrode of the third transistor, a drain electrode of the second transistor is coupled to a source electrode of the fourth transistor, and the drain electrodes of the third and fourth transistors are coupled together to the output node. |
| US10164623B2 |
Circuit device, electronic device, physical quantity sensor, and vehicle
A circuit device includes a comparator and a flag signal generation circuit. The comparator includes a first voltage-time conversion circuit to which at least a first input signal is input and which outputs a first time information signal, a second voltage-time conversion circuit to which at least a second input signal is input and which outputs a second time information signal, and a determination circuit that determines magnitude relation of the first input signal and the second input signal, based on the first time information signal and the second time information signal. The flag signal generation circuit generates a flag signal indicating that a voltage difference between the first input signal and the second input signal is a predetermined voltage or less, based on the first time information signal and the second time information signal. |
| US10164622B2 |
Circuit and method for reducing mismatch for combined clock signal
A circuit comprises a cycle-cycle detector, configured to receive a synthesized clock signal, and detect a cycle difference index signal between any two neighboring cycles of the synthesized clock signal, wherein the synthesized clock signal is combined by a plurality of phase shifted signals; a demultiplexer connected to the cycle-cycle detector, configured to convert the cycle difference index signal into a plurality of parallel data signals; and a first state machine, connected to both the demultiplexer and the cycle-cycle detector, configured to generate a tuning signal based on the parallel data signals, and feed the tuning signal back to the cycle-cycle detector; wherein the cycle-cycle detector is further configured to adjust delay time of the synthesized clock signal according to the tuning signal. |
| US10164612B2 |
Storage circuit and semiconductor device
The storage circuit includes first and second logic circuits, first and second transistors whose channel formation regions include an oxide semiconductor, and a capacitor. The first and second transistors are connected to each other in series, and the capacitor is connected to a connection node of the first and second transistors. The first transistor functions as a switch that controls connection between an output terminal of the first logic circuit and the capacitor. The second transistor functions as a switch that controls connection between the capacitor and an input terminal of the second logic circuit. Clock signals whose phases are inverted from each other are input to gates of the first and second transistors. Since the storage circuit has a small number of transistors and a small number of transistors controlled by the clock signals, the storage circuit is a low-power circuit. |
| US10164608B2 |
Switch with phase change material
Switch comprising at least one PCM portion that can be in a conducting or blocked state depending on the amorphous or crystalline state of the PCM that can change state when it is heated, in which the PCM portion is continuous and has an elongated shape such that an input and an output of the switch are connected to two ends of the PCM portion respectively that are separated from each other by a distance corresponding to the largest dimension of the PCM portion, and comprising a control device of the state of the switch capable of passing heating currents through the PCM portion, approximately perpendicular to the largest dimension of the PCM portion, from at least two input points separated from each other and separated from the ends of the PCM portion, to at least two output points separated from each other and separated from the ends of the PCM portion. |
| US10164606B1 |
Load-compensated tunable coupling
A load-compensated tunable coupler leverages a cross-bar switch and simulated loads or ballasts to provide a tunable coupling between two quantum objects that can be selectively coupled or decoupled without changing their resonant frequencies. |
| US10164605B2 |
Bulk acoustic wave resonator with piezoelectric layer comprising lithium niobate or lithium tantalate
A bulk acoustic wave (BAW) resonator includes a substrate defining a cavity, a bottom electrode disposed over the substrate and the cavity, a piezoelectric layer disposed on the bottom electrode, and a top electrode disposed on the piezoelectric layer. The piezoelectric layer includes polycrystalline lithium niobate (LN) material or polycrystalline lithium tantalite (LT) material. The BAW resonator may further include an encapsulant layer formed on side and top surfaces of the piezoelectric layer. The encapsulant layer is configured to protect the LN material or the LT material of the piezoelectric layer from a release solvent previously applied to sacrificial material within the cavity in the substrate. |
| US10164602B2 |
Acoustic wave device and method of manufacturing the same
An acoustic wave device includes a substrate comprising one surface on which an acoustic wave generator and at least one ground pad are included; a support component formed of an insulating material and disposed on the substrate along a circumference of the acoustic wave generator; and a shielding member electrically connected to the ground pad and blocking reception or emission of electromagnetic waves at the acoustic wave generator. |
| US10164599B2 |
Circuitry with a noise attenuation circuit to reduce noise generated by an aggressor circuit
A circuitry includes a functional circuit providing a predetermined function and a resistive device coupled between a power supply and the functional circuit to contribute a resistance on a power supplying path for the power supply to supply power to the functional circuit. The resistance is tunable. |
| US10164597B2 |
Switchable filters and design structures
Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes. |
| US10164596B2 |
Switchable filters and design structures
Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed to be in contact with at least one piezoelectric substrate. The method further includes forming a micro-electro-mechanical structure (MEMS) comprising a MEMS beam in which, upon actuation, the MEMS beam will turn on the at least one piezoelectric filter structure by interleaving electrodes in contact with the piezoelectric substrate or sandwiching the at least one piezoelectric substrate between the electrodes. |
| US10164594B2 |
High-frequency semiconductor amplifier
A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source. |
| US10164593B1 |
Accurate, low-power power detector circuits and related methods using programmable reference circuitry
Embodiments of power detector circuits and related methods to compensate for undesired DC offsets generated within power detector circuits are disclosed. Input signals having input frequencies are received and converted to a magnitude signal, and reference signals are also generated. The magnitude signal may include a DC component proportional to a power of the input signal along with undesired DC offsets. The reference signal may include a DC component proportional to a power of at least one input reference signal along with undesired DC offsets. To compensate for errors introduced by the DC offsets, a programmable digital input signal is determined in a calibration mode and then applied to reference circuitry in a normal mode to compensate for the DC offsets. For the calibration mode, a difference between the magnitude signal and the reference signal is compared to a threshold value to generate a power detection output signal. |
| US10164592B1 |
Individually programmable preamplifier
A preamplifier may have a freeze bit that when set, puts the preamplifier in a static state, which prevents the preamplifier from implementing subsequent programming commands. The freeze state may continue until an unfreeze bit is programmed. In a multiple preamplifier system, preamplifiers can be differently and individually configured over a single interface. Preamplifiers may be released from the static state (frozen) by either programming the unfreeze bit (which can release all of the preamps) or by programming the freeze bit to a “0” state (releases the individual preamp). An inversion control circuit can allow inversion of a control signal to a preamplifier. The inversion control circuit may be enabled and disabled based on a physical conductive connection to a logic high voltage or a logic low voltage. One or more programmable control lines can determine whether the inversion function is activated when the inversion control circuit is enabled. |
| US10164588B2 |
Audio amplifier circuit, audio output device using the same, and electronic device using the same
An audio amplifier circuit for driving an electro-acoustic transducer, which is bridged transless (BTL)-connected to the audio amplifier circuit, in a filterless manner, including: a class D amplifier including a high side transistor and a low side transistor; a high side driver configured to drive the high side transistor; and a low side driver configured to drive the low side transistor, as a pair, wherein the low side driver is configured so that a time for turning off the low side transistor by the low side driver is longer than that for turning off the high side transistor by the high side driver. |
| US10164587B2 |
Electronically reconfigurable matching network
An electronically reconfigurable matching network having a plurality of electronically reconfigurable components is disclosed. Each of the plurality of electronically reconfigurable elements includes a plurality of selectable impedance elements coupled together. Each selectable impedance element includes an impedance element coupled between first and second end terminals and a field-effect transistor (FET)-based switch coupled between the first and second end terminals. The FET-based switch includes a first FET having first and second current terminals coupled to a first gate terminal and a second FET having a third current terminal coupled to the first gate terminal, a fourth current terminal, and a second gate terminal coupled to a first control terminal; and a third FET having a fifth current terminal coupled to the first end terminal, a sixth current terminal coupled to the second end terminal, and a third gate terminal coupled to the third current terminal. |
| US10164583B2 |
Method and system for the linearization of a MIMO communication scheme having nonlinear power amplifiers
A linearized MIMO system which includes a MIMO receiver which comprises one or more receiving units, each receiving unit comprises one or more receiving antennas and an optional MIMO spatial decoder. The linearized MIMO system also includes a linearized MIMO transmitter, which comprises a plurality of non-linear power amplifiers at respective transmission branches, where each of the non-linear power amplifiers feeds a respective antenna with an amplified signal. The linearized MIMO system also includes a MIMO spatial pre-coder for receiving an artificial data signal from a global linearizer, and based on a channel state information of the medium (medium-channel), the linearized MIMO system creates a plurality of transmission branch-signals. Each of the branch signals feeds one of the non-linear power amplifiers, respectively. The global linearizer receives a data signal and creates the artificial data signal. |
| US10164581B2 |
Self-oscillating amplifier with high order loop filter
A self-oscillating amplifier system is disclosed. The system comprises a pulse modulator, a switching power amplification stage and a demodulation filter. Moreover, the system comprises a compensator including a forward filter which is a high order filter including a second order pole pair and a second order zero pair. Hereby it is possible to decrease the phase turn at low frequencies for better stability and increasing the gain of the control loop within the desired bandwidth. |
| US10164575B2 |
System for monitoring the peak power for an RF power amplification and associated method of calculating peak value and of selecting supply voltage
Disclosed is a system for monitoring the peak power of a telecommunication signal to be transmitted for RF power amplification of the telecommunication signal to be transmitted, including a digital processing device, a digital to RF converter and a dc-dc converter, wherein the output of the dc-dc converter can take a discrete voltage value from N discrete voltage values, N being an integer equal to or greater than 2, the digital processing device including a processing path including an envelope tracking control logic adapted to create a continuous envelope tracking control signal. The processing path further includes logic for driving the dc-dc converter including a peak value calculating device and a power supply voltage selecting device. |
| US10164569B2 |
Signal generator and associated resonator circuit
A signal generator and an associated resonator circuit are provided. The signal generator includes the resonator circuit and a core circuit. The resonator circuit further includes a first inductor (L1), a second inductor (L2), a plurality of capacitors and a switching circuit. The first inductor (L1) has a first terminal (N1) and a third terminal (N3), and the second inductor (L2) has a second terminal (N2) and a fourth terminal (N4). The switching circuit includes a first switch (S1), a second switch (S2), a third switch (S3) and a fourth switch (S4). The core circuit further includes a first inner circuit, a first outer circuit, a second inner circuit, and a second outer circuit. Configurations of these switches are adjustable and resonance caused between these terminals is changed accordingly. |
| US10164568B2 |
Electronic component, electronic apparatus, and moving object
An oscillator including a container, a first protrusion portion protruding from the container along a first direction, a second protrusion portion protruding from the container along the first direction, and a projection portion protruding from the container along the first direction. The second protrusion portion is shorter than the first protrusion portion in the first direction, and the projection portion is longer than the second protrusion portion and shorter than the first protrusion portion in the first direction. |
| US10164567B2 |
Preventing harmful polarization of solar cells
In one embodiment, harmful solar cell polarization is prevented or minimized by providing a conductive path that bleeds charge from a front side of a solar cell to the bulk of a wafer. The conductive path may include patterned holes in a dielectric passivation layer, a conductive anti-reflective coating, or layers of conductive material formed on the top or bottom surface of an anti-reflective coating, for example. Harmful solar cell polarization may also be prevented by biasing a region of a solar cell module on the front side of the solar cell. |
| US10164565B1 |
Method of using solar panel support apparatus
A method of using a solar panel support apparatus for selectively positioning a solar panel contained thereon comprises securing forward and rearward legs to the ground or an affixed structure. A solar panel is supported by a rack having an end pivotally attachable to the forward leg. First and second arms pivotally connected to one another pivotally attach to the forward leg and the rack permitting the rack to be positionable relative the forward leg. A locking mechanism locks the first arm and the second arm at a selected angle relative to one another, whereupon securing the rearward and the forward leg to the ground or an affixed structure the rack is pivotal to position the solar panel. Upon positioning the rack to place the solar panel at a selected position, the locking mechanism is engaged to retain the solar panel at the selected position. |
| US10164561B2 |
Motor control system and motor control method
A motor control system is provided in the present disclosure. The motor control system includes a motor and a control module providing a control signal for driving the motor. The control system includes a processing module, a duty cycle detecting module for receiving a PWM signal from a system, a speed detecting module for providing a speed signal of the motor, a setting module for setting a configuration of the control module. The processing module adjusts the control signal to drive the motor based on a duty cycle value, a speed and a configuration value. |
| US10164559B1 |
System and method for measuring and diagnosing initial offsets of an analog input sensor
An electric power system includes a polyphase electric machine, battery pack, power inverter module, analog input sensor, and diagnostic controller executing a method. The sensor measures an electrical parameter that differs from a true value of the parameter by an initial offset value. The controller collects sample sets of the parameter, compares the initial offset of each sample to an outlier threshold in a first diagnostic loop, and transmits a bit flag indicative of an outlier sample to a slower second diagnostic loop when the initial offset of a sample exceeds the outlier threshold. The second control loop calculates a rolling average of the initial offsets of the sample sets, discards the set containing the outlier sample in response to the bit flag, and executes a control action when the average exceeds a threshold that is lower than the outlier threshold. |
| US10164558B2 |
Electric motor control device
An electric motor control device includes a control unit that controls operation of a drive circuit supplying electric power to an electric motor and a current sensor that detects current generated in the electric motor. The control unit detects fundamental high frequency current generated when the electric motor is applied with fundamental high frequency voltage for estimating the magnetic pole position, selects first electric angle and second electric angle corresponding to a d-axis direction of the magnetic pole position, detects first specific high frequency current generated when a position of the first electric angle is applied with specific high frequency voltage and second specific high frequency current generated when a position of the second electric angle is applied with the specific high frequency voltage, and compares the first and the second specific high frequency currents to estimate a positive d-axis direction of the magnetic pole position. |
| US10164557B2 |
Motor driving circuit
A first calculation unit subtracts third digital data which indicates the minimum value of the duty ratio from first digital data which indicates the duty ratio of the PWM driving operation. A slope calculation unit generates slope data which is dependent on the temperature based upon second digital data which indicates the temperature. A second calculation unit multiplies the slope data by the output data of the first calculation unit. A third calculation unit sums the output data of the second calculation unit and the third digital data. A selector receives the output data of the third calculation unit and the third digital data, selects one data that corresponds to the sign of the output data of the first calculation unit, and outputs the data thus selected as a duty ratio control signal. |
| US10164556B2 |
Control apparatus for eliminating magnetizing error of rotor in DC motor and method thereof
A control apparatus for eliminating a magnetizing error of a rotor in a DC motor and a method thereof. The rotor in the DC motor is provided with 2N magnetic pole positions disposed therein for phase switching, where N is a positive integer no less than 1. The control apparatus includes a phase detector, at least one counter, a PWM signal generator, control circuit and a full-bridge driving circuit. The phase detector detects changes of states of the magnetic pole positions of the rotor to generate a periodic phase-switching signal. The counter counts a count value associated with each of the magnetic pole positions, respectively. The PWM signal generator periodically outputs 2N PWM signals and adjusts each of the PWM signals issued in a next cycle, respectively, according to the count value associated with each of the magnetic pole positions received in a current cycle. |
| US10164550B2 |
Method, circuit configuration and bridge circuit for charging a capacitance effective on main current terminals of semiconductor switch
A method, circuit configuration and bridge circuit for charging a capacitance effective on the main current terminals of a semiconductor switch, in particular an intrinsic capacitance, in particular the drain-source capacitance of a MOSFET semiconductor switch or the collector-emitter capacitance of an IGBT semiconductor switch, the precharging, in particular the at least partial charging, of the effective capacitance being forcibly controlled via a charging current path. |
| US10164549B2 |
Power module cascaded converter system
Disclosed is a power module cascaded converter system, a control sub-system thereof includes a master controller, and is provided with switch modules corresponding one-to-one to power modules. For each switch module, before the corresponding power module is removed, a driver circuit thereof can drive the switch circuit into a closed state through a control signal sent from the master controller, so as to bypass the power module. An optical-electric module in the power module cascaded converter system converts an optical signal input from an optical fiber into an electrical signal. With a first control port of each switch module, which is detachably and electrically coupled to a second control port of the power module, the power module cascaded converter system can support insertion and extraction of the power module without cutting off electricity, thereby adding flexibility and convenience for replacing power modules. |
| US10164546B2 |
Electric power conversion device
An electric power conversion device which performs conversion to desired voltage using charge and discharge of a DC capacitor includes: a reactor connected to a rectification circuit; a leg part in which diodes and first and second switching elements are connected in series between positive and negative terminals of a smoothing capacitor, and to which the reactor is connected; and the DC capacitor. A control circuit performs high-frequency PWM control for the first and second switching elements using the same drive cycle, with their reference phases shifted from each other by a half cycle, and controls a sum and a ratio of ON periods of the first and second switching elements in one cycle, thereby allowing both high-power-factor control for input AC current and voltage control for the DC capacitor. |
| US10164541B2 |
Power supply unit
A power supply unit includes a conversion circuit that performs power conversion of power input into the power supply unit to supply direct-current power to an output path of the power supply unit, a control circuit that controls the conversion circuit so that output voltage supplied from the conversion circuit to the output path has a fixed value if output current supplied from the conversion circuit to the output path is lower than or equal to an overcurrent trip point and controls the conversion circuit so that the output voltage is decreased if the output current exceeds the overcurrent trip point, a monitoring circuit that monitors a discharge output from a discharge circuit to the output path, and a trip point changing circuit that increases the overcurrent trip point if the discharge output monitored by the monitoring circuit is decreased to a threshold value. |
| US10164540B2 |
Bi-directional feedback pin
A controller for a power conversion circuit has a first current-reading circuit coupled for receiving a first feedback signal at a first circuit node and generating an internal feedback signal at a second circuit node inversely proportional to the first feedback signal. A second current-reading circuit is coupled for receiving a second feedback signal at the first circuit node and generating the internal feedback signal at the second circuit node inversely proportional to the second feedback signal. The first current-reading circuit generates the internal feedback signal inversely proportional to an electric current injected into the controller at the first circuit node. The second current-reading circuit generates the internal feedback signal inversely proportional to an electric current drawn from the controller at the first circuit node. |
| US10164539B1 |
Power conversion system with clamp mode switching
A power conversion system with clamp mode switching includes a clamp conversion circuit, a switching circuit module, a PWM control module, and a feedback control module. The PWM control module stabilizes a feedback voltage when the feedback control module feeds the feedback voltage back to the switching circuit module and the PWM control module. The switching circuit module switches the clamp conversion circuit to operate in an active clamp mode or a non-active clamp mode. |
| US10164538B1 |
Dual-capacitors-based AC line frequency low voltage DC power supply circuit
A supply circuit includes a rectifying bridge arranged in series between two high voltage capacitors. An AC line provides an intermediate voltage to a low voltage capacitor through the two high voltage capacitors. A plurality of resistors mounted in series with the two high voltage capacitors. A voltage clamping device limits the intermediate voltage at the low voltage capacitor and a linear series regulator provides an output DC voltage. |
| US10164537B2 |
Switching regulator
A switching regulator includes a first switch; a second switch coupled between the first switch and ground; an inductor coupled to a common node between the first and second switches; a capacitor coupled between the inductor and ground; a controller receiving a disable signal, and generating first and second control signals respectively for the first and second switches; and a crossing detector comparing an auxiliary voltage at the common node with a negative reference voltage to generate a comparison signal, and generating the disable signal based on the first control signal and the comparison signal. The second control signal switches into an inactive state upon the disable signal indicating a reference-crossing of the auxiliary voltage. |
| US10164534B2 |
Single inductor multi-output buck-boost converter and control method thereof
A converter can include: (i) a first switch having a first terminal for receiving an input voltage, and a second terminal coupled to a first terminal of a second switch; (ii) an inductor having a first terminal coupled to a common node of the first and second switches, and a second terminal coupled to a first terminal of a third switch, where second terminals of the second and third switches are coupled to ground; and (iii) a plurality of output channels coupled to a common node of the inductor and the third switch, where the converter operates in a buck-boost mode, a buck mode, or a boost mode based on the relationship between the input voltage and output voltages of the plurality of output channels. |
| US10164531B2 |
Adaptive control method for generating non overlapping time in output devices
The disclosure describes an adaptive technique for generating minimum dead time in a DC-DC switching power converter, while ensuring no short circuit losses occur, resulting in efficiency improvement of the switching converter. In addition, this adaptive scheme makes sure that even the ambient conditions of the switching converter give the best decision at the ON/OFF timings of the switches. Body diode conduction feedback is detected, with reduced process sensitivity, and an algorithm is disclosed that finds the minimum dead time for a given load current, temperature, and process conditions. |
| US10164530B2 |
Boost chopper circuit including switching device circuit and backflow prevention diode circuit
In a boost chopper circuit, a distance between a plurality of first mounting portions of a first semiconductor package that houses a switching device circuit and a distance between a plurality of second mounting portions of a second semiconductor package that houses a backflow prevention diode circuit are different from each other. |
| US10164529B2 |
Spread spectrum clock generator and method
In one form, a spread spectrum clock generator includes an oscillator and a digital modulator. The oscillator has a control input for setting an output frequency, and an output for providing a clock output signal. The digital modulator is responsive to the clock output signal to provide a control code to the control input of the oscillator as a periodic signal with a plurality of discrete steps, wherein the digital modulator provides said control code at each of said plurality of discrete steps for substantially a predetermined time. |
| US10164528B2 |
Switch control circuit and buck converter including the same
A buck converter includes a power switch having one end to which an input voltage is transferred, a synchronous switch connected between the other end of the power switch and the ground, an inductor having an end connected to the other end of the power switch, and a switch control circuit configured to calculate a zero voltage delay time based on at least an ON time of the power switch and a delay time. The delay time is determined based on the inductor and parasitic capacitors of the power switch and the synchronous switch. |
| US10164526B2 |
Signal generation circuit, voltage conversion device, and computer program
A signal generation circuit, a voltage conversion device, and a computer program are provided wherein the minimum increment of a value to be set for a generating portion, can be made substantially smaller than an actual increment with a relatively small processing load. A CPU specifies a set value Y (closest to a target value X) and a second closest set value Z in every N periods of a first signal, determines N set values for the first signal by combining Y and Z based on the result of comparison between the values of Y and Z and the value of X, sets one set value for a generating portion for each period of the first signal, calculates a value for setting off-time of the second signal in a first period in N periods as an additional value, and sets the calculated value for the generating portion. |
| US10164506B2 |
Winding device and winding method
A winding device including radially disposed nozzles of a same number as the number of teeth, a plurality of the nozzles simultaneously drawing out a wire to corresponding slots between respective teeth to simultaneously wind the wire between predetermined two slots that correspond to a respective one of the nozzles, includes a wire drawing and cutting mechanism configured to draw out the wire from a single spool and cut the drawn-out wire at a predetermined length, a wire storing mechanism configured to dispose the wire of the predetermined length obtained by the wire drawing and cutting mechanism in a radial manner and store the wire to a same number as that of the plurality of nozzles, and a wire conveyance mechanism configured to convey the radially disposed plurality of wires from the wire storing mechanism, to the plurality of nozzles. |
| US10164504B2 |
Bi-directional MOSFET cooling for an electric machine
A power module for an electric machine. The power module includes a thermally conductive base having opposite first and second surfaces. The first surface is adapted for mounting the power module in conductive thermal communication with a heat sink. A MOSFET superposes the base second surface and is in conductive thermal communication with the base. A MOSFET driver superposes the base second surface and is operatively connected to the MOSFET. The transference from the power module of heat generated by the MOSFET and the MOSFET driver from the power module is directed along a primary cooling path to the heat sink through the base and a secondary cooling path to ambient air. The primary and secondary cooling paths are separate from each other. An electronics package and an electric machine including a power module are also disclosed. |
| US10164500B2 |
Signal bypass routed through a motor of an electrical submersible pump
An electrical submersible pumping system includes a well fluid pump driven by a three-phase motor. The motor has a stack of motor laminations mounted in a housing. The motor laminations have axially aligned slots spaced circumferentially around a bore. Motor windings are wound through the slots for receiving three-phase power provided to the motor. At least one set of three control lines extend axially through the motor laminations radially outward from the bore and equally spaced around the axis, The control lines may extend through channels on the outer diameter of the motor laminations. The control lines may also extend through the same slots that contain the windings. The control lines extend to a downhole element below the motor for controlling the downhole element. |
| US10164496B2 |
Electric machine and method for operating an electric machine
An electric machine for starting an internal combustion engine, comprising a housing (10) having at least one sealing device (14) which seals an interior (10a) of the housing with respect to the surroundings of the housing (10), and at least one pressure reduction device (1), wherein the at least one pressure reduction device (1) is embodied so as to be moveable in a translatory fashion relative to the at least one sealing device (14) in order to form, in the case of an overpressure in the interior (10a) of the housing, at least one venting duct via which an at least partial reduction in pressure is ensured. |
| US10164495B2 |
Motor-driven fluid machine
A motor-driven fluid machine has three motor wires. The innermost one of the three motor wires in the radial direction of a rotary shaft on a specific section of an outer end portion of a coil end is defined as a first motor wire. The first motor wire has a first extension, which extends from an inner side toward an outer side in the radial direction of the rotary shaft at a position between the specific section and a downstream side in the extending direction of the motor wires, and a second extension, which is continuous from the first extension and extends from the outer side toward the inner side in the radial direction of the rotary shaft to be connected to a corresponding conductive member. |
| US10164494B2 |
Electric machine
The invention relates to an electric machine comprising a stator (1) and a rotor (2) movable relative to said stator. Said stator comprises two multi-stranded, concentrated windings (A1, B1, C1, A2, B2, C2) which are placed in respective slots of the stator (1). While the first winding (A1, B1, C1) comprises six coils, the second winding (A2, B2, C2) is designed to have twelve coils. The number of turns (Nw1) of the coils of the first winding is different from the number of turns (Nw2) of the coils of the second winding. |
| US10164491B2 |
Rotary electric machine
Winding bodies are produced by repeatedly winding a δ-shaped coil pattern that is formed by inserting the conductor wire sequentially into a second slot, a first slot, a second slot, and a third slot, so as to alternate an axial direction of insertion into the first slot, the second slot, and the third slot, for two turns in a radial direction, and are configured such that a plurality of rectilinear portions that are respectively inserted into the first slot, the second slot, and the third slot are linked continuously by coil end portions, and a liquid coolant is supplied to a coil end that is constituted by the coil end portions. |
| US10164487B2 |
Motor, method for manufacturing magnetic plate, and method for manufacturing stator
A motor includes a rotation shaft, a stator, and a rotor. The stator includes an armature winding and a stator core including a main core portion with an axial stack of core sheets and a magnetic plate on an end thereof. Each core sheet includes a tooth formation portion around which the armature winding is wound. The magnetic plate includes a stacked portion and an axially extending portion. The stacked portion stacked on the axial end of the main core portion and includes an end located toward the rotor. The axially extending portion extends toward the outer side in the axial direction from the end of the stacked portion located toward the rotor and is opposed to the rotor in a radial direction of the motor. The axially extending portion is shaped to be magnetically skewed in a circumferential direction relative to the tooth formation portion and the stacked portion. |
| US10164486B2 |
Optimized electric motor with narrow teeth
The present disclosure relates to a mono- or polyphase electric motor including a stator carrying at least three coils and consisting of 12×N straight teeth extending radially, N being an integer greater than or equal to 1, and of an equal peak divergence alpha, measured at their end from the center of the motor, and a rotor exhibiting P pairs of magnetized poles such that P=5+2×R, P being a non-multiple of three, R being an integer greater than or equal to 0, alpha lying between 360°(12×N)/3 and 360°(12×N)/2. |
| US10164485B2 |
Stator-rotor device for an electrical machine
A stator-rotor device for an electrical machine, in particular an electric motor, includes a stator and a rotor, wherein the stator-rotor device pole cores provided with windings comprise pole shoes and magnets associated therewith. The pole shoes are connected via a first surface to a respective pole core and have a second surface that is facing towards the magnets. The pole shoes cooperate magnetically with the magnets and are separated from the latter by an air gap. The pole shoes and the magnets engage with one another in an engagement direction in such a way that in each case a section of the other component—magnet or pole shoes—is arranged lying opposite the respectively engaging component—pole shoe or magnet—transverse to the engagement direction on two sides facing away from one another. The second surface is larger than the first surface. |
| US10164484B2 |
Techniques for leveraging existing components of a device for wireless power transfer functionality
Techniques are described herein for leveraging these existing components of electronic devices with wireless or internet connectivity to reduce cost, size and complexity of electronic devices while enabling wireless power transfer. The techniques described herein can also be utilized to new low cost dual-function devices that utilize one or more of the same components for both wireless connectively and wireless power transfer. |
| US10164483B2 |
Tunable resonant inductive coil systems for wireless power transfer and near field communications
A tunable resonant inductive coil system includes an electrical circuit having an alternating current (AC) voltage source, a barium strontium titanate (BST) variable capacitor coupled in series with a first terminal of the AC voltage source, a coil coupled in series with the BST variable capacitor, and a return line coupling the coil with a second terminal of the AC voltage source and/or a ground. The electrical circuit forms an LC circuit (resonant circuit). The electrical circuit adjusts between two configurations. In the first configuration the resonant circuit has a first resonant frequency configured for wireless power transfer and in the second configuration it has a second resonant frequency configured for near field communication (NFC). An entire length of the coil is used for both resonant frequencies. Adjusting between the first and second configurations includes varying a capacitance of the BST variable capacitor in response to receiving a control signal. |
| US10164482B2 |
Wireless power transfer method, apparatus and system
The present invention relates to a wireless power transmission method, a wireless power transmission apparatus, and a wireless charging system in a wireless power transmission field, and the wireless power transmission method may include receiving first information of a first wireless power receiver and second information of a second wireless power receiver that receive power in a wireless manner within a first slot among a plurality of slots, transmitting a NAK (not-acknowledge) signal to the first and the second wireless power receiver and executing a collision resolution mechanism in the first and the second wireless power receiver. |
| US10164472B2 |
Method and apparatus for wirelessly charging portable electronic devices
Wireless charging of portable electronic devices is carried out by detecting load variations caused by the device and dynamically compensating for these variations during charging to increase system efficiency and regulate delivered power. In some embodiments, load variations are tracked by comparing a feedback signal to a value range and determining whether the feedback value is higher than, lower than, or within the range of values. This information is then used to modify one or more parameters associated with a power amplifier in a transmitter device. |
| US10164469B1 |
Adaptive wireless power transfer system
Wireless power may be transferred using wireless power elements such as coil antennas for inductive wireless power transfer technology or patch antennas for capacitive wireless power transfer technology. These antennas in source equipment may couple in a near-field region to antennas implemented in target equipment. Wireless power may also be transferred from the source equipment to the target equipment using radiating antennas in their far-field regions. Wireless power transfer may be optimized by performing channel estimation operations. Foreign objects can be detected and located using sensors or by analyzing the quality of wireless channels. Optimum power transfer settings may be used to maximize wireless power transfer to a set of the antennas in the target equipment while minimizing power transfer to the foreign object. |
| US10164467B2 |
Physical and virtual identification in a wireless power network
A wireless charging system is disclosed. The wireless charging system includes a detector configured to identify device information related to a device to be powered at a location, a location processor coupled with the detector and configured to deliver location-specific information related to the location to the device to be powered based on the detected device information, a power supply in communication with the location processor configured to wirelessly provide power to the device based on the detected device information, such that the location processor is configured to deliver the location specific information to the device via a first channel, and wherein the power supply is configured to wirelessly provide power to the device via a second channel. |
| US10164465B2 |
Transfer switching equipment
The present disclosure provides a transfer switching equipment, comprising a first switch set and a second switch set. The transfer switching equipment is configured in a way that during the switching from a closed state of one of the first switch set and the second switch set to a closed state of the other of the first switch set and the second switch set, there is a state in which the neutral poles of the first switch set and the neutral pole of the second switch set are closed at the same time while all phase poles of the first switch set and all phase poles of the second switch set are all opened. The transfer switching equipment has a simple and reliable structure and occupies a small space and can provide continuous voltage with high-quality during switching the power supply. |
| US10164462B1 |
Digital reservoir controller
A digital controller controls contingency discharges of a utility from a reservoir to a plant during a first time period and compensatory charges from the plant back to the reservoir during a second time period. The utility can be electric power. The plant and reservoir are connected by a grid. The reservoir may be any electric power storage device. When the utility is electric power, the contingency discharges make up for the power not generated by the plant due to an accident. The compensatory charges replenish the reservoir. The digital controller may use a sectionally linear transfer function with a maximum to control the compensatory charges based on the contingency discharges. The transfer function may be balanced using a trim function so that on average, the compensatory charges will make up for the contingency discharges. |
| US10164460B2 |
Wireless charging device, wireless charging case and method of wireless charging with frequency or position adjustment according to detected temperature
A wireless charging device, a wireless charging case and a wireless charging method thereof are provided. The wireless charging device includes a wireless signal transmitter, a controller and a temperature sensor. The wireless signal transmitter is configured to transmit an electromagnetic signal. The controller is coupled to the wireless signal transmitter. The temperature sensor is coupled to the controller. The temperature sensor is configured to detect an ambient temperature to obtain a temperature sensing value. The controller controls the wireless signal transmitter to adjust a frequency or a transmitting position of the electromagnetic signal according to the changing state of the temperature sensing value. |
| US10164455B2 |
Charging management apparatus, charging apparatus, and charging management method
A charging management apparatus, a charging apparatus, and a charging management method are disclosed. The charging management apparatus includes: a circuit board; a wireless communication module, connected to the circuit board and used to perform wireless communication with an intelligent terminal; and a current sensing module and/or a voltage sensing module, connected to the circuit board. The current sensing module is used to sense a charging current, and the voltage sensing module is used to sense a charging voltage. The charging apparatus includes the charging management module. The charging management method includes acquiring parameters of a charging apparatus and parameters of an intelligent terminal to be charged and correspondingly displaying the parameters; and issuing a prompt when a battery power of the charging apparatus and/or the intelligent terminal reaches a preset threshold. |
| US10164451B2 |
Shopping cart power generation
A shopping cart that generates power, and comprising a shopping cart body; a set of wheels that each rotates about an axle coupled to the shopping cart body; a power generator that generates a source of power from a rotational force of the wheels when a user moves the shopping cart; a voltage regulator that controls the source of power output from the power generator; and an outlet for outputting the controlled power to an electronic device. |
| US10164448B2 |
Power conversion system
When a plurality of storage batteries is used by connecting them in parallel, since the progress of degradation differs among the storage batteries, a power conversion system includes a degradation information acquisition device for acquiring the degradation information of the storage batteries, a temperature information acquisition device for detecting the temperature information of the storage batteries, and a control device for controlling the storage battery power converter based on the degradation information of the storage batteries by the degradation information acquisition device and the temperature information of the storage batteries by the temperature information acquisition device so that the degradation states of the plurality of the storage batteries can be matched. |
| US10164447B2 |
Semiconductor chip, semiconductor device and battery pack
To provide a semiconductor product high in versatility.A common drain pad is formed over the surface of a semiconductor chip together with source pads and gate pads of discharging and charging power transistors. Thus, when the semiconductor chip is face-down mounted over a wiring board, not only the source pads and gate pads of the discharging and charging power transistors, but also the common drain pad is electrically coupled to wirings of the wiring board. |
| US10164445B2 |
Electric power system and control method therefor
An electric power system includes a relay which is switched between an on state in which charging/discharging of a battery is permitted and an off state in which charging/discharging of the battery is inhibited, and an electronic control unit which controls switching of the relay between an on state and an off state based on a command from an electronic control unit. When a command for switching the relay from the on state to the off state is given from the electronic control unit to the electronic control unit, in a case where an abnormality occurs in the electronic control unit or in a case where an abnormality occurs in communication between the electronic control unit and the electronic control unit, the electronic control unit switches the relay to the off state. |
| US10164443B2 |
Method of controlling frequency of power system
Disclosed is a method of controlling frequency of a power system by which a frequency of a power system is regulated using high-speed charging and discharging characteristics of a plurality of energy storage systems (ESSs) and a battery state of charge (SOC), the method including: an operation of comparing, by a control unit, first time information and second time information and performing an exit control mode when the first time information (Before_Exit_time) is equal to or less than the second time information (After_Exit_time); an operation of determining, the control unit, an output amount for each ESS for discharging batteries using a battery discharging amount determining function (Exit_control_output( ) function) when a first parameter value (D_time) preset in the exit control mode is a positive value greater than zero and the second time information (After_Exit_time) is equal to or less than a second parameter value (Clear_time); and an operation of discharging, by the control unit, batteries until the frequency is out of a normal range, when an allocated amount of output for each ESS is calculated. |
| US10164438B2 |
Power-supply device determination apparatus, power-supply device determination method, and power conversion apparatus
Provided is a determination apparatus and determination method for automatically determining the types of power-supply devices connected, in a power conversion apparatus employing a DC link. The determination apparatus includes: a plurality of connectors that may be connected with the plurality of power-supply devices; a plurality of voltage transducers connected in series with the plurality of connectors; a voltage measuring part configured to measure output voltage values having passed through the plurality of voltage transducers; and a controller determining the plurality of power-supply devices, based on the output voltage values measured by the voltage measuring part when the plurality of voltage transducers have the same step-up ratio, to thereby automatically determine the power-supply devices connected thereto. |
| US10164437B2 |
Module for storing/drawing electricity in/from an electric accumulator applicable to photovoltaic systems, a photovoltaic system and a method of upgrading a photovoltaic system
The module according to the present invention is used for accumulating/drawing electricity in/from an electric accumulator (502); the module comprises first terminals and second terminals; the first terminals are adapted to be connected to a photovoltaic panel (501) and to an inverter (504), and the second terminals are adapted to be connected to the electric accumulator (502); the module comprises a conversion unit (503) adapted to be connected between the first terminals and the second terminals; the conversion unit (503) comprises, in turn, a two-way DC/DC converter (550) adapted to convert a first energy flow generated by the photovoltaic panel (401, 501) to store it in the accumulator (502) and a second energy flow drawn from the accumulator (502) to supply it to the inverter (504), the two-way DC/DC converter (450, 550) is configured to convert said first energy flow and said second energy flow in a selective manner. The module is characterized in that comprises: power detector means (507) adapted to be connected between a user arrangement (520), which comprises the inverter (504), in particular of the type with MPPT, and a user (506), and a public electric grid (508), and adapted to detect the power flowing between the user arrangement (520) and the public electric grid (508) and vice versa between the public electric grid (508) and the user arrangement (520); the conversion unit (403, 503) comprises a control unit (501) connected to the power detector means (507) and adapted to control the two-way DC/DC converter (550) as a function of signals generated by the power detector means (507). By means of such a module, it is possible to upgrade a photovoltaic system so as to minimize the electricity exchanges between the photovoltaic system and the public electric grid. |
| US10164434B2 |
Methods and systems for power injection or extraction in a power network
Systems and methods for injecting power into or extracting power out of a power network are provided. In a method, Thevenin parameters, in the form of at least a Thevenin voltage and a Thevenin resistance, of an equivalent Thevenin circuit are obtained with respect to each wire of the PCC. A total Thevenin power for all the wires is obtained, based on a specific amount of power at the PCC and the obtained Thevenin parameters. The method calculates an optimal current to be injected into or extracted from the PCC so as to inject or extract a specific amount of power. The calculation is based on the total Thevenin power and the Thevenin parameters. The method controls an injection or extraction of current at the PCC in accordance with the optimal current. |
| US10164432B2 |
Systems, methods, and apparatus for powering devices using energy from a communication bus
In some embodiments, an apparatus includes a power source, a communication bus, a first electrical component connected to the power source and the communication bus, and a second electrical component connected to the communication bus. In such embodiments, the second electrical component can be to be powered by the communication bus such that performance of the communication bus does not fall below a specified performance for the communication bus. |
| US10164429B1 |
Electrical power plant
An Electrical Power Plant (EPP) derives power through a semi-cone roof and platform serving as a source of distributed electrical/storage energy. Electric power is generated through renewable resource systems mounted upon and within the semi-cone roof. Two paths generate electrical power/heat. A Direct path uses solar panels and wind turbines. An Indirect path has a Compact Solar Heat Generator (CSHG) that generates electrical power and/or heat through a High Temperature Electrolysis (HTE) system to produce hydrogen and oxygen which are fed into Fuel Cells to produce electrical power, pure water and waste heat. The waste heat and pure water are then fed into the Computer Distributer Controller Tank (CDCT) as part of cogenerated energy. These paths are the power input to the EPP that provides a distributed source of electrical/storage power. The CDCT also provides a path for hot water to the Hot Water Heater or Boiler. |
| US10164422B2 |
Protection circuit for low voltage devices driven by a high voltage circuit
A method and system for protecting low voltage devices driven by a high voltage circuit is disclosed. The method comprises monitoring an output voltage, from a high voltage block, to a low voltage block. The method further comprises comparing the output voltage with a range of voltages allowable for driving the low voltage block. The range of voltages may be pre-defined or dynamically determined. Furthermore, the method comprises operating a first set of switches and a second set of switches. The first set of switches are operated to feed voltage from the high voltage block to input of the low voltage block, and the second set of switches are operated to feed a plurality of reference voltages to the input of the low voltage block. |
| US10164412B1 |
Switchgear with a two-high circuit interrupter configuration
An apparatus includes a housing, at least one first gas-insulated circuit interrupter in the housing and at least one second gas-insulated circuit interrupter disposed in the housing above the at least one first gas-insulated circuit interrupter. The at least one first gas-insulated circuit interrupter and the at least one second gas-insulated circuit interrupter may be housed in respective ones of a first gas containment compartment and a second gas containment compartment vertically arranged in the housing. At least one first bus may be coupled to the at least one first gas-insulated circuit interrupter and at least one second bus may be coupled to the at least one second gas-insulated circuit interrupter. The buses may be disposed between the first and second gas-insulated circuit interrupters. |
| US10164409B2 |
Semiconductor light-emitting device and method for manufacturing the same
A method for manufacturing a semiconductor light-emitting device includes: forming a plurality of guide grooves so as to be depressed from a surface of a semiconductor structure layer toward a semiconductor substrate and to align and extend along a direction perpendicular to an extending direction of a plurality of line electrodes; forming, in each of the plurality of guide grooves, a scribe groove so as to be depressed from a bottom surface of the guide groove toward the semiconductor substrate and to extend along an extending direction of the guide groove; and dividing a semiconductor wafer along the plurality of guide grooves. The guide groove and the scribe groove are formed to have end shapes in such a manner that inner walls thereof project toward each other in the extending direction of the scribe groove. |
| US10164398B2 |
Efficient lasing with excited-state absorption-impaired materials
Laser signal intensity is resonantly enhanced within a laser cavity to be greater than a pump intensity. This enables the suppression of excited-state absorption and is applicable to terbium-doped fiber lasers, lambda-type materials, or other materials used in lasers. In other embodiments, ESA is suppressed by de-populating the higher excited state using a resonant cavity. |
| US10164395B2 |
Electrical disconnection tools for disconnecting a battery
A tool for disconnecting a battery from an electrical connector pad, the tool having a body connected to at least three prongs, including a first outer prong, a second outer prong, and a middle prong. Each prong has a proximal portion connected to a distal portion by a sloped portion. The middle prong may have a side extension, including a side extension proximal portion, a side extension sloped portion, and a side extension distal portion. The tool may be part of kit comprising at least one battery adapted to be disconnected using the tool. |
| US10164392B1 |
Tow vehicle electric connector system and method
A towing vehicle/towed vehicle connection system for operably electrically coupling a towing vehicle to a towed vehicle, the system includes a first transceiver disposed on the towing vehicle to provide a wireless electric power signal. A second transceiver is disposed on the towed vehicle and is wirelessly coupled to the first transceiver to receive the wireless electric power signal. The second transceiver is further coupled to the provide energizing electric power to the towed vehicle. |
| US10164383B2 |
Fast plug connector for use with copper wire
Disclosed is a fast plug connector for use with copper wire, including an integrally-formed plastic-molded connector housing. The housing includes at least two terminal receiving slots juxtaposed inside the housing. The terminal receiving slots is embedded with engaging terminals having barbed pieces mounted at both tail ends thereof and twisted elastic sheets mounted at both head ends thereof. The upper end located at the left side and the right side of the head of the connector housing is mounted with fastening clamps, and a lower end located at the left side and the right side of the head of the connector housing is mounted with fastening holes that are respectively corresponding to the fastening clamps. The invention provides an electric connection using fast plug electrical connector that can be readily adapted for copper wires. |
| US10164379B2 |
Electrical receptacle connector with improved durability and shielding performance
An electrical receptacle connector includes a mount member, an insulated housing, first receptacle terminals, second receptacle terminals, and a shielding plate. The insulated housing is molded with the mount member and forms a tongue portion. Each of the first receptacle terminals includes a first flat contact portion and a first tail portion. The first flat contact portion is on a lower surface of the tongue portion, and front ends of the first flat contact portions are held in the tongue portion. Each of the second receptacle terminals includes a second flat contact portion and a second tail portion. The second flat contact portions are on an upper surface of the tongue portion, and front ends of the second flat contact portions are held in the tongue portion. The shielding plate is on the tongue portion and between the first receptacle terminals and the second receptacle terminals. |
| US10164378B2 |
Grounding for high-speed connectors
To address the issue of radio frequency interference with high-speed connectors, a communication port connector for use in a computing device is provided. The communication port connector may include a shell that defines a void that is configured to receive an electrical plug. Port-side electrical contacts in the shell may be configured to make electrical connections with plug-side electrical contacts. One or more double leaf spring fingers may be formed in a side of the shell, with each double leaf spring finger including a first spring finger coupled to a second spring finger. The first spring finger may be configured to contact the electrical plug, and the second spring finger may be configured to contact a chassis of the computing device, thereby creating a ground path to ground the electrical plug to the primary ground plane of the device when it is inserted into the communication port connector. |
| US10164371B2 |
Waterproof electrical connector with retainer for terminal
A waterproof connector includes male terminals (20) each of which has a box-shaped body (21) and a tab-shaped contact (22) that projects forward from a front end of a box-shaped body (21). The connector also has an outer housing (40) and an inner housing (30) accommodated in the outer housing (40). A terminal accommodating portion (34) is formed in the inner housing (30). A retainer (70) is mounted into the terminal accommodating portion (34) and includes a lock (71) configured to lock rear ends of the bodies (21) accommodated in the terminal accommodating portion (34). A seal seals the interior of the outer housing (40). The retainer (70) includes a releasing portion (72) projecting forward of the terminal accommodating portion (34). The inner housing (30) includes a protection wall (38) between the contact portions (22) of the male terminals (20) and the releasing portion (71). |
| US10164368B1 |
Adapter and using method thereof
An adapter including an accommodating element, a driving element having a driving unit, and multiple electrical connectors is provided. The accommodating element has a first space and multiple second spaces. The driving element is sleeved to the accommodating element along an actuating axis. The driving unit has a first electrical connecting portion. In a storage state, the driving unit is stored in the first space, and the electrical connectors are stored in the second space. In an operating state, the first electrical connecting portion of the driving unit is coupled to one of these electrical connecters. Then, the driving unit can enter the second space where the electrical connector stays originally, and at least part of the electrical connector is pushed out of the accommodating element. A using method of the adapter is provided. |
| US10164366B2 |
Connector terminal and electric connector
A connector terminal includes a contact portion to be contacted with a counter connector terminal, a hold portion held in a connector housing, and a coupling portion coupling the contact portion and the hold portion, the coupling portion being configured as a rectangular tube with four bending portions and having a single continuous band portion from the contact portion to the hold portion by having notches staggered from the contact portion toward the hold portion, each of the notches including an oblique part that extends to cross over adjacent two of the four bending portions, the oblique part of an odd numbered notch being slanted in a direction from the contact portion toward the hold portion as approaching a tip from an entrance thereof, an even numbered notch being slanted in a direction from the hold portion toward the contact portion as approaching a tip from an entrance thereof. |
| US10164363B2 |
Double-sided card edge connector
To prevent an increase of the number of kinds of components required for offset arrangement, an increase in risk of assembly error and extra time and effort for parts management, in a connector including mutually facing terminal members with contacting portions being offset in the insertion direction. Mutually facing terminal members 20 are formed on components identical in shape. The mutually facing terminal members 20 are secured to a connector housing 12 while being offset in an insertion direction of a double-sided card edge 102 inserted into a receptacle compartment 14 of the connector housing 12. |
| US10164361B2 |
Separator for electrical assembly
A separator is configured to separate first and second printed circuit boards that are in electrical communication with each other through first and second pluralities of electrical connectors that are mounted to the first and second substrates, respectively, and mated to each other. |
| US10164356B2 |
Tap clamp for receiving electrical conductors
A clamp provides electrical communication between a first conductor and a second conductor. The clamp includes a first housing portion having a first surface, a second surface, a first housing bore, and a cavity, the first housing bore extending along a longitudinal axis. The clamp further includes a clamp member at least partially disposed within the cavity of the first housing portion, the clamp member including a first clamp surface adjacent the second surface of the housing in a facing relationship. The clamp further includes a shaft oriented parallel to the longitudinal axis, the shaft coupling the first housing portion and the clamp member. The clamp further includes a second housing portion movably coupled to the first housing portion by the shaft, the second housing portion including a second housing bore and a second clamp surface, the second housing bore aligned with the longitudinal axis, the second clamp surface adjacent the first surface of the first housing portion in a facing relationship. |
| US10164355B2 |
Motor drive device
This motor drive device includes a first motor driving unit, a first terminal block 11 attached to the first motor driving unit, a second motor driving unit, a second terminal block attached to the motor driving unit, a first short bar whose one end portion is attached to the first terminal block so that the first short bar can be rotated around a first axis line, and a second short bar whose one end portion is attached to the first terminal block so that the second short bar can be rotated around a second axis line, the other end sides thereof can be placed at a connection position so that the other end sides can be connected to the second terminal block, and at a retract position which is distant from the second terminal block by rotation of the first and the second short bars. |
| US10164354B2 |
Terminal block apparatus
An example terminal block includes an annular arrangement of terminal pairs. Each of the terminal pairs has a first height and is adjacent another terminal pair having a second height different from the first height. |
| US10164353B2 |
Waterproof connector
To simplify an assembling process and reduce a height while keeping a reliable waterproof structure by improving structures of a housing and an elastic body. Provided are an insulative housing 31, an insulative elastic body 40 which is held by the housing 31, and terminal pins 50 which penetrate through the elastic body 40 and are held by the housing 31. The insulative elastic body 40 has an outside elastic portion 41 and inside elastic portions 42 into which the insulative elastic body 40 is partitioned by the housing 31 and link portions 45 which link the outside elastic portion 41 to the inside elastic portions 42. The housing 31 is provided with wall portions 35 with which the inside elastic portions 42 through which the respective terminal pins 50 penetrate are in contact in a compressed state. |
| US10164349B2 |
Connection terminal having at least two spring-force clamping connections
A connection clamp for connecting at least two electrical conductors to one another, having an insulating housing with at least one first and one second conductor insertion opening that are arranged on mutually opposite sides of the insulating housing. A first spring-force clamping connection for electrically contacting a first electrical conductor inserted through the first conductor insertion opening and a second spring-force clamping connection for electrically contacting a second electrical conductor inserted through the second conductor insertion opening are provided. The first spring-force clamping connection is electrically connected to the second spring-force clamping connection via a bus bar. The first spring-force clamping connection has at least one first clamping spring for clamping the first electrical conductor against a first clamping point of the bus bar, the second spring-force clamping connection has a clamping leg for clamping the second electrical conductor against a second clamping point of the bus bar. |
| US10164346B2 |
Multiple-input multiple-output (MIMO) omnidirectional antenna
The present invention relates to a Multiple-Input Multiple-Output (MIMO) omnidirectional antenna comprising three or more column sets arranged in a centrosymmetricly. Each column set comprises two or more antenna columns, each having a plurality of radiators mounted thereon. Each antenna column receives no more than two signals to be transmitted, and is arranged axisymmetricly about a radially-directed axis created between the center point of the antenna and a transverse cross-sectional midpoint on the antenna column. Therefore, each radiation pattern established by each of the three or more column sets is centrosymmetric about the center point of the antenna and axisymmetric about the radially-directed axis. The MIMO omnidirectional antenna can fit within a radome of small diameter, while providing relatively uniform radiation plot coverage across a microcell where it is deployed. As no phase shifting is utilized, there is little ripple effect and all of the ports have a similar gain. |
| US10164345B2 |
Antenna arrangement
There is presented an antenna arrangement with P polarization directions. The antenna arrangement comprises M transmission (Tx) ports and N reception (Rx) ports, where M≠N. The antenna arrangement comprises an antenna panel divided into S subpanels, where S=max (M, N)/P. The subpanels are, for each polarization direction, operatively connected to separate radio chains for the N Rx ports if N>M or for the M Tx ports if M>N. |
| US10164343B2 |
Communication device
A communication device includes an antenna system. The antenna system at least includes a dual-polarized antenna, a reflector, a PIFA (Planar Inverted F Antenna), and a fork structure. The reflector is configured to reflect the radiation energy from the dual-polarized antenna. The PIFA is separated from the reflector. The fork structure is positioned between the reflector and the PIFA, and is coupled to the reflector or the PIFA. |
| US10164342B2 |
Compact WiFi antenna with a metamaterial reflector
A compact antenna for centimetric frequency bands includes an active planar element forming a radiator, coupled to an input of a receiver circuit and/or to the output of an emitter circuit, and a passive planar element forming a reflector. The passive planar element is formed by a periodic structure of the metamaterial type comprising a network of resonating cells, in particular cells of the complementary concentric slit-ring type Complementary Split-Ring Resonator (CSRR). A clip-shaped support made of a dielectric material supports the active planar element and the passive planar element. |
| US10164338B2 |
Multiple antennas configured with respect to an aperture
A device includes a first antenna and a second antenna. The first antenna may be configured to transmit or receive through an aperture provided by the device. The second antenna may include an array of a plurality of antenna elements configured to transmit or receive through the aperture. The plurality of antenna elements may overlap at least a portion of the first antenna. |
| US10164337B2 |
Antenna device
An antenna device of a magnetic coupling type includes a magnetic body having a plate-like shape; and a coil, which is wound around the magnetic body. |
| US10164336B2 |
Antenna device and electronic apparatus
An antenna device includes a planar coil, a planar conductor, a first power feed terminal, and a second power feed terminal. The planar conductor includes a cutout opposed to the planar coil that overlaps with a coil aperture. The planar coil includes a first conductor pattern portion and a second conductor pattern portion. The first power feed terminal is connected to a first end of the first conductor pattern portion and the second power feed terminal is connected to a first end of the second conductor pattern portion on a side adjacent to or in a vicinity of the first end of the first conductor pattern portion. Second ends of the first conductor pattern portion and the second conductor pattern portion are connected to the planar conductor. |
| US10164335B2 |
Unit cell filtering and diplexing for electronically scanned arrays
Electronically scanned array (ESA) antennas are disclosed. An antenna may include an electronically scanned array (ESA) panel. The ESA panel may include a plurality of transmit/receive (T/R) modules, and each T/R module of the plurality of T/R modules may be contained within a unit cell of the ESA panel, where the unit cell has a surface area constrained by a maximum operating frequency of the ESA panel. The antenna may also include at least one radio frequency (RF) filter positioned within each particular unit cell of the ESA panel. The at least one RF filter may be configured to provide RF filtering specifically for the T/R module co-located within that particular unit cell of the ESA panel. |
| US10164334B2 |
Antenna system calibration
A method for antenna calibration is disclosed, the method including driving calibration signals for antenna array beam calibration to an antenna array feeder line in a transceiver front end unit by using one or more directional couplers and/or radio frequency probes, wherein calibration signal paths are integrated inside the transceiver front end unit. Measurements are carried out on the calibration signals, between different antenna combinations inside the antenna array. Based on collected measurement data, calibration information is calculated for each measurement branch of the antenna array by using a mathematical formula. Active antenna array beam calibration is then performed based on the calculated calibration information. |
| US10164333B2 |
Short-range magnetic field system
A short-range magnetic field system according to an embodiment includes a transmission antenna part located at a transmission port; and a reception antenna part located at a reception port to face the transmission antenna part. wherein a magnetic field formed around the transmission antenna part or the reception antenna part can be offset. |
| US10164329B2 |
Wideband MIMO array with low passive intermodulation attributes
A wideband array capable of MIMO operation and possessing low Passive Intermodulation (PIM) characteristics is described for use in Distributed Antenna Systems (DAS) and other applications which require low PIM levels. The antenna can be configured to provide a narrow radiated beamwidth across multiple frequency bands and can support high power levels. A novel antenna design is implemented to populate the array configuration, wherein both fed and counterpoise elements are isolated from the ground plane to provide low PIM performance, while maintaining constant beamwidth across wide frequency ranges. |
| US10164327B2 |
Antenna device
Provided is an antenna device capable of simplifying a structure while preventing degradation of antenna performance even with an upright type double-case structure. An antenna device having a double-case structure includes an inner case inside of which a housing space is formed so as to house a coil element and the like therein, the inner case being covered with an outer case. An antenna element is provided between an outer surface of the inner case and an inner surface of the outer case. The antenna element is electrically connected to the coil element provided in the housing space while keeping water-tightness of the housing space. |
| US10164323B2 |
Mobile terminal
A mobile terminal, comprising of a terminal body having a front surface, a rear surface, and side surfaces extending from end portions of the rear surface toward the front surface, the terminal body being made of a metal, a lower module coupled to a lower end of the terminal body and externally exposed to operate as a radiator of an antenna apparatus and a non-metal member interposed between the terminal body and the lower module and forming a slot by spacing the terminal body and the lower module apart from each other, and wherein the antenna apparatus comprises first and second antenna resonating different frequency bands wherein the first antenna and the second antenna comprise a first feeder and a second feeder, respectively, connected to a main printed circuit board provided in the terminal body and generating the electric fields on the first slot and the second slot, respectively, and wherein the lower module comprises first and second member and a connecting portion connecting end portions of the first and second members each other, and wherein the first member is exposed to the front surface of the terminal body, the second member is exposed to the rear surface of the terminal body, and wherein the connecting portion, the first and second members are made of a metal. |
| US10164321B2 |
Wireless communication device
A compact wireless communication includes a first radiating element and a second radiating element, which define and function as a dipole antenna, a feeder circuit including a wireless IC chip coupled with the first and second radiating elements, and a feeder substrate that is provided with the wireless IC chip. The first radiating element is provided to the feeder substrate. The second radiating element is provided to a substrate other than the feeder substrate. |
| US10164319B2 |
Method and apparatus for optimal antenna alignment
An approach for determining remote terminal antenna alignment in a satellite communications system is provided. A point in time for an expected conjunction of an a remote terminal antenna, a satellite in communication with the remote terminal and the Sun is determined based on predetermined positional data. An interference level imposed by the Sun on communication signals between the antenna and the satellite is measured at a number of respective points in time. A one of the points in time is determined when the interference is at a peak level. Then information regarding alignment of the antenna with respect to the satellite is determined, wherein the determination of the antenna alignment information is based on a comparison between the one point in time of the peak interference level and the expected point in time of the conjunction of the antenna, the satellite and the Sun. |
| US10164312B2 |
Wiring board, electronic apparatus, and manufacturing method of wiring board
A wiring board includes: a first substrate that includes signal wiring; a second substrate that includes a conductor with an area larger than an area of the signal wiring, and projection formed on a face of the conductor and constituted of an insulator with a pattern corresponding to a pattern of the signal wiring, the second substrate being arranged so that the face of the conductor on which the projection is formed faces the signal wiring; and an intermediate layer that is arranged between the signal wiring and the conductor and includes a fibrous member. |
| US10164310B2 |
High-frequency transmission line
A first signal line is closer to a second ground conductor than a second signal line and, hence, crosstalk between the first and second signal lines is unlikely to be generated. By providing first opening portions in the second ground conductor, capacitive coupling between the first and second signal lines is reduced. Hence, in a transmission line including the first signal line, an increase in the capacitance due to the increased width of the first signal line is cancelled out by a decrease in the capacitance due to the increased distance from the first ground conductor and the first opening portions. Further, the width of the high-frequency transmission line need not be large. Further, since the capacitance is reduced by the first and second opening portions, the distances between the first ground conductor and the first and second signal lines are shortened. |
| US10164309B2 |
Dielectric resonator and dielectric filter
The present application provides a dielectric filter, including a body part, a dielectric resonator, a cavity is formed in the body part, and a support kit is disposed at a bottom of the cavity. The dielectric resonator, including a dielectric body and at least two adjusting holes disposed on the dielectric body, is contained in the cavity and is disposed on the support kit. The dielectric body has a first mirror plane and a second mirror plane, which are perpendicular to each other and penetrate through the top plane and the bottom plane of the dielectric body, and any two of the at least two adjusting holes are not mirror symmetric relative to the first mirror plane or the second mirror plane. |
| US10164306B2 |
Battery cell having inward extending cup edge and method of manufacture
An electrochemical battery cell is provided having a housing formed by a can and a cup, with a sealing gasket disposed therebetween. First and second electrodes and electrolyte are disposed within the housing. The cup has a peripheral wall and a cup edge portion that extends inward, away from the can wall at angle less than 180° relative to a longitudinal axis of the cell housing. The gasket likewise has a base that extends inward, and a surface of the cup edge portion is sealingly engaged with the gasket base. |
| US10164302B2 |
Process for recycling li-ion batteries
The present invention concerns a process for the recovery of metals and of heat from spent rechargeable batteries, in particular from spent Li-ion batteries containing relatively low amounts of cobalt. It has in particular been found that such cobalt-depleted Li-ion batteries can be processed on a copper smelter by: feeding a useful charge and slag formers to the smelter; adding heating and reducing agents; whereby at least part of the heating and/or reducing agents is replaced by Li-ion batteries containing one or more of metallic Fe, metallic Al, and carbon. Using spent LFP or LMO batteries as a feed on the Cu smelter, the production rate of Cu blister is increased, while the energy consumption from fossil sources is decreased. |
| US10164299B2 |
Flexible sensor module and manufacturing method thereof
A flexible sensor module, includes: a sensing unit formed on a first substrate so as to be exposed to the outside, and configured to measure external environment information; a solar cell disposed on the first substrate together with the sensing unit, and configured to generate a power by receiving light; a wireless communication unit disposed at one side on the first substrate, and configured to transmit the information measured by the sensing unit to an external server; and a chemical cell disposed at another side on the first substrate, charged by receiving the power from the solar cell, and configured to supply the power to the sensing unit and the wireless communication unit, wherein the solar cell includes: a compound layer disposed on the second substrate, and configured to generate the power to be supplied to the sensing unit by receiving light; and a metallic electrode formed on the compound layer. |
| US10164291B2 |
Electrolyte for electrochemical energy storage devices
An electrolyte for an electrochemical storage device is disclosed. In one embodiment, the electrolyte includes a lithium salt from about 3% to about 20% by weight, a primary solvent from about 15% to about 25% by weight, wide-temperature co-solvents from about 14% to about 55% by weight, interface forming compounds from about 0.5% to about 2.0% by weight, and a flame retardant compound from about 6% to about 60% by weight. The electrolyte interacts with the positive and negative electrodes of the electrochemical storage device to provide both high performance and improved safety such that the electrolyte offers adequate ionic conductivity over the desired operating temperature range, a wide electrochemical stability window, high capacities for both the cathode and anode, low electrode-electrolyte interfacial resistance, and reduced flammability. |
| US10164289B2 |
Vitreous solid electrolyte sheets of Li ion conducting sulfur-based glass and associated structures, cells and methods
A lithium ion-conductive solid electrolyte including a freestanding inorganic vitreous sheet of sulfide-based lithium ion conducting glass is capable of high performance in a lithium metal battery by providing a high degree of lithium ion conductivity while being highly resistant to the initiation and/or propagation of lithium dendrites. Such an electrolyte is also itself manufacturable, and readily adaptable for battery cell and cell component manufacture, in a cost-effective, scalable manner. |
| US10164288B2 |
Flexible battery, manufacturing method therefor, and auxiliary battery comprising flexible battery
A flexible battery is disclosed, which comprises an electrode assembly, and an exterior material for sealing the electrode assembly along with an electrolyte. Both the electrode assembly and the exterior material are formed such that patterns for contraction and extension with respect to the longitudinal direction have the same directionality in the event of being bent. |
| US10164282B2 |
Microbial fuel cells and methods for generating an electric current
A microbial fuel cell and a method for generating an electric current using the microbial fuel cell are disclosed. The microbial fuel cell comprises a housing provided with multiple cell compartments. The cell compartments includes an anode compartment having an anode in a side, and a cathode compartment having a cathode on another side separated by an ion exchange membrane. The anode is a carbon cloth modified with a graphene electrode comprising high-surface-area graphene nanoparticles attached to a biocatalyst. The cathode is a carbon cloth modified with a platinum electrode immersed in a medium. The anode and cathode are electrically connected to one another via a resistance to generate electricity. The large specific surface area and biocompatibility of the graphene anode in the microbial fuel cell increases the bacterial biofilm formation and charge transfer efficiency. |
| US10164280B2 |
Filtering device, in particular for the air to be supplied to a fuel cell
A filtering device features a carrier medium and activated carbon stratum as adsorbent and having a sealing closing over or sealing longitudinal and width sides of the activated carbon stratum all-around a periphery of the activated carbon stratum. |
| US10164279B2 |
Device for decreasing hydrogen concentration of fuel cell system
A device for decreasing hydrogen concentration of a fuel cell system is installed in an exhaust system for discharging exhaust gas which includes hydrogen and air and is discharged from fuel cells to the atmosphere through an exhaust line. The device includes a catalyst diluter having catalysts for diluting the hydrogen in an exhaust gas by generating a catalytic reaction and connected to the exhaust line. An air diluter is disposed outside the catalyst diluter and guides external air to a gas exit side of the catalyst diluter. |
| US10164277B2 |
Steam reformer bypass line and flow controller
A reformer unit and high temperature, pressure, or both variable orifice flow controller is provided. The reformer unit may have a reforming section, a heat exchanging section, and a bypass section. The bypass section provides a flow path for the hydrocarbon-containing fuel around the reforming section and has a variable orifice flow controller positioned in the bypassing flow path. |
| US10164276B2 |
Fuel cell device
A fuel cell device is improved for operating conditions during a partial load operation. The fuel cell device comprises a cell stack formed by electrically connecting fuel cells for generating power by fuel gas and oxygen-containing gas; a fuel gas supply unit for supplying the fuel gas to the fuel cells; and a power adjustment unit for adjusting the amount of current that is supplied to an external load and a controller for controlling the fuel gas supply unit and the power adjustment unit. The controller adjusts, during the partial load operation of the fuel cell device and when the fuel gas supplied to the cell stack is at low flow rate. The a relationship between a fuel utilization rate of the cell stack and the amount of power generated by the cell stack can be nonlinear. |
| US10164274B2 |
Active cathode temperature control for metal-air batteries
A metal-air battery is disclosed, including a cathode temperature controller that identifies a power-boosted operating temperature at which a projected power boost exceeds a projected battery lifetime penalty and a temperature regulator that adjusts the cathode temperature to the power-boosted operating temperature using power generated by the metal-air battery when the metal-air battery is in a discharge state. |
| US10164273B2 |
Apparatus and method for heating a fuel cell stack
An apparatus for heating a fuel cell stack in a cold start mode is provided. The apparatus comprises a fuel cell stack, a boost converter, and a controller. The fuel cell stack powers a vehicle. The boost converter includes a power switch that is thermally coupled to the fuel cell stack. The controller is configured to receive a signal indicative of a temperature during a vehicle startup and to compare the temperature to a predetermined temperature value. The controller is further configured to activate the power switch if the temperature is below the predetermined temperature value such that the power switch generates heat to apply to the fuel cell stack and generates a voltage for powering a power circuit to enable the vehicle to driveaway while the fuel cell stack receives the heat. |
| US10164271B2 |
Polymer electrolyte fuel cell with a recess is formed downstream of a gas lead-out port
A polymer electrolyte fuel cell according to the present invention includes: a unit cell including a membrane-electrode assembly and a pair of separators; a manifold; a gas introducing member; and a first member. A recess is formed at a gas lead-out port side of the gas introducing member so as to be connected to the gas lead-out port. The first member is provided such that a communication portion thereof communicates with the manifold. The gas introducing member is provided such that: the recess communicates with the communication portion; and when viewed from a thickness direction of the polymer electrolyte membrane, the gas lead-out port and a main surface of the first member overlap each other. |
| US10164270B2 |
Gas storage system
Among other things, a gas storage system includes a group of capsules and an activation element coupled to the group. The group of capsules are formed within a substrate and contain gas stored at a relatively high pressure compared to atmospheric pressure. The activation element is configured to deliver energy in an amount sufficient to cause at least one of the capsules to release stored gas. |
| US10164267B2 |
Reduced-weight fuel cell plate with corrosion resistant coating
The disclosed embodiments provide a fuel cell plate. The fuel cell plate includes a substrate of electrically conductive material and a first outer layer of corrosion-resistant material bonded to a first portion of the substrate. To reduce the weight of the fuel cell plate, the electrically conductive material and the corrosion-resistant material are selected to be as light as practicable. |
| US10164264B2 |
Method and apparatus for manufacturing a fuel cell electrode
A method of manufacturing a fuel cell electrode includes stamping an electrode workpiece (50, 50′) in a sequence configured to control and/or reduce material growth, such as stamping discrete sections of the electrode workpiece in a sequential order. The method can employ a die with a die face (18, 18′) having a plurality of projections (24, 24′), wherein each projection has a top surface (26, 26′) with a concave curve along at least one plane to control and/or reduce material growth during a stamping operation. |
| US10164261B2 |
Multifunctional web for use in a lead-acid battery
The present invention relates to a multifunctional web for use in a lead-acid battery comprising natural fibers and heat-sealable fibers, the use of the multifunctional web in a lead-acid battery, a lead plate comprising a metal grid coated with a lead paste contacting the multifunctional web, a method of preparing the lead plate and a lead-acid battery assembly comprising the lead plate. |
| US10164258B2 |
Fused-ring quinone-substituted polynorbornene, electrode active material and secondary battery
A fused-ring quinone-substituted polynorbornene has recurring units of formula (1) and/or (2) below. In formulas (1) and (2), A1 is independently a substituent of formula (3) or (4) below, n is an integer from 1 to 6, and A2 is a substituent of formula (5) or (6) below. In formulas (3) to (6), each X is independently a single bond or a divalent group, and Ar1 and Ar2 are each independently an aromatic hydrocarbon ring or an oxygen atom or sulfur atom-containing aromatic heterocycle that forms together with two carbon atoms on a benzoquinone skeleton. This polymer has charge-storing properties and, when used as an electrode active material, is capable of providing a high-performance battery possessing high capacity, high rate characteristics and high cycle characteristics. |
| US10164252B2 |
Composite anode active material, method of preparing the same, and anode and lithium secondary battery including the composite anode active material
A composite anode active material includes a metal silicide core, a silicon shell, and a metal nitride and a carbon material that are dispersed in at least one surface of the silicon shell. |
| US10164247B2 |
Sulfur-carbon composite, nonaqueous electrolyte battery including electrode containing sulfur-carbon composite, and method for producing sulfur-carbon composite
A sulfur-carbon composite in which sulfur is combined with porous carbon is provided. In the sulfur-carbon composite, a mass loss ratio X at 500° C. in thermal mass analysis and a mass ratio Y of sulfur/(sulfur+carbon) in an observation visual field at a magnification of 1000 in SEM-EDS quantitative analysis satisfy the relationship of |X/Y−1|≤0.12, and porous carbon has a mean pore diameter of 1 to 6 nm, and a specific surface area of 2000 m2g−1 or more and 3000 m2g−1 or less. |
| US10164246B2 |
Sulfur-carbon composite and preparing method thereof
The present disclosure relates to a sulfur-carbon composite and a preparing method thereof, and more particularly, to a sulfur-carbon composite having an aggregated structure by performing a pressure heat treatment on a mixture of a carbonaceous conductive material and a sulfur-containing amorphous carbon material and carbonizing the same, and a preparing method thereof. |
| US10164245B2 |
High performance silicon electrodes having improved interfacial adhesion between binder, silicon and conductive particles
Methods for making a negative electrode material for use in an electrochemical cell, like a lithium ion battery, are provided. The electroactive material includes a functionalized surface having a grafted reactive group (e.g., an amino group, a carboxyl group, an anhydride group, and the like). The electrically conductive material includes a functionalized surface having a grafted reactive group (e.g., an amino group, a carboxyl group, and the like). The functionalized electroactive material and the functionalized electrically conductive material is admixed and reacted with at least one binder precursor having a reactive group (e.g., an amino group, an anhydride group, and the like). A porous solid electrode material is thus formed. Negative electrodes are also provided, which provide significant performance benefits and reduce the issues associated with capacity fade, diminished electrochemical cell performance, cracking, and short lifespan associated with conventional silicon anode materials. |
| US10164244B2 |
Negative-electrode mixture for non-aqueous electrolyte secondary cell, negative electrode for non-aqueous electrolyte secondary cell containing said mixture, non-aqueous electrolyte secondary cell provided with said negative electrode, and electrical device
A negative electrode mixture for a nonaqueous electrolyte secondary cell according to the present invention includes: a negative electrode active material; a conductive assistant; and a binder. The binder contains a copolymer of vinyl alcohol and an alkali metal-neutralized product of ethylene-unsaturated carboxylic acid. |
| US10164242B2 |
Controlled porosity in electrodes
Porous electrodes in which the porosity has a low tortuosity are generally provided. In some embodiments, the porous electrodes can be designed to be filled with electrolyte and used in batteries, and can include low tortuosity in the primary direction of ion transport during charge and discharge of the battery. In some embodiments, the electrodes can have a high volume fraction of electrode active material (i.e., low porosity). The attributes outlined above can allow the electrodes to be fabricated with a higher energy density, higher capacity per unit area of electrode (mAh/cm2), and greater thickness than comparable electrodes while still providing high utilization of the active material in the battery during use. Accordingly, the electrodes can be used to produce batteries with high energy densities, high power, or both compared to batteries using electrodes of conventional design with relatively highly tortuous pores. |
| US10164241B2 |
Electrode material for lithium-ion rechargeable battery and method for manufacturing same
An electrode material for a lithium-ion rechargeable battery of the present invention is an electrode material for a lithium-ion rechargeable battery formed by coating a surface of an electrode active material represented by General Formula LiFexMn1-x-yMyPO4 (here, M represents at least one element selected from Mg, Ca, Co, Sr, Ba, Ti, Zn, B, Al, Ga, In, Si, Ge, and rare earth elements, 0.05≤x≤1.0, 0≤y≤0.14) with a carbonaceous film, in which an angle of repose is in a range of 35° or more and 50° or less. |
| US10164238B2 |
Method for manufacturing battery protection device and battery protection device
The present invention relates to a method for manufacturing a battery protection device and a battery protection device manufactured by the method, and more particularly, a method for manufacturing a battery protection device and a battery protection device which reduce a defect rate and also the number of processes, thus enhancing productivity. |
| US10164237B2 |
Air battery cell with electrically conductive members and battery pack
An air battery includes: a cell frame of an insulating material having a bottomed frame shape in which an electrolytic solution and an anode are stored; a cathode that is disposed opposite the anode across the electrolytic solution stored in the cell frame; and a current collecting member that is electrically connected to the anode, wherein the anode and the current collecting member are electrically connected to each other via a plurality of electrically conducting members that penetrate a bottom of the cell frame. |
| US10164236B2 |
Battery pack
There is provided a battery pack with improved stability. The battery pack includes a plurality of bare cells including electrode units and arranged in a direction, a holder case configured to accommodate the plurality of bare cells, and a connection tab including a body unit electrically connected to the plurality of bare cells, a slit unit positioned in each of the electrode units of the plurality of bare cells, and at least one welding unit positioned to be adjacent to the slit unit and welded to the electrode unit of the bare cell. The slit unit includes first and second slits separated from each other by a certain distance, first and second bridges respectively provided between ends of the first and second slits, and a welding slit that crosses one point of each of the first and second slits. In the battery pack, one of the first and second bridges is formed to be stepped so that it is possible to rapidly and easily block flow of a current when over-charge or over-discharge occurs. Therefore, stability of the battery pack may improve. |
| US10164235B2 |
Battery assembly including multi-row battery interconnection member
The present disclosure is directed toward apparatuses for packaging one or more cells in a larger battery pack, and apparatuses for electrically coupling a battery management system to the one or more cells in a battery pack. In the aspect of the present disclosure directed toward a battery packaging apparatus with integrated spring contacts, an electrically conductive element has first and second surface a, with the first surface electrically coupled to a first battery, and a first spring-like element that is coupled to the first face of the electrically conductive element. The electrically conductive element has a cross section such that the second surface contacts the spring-like element in first and second areas. The spring-like element is operable for providing a force on the electrically conductive element when the first area is translocated toward the second area. |
| US10164234B2 |
Separator roll and method of producing same
A separator roll etc. capable of reducing meandering is provided. The separator roll includes a core and a battery separator wound around the core. The core has an axis hole along a central axis of the core. A value, obtained by dividing a difference between a diameter of the core and a diameter of the axis hole by a width of the core in a direction of the central axis, is not less than 0.3 and not more than 1.5. |
| US10164230B2 |
Separator including microbial cellulose, method of producing the separator, and use of the separator
Provided is a separator including microbial cellulose, a battery comprising the separator, and a method of producing the separator. |
| US10164219B2 |
Peeling method
To improve the yield in a peeling process and improve the yield in a manufacturing process of a flexible light-emitting device or the like, a peeling method includes a first step of forming a peeling layer over a first substrate, a second step of forming a layer to be peeled including a first layer in contact with the peeling layer over the peeling layer, a third step of curing a bonding layer in an overlapping manner with the peeling layer and the layer to be peeled, a fourth step of removing part of the first layer overlapping with the peeled layer and the bonding layer to form a peeling starting point, and a fifth step of separating the peeling layer and the layer to be peeled. The peeling starting point is preferably formed by laser light irradiation. |
| US10164217B2 |
Method of manufacturing array substrate having OLED connected to TFT substrate with a conductive bridge
An array substrate, a manufacturing method thereof and a display device are provided. The array substrate comprises a base substrate (1), an organic light-emitting diode (OLED) device and a thin-film transistor (TFT) structure, the OLED device disposed on one side of the base substrate (1); the TFT structure disposed on the other side of the base substrate (1); a through hole formed on the base substrate and provided with a conductive bridge (2); and the OLED device connected with the TFT structure through the conductive bridge (2). The array substrate can avoid electrical interference of the TFT structure on the OLED device, and hence accurate drive for the OLED device can be achieved; as the OLED device can be directly formed on a surface of the base substrate, surface treatment of a pixel electrode is saved with respect to conventional OLED display device, and hence manufacturing process can be accelerated and manufacturing cost can be reduced; and as both an anode and a cathode of the OLED device are made from transparent materials, double-sided light emission can be achieved in the array substrate, and hence double-sided display can be achieved in the array substrate. |
| US10164216B2 |
Base substrate with polymer material having a gradient distribution for organic light emitting diode
The present application discloses an organic light emitting diode base substrate including a support substrate and a light outcoupling layer on the support substrate for enhancing light outcoupling efficiency of an organic light emitting display substrate, the light outcoupling layer having a corrugated surface on a side of the light outcoupling layer distal to the support substrate. The light outcoupling layer including a polymer material having a gradient distribution in a direction from the corrugated surface to the support substrate. |
| US10164213B2 |
Flexible display panel, method for fabricating the same, and apparatus for forming the same
The present disclosure provides a method for bonding an integrated circuit (IC) chip onto a flexible display body. The method includes providing a substrate having a flexible display body thereon, and aligning a first stiffening component with the flexible display body having an IC bonding region. The method further includes attaching the first stiffening component onto a front surface of the flexible display body, and separating the substrate from the first stiffening component and the flexible display body to expose a back surface of the flexible display body; and bonding an IC chip onto the IC bonding region. |
| US10164208B2 |
Foldable display device
Disclosed is a foldable display device capable of preventing distortion of a folding part of a display screen due to deformation of the folding part. The foldable display device includes a display panel including a folding part and non-folding parts, and a back cover attached to the rear surface of the display panel via an adhesive layer, wherein the back cover includes folding patterns and open patterns, both of which are disposed at the folding part, and unevenness compensation patterns disposed on areas of a surface of the back cover contacting the adhesive layer, the areas of the surface of the back cover corresponding to the non-folding parts. The unevenness compensation patterns may be a plurality of open patterns, which are fully formed through the back cover, or may be a plurality of grooves, which are not fully formed through the back cover. |
| US10164207B2 |
Organic light-emitting device and method for manufacturing same
An exemplary embodiment of the present invention provides a method for preparing an organic light-emitting device, comprising the steps of: 1) forming a spacer pattern on a first electrode formed on a substrate; 2) forming an organic material layer and a second electrode; 3) exposing the first electrode by forming an encapsulation thin film and then etching at least one portion of the encapsulation thin film; and 4) forming an auxiliary electrode which is electrically connected to the first electrode exposed in the step 3). The organic light-emitting device according to the exemplary embodiment of the present invention may solve problems of a voltage drop due to resistance of a transparent electrode in a longitudinal direction and of resultant brightness non-uniformity of the diode. |
| US10164206B2 |
Light-emitting element, light-emitting device, display device, electronic device, and lighting device
An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with the longest-wavelength-side local maximum peak of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power. |
| US10164205B2 |
Device including quantum dots
A device including an emissive material comprising quantum dots is disclosed. In one embodiment, the device includes a first electrode and a second electrode, a layer comprising quantum dots disposed between the first electrode and the second electrodes, and a first interfacial layer disposed at the interface between a surface of the layer comprising quantum dots and a first layer in the device. In certain embodiments, a second interfacial layer is optionally further disposed on the surface of the layer comprising quantum dots opposite to the first interfacial layer. In certain embodiments, a device comprises a light-emitting device. Other light emitting devices and methods are disclosed. |
| US10164204B2 |
OLED display device comprising red, green, and blue OLEDs with quantum dot material receiving and excited by blue light from blue OLED
The present invention provides an OLED display device, comprising a substrate, an OLED layer located on the substrate, and a quantum dot package layer covering the OLED layer, and the quantum dot package layer comprises quantum dot material; the blue light or the white light emitted by the OLED layer excites the quantum dot material of the quantum dot package layer to emit light to achieve the color display of the high color gamut while not adding additional structures, and the product competitiveness is high. |
| US10164203B2 |
Light-emitting element, light-emitting device, electronic device, and lighting device
A novel light-emitting element is provided. A light-emitting element that emits red light with high color purity and has high emission efficiency is provided. A full-color light-emitting device having low power consumption is provided. In the light-emitting element that exhibits white light emission, the emission wavelength range of red light is a specific range on the longer wavelength side than the conventional emission wavelength range of red light that is usually used, and an optical element having a specific transmittance in the specific wavelength range is used. |
| US10164200B2 |
Organometallic compound and organic light-emitting device including the same
An organometallic compound represented by Formula 1: M(L1)n1(L2)n2 Formula 1 wherein in Formula 1, M in Formula 1 is selected from iridium (Ir), platinum (Pt), osmium (Os), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), thulium (Tm), and rhodium (Rh), L1 in Formula 1 is selected from a ligand represented by Formula 2A or 2B as they are defined in the specification, and L2 in Formula 1 is selected from a mono-anionic organic ligand. |
| US10164198B2 |
Organometallic compound, composition containing organometallic compound, and organic light-emitting device including the same
An organometallic compound represented by Formula 1: wherein in Formula 1, R11 to R20, L11, m11, and n11 are the same as described in the specification. |
| US10164197B2 |
Organic electroluminescent device
An organic electroluminescent device having improved emission efficiency includes an anode, an emission layer, an anode-side hole transport layer between the anode and the emission layer and mainly including an electron accepting material, a middle hole transport material layer between the anode-side hole transport layer and the emission layer and including a middle hole transport material, and an emission layer-side hole transport layer between the middle hole transport material layer and the emission layer, adjacent to the emission layer and including an emission layer-side hole transport material represented by the following Formula 1. |
| US10164195B2 |
Organic light-emitting device
An organic light-emitting device including: a first electrode; a second electrode facing the first electrode; an emission layer between the first electrode and the second electrode; a hole transport region between the first electrode and the emission layer; and an electron transport region between the emission layer and the second electrode, wherein the emission layer includes a first compound represented by Formula 1A or 1B, and at least one selected from the hole transport region and the electron transport region includes a second compound represented by Formula 2A or 2B: |
| US10164194B2 |
Compound for organic electroluminescent device
The present invention discloses a compound is represented by the following formula (I), the organic EL device employing the compound as fluorescent host material, phosphorescent host material, can display good performance like as lower driving voltage and power consumption, increasing efficiency and half-life time. The same definition as described in the present invention. |
| US10164192B2 |
Solution process for fabricating high-performance organic thin-film transistors
The present invention relates to a solution or ink composition for fabricating high-performance thin-film transistors. The solution or ink comprises an organic semiconductor and a mediating polymer such as polyacrylonitrile, polystyrene, or the like or mixture thereof, in an organic solvent such as chlorobenzene or dichlorobenzene. The percentage ratio by weight of semiconductor: mediating polymer ranges from 5:95 to 95:5, and preferably from 20:80 to 80:20. The solution or ink is used to fabricate via solution coating or printing a semiconductor film, followed by drying and thermal annealing if necessary to provide a channel semiconductor for organic thin-film transistors (OTFTs). The resulting OTFT device with said channel semiconductor has afforded OTFT performance, particularly field-effect mobility and current on/off ratio that are superior to those OTFTs with channel semiconductors fabricated without a mediating polymer. |
| US10164190B2 |
Organic semiconductor compound and method for manufacturing the same
An organic semiconductor compound and a method for manufacturing the same is provided. The method for manufacturing the organic semiconductor compound may include stirring a solated organic semiconductor and a solated organometallic precursor. Herein, the manufacturing the organic semiconductor compound includes: forming a three-dimensional organic semiconductor compound by allowing the solated organic semiconductor to orthogonally penetrate one or more gaps in a lattice structure of a gelated organometallic precursor formed by stirring the solated organometallic precursor. |
| US10164188B2 |
Polymer-hybrid electro-optic devices and method of fabricating polymer-hybrid electro-optic devices
A polymer-hybrid electro-optic device is fabricated by providing a semiconductor substrate, depositing a metal electrode layer on the semiconductor substrate, depositing a dielectric barrier core layer within a gap of the metal electrode layer, patterning a polymer layer to cover the dielectric barrier core layer and partially covering the metal electrode layer, infiltrating the polymer layer with an inorganic component to form a hybrid oxide-polymer layer, and removing excess inorganic component from the semiconductor substrate and metal electrode layer. |
| US10164187B2 |
Methods, apparatuses, and circuits for programming a memory device
Subject matter described pertains to methods, apparatuses, and circuits for programming a memory device. |
| US10164186B2 |
Methods of operating memory devices and electronic systems
Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices. |
| US10164184B2 |
Resistance variable memory structure and method of forming the same
A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening. |
| US10164180B2 |
Variable resistance element and memory device
According to one embodiment, a variable resistance element includes first and second conductive layers and a first layer. The first conductive layer includes at least one of silver, copper, zinc, titanium, vanadium, chrome, manganese, iron, cobalt, nickel, tellurium, or bismuth. The second conductive layer includes at least one of platinum, gold, iridium, tungsten, palladium, rhodium, titanium nitride, or silicon. The first layer includes oxygen and silicon and is provided between the first conductive layer and the second conductive layer. The first layer includes a plurality of holes. The holes are smaller than a thickness of the first layer along a first direction. The first direction is from the second conductive layer toward the first conductive layer. The first layer does not include carbon, or a composition ratio of carbon included in the first layer to silicon included in the first layer is less than 0.1. |
| US10164179B2 |
Memristive device based on alkali-doping of transitional metal oxides
Embodiments are directed to a memristive device. The memristive device includes a first conductive material layer. An oxide material layer is arranged on the first conductive layer. And a second conductive material layer is arranged on the oxide material layer, wherein the second conductive material layer comprises a metal-alkali alloy. |
| US10164178B2 |
Methods for forming narrow vertical pillars and integrated circuit devices having the same
In some embodiments, an integrated circuit includes narrow, vertically-extending pillars that fill openings formed in the integrated circuit. In some embodiments, the openings can contain phase change material to form a phase change memory cell. The openings occupied by the pillars can be defined using crossing lines of sacrificial material, e.g., spacers, that are formed on different vertical levels. The lines of material can be formed by deposition processes that allow the formation of very thin lines. Exposed material at the intersection of the lines is selectively removed to form the openings, which have dimensions determined by the widths of the lines. The openings can be filled, for example, with phase change material. |
| US10164176B2 |
Method of integration of a magnetoresistive structure
A method of manufacturing one or more interconnects to a magnetoresistive structure, the method comprising depositing a first conductive material (i) in a via which is formed through a first surface of a first dielectric layer and (ii) directly on the first surface of the first dielectric layer. The method further includes etching the first conductive material wherein, after etching the first conductive material, a portion of the first conductive material remains (i) in the via and (ii) directly on the first surface of the first dielectric layer. The method also includes partially filling the via by depositing a second conductive material (i) in the via and (ii) directly on the first conductive material remaining in the via, depositing a first electrode material (i) in the via and (ii) directly on the second conductive material which is in the via, and forming a magnetoresistive structure over the first electrode material. |
| US10164167B2 |
Method for producing an electric component and electric component
A method for producing an electric component (19) is specified, wherein in a step A) a body (1) having at least one cavity (7, 8) is provided. In a step B), the cavity (7, 8) is at least partly filled with a liquid insulation material (13) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an insulation material (13). The insulation material (13) is introduced into the cavity (7, 8) by means of capillary forces. Furthermore, an electric component (19) is specified wherein a cavity (7, 8) is at least partly filled with an organic insulation material (13) and wherein the cavity is at least partly covered by a fired external contacting (17, 18). |
| US10164166B2 |
MEMS component and method for encapsulating MEMS components
A MEMS component includes, on a substrate, component structures, contact areas connected to the component structures, metallic column structures seated on the contact areas, and metallic frame structures surrounding the component structures. A cured resist layer is seated on frame structure and column structures such that a cavity is enclosed between substrate, frame structure and resist layer. A structured metallization is provided directly on the resist layer or on a carrier layer seated on the resist layer. The structured metallization includes at least external contacts of the component and being electrically conductively connected both to metallic structures and to the contact areas of the component structures. |
| US10164164B2 |
Futuristic hybrid thermoelectric devices and designs and methods of using same
This patent incorporates several new hybrid thermoelectric element and thermoelectric device designs that utilize additional electronic materials to enhance the flow of charges in the thermoelectric elements without changing thermoelectric nature of the thermoelectric material used. The thermoelectric device efficiency is thereby increased and cost and size are lowered. Thermoelectric conversion devices using the new design criteria have demonstrated comparative higher performance than current commercially available standard design thermoelectric conversion devices. |
| US10164163B2 |
Optical-semiconductor device with bottom surface including electrically conductive members and light-blocking base member therebetween, and method for manufacturing the same
A method for manufacturing an optical-semiconductor device, including forming a plurality of first and second electrically conductive members that are disposed separately from each other on a support substrate; providing a base member formed from a light blocking resin between the first and second electrically conductive members; mounting an optical-semiconductor element on the first and/or second electrically conductive member; covering the optical-semiconductor element by a sealing member formed from a translucent resin; and obtaining individual optical-semiconductor devices after removing the support substrate. |
| US10164162B2 |
Light emitting device, package for light emitting device, and method for manufacturing light emitting device
A light emitting device includes: a light emitting element; and a light reflective member adapted to reflect light emitted from the light emitting element, the light reflective member comprising a base metal made of a crystallized metal, an amorphous layer located over the base metal and made of an amorphous metal, and an Ag-containing layer located over the amorphous layer. |
| US10164161B2 |
Directional light emitting arrangement and a method of producing the same
A light emitting arrangement is suggested for generating directional projections of light with sharply defined beam profile. Light from a top-emitting solid state light source (12), having reflective side-coating (34), is pre-collimated via a beam-shaping optic (16), before being propagated through a secondary collimating funnel (18), capturing any light rays with still too great an escape angle. Chip-scale package dimensions may be achieved through the use of a thin-film side-coating and undersized phosphor layers. Substrate level process flow further allows for parallel processing of a plurality of devices. |
| US10164150B2 |
Near UV light emitting device
Disclosed is a near UV light emitting device. The light emitting device includes an n-type contact layer, a p-type contact layer, an active area of a multi-quantum well structure disposed between the n-type contact layer and the p-type contact layer, and at least one electron control layer disposed between the n-type contact layer and the active area. Each of the n-type contact layer and the p-type contact layer includes an AlInGaN or AlGaN layer, and the electron control layer is formed of AlInGaN or AlGaN. In addition, the electron control layer contains a larger amount of Al than adjacent layers to obstruct flow of electrons moving into the active area. Accordingly, electron mobility is deteriorated, thereby improving recombination rate of electrons and holes in the active area. |
| US10164146B2 |
P-side layers for short wavelength light emitters
A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow≤xhigh≤0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN. |
| US10164141B2 |
Image sensor device with damage reduction
A semiconductor device includes a carrier wafer, a device layer, a first semiconductor layer and a second semiconductor layer. The device layer is disposed on the carrier wafer. The first semiconductor layer is disposed on the device layer, and has a first side face and a second side face opposite to the first side face, in which the first side face is adjacent to the device layer. The second semiconductor layer is disposed on the first semiconductor layer, and has a third side face and a fourth side face opposite to the third side face, in which the fourth side face of the second semiconductor layer is adjacent to the second side face of the first semiconductor layer, and the second semiconductor layer is implanted and annealed. |
| US10164125B2 |
Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit
A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate. |
| US10164123B2 |
Imaging device including semiconductor substrate and unit pixel cell
An imaging device includes a semiconductor substrate comprising a first semiconductor; and a unit pixel cell provided to the semiconductor substrate. The unit pixel cell includes: a photoelectric converter that includes a pixel electrode and a photoelectric conversion layer, the photoelectric converter converting incident light into electric charges; a charge detection transistor that includes a part of the semiconductor substrate and detects the electric charges; and a reset transistor that includes at least a part of a first semiconductor layer comprising a second semiconductor and initializes a voltage of the photoelectric converter. The pixel electrode is located above the charge detection transistor. The reset transistor is located between the charge detection transistor and the pixel electrode. A band gap of the second semiconductor is larger than a band gap of the first semiconductor. |
| US10164121B2 |
Stacked independently contacted field effect transistor having electrically separated first and second gates
A semiconductor device including: a substrate; a first active layer on the substrate and including a first channel between a source and a drain; a second active layer stacked on the first active layer, the second active layer including a second channel between the source and the drain; a first gate corresponding to the first channel; and a second gate electrically separated from the first gate and corresponding to the second channel. |
| US10164119B2 |
Vertical field effect transistors with protective fin liner during bottom spacer recess etch
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material. |
| US10164118B2 |
Semiconductor device and method for producing same
A semiconductor device (100A) includes a substrate (101) and a thin film transistor (10) supported by the substrate. The thin film transistor includes a gate electrode (102), an oxide semiconductor layer (104), a gate insulating layer (103), a source electrode (105) and a drain electrode (106). The oxide semiconductor layer includes an upper semiconductor layer (104b) which is in contact with the source electrode and the drain electrode and which has a first energy gap, and a lower semiconductor layer (104a) which is provided under the upper semiconductor layer and which has a second energy gap that is smaller than the first energy gap. The source electrode and the drain electrode include a lower layer electrode (105a, 106a) which is in contact with the oxide semiconductor layer and which does not contain Cu, and a major layer electrode (105b, 106b) which is provided over the lower layer electrode and which contains Cu. An edge of the lower layer electrode is at a position ahead of an edge of the major layer electrode. |
| US10164115B2 |
Non-linear fin-based devices
An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein. |
| US10164107B2 |
Embedded source or drain region of transistor with laterally extended portion
In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled. |
| US10164105B2 |
Forming conductive STI liners for FinFETs
An integrated circuit device, and a method of forming, including a semiconductor substrate, isolation regions extending into the semiconductor substrate, a semiconductor strip, and a semiconductor fin overlapping and joined to the semiconductor strip is provided. A first dielectric layer and a second dielectric layer are disposed on opposite sidewalls of the semiconductor strip. The integrated circuit device further includes a first conductive liner and a second conductive liner, wherein the semiconductor strip, the first dielectric layer, and the second dielectric layer are between the first conductive liner and the second conductive line. The first conductive liner and the second conductive liner are between, and in contact with, sidewalls of a first portion and a second portion of the isolation regions. |
| US10164104B2 |
Method to form air-gap spacers and air-gap spacer-containing structures
A device includes an air-gap (i.e., air-gap spacer) formed in situ during the selective, non-conformal deposition of a conductive material. The air-gap is disposed between source/drain contacts and a gate conductor of the device and beneath a portion of the conductive material, and is configured to decrease capacitive coupling between adjacent conductive elements. Prior to deposition of the conductive material, source/drain contact structures are recessed and a selective etch is used to remove sidewall spacers that are disposed between the source/drain contacts and the gate structures. |
| US10164102B2 |
Method and structure for FinFET devices
A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers. |
| US10164096B2 |
Semiconductor device and manufacturing method thereof
A fin field effect transistor (Fin FET) device includes a fin structure extending in a first direction and protruding from an isolation insulating layer disposed over a substrate. The fin structure includes a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer. The Fin FET device includes a gate structure covering a portion of the fin structure and extending in a second direction perpendicular to the first direction. The Fin FET device includes a source and a drain. Each of the source and drain includes a stressor layer disposed in recessed portions formed in the fin structure. The stressor layer extends above the recessed portions and applies a stress to a channel layer of the fin structure under the gate structure. The Fin FET device includes a dielectric layer formed in contact with the oxide layer and the stressor layer in the recessed portions. |
| US10164091B1 |
Electronic device including a ring suppression structure
A circuit can include a field-effect transistor having a body, a drain, a gate, and a source. In an embodiment, the circuit can further include a bipolar transistor having a base and a collector, wherein the collector of the bipolar transistor is coupled to the body of the field-effect transistor; and the drain of the field-effect transistor is coupled to the base of the bipolar transistor. In another embodiment, the circuit can include a diode having an anode and a cathode, wherein the source of the field-effect transistor is coupled to the anode of the diode, and the gate of the field effect transistor is coupled to the cathode of the diode. In another aspect, an electronic device can include one or more physical structures that correspond to components within the circuits. |
| US10164089B1 |
Power MOSFET
A power MOSFET including a first transistor and a second transistor is provided. The first and the second transistors respectively include following elements. A well region is located in a substrate structure. A trench gate is disposed in the well region. First doped regions are disposed in the well region at two sides of the trench gate. A first metal layer is disposed on a first surface of the substrate structure and electrically connected to the first doped regions. A second doped region is disposed in the substrate structure. A second metal layer is disposed on a second surface of the substrate structure opposite to the first surface and electrically connected to the second doped region. The well regions of the first and the second transistors are separated from each other. The first and the second transistors share the second doped region and the second metal layer. |
| US10164087B2 |
Semiconductor device and method of manufacturing same
To provide a semiconductor device equipped with a snubber portion having an improved withstand voltage and capable of reducing a surge voltage at turn-off of an insulated gate field effect transistor portion. The concentration of a first conductivity type impurity in a snubber semiconductor region is greater than that in a drift layer. The thickness of a snubber insulating film between the snubber semiconductor region and a snubber electrode is greater than that of a gate insulating film between a gate electrode and a body region. |
| US10164086B2 |
Vertical field effect transistor device having alternating drift regions and compensation regions
A semiconductor device includes a plurality of drift regions of a vertical field effect transistor arrangement arranged in a semiconductor substrate. The plurality of drift regions has a first conductivity type. The semiconductor device further includes a plurality of compensation regions arranged in the semiconductor substrate. The plurality of compensation regions has a second conductivity type. Each drift region of the plurality of drift regions is arranged adjacent to at least one compensation region of the plurality of compensation regions. The semiconductor device further includes a body region of a transistor structure of the vertical field effect transistor arrangement arranged adjacent to a drift region of the plurality of drift regions. The semiconductor device further includes a gate extending substantially vertically along the body region of the transistor structure for controlling a substantially vertical channel region between a first doping region of the transistor structure and the drift region. |
| US10164081B2 |
Method for forming an implanted area for a heterojunction transistor that is normally blocked
The invention relates to a method for manufacturing a heterojunction transistor (1), said method comprising the steps of: forming an implanted area (8) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer (4), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer (6) on the first semiconductor layer so as to form an electron gas layer (5) at the interface between the first and second layers; and forming a control gate (75) over the second conductive layer (6) and vertically in line with the implanted area (8). |
| US10164079B2 |
Power semiconductor device
A power semiconductor device is disclosed. In one example, the device comprises a semiconductor body having a front side, a backside, a first load terminal, and a drift region. A first cell is arranged at the front side. Further, the power semiconductor device comprises: a first backside emitter region included in the semiconductor body, the first backside emitter region being electrically connected with the second load terminal and having dopants of the second conductivity type, wherein the first backside emitter region and the first cell have a first common lateral extension range; and a second backside emitter region included in the semiconductor body, the second backside emitter region being electrically connected with the second load terminal and having dopants of the first conductivity type, wherein the second backside emitter region and the second cell have a second common lateral extension range. |
| US10164075B2 |
Manufacturing method of semiconductor device including transistor
The transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film. The oxide semiconductor film includes a first oxide semiconductor film on the gate electrode side and a second oxide semiconductor film over the first oxide semiconductor film. The first oxide semiconductor film includes a first region in which an atomic proportion of In is larger than that of M (M is Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf). The second oxide semiconductor film includes a second region in which an atomic proportion of In is smaller than that of the first oxide semiconductor film. The second region includes a portion thinner than the first region. |
| US10164074B2 |
Semiconductor device with gate electrode embedded in substrate
A semiconductor device includes a semiconductor substrate, a gate dielectric layer, a gate electrode and source and drain regions. The gate dielectric layer extends into a first trench in the semiconductor substrate. The gate electrode is over the gate dielectric layer and is at least partially embedded in the first trench in the semiconductor substrate. The source and drain regions are in the semiconductor substrate and proximate the first trench in the semiconductor substrate. |
| US10164073B2 |
Apparatus and method for memory device
A method comprises forming a gate stack over a substrate, applying an oxygen flush process to the gate stack, forming a uniform oxide layer on the gate stack as a result of performing the step of applying the oxygen flush process and removing the uniform oxide layer through a pre-clean process. |
| US10164069B2 |
Devices including gate spacer with gap or void and methods of forming the same
Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion. |
| US10164067B2 |
Method of fabricating a semiconductor device
A method for fabricating a semiconductor device includes forming a gate electrode structure over a first region of a semiconductor substrate, and selectively forming an oxide layer overlying the gate electrode structure by reacting a halide compound with oxygen to increase a height of the gate electrode structure. The halide compound may be silicon tetrachloride, and the oxide layer may be silicon dioxide. The gate electrode structure may be a dummy gate electrode, which is subsequently removed, and replaced with another gate electrode structure. |
| US10164065B1 |
Film deposition for 3D semiconductor structure
In a method for manufacturing a semiconductor device, a first raised structure is formed on a surface of a substrate. The first raised structure includes a top surface and a side surface adjoining the top surface. The side surface includes an upper portion, a middle portion, and a lower portion. A deposition operation is performed with a precursor to form a first film on the top surface, the upper portion and the lower portion of the side surface, and the surface of the substrate. Performing the deposition operation includes controlling a saturated vapor pressure of the precursor. A re-deposition operation is performed on the first film and the first raised structure, so as to form a film structure. A thickness of the film structure on the middle portion of the side surface is smaller than a thickness of the film structure on the top surface. |
| US10164063B2 |
Semiconductor structure with protection layer
The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer. |
| US10164061B2 |
Method of fabricating non-volatile memory device array
A method of fabricating nanocrystal memory array includes stacking a silicon layer and a silicon germanium layer on a wafer. A gate oxide layer over is then formed on the silicon layer and the silicon germanium layer. Next, a gate layer is deposited on the gate oxide layer. Subsequently, the gate layer, gate oxide layer and the silicon germanium layer are patterned. Finally, the silicon germanium layer is oxidized. The nanocrystal is sandwiched in between the gate and the silicon layer, and the gate oxide layer surrounds the nanocrystal. |
| US10164053B1 |
Semiconductor device and method
In an embodiment, a method includes: forming a gate stack on a semiconductor fin, the gate stack having gate spacers along opposing sides of the gate stack; forming source/drain regions adjacent the gate stack; recessing the gate stack to form a first recess between the gate spacers; depositing a dielectric layer over the gate stack in the first recess; forming a first metal mask over the dielectric layer and the gate stack in the first recess; etching back the dielectric layer and the gate spacers to form a dielectric mask under the first metal mask; depositing a conductive material over the first metal mask and adjacent the gate stack; and planarizing the conductive material to form contacts electrically connected to the source/drain regions, top surfaces of the contacts and the dielectric mask being level. |
| US10164052B2 |
Semiconductor device and method for fabricating the same
A semiconductor device includes an interfacial layer on a substrate and agate structure on the interfacial layer. Preferably, the gate structure includes a patterned high-k dielectric layer, the patterned high-k dielectric layer comprises a metal oxide layer, and a horizontal direction width of the patterned high-k dielectric layer and a horizontal direction width of the interfacial layer are different. The semiconductor device also includes a first spacer adjacent to the gate structure and on part of the interfacial layer and contacting a top surface of the interfacial layer and a second spacer on the sidewalls of the first spacer and the interfacial layer. Preferably, a planar bottom surface of the second spacer is lower than a planar bottom surface of the first spacer and extending along a same direction as the planar bottom surface of the first spacer. |
| US10164045B2 |
Integrated circuit metal gate structure
A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer. |
| US10164037B2 |
Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate having a top surface, a source region, and a drain region. The semiconductor device structure includes a gate structure over the top surface and extending into the semiconductor substrate. The gate structure in the semiconductor substrate is between the source region and the drain region and separates the source region from the drain region. The semiconductor device structure includes an isolation structure in the semiconductor substrate and surrounding the source region, the drain region, and the gate structure in the semiconductor substrate. |
| US10164035B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device having a composite barrier structure over a transistor and a method for manufacturing the same is disclosed. The method includes a series of steps including: forming a transistor having source/drain regions within a fin structure and adjacent to a gate structure across over the fin structure; forming first source/drain contacts right above and electrically connected to the source/drain regions; depositing a composite barrier structure over the transistor and the first source/drain contacts; and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method further includes depositing a second etch-stop layer before depositing the composite barrier structure and forming second source/drain contacts right above and electrically connected to the first source/drain contacts. The method also includes forming contacts over and electrically connected to the second source/drain contacts. |
| US10164030B2 |
Semiconductor device and method of fabricating the same
A semiconductor device may include a substrate including an NMOS region and a PMOS region, and having a protrusion pattern; first and second gate structures respectively formed on the NMOS region and the PMOS region of the substrate, crossing the protrusion pattern, and extending along a first direction that is parallel to an upper surface of the substrate; first and second source/drain regions formed on both sides of the first and second gate structures; and first and second contact plugs respectively formed on the first and second source/drain regions, wherein the first contact plug and the second contact plug are asymmetric. Methods of manufacturing are also provided. |
| US10164029B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer. |
| US10164027B2 |
Symmetric tunnel field effect transistor
The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region. |
| US10164024B2 |
Heterostructures for semiconductor devices and methods of forming the same
Various heterostructures and methods of forming heterostructures are disclosed. A method includes removing portions of a substrate to form a temporary fin protruding above the substrate, forming a dielectric material over the substrate and over the temporary fin, removing the temporary fin to form a trench in the dielectric material, the trench exposing a portion of a first crystalline material of the substrate, forming a template material at least partially in the trench, the template material being a second crystalline material that is lattice mismatched to the first crystalline material, forming a barrier material over the template material, the barrier material being a third crystalline material, forming a device material over the barrier material, the device material being a fourth crystalline material, forming a gate stack over the device material, and forming a first source/drain region and a second source/drain region in the device material. |
| US10164023B2 |
FinFETs with strained well regions
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band. |
| US10164022B2 |
FinFETs with strained well regions
A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band. |
| US10164021B2 |
Silicon carbide semiconductor device
A silicon carbide semiconductor device includes an n-type drift region made of SiC, n-type base regions, gate electrodes formed inside trenches with gate insulating films interposed therebetween, n-type source regions formed in upper portions of the base regions, an n-type drain region formed on the bottom of the drift region, p-type protection regions formed beneath the trenches, and p-type avalanche breakdown-inducing regions (first under-contact base regions) formed at the same depth as the protection regions and having the same impurity concentration as the protection regions. The width wcb of the avalanche breakdown-inducing regions and the width wtb of the protection regions satisfy the relationship wtb/wcb>4/3. |
| US10164018B1 |
Semiconductor interconnect structure having graphene-capped metal interconnects
The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphene barrier layers can be selected by varying the thickness of the amorphous carbon layer. |
| US10164016B2 |
Integrated circuit structure and method with solid phase diffusion
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration |
| US10164004B2 |
Semiconductor device having a second conductive layer partially embedded in a stacked insulating structure and having a first conductive layer
Disclosed herein is a device that includes: a semiconductor substrate; a first insulating layer over a surface of the semiconductor substrate; first and second contact plugs each including side and upper surfaces, the side surfaces of the first and second contact plugs being surrounded by the first insulating film, the upper surfaces of the first and second contact plugs being substantially on the same plane with an upper surface of the first insulating layer; a second insulating layer over the first insulating layer; a first conductive layer including a bottom portion on the first contact plug and a side portion surrounded by the second insulating layer; a third insulating layer over the first conductive layer; and a second conductive layer on the second contact plug, apart of a side surface of the second conductive layer being surrounded by both the second and third insulating layers. |
| US10164002B2 |
Semiconductor device and layout method
A semiconductor device is disclosed. The semiconductor device includes a first set of conductive layers coupled with an active device, a second set of conductive layers for connection to an external device, a set of intermediate conductive layers between the first set of conductive layers and the second set of conductive layers, and a resistive layer disposed in the set of intermediate conductive layers. |
| US10164000B2 |
OLED lighting device with short tolerant structure
A first device that may include a short tolerant structure, and methods for fabricating embodiments of the first device, are provided. A first device may include a substrate and a plurality of OLED circuit elements disposed on the substrate. Each OLED circuit element may include a fuse that is adapted to open an electrical connection in response to an electrical short in the pixel. Each OLED circuit element may comprise a pixel that may include a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. Each of the OLED circuit elements may not be electrically connected in series with any other of the OLED circuit elements. |
| US10163997B2 |
OLED array substrate, manufacturing method thereof, and display apparatus
The present invention discloses an OLED array substrate and a manufacturing method thereof, a display apparatus. The OLED array substrate includes a TFT and an OLED. The method includes: forming an oxide semiconductor layer by a film forming process, and performing one patterning process on the oxide semiconductor layer to form an active layer of the TFT and a first electrode of the OLED; sequentially forming a first insulating layer and a second insulating layer on the active layer and the first electrode of the OLED, the first insulating layer being a lyophilic layer, and the second insulating layer being a lyophobic layer; forming an accommodation cavity exposing the first electrode by performing a patterning process on the first and second insulating layers; and injecting, into the accommodation cavity, and drying a solution containing an organic light emitting material to form an organic light emitting material layer. |
| US10163993B2 |
Display panel and method for manufacturing same
A display panel including a substrate; first, second, and third lower electrodes; first and second column banks; first, second, and third organic light-emitting layers; and an upper electrode. When a first ink for forming the first organic light-emitting layer, a second ink for forming the second organic light-emitting layer, and a third ink for forming the third organic light-emitting layer are applied, ink-separating capability of the first column bank for separating the first ink and the second ink is lower than ink-separating capability of the second column bank for separating the second ink and the third ink, and ink-separating capability depends on: (i) a height of the first and second column banks, or (ii) liquid repellency of the first column bank against the first ink and the second ink and liquid repellency of the second column bank against the second ink and the third ink. |
| US10163986B2 |
Electro-optical device, method for manufacturing electro-optical device, and electronic apparatus
There is provided an electro-optical device including a light-emitting element, a sealing layer that covers the light-emitting element, a first color filter transmits light in a first wavelength region, and a second color filter that is formed on the sealing layer and the first color filter and transmits light in a second wavelength region, in which the light in the first wavelength region has higher visibility than the light in the second wavelength region, and the first color filter is first formed on the sealing layer. |
| US10163982B2 |
Multi-deck memory device with inverted deck
Described herein are multi-deck memory devices with an inverted deck. For example, in one embodiment a memory device includes a first deck of memory cells including layers of material, including a layer of storage material and a layer of selector material, and a second deck of memory cells over the first deck of memory cells, the second deck comprising layers of material in an order opposite relative to the first deck. In one such embodiment, conductive bitlines located between the first and second decks are common to both decks. Inverting the second deck can enable operating the decks symmetrically despite accessing the decks with opposite polarity voltages. |
| US10163981B2 |
Metal landing method for RRAM technology
The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device. |
| US10163979B2 |
Selector-resistive random access memory cell
Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer. |
| US10163974B2 |
Method of forming absorption enhancement structure for image sensor
In some embodiments, the present disclosure relates to a method of forming an absorption enhancement structure for an integrated chip image sensor that reduces crystalline defects resulting from the formation of the absorption enhancement structure. The method may be performed by forming a patterned masking layer over a first side of a substrate. A dry etching process is performed on the first side of the substrate according to the patterned masking layer to define a plurality of intermediate protrusions arranged along the first side of the substrate within a periodic pattern. A wet etching process is performed on the plurality of intermediate protrusions to form a plurality of protrusions. One or more absorption enhancement layers are formed over and between the plurality of protrusions. The wet etching process removes a damaged region of the intermediate protrusions that can negatively impact performance of the absorption enhancement structure. |
| US10163973B2 |
Method for forming the front-side illuminated image sensor device structure with light pipe
A method for forming an FSI image sensor device structure is provided. The method includes forming a pixel region in a substrate and forming a dielectric layer over the substrate. The method includes forming a trench through the dielectric layer, and the trench includes a top portion and a bottom portion, and the trench is directly above the pixel region. The method includes forming a protection layer in the bottom portion of the trench and enlarging a top width of the top portion of the trench, and the trench has a wide top portion and a narrow bottom portion. The wide top portion has top sidewall surfaces, the narrow bottom portion has bottom sidewall surfaces, and the top sidewall surfaces taper gradually toward the bottom sidewall surfaces. The method includes filling a transparent dielectric layer in the trench to form a light pipe. |
| US10163967B2 |
Imaging device, method for operating the same, and electronic device
An imaging device with low power consumption. The imaging device includes a plurality of pixels arranged in a matrix, a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit has a function of converting an analog signal into a digital signal. The second circuit has a function of detecting a difference between image data of a first frame and image data of a second frame. The third circuit has a function of controlling the frequency of a clock signal. The fourth circuit has a function of generating clock signals of a plurality of frequencies. |
| US10163962B2 |
Solid-state imaging apparatus, manufacturing method therefor, and electronic apparatus
The present technology relates to a solid-state imaging apparatus, a manufacturing method therefor, and an electronic apparatus by which fine pixel signals can be suitably generated.A charge accumulation section that is formed on a first semiconductor substrate and accumulates photoelectrically converted charges, a charge-retaining section that is formed on a second semiconductor substrate and retains charges accumulated in the charge accumulation section, and a transfer transistor that is formed on the first semiconductor substrate and the second semiconductor substrate and transfers charges accumulated in the charge accumulation section to the charge-retaining section are provided. A bonding interface between the first semiconductor substrate and the second semiconductor substrate is formed in a channel of the transfer transistor. |
| US10163961B2 |
Image sensor
An image sensor may include a pixel array that includes a plurality of pixel blocks arranged in an M×N (where M and N are natural numbers) matrix structure, wherein, among the plurality of pixel blocks, when compared to any one pixel block as a first pixel block, any one pixel block as a second pixel block adjacent to the first pixel block in an M direction or an N direction has a planar shape that is obtained by inverting a planar shape of the first pixel block in the M direction. Each of the plurality of pixel blocks may include a light reception unit including a plurality of unit pixels which generate photocharges in response to incident light and are arranged in an m×n matrix structure to have a shared pixel structure; and a driving circuit suitable for outputting an image signal corresponding to the photocharges. |
| US10163958B2 |
CMOS image sensor
A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate having a front side and a back side and a pixel region having a plurality of pixels in the front side, each pixel including a sensor element, forming a metal reflective layer in the front side of the substrate and on the pixel region, thinning the back side of the substrate, doping the thinned back side of the substrate with a dopant, and laser annealing the doped back side of the substrate. The sensor element is configured to receive incident light to the thinned back side of the semiconductor substrate. The metal reflective layer reflects heat generated in the laser annealing process to more fully activate the dopant in the back side of the substrate, thereby effectively reducing dark current and improving the device performance. |
| US10163953B2 |
Image pickup device and method of manufacturing the same
A P-type well is defined by an isolation region formed in a semiconductor substrate. A pixel region and a ground region are defined in the P-type well. In the pixel region, a pixel transistor region and a photodiode region having a photodiode formed therein are defined. An antireflection film is formed so as to cover at least the photodiode region and the ground region. A plug connected to the ground region is formed so as to extend through the antireflection film and the like. |
| US10163952B2 |
Backside illuminated image sensor device structure
A method for forming a backside illuminated (BSI) image sensor device structure is provided. The BSI image sensor includes a first substrate having a top surface and a bottom surface, and a plurality of pixel regions formed at the top surface of the first substrate. The BSI image sensor also includes a grid structure through the first substrate and between two adjacent pixel regions. The grid structure extends continuously through the first substrate in a vertical direction and has a top surface and a bottom surface, the top surface of the grid structure protrudes above the bottom surface of the first substrate, and the bottom surface is leveled with the top surface of the first substrate. |
| US10163950B2 |
Solid state imaging device and electronic apparatus
A solid state imaging device including: a pixel region that is formed on a light incidence side of a substrate and to which a plurality of pixels that include photoelectric conversion units is arranged; a peripheral circuit unit that is formed in a lower portion in the substrate depth direction of the pixel region and that includes an active element; and a light shielding member that is formed between the pixel region and the peripheral circuit unit and that shields the incidence of light, emitted from an active element, to the photoelectric conversion unit. |
| US10163944B2 |
Thin film transistor substrate having a plurality of stacked storage capacitors
A thin film transistor (TFT) substrate and a display device using the same are disclosed. The TFT substrate includes a first TFT including a polycrystalline semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode deposited on a substrate, a second TFT separated from the first TFT, the second TFT including a second gate electrode, an oxide semiconductor layer, a second source electrode, and a second drain electrode deposited on the first gate electrode, and a plurality of storage capacitors separated from the first and second TFTs, each storage capacitor including a first dummy semiconductor layer, a first gate insulating layer on the first dummy semiconductor layer, a first dummy gate electrode on the first gate insulating layer, and an intermediate insulating layer on the first dummy gate electrode. |
| US10163943B2 |
Display device
To make the dimension of an electrostatic protection circuit small with the same maintained high in sensitivity. The electrostatic protection circuit is of the configuration that a first diode and a second diode are connected in series, wherein a semiconductor layer owned by each diode is configured to be sandwiched between a gate electrode and a conductive light shielding film. The light shielding film is formed to overlap with the semiconductor layer and has a wider area than the semiconductor layer. This results in having a gate covering the semiconductor layer from an upper side and a back gate covering the semiconductor layer from a lower side, so that the sensitivity can be maintained high irrespective of decreasing the electrostatic protection circuit in dimension. |
| US10163941B1 |
Display apparatus
A display apparatus is provided that includes a substrate having a display area and a peripheral area located outside the display area. A first part of an edge of the display area has a round shape and the peripheral area includes a pad area. The display apparatus further includes a first wiring extending in a direction toward the first part from the pad area, and having a first discontinuous point at which the first wiring is physically discontinuous; and a first bridge wiring allowing the first wiring to be electrically continuous at the first discontinuous point. |
| US10163939B2 |
Thin film transistor array substrate and display device
The present disclosure provides a thin film transistor array substrate and a display device implementing the same. The thin film transistor array substrate includes a substrate; a first signal line formed on the substrate; and a thin film transistor formed on the substrate, and an active layer of the thin film transistor and the first signal line are located on different layers above the substrate and projections of them on a plane where the substrate is located overlap with each other at at least two positions. The present disclosure may improve wiring efficiency and reliability of the thin film transistor array substrate. |
| US10163938B2 |
Array substrate and manufacturing method thereof, and display device
An array substrate and a manufacturing method thereof, and a display device are provided. The array substrate includes a plurality of mutually parallel signal lines, an insulating layer located on a layer in which the plurality of signal lines is located and at least one first conductive structure located on the insulating layer. The insulating layer includes at least two first through holes corresponding to the first conductive structure, and the first conductive structure is electrically connected with the signal lines through the at least two first through holes. |
| US10163933B1 |
Ferro-FET device with buried buffer/ferroelectric layer stack
Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer. |
| US10163931B2 |
Non-volatile semiconductor storage device and method of manufacturing the same
A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells. |
| US10163930B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer. |
| US10163926B2 |
Memory device and method for fabricating the same
A memory device memory device includes a multi-layers stack, a charge-trapping layer, a first channel layer and a SSL switch. The multi-layers stack includes a plurality of insulating layers, a plurality of conductive layers alternatively stacked with the insulating layers and at least one first through opening passing through the conductive layers. The charge-trapping layer blankets over a sidewall of the first through opening. The first channel layer is disposed in the first through opening. The SSL switch is disposed on the multi-layers stack and includes a second channel layer, a gate dielectric layer and a gate. The second channel layer is disposed on and electrically contacting to the first channel layer. The gate dielectric layer is disposed on the second channel layer and made of a material other than that for making the charge-trapping layer. The gate is disposed on the gate dielectric layer. |
| US10163924B2 |
Manufacturing method of three-dimensional semiconductor memory device
A method of manufacturing a semiconductor device includes sequentially stacking a source sacrificial layer, an upper protective layer, and an etch stop layer, which are formed of different materials from each other, over a substrate, alternately stacking interlayer dielectric layers and gate sacrificial layers over the etch stop layer, forming a first slit which penetrates the interlayer dielectric layers and the gate sacrificial layers, wherein a bottom surface of the first slit is disposed in the etch stop layer, replacing the gate sacrificial layers with gate conductive patterns through the first slit, forming a second slit which extends from the first slit through the etch stop layer and the upper protective layer to the source sacrificial layer, and replacing the source sacrificial layer with a first source layer through the second slit. |
| US10163919B2 |
Embedded flash memory device with floating gate embedded in a substrate
An embedded flash memory device includes a gate stack, which includes a bottom dielectric layer extending into a recess in a semiconductor substrate, and a charge storage layer over the bottom dielectric layer. The charge storage layer includes a portion in the recess. The gate stack further includes a top dielectric layer over the charge storage layer, and a metal gate over the top dielectric layer. Source and drain regions are in the semiconductor substrate, and are on opposite sides of the gate stack. |
| US10163911B2 |
SRAM cell with T-shaped contact
An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments. |
| US10163909B2 |
Methods for fabricating a semiconductor memory device
A semiconductor memory device includes a semiconductor substrate having active areas and a trench isolation region between the active areas. The active areas extend along a first direction. Buried word lines extend along a second direction in the semiconductor substrate. Two of the buried word lines intersect with each of the active areas, separating each of the active areas into a digit line contact area and two cell contact areas. The second direction is not perpendicular to the first direction. A digit line contact is disposed on the digit line contact area. A storage node contact is disposed on each of the two cell contact areas. The digit line contact and the storage node contact are coplanar. At least one digit line extends along a third direction over a main surface of the semiconductor substrate. The at least one digit line is in direct contact with the digit line contact. |
| US10163905B2 |
Method and structure for FinFET device
The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion. |
| US10163902B2 |
FinFET transistor with fin back biasing
A semiconductor device includes multiple first fins oriented lengthwise along a first direction and multiple first gate structures oriented lengthwise along a second direction generally perpendicular to the first direction. Each of the first fins includes an end that is narrower than a main body of the respective first fin. The first gate structures are disposed over channel regions of the main body of the first fins to form multiple first FinFETs. The end of the first fins and the channel regions of the first fins sandwich some of source/drain regions of the first fins. The semiconductor device further includes a first contact disposed over and in electrical contact with the ends of the first fins. |
| US10163900B2 |
Integration of vertical field-effect transistors and saddle fin-type field effect transistors
Structures for the integration of a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit, as well as methods of integrating a vertical field-effect transistor and a saddle fin-type field-effect transistor into an integrated circuit. A trench isolation is formed in a substrate that defines a first device region and a second device region. A first semiconductor fin is formed that projects from the first device region and a second semiconductor fin is formed that projects from the second device region. A vertical field-effect transistor is formed using the first semiconductor fin, and a saddle fin-type field-effect transistor is formed using the second semiconductor fin. A top surface of the trench isolation in the second device region adjacent to the second semiconductor fin is recessed relative to the top surface of the trench isolation in the first device region adjacent to the first semiconductor fin. |
| US10163899B2 |
Temperature compensation circuits
The present disclosure relates generally to integrated circuits, and more particularly to low-bias voltage reference circuits. The voltage reference circuits are capable of providing highly-accurate and temperature-insensitive outputs. Specifically, the present disclosure provides complementary-to-absolute-temperature circuits with low process variation and tunable temperature coefficient. |
| US10163894B2 |
FinFET-based ESD devices and methods for forming the same
A semiconductor device includes semiconductor fins on semiconductor strips on a substrate. The semiconductor fins are parallel to each other. A gate stack is over the semiconductor fins, and a drain epitaxy semiconductor region is disposed laterally from a side of the gate stack and on the semiconductor strips. A first dielectric layer is over the substrate, and the first dielectric layer has a first metal layer. A second dielectric layer is over the first dielectric layer, and the second dielectric layer has a second metal layer. Vias extend from the second metal layer and through the first dielectric layer, and the vias are electrically coupled to the drain epitaxy semiconductor region. |
| US10163891B2 |
High voltage ESD protection apparatus
A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well. |
| US10163885B2 |
Systems and methods for a sequential spacer scheme
Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a target layer disposed over the substrate. The target layer includes a first target feature, a second target feature, and a third target feature. The second target feature is spaced a first distance from the first target feature, and the third target feature is spaced a second distance from the first target feature. The first distance corresponds with a first width of a first spacer fabricated during a first spacer patterning process, and the second distance corresponds with a second width of a second spacer fabricated during a second spacer patterning process. |
| US10163879B2 |
Semiconductor device having jumper pattern
According to an exemplary embodiment of the present inventive concept, a semiconductor device is provided as follows. An active region is disposed in one side of a gate line. A non-active region is disposed in the other side of the gate line. A jumper pattern crosses a top portion of the gate line, overlapping the active region and the non-active region. A boundary between the active region and the non-active region is underneath the gate line. |
| US10163870B2 |
Light emitting device package and light emitting device package module
Disclosed herein is a light emitting device package and a light emitting device package module. The light emitting device package includes: a base including a cavity; a first light emitting device disposed in the cavity, the first light emitting device including a first light emitting element configured to produce light having a first peak wavelength and a first fluorescent layer covering a top and side surfaces of the first light emitting element; and a second light emitting device disposed in the cavity, the second light emitting device including a second light emitting element configured to produce light having a second peak wavelength and a second fluorescent layer covering a top and side surfaces of the second light emitting element, wherein the first fluorescent layer is configured to convert the light having the first peak wavelength of the first light emitting element to light having a third peak wavelength, and the second fluorescent layer is configured to convert the light having the second peak wavelength of the second light emitting element to light having a fourth peak wavelength. |
| US10163865B2 |
Integrated circuit package assembly
An integrated circuit package assembly includes a first integrated circuit package and a second integrated circuit package. The first integrated circuit package includes a first integrated circuit die mounted on a first substrate. The second integrated circuit package includes a second integrated circuit die mounted on a second substrate. The second integrated circuit package is disposed under the first integrated circuit package. Solder bumps are disposed between the first integrated circuit package and the second integrated circuit package and provide electrical signal connections between the first integrated circuit die and the second integrated circuit die. A buffer layer is disposed between the first substrate and the second integrated circuit die to facilitate thermal conduction between the first integrated circuit package and the second integrated circuit package. |
| US10163862B2 |
Package structure and method for forming same
A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package. |
| US10163859B2 |
Structure and formation method for chip package
A chip package is provided. The chip package includes a semiconductor chip and a semiconductor die over the semiconductor chip. The chip package also includes a dielectric layer over the semiconductor chip and encapsulating the semiconductor die, and the dielectric layer is substantially made of a semiconductor oxide material. The chip package further includes a conductive feature penetrating through a semiconductor substrate of the semiconductor die and physically connecting a conductive pad of the semiconductor chip. |
| US10163857B2 |
Multi-chip fan out package and methods of forming the same
A package includes a die having a conductive pad at a top surface of the die, a stud bump over and connected to the conductive pad, and a redistribution line over and connected to the stud bump. An electrical connector is over and electrically coupled to the redistribution line. |
| US10163854B2 |
Package structure and method for manufacturing thereof
A package structure includes a package, at least one second molding material, and at least one electronic component. The package includes at least one first semiconductor device therein, a first molding material, at least one dielectric layer and at least one redistribution line. The first molding material is at least in contact with at least one sidewall of the first semiconductor device. The dielectric layer is over the first semiconductor device and the first molding material. The redistribution line is present at least partially in the dielectric layer and is electrically connected to the first semiconductor device. The second molding material is present on the package. The electronic component is present on the package and is external to the second molding material. |
| US10163852B2 |
Integrated fan-out package including voltage regulators and methods forming same
A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die. |
| US10163844B2 |
Semiconductor device having conductive bumps of varying heights
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate including a plurality of conductive traces and a recess filled with a conductive material electrically coupled to at least one of the plurality of conductive traces. The semiconductor structure also includes semiconductor chip. The semiconductor chip includes a plurality of conductive pads correspondingly electrically connected with the plurality of conductive traces through a plurality of conductive bumps. A height of each of the plurality of conductive bumps is determined by a minimum distance between the plurality of conductive pads and the corresponding conductive traces thereof. |
| US10163841B2 |
Multi-chip package and method of formation
A device comprises a first semiconductor die embedded in a molding compound layer, a surface-mount device embedded in the molding compound layer, a plurality of interconnect structures formed on the molding compound layer, wherein the first semiconductor die is electrically coupled to the interconnect structures and the surface-mount device is electrically coupled to the interconnect structures through at least a metal pillar and a plurality of bumps formed on and electrically coupled to the interconnect structures. |
| US10163837B2 |
Cu pillar bump with L-shaped non-metal sidewall protection structure
A method of forming an integrated circuit device includes forming a bump structure on a substrate, wherein the bump structure has a top surface and a sidewall surface, and the substrate has a surface region exposed by the bump structure. The method further includes depositing a non-metal protection layer on the top surface and the sidewall surface of the bump structure and the surface region of the substrate. The method further includes removing the non-metal protection layer from the top surface of the bump structure, wherein a remaining portion of the non-metal protection layer forms an L-shaped protection structure, and a top surface of the remaining portion of the non-metal protection layer is farther from the substrate than a top surface of the bump structure. |
| US10163835B2 |
Solder bump stretching method
A wafer-level pulling method includes securing a top holder to a plurality of chips. The method further includes securing a bottom holder to a wafer, wherein the plurality of chips are bonded to the wafer by a plurality of solder bumps. The method further includes softening the plurality of solder bumps. The method further includes stretching the plurality of softened solder bumps, wherein stretching the plurality of softened solder bumps comprises leveling the plurality of chips using a plurality of levelling devices separated from the plurality of chips, and a first levelling device of the plurality of levelling devices has a different structure from a second levelling device of the plurality of levelling devices. |
| US10163834B2 |
Chip package structure comprising encapsulant having concave surface
A chip package structure includes a chip, an encapsulant, a dielectric layer and a patterned circuit layer. The chip includes an active surface and a plurality of pads disposed on the active surface. The encapsulant encapsulates the chip and exposes active surface, wherein the encapsulant includes a concave surface and a back surface opposite to the concave surface, the concave surface exposes the active surface and is dented toward the back surface. The dielectric layer covers the concave surface and the active surface and includes a plurality of openings exposing the pads, wherein the opening includes a slanted side surface and the angle between the slanted side surface and the active surface is an acute angle. The patterned circuit layer is disposed on the dielectric layer and electrically connected to the pads through the openings. |
| US10163832B1 |
Integrated fan-out package, redistribution circuit structure, and method of fabricating the same
A redistribution circuit structure electrically connected to a die underneath is provided. The redistribution circuit structure includes a dielectric layer and a conductive layer. The dielectric layer partially covers the die, so that a conductive pillar of the die is exposed by the dielectric layer. The conductive layer is disposed over the dielectric layer and electrically connected to the die by the conductive pillar. The conductive layer includes a multilayer structure, wherein an average grain size of one layer of the multilayer structure is less than or equal to 2 μm. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided. |
| US10163829B2 |
Compound semiconductor substrate and power amplifier module
A compound semiconductor substrate has a first main surface parallel to a first direction and a second direction perpendicular to the first direction, a second main surface located on a side opposite to the first main surface, and a recess. The recess has an opening, a bottom surface facing the opening, and a plurality of side surfaces located between the opening and the bottom surface. The side surfaces include at least one first side surface forming an angle of about θ degrees with the bottom surface in the recess and at least one second side surface forming an angle of about ϕ degrees with the bottom surface in the recess. The total length of edge lines between the first main surface and the at least one first side surface is larger than that of edge lines between the first main surface and the at least one second side surface. |
| US10163828B2 |
Semiconductor device and fabricating method thereof
A semiconductor structure includes an oval-shaped pad and a dielectric layer. The oval-shaped pad is on a substrate and includes a major axis corresponding to the largest distance of the oval-shaped pad. The major axis is toward a geometric center of the substrate. The dielectric layer covers the substrate and surrounds the oval-shaped pad. |
| US10163826B2 |
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system. |
| US10163823B2 |
Method and apparatus of ESD protection in stacked die semiconductor device
An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies. |
| US10163820B2 |
Chip carrier and method thereof
A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included. |
| US10163817B2 |
Semiconductor device structure comprising a plurality of metal oxide fibers and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a conductive structure over the substrate. The semiconductor device structure includes first metal oxide fibers over the conductive structure. The semiconductor device structure includes a dielectric layer over the substrate and covering the conductive structure and the first metal oxide fibers. The dielectric layer fills gaps between the first metal oxide fibers. |
| US10163815B2 |
Semiconductor device with dummy metal protective structure around semiconductor die for localized planarization of insulating layer
A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die. |
| US10163814B2 |
Semiconductor package having a metal paint layer
Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module. Such a module can include a packaging substrate, one or more RF components mounted on the packaging substrate, a ground plane disposed within the packaging substrate, and a plurality of RF-shielding wirebonds disposed on the packaging substrate and electrically connected to the ground plane. The module can further include an overmold structure formed over the packaging substrate and dimensioned to substantially encapsulate the RF component(s) and the RF-shielding wirebonds. The overmold structure can define an upper surface that exposes upper portions of the RF-shielding wirebonds. The module can further include a conductive paint layer having silver flakes disposed on the upper surface of the overmold structure so that the conductive paint layer, the RF-shielding wirebonds, and the ground plane form an RF-shield for the RF component(s). |
| US10163806B2 |
Photolithography alignment mark structures and semiconductor structures
A method is provided for fabricating a photolithography alignment mark structure. The method includes providing a substrate; forming a first grating, a second grating, a third grating and a fourth grating in the substrate; forming a photoresist layer on a surface of the substrate; obtaining a first alignment center along a first direction and a second alignment center alone a second direction based on the first grating and the fourth grating, respectively; providing a mask plate having a fifth grating pattern and a sixth grating pattern; aligning the mask plate with the substrate by using the first alignment center as an alignment center along the first direction and the second alignment center as an alignment center along the second direction; reproducing the fifth grating pattern and the sixth grating pattern in the photoresist layer; and forming a fifth grating and a sixth grating on the substrate by removing a portion of photoresist layer. |
| US10163805B2 |
Package structure and method for forming the same
A package structure and method for forming the same are provided. The package structure includes a substrate and a package layer formed over the substrate. The package structure further includes an alignment structure formed over the package layer, and the alignment structure includes a first alignment mark formed in a trench, and the trench has a step-shaped structure. |
| US10163801B2 |
Structure and formation method of chip package with fan-out structure
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive feature and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer arranged over the semiconductor die and the protection layer and partially covering the conductive feature. The conductive feature is arranged accessibly from the protection layer and the dielectric layer. The chip package further includes a conductive layer penetrating through the dielectric layer and electrically connected to the conductive feature of the semiconductor die. The conductive feature has a first portion covered by the dielectric layer and a second portion accessibly exposed from the dielectric layer, and the second portion has a surface roughness greater than that of the first portion. |
| US10163799B2 |
Semiconductor structure and method of manufacturing the same
The present disclosure provides a semiconductor structure, including a first silicon layer having a through silicon via (TSV), a III-V structure over the first silicon layer, electrically coupling to the TSV, and a redistribution layer (RDL) under the first silicon layer, electrically coupling to the TSV. The present disclosure also provides a method of manufacturing a semiconductor device. The method includes providing a III-V-on-Si structure, comprising a III-V device over a silicon layer, forming a through silicon via (TSV) in the silicon layer, electrically coupling to the III-V device, and forming a redistribution layer (RDL) over a side of the silicon layer opposite to the III-V device. |
| US10163798B1 |
Embedded multi-die interconnect bridge packages with lithotgraphically formed bumps and methods of assembling same
An embedded multi-die interconnect bridge apparatus and method includes photolithographically formed interconnects coupled to laser-drilled interconnects. Several structures in the embedded multi-die interconnect bridge apparatus exhibit characteristic planarization during fabrication and assembly. |
| US10163796B2 |
Surface treatment for semiconductor structure
A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor at least partially in the dielectric layer includes performing a planarization process. The method further includes treating respective surface areas of the dielectric layer and the metallic conductor, after the planarization process, to modify the respective surface areas of the dielectric layer and the metallic conductor. In one example, the surface treatment is a neutral atom beam treatment. |
| US10163795B2 |
Electro-migration barrier for Cu interconnect
The present disclosure relates to an integrated circuit device and an associated method of formation. The integrated circuit device includes a substrate, and a conductive metal interconnect line arranged within a dielectric material disposed over the substrate. An interfacial layer is in contact with an upper surface of the conductive metal interconnect line. An upper dielectric layer is arranged over the interfacial layer. A middle dielectric layer is arranged between the upper dielectric layer and the interfacial layer. |
| US10163791B2 |
Semiconductor device
It is intended to reduce the price of a semiconductor device and increase the reliability thereof. In an interposer, a plurality of wiring layers are disposed between uppermost-layer wiring and lowermost-layer wiring. For example, a third wiring layer is electrically coupled directly to a first wiring layer as the uppermost-layer wiring by a long via wire extending through insulating layers without intervention of a second wiring layer. For example, an upper-surface terminal made of the first wiring layer is electrically coupled directly to a via land made of the third wiring layer by the long via wire. Between the adjacent long via wires, three lead-out wires made of the second wiring layer can be placed. The number of the lead-out wires that can be placed between the adjacent long via wires is larger than the number of the lead-out wires that can be placed between the adjacent via lands. |
| US10163789B2 |
Semiconductor device and display device
Provided is a semiconductor device that includes: an integrated circuit (IC) chip including a terminal array that is a matrix of terminals arranged in at least seven rows and at least seven columns, the terminals including a reference terminal to which a reference voltage is applied; a capacitor electrically connected to the reference terminal; and a substrate including one main surface as a mounting surface on which the IC chip and the capacitor are mounted. The IC chip is an application specific integrated circuit (ASIC) chip or a field-programmable gate array (FPGA) chip. The reference terminal is disposed at a position within three rows or three columns from an outer edge of the terminal array. |
| US10163787B2 |
Semiconductor structure
The semiconductor structure includes a first conductive path including first and second segments. The first segment is in a first conductive layer. The second segment is in a second conductive layer. The first and second segments are electrically connected. The semiconductor structure includes a second conductive path including third and fourth segments. The third segment is in the first conductive layer. The fourth segment is in the second conductive layer. The third and fourth segments are electrically connected. The semiconductor structure includes a third conductive path between the first conductive path and the second conductive path, the third conductive path includes fifth and sixth segments. The fifth segment is in the second conductive layer. The sixth segment is in the first conductive layer. The fifth and sixth segments are electrically connected. An area of the first conductive layer between the first and third segments is free of the sixth segment. |
| US10163785B2 |
Semiconductor die contact structure and method
A system and method for forming a semiconductor die contact structure is disclosed. An embodiment comprises a top level metal contact, such as copper, with a thickness large enough to act as a buffer for underlying low-k, extremely low-k, or ultra low-k dielectric layers. A contact pad or post-passivation interconnect may be formed over the top level metal contact, and a copper pillar or solder bump may be formed to be in electrical connection with the top level metal contact. |
| US10163784B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device and a method for manufacturing the same are disclosed. In the semiconductor device, an upper part of a storage node contact plug is increased in size, and an area of overlap between a storage node formed in a subsequent process and a storage node contact plug is increased, such that resistance of the storage node contact plug is increased and device characteristics are improved. The semiconductor device includes at least one bit line formed over a semiconductor substrate, a first storage node contact plug formed between the bit lines and coupled to an upper part of the semiconductor substrate, and a second storage node contact plug formed over the first storage node contact plug, wherein a width of a lower part of the second storage node contact plug is larger than a width of an upper part thereof. |
| US10163769B2 |
Manufacturing method for electronic element
The present invention provides a manufacturing method for an electronic element of an electronic apparatus. The electronic element includes a substrate, a bump and at least one under bump metal (UBM) layer. The manufacturing method includes sequentially disposing the UBM layer and the bump onto the substrate; and processing an etching operation at the UBM layer to form a breach structure. |
| US10163766B2 |
Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks
A leadless package with wettable flanks is formed by providing a substrate and plating a metal layer onto the substrate to form a contact on the substrate extending across a saw street. An encapsulant is deposited over the contact. The substrate is removed to expose the contact and encapsulant. The encapsulant and contact are singulated. In some embodiments, the substrate includes a ridge, and the contact is formed over the ridge. |
| US10163763B1 |
Integrated circuit package with multi-die communication
An integrated circuit package having a first die configured to sense a first physical characteristic and provide a first data signal, and a second die, wherein the first die is configured to transmit the first data signal to the second die, and the second die is configured to determine if there is an error in the first die and transmit the result to a controller. |
| US10163762B2 |
Lead frame with conductive clip for mounting a semiconductor die with reduced clip shifting
A semiconductor assembly includes a semiconductor die comprising lower and upper electrical contacts. A lead frame having a lower die pad is electrically and mechanically connected to the lower electrical contact of the die. An upper conductive member has a first portion electrically and mechanically connected to the upper electrical contact of the die. A lead terminal has a surface portion electrically and mechanically connected to a second portion of the conductive member. The surface portion of the lead terminal and/or the second portion of the conductive member has a series of grooves disposed therein. Packaging material encapsulates the semiconductor die, at least a portion of the lead frame, at least a portion of the upper conducive member and at least a portion of the lead terminal. |
| US10163761B2 |
Power semiconductor arrangement
A power semiconductor device comprises a substrate; and power semiconductor components disposed on and connected thereto. The device includes a housing part with a housing wall having a first cutout. The device has, for making electrical contact therewith, a unitary load connection element which passes through the first cutout in an X direction, is electrically conductive, and has an outer connection section disposed outside the housing part and an inner connection section disposed within the housing part. A first bush which has an internal thread running in the X direction is rotationally fixed and movable in the X direction in the housing wall. The first outer connection section has a second cutout aligned with the first bush. The load connection element has a first holding element disposed near the first cutout, the holding element engaging in a groove in the housing wall which runs perpendicular to the X direction. |
| US10163759B2 |
Apparatus and method of three dimensional conductive lines
An apparatus and method of three dimensional conductive lines comprising a first memory column segment in a first tier, a second memory column segment in a second tier, and conductive lines connecting the first memory column segment to the second memory column segment. In some embodiments a conductive line is disposed in the first tier on a first side of the memory column and in the second tier on a second side of the memory column. |
| US10163756B2 |
Isolation structure for stacked dies
An isolation structure for stacked dies is provided. A through-silicon via is formed in a semiconductor substrate. A backside of the semiconductor substrate is thinned to expose the through-silicon via. An isolation film is formed over the backside of the semiconductor substrate and the exposed portion of the through-silicon via. The isolation film is thinned to re-expose the through-silicon via, and conductive elements are formed on the through-silicon via. The conductive element may be, for example, a solder ball or a conductive pad. The conductive pad may be formed by depositing a seed layer and an overlying mask layer. The conductive pad is formed on the exposed seed layer. Thereafter, the mask layer and the unused seed layer may be removed. |
| US10163751B2 |
Heat transfer structures and methods for IC packages
A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer. |
| US10163750B2 |
Package structure for heat dissipation
A package structure and method of manufacturing is provided, whereby heat dissipating features are provided for heat dissipation. Heat dissipating features include conductive vias formed in a die stack, thermal chips, and thermal metal bulk, which can be bonded to a wafer level device. Hybrid bonding including chip to chip, chip to wafer, and wafer to wafer provides thermal conductivity without having to traverse a bonding material, such as a eutectic material. Plasma dicing the package structure can provide a smooth sidewall profile for interfacing with a thermal interface material. |
| US10163744B2 |
Semiconductor device and method of forming a low profile dual-purpose shield and heat-dissipation structure
A semiconductor device has a substrate including a recess and a peripheral portion with through conductive vias. A first semiconductor die is mounted over the substrate and within the recess. A planar heat spreader is mounted over the substrate and over the first semiconductor die. The planar heat spreader has openings around a center portion of the planar heat spreader and aligned over the peripheral portion of the substrate. A second semiconductor die is mounted over the center portion of the planar heat spreader. A third semiconductor die is mounted over the second semiconductor die. First and second pluralities of bond wires extend from the second and third semiconductor die, respectively, through the openings in the planar heat spreader to electrically connect to the through conductive vias. An encapsulant is deposited over the substrate and around the planar heat spreader. |
| US10163742B2 |
Customized module lid
A method of forming a custom module lid. The method may include placing a multichip module (MCM) between a module base and a temporary lid, target components are exposed through viewing windows in the temporary lid, a top surface of the target components is measured and mapped to create a target profile, the target profile is used to form custom pockets in a custom lid, and the custom pockets correspond to the target components. |
| US10163741B2 |
Scribe lane structure in which pad including via hole is arranged on sawing line
A semiconductor device structure, including integrated circuits of semiconductor chips and scribe lanes between the regions in which the circuits have been formed, has at least one redistribution pad disposed in one of the scribe lanes for simultaneously testing a group of the integrated circuits, and a metal interconnection structure disposed beneath the redistribution pad(s). The metal interconnection structure includes at least conductive via contacting the redistribution pad at the bottom of the pad. The conductive via(s) is/are arranged so that at least a portion of each via remains attached to the redistribution pad when the structure is sawed along the scribe lane. |
| US10163738B2 |
Structure and method for overlay marks
A partially fabricated semiconductor device includes a semiconductor overlay structure. The semiconductor overlay structure includes a first gate stack structure over the semiconductor substrate, the first gate stack structure being configured as an overlay mark in an overlay region of the semiconductor substrate. The semiconductor overlay structure further includes a doped region in the semiconductor substrate surrounding the first gate stack structure. The doped region has a first dopant concentration greater than or equal to a second dopant concentration next to a second gate stack structure in a device region of the semiconductor substrate. |
| US10163737B2 |
Semiconductor device and method of forming build-up interconnect structures over carrier for testing at interim stages
A semiconductor device has a first interconnect structure formed over the carrier. A semiconductor die is disposed over the first interconnect structure after testing the first interconnect structure to be known good. The semiconductor die in a known good die. A vertical interconnect structure, such as a bump or stud bump, is formed over the first interconnect structure. A discrete semiconductor device is disposed over the first interconnect structure or the second interconnect structure. An encapsulant is deposited over the semiconductor die, first interconnect structure, and vertical interconnect structure. A portion of the encapsulant is removed to expose the vertical interconnect structure. A second interconnect structure is formed over the encapsulant and electrically connected to the vertical interconnect structure. The first interconnect structure or the second interconnect structure includes an insulating layer with an embedded glass cloth, glass cross, filler, or fiber. |
| US10163736B2 |
Electroluminescent light source with an adjusted or adjustable luminance parameter and method for adjusting a luminance parameter of the electroluminescent light source
An electroluminescent light source is provided with an adjusted or adjustable luminance parameter wherein: the source includes a set of segments, each segment comprising a discrete electroluminescent element or multiple discrete electroluminescent elements connected permanently to one another and having an emission area; at least a portion of the segments has different emission areas; the source comprising means for controlling at least a portion of the segments. |
| US10163735B2 |
Pressure-activated electrical interconnection by micro-transfer printing
A printed electrical connection structure includes a substrate having one or more electrical connection pads and a micro-transfer printed component having one or more connection posts. Each connection post is in electrical contact with a connection pad. A resin is disposed between and in contact with the substrate and the component. The resin has a reflow temperature less than a cure temperature. The resin repeatedly flows at the reflow temperature when temperature-cycled between an operating temperature and the reflow temperature but does not flow after the resin is exposed to a cure temperature. A solder can be disposed on the connection post or the connection pad. After printing and reflow, the component can be tested and, if the component fails, another component is micro-transfer printed to the substrate, the resin is reflowed again, the other component is tested and, if it passes the test, the resin is finally cured. |
| US10163729B2 |
Silicon and silicon germanium nanowire formation
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process. |
| US10163726B2 |
FinFET devices and methods of forming
In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region. |
| US10163722B2 |
Method and structure for FinFet isolation
A semiconductor device includes a substrate; first and second fins over the substrate and extending lengthwise generally along a first direction; first and second gate stacks over the substrate and the first and second fins respectively; and a first isolation structure disposed between the first and second fins and extending lengthwise generally along a second direction perpendicular to the first direction, wherein the first isolation structure is adjacent to a first source/drain (S/D) region in the first fin and adjacent to a second S/D region in the second fin. |
| US10163719B2 |
Method of forming self-alignment contact
A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack. |
| US10163717B2 |
Method of forming FinFET device by adjusting etch selectivity of dielectric layer
A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights. |
| US10163715B2 |
FinFET device and method of forming same
A FinFET device and a method of forming the same are provided. A method includes forming a fin over a substrate. An isolation region is formed adjacent the fin. A dummy gate structure is formed over the fin. The fin adjacent the dummy gate structure is recessed to form a first recess. The first recess has a U-shaped bottom surface. The U-shaped bottom surface is below a top surface of the isolation region. The first recess is reshaped to form a reshaped first recess. The reshaped first recess has a V-shaped bottom surface. At least a portion of the V-shaped bottom surface comprises one or more steps. A source/drain region is epitaxially grown in the reshaped first recess. |
| US10163689B2 |
Integrated circuit with conductive line having line-ends
A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion. |
| US10163687B2 |
System, apparatus, and method for embedding a 3D component with an interconnect structure
A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure. |
| US10163685B2 |
Methods of forming one or more covered voids in a semiconductor substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures. |
| US10163683B2 |
MOSFETs with channels on nothing and methods for forming the same
A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is between two insulation regions that are in a substrate. The method further includes recessing the insulation regions to expose portions of sidewalls of the semiconductor region, and etching a portion of the semiconductor region, wherein the etched portion of the semiconductor region is under and contacting a bottom surface of the semiconductor layer, wherein the semiconductor layer is spaced apart from an underlying region by an air gap. A gate dielectric and a gate electrode are formed over the semiconductor layer. |
| US10163682B2 |
Methods of forming semiconductor structures
The present disclosure relates to a process for the manufacture of a high resistivity semiconductor substrate, comprising the following stages: providing a first substrate with an in-depth weakened layer; providing a second substrate with a layer of an oxide at the surface; attaching the first substrate to the second substrate so as to form a compound substrate comprising a layer of buried oxide; and cleaving the compound substrate at the level of the weakened layer. The process additionally comprises at least one stage of stabilization, in particular, a stabilization heat treatment, of the second substrate with the layer of oxide before the stage of cleaving at the level of the weakened layer. |
| US10163680B1 |
Sinker to buried layer connection region for narrow deep trenches
A method of forming an IC includes forming a buried layer (BL) doped a second type in a substrate doped a first type. Deep trenches are etched including narrower inner trench rings and wider outer trench rings through to the BL. A first deep sinker implanting uses ions of the second type with a first dose, a first energy, and a first tilt angle. A second deep sinker implant uses ions of the second type with a second dose that |
| US10163679B1 |
Shallow trench isolation formation without planarization
Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region. |
| US10163675B2 |
Method and apparatus for stacking devices in an integrated circuit assembly
Methods and apparatuses for stacking devices in an integrated circuit assembly are provided. A tray for supporting multiple dies of a semiconductor material enables both topside processing and bottom side processing of the dies. The dies can be picked and placed for bonding on a substrate or on die stacks without flipping the dies, thereby avoiding particulate debris from the diced edges of the dies from interfering and contaminating the bonding process. In an implementation, a liftoff apparatus directs a pneumatic flow of gas to lift the dies from the tray for bonding to a substrate, and to previously bonded dies, without flipping the dies. An example system allows processing of both top and bottom surfaces of the dies in a single cycle in preparation for bonding, and then pneumatically lifts the dies up to a target substrate so that topsides of the dies bond to bottom sides of dies of the previous batch, in an efficient and flip-free assembly of die stacks. |
| US10163674B2 |
Circular support substrate for semiconductor
An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means for solving the problems, a circular support substrate is provided that has at least three chords along its circumference, wherein the chords are provided at positions where they do not run linearly symmetrical to the straight line passing through the center axis of the circular support substrate. |
| US10163670B2 |
Device and method for heat treating an object
The present invention relates to a device for heat treating an object, in particular a coated substrate, with an in particular gas-tightly sealable housing that encloses a hollow space, wherein the hollow space has a separating wall, by which the hollow space is divided into a process space for accommodating the object and an intermediate space, wherein the separating wall has one or a plurality of openings, which are implemented such that the separating wall acts as a barrier for the diffusion out of the process space into the intermediate space of a gaseous substance generated in the process space by the heat treatment of the object. The housing has at least one housing section coupled to a cooling device for its active cooling, wherein the separating wall is arranged between the object and the coolable housing section. The invention further relates to the use of a separating wall as a diffusion barrier in a device for heat treating an object as well as a corresponding method for heat treating an object. |
| US10163663B2 |
Substrate processing apparatus, exhaust system and method of manufacturing semiconductor device
A configuration capable of increasing an exhaust capability of an apparatus without degrading an operation of the apparatus includes: a processing furnace; an exhaust unit configured to exhaust a gas from a process chamber defined by the processing furnace, the exhaust unit having a first sidewall and a second sidewall opposite to the first sidewall; and an exhaust device disposed adjacent to the exhaust unit and connected to the exhaust unit via a connecting pipe provided with a vibration-absorbing member, the exhaust device having a first sidewall and a second sidewall opposite to the first sidewall, wherein the processing furnace, the exhaust unit and the exhaust device are disposed on a same plane, and only the first sidewall of the first and the second sidewalls of the exhaust device is disposed in a space defined by extensions of the first and the second sidewalls of the exhaust unit. |
| US10163662B2 |
Fabrication method of semiconductor package
A semiconductor package is provided, which includes: a packaging substrate having opposite first and second surfaces and a plurality of first and second conductive pads formed on the first surface; a chip having opposite active and inactive surfaces and disposed on the first conductive pads via the active surface thereof; a plurality of conductive posts formed on the second conductive pads, respectively; and a first encapsulant formed on the first surface of the packaging substrate for encapsulating the chip and the conductive posts and having a plurality of openings for exposing upper surfaces of the conductive posts, thereby increasing the package density and protecting the chip and the interconnection structure from being adversely affected by intrusion of moisture. |
| US10163656B2 |
Methods for dry etching cobalt metal using fluorine radicals
Embodiments of methods for etching cobalt metal using fluorine radicals are provided herein. In some embodiments, a method of etching a cobalt layer in a substrate processing chamber includes: forming a plasma from a process gas comprising a fluorine-containing gas; and exposing the cobalt layer to fluorine radicals from the plasma while maintaining the cobalt layer at a temperature of about 50 to about 500 degrees Celsius to etch the cobalt layer. |
| US10163653B2 |
Plasma etching method and plasma etching apparatus
A plasma etching method for plasma-etching an object including an etching target film and a patterned mask. The plasma etching method includes a first step of plasma-etching the etching target film using the mask, and a second step of depositing a silicon-containing film using plasma of a silicon-containing gas on at least a part of a side wall of the etching target film etched by the first step. |
| US10163651B1 |
Structure and method to expose memory cells with different sizes
A memory cell with an etch stop layer is provided. The memory cell comprises a bottom electrode disposed over a substrate. A switching dielectric is disposed over the bottom electrode and having a variable resistance. A top electrode is disposed over the switching dielectric. A sidewall spacer layer extends upwardly along sidewalls of the bottom electrode, the switching dielectric, and the top electrode. A lower etch stop layer is disposed over the lower dielectric layer and lining an outer sidewall of the sidewall spacer layer. The lower etch stop layer is made of a material different from the sidewall spacer layer and protects the top electrode from damaging during manufacturing processes. A method for manufacturing the memory cell is also provided. |
| US10163649B2 |
Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer. |
| US10163648B2 |
Method of semiconductor device fabrication having application of material with cross-linkable component
Provided is a material composition and method for that includes providing a primer material including a surface interaction enhancement component, and a cross-linkable component. A cross-linking process is performed on the deposited primer material. The cross-linkable component self-cross-links in response to the cross-linking process to form a cross-linked primer material. The cross-lined primer material can protect an underlying layer while performing at least one process on the cross-linked primer material. |
| US10163647B2 |
Method for forming deep trench structure
A method for forming a deep trench structure is provided. The method includes forming a first recess in a top portion of a substrate and forming a first protective layer on sidewalls of the first recess. The method includes etching a middle portion of the substrate by using the first protective layer as a mask to form a second recess and forming a second protective layer on sidewalls of the second recess. The method also includes etching a bottom portion of the substrate by using the second protective layer as a mask to form a third recess; and removing the first protective layer and the second protective layer to form a deep trench structure. The deep trench structure is constructed by the first recess, the second recess and the third recess, and the deep trench structure has a stair shape. |
| US10163642B2 |
Semiconductor device, method and tool of manufacture
A semiconductor manufacturing tool and process to form semiconductor devices is provided. An edge ring of the semiconductor manufacturing tool comprises a high electron mobility material in order to extend an electrical field and sheath such that curvature from the sheath is moved away from a semiconductor wafer so that an impact from the curvature is reduced or eliminated during an etching process. |
| US10163638B2 |
High-voltage semiconductor device
High-voltage semiconductor devices are provided. The high-voltage semiconductor device includes a substrate having a first conductive type and an epitaxial layer having a second conductive type disposed on the substrate. The epitaxial layer includes a high-voltage unit, a low-voltage unit disposed around the high-voltage unit and a level-shift unit disposed between the high-voltage unit and the low-voltage unit. The level-shift unit includes a source region, a drain region having disposed between the source region and the high-voltage unit, wherein the drain region is electrically connected to the high-voltage unit by a drain electrode disposed above the drain region. The level unit includes a gate electrode disposed between the source region and the drain region. The high-voltage semiconductor device also includes an isolation structure disposed between the high-voltage unit and the low-voltage unit, and the isolation structure is disposed directly under the drain electrode. |
| US10163636B2 |
Method of fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a first material layer over a substrate, forming a middle layer over the first material layer, forming a first hard mask (HM) layer over the middle layer, forming a second HM layer over the first HM layer, forming a first trench in the second HM layer that extends into the first HM layer, forming a second trench in the second HM layer, The second trench is parallel to the first trench. The method also includes forming a first hole feature in the middle layer within the first trench by using the second HM layer and the first HM layer as a mask and forming a second hole feature in the middle layer within the second trench by using the second HM layer as a mask. |
| US10163635B1 |
Asymmetric spacer for preventing epitaxial merge between adjacent devices of a semiconductor and related method
A method for preventing epitaxial merge between adjacent devices of a semiconductor is provided. Embodiments include forming a protection layer over a spacer formed over a first and second plurality of fins deposited within a substrate; pinching off a portion of the protection layer formed within a space between each of the plurality of fins; forming a planarization layer over the protection layer and the spacer; and etching a portion of the spacer to form inner sidewalls between each of the plurality of fins, outer sidewalls of a height greater than the height of the inner sidewalls for preventing the growth of the epitaxial layer beyond the outer sidewalls, or a combination thereof. |
| US10163633B2 |
Non-mandrel cut formation
Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area. |
| US10163627B2 |
Semiconductor device and method for fabricating the same
A semiconductor device includes a substrate, a first dielectric layer, a first semiconductor layer, a second dielectric layer and a second semiconductor layer. The first dielectric layer is disposed on the substrate and includes at least one first trench formed in the first dielectric layer. The first semiconductor layer is disposed on the first dielectric layer and within the at least one first trench. The second dielectric layer is disposed on the first semiconductor layer and includes at least one second trench formed in the second dielectric layer, wherein in a planar view, the at least one first trench and the at least one second trench are not overlapped with each other. The second semiconductor layer is disposed on the second dielectric layer and within the at least one second trench. |
| US10163623B1 |
Etch method with surface modification treatment for forming semiconductor structure
An etching method with a surface modification treatment for forming a semiconductor structure is provided. The method includes providing a semiconductor substrate, forming a silicon nitride (SiN) layer on the semiconductor substrate, and forming a silicon-containing layer on the semiconductor substrate and beside the SiN layer. The silicon-containing layer includes a silicon dioxide layer, a n-type silicon-containing layer, a p-type silicon-containing layer or a combination thereof. The method further includes performing a surface modification treatment onto the SiN layer and the silicon-containing layer by using a surface modification solution, thereby forming a modified layer on the SiN layer and the silicon-containing layer. The method further includes removing a portion of the modified layer and its underlying SiN layer by a wet etching operation, while the other portion of the modified layer and its underlying silicon-containing layer remain, and removing the other portion of the modified layer. |
| US10163616B2 |
Multi-reflecting time-of-flight analyzer
A multi-reflecting time-of-flight mass spectrometer comprises a pair of parallel aligned ion mirrors and a set of periodic lenses for confining ion packets along the drift z-direction. To compensate for time-of-flight spherical aberrations T|zz created by the periodic lenses, at least one set of electrodes are disposed within the apparatus, forming an accelerating or reflecting electrostatic fields which are curved in the z-direction in order to form local negative T|zz aberration. The structure may be formed within an accelerator, within flinging fields or intentionally and locally curved fields of ion mirrors, within electrostatic sector interface, or at curved surface of ion to electron converter at the detector. |
| US10163612B2 |
Online adjustable magnet bar
An end-block for rotatably carrying a sputtering target tube and for rotatably restraining a magnet bar inside the sputtering target tube includes a receptacle for receiving a magnet bar fitting. The receptacle comprises a first part of a signal connector arranged to receive a second part of a signal connector from the magnet bar fitting, and allow a signal connector between the end-block and the magnet bar to be formed. The end-block is adapted for providing protection means to the signal connector for protecting it from degradation, destruction or interference of a power and/or data signal transmitted between the end-block and the magnet bar, due to surrounding cooling fluid and/or surrounding high energy fields. The disclosure provides a corresponding magnet bar, and a method for adjusting a magnetic configuration of a magnet bar in a cylindrical sputtering apparatus. |
| US10163610B2 |
Extreme edge sheath and wafer profile tuning through edge-localized ion trajectory control and plasma operation
An edge ring assembly for a plasma processing chamber is provided, including: an edge ring configured to surround an electrostatic chuck (ESC) that is configured for electrical connection to a first RF power supply, the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface; an annular electrode disposed below the edge ring in the annular step and above the annular shelf; a dielectric ring disposed below the annular electrode for isolating the annular electrode from the ESC, the dielectric ring positioned in the annular step over the annular shelf; and, a plurality of insulated connectors disposed through the ESC and through the dielectric ring, each of the plurality of insulated connectors providing electrical connection between a second RF power supply and the annular electrode. |
| US10163606B2 |
Plasma reactor with highly symmetrical four-fold gas injection
An annular lid plate of a plasma reactor has upper and lower layers of gas distribution channels distributing gas along equal length paths from gas supply lines to respective gas distribution passages of a ceiling gas nozzle. |
| US10163599B1 |
Electron multiplier for MEMs light detection device
An electron multiplier for a Micro-Electro-Mechanical-Systems (MEMS) image intensifier includes an input surface, an emission surface, a plurality of doped ribs, and a plurality of textured surfaces. The input surface receives electrons and the emission surface is opposite the input surface. The plurality of doped ribs extends at least partially between the input surface and the emission surface to form a plurality of pixels. The plurality of textured surfaces are disposed in the plurality of pixels. |
| US10163595B2 |
Gasket, magnetic switch of starter comprising same, and starter provided with magnetic switch
The present invention relates to a gasket, a magnetic switch of a starter including the same, and a starter including the magnetic switch, the gasket including: a membrane which carries out a sealing function and is made of a resin material having flexibility; and a membrane washer provided along the edge of the membrane in order to prevent bending of the membrane, wherein the membrane and the membrane washer are insert injected. Unlike prior art, the present invention can enhance the durability of the membrane by insert injection molding a hard membrane washer into the membrane having flexibility, can enhance a waterproofing performance by enabling the membrane to be firmly fixed to a plunger, and can enhance an assembly performance by enabling assembly through an automatic production line. |
| US10163594B2 |
Electromagnetic relay
An electromagnetic relay including: a base unit that includes a slit having a first wall part and a second wall part, and a first projection projecting from the first wall part of the slit; a terminal that is press-fitted into the slit, and includes a second projection at a position opposite to the first projection; and a preventer that prevents deviation of the second projection against the first projection when the terminal is press-fitted into the slit. |
| US10163593B2 |
Temperature switch
A temperature switch 1 includes first terminal unit 2 having a first terminal 5 and a first fixed contact 6, a switch body unit 3 including a bimetal element 22 in which both ends engage a movable plate 15 holding, via an tongue portion 17, first and second fixed contacts 6 and 8 arranged in an internal center portion of an insulation material 10 at prescribed intervals and also holding a movable contact 18 arranged above them, and a second terminal unit 4 having a second terminal 7 and the second fixed contact 8. The first terminal unit 2, the switch body unit 3, and the second terminal unit 4 are sequentially arranged in line. At an ambient temperature, the bimetal element 22 deforms into a convex shape in the contact direction so as to push out the tongue portion 17 and the movable contact 18 at the center of the convex shape, and the movable contact 18 is closed with respect to the first and second fixed contacts 6 and 8 so that a current flows between the first and second terminals 5 and 7. At an ambient temperature equal to or higher than a prescribed value, the bimetal element 22 causes inversion to become concave in the contact direction, releases the biasing force of the spring property toward the space above the tongue portion 17, the movable contact 18 moves away from the first and second fixed contacts 6 and 8, and a current is cut off. |
| US10163589B2 |
Adapter assemblies for interconnecting surgical loading units and handle assemblies
An adapter assembly configured to be coupled to a surgical loading unit includes a switch, an elongated member, and an annular member. The switch is configured to be toggled in response to the surgical loading unit being coupled to the adapter assembly. The elongated member is in communication with the switch and is resiliently biased in a distal direction toward a locking position in which the switch is toggled. The annular member is disposed adjacent the elongated member and is rotatable between a first orientation, in which the annular member prevents distal movement of the elongated member, and a second orientation, in which the elongated member moves distally to toggle the switch. |
| US10163588B2 |
Electromagnetic relay including yoke-retaining bottom plate
An electromagnetic relay includes a base, a fixed contact terminal including a fixed contact, and fixed to the base, a movable contact terminal including a movable contact that contacts the fixed contact, an electromagnet that generates a magnetic field when an electric current flows through a coil wrapped around an iron core, an armature connected to the movable contact terminal, and moved by a magnetic force generated in the electromagnet, a yoke including a vertical part, and a horizontal part connected to the iron core, and a bottom plate formed of an insulator, and covering a surface of the horizontal part facing away from the iron core. The bottom plate includes a yoke insertion part into which the horizontal part is inserted in a direction parallel to the horizontal part. |
| US10163584B1 |
Low-silver, low-profile electrical contact apparatus and assembly
An electrical contact apparatus having low silver content and defined thickness and length geometry. The electrical contact apparatus has a contact body made of a silver-containing alloy having SC≤60 wt. %, and having L/T≥5.4, wherein L is a longest contact length dimension of the contact body, T is a maximum contact thickness dimension of the contact body, SC is the silver content in wt. %, and L/T is a contact dimension ratio. Electrical contact assemblies, circuit breaker electrical contact subassemblies, and methods of operating a circuit breaker electrical contact subassembly are disclosed, as are other aspects. |
| US10163583B2 |
Graphene oxide and carbon nanotube ink and methods for producing the same
An energy device including a paper based substrate having a top surface and a bottom surface, and a graphene oxide and carbon nanotube composite deposited onto at least the top surface. The energy device can be used as an electrode in, for example, a supercapacitor. |
| US10163580B2 |
OLED device and method for manufacturing the same
An OLED device and a method for manufacturing the OLED device are provided. The OLED device includes a substrate, a first electrode layer, an electron injection layer, an electron transport layer, a photoactive layer, a hole transport layer, and a second electrode layer, which are sequentially disposed on the substrate. The photoactive layer includes an exciton control layer and an active material layer, the active material layer includes a perovskite material and a small molecule luminescent material, and a doping molar ratio of the small molecular luminescent material ranges from 0.1% to 15%. |
| US10163579B2 |
Glass materials for large scale dye-sensitized solar cell sealing and pastes comprising the same
Disclosed is a glass composition for sealing a large-area dye-sensitized solar cell, and more particularly, to a glass composition which may be uniformly bonded to a large-area without reacting with an electrolyte. |
| US10163578B2 |
Photovoltaic device having an electrically conductive transparent substrate and light absorbing compound
An oxadiazole dye for use as an organic photosensitizer. The oxadiazole dye comprising donor-π-spacer-acceptor type portions in which at least one of an oxadiazole isomer acts as a π-conjugated bridge (spacer), a biphenyl unit acts as an electron-donating unit, a carboxyl group act as an electron acceptor group, and a cyano group acts as an anchor group. An optional thiophene group acts as part of the π-conjugated bridge (spacer). The dye for use as organic photosensitizers in a dye-sensitized solar cell and in photodynamic therapies. Computational DFT and time dependent DFT (TD-DFT) modeling techniques showing Light Harvesting Efficiency (LHE), Free Energy for Electron Injection (ΔGinject), Excitation Energies, and Frontier Molecular Orbitals (FMOs) indicate that the series of dye comprise a more negative ΔGinject and a higher LHE value; resulting in a higher incident photon to current efficiency (IPCE). |
| US10163577B2 |
Aluminum electrolytic capacitor and assembly thereof
Designs of a capacitor housing and method of assembly are presented. A case for an electrolytic capacitor includes a non-conducting cover, a non-conducting ring component, and a non-conducting plate. The non-conducting cover has a patterned groove on a surface of the non-conducting cover. The non-conducting ring component has a shape that is substantially the same as a shape of the non-conducting cover, and is coupled to the non-conducting cover via the patterned groove of the non-conducting cover. The non-conducting plate has a shape that is substantially the same as the shape of the non-conducting cover, and has a patterned groove on a surface of the non-conducting plate. The non-conducting ring component is coupled to the non-conducting plate via the groove of the non-conducting plate. |
| US10163576B2 |
Capacitor cathode foil structure and manufacturing method thereof
The instant disclosure relates to a manufacturing method of capacitor cathode foil structure, comprising the following steps. The first step is providing a base foil, subsequently inserting the foil into a reactor. The next step is executing a heating process for heat the base foil to a temperature region of 400° C. to 1000° C. The next step is directing a carbon containing precursor gas into the reactor. The last step is executing a cooling process for cooling the base foil to a temperature below 100° C. to deposit a graphene-based layer on one surface of the base foil, wherein the graphene-based layer is consisted of a plurality of graphene-based thin films in stacked arrangement. |
| US10163572B2 |
Ceramic-wound-capacitor with lead lanthanum zirconium titanate dielectric
A ceramic-wound-capacitor includes a first-electrically-conductive-layer, a dielectric-layer, a second-electrically-conductive-layer, and a protective-coating. The dielectric-layer is formed of lead-lanthanum-zirconium-titanate (PLZT). The protective-coating has a thickness of less than ten micrometers (10 μm) and provides electrical isolation between the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor. A method for fabricating the ceramic-wound-capacitor includes the steps of feeding a carrier-strip, depositing a sacrificial layer, depositing a first-electrically-conductive-layer, depositing a dielectric-layer, and depositing a second-electrically-conductive-layer to form an arrangement coupled to the carrier-strip by the sacrificial-layer, separating the arrangement from the carrier-strip and sacrificial-layer, creating an exposed-surface of the first-electrically-conductive-layer, applying a protective-coating to the exposed-surface of the first-electrically-conductive-layer, winding the arrangement with the protective-coating to form a ceramic-wound-capacitor, where the protective-coating is in direct contact with the first-electrically-conductive-layer and the second-electrically-conductive-layer of the ceramic-wound-capacitor. |
| US10163567B2 |
Multi-layered aluminum oxide capacitor
The present invention relates to a multi-layered aluminum oxide capacitor comprising an aluminum substrate; a plurality of aluminum oxide layer formed in at least a portion of on both sides or one side of the substrate with respect to the aluminum substrate; and a plurality of electrode layers formed on the aluminum oxide layers. According to the present invention, manufacturing process is more simplified since Al2O3 insulation layer is formed by anodizing the aluminum layer without forming an extra insulation layer after forming the aluminum layer, so that the manufacturing cost can be reduced, and also a multi-layered capacitor having a high capacitance and a high reliability can be provided by stacking capacitors comprising a plurality of aluminum oxide layers using a more simplified process according to the present invention. |
| US10163565B2 |
Method for winding a multi-layer flat wire coil
The present invention is related to a method for winding a dual-layer flat wire coil, and to method for winding a multi-layer flat wire coil. Furthermore, the present invention is related to a device for winding such coils and to a dual-layer flat wire coil and to a multi-layer flat wire coil obtainable by performing the method of the present invention. Finally, the invention is related to a linear motor comprising such a dual-layer flat wire coil and/or multi-layer flat wire coil. According to the invention, an auxiliary winding core is used to temporarily store wire that is intended to form the odd layer of any pair of layers in the multi-layer coil. |
| US10163563B2 |
Reactor
Provided is a reactor in which an accessory member that is attached to the reactor is integrated with an assembly. The reactor includes an assembly of a coil having a winding portion and a magnetic core and an accessory member that is attached to the assembly. In this reactor, an outer core portion of the magnetic core is made of a composite material obtained by dispersing soft magnetic powder in a resin, the outer core portion protruding from the winding portion, and the accessory member includes an embedded portion that is embedded in the outer core portion and a functional portion that protrudes outward from the outer core portion. |
| US10163561B1 |
Distributed planar inductor with multi-2D geometry for energy storage
A distributed planar inductor is provided with energy storage components featuring high energy storage density, multilayer winding and low copper losses. The inductor includes a magnetic core with a plurality of vertically oriented posts, a plurality of horizontally oriented plates coupled to define an interior, and a conductive winding extending through the interior. The vertical posts each include a plurality of energy storage elements coplanar in orientation with respect to the winding and having a substantially two dimensional structure. The conductive winding may comprise co-planar winding tracks extending through the interior, for example vertically coupled in parallel. A set of co-planar winding tracks may correspond to respective layers in a multilayer printed circuit board, and for example may comprise printed circuit board tracks vertically interconnected by vias extending there-through. |
| US10163558B2 |
Vertically stacked inductors and transformers
The present disclosure relates generally to semiconductor structures, and more particularly, to structures and methods for implementing high performance vertically stacked inductors and transformers. The structure includes: a first conductor composed of a redistribution line; a second conductor composed of a back end of line wiring layer, coupled to the redistribution line; and a ferro magnetic material between the first conductor and the second conductor. |
| US10163557B2 |
Helical plated through-hole package inductor
Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall. |
| US10163556B2 |
Multilayer seed pattern inductor, manufacturing method thereof, and board having the same
A multilayer seed pattern inductor includes: a magnetic body containing a magnetic material; and an internal coil part encapsulated in the magnetic body, wherein the internal coil part includes a seed pattern and a surface plating layer disposed on the seed pattern, the seed pattern being formed as two or more layers. |
| US10163554B2 |
Transformer and power supply device including the same
A transformer includes a magnetic core, a first coil unit and a second coil unit. The first coil unit is disposed within the magnetic core and includes a laminated board having layers laminated therein and conductive patterns. Respective ones of the conductive patterns are disposed on the laminated layers. The second coil unit includes a conductive wire spaced apart from the conductive patterns of the laminated board by an insulating distance. The conductive wire includes a triple-insulated wire surrounded by three sheets of insulating paper to maintain the insulating distance from the conductive patterns. |
| US10163553B2 |
Resistor and method for producing the same
Provided is a resistor including a first electrode, a second electrode, and a resistive element disposed between the first and second electrodes. Each of the first and second electrodes includes a main electrode portion and a narrow electrode portion with a narrower width than that of the main electrode portion. The resistive element is disposed between the two narrow electrode portions. |
| US10163552B2 |
Rotary variable resistor
A rotary variable resistor includes a resistance circuit module, a fixation frame, a brush assembly and a rotor shaft. The resistance circuit module has a circuit board, an output circuit, three input circuits and a resistance ring. The output circuit includes a brush contact port having an annular brush contact area and an output port extending out from the brush contact port. Each input circuit has a resistor contact end and an input port. The three resistor contact ends are evenly annularly separated. The resistance ring co-axially and annularly spaced to the brush contact port contacts the resistor contact ends. The fixation frame is fixedly mounted on the resistance circuit module. The brush assembly rotatably restrained by the fixation frame bridges the annular brush contact area and the resistance ring. The rotor shaft for driving the brush assembly is connected with the brush assembly. |
| US10163551B2 |
Methods of manufacturing a coated conducting wire assembly
A method of manufacturing a coated conducting wire assembly includes forming a conducting wire assembly by twist-deforming a conducting wire bundle, forming a coated conducting wire assembly by covering the conducting wire assembly with an insulation coating, and annealing the coated conducting wire assembly. The conducting wire bundle is formed by bundling a plurality of conducting wires. The conducting wire assembly includes a parallel portion, a left-wound portion, and a right-wound portion. The annealing is performed by heating and holding the coated conducting wire assembly at an annealing temperature while applying tension to the covered conducting wire assembly. |
| US10163549B2 |
Oxide superconducting wire
An oxide superconducting wire wherein an outer periphery of an oxide superconductor is covered with a plating layer (stabilizing layer). In addition, the oxide superconductor includes: an oxide superconducting laminate that is formed by a tape-shaped substrate, an interlayer, and an oxide superconducting layer, in which the interlayer and the oxide superconducting layer are laminated on a main surface of the substrate; and an undercoat stabilizing layer that is laminated on an outer periphery of the oxide superconducting laminate. The undercoat stabilizing layer includes: a first undercoat stabilizing layer formed of Ag or an Ag alloy; and a second undercoat stabilizing layer formed of one of Cu, Ni, Pb, Bi, and an alloy containing Cu, Ni, Pb or Bi as a major component. |
| US10163545B2 |
Polymeric compositions with voltage stabilizer additive
Disclosed are polymeric compositions with improved breakdown strength. The polymeric compositions contain a polyolefin and a voltage stabilizing agent. The voltage stabilizing agent is a diphenoxybenzene and/or a benzanilide. The present polymeric compositions exhibit improved breakdown strength when applied as an insulating layer for power cable. |
| US10163538B2 |
Method of preparing graphene-coated alumina and graphene-coated alumina prepared using the method
A method of preparing graphene-coated alumina, the method including: (1) preparing a liquid polyacrylonitrile (LPAN) solution, stirring the LPAN solution at between 100 and 200° C. to yield a cyclized polyacrylonitrile solution; (2) heating the cyclized LPAN solution at between 200 and 300° C. to yield a thermally-oxidized polyacrylonitrile (OPAN) having a ladder structure; (3) mixing the thermally-oxidized polyacrylonitrile with an aluminum compound, to yield a mixture, and adding a solvent to the mixture, uniformly mixing, to yield a polyacrylonitrile-coated aluminum compound; (4) drying the polyacrylonitrile-coated aluminum compound until the solvent is evaporated, to yield a carbonized precursor-coated aluminum compound; and (5) calcining the carbonized precursor-coated aluminum compound in the presence of an inert gas flow, to yield graphene-coated alumina. |
| US10163535B2 |
Processing materials
Biomass (e.g., plant biomass, animal biomass, and municipal waste biomass) is processed to produce useful intermediates and products, such as energy, fuels, foods or materials. For example, systems and methods are described that can be used to treat feedstock materials, such as cellulosic and/or lignocellulosic materials, while cooling equipment and the biomass to prevent overheating and possible distortion and/or degradation. The biomass is conveyed by a conveyor, which conveys the biomass under an electron beam from an electron beam accelerator. The conveyor can be cooled with cooling fluid. The conveyor can also vibrate to facilitate exposure to the electron beam. The conveyor can be configured as a trough that can be optionally cooled. |
| US10163526B2 |
Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing
The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense amplifier which is connected to the twin-cell memory and is configured to sense a current differential and latch a differential voltage based on the current differential, and at least one current source which is connected to the current sense amplifier and is configured to add an offset current to the current sense amplifier to create the differential voltage. |
| US10163515B1 |
Memory system having feature boosting and operating method thereof
A semiconductor memory system and an operating method thereof include a plurality of memory devices; and a memory controller including a feature booster and a linear predictor and coupled with the plurality of memory devices, wherein the controller is configured to collect NAND data from at least 1 data point, and model the collected NAND data with a mixture model, wherein the mixture model includes parameters and at least two latent variables modeled with different distribution modeling, the feature booster is configured to predict the parameters, and the linear predictor is configured to predict feature information. |
| US10163509B2 |
Method and apparatus for storing information using a memory able to perform both NVM and DRAM functions
A memory device is able to store data using both on-chip dynamic random-access memory (“DRAM”) and nonvolatile memory (“NVM”). The memory device, in one aspect, includes NVM cells, word lines (“WLs”), a cell channel, and a DRAM mode select. The NVM cells are capable of retaining information persistently and the WLs are configured to select one of the NVM cells to be accessed. The cell channel, in one embodiment, is configured to interconnect the NVM cells to form a NVM string. The DRAM mode select can temporarily store data in the cell channel when the DRAM mode select is active. |
| US10163488B2 |
SRAM structure with reduced capacitance and resistance
A structure includes an SRAM cell includes a first and a second pull-up MOS device, and a first and a second pull-down MOS device forming cross-latched inverters with the first pull-up MOS device and the second pull-up MOS device. A first metal layer is over the gate electrodes of the MOS devices in the SRAM cell. The structure further includes a first metal layer, and a CVss landing pad, wherein the CVss landing pad has a portion in the SRAM cell. The CVss landing pas is in a second metal layer over the first metal layer. A word-line is in the second metal layer. A CVss line is in a third metal layer over the second metal layer. The CVss line is electrically coupled to the CVss landing pad. |
| US10163486B1 |
Command signal clock gating
A semiconductor device includes a clock gating tree comprising a first clock gating stage and a second clock gating stage. The first clock gating stage is configured to receive an activate detection signal and to activate clocking events in the second clock gating stage in response to the activate detection signal. The clocking events are not activated in the absence of the activate detection signal. |
| US10163483B2 |
Dynamic reference voltage determination
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A first value may be written to a first memory cell and a second value may be written to a second memory cell. Each value may have a corresponding voltage when the memory cells are discharged onto their respective digit lines. The voltage on each digit line after a read operation may be temporarily stored at a node in electronic communication with the respective digit line. A conductive path may be established between the nodes so that charge sharing occurs between the nodes. The voltage resulting from the charge sharing may be used to adjust a reference voltage that is used by other components. |
| US10163474B2 |
Apparatus and method of clock shaping for memory
A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value. |
| US10163473B2 |
Nonvolatile memory device, semiconductor device, and method for operating semiconductor device
A nonvolatile memory device may include a plurality of cell strings including a plurality of memory cells serially coupled to one another; a plurality of bit lines coupled to a corresponding cell string of the plurality of cell strings; a plurality of page buffers each including a plurality of latches and coupled to a corresponding bit line of the plurality of bit lines; a first control circuit suitable for controlling the plurality of latches to perform an operation corresponding to an activated command signal of a plurality of command signals in an access operation; and a second control circuit suitable for activating one or more of the plurality of command signals, while controlling operations of the plurality of cell strings and the plurality of bit lines in the access operation. |
| US10163469B2 |
System and method for write data bus control in a stacked memory device
Apparatuses and methods for transmitting data between a plurality of chips are described. An example apparatus includes: a first chip, wherein the first chip includes a receiver that receives a data strobe signal and further generates an internal strobe signal responsive, at least in part, to the data strobe signal, the internal strobe signal including a first edge and a second edge following the first edge; a buffer circuit coupled to a set of input terminals and captures first data at the set of input terminals responsive, at least in part, to the first edge of the internal strobe signal and further captures second data at the set of input terminals responsive, at least in part, to the second edge of the internal strobe signal; a driver coupled between the buffer circuit and a set of data terminals and configured to be activated to provide the first and second data from the buffer circuit to the set of data terminals responsive, at least in part, to a control signal; and a width expanding circuit that provides the control signal responsive, at least in part, to the internal strobe signal. |
| US10163462B1 |
Two-pass logical write for interlaced magnetic recording
An exemplary write method disclosed herein includes receiving a request to write data to a consecutive sequence of logical block addresses (LBAs) that is the mapped to a non-contiguous sequence of data tracks on a storage medium, and writing the data of the consecutive sequence of LBAs to a non-contiguous sequence of data tracks on the storage medium and according to a consecutive track order. |
| US10163456B2 |
Near-field transducer with recessed region
A near-field transducer is situated at or proximate an air bearing surface of the apparatus and configured to facilitate heat-assisted magnetic recording on a medium. The near-field transducer includes an enlarged region comprising plasmonic material and having a first end proximate the air bearing surface. The near-field transducer also includes a disk region adjacent the enlarged region and having a first end proximate the air bearing surface. The disk region comprises plasmonic material. A peg region extends from the first end of the disk region and terminates at or proximate the air bearing surface. The near-field transducer further includes a region recessed with respect to the peg region. The recessed region is located between the peg region and the first end of the enlarged region. |
| US10163454B2 |
Training deep neural network for acoustic modeling in speech recognition
A method is provided for training a Deep Neural Network (DNN) for acoustic modeling in speech recognition. The method includes reading central frames and side frames as input frames from a memory. The side frames are preceding side frames preceding the central frames and/or succeeding side frames succeeding the central frames. The method further includes executing pre-training for only the central frames or both the central frames and the side frames and fine-tuning for the central frames and the side frames so as to emphasize connections between acoustic features in the central frames and units of the bottom layer in hidden layer of the DNN. |
| US10163452B2 |
Electronic device for speech recognition
An electronic device including a voice obtaining microphone configured to receive a voice signal including a noise at a first level; a noise obtaining microphone configured to receive a voice signal including a noise at a second level higher than the first level; and a controller configured to estimate the noise at the second level from the voice signal received by the noise obtaining microphone, remove the noise at the first level from the voice signal received by the voice obtaining microphone based on the estimated noise, and perform an operation corresponding to the voice signal having the noise at the first level eliminated therefrom. |
| US10163451B2 |
Accent translation
Techniques for accent translation are described herein. A plurality of audio samples may be received, and each of the plurality of audio samples may be associated with at least one of a plurality of accents. Audio samples associated with at least a first accent of the plurality of accents may be compared to audio samples associated with at least one other accent of the plurality of accents. A translation model between the first accent and a second accent may be generated. An input audio portion in a first spoken language may be received. It may be determined whether the input audio portion is substantially associated with the first accent, and if so, an output audio portion substantially associated with the second accent in the first spoken language may be outputted based, at least in part, on the translation model. |
| US10163450B2 |
Linear predictive analysis apparatus, method, program and recording medium
An autocorrelation calculating part calculates autocorrelation Ro(i) from an input signal. A predictive coefficient calculating part performs linear predictive analysis using modified autocorrelation. R′o(i) obtained by multiplying the autocorrelation Ro(i) by a coefficient wo(i). Here, a case is comprised where, for at least part of each order i, the coefficient wo(i) corresponding to each order i monotonically decreases as a value having positive correlation with a pitch gain in an input signal of a current frame or a past frame increases. |
| US10163449B2 |
Stereo audio encoder and decoder
The present disclosure provides methods, devices and computer program products for encoding and decoding a stereo audio signal based on an input signal. According to the disclosure, a hybrid approach of using both parametric stereo coding and a discrete representation of the stereo audio signal is used which may improve the quality of the encoded and decoded audio for certain bitrates. |
| US10163444B2 |
Apparatus and method for generating an error concealment signal using an adaptive noise estimation
An apparatus for generating an error concealment signal, includes: an LPC representation generator for generating a replacement LPC representation; an LPC synthesizer for filtering a codebook information using the replacement LPC representation; and a noise estimator for estimating a noise estimate during a reception of good audio frames, wherein the noise estimate depends on the good audio frames representation generator is configured to use the noise estimate estimated by the noise estimator in generating the replacement LPC representation. |
| US10163443B2 |
Methods and systems for detecting and processing speech signals
Provided are methods, systems, and apparatuses for detecting, processing, and responding to audio signals, including speech signals, within a designated area or space. A platform for multiple media devices connected via a network is configured to process speech, such as voice commands, detected at the media devices, and respond to the detected speech by causing the media devices to simultaneously perform one or more requested actions. The platform is capable of scoring the quality of a speech request, handling speech requests from multiple end points of the platform using a centralized processing approach, a de-centralized processing approach, or a combination thereof, and also manipulating partial processing of speech requests from multiple end points into a coherent whole when necessary. |
| US10163442B2 |
Methods and systems for detecting and processing speech signals
Provided are methods, systems, and apparatuses for detecting, processing, and responding to audio signals, including speech signals, within a designated area or space. A platform for multiple media devices connected via a network is configured to process speech, such as voice commands, detected at the media devices, and respond to the detected speech by causing the media devices to simultaneously perform one or more requested actions. The platform is capable of scoring the quality of a speech request, handling speech requests from multiple end points of the platform using a centralized processing approach, a de-centralized processing approach, or a combination thereof, and also manipulating partial processing of speech requests from multiple end points into a coherent whole when necessary. |
| US10163440B2 |
Generic virtual personal assistant platform
A method for assisting a user with one or more desired tasks is disclosed. For example, an executable, generic language understanding module and an executable, generic task reasoning module are provided for execution in the computer processing system. A set of run-time specifications is provided to the generic language understanding module and the generic task reasoning module, comprising one or more models specific to a domain. A language input is then received from a user, an intention of the user is determined with respect to one or more desired tasks, and the user is assisted with the one or more desired tasks, in accordance with the intention of the user. |
| US10163433B2 |
Acoustic comfort in the passenger compartment of a motor vehicle
An automotive active brake noise damping system to actively damp braking noise perceivable in the passenger compartment of a motor vehicle comprising a braking system comprising a plurality of braking assemblies associated with wheels of the motor vehicle. The automotive active brake noise damping system comprises a sensory system to sense quantities that allow braking noise perceived in the passenger compartment of the motor vehicle and generated by the braking assemblies during braking to be estimated, an audio system to diffuse sounds in the passenger compartment of the motor vehicle, and an electronic control unit connected to the sensory system and the audio system, and programmed to control the audio system based on the quantities sensed by the sensor system to actively damp the braking noise perceived in the passenger compartment of the motor vehicle. The sensory system comprises vibration sensors, conveniently in the form of piezoelectric accelerators, which are applied to the braking assemblies to sense the amplitude of the vibrations generated by the braking assemblies during braking, and the electronic control unit is programmed to store a mathematical model, which correlates vibrations generated by the braking assemblies during braking with corresponding braking noise perceived in the passenger compartment of the motor vehicle and produced by the braking assemblies during braking, estimate the braking noise perceived in the passenger compartment of the motor vehicle and generated by the braking assemblies of the braking system during braking as a function of the vibrations generated by the braking assemblies during braking and sensed by the vibration sensors applied to the braking assemblies and of the stored mathematical model, compute an interfering sound to be diffused in the passenger compartment of the motor vehicle to damp the braking noise perceived in the passenger compartment of the motor vehicle and generated by the braking assemblies during braking, and control the audio system to cause it to diffuse the computed interfering sound. |
| US10163430B2 |
Telescopically extendable collapsible pedalboard
An expandable collapsible pedalboard for supporting effects pedals or other audio processing units features a first section having a first platform, and a second section having a second platform of lesser elevation and width than said first platform. The second section is telescopically mated with the first section for sliding movement in a longitudinal direction between a retracted position placing at least a majority of the second platform beneath said first platform, and an extended position reaching outwardly beyond an end of said first section to reveal more of the second platform from beneath said first platform. Multiple pedalboards can be laid out side-by-side and fastened together to collectively form a larger modular pedalboard. A hollow space delimited between side walls of the second section can accommodate one or more power supply components for the effects pedals or other audio processing units. |
| US10163427B1 |
Percussion musical instrument
A percussion musical instrument constructed to be played by striking the instrument with one or both of a person's feet comprising a body having at least one surface area to which is affixed at least one snare mechanism bearing on the surface area in a manner to be responsive to the striking of the feet on a second surface area of the body. |
| US10163423B2 |
Backlight control and image compensation method applied to display and associated control method
A control method of a display includes a statistics circuit, a backlight determining circuit and a backlight control circuit. The display includes a backlight module having a maximum luminance. The statistics module receives frame, and generates luminance statistical information of a plurality of blocks included in the frame. The backlight determining circuit determines a backlight intensity corresponding to each of the blocks according to the luminance statistical information of the blocks and the maximum luminance. At least one of the backlight intensities corresponding to the blocks is greater than a normal luminance, which is a backlight intensity corresponding to one of the blocks when a maximum power is evenly distributed on light emitting elements of the display. The backlight control circuit controls the luminance of the backlight module according to the backlight intensities. |
| US10163422B1 |
Accelerated secondary display system
An accelerated secondary display system comprising a display adapter with a display simulator, a host computer with host software, a client device with a screen and client software. The display simulator is configured to send display characteristics to the host computer. The host computer is configured to receive the display characteristics and render an image with hardware acceleration into a frame buffer. The host software is configured to cause the host computer to stream image data over a communication channel, the image data based on the image in the frame buffer. The client software is configured to receive the image data over the communication channel and present a copy of the image on the screen based on the image data. |
| US10163410B2 |
Driving method for image display apparatus
A driving method for an image display apparatus which includes an image display panel having a plurality of pixels arrayed in a two-dimensional matrix and each configured from a first subpixel for displaying a first primary color, a second subpixel for displaying a second primary color, a third subpixel for displaying a third primary color and a fourth subpixel for displaying a fourth color, and a signal processing section. The signal processing section is capable of calculating a first subpixel output signal, a second subpixel output signal, a third subpixel output signal, and a fourth subpixel output signal. The driving method includes a step of calculating a maximum value (Vmax(S)) of brightness, a saturation (S) and brightness (V(S)), and determining the expansion coefficient (α0). |
| US10163408B1 |
LCD image compensation for LED backlighting
A method includes determining a display backlight level based upon an ambient light level, using image content of incoming image data to adjust the display backlight level based upon image content to produce an image-compensated backlight value, and adjusting pixel values in the image data as needed based upon the image-compensated backlight value. |
| US10163405B2 |
Configurable lighting system
A luminaire can include a housing having at least one outer surface that forms a cavity. The luminaire can also include an aperture that traverses the at least one outer surface of the housing. The luminaire can further include a substrate disposed within the cavity. The luminaire can also include an electrical connector disposed on the substrate adjacent to the aperture. The luminaire can further include a dial coupled to the electrical connector, where dial has a range of positions, where each position within the range of positions of the dial corresponds to a discrete correlated color temperature (CCT) output by multiple light sources of the luminaire. |
| US10163404B2 |
Image generator for suppressing a gap between two adjacent reflective surfaces
The present image generator visually suppresses a gap between two adjacent reflective surfaces of a reflective display. The image generator comprises memory and a processor. The memory stores position of the gap on the reflective display. The processor analyzes a stream of images to be displayed on the reflective display and determines corresponding lighting data alongside the gap. The processor further controls at least one lighting unit located behind a seam inserted in the gap based on the determined lighting data. |
| US10163397B2 |
Pixel unit and display apparatus having the pixel unit
A pixel unit includes a first organic light emitting diode for a front-side emission, a second organic light emitting diode for a back-side (both-sides) emission, and a pixel circuit configured to driver the first and second organic light emitting diodes. The pixel unit PU may include a pixel circuit, a first organic light emitting diode and a second organic light emitting diode. |
| US10163394B2 |
Pixel circuit and method for driving the same, display apparatus
Pixel circuit, driving method therefor and display apparatus are provided. The pixel circuit includes driving transistor, light-emitting device, storage capacitor, gating module, compensating module and switching module. First end of storage capacitor is connected to gate electrode of driving transistor, and second end thereof is connected to first electrode of driving transistor. Compensating module includes reset sub-module having output terminal connected to second electrode of driving transistor and configured to charge first electrode of driving transistor in reset stage to store threshold voltage of driving transistor in storage capacitor, and voltage dividing sub-module having first terminal connected to first electrode of driving transistor and second terminal connected to high-level input terminal such that voltage dividing sub-module is connected in series with storage capacitor. According to the invention, the effect of threshold voltage and IR drop on uniformity of display can be reduced, which improves display effect. |
| US10163389B2 |
Electronic device including an organic light emitting diode display device, and a method of compensating for a degradation of an organic light emitting diode display device in an electronic device
An electronic device includes an organic light emitting diode (OLED) display device, and a display controller configured to provide image data to the OLED display device. The display controller calculates stress data for the OLED display device by accumulating the image data, and determines a compensation factor for the OLED display device based on the stress data. The OLED display device receives the image data and the compensation factor from the display controller, converts the image data into compensated image data based on the compensation factor, and displays an image based on the compensated image data. |
| US10163386B2 |
Display device and driving method thereof
Disclosed is a display device that can rapidly recover from a fail situation. The display device includes: a display panel; a source drive IC configured to supply a data signal to the display panel and including a calibrating unit; a timing controller configured to supply a data control signal and a frame data to the source drive IC; and a common bus line formed between the source drive IC and the timing controller. The calibrating unit sets and stores a calibration value in response to the data control signal during an initialization period before receiving the frame data from the timing controller, and transmits the calibration value to the timing controller through the common bus line. |
| US10163380B2 |
Image corrector, display device including the same and method for displaying image using display device
There is provided an image corrector including a shift determiner configured to determine a shift direction and a shift amount of an image corresponding to first image data, an area determiner configured to divide the image into a plurality of areas and, in accordance with the shift direction, to determine a first area of the plurality of areas as a reduction area and a second area of the plurality of areas as an enlargement area, and an image data generator configured to set second image data corresponding to the shift amount of the image corresponding to the first area. |
| US10163378B1 |
Multi-panel display project board whose header panel pivots between fold-in and fold-out orientations without any need for a pivotable footer or pivotable braces
A multi-panel display project board with a center panel between two side panels and with a header panel movable between a fold-in position and a fold-out position. Each panel has a medium sandwiched between two linerboards. Creases between the panels are formed by slitting linerboard beneath the creases or by forming the creases each as a crushed score. The header panel has a long segment separated from two shorter segments by segment creases. When the header panel is in the fold-in position after pivoting from a fully folded orientation about panel creases, the shorter segments define respective obtuse angles with the long segment. In the fold-out position after pivoting the header panel about additional creases, the shorter segments define respective reflex angles instead. There is no footer or braces. |
| US10163377B2 |
Programmable base to hold and illuminate a panel assembly
A universal base for one or more panel assemblies has a processor that receives and processes instructions from at least one non-transitory computer readable storage medium. The instructions direct an illumination sequence to be executed by the processor to illuminate lights in the base. The at least one non-transitory computer readable storage medium is removably connected to the base such that when it is removed and a different second non-transitory computer readable storage medium is connected with the base, the lights are illuminated in a second illumination sequence in accordance with a set of second illumination instructions. |
| US10163375B2 |
Foldable display apparatus
A foldable display apparatus is provided. The foldable display apparatus includes a first substrate, a second substrate, a flexible display panel having a first display area, a pliable display area and a second display area, which are sequentially connected, a first hinge base, a second hinge base, and a rotary connecting rod. An end of the rotary connecting rod is connected to the first hinge base, and the other end is connected to the second hinge base. When the rotary connecting rod rotates to the folded state, the first substrate and the second substrate are paralleled to and opposite each other. |
| US10163374B2 |
Display unit and electronic apparatus
A display unit includes a display region, a peripheral region, and an inorganic film. The display region is a region in which a plurality of pixels are disposed. The peripheral region is provided outside the display region. The inorganic film is provided in the peripheral region, and surrounds the display region continuously. |
| US10163373B2 |
Method for updating the position of electronic price tag by graphic code
A method for updating the position of electronic price tag by graphic code including: step 1, placing a plurality kinds of commodities on a commodity shelf, mounting an electronic price tag screen on the commodity shelf and below the commodities; step 2, displaying at least n position graphic codes with an even interval on the electronic price tag screen; step 3, carrying out a first scan to send the commodity information to a server; step 4, carrying out a second scan to check a position of the commodity; step 5, sending a plurality of size graphic codes with different size information to a position where the position graphic code in step 4 locates; step 6, selecting a size graphic code with a proper size for a third scan by the supermarket tally clerk; step 7, generating a commodity tag by the server. |
| US10163372B1 |
Self-destructive documents for information security and privacy protection
The inventor here discloses destructive (self-destructing) documents useful for the protection of confidential information. The invention comprises a document which can be easily and instantly broken down into dozens of individual components, hence obliterating any information contained thereon. As the self-destruction of the document requires no extraneous equipment for destruction and guarantees elimination of readable data, the invention represents a vast improvement over the state of the art. Numerous embodiments of the document of the invention specialized for different applications are illustrated and described. |
| US10163371B1 |
Rotating bit values based on a data structure while generating a large, non-compressible data stream
Generating non-compressible data streams is disclosed, including: receiving a sequence comprising a plurality of byte values calculated from an initialization parameter and a constrained prime number; determining a data structure index from a plurality of bits within at least one of the plurality of byte values; retrieving a rotation value from a data structure, wherein the rotation value is stored in the data structure at the data structure index; and rotating a portion of the sequence based on a rotation value to form a rotated sequence, wherein the rotated sequence comprises byte values substantially defeating a predictive compression algorithm. |
| US10163368B2 |
Acoustic representations of environments
Concepts and technologies are disclosed herein for acoustic representations of environments. A processor can execute an acoustic representation service. The processor can receive a request to provide acoustic representation data to a device. The processor can obtain input data from the device. The input data can include captured data. The processor can analyze the input data to recognize an object represented in or by the input data and a path associated with the object. The processor can generate acoustic representation data representing the object and the path, and provide the acoustic representation data to the device. |
| US10163367B2 |
Refreshable tactile display
A system for providing a tactile display is disclosed. The system utilizes magnetic forces and actuators in order to move a series of tactile elements. The system can be arranged such that the display may include an entire array of thousands of elements. |
| US10163364B2 |
Method of providing feedback for a piece of cue sport equipment during game play
A method of providing feedback for a piece of cue-sport equipment, a cue ball or cue stick, during a game play first collect spatial positioning and orientation data from a plurality of measurement sensors that is integrated into the cue-sport equipment. Then, the collected data is analyzed to generate a virtual movement model of the cue-sport equipment as the virtual movement model includes a calculated impact force diagram, an animated travel path, and a calculated absolute orientation for the cue-sport equipment. Then, the player can view the virtual movement model through an external computing device to improve their cue-sport skills effectively and efficiently. |
| US10163360B2 |
Navigation controller for virtual-reality systems
A virtual-reality navigation controller includes a base and a seating portion. The seating portion includes a seat for supporting a weight of a user seated thereon, and a back-rest coupled to the seat to move integrally with the seat and to support the user's back. The virtual-reality navigation controller further includes a displacement connector between the seating portion and the base to reciprocate the seating portion upwards and downwards, and a motion-detection controller to measure upwards and downwards displacement of the seating portion. The displacement connector is configured to move the seating portion upwards along with the user to support the user when the user ascends from the seat during virtual-reality activities. The displacement connector is further configured to move the seating portion downwards at a slower maximum speed than the upwards movement, when the user's body rests back on the seat. |
| US10163358B2 |
Method and system for student project management
Described herein is a method and a system of student activity management comprising receiving a plurality of information related to one or more activities of a student in an educational system; storing at least a portion of the information in one or more files, wherein the information is stored based on the activity the information is related to and the content of the information; applying at least a portion of the received information to a calendar function, wherein the at least a portion of received information applied to the calendar function is used to create a timeline for completing at least one activity of the student; applying one or more tools to at least a portion of the information; tracking progress made toward completion of the at least one activity; and providing alerts to at least the student regarding the progress made toward completion of the at least one activity. |
| US10163357B2 |
Navigation assistance data and route planning for drones
Methods, systems, computer-readable media, and apparatuses for determining a flight route for a flight of an unmanned aerial vehicle (UAV) are presented. The flight-specific route for the UAV is determined dynamically during the flight or in advance before the flight, using navigation assistance data that includes flight-specific navigation assistance data for a plurality of geographic zones determined based on flight-specific information. The flight-specific navigation assistance data includes flight-specific ranking data for the plurality of geographic zones that can be used by the UAV or a server to determine the flight route. |
| US10163354B2 |
Query system for crowdedness of bus and method thereof
The present disclosure illustrates a query system for crowdedness of a bus and a method thereof. In the query system, a passenger may select a bus route displayed on the mobile device, to download and browse a bus dynamic message corresponding to the selected bus route, and then input and transmit a passenger pick-up request message to a server-end device, and the server-end device stores the passenger pick-up request message and calculates the numbers of passengers on the bus reaching all bus stations according to the passenger pick-up request messages of all mobile devices, and the numbers of passengers and the bus dynamic message are displayed on the passenger's mobile device at the same time. Therefore, the technical means of the present disclosure may achieve a technical effect of improving efficiency in selecting the bus to take. |
| US10163349B1 |
Impact induced lighting to mitigate post-accident risk
The present disclosure relates generally to safety lighting devices for automotive vehicles. A safety lighting system coupled to an automotive vehicle includes a power source that is independent of an electrical system of the vehicle. The system also includes a lighting feature electrically coupled to the power source, wherein the lighting feature is configured to activate in response to an impact event. |
| US10163348B2 |
Drive assist device
A drive assist devices include a display that displays an image around a vehicle imaged by an imaging device installed on the vehicle, a setting unit that sets a target designated by a user on the image as a recognition target, a detection unit that detects a state change of the recognition target on the image in a case where the recognition target is set, and a notification control unit that controls a notification device to notify the user of the detection result in a case where the state change of the set recognition target is detected. |
| US10163345B2 |
Method and device for providing an event message indicative of an imminent event for a vehicle
A method for providing an event message indicative of an imminent event for a vehicle. In a first step, a first event message and a second event message are initially received. The first event message represents a signal output by a first mobile terminal device in response to the imminent event; and the second event message represents a signal output by a second mobile terminal device in response to the imminent event. In a further step, an aggregated event message is generated on the basis of the first event message and the second event message. A step follows for ascertaining a plausibility value to check the plausibility of the aggregated event message. Finally, the aggregated event message and the plausibility value are output. The aggregated event message and the plausibility value represent a signal that is receivable from at least one mobile playback device. |
| US10163344B2 |
Driving support device and driving support method
A driving support device includes: an intersection information acquiring unit 3 to obtain signal light information about traffic signals installed at one or more intersections ahead of a road along which the vehicle is traveling and to obtain distances to the intersections; a vehicle state detector 4 to detect a position and speed of travel of the vehicle; a signal passableness deciding unit 5 to decide a passable or impassable state of the traffic signals by the vehicle from the signal light information, the distances to the intersections, and the position and speed of travel of the vehicle; and a display controller 7 to display the passable or impassable state of the traffic signals decided by the signal passableness deciding unit 5 by changes of color on the map. |
| US10163342B2 |
Method and apparatus for traffic safety
A method and apparatus for traffic safety are provided using vehicle driving-related information obtained on the basis of a transmission/reception beam pair of a road side unit (RSU) and a vehicle on-board unit (OBU), thereby reducing a probability that vehicle collisions occur where visual fields may be obscured. The method includes setting a path from a current location of the electronic device to a destination, and transmitting a message indicating an emergency situation to other devices located on the path while moving to the destination. The method further includes determining a transmission/reception beam pair of the electronic device and a road apparatus, using a reference signal received from the road apparatus, transmitting a signal including information for the transmission/reception beam pair to the road apparatus, and receiving, from the road apparatus, a message warning that the electronic device and another neighboring electronic device are approaching each other. |