| Document | Document Title |
|---|---|
| US10164841B2 |
Cloud assist for storage systems
Systems, methods, and computer readable storage mediums for using a cloud assist service to generate a read-only GUI to view the status of a storage system. An authorized user can login remotely to the cloud assist service to view the read-only GUI of the storage system. The read-only GUI will present a view of the status of the storage system that is similar to a local GUI available to users connecting directly to the storage system. Responses used to generate the local GUI are recorded and simulated by the cloud assist service to create a familiar read-only GUI. |
| US10164840B2 |
Device and method for configuring multiple interferers
An approach is provided for configuring multiple interferers. An interference effect minimum protective distance is calculated in response to detection of an input of an interferer parameter. Physical (PHY) layer modeling is performed to individually apply a pathloss caused by a separation distance between an interferer node and a victim and apply a pathloss of each node to an attenuator and a transmitter amplifier in an HW manner. MAC layer modeling is performed to determine a transmission node and a transmission time using Markov chain or determine a transmission node and a transmission time using a result log file of an external MAC simulator and a transmission/reception time is reflected in an HW manner by turning ON/OFF a switch. Multiple correlated interferer signals are generated for analyzing an effect of frequency interference in view of both of PHY and MAC layers. |
| US10164838B2 |
Seamless segment routing
A method, network device, and computer readable medium are disclosed. In one embodiment of the method, a data packet is received at a node within a first segment routing enabled access network. The first access network is connected, via a first area edge node, to a first area of a subdivided segment routing enabled network, and a specified destination for the data packet is reachable via a second segment routing enabled access network connected to the subdivided network. The method embodiment further includes receiving from a centralized controller a remote segment identifier stack, where the remote segment identifier stack encodes a path extending from the first area edge node to the second access network. The embodiment of the method continues with encapsulating the data packet with a full segment identifier stack comprising the remote segment identifier stack, and forwarding the encapsulated data packet toward the first area edge node. |
| US10164820B2 |
Method and device for detecting radio communication anomalies
A radio communication anomaly detecting method includes: gathering and storing different kinds of parameters indicating a radio quality with a sensor node in a storage unit; classifying parameter sets, each containing specific kinds of parameters gathered during a prescribed time period among the stored parameters, into clusters; estimating that a rapid radio quality degradation has occurred during the prescribed time period when there is a cluster of which all average values of specified kinds of parameters among the different kinds of parameters degrade more than those of another cluster; and performing a trend analysis for a time period during which it is not estimated that the rapid radio quality degradation has occurred to determine whether each of the different kinds of parameters gathered during the time period exhibits a trend of degradation, and estimating that a slow radio quality degradation has occurred based on a result of the trend analysis. |
| US10164814B1 |
Offset decoding of resource elements within resource blocks to compensate for propagation delay
Disclosed is a method and system for offset decoding of resource elements in a resource block to compensate for propagation delay in uplink coordinated multipoint service. A determination may be made that the initial data symbol of a time-ordered sequence of N data symbols transmitted by a user equipment device (UE) to a base station (BS) will be received at an arrival time beyond an initial one of N equally-spaced tolerance windows for simultaneous decoding of data symbols received from UEs. If it is determined that the arrival time will be within a subsequent one of the N equally-spaced tolerance windows, then the BS may receive and decode those of the N data symbols with respective arrival times in one of the subsequent tolerance windows. Otherwise, the BS may refrain from decoding any of the N data symbols. The decode data symbols may be merged with those from another BS. |
| US10164810B2 |
Pilot design for wireless system
The description herein relates to pilot designs for an Orthogonal Frequency Division Multiplexing (OFDM) based communication system. In at least one embodiment, the communication system is one operating according to the IEEE 802.16m, or WiMax, standard. In general, an OFDM transmitter operates to insert pilot symbols into a resource of a transmit frame according to a predetermined staggered pilot symbol pattern defining pilot symbol locations within the resource of the transmit frame. The predetermined pilot symbol pattern is defined such that pilot symbols are located at or near time boundaries of the resource, at or near frequency boundaries of the resource, or both. By doing so, when generating a channel estimate for the communication channel between the OFDM transmitter and an OFDM receiver based on the pilot symbols, extrapolations needed to estimate the channel near the boundaries of the resource are optimized, thereby improving overall channel estimation accuracy. |
| US10164807B2 |
Receiver circuits
A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analog-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analog-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal. |
| US10164806B2 |
Clock data recovery circuit using pseudo random binary sequence pattern and operating method for same
A clock data recovery circuit includes; a clock recovery circuit that receives a pseudo random binary sequence (PRBS) pattern and generates a recovery clock by counting edges of the PRBS pattern, and a data recovery circuit that generates recovery data from at least one of the PRBS pattern and externally provided serial data. |
| US10164805B1 |
Characterization of decision feedback equalizer taps
Various embodiments, disclosed herein, can include apparatus and methods to characterize taps of a decision feedback equalizer of a data receiver. In characterizing the taps of the decision feedback equalizer of the data receiver, a signal can be transmitted to the data receiver and the received data can be iteratively sampled at an output of the decision feedback equalizer. The sampling can include stepping a sample time relative to arrival of the received data and stepping a reference voltage level to which the received data is compared. Values of the sampled data can be compared with known correct values and such measurements can be used to characterize the taps. Additional apparatus, systems, and methods are disclosed. |
| US10164803B2 |
Method and apparatus for controlling interference in QAM-FBMC system
Disclosed are a method and an apparatus for controlling a quadrature amplitude modulation-filter bank multi-carrier (QAM-FBMC) system. A method of controlling interference is performed by a reception apparatus of the QAM-FBMC system, wherein the reception apparatus is paired with a transmission apparatus. The method includes receiving a pre-coded data symbol; and removing residual interference caused due to a non-orthogonal filter from the pre-coded data symbol by using a decision feedback equalizer. |
| US10164797B2 |
Data transmission method and station
The present invention provides a data transmission method. In the method of the present invention, a station receives an indication frame sent by an access point, where the indication frame is used for allocating a designated random contention channel; a channel state of the designated random contention channel is sensed according to the indication frame; and the station sends data on the designated random contention channel after it is detected that the designated random contention channel is in an idle state. Because in the method of the present invention, a designated random contention channel is allocated to a station, the station can send data on the designated random contention channel, contention among stations is reduced and a time for a station to be connected to a random contention channel is reduced. |
| US10164795B1 |
Forming a multi-device layer 2 switched fabric using internet protocol (IP)-router / switched networks
In some embodiments, a method includes defining, by a processor included in a first node, a virtual-extensible-local-area-network (VXLAN) tunnel between the first node included in a first layer-two network, and a second node included in a second layer-two network, the VXLAN tunnel traversing at least one node of a layer-three network. The method includes receiving, at the first node, a layer-two data unit that is sent from a third node included in the first layer-two network, to a fourth node included in the second layer-two network. The method includes encapsulating, at the first node, the layer-two data unit to define an encapsulated data unit that includes a VXLAN header. The method includes sending the encapsulated packet from the first node towards the fourth node via the VXLAN tunnel. |
| US10164794B2 |
Bridging of non-capable subnetworks in bit indexed explicit replication
Methods and network devices are disclosed for traversal, within a network configured for bit indexed forwarding, of a subnetwork having nodes not configured for bit indexed forwarding. In one embodiment, a method includes receiving, from a first network node not configured for bit indexed forwarding, a data message comprising a local label and a message bit array. Bit values in the message bit array identify intended destination nodes for the message. The embodiment further includes modifying the message bit array to exclude as intended destination nodes for the message any nodes not represented by one or more relative bit positions associated with the local label and stored in an ingress filter data structure. In addition, the embodiment includes forwarding a copy of the data message to a second network node, which is configured for bit indexed forwarding, identified in an accessed entry of a bit indexed forwarding table. |
| US10164792B2 |
User station for a bus system and method for reducing line-conducted emissions in a bus system
A user station for a bus system and a method for reducing line-conducted emissions in a bus system, in which the user station includes a transceiver for transmitting or receiving a message from at least one additional user station of the bus system via the bus system. In the bus system, exclusive, collision-free access to a bus of the bus system by a user station is at least temporarily ensured. The transceiver includes an emission control device for controlling the properties of the transceiver to reduce line-conducted emissions in the bus system. The transceiver is also configured for switching the emission control device on or off as a function of the arbitration phase and the data area of the message. |
| US10164788B2 |
Remote control method and system using control user interface
The present disclosure relates to a method and a system for remote control, and a remote control method using a control user interface of a remote user interface (UI) client according to an exemplary embodiment of the present invention includes receiving, by the remote UI client, a message requesting a service from a remote device; transmitting a message requesting a control UI related to the requested service to a remote UI server when the remote UI client receives the message requesting the service from the remote device; receiving, by the remote UI client, a control UI corresponding to the message requesting the control UI from the remote UI server; and transmitting, by the remote UI client, the received control UI to the remote device. According to an exemplary embodiment of the present invention, a user may easily control a corresponding remote user interface through a control user interface specified for a screen on which the remote user interface is being reproduced. |
| US10164787B1 |
Print to eBook reader
Techniques for transferring printable content from a remote device to an eBook reader include exposing a network printer interface that represents the eBook reader as a physical network printer. The remote device can be configured with a printer driver corresponding to the network printer interface, and a user may print documents from the remote device in order to transfer them to the eBook reader. |
| US10164785B2 |
Method for implementing a real-time industrial internet field broadband bus
The invention discloses a method for implementing a real-time industrial internet field broadband bus, the method including: determining, by a bus controller, the number of bus terminals connected therewith; and allocating, by the bus controller, time slices for the bus terminals according to the number of bus terminals, and transmitting, by the bus controller, the time slices to the bus terminals so that the bus terminals operate in the allocated time slices. Moreover data are transmitted in the bus system by removing Ethernet/IP message header information to thereby reduce the length of the message, and shorten a transmission delay and a bus scan periodicity so as to improve the real-time characteristic of the bus system. |
| US10164782B2 |
Method and system for constructing a loop free multicast tree in a data-center fabric
Systems, methods and transitory computer-readable storage media for constructing a loop free multicast tree. The methods include observing a network topology transition affecting a first path from the particular node to a root node, calculating a second path from the particular node to the root node and sending a message to an upstream node requesting that the upstream node be a root port in the calculated second path. If the upstream node agrees to be the root port in the calculated second path, the method further includes creating a new FTAG tree topology view that includes the upstream node as the root port in the second path. |
| US10164778B2 |
Method and system for distributing attestation key and certificate in trusted computing
One embodiment described herein provides a system and method for secure attestation. During operation, a Trusted Platform Module (TPM) of a trusted platform receives a request for an attestation key from an application module configured to run an application on the trusted platform. The request comprises a first nonce generated by the application module. The TPM computes an attestation public/private key pair based on the first nonce and a second nonce, which is generated by the TPM, computes TPM identity information based on a unique identifier of the TPM and attestation key, and transmits a public key of the attestation public/private key pair and the TPM identity information to the application module, thereby enabling the application module to verify the public key of the attestation public/private key pair based on the TPM identity information. |
| US10164776B1 |
System and method for private and point-to-point communication between computing devices
A hardware and software bundle that can enable computers and mobile phones to communicate small data packages without relying on the internet or the central cellular network infrastructure. The bundle enables users to send text messages and other data. For example, GPS coordinates, multimedia from the situation, accelerometer and other sensor data can all be sent over a decentralized network, enabling enhanced communication and situation response when the central grid is unavailable. |
| US10164772B2 |
Permutation composition based hash function
The disclosed hash and message padding functions are based on the permutation composition problem. To compute a hash of a message using permutation composition based hashing, the message is split into equal size blocks. For each block, a permutation composition value is computed. The block permutation composition values are then combined through composition to generate an overall permutation composition value. The hash of the message is then based on the overall permutation composition value. To pad a message using permutation composition based padding, the message is split into equal size blocks. For each block, a permutation composition value is computed and the permutation composition value is added to the block. The padded blocks are then recombined to generate the padded message. |
| US10164771B2 |
Encryption method and encryption device
The present disclosure discloses an encryption method and an encryption apparatus. The encryption method comprises: generating an AES initial key by using an SAES encryption algorithm, and expanding the AES initial key to obtain an AES encryption key; and encrypting information to be encrypted by using the AES encryption key according to an AES encryption algorithm to generate encrypted data. As such, the AES encryption key is encrypted by introducing the SAES algorithm, which increases the difficulty in cracking the AES encryption key. An attacker may crack the AES by firstly cracking the AES encryption key, which increases the overall difficulty in cracking the AES encrypted data. Further, the SAES encryption algorithm and the AES encryption algorithm are implemented by means of an ASIC integrated in an encryption chip. |
| US10164768B1 |
Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors
In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate. |
| US10164765B2 |
Receivers and method for detecting a non-persistent communication superimposed on an overt communication channel
Aspects are generally directed to optical receivers and methods for detecting a non-persistent communication superimposed on an overt communication channel. In one example, an optical receiver includes an optical resonator to receive an optical signal having one or more symbols encoded thereon at a modulated symbol repetition rate, the modulated symbol repetition rate being modulated relative to a nominal symbol repetition rate. The optical resonator is configured to emit an intensity-modulated output optical signal that has a variation in an intensity thereof corresponding to a symbol transition in the optical signal. The optical receiver further includes signal processing circuitry including a clock configured to generate a reference signal, a photodetector configured to generate a trigger signal, and a non-persistent communication decoder configured to determine a temporal misalignment between the symbol transition and the nominal symbol repetition rate based on the reference signal and the trigger signal. |
| US10164759B1 |
Distributed precision time architecture
Provided are systems and methods for implementing a reliable precision time architecture in a network device. In various implementations, a first port of the network device can be configured to synchronize to a first network time from the network. A second port can be configure to receive the first network time from the first port, and further provide the first network time to the network. A third port of the network device can further be configured to synchronize to a second network time from the network. A fourth port can be configured to receive the second network time from the third port, and provide the second network time to the network. The network device can further be configured to use the first network time as a current time. |
| US10164757B2 |
Communication apparatus
Communication apparatus comprises a first transceiver unit (205A) and a signal processing device (106) configured to receive a signal from the first transceiver unit and to produce a signal for transmission by the first transceiver unit. A cable (201A) connects the first transceiver unit to the signal processing device. The first transceiver unit comprises a housing; a first pair of transducers (204T, 204R) located at, or adjacent, a first end of the housing, and a second set of transducers (206T, 206R) located at, or adjacent, an opposite end of the housing. |
| US10164752B2 |
Dynamic precoding of shared reference signals
A receiver apparatus receives a terminal-specific demodulation reference signal having a rank k and estimates an effective multi-layer channel response, using the received terminal-specific demodulation reference signal. The receiver demodulates first data symbols from first time-frequency resource elements, using the estimate of the effective multi-layer channel response and using a first symbols-to-virtual-antenna mapping matrix M to obtain nc modulation symbols from each of the first time-frequency resource elements, wherein nc>1 and wherein the first symbol-to-transmit-layer mapping matrix M has dimensions k by nc. The first data symbols are decoded to obtain downlink control information assigning second time-frequency resource elements to the receiver. The receiver demodulates second data symbols from the second time-frequency resource elements, using the estimate of the effective multi-layer channel response, to obtain nd modulation symbols from each of the second time-frequency resource elements, wherein 1 |
| US10164750B2 |
Pilot patterns for OFDM systems with multiple antennas
The present invention relates to orthogonal frequency-division multiplexing (OFDM) communication systems with four transmit antennas and one or more receive antennas, and in particular to methods for inserting scattered pilots (SPs) into the transmit signals of such OFDM systems, for estimating channel properties on the basis of the scattered pilots, a multi-antenna OFDM transmitter, and an OFDM receiver. In this context, it is the particular approach of the present invention to keep the same SP pattern like in the single-transmitter case, to partition the pilots into as many subsets as there are transmitters (transmit antennas), and to interleave these subsets both in time and in frequency. In this manner, the granularity of pilots of the same subset is reduced. This offers increased flexibility in designing the scattered pilot patterns and greater accuracy of the estimated channel properties. |
| US10164749B2 |
Channel-state information process processing method, network device, and user equipment
Embodiments of the present invention provide a channel-state information process processing method, a network device, and a user equipment, where the channel-state information process processing method includes: after receiving a first channel-state information CSI request sent by a first network device, if CSI corresponding to multiple aperiodic CSI processes has not been reported by a user equipment, dropping CSI corresponding to a part of aperiodic CSI processes among the multiple aperiodic CSI processes, where each CSI process is associated with a channel measurement resource and an interference measurement resource. A problem existing after a CoMP technology is introduced can be solved that the UE cannot implement processing of multiple CSI processes. |
| US10164747B2 |
Method and apparatus for operating MIMO measurement reference signals and feedback
Methods and apparatuses for CSI reporting mechanisms are provided. A user equipment (UE) includes a transceiver configured to receive channel state information (CSI) process configuration information with a plurality of non-zero-power (NZP) CSI reference signal (CSI-RS) resource configurations. The UE includes a processor operably connected to the transceiver, the processor configured to calculate, in response to receipt of the configuration information, a CSI report associated with a CSI-RS type or a multiple-input multiple-output (MIMO) type. The transceiver is further configured to transmit the CSI report on an uplink channel. At least one of the NZP CSI-RS resource configurations corresponds to a beamformed type. |
| US10164744B2 |
Flexible OFDMA packet structure for wireless communications
A communication device includes a processor configured to generate OFDMA packets using various OFDMA packet structures and to transmit such OFDMA packets, via a communication interface, to at least one other communication device. The processor is also configured to receive, interpret, and process such OFDMA packets. One example of an OFDMA packet includes common SIG for two or more other wireless communication devices modulated across all sub-carriers of the OFDMA packet. The common SIG is followed by first SIG and first data for a first other wireless communication device modulated across first subset of the sub-carriers of the OFDMA packet and is also followed by second SIG and second data for a second other wireless communication device modulated across second subset of the sub-carriers of the OFDMA packet. Another example of an OFDMA packet includes the common SIG followed directly by first data and second data modulated as described above. |
| US10164741B2 |
Packet data transmission device and packet data transmission method
[Problem]To prevent either of two packet data having the same content from being affected by noise[Solution]A packet data transmission device (not shown) transmits first packet data 1A, . . . and second packet data 1B, . . . having the same content intermittently with an idle time I therebetween. When the length of the first and second packet data 1A, . . . , 1B, . . . is denoted by LP, the length of the idle time I is denoted by LI, the duration of low-frequency noise N is denoted by LN, the time with no low-frequency noise from the occurrence of one low-frequency noise N to the occurrence of the next low-frequency noise N is denoted by LC, the following expressions (1), (2) are satisfied. Consequently, either the first packet data or the second packet data is transmitted to a receiver without being affected by noise. LI>LN (1) 2×LP+LI |
| US10164739B2 |
Joint space-time and FEC coding in multi-mode fiber optical transmission systems
Embodiments of the invention provide an optical transmitter configured to transmit a data sequence over at least two spatial propagation modes through an optical transmission channel in a multi-mode optical fiber transmission system, the transmission system being associated with a predefined value of a mode-dependent loss, wherein the optical transmitter comprises: a forward error correcting code encoder (22) configured to encode said data sequence into a codeword vector by applying at least one error correcting code; a modulator (23) configured to determine a set of modulated symbols by applying a modulation scheme to said codeword vector; and a Space-Time encoder (24) configured to determine a codeword matrix by applying a Space-Time code to said set of modulated symbols. |
| US10164738B2 |
Interlacing method for high throughput forward error correction
Encoders, decoders and methods of encoding and decoding data can comprise receiving source symbols in a first sequence, storing the source symbols to a first memory in a second sequence, wherein the first sequence is a first interlacing relative to the second sequence, determining if the memory contains all source symbols of a codeword, wherein the source symbols of a codeword are the symbols used to generate repair symbols for that codeword, generating repair symbols for the codeword, storing the repair symbols to a second memory in a third sequence, interlacing the repair symbols and the source symbols into an output stream as a stream of encoded symbols, wherein the repair symbols appear in the output stream in a fourth sequence, wherein the fourth sequence is a second interlacing relative to the third sequence, and outputting the stream of encoded symbols. |
| US10164735B2 |
Adaptive modulation and coding method, apparatus, and system
Embodiments relate to the communications field, and provide an adaptive modulation and coding method, apparatus, and system. The method includes: obtaining to-be-processed data; obtaining channel information corresponding to the to-be-processed data, and determining a modulation mode according to the channel information. The method also includes determining first data and second data from the to-be-processed data according to the modulation mode; performing soft decision forward error correction FEC coding on the first data to obtain a first bit stream. The method also includes obtaining a second bit stream according to the second data, and modulating the first bit stream and the second bit stream according to a constellation mapping rule; and sending modulated data. |
| US10164734B2 |
Integrated physical coding sublayer and forward error correction in networking applications
Method and apparatus for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. The method includes performing a first forward error-correcting (FEC) sub-function on the data in the PCS transmit structure. The method further includes transmitting the data on one or more physical medium attachment (PMA) lanes to a PCS receive structure. The method also includes performing a second FEC sub-function on the data in the PCS receive structure. |
| US10164727B1 |
Shared schedule time slot allocation
A method for allocating time slots of a shared schedule for a plurality of communication lines having a crosstalk relationship is described. A first number of allocated time slots is allocated, according to respective priorities, corresponding to a first time interval for first data to be transmitted. The first data is transmitted. A second number of allocated time slots is allocated, corresponding to a second time interval for second data to be transmitted. The second number is larger than the first number if an allocation increase threshold has been met, based on utilization of a first time slot having a lowest priority of the first number of allocated time slots. The second number is smaller than the first number if an allocation decrease threshold has been met, based on utilization of a second time slot having a higher priority than the first time slot. |
| US10164726B2 |
Method for packet scheduling using multiple packet schedulers
A method comprising: receiving, by a first network packet scheduler, from each other network packet scheduler of a plurality of network packet schedulers, a virtual packet for each traffic class of a plurality of traffic classes defining relative transmission priority of network packets; receiving, by the first network packet scheduler, a network packet of a first traffic class of the plurality of traffic classes; transmitting, by the first network packet scheduler, each virtual packet into a virtual connection of a plurality of virtual connections created for each traffic class; scheduling, by the first network packet scheduler, a network packet or a virtual packet as a next packet in a buffer for transmission; determining, by the first network packet scheduler, that the next packet in the buffer is a virtual packet; and discarding, by the first network packet scheduler, the virtual packet, responsive to the determination that the next packet in the buffer is a virtual packet. |
| US10164704B2 |
Satellite transmitter system
A satellite transmitter module for accepting input signals and emitting output signals for uplink transmission. The module includes a transmitter unit that includes i) transmitter circuitry, ii) at least one input port, iii) and at least one output port. At least one heat sink coupled to the transmitter unit includes a plurality of heat sink fins, wherein at least two of the plurality of heat sink fins are of different heights. A fan is capable of generating air flow parallel with the plurality of heat sink fins. The module further includes an outer enclosure that i) encloses the transmitter unit and the plurality of heat sink fins and ii) is impermeable to the air flow generated by the fan. The outer enclosure includes an enclosure cross section shape that is substantially similar to the at least one heat sink cross section shape defined by the height of each of the plurality of the heat sink fins. |
| US10164703B2 |
Architecture for observing a plurality of objects arranged in geographically separate locations and method of collecting the associated observation data
Disclosed is an architecture for observing a plurality of objects arranged in geographically separate locations, including: a processing center connected to a global computer network, and at least one airliner. The at least one airlines includes: a cabin system including a local network, a first external communication module, a second external communication module, and an intermediate communication module connected to the first external communication module by the local network and to the second external communication module by the local network, the intermediate communication module communicating digital data including observation data between the second external communication module and the first external communication module via the local network. |
| US10164699B2 |
CSI reporting in beamforming systems via time- and frequency-distributed CSI estimation
An apparatus of a user equipment (UE) may include memory and processing circuitry coupled to the memory. The processing circuitry may be configured to estimate a communication channel for a multi-carrier signal based on a received reference signal, the multi-carrier signal aggregating a plurality of component carriers. During a transmission time interval of the multi-carrier signal, the UE can perform a global search over a beam search space to obtain a beam index recommendation for a component carrier of the plurality of component carriers. The beam index recommendation corresponds to a maximized channel quality metric of the estimated communication channel and is indicative of a beam grid within the beam search space. The UE can perform a localized search of a subset of the beam search space to obtain a second beam index recommendation for a second component carrier of the plurality of component carriers. |
| US10164685B2 |
Spatially aware wireless network
Technology for a spatially aware wireless network is disclosed. One embodiment comprises a plurality of near field magnetic induction nodes. One or more nodes is configured to communicate a polarized spatial position signal using near field magnetic induction (NFMI) to determine one or more of a position and an orientation of one or more nodes in the spatially aware wireless network. A detection module is operable to configure the spatially aware wireless network based one or more of a position and an orientation of one or more nodes in the plurality of nodes. |
| US10164683B2 |
Method for receiving interference cancellation
One disclosure of the present specification provides a method for receiving interference cancellation. The method for receiving interference cancellation can comprise: a step for cancelling, in signals received from a serving cell, cell-specific reference signals (CRS) from the serving cell, the CRS from a first primary interference cell, and the CRS from a second primary interference cell; a step for comparing the signal size of the serving cell, the signal size of the first primary interference cell, and the signal size of the second primary interference cell; a step for determining whether the CRS of the serving cell conflicts with the CRS of the first primary interference cell or the CRS of the second primary interference cell; and a step for canceling, when it is determined that the CRS' conflict with one other, data signals from the first primary interference cell and data signals from the second primary interference cell in the signals where the CRS are cancelled in the order determined according to the size comparison of signals. |
| US10164679B1 |
Electronic devices having multiple slot antennas
An electronic device may have conductive housing structures and first, second, third, and fourth slot antennas having respective first, second, third, and fourth slot elements in the conductive housing structures. The third slot element may be interposed between the first and second slot elements and the second slot element may be interposed between the third and fourth slot elements. Switching circuitry may be coupled between a transceiver and the slot elements. Control circuitry may control the switching circuitry to activate a selected pair of the slot antennas based on an orientation of the device or other data. The active pair of antennas may convey radio-frequency signals at the same frequencies using a multiple-input and multiple-output (MIMO) communications scheme. In this way, the device may perform wireless communications at relatively high data throughputs regardless of how the device is being held by a user. |
| US10164678B2 |
Electronic product protective case
An electronic product protective case includes a rear housing and a holder which further includes a magnet assembly, and the magnet assembly includes a first magnet group and a second magnet group. The first magnet group includes a first magnet and a third magnet that have opposite polarities. The second magnet group includes a second magnet and a fourth magnet that have opposite polarities. The first magnet and the second magnet have opposite polarities. The third magnet and the fourth magnet have opposite polarities. The first magnet and the second magnet are mutually absorbed, and the third magnet and the fourth magnet are mutually absorbed. |
| US10164670B2 |
Time sequenced spectral stitching
Methods and systems are disclosed for using a single receiving device, such as a single VSA, to capture and digitize multiple time-domain acquisitions of a repeating signal at different center frequencies, to create a single time-domain waveform having a bandwidth greater than the real-time instantaneous bandwidth of the receiving device. Specifically, one or more signal processing paths may process the multiple digitized acquisitions of the repeating signal, either sequentially or in parallel, such that the processed acquisitions may be aggregated into a representation of one or more repetitions of the repeating signal. |
| US10164668B2 |
Mobile device, radio transceiver circuit, and impedance adjustment device
A mobile phone device, a radio frequency transceiver circuit and an impedance adjusting device. The present invention discloses a mobile phone device. The mobile phone device comprises a baseband processor, an antenna, a duplexer and a radio frequency transceiver circuit. The antenna is used to receive and send radio frequency signals. The duplexer is electrically connected to the antenna. The radio frequency transceiver circuit is connected to the baseband processor and the duplexer, respectively. The radio frequency transceiver circuit comprises a first power amplifier and an impedance adjusting device. The first power amplifier has a first output impedance. The impedance adjusting device is electrically connected between the first power amplifier and the duplexer, and comprises at least one switch, wherein the baseband processor is connected to and control the at least one switch of the impedance adjusting device to adjust an impedance value of the impedance adjusting device, such that a first load impedance of the first power amplifier and the first output impedance match one another. |
| US10164666B2 |
Radio frequency front end circuitry for MIMO and carrier aggregation
RF front end circuitry includes a first antenna node, a second antenna node, a diplexer, a first band filter, a second band filter, and switching circuitry. The diplexer may be used to separate signals for carrier aggregation, providing signals within a first RF frequency band to the first band filter and signals within a second RF frequency band to the second band filter. Further, by strategically arranging the switching circuitry, the diplexer may also be used as a multiple-input-multiple-output filter, such that additional filters are not required to support one or more MIMO modes of the RF front end circuitry. |
| US10164665B2 |
HF circuit and HF module
An HF circuit is specified, by means of which carrier aggregation is possible with a simple design. The circuit comprises a duplexer, a further filter, and two phase shifters, and can be used in an HF module of a mobile wireless device. |
| US10164660B1 |
Syndrome-based Reed-Solomon erasure decoding circuitry
An integrated circuit may include a Reed-Solomon decoder that receives a transmitted code word and an associated bit mask and that generates a corresponding corrected message. The bit mask indicates an erasure pattern for the received code word. The Reed-Solomon decoder may include a syndrome generator, a multiplication circuit, a read-only memory (ROM) circuit, an address compressor, and an aggregation circuit. The syndrome generator may receive the transmitted code word and generate a corresponding syndrome. The address compressor may receive the bit mask and generate a corresponding unique address for accessing the ROM circuit. The ROM circuit may then output an inverse parity matrix based on the unique address. The multiplication circuit may multiply the syndrome by the retrieved inverse parity matrix to output corrected symbols. The aggregation circuit may then path the received code word with the corrected symbols to obtain the corrected message. |
| US10164657B2 |
Systems and methods for differential message scaling in a decoding process
Systems and method relating generally to data processing, and more particularly to systems and methods for scaling messages in a data decoding circuit. In one embodiment, the systems and methods include applying a variable node algorithm, applying a check node algorithm, calculating a first number of errors, calculating a second number of errors, calculating a difference between the first and second number of errors, multiplying by scalar values to yield a scaled set of messages, and re-applying the variable node algorithm to the scaled set of messages. |
| US10164653B1 |
Analog to digital converter
An analog-to-digital converter (“ADC”) includes receiving an analog input voltage signal, converting the analog input voltage signal to a first digital value and an analog residue signal, converting the analog residue signal to a time value representing the analog residue signal, and converting the time value to a second digital value. The first digital value and the second digital value are combined into a digital output signal representing the analog input voltage signal. |
| US10164651B2 |
A/D converter, A/D conversion method, and semiconductor integrated circuit
An A/D converter includes a capacitor DAC, a resistor DAC, a first capacitive element, and a comparator. The capacitor DAC is configured to convert high-order M bits, where M and N are integers equal to or greater than 2, and the resistor DAC is configured to convert low-order N bits. The first capacitive element is provided between the capacitor DAC and the resistor DAC, and the comparator is configured to compare an input signal voltage with a voltage output from the capacitor DAC. The resistor DAC generates and outputs a voltage by adding or subtracting a wait based on redundant bits in addition to N-bit resolution. |
| US10164650B2 |
Delay-free poly-phase quantizer and quantization method for PWM mismatch shaping
A system and method for pulse-width modulation (PWM) mismatch shaping. The method includes receiving a multi-bit pulse-code modulated (PCM) signal and generating a voltage ramp signal. The method includes generating a first corrected signal based on a first feedback signal and the multi-bit PCM signal. The method includes generating a first single-bit PWM signal based on the first corrected signal and the voltage ramp signal. The method includes delaying the voltage-ramp signal and generating a second corrected signal based on a second feedback signal and the multi-bit PCM signal. The method includes generating a second single-bit PWM signal based on the second corrected signal and the delayed voltage ramp signal and generating a multi-bit pulse-density modulation (PDM) signal based on the first single-bit PWM signal and the second single-bit PWM signal. |
| US10164649B2 |
Hybrid phase lock loop
Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital controlled loop that receives a reference input signal and an output signal of the hybrid PLL, and generates a digital tuning word. The hybrid PLL further includes an analog controlled loop that receives the reference input signal and the output signal of the hybrid PLL, and generates an output voltage. The hybrid PLL also includes a hybrid oscillator. An oscillator controller of the digital controlled loop controls the hybrid oscillator using the digital tuning word and disables the analog controlled loop during a frequency tracking operation mode of the hybrid PLL. The oscillator controller enables the analog controlled loop to control the hybrid oscillator during the phase tracking operation mode of the hybrid PLL. |
| US10164645B2 |
Semiconductor device including DLL and semiconductor system
A semiconductor system includes: a controller suitable for outputting an external clock signal and a command/address signal; and a semiconductor device suitable for selecting one of pre-stored code values of a delay control signal to output an initial value control signal according to the command/address signal, and outputting an internal clock signal by delaying the external clock signal by a predetermined time based on the delay control signal having an initial value that is set in response to the initial value control signal. |
| US10164639B1 |
Virtual FPGA management and optimization system
A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition. |
| US10164634B2 |
Impedance calibration circuit and semiconductor apparatus including the same
An impedance calibration circuit includes a first detection unit configured to generate a first pull-up impedance detection signal according to a resistance value of an internal reference resistor, a second detection unit configured to generate a second pull-up impedance detection signal according to a resistance value of an external reference resistor coupled to an external reference resistor pad, a switching unit configured to select the first pull-up impedance detection signal or the second pull-up impedance detection signal according to the internal impedance calibration enable signal and output the selected pull-up impedance detection signal, and an impedance calibration signal generation unit configured to generate a plurality of impedance calibration signals according to an output of the switching unit. |
| US10164630B2 |
Activation device for a motor vehicle
An activation device for actuation of a vehicle function includes a cover element, a light distribution device arranged under the cover element, and a light source arranged under or in the light distribution device. The light source and the light distribution device are arranged for backlighting the cover element. The cover element includes an outward directed operation area at least partially formed of an electrically-conductive metallic material with the operation area being galvanically decoupled from the remaining components. A circuit board is arranged under the light distribution device with a capacitive sensor such that the capacitive sensor is coupled to the operation area. The control and evaluation circuit is coupled to the light source and the proximity sensor to control the light source depending on an approach. |
| US10164629B2 |
Method and apparatus for controlling current slew rate of a switching current through an external resistive load
In one aspect of the teachings herein, a switching circuit for switching a power transistor is configured to control the slew rate of the switched load current in a manner that yields substantial independence from the load voltage, based on the use of a Miller-effect compensation capacitor and controllable source resistances for driving the gate or base of the power transistor. In a non-limiting example, a control circuit, such as a microcontroller, uses a set of bidirectional input/output ports to drive the transistor base or gate through a selectable combination of parallel resistors, so that the effective source resistance for transistor turn-on and turn-off is selectable by configuring different combinations of input/output settings for the set of bidirectional input/output ports. Controlling the source resistance in this manner allows the control circuit to set or otherwise control the slew rate of the load current. |
| US10164628B2 |
Switch box
A switch box includes a relay transistor circuit connecting a pair of batteries in parallel, and an breaker circuit that breaks the relay transistor circuit when a sign of a potential difference between a potential of at least one of the pair of batteries connected to the relay transistor circuit and a predetermined reference potential is reversed with respect to the sign of the potential difference in which the batteries are correctly connected. |
| US10164627B1 |
Power-on control circuit
A power-on control circuit controlling a first output switch and a second output switch is provided. A detecting circuit detects a first voltage to generate a detection signal to a first node. A switching circuit receives the first voltage and a second voltage and transmits the first or second voltage to a second node according to the voltage level of the first node. A setting circuit generates a feedback signal to the first node according to a voltage level of the second node. When the first voltage reaches a first pre-determined value and the second voltage has not reached a second pre-determined value, the switching circuit transmits the second voltage to the second node. When the second voltage reaches the second pre-determined value, the switching circuit transmits the first voltage to the second node. |
| US10164626B2 |
Semiconductor device and method of outputting temperature alarm
A semiconductor device including a semiconductor switch circuit and a drive circuit. The semiconductor switch circuit includes a semiconductor switch and a temperature sensor for detecting a temperature in a periphery of the semiconductor switch. The drive circuit includes an overheating protection unit configured to, upon determining that the detected temperature of the semiconductor switch reaches an overheating protection temperature, perform overheating protection of the semiconductor switch and issue an overheating protection alarm signal. The drive circuit also includes an advance warning control unit configured to set a threshold temperature that is lower than the overheating protection temperature, and upon determining that the detected temperature reaches the threshold temperature, to output an advance warning signal before the overheating protection becomes operational. The overheating protection alarm signal and the advance warning signal are outputted from a same terminal of the drive circuit and are of different signal levels. |
| US10164621B2 |
Circuit and method of operating circuit
A circuit includes a first switch, a second switch, a first delay circuit and a second delay circuit. The first switch includes a first terminal, and the second switch includes a second terminal. The first circuit is coupled to the first terminal and the second terminal. The first circuit is configured to alternately turn ON the first switch and the second switch in accordance with an input signal and a delay setting. The delay setting corresponds to a delay between successive ON times of the first switch and the second switch. The second circuit is coupled to the first circuit. The second circuit is configured to monitor a first voltage on the first terminal and a second voltage on the second terminal, and to generate the delay setting based on at least the first voltage on the first terminal, or the second voltage on the second terminal. |
| US10164618B1 |
Jitter cancellation with automatic performance adjustment
Methods, systems, and devices for jitter cancellation with automatic performance adjustment are described. Within a clock distribution system in an electronic device (e.g., a memory device), a jitter cancellation system may be configured to introduce delay between an input clock signal and output clock signal that is directly proportional to the supply voltage for the clock distribution system. In response to supply noise, the delay introduced by the jitter cancellation system may vary directly with respect to the supply voltage fluctuations and thus may offset fluctuations in the delay introduced by other components of the clock distribution system, which may vary inversely with respect to the supply voltage fluctuations. A control component within the jitter cancellation system may execute an algorithm to adjust or regulate the delay introduced by the jitter cancellation system, including its responsiveness to fluctuations in the supply voltage. |
| US10164616B2 |
Level shift circuit
A level shift circuit is provided, which includes a boost circuit and a voltage converting circuit. The boost circuit is coupled to a first high voltage terminal to receive an input voltage signal. The boost circuit includes at least one low threshold voltage element and is configured to boost the input voltage signal. The voltage converting circuit is coupled to a second high-voltage terminal and includes a low-pass filter circuit, a high-pass filter circuit, an upper switch element and a lower switch element. The upper switch element and the lower switch element are electrically cascaded between the second high-voltage terminal and a low voltage terminal. The low-pass filter circuit and the high-pass filter are electrically connected between the control terminal of the upper switch element and the control terminal of the lower switch element. The upper switch element and the lower switch element are standard threshold voltage elements. |
| US10164614B2 |
Tank circuit and frequency hopping for isolators
Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair. |
| US10164613B2 |
Phase-inverted clock generation circuit and register
A phase-inverted clock generation circuit is provided, where sources of a first PMOS and a second PMOS are connected to a power source, drains of the first PMOS and the second PMOS are connected to a source of a third PMOS, and a drain of the third PMOS is connected to a drain of a third NMOS; and the drain of the third PMOS is connected to a drain of a second NMOS, a source of the second NMOS is connected to a drain of a first NMOS, and a source of the first NMOS and a source of the third NMOS. |
| US10164610B2 |
Signal output device
A signal output device is provided in a communication apparatus. The communication apparatus communicates with a different one of the communication apparatus using a single line. The signal output device includes a signal output unit. The signal output unit includes a first filter and a second filter. The first filter is provided by a Bessel filter. The second filter is provided by a Chebyshev filter or a Butterworth filter. The signal output unit outputs a signal which is obtained by passing a predetermined signal through the first filter and the second filter. The signal output from the signal output unit has a pass characteristic of the first filter and a pass characteristic of the second filter. A cutoff frequency of the first filter is set to be lower than a cutoff frequency of the second filter. |
| US10164607B1 |
Adjustable condenser
Certain aspects of the present disclosure are generally directed to an integrated circuit device. The integrated circuit device generally includes a capacitive element, a first switch having a first terminal coupled to a first terminal of a capacitive element, and a second switch coupled between the first terminal and a second terminal of the capacitive element in the integrated circuit device. |
| US10164604B2 |
Crystal device
A crystal device includes a package including a cavity formed therein, a thermistor disposed on a bottom surface of the cavity and integrated with the package, a crystal blank spaced apart from the thermistor in the cavity, and a lead coupled to the package so as to cover the cavity. |
| US10164601B2 |
BAW resonator having temperature compensation
A temperature-compensated BAW resonator is disclosed. In an embodiment, the BAW includes a substrate and a layer stack disposed thereon, the layer stack including a bottom electrode layer, a top electrode layer, a piezoelectric layer arranged between the bottom and top electrode layers and an acoustic mirror arranged between the bottom electrode layer and the substrate, wherein the acoustic mirror comprises at least two mirror layers, wherein the acoustic mirror comprises high impedance and low impedance layers arranged in an alternating sequence. The layer stack further includes a compensation layer including a material having a positive temperature coefficient of viscoelastic properties, wherein the compensation layer is arranged between the acoustic mirror and the bottom electrode layer, wherein the mirror layers together form a Bragg mirror. |
| US10164598B2 |
Power filter arrangement having a toroidal inductor package
A power filter arrangement includes a toroidal package having a toroid and a resistive element. The resistive element is disposed about an outer circumference of the toroid and is joined to the toroid. The resistive element is wound about the toroid. The resistive element is provided with a first resistive pattern having an even number of total turns. |
| US10164589B2 |
Power amplifier circuit
A power amplifier circuit includes: a first differential amplifier that amplifies a first signal split from the input signal and outputs a second signal; a second differential amplifier that amplifies a third signal split from the input signal and outputs a fourth signal; a first transformer including a first input-side winding to which the second signal is input and a first output-side winding; a second transformer including a second input-side winding to which the fourth signal is input and a second output-side winding; a first phase conversion element that is connected in parallel with the first output-side winding and outputs a fifth signal; and a second phase conversion element that is connected in parallel with the second output-side winding and outputs a sixth signal. The first and second output-side windings are connected in series and output a signal obtained by adding voltages of the fifth and sixth signals together. |
| US10164586B2 |
Impedance-matching circuit
An impedance-matching circuit includes a resonant circuit, first and second capacitors, and first through third inductive circuits. The resonant circuit includes a fourth inductive circuit connected in parallel with a capacitive circuit. The impedance-matching circuit receives a radio frequency power amplifier (RFPA) output signal, which includes first and second signals at first and second frequencies, respectively. A resonant frequency of the resonant circuit is between the first and second frequencies. The resonant circuit offers inductive and capacitive impedances to the first and second signals, respectively. The impedance-matching circuit generates a matched RFPA output signal including the first signal and the second signal, where the second signal is at a reduced voltage level. |
| US10164584B2 |
Method to mitigate undesired oscillator frequency modulation effects in-side a synthesizer due to interference signals and synthesizer circuit
A synthesizer circuit to generate a local oscillator carrier signal for a baseband signal includes a controlled oscillator comprising a phase lock loop and an oscillator configured to generate an oscillating signal. A pulling compensation circuit is configured to generate a correction signal for a present output of the phase locked loop using information on an error of the oscillating signal, information on a present sample of a baseband signal and a preceding correction signal for a preceding output of the phase locked loop. |
| US10164580B2 |
Multiplexed multi-stage low noise amplifier uses gallium arsenide and CMOS dies
A gate bias circuit for a plurality of GaAs amplifier stages is a transistor coupled to a temperature compensation current received from a CMOS control stage. A plurality of pHEMPT amplifier stages are coupled to the gate bias circuit and to a control voltage which switches the amplifier stage. A selectively controlled stage pass transistor enables a current mirror between the gate bias circuit and each stage amplifying transistor. The penultimate pHEMPT amplifier stage is coupled to a CMOS amplifier. A CMOS circuit provides both the temperature compensation current by a proportional to absolute temperature (PTAT) circuit and the control voltage enabling each pHEMPT transistor to receive its input signal in combination with the gate bias voltage. |
| US10164578B2 |
Frequency selective low noise amplifier circuit
Embodiments of the disclosure relate to a frequency selective low noise amplifier (LNA) circuit, which includes a transconductive LNA(s). In one aspect, filter circuitry is provided in a degeneration path of a transconductive LNA(s) to pass in-band frequencies and reject out-of-band frequencies by generating low impedance and high impedance at the in-band frequencies and the out-of-band frequencies, respectively. However, having the filter circuitry in the degeneration path may cause instability in the transconductive LNA. As such, a feedback path is coupled between an input node of the transconductive LNA(s) and the degeneration path to provide a feedback to improve stability of the transconductive LNA(s). In addition, the feedback can help improve impedance match in the frequency selective LNA circuit. As a result, the transconductive LNA(s) is able to achieve improved noise figure (NF) (e.g., below 1.5 dB), return loss, linearity, and stability, without compromising LNA gain. |
| US10164571B2 |
Crystal oscillator and method of manufacturing crystal oscillators
An crystal resonator includes a first oscillating circuit that oscillates a crystal resonator at a first frequency, a first impedance adjusting circuit that adjusts an impedance of a first oscillating system including the crystal resonator and the first oscillating circuit, a second oscillating circuit that oscillates the crystal resonator at a second frequency that is different from the first frequency, a second impedance adjusting circuit that adjusts an impedance of a second oscillating system including the crystal resonator and the second oscillating circuit, and a controlling circuit that controls the first impedance adjusting circuit and the second impedance adjusting circuit. |
| US10164570B2 |
Coupling structure for inductive device
A circuit includes a coupling structure and a first inductive device. The coupling structure includes two or more conductive loops and a set of conductive paths electrically connecting the two or more conductive loops. The first inductive device is magnetically coupled with a first conductive loop of the two or more conductive loops. |
| US10164562B2 |
Method and system for pulse width modulation
A method of controlling an alternating current (AC) motor includes following steps: (a) providing a voltage to the AC motor, wherein the voltage is a pulse-width modulation (PWM) signal, which is represented by a voltage reference vector; (b) determining that the voltage reference vector is in a distortion region; and (c) in response to determining that the voltage reference vector is in the distortion region, modifying, via a controller, the PWM signal by updating the voltage reference vector every half switching period to avoid the distortion region. |
| US10164560B2 |
Method for creating switch reluctance motor memory sensor model
A method for creating a switch reluctance motor memory sensor model. A switch reluctance motor memory sensor circuit model is formed by two current transmitters AD844, an operational amplifier AD826, a memristor, a capacitor, and three resistors. The method for creating a switch reluctance motor memory sensor model enables physical phenomena in a simulation system to be similar to an actual switch reluctance motor system, and is beneficial for direct mathematical simulation of a switch reluctance motor system. The method is simple, can improve static and dynamic performance of a system, and achieves real-time simulation and real-time control of the switch reluctance motor system. |
| US10164553B2 |
Method and device for damping voltage harmonics in a multilevel power converter
A method for reducing lower order harmonics of a power converter includes, for each phase leg of the converter: obtaining a voltage reference for the phase leg; for a present sample, obtaining a flux error of the output voltage of the leg; dividing the first sample flux error by a time period to obtain an average voltage error over said time period; subtracting an obtained processed average voltage error, based on the average voltage error, from the voltage reference to obtain a modified voltage reference for the phase leg; and providing the modified voltage reference to a modulation unit of the converter for controlling the phase leg. |
| US10164548B2 |
Delay control for a power rectifier
A power rectifier rectifies alternating electric current by using a controller in the power rectifier to control a first delay circuit in the power rectifier to turn on a high side switch in the power rectifier, wherein the high side switch provides a path for power from an input voltage line of the power rectifier to an output voltage line of the power rectifier. The controller controls a second delay circuit in the power rectifier to maintain the high side switch in an on state to change a switching state of the high side switch based on detection, by a current inversion detector, of a current inversion associated with the input and output voltage lines of the power rectifier. |
| US10164545B2 |
Power distribution system for low-frequency AC outlets
A power distribution system in which a power source is configured to supply an amount of high-frequency input power to a centralized frequency converter unit. The centralized frequency converter unit is configured to convert the high-frequency input power into low-frequency converted power. Passenger Electronic Device Controllers receive the converted power and distribute it to outlet units. Power management functions may be integrated with the distribution system. For instance, the centralized frequency converter unit can cause to be disabled unused outlet units when the power drawn by the used outlet units exceeds a predetermined threshold. |
| US10164544B2 |
Isolated partial power converter
An Input-Series-Output-Parallel (ISOP)-type partial power converter circuit comprises: an isolated, unregulated DC-to-DC converter configured to generate a first output voltage at a first output voltage node; and a regulated DC-to-DC converter coupled with the unregulated DC-to-DC converter and configured to generate a second output voltage at a second output voltage node, the regulated DC-to-DC converter comprising a resonant forward-flyback converter configuration; wherein the first output voltage node is coupled in parallel with the second output voltage node. |
| US10164543B2 |
System and method for controlling power converter with adaptive turn-on delay
A method for controlling a power converter includes generating a load detection signal in response to a conduction signal and a driver input signal, and generating a gate control signal in response to the load detection signal. The gate control signal is delayed by a delay amount in response to the load detection signal. An apparatus for controlling a power converter includes a gate signal control circuit generating a load detection signal in response to a conduction signal and a driver input signal, and a synchronous rectifier (SR) driver generating a gate control signal in response to the load detection signal. |
| US10164542B2 |
Electronic converter, and corresponding method for designing a magnetic component
A converter includes first and second input terminals and first and second output terminals. The converter also includes an output capacitor coupled between the first output terminal and the second output terminal, and a magnetic component having two input terminals and three output terminals. A first output terminal of the magnetic component is coupled through a first electronic switch to the second output terminal of the converter, a second output terminal of the magnetic component is coupled to the first output terminal of the converter, and a third output terminal of the magnetic component is coupled through a second electronic switch to the second output terminal of the electronic converter. In addition, the converter includes a switching stage configured to transfer current pulses from the first input terminal and the second input terminal of the converter to the two input terminals of the magnetic component. |
| US10164535B2 |
Cycle-by-cycle peak current limiting in current mode buck/boost converters
An SMPS current mode control loop with an adjusted cycle-by-cycle peak current limit for buck and boost (and bidirectional buck/boost) regulators. An SMPS regulator can include a PWM driver to drive switching control signals with a PWM duty cycle to an output terminal OUT, and a PWM controller to control the PWM duty cycle based on a current mode control loop that includes slope compensation to provide a signal VPK corresponding to a current sense signal from a current sense terminal CS, based on sensed peak current through the energy storage element, superimposed with an injected slope compensation current corresponding to a predefined slope compensation based on PWM duty cycle. Adjusted peak limit circuitry generates a signal VLMT corresponding to an adjusted peak current limit based on a pre-defined peak current limit threshold for the energy storage element, including generating a peak limit adjustment current corresponding to the injected slope compensation current, and combining the peak limit adjustment current with the pre-defined peak current limit threshold so that VLMT is substantially constant. |
| US10164533B2 |
Converter circuit for reducing a nominal capacitor voltage
The present invention relates to a converter circuit (1) for reducing a nominal capacitor voltage, the converter circuit (1) comprising: an input node (TI1), which is configured to receive an input voltage (VG); an output node (TO1; TO2), which is configured to supply an output voltage (VO) to a load (RL1; RL2); and a capacitor (C1; C2), which is coupled to the load so that the input voltage is divided between the capacitor (C1; C2) and the load (RL1; RL2) and which is configured to be charged up to a voltage corresponding to a differential voltage between the input voltage (VG) and the output voltage (VO). |
| US10164524B1 |
Methods and devices for charge pump level translation in high-speed memory drivers
Embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer readable media to enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. In one embodiment, a programmable level translator device is implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are modified with the use of a charge pump connected to the gate terminals of two of the PMOS transistors within the PMOS cross quad. Transmission gates are also employed to engage and disengage the charge pump based on a control switch. In various embodiments, the level translator device works with a number of memory devices operating over a wide range of power supply voltages. |
| US10164521B2 |
Control device for a switching regulator with interleaved converter stages, switching regulator and corresponding control method
A control device for a switching regulator having two or more converter stages operating with interleaved operation, each converter stage including an inductive element and a switch element, generates command signals having a switching period for controlling switching of the switch elements, and determining alternation of a storage phase of energy in the respective inductive element and a transfer phase of the stored energy onto an output element. The control device generates the command signals phase-offset by an appropriate fraction of the switching period to obtain interleaved operation. In particular, a synchronism stage generates a synchronism signal and a control stage generates the command signals for the converter stages timed by the same synchronism signal. |
| US10164520B2 |
Short circuit protection for switching power converters
A circuit (100) for protecting a Switching Power Converter (“SPC”) when a short-circuit load condition occurs. The SPC has an output current sensor utilizing at least one current transformer that has a primary winding connected in series with a rectifier and has a magnetic core that should avoid saturation. A pulse-width modulator includes a skip controller providing a series of control pulses to at least one switch. A control pulse is skipped when an abnormally low load resistance causes an input current ramp signal to exceed an input current setpoint signal proximate a start time of a next control pulse of the series and the output current is greater than a predetermined threshold. Operation of the SPC is stopped if more than a predetermined number of consecutive switching cycles are skipped to prevent operation of the SPC while the core of an output current transformer is saturated. |
| US10164513B1 |
Method of acquiring input and output voltage information
Disclosed is a method of acquiring input and output voltage information by employing a pulse width modulation (PWM) controller, which is in collocation with an input power processing unit, a primary inductor, a switch element, a current-sensing resistor, an output rectifier, and an output filter for converting an alternating current input power into an rectified input power and an output power, and the output power supplies an external load. A current-sensing signal is specifically disposed and applied to calculation of the input voltage and output voltage of the rectified input power when the switch element is turned on and off, respectively. Thus, no resistive voltage divider is needed, and power consumption at no load is greatly improved. |
| US10164512B2 |
Vibration motor
A vibration motor is provided in the present disclosure. The vibration motor includes a frame, vibrating assemblies and elastic connectors. The elastic connectors comprise a first elastic connector and a second elastic connector. The vibrating assemblies comprise a first vibration system and a second vibration system disposed at two sides of the frame respectively. A portion of the first elastic connector is connected with the first vibration system and another portion of the first elastic connector is connected with one side of the frame, and a portion of the second elastic connector is connected with the second vibration system and another portion of the second elastic connector is connected with the other side of the frame. The first vibration system comprises a coil, the second vibration system comprises a magnetic circuit system with a magnetic gap, at least part of the coil is disposed in the magnetic gap. |
| US10164508B2 |
Lamination pack and method of forming same
A lamination pack for a motor and method of forming the lamination pack is provided. The method includes inserting a plurality of conductor bars into a plurality of rotor slots defined by a lamination stack such that opposing bar ends of the conductor bars extend from opposing end faces of the lamination stack, skewing the lamination stack and the conductor bars to a skew angle relative to a rotation axis of the lamination stack, and subsequently bending the bar ends of the conductor bars in opposing radial directions to a locking angle greater than the skew angle, to lock each of the conductor bars in its respective rotor slot. The bent bar ends exert a compressive axial locking force on the lamination stack to prevent axial and radial movement of the laminations in the lamination stack and to prevent axial movement of the conductor bars relative to the lamination stack. |
| US10164507B2 |
Single-phase shaded pole induction motor, convertible to permanent magnet motor
The present invention refers to a shaded-pole single-phase motor convertible into a permanent magnet motor of the type that comprises a front casing, a stator element, a rotor element, a plurality of windings placed over the protruding poles of the stator element, and a rear casing, wherein the stator element presents a square-shape configuration with the four protruding poles rotated 45° relative to the horizontal and vertical symmetry axes in order to be aligned with the four corners of the stator element.The stator new configuration enables optimizing the use of lamination material during manufacturing and assembling the sheet packages of the stator element and rotor element; furthermore, the protruding poles, by being rotated 45° in the stator element, enable a reduction of electric losses in its windings and a decrease in the operative temperature of both the stator element and the rotor element, which enables an increase of the motor operation efficiency. Similarly, the reduction of the operative temperature of the stator element allows the use of plastic materials for its components. |
| US10164505B2 |
Forced air cooling of vacuum motor control
A motor assembly is provided for powering a blower operable to generate fluid flow. The motor assembly includes a motor, a controller assembly, and a flow director. The motor includes a rotor rotatable about an axis. The rotor includes a rotatable support body, a plurality of arcuately spaced apart magnets, and a magnet retention ring at least in part securing the magnets relative to the support body. The controller assembly includes a controller and a controller case at least substantially housing the controller. The controller extends lengthwise to present opposite first and second sides at least in part spaced from the controller case. The flow director and the controller case cooperatively direct fluid received from the blower along a flow path that at least in part extends along each of the first and second sides of the controller. |
| US10164502B1 |
Mobile diesel generator and power propulsion system
A mobile diesel generator and propulsion system preferably includes a diesel engine, a vehicle platform, a generator with voltage inverter, a battery charging system, at least one storage battery, an AC voltage to DC voltage converter, a motor controller and an AC motor. The generator with voltage inverter is driven by the diesel engine. The battery charging system receives AC voltage from the generator with voltage inverter and outputs a DC voltage to charge the at least one storage battery. The AC voltage to DC voltage converter receives output from the generator with voltage inverter and outputs a DC voltage to the motor controller. The motor controller receives DC voltage output from either the AC voltage to DC voltage converter or the at least one storage battery and outputs AC voltage to the AC voltage motor. The AC voltage motor drives a rear wheel of the vehicle platform. |
| US10164501B2 |
Reluctance motor with dual-pole rotor system
A method and apparatus for operating a reluctance motor. The apparatus comprises a stator and a rotor device. The stator comprises a first stator component and a second stator component. The first stator component has at least three poles. The second stator component has at least three corresponding poles. The at least three poles and the at least three corresponding poles form pole pairs. The rotor device is positioned between the first stator component and the second stator component. The rotor device has two rotor poles. |
| US10164499B2 |
Voice coil motor
A voice coil motor (VCM) is disclosed, the VCM including: a rotor including a bobbin accommodated by a lens, and a coil block arranged at a periphery of the bobbin, a base formed with an opening for exposing a lens and a first foreign object penetration prevention unit formed along an upper edge, a stator including magnets wrapping the coil block and a housing formed with an opening for fixing the magnets and formed at a bottom surface with lateral surfaces formed with a second foreign object penetration prevention unit coupled to the first foreign object prevention unit, and an elastic member coupled to the bobbin to elastically support the bobbin. |
| US10164498B2 |
Fan device
A fan device includes: a stator core having a plurality of salient poles that protrude outwards in a radial direction; a rotor magnet that is rotatably provided outside the stator core; and a dustproof cover mounted to the stator core and positioned between the stator core and the rotor magnet, wherein the dustproof cover has a cylindrical part having an inner surface being provided with one or more convex part, the convex part being fitted into a slot gap between distal ends of adjacent two of the salient poles. |
| US10164497B2 |
Dynamic sealing encoder assembly
Electric motors are disclosed. The motors are preferably for use in an automated vehicle, although any one or more of a variety of motor uses are suitable. The motors include lift, turntable, and locomotion motors. |
| US10164476B2 |
Device handover
Described herein are methods and systems for facilitating a wireless power handover. In particular, a controller may cause a first transmitter to provide electrical power to a receiver. The controller may then determine that a handover condition is met and may responsively facilitate a handover to a second transmitter. During this handover, the controller may engage in a phase-determination process to determine first and second phases at which the first and second transmitters should respectively provide electrical power to the receiver. Once determined, the controller may then cause the first and second transmitters to respectively provide electrical power to the receiver at the first and second phases and at substantially the same time. Subsequently, the controller may cause the first transmitter to no longer provide electrical power to the receiver and the second transmitter to continue to provide electrical power to the receiver, thereby completing the handover. |
| US10164474B2 |
Wireless power transmitter and wireless power transmission method
A wireless power transmitter includes a sensor configured to sense an object, a power transmitter configured to wirelessly transmit power to a wireless power receiver, and a controller configured to determine whether the object is the wireless power receiver, and control the power transmitter to wirelessly transmit power to the wireless power receiver upon the object being determined to be the wireless power receiver, wherein the sensor and the power transmitter comprise separate coils. |
| US10164473B2 |
System and method for device charging
Aspects of the present disclosure involve a system and method for charging a device. The current disclosure also presents a cradle which can be used as an interface for communicating with external computing systems and power charging systems. In one embodiment, the cradle is used to down convert a high powered signal from a power charging system for use to charge a device such as a wearable. In another embodiment, the cradle is used to communicate with and external computing system for device upgrades and maintenance. |
| US10164471B2 |
Transmitter for wireless charger
Provided is a transmission device for a wireless charger. A transmission device for a wireless charger in accordance with exemplary embodiments of the present invention comprises: a plurality of planar coils which transmit a wireless power signal for wireless charging and which are arranged so as to be at least partially overlapped with each other; a shielding sheet which has an attachment surface to which a part or all of the planar coils are fixed by the medium of an adhesive layer, and which shields a magnetic field generated from the planar coils; and a height deviation compensation means which is provided on the attachment surface and which compensates for individual height deviation between each planar coil and the attachment surface. |
| US10164468B2 |
Protective cover with wireless charging feature
A protective cover for a portable electronic device includes a protective shell for receiving and at least partially covering the portable electronic device. The protective cover includes a rechargeable power storage device and an electrical coil proximate a back surface of the shell. The protective cover also includes electrical circuitry configured to transfer first electrical power from the rechargeable power storage device to the installed portable electronic device. The electrical circuitry is also configured to transfer second electrical power from the rechargeable power storage device to the electrical coil. The electrical coil is configured to wirelessly transfer at least a portion of the second electrical power to a second portable electronic device. The protective cover may also include a visual indicator for indicating a status of the wireless transfer of the second electrical power to the second portable electronic device. |
| US10164463B2 |
Reducing power losses in a redundant power supply system
A power supply system includes at least a first power supply module and at least one redundant power supply module. The at least one power supply module supplies power to an output terminal. The at least one redundant power supply module operates in a first state and in a second state. In the first state the second power supply module supplies power to the output terminal. In the second state the second power supply module provides standby power and operates in a burst mode (for example, such as a discontinuous conduction mode). |
| US10164461B2 |
Wireless charging device, system, and method based on back cover mobile power supply
The present disclosure discloses a wireless charging device, system, and method based on a back cover mobile power supply. The wireless charging system includes a wireless charger, a back cover mobile power supply, and an intelligent terminal. The intelligent terminal is provided with a main battery and a wireless charging device. A built-in induction coil is powered and generates an electromagnetic field when a wireless charger is powered on. The back cover mobile power supply inducts the electromagnetic field and generates a current to the wireless charging device. The intelligent terminal and the back cover mobile power supply are controlled to enter a charging state, and a charging current is transmitted to the main battery of the intelligent terminal and the back cover mobile power supply, respectively, so as to perform charging, when the current is detected by the wireless charging device. |
| US10164456B2 |
Method for charging a lithium ion battery
A method for charging a lithium ion battery includes the steps of: 1) determining a maximum charging current I0 and a lowest anode potential η of the lithium ion battery at which no lithium precipitation occurs; 2) charging the lithium ion battery at a constant current of I1 which is greater than I0 for a charging time t1; 3) discharging the lithium ion battery at a constant current of I2 which is less than I0 for a discharging time t2, 5≤t1/t2≤50; 4) repeating steps 2) and 3) until a cutoff voltage of the lithium ion battery reaches V0 and standing the lithium ion battery for a standing time t3; and 5) charging the lithium ion battery at a constant current of I0 until the cutoff voltage of the lithium ion battery reaches V0 and charging the lithium ion battery to a cutoff current of I3 at a constant voltage. |
| US10164454B2 |
DC voltage supply system configured to precharge a smoothing capacitor before supplying a load
The invention concerns an electrical system that comprises: —an electrical charge (42, 43); —a decoupling capacitor (41); —a DC voltage power supply system, comprising first and second terminals (321, 322), including: —a DC voltage source (2) comprising first and second poles; —a first branch including a first contactor (51); —a second branch including first and second switches (302, 303) and an inductor (305) connected in series in order to selectively connect the DC voltage source to the first terminal (321) of the power supply system; —a unidirectional conducting device (307, 308, 309) for conduction from the second terminal of the DC power supply system to a connection node (323) between the second switch (303) and said inductor (305); —a control circuit (304) comprising —a mode for supplying electrical load (42, 43); —a mode for charging the decoupling capacitor (41). |
| US10164450B2 |
Early alert of battery thermal state based on voltage
A battery management controller includes input channels to receive a voltage signal from a battery and output channels to provide diagnostic signals to an operator. The controller is programmed to output a diagnostic signal predictive of a thermal condition in response to the voltage decreasing at a rate greater than a predetermined rate that signals that the voltage is decreasing toward a local minimum that precedes an increase in the voltage indicative of a battery temperature increase rate becoming greater than a threshold. The diagnostic signal may be used to alert the operator of the condition. The controller may be further programmed to issue commands to mitigate the thermal condition based on the diagnostic signal. |
| US10164449B2 |
Mobile terminal charger
A mobile terminal charger relates to the field of mobile terminals such as cell phone and data card with battery charging. The mobile terminal charger comprises: a thermistor and a charger output protection circuit, wherein the thermistor mounted on a head of a connector accesses a charger circuit via a charger direct current (DC) cable, constitutes a charger loop resistor with the resistor in the charger; and the charger output protection circuit cuts off or reduces the output power of the charger when the resistance of the charger loop resistor is less than the overcurrent protection threshold value. |
| US10164446B2 |
Discharge circuit malfunction diagnosis device and discharge circuit malfunction diagnosis method
The discharge circuit malfunction diagnosis device configured to diagnose a malfunction of a discharge circuit, which is to be applied to a power supply system including: an assembled battery including a plurality of cells; a discharge circuit which is configured to discharge the each of the plurality of cells when driven; and a voltage adjustment section configured to determine, based on voltages of the respective plurality of cells of the assembled battery, a target cell voltage and a cell to be discharged, and configured to drive a discharge circuit for the cell to be discharged in accordance with the target cell voltage, includes a malfunction diagnosis section configured to compare a discharge circuit pre-driving voltage and a discharge circuit post-driving voltage of the cell to be discharged, to thereby diagnose a malfunction of a discharge circuit corresponding to the cell to be discharged. |
| US10164442B2 |
Battery monitoring device
A battery monitoring device monitoring a battery unit connecting battery blocks, the battery unit being configured by each of the battery blocks connecting battery cells, includes: a voltage detection circuit connected to each of the plurality of battery cells via a voltage detection line; a first equalization circuit as a circuit provided with at least a first switching element, the first equalization circuit being disposed for each of the battery cells and connected to the corresponding battery cell; a resistor element disposed on the voltage detection line; a second equalization circuit as a circuit provided with at least a second switching element, the second equalization circuit being disposed for each of the battery blocks and connected to the corresponding battery block; and a controller configured to control driving of the switching elements. The second equalization circuit is connected further on the battery block side than the resistor element. |
| US10164436B2 |
Power control system, power control apparatus and power control method
In a power control system including a first controller configured to control supply of power from a photovoltaic module to a plurality of loads and a second controller configured to control charge/discharge of a storage battery, which is one of the plurality of loads, the first controller controls output following power consumption by the plurality of loads, and the second controller increases, during a self-sustaining operation, charging power of the storage battery and detects output fluctuation from the photovoltaic module or from the first controller along with the increase in the charging power, then based on the detected output fluctuation, controls charge of the storage battery, thus, even if connection to the grid is disconnected, supply power may be replenished by the load power used for supply to the predetermined loads, thereby allowing a stable power supply to the other loads. |
| US10164431B2 |
Outage management and prediction for a power grid system
Outages associated with an electrical energy distribution system are managed, identified and/or predicted. In an implementation, a system provides for generating network topology data, indicative of a topology for an electrical energy distribution system associated with a power outage, based on connectivity data for devices in the electrical energy distribution system. The system also provides for determining, based on the network topology data, a first set of devices from the devices that are de-energized and determining a second set of devices from the devices that are not included in the first set of devices. Furthermore, the system provides for updating, based on report data associated with the second set of devices, the network topology data. Then, the system provides for identifying, based on the updated network topology data, a device from the second set of devices that satisfies a criterion associated with the power outage. |
| US10164430B2 |
Subsea power distribution device and system
A subsea power distribution device and system. The subsea power distribution device comprises a watertight housing accommodating at least one transformer, the transformer having a primary winding and a plurality of secondary windings; input terminals, electrically connected to the primary winding and arranged to be connected to a remote power supply; output terminals, electrically connected to the secondary windings and arranged to be connected to subsea power consuming devices. The switches are arranged to break the connections between each secondary winding and a corresponding output terminal, and the switches are arranged within the watertight housing. |
| US10164428B2 |
Voltage-source multi-level converter, DC power transmission system, and fault processing method and device
The disclosure is related to a voltage-source multi-level converter including a phase unit. The phase unit includes first and second bridge arms, each includes modules and reactor connected in series. In the first bridge arm, a first terminal of first reactor is connected to alternating-current terminal of the phrase unit, a second terminal thereof is connected to a first terminal of the first modules, and second terminal of the first modules is connected to first DC terminal of the phrase unit. In the second bridge arm, a first terminal of the second reactor is connected to the alternating-current terminal, a second terminal thereof is connected to a first terminal of the second modules, and a second terminal of the second modules is connected to second DC terminal of the phrase unit. Then, a parallel fault shunt circuit is connected between the second terminals of the first and second reactors. |
| US10164427B2 |
Sequentially operated modules
Method, modules and a system formed by connecting the modules for controlling payloads are disclosed. An activation signal is propagated in the system from a module to the modules connected to it. Upon receiving an activation signal, the module (after a pre-set or random delay) activates a payload associated with it, and transmits the activation signal (after another pre-set or random delay) to one or more modules connected to it. The system is initiated by a master module including a user activated switch producing the activation signal. The activation signal can be propagated in the system in one direction from the master to the last module, or carried bi-directionally allowing two way propagation, using a module which revert the direction of the activation signal propagation direction. A module may be individually powered by an internal power source such as a battery, or connected to external power source such as AC power. The system may use remote powering wherein few or all of the modules are powered from the same power source connected to the system in a single point. The power may be carried over dedicated wires or concurrently with the conductors carrying the activation signal. The payload may be a visual or an audible signaling device, and can be integrated within a module or external to it. The payload may be powered by a module or using a dedicated power source, and can involve randomness associated with its activation such as the delay, payload control or payload activation. |
| US10164424B2 |
High precision low-voltage output limiter
An overvoltage protector uses a low-power shunt regulator to provide precise overvoltage protection at low voltages. The shunt regulator communicates with the current limiter to the input voltage allowing precise current measurement while protecting the shunt regulator from excessive power consumption. |
| US10164423B2 |
Method and system for ground plane isolation
A system has a plurality of circuits each having an individual ground connection. The system further has a common ground connection connected with each ground connection of each circuit of the plurality of circuits via an associated isolation circuit, wherein each isolation circuit has: an NMOS transistor having a load path connecting the common ground connection with an individual ground connection of an associated circuit, and having a gate connection receiving an activation signal, and a first shunt resistor coupled in parallel with the load path. |
| US10164421B1 |
Safety circuits for electrical products
The response of a switch supplying electrical power to a load is periodically tested to ensure proper operation and control over the switch. In the event the switch does not respond to commands from a controller during a test cycle to turn off and open a circuit supplying power to the load, a short circuit is created by a test switch. In this event, a fuse is automatically blown preventing uncontrolled power from reaching the load. In one example, the load can take the form of a resistive heating element in an electric heating blanket or electric heating pad. |
| US10164416B2 |
Electrical cord connection covering techniques
An electrical connection covering apparatus is designed to protect from moisture a connection between a plug of one extension cord and a socket of another extension cord. A compressible and elastic diaphragm is used to form a seal around the cables of the extension cords where they enter the apparatus. The apparatus includes a housing that has at least one aperture. The diaphragm extends across the aperture. The diaphragm projects inwardly with respect to an interior surface of the housing. The compressibility and elasticity of the diaphragm material is greater than that of the housing material. |
| US10164411B2 |
Switchgear
A switchgear according to the present invention includes: an air intake mechanism attachment body arranged on an air intake portion provided on a housing; an air intake opening provided in the air intake mechanism attachment body; a check valve type shutter which is arranged on the inner side of the air intake opening on the housing, performs an air intake from the outside of the housing, and blocks the air intake opening in the occurrence of an internal short circuit fault; and a ground fault partition body which is arranged between said check valve type shutter and a conductive portion in said housing and in which the length of at least one side is longer than said check valve type shutter. |
| US10164410B2 |
Spark plug extension
The following invention relates to an ignition coil assembly for an ignition system comprising an ignition coil where said assembly has a main axis and is configured for insertion into and/or removal out of a well associated with an internal combustion engine, wherein the assembly comprises an elongated extension body made of flexible material, said extension body comprising an upper end portion and a lower end portion wherein the extension body is arranged to be transversally bendable in relation to the main axis so that the upper end portion and the lower end portion may assume an angle (α) in relation to each other. |
| US10164407B2 |
Semiconductor laser with integrated phototransistor
The present invention relates to a semiconductor laser for use in an optical module for measuring distances and/or movements, using the self-mixing effect. The semiconductor laser comprises a layer structure including an active region (3) embedded between two layer sequences (1, 2) and further comprises a photodetector arranged to measure an intensity of an optical field resonating in said laser. The photodetector is a phototransistor composed of an emitter layer (e), a collector layer (c) and a base layer (b), each of which being a bulk layer and forming part of one of said layer sequences (1, 2). With the proposed semiconductor laser an optical module based on this laser can be manufactured more easily, at lower costs and in a smaller size than known modules. |
| US10164405B2 |
Wavelength locker integrated with a silicon photonics system
A wavelength locker integrated with a silicon photonics transmission system comprising a silicon-on-insulator (SOI) substrate and an input via a power tap coupler to receive a fraction of a transmission signal with one or more frequencies from a primary output path of the silicon photonics transmission system. The wavelength locker further includes a splitter configured to split the input to a first signal in a first path and a second signal in a second path and a first delay-line-interferometer (DLI) coupled to the second path to receive the second signal and configured to generate an interference spectrum and output at least two sub-spectrums tunable to keep quadrature points of the sub-spectrums at respective one or more target frequencies. The wavelength locker is configured to generate an error signal fed back to the silicon photonics transmission system for locking the one or more frequencies at the one or more target frequencies. |
| US10164404B2 |
Crystalline color-conversion device
According to an embodiment, a crystalline color-conversion device includes an electrically driven first light emitter, for example a blue or ultraviolet LED, for emitting light having a first energy in response to an electrical signal. An inorganic solid single-crystal direct-bandgap second light emitter having a bandgap of a second energy less than the first energy is provided in association with the first light emitter. The second light emitter is electrically isolated from, located in optical association with, and physically connected to the first light emitter so that in response to the electrical signal the first light emitter emits first light that is absorbed by the second light emitter and the second light emitter emits second light having a lower energy than the first energy. |
| US10164403B2 |
Cap member and light-emitting device
A cap member comprises a cylindrical part, an annular top plate part having an opening formed at a central portion thereof and being configured to cover one end of the cylindrical part, a window glass disposed inside the cylindrical part, and an adhesion member configured to adhere the top plate part and the window glass each other. The top plate part is depressed so that an opening end of the opening enters an inside of the cylindrical part, and an inner surface of the top plate part is configured as a flat inclined surface from a coupling part between the cylindrical part and the top plate part to the opening end. |
| US10164402B2 |
Stabilizing optical frequency combs
A method for operating a laser device (1), wherein an optical frequency comb can be stabilized and the frequencies of the modes thereof are describable by the formula fm=m×frep+f0, where frep is a mode spacing, f0 is an offset frequency and m is a natural number. At least one signal (S1, S2, S3, S4) is determined, which correlates with an actual value of a degree of freedom (F), wherein the degree of freedom (F) is a linear combination of the offset frequency f0 and the mode spacing frep of the frequency comb. The actual value of the degree of freedom (F) is set in a predetermined capture range (F) of a second control unit (40) using a first control unit (10) on the basis of the signal. As soon as the capture range (ΔFcapture) of the second control unit (40) is reached, the second control unit (40) is activated and the actual value is regulated to an intended value (ΔFintended) with the aid of the second control unit (40). |
| US10164400B2 |
Wavelength conversion element, light source device, and projector
A wavelength conversion element includes a substrate; a wavelength conversion portion that converts incident light of a first wavelength into light of a second wavelength different from the light of the first wavelength; and a bonding material that bonds the substrate and the wavelength conversion portion. The wavelength conversion portion includes a first surface on which the light of the first wavelength is incident, and a second surface that is positioned on a side opposite to the first surface. The bonding material bonds the substrate and the second surface of the wavelength conversion portion, and forms a bonding region inside the second surface. The wavelength conversion portion is configured such that an irradiation region irradiated with the light of the first wavelength is set on the first surface inside the bonding region. |
| US10164399B2 |
Mid-infrared cascading fiber amplifier and method for amplification thereof
A mid-infrared cascading fiber amplifier device having a source configured to generate a first electromagnetic wave output at a first frequency, a fiber coupled to the source and a pump coupled to the fiber and configured to generate a second electromagnetic wave output at a second frequency, wherein the second frequency is higher than the first frequency and causes the fiber to undergo two or more transitions in response to stimulation by the first electromagnetic wave output at the first frequency, wherein the first transition generates the first electromagnetic wave output approximately at the first frequency and the second transition generates the first electromagnetic wave output approximately at the first frequency. |
| US10164397B2 |
Laser oscillation device
A laser oscillation device includes: a refrigerant container; at least one cartridge which is attached to the refrigerant container and which includes a laser gain medium and an incidence path section for guiding laser seed light to the laser gain medium; at least one nozzle for spraying a refrigerant to the laser gain medium, the at least one nozzle being disposed inside the refrigerant container, and a vacuum heat insulating container housing the refrigerant container inside and forming a vacuum insulation layer on an outer peripheral side of the refrigerant container. The cartridge is disposed so as to be insertable and removable with respect to the refrigerant container along a longitudinal direction of the laser gain medium. |
| US10164396B2 |
Laser unit and non-transitory computer-readable storage medium
There may be provided a laser unit including a display configured to display one or both of electric power consumed by the laser unit and electric energy consumed by the laser unit. |
| US10164394B2 |
Direct-attach connector
A contact ribbon configured to connect a cable to a substrate includes a plurality of signal contacts, a ground plane, and at least one ground contact extending from the ground plane. The plurality of signal contacts are connected by a support member, and the support member is removable after the plurality of signal contacts are connected to the cable. |
| US10164391B2 |
Retrofit LED adapter
An LED adapter to retrofit non-LED light fixtures to accept LED lights without electrical rewiring. The LED adapter includes a multi-use base plug that is configured to connect to the socket on the non-LED light fixture and a universal LED plug configured to connect to the socket on an LED light. The multi-use base plug may be a four-pin square base, a two-pin (aligned or off-set) square base, a two-pin tombstone base, a two-pin oval base, or a threaded base. The adapter may also include a power regulator disposed between the universal LED plug and the multi-use base plug. The power regulator includes one or more resistor to adjust the current or voltage supplied by the non-LED light fixture so as to be compatible with the LED light fixture. |
| US10164389B2 |
Breakout enclosure for transitioning from trunk cable to jumper cable
An assembly for breaking out a trunk cable includes: a base having a generally flat surface adapted for mounting to a mounting surface; a shell having a front wall, two side walls extending from opposite sides of the front wall, and two opposed end walls, the side walls of the shell mounted to the base to form a cavity; a plurality of connectors mounted to each of the side walls; a trunk cable routed into the cavity through one of the end walls, the trunk cable comprising a plurality of power conductors; and at least one bus bar mounted to the shell within the cavity, at least one of the power conductors and at least one of the connectors in electrical connection with the bus bar. |
| US10164386B2 |
Socket outlet adapter
The invention relates to an electric socket outlet, in particular an electric socket outlet adapter (11) comprising a housing (13), a socket zone that is located on the housing (13) and includes a first socket (15) and a second socket (17) for accommodating plugs of a first standard and a second standard, the first and second sockets being provided with first and second plug holes. The socket outlet (11) also comprises a first movable protective element (19) which can cover the first plug holes as well as a second movable protective element (21) which can cover the second plug holes. In the closed position, the first or the second protective element (19, 21) is mechanically locked when the other protective element (19, 21) is in the open position. |
| US10164384B2 |
Coaxial connector
A coaxial connector mounted to a board, wherein a center conductor is provided with a contact portion in contact with the terminal of a counterpart connector. A first coupling portion couples to the contact portion and extends in the axial direction of an outer conductor. A bend portion couples to the first coupling portion and is bent in the radial direction of the outer conductor. A second coupling portion couples to the bend portion and extends in the radial direction of the outer conductor. A connecting portion couples to the second coupling portion and connects said center conductor to on-board circuitry. A first and second expanded portion produced by an expansion of a portion of the outer peripheral surface of said first and second coupling portions, is formed in the first and second coupling portions. |
| US10164381B2 |
Plug-in fuse element
Embodiments disclose a plug-in fuse element comprising a strip-shaped sheet metal part having a first end section, a second end section, and an interposed center section, wherein the first end section is a flat plug-in contact; the second end section is a connecting region configured to connect to a stranded conductor, and the center section is an overcurrent protection device. In some embodiments, a stranded conductor is connected on at least one end to a connecting region of at least one plug-in fuse element. In some embodiments, a wiring system includes at least one stranded conductor connected via a flat plug-in contact of a plug-in fuse element to a flat conductor. In some embodiments, a vehicle comprises the at least one wiring system. |
| US10164377B2 |
Plug connector and electrical connector assembly
A plug connector being insertable into a corresponding socket connector is provided. The plug connector includes a first housing, a lock, and a first insertion device. The first housing includes a plurality of first connection terminal receiving passageways, while the lock is integrally connected with the first housing. The first insertion device formed on the lock. |
| US10164376B2 |
Block-out lock and removal key for computer network ports
A block-out lock and removal key includes a locker and a key. The locker has a hollow housing in a shape corresponding to a socket of a network port for engagement, a locker hole extending through a front portion of the housing and a latch body connecting to a rear portion of the housing. The latch body has a rear section extended upwards toward the front portion of the housing and then downwards to form a displaceable piece parallel with the front portion of the housing with a holding section at a top of the displaceable piece and a block facing toward an inner end of the locker hole. The key has its front section arranged correspondingly to a shape of the locker hole to be inserted therein and rotated for unlocking. An eccentric block is further arranged at the front section of the key correspondingly to the block on the displaceable piece for removing the locker from the socket of the network port in operation. |
| US10164375B1 |
Plug connector
A plug connector includes an insulating housing, a plurality of detecting terminals, a plurality of connection terminals, an outer shell and at least one ground piece. The insulating housing has a plurality of connection terminal grooves and a plurality of detecting terminal grooves. The plurality of the detecting terminals are assembled in the plurality of the detecting terminal grooves separately. The plurality of the connection terminals are assembled in the plurality of the connection terminal grooves separately. The outer shell surrounds the insulating housing. A top surface of the outer shell protrudes upward and then is bent frontward to form a locking portion. The at least one ground piece is mounted to at least one side of the insulating housing, and a portion of the at least one ground piece is exposed outside from the insulating housing and the outer shell. A receptacle connector is to receive the plug connector and includes a sliding block to cover the detecting terminals and to be raised by the plug connector as it is inserted. |
| US10164372B1 |
Electrical connecting assembly
An electrical connecting assembly is provided, including a male connector and a female connector corresponding to the male connector. The male connector has a first insulating body and a conductive member protruding from the insulating body. The female connector has a second insulating body, a hollow conductive seat, a resilient element, and sliding unit. The second insulating body has an opening portion and a chamber for receiving the conductive member. The conductive seat is disposed in the chamber, the sliding unit is movably disposed in the conductive seat, and the resilient element connects the sliding unit to the conductive seat. Specifically, the internal diameter of the opening portion is shorter than the internal diameter of the conductive seat, and the resilient element forces the sliding unit to move to the opening portion, so that the sliding unit forms a seal with the opening portion. |
| US10164365B2 |
Female terminal and connector including female terminal
A female terminal downsized in a male terminal-inserting direction. A terminal body has a reception portion, for receiving a male terminal. A first and second spring portions are arranged to be opposed to each other so as to sandwich the male terminal inserted into the reception portion from an inlet portion thereof. The first spring portion has a first and second contact points brought into contact with the sale terminal in the reception portion. The second spring portion has a third contact point brought into contact with the stale terminal in the reception portion. The third contact point is between the first and second, contact points in the male terminal-inserting direction. The first contact point is in the inlet portion of the reception portion, and the second contact point is at a more inward location in the reception portion than the first contact point. |
| US10164360B2 |
Connector, and header and socket used in connector
In a connector, fitting a socket housing and a header housing to each other brings a socket-side signal terminal and a header-side signal terminal into contact with each other, and brings a socket-side power supply terminal and a header-side power supply terminal into contact with each other. The socket-side signal terminal and the socket-side power supply terminal are disposed along a long side direction of the socket housing. In the long side direction of the socket housing, the socket-side signal terminal is smaller than the socket-side power supply terminal in width. |
| US10164358B2 |
Electrical feed-through and connector configuration
An electrical feed-through assembly includes electrically conductive pins having a top apex and a bottom apex, where the pins extend through at least a majority of an electrically non-conductive material. The top apexes, the bottom apexes, or both the top and bottom apexes of the pins have an electrically conductive connection pad material, such as a solder pad, coupled thereto. In variations, the top and/or bottom apexes may be slightly recessed from a corresponding surface of the non-conductive material, such that the connection pads fill the respective recesses; and/or the top and/or bottom apexes barely extend from a corresponding surface, such that the connection pads bulge out from the corresponding surface. Such a feed-through configuration may inhibit pin bending, in addition to enabling use of more types of connectors beyond pin-and-socket type connectors. |
| US10164352B2 |
Resilient bushing and connector comprising same
The present invention relates to a bushing for contacting a braid of a line within a connector, the bushing is essentially tapering in an insertion direction in which the bushing is adapted to be inserted into the braid in order to be encompassed thereby. Further, the invention relates to a connector comprising a bushing. In order to provide a bushing which allows for being inserted into the braid in a gentle manner and at the same time allows the braid to be evenly contacted with the bushing for establishing a reliable mechanical and/or electrical connection therewith, the present invention provides that the bushing has a radial elasticity allowing a spring tensioned widening and/or compression of the bushing. |
| US10164350B2 |
Terminal attached wire
A terminal attached wire includes a wire and a terminal fitting. The wire includes a core wire. The core wire is made of aluminum or an aluminum alloy and is covered with a coating. The core wire is exposed at and end portion of the wire. The terminal fitting is made of copper or a copper alloy and is connected to the end portion of the wire. A sacrifice layer having a higher ionization tendency than aluminum is provided on a portion of the terminal fitting except for an electrical connection portion with another member. |
| US10164348B2 |
Terminal/connector having integral oxide breaker element
A one piece integral electrical terminal has a mount portion and a wire receiving portion. The wire receiving portion has a continuous annular interior wall having a contact portion with an integral oxide breaker especially suited to breaking through the oxide layer on aluminum wire. The wire receiving portion also has a sealing portion with at least one integral seal ring. An electrical cable is made by crimping the electrical terminal to an aluminum wire using a modified hexagonal crimp. |
| US10164344B2 |
Waveguide device, slot antenna, and radar, radar system, and wireless communication system including the slot antenna
A waveguide device includes a first electrically conductive member having a first electrically conductive surface; a second electrically conductive member having a second electrically conductive surface which opposes the first electrically conductive surface; and a ridge-shaped waveguide member on the second electrically conductive member. The second electrically conductive member has a throughhole which splits the waveguide member into first and second ridges. The first and second ridges each have an electrically conductive end face, the end faces opposing each other via the throughhole. The opposing end faces and the throughhole together define a hollow waveguide. The hollow waveguide is connected to a first waveguide extending between the waveguide face of the first ridge and the first electrically conductive surface, and to a second waveguide extending between the waveguide face of the second ridge and the first electrically conductive surface. |
| US10164330B2 |
Antenna assembly and self-curing decoupling method for reducing mutual coupling of coupled antennas
The disclosure provides antenna assemblies and methods for reducing mutual coupling of coupled antennas. According to an embodiment, the antenna assembly, comprises: a first antenna; and a second antenna coupled with the first antenna; wherein a first capacitive load is provided to the first antenna at a first position of the first antenna so that a mutual coupling between the first antenna and the second antenna is reduced. According to the present disclosure, at least some of the following advantages may be achieved: 1) no any component that connects or structure between coupled antennas is required; 2) the capacitive load is very little frequency dependent so that the method is highly suitable for antenna decoupling at low frequencies; 3) the required capacitive load takes almost no space in the circuit layout; and 4) the load does not noticeably change antenna radiation patterns. |
| US10164326B2 |
Frequency-selective surface composite structure
A frequency-selective composite structure includes a laminate panel, and a frequency-selective filter including a plurality of frequency-selective surface elements coupled to an exterior surface of the laminate panel and arranged in a frequency-selective surface pattern, wherein each one of the frequency-selective surface elements includes a nanomaterial composite. |
| US10164325B1 |
Communication device
A communication device includes an antenna system. The antenna system includes a first dual-polarized antenna, a second dual-polarized antenna, a first reflector, a second reflector, a first PIFA (Planar Inverted F Antenna), a second PIFA, a third PIFA, a first metal loop, a second metal loop, and a third metal loop. The first reflector is disposed adjacent to the first dual-polarized antenna. The second reflector is disposed adjacent to the second dual-polarized antenna. The first metal loop is disposed adjacent to the first PIFA. The first metal loop is floating and completely separated from the first PIFA. The second metal loop is disposed adjacent to the second PIFA. The second metal loop is floating and completely separated from the second PIFA. The third metal loop is disposed adjacent to the third PIFA. The third metal loop is floating and completely separated from the third PIFA. |
| US10164324B1 |
Antenna placement topologies for wireless network system throughputs improvement
A combined antenna placement topology is disclosed herein. The combined antenna placement topology is utilized to get optimized antenna isolation, efficiency, system coverage and throughputs. The combined topology includes antenna location diversity, polarization diversity and antenna type diversity. |
| US10164322B2 |
Signal transmission system for electronic devices
An electronic device including a signal transmission system. The electronic device may include a housing, and a cover coupled to the housing and defining a groove formed in the cover. The electronic device may also include a signal transmission system positioned within the housing. The signal transmission system may include an antenna at least partially received within the groove formed in the cover. The antenna may have an antenna body, and a contact pad in electrical communication with the antenna body. The signal transmission system may also have a flexible member positioned adjacent the antenna body. The flexible member may contact the contact pad of the antenna. |
| US10164314B2 |
Antenna module
The present disclosure relates to an antenna module for installing at an opening of a vehicle roof, wherein the antenna module can be arranged at the opening and can be latched there via at least one spring element, wherein the fastening of the antenna module can be secured to the vehicle roof via a locking element which, in its locking position, blocks a resilient backward movement of the spring element out of the latched position. |
| US10164313B2 |
Coaxial diplexer and signal coupling device
A signal coupling device associating a first frequency band signal and a second, different frequency band, signal in a common waveguide and distributing the signals to two separate waveguides. The device comprises first and second circular waveguides. The second waveguide is coaxially arranged inside a cylindrical interior of the first waveguide. The first waveguide comprises inwardly projecting inner circumference projections in a region occupied only by the first waveguide. The projections activate higher modes from a fundamental mode. The first and second waveguides and the projections cause the superposition of the fundamental and higher modes to produce a wave front having field components in the first frequency band only in a cylindrical ring region between the second waveguide outer circumference and the first waveguide inner circumference, and having field components in the second frequency band only in a cylindrical interior of the second waveguide. |
| US10164311B2 |
High frequency signal transmission device
The instant disclosure relates to a high frequency signal transmission device which includes an insulation cover, at least one flexible flat cable, and an electrical connector assembly. The insulation cover has an accommodation space, the at least one flexible flat cable is disposed in the accommodation space, and the electrical connector assembly is electrically connected to one end of the at least one flexible flat cable. The at least one flexible flat cable includes a plurality of conductors, an insulation layer, a polyolefin resin layer, and a shielding layer. The insulation layer is laminated over the conductors. The polyolefin resin layer is attached to the insulation layer by a first low-k dielectric adhesive layer, and the shielding layer is attached to the polyolefin resin layer by another first low-k dielectric adhesive layer. |
| US10164304B1 |
Thermally dissipative electrochemical cell
According to exemplary practice of the present invention, a cylindrical secondary electrochemical cell (e.g., lithium-ion cell) includes a disk that is made of a thermally and electrically conductive material (e.g., metal material), and that lies in a geometric plane that is perpendicular to the cylindrical axis. The disk is adjacently intermediate, axially aligned with, and electrically connected to two cylindrical jelly-roll electrode components. Inventive practice is possible with respect to a variety of cell types, shapes, and chemistries. Depending on the inventive embodiment, the numbers of disks (≥1) and jelly-roll electrode components (≥2) can vary, each disk serving to augment heat transport in the radial direction. An inventive cylindrical cell thus affords superior heat spreading in the direction radially outward, 360 degrees, from the central axis of the cell. |
| US10164296B2 |
Battery module separator plates
The present disclosure includes a battery module having a first electrochemical cell and a second electrochemical cell positioned adjacent to the first electrochemical cell. The battery module also includes a separator plate disposed between the first electrochemical cell and the second electrochemical cell. The separator plate includes a body comprising a first side and a second side opposite the first side. The first side is disposed adjacent a first face of the first electrochemical cell and includes a first indention. The first indention defines a first space between the first face of the first electrochemical cell and the first side of the separator plate. The first space is configured to enable swelling of the first electrochemical cell into the first space. |
| US10164293B2 |
Nonaqueous electrolyte and electricity storing device in which same is used
Disclosed are a non-aqueous electrolytic solution, which can improve cycle characteristics when a power storage device is used at high temperature and high voltage, and a power device using the same. The non-aqueous electrolytic solution according to the present invention comprises, in addition to a non-aqueous solvent and an electrolyte salt dissolved therein, a compound represented by the following formula (I): wherein n is an integer of 1 or 2; and when n is 1, L represents a straight or branched unsaturated hydrocarbon group of which at least one hydrogen atom is optionally substituted by a halogen atom, a cycloalkyl group of which at least one hydrogen atom is optionally substituted by a halogen atom, or an aryl group of which at least one hydrogen atom is optionally substituted by a halogen atom; and when n is 2, L represents a saturated or unsaturated divalent hydrocarbon group which optionally contains ether bond(s), or an arylene group. |
| US10164287B2 |
All-solid battery and manufacturing method therefor
A method for manufacturing an all-solid battery that includes preparing a first green sheet as a green sheet for at least any one of a positive electrode layer and a negative electrode layer and a second green sheet as a green sheet for a solid electrolyte layer, stacking the first green sheet and the second green sheet to form a stacked body, and firing the stacked body with a setter placed in contact with at least one surface of the stacked body. The setter in contact with the at least one surface of the stacked body is 0.11 μmRa or more and 50.13 μmRa or less in surface roughness. |
| US10164286B2 |
Separator-fitted single fuel cell inducing joint portion with protruding portion and sealing portion, and fuel cell stack
A separator-fitted single fuel cell having a single fuel cell, a plate-shaped metallic separator that includes a through hole, and a joint portion that joins the single fuel cell to the metallic separator and is made of a brazing material containing Ag. The joint portion includes a protruding portion that protrudes from a gap between the single fuel cell and the first main surface of the metallic separator toward the through hole. The protruding portion is lower than the second main surface as viewed from the single fuel cell. The single fuel cell includes a sealing portion that is disposed along the entire circumference of the through hole of the metallic separator, covers the protruding portion and a part of the second main surface, and is made of a sealing material containing glass. |
| US10164284B2 |
Aqueous redox flow batteries featuring improved cell design characteristics
Provided are compositions having the formula MnTi(L1)(L2)(L3) wherein L1 is a catecholate, and L2 and L3 are each independently selected from catecholates, ascorbate, citrate, glycolates, a polyol, gluconate, glycinate, hydroxyalkanoates, acetate, formate, benzoates, malate, maleate, phthalates, sarcosinate, salicylate, oxalate, a urea, polyamine, aminophenolates, acetylacetone or lactate; each M is independently Na, Li, or K; n is 0 or an integer from 1-6. Also provided are energy storage systems. |
| US10164281B2 |
Fuel-cell unit cell
A fuel-cell unit cell comprises: a membrane electrode and gas diffusion layer assembly; a cathode-side separator made of a press-molded plate, the cathode-side separator forming a plurality of cathode gas flow paths and non-flow-path portions therebetween on a cathode-side surface of the membrane electrode and gas diffusion layer assembly; and an anode-side separator made of a press-molded plate, the anode-side separator forming a plurality of anode gas flow paths and non-flow-path portions therebetween on an anode-side surface of the membrane electrode and gas diffusion layer assembly. At least one gas flow path among the plural cathode gas flow paths and the plural anode gas flow paths includes a constricting portion that is configured to reduce a flow-path height in a stacking direction of the fuel-cell unit cells as well as to reduce a flow path cross-sectional area of the gas flow path. When projected and observed along the stacking direction, the plural cathode gas flow paths and the plural anode gas flow paths are configured to have mutually different two-dimensional shapes, there exist intersect positions at which the cathode gas flow paths and the anode gas flow path intersect each other, and the constricting portion is provided at a position other than the intersect positions. |
| US10164278B2 |
Nitrogen enriched air generation and fuel tank inerting system
A fuel cell power module is used to provide nitrogen enriched air for, in one application, fuel tank inerting in an aircraft. The fuel cell power module has a recirculation line between its cathode side outlet and cathode side inlet. At least one controllable device is provided to allow the flow rate in the recirculation line to be controlled. The recirculation flow rate is adjusted such that the cathode exhaust has an oxygen concentration useful for inerting a fuel tank or suppressing fire. |
| US10164275B2 |
Fuel cell system
A fuel cell system includes: a wetness target value calculating unit configured to calculate a target value of a wet state of the fuel cell; a gas required flow rate calculating unit configured to calculate a cathode gas required flow rate on the basis of a power generation request to the fuel cell; a wetness-control anode gas flow rate calculating unit configured to calculate a wetness-control anode gas circulation flow rate at least on the basis of the wetness target value and the cathode gas required flow rate during a dry control; an anode gas flow rate control unit configured to control an anode gas circulation flow rate on the basis of the wetness-control anode gas circulation flow rate; a wetness-control cathode gas flow rate calculating unit configured to calculate a wetness-control cathode gas flow rate at least on the basis of the wetness target value and a measured value or estimated value of the anode gas circulation flow rate during the dry control; and a cathode gas flow rate control unit configured to control a cathode gas flow rate on the basis of the cathode gas required flow rate and the wetness-control cathode gas flow rate. |
| US10164266B2 |
Separator including tilted gas flow path grooves that retain water by capillary force and fuel cell using the same
A separator to be used in a fuel cell includes a gas flow path including a plurality of gas flow path grooves that allow reactive gas to flow; a gas discharge hole used for discharging the reactive gas from the gas flow path; and an outlet flow path part positioned between the gas discharge hole and the gas flow path and used for flowing the reactive gas discharged from the gas flow path into the gas discharge hole. The plurality of gas flow path grooves includes a coupling flow path part coupled to the outlet flow path part. The coupling flow path part includes tilted gas flow path grooves tilted from a direction of gravitational force. A groove width of the tilted gas flow path groove in the coupling flow path part is set such that a force of a wall surface of the tilted gas flow path groove to retain water by means of a surface tension of the water is larger than a force applied to the water by the gravitational force. |
| US10164263B2 |
Current collector for secondary battery and electrode using same
The present invention relates to a battery technology, and more particularly, to a current collector that may be widely used in secondary batteries and an electrode employing the same. The current collector includes a conductive fiber layer including a plurality of conductive fibers. Each of the conductive fibers includes a conductive core consisting of a plurality of metal filaments; and a conductive binder matrix surrounding the outer circumferential surfaces of the conductive core. |
| US10164262B2 |
Method for producing a porous metal body
Provided are a porous metal body that is excellent in terms of corrosion resistance and that is suitable for a collector for batteries such as lithium-ion batteries, capacitors, or fuel cells; and methods for producing the porous metal body. A production method includes a step of coating a porous nickel body with an alloy containing at least nickel and tungsten or a metal containing at least tin; and a subsequent step of a heat treatment. Another production method includes a step of forming a nickel-plated layer on a porous base and then continuously forming an alloy-plated layer containing at least nickel and tungsten or tin, a step of removing the porous base, and a step of reducing metal. Such a method can provide a porous metal body in which tungsten or tin is diffused in a porous nickel body or a nickel-plated layer. |
| US10164257B2 |
Negative electrode material for lithium-ion battery, and use therefor
A negative electrode material for a lithium ion battery containing a composite material, the composite material including silicon-containing particles, graphitic carbon material particles, and a carbonaceous carbon material, in which the composite material has a ratio (A/B) of an area (A) of a peak near 100 eV derived from metal Si to an area (B) of a peak near 103 eV derived from silicon oxide, as measured by XPS, of not less than 0.10 and not more than 2.30. Also disclosed is a paste including the negative electrode material, as well as a negative electrode for a lithium ion battery including a formed body of the paste and a lithium ion battery including the negative electrode. |
| US10164255B2 |
Silicon material and negative electrode of secondary battery
A silicon material useful as a negative electrode active material is provided.The silicon material has a band gap within a range of greater than 1.1 eV and not greater than 1.7 eV. A secondary battery in which this silicon material is used as a negative electrode active material has improved initial efficiency. |
| US10164254B2 |
Composite for anode active material, anode including the composite, lithium secondary battery including the anode, and method of preparing the composite
A composite anode active material includes: a silicon anode active material, a metal nitride; and a metal fluoride, wherein the metal nitride and the metal fluoride are each independently disposed on at least one surface of the silicon anode active material. |
| US10164250B2 |
Lithium-iron-manganese-based composite oxide and lithium-ion secondary battery using same
There is provided a lithium-iron-manganese-based composite oxide capable of providing a lithium-ion secondary battery which has a high capacity retention rate in charge/discharge cycles and in which the generation of a gas caused by charge/discharge cycles is reduced. A lithium-iron-manganese-based composite oxide having a layered rock-salt structure, wherein at least a part of the surface of a lithium-iron-manganese-based composite oxide represented by the following formula (1) is coated with an inorganic material: LixM1(y-p)MnpM2(z-p)FeqO(2-δ) (1) (wherein 1.05≤x≤1.32, 0.33≤y≤0.63, 0.06≤z≤0.50, 0 |
| US10164248B2 |
Negative electrode active material comprising silicon and at least one metal element, and battery, battery pack, electronic apparatus, electric vehicle, electrical storage apparatus and electricity system using same
A negative electrode active material includes a core particle comprising silicon; and at least one metal element selected from the group consisting of: Ge, Sn, Ni, Mo, W, Ag, Pd, Cu, Bi, Fe, Co, Mn, Cr, V, Ga, B, Sb, In, Te, Cd, Rh, Ru, Nb, Ta, Re, Os, Ir, Pt, Pb and P. The negative electrode active material has an elemental composition that varies continuously from a center of the core particle to a surface of the core particle. A negative electrode, a battery, an electric vehicle, an electric storage apparatus, an electronic apparatus and a power storage system each include the negative electrode active material. |
| US10164243B2 |
Method for manufacturing positive electrode active material for energy storage device and energy storage device
An energy storage device having high capacity per weight or volume and a positive electrode active material for the energy storage device are manufactured. A surface of a main material included in the positive electrode active material for the energy storage device is coated with two-dimensional carbon. The main material included in the positive electrode active material is coated with a highly conductive material which has a structure expanding two-dimensionally and whose thickness is ignorable, whereby the amount of carbon coating can be reduced and an energy storage device having capacity close to theoretical capacity can be obtained even when a conduction auxiliary agent is not used or the amount of the conduction auxiliary agent is extremely small. Accordingly, the amount of carbon coating in a positive electrode and the volume of the conduction auxiliary agent can be reduced; consequently, the volume of the positive electrode can be reduced. |
| US10164225B2 |
Battery system housing with busbar grid fixation
A rechargeable battery system, a battery pack, methods of manufacturing the same, and an electric vehicle are disclosed herein. The battery pack includes an upper tray, a first busbar attached to the upper tray, a lower tray, a second busbar attached to the lower tray, and a plurality of battery cells arranged in the upper and lower trays. The rigidity of the combination of the upper tray and the first busbar is provided predominantly by the first busbar. |
| US10164223B2 |
Case system for electric cells with horizontally-oriented lead sheets, and battery and battery rack using the same
A case system for lead batteries is provided. The case system has an essentially six sided cuboid shape with two pairs of parallel sidewalls perpendicular to each other. Each pair of sidewalls defines two opposite surfaces of the essentially cuboid shape and further defines an interior volume inside the case system. The case system includes a further pair of parallel sidewalls, each of them perpendicular to the sidewalls above and each with a surface area larger than that of any one of the surface areas of the above sidewalls. One of the sidewalls is arranged as a separate cover wall for sealing the case system. At least one division plane is further included in the case system. The division plane divides the interior volume, such as to form a plurality of compartments, each for storing an electrical cell. All division planes are perpendicular to the cover wall. Further, an electrical cell, a lead battery and a lead battery layout including the above are shown. |
| US10164222B2 |
Battery module
A battery module is provided. The battery module includes a battery module comprising a plurality of battery units comprising a pair of terminals respectively; and a connector comprising insertion portions, wherein the pair of terminals are inserted into the insertion portions and the plurality of terminals are electrically connected to each other. |
| US10164221B2 |
Secondary battery
A secondary battery is disclosed. In one aspect, the secondary battery includes an electrode assembly, a case having an opening and housing the electrode assembly and a cap assembly sealing the opening of the case. The cap assembly includes an electrode terminal electrically connected to the electrode assembly. The cap assembly also includes a cap plate including a first terminal hole into which the electrode terminal is inserted and a coupling groove extending from a lateral surface of the cap plate past the first terminal hole. The coupling groove has an open side facing the electrode assembly. The cap assembly further includes an insulation member connected to the cap plate via the inside of the coupling groove and configured to be slidably engaged with the coupling groove. |
| US10164218B2 |
Manufacturing device and manufacturing method of light-emitting element
Disclosed is a manufacturing apparatus of a light-emitting element including: a main transporting route extending in a first direction, the main transporting route comprising first and second transfer devices connected through a first transporting chamber; a sub-transporting route extending in a second direction intersecting the first direction, the sub-transporting route comprising a second transporting chamber connected to the first or second transfer device and a delivery chamber connected to the second transfer chamber; and a plurality of first treatment chambers connected to the delivery chamber. The main transporting route is configured to transfer a substrate to be treated in a horizontal state, and one of the plurality of treatment chambers is configured to hold the substrate in a vertical state during treatment. |
| US10164215B2 |
Electro-optic device that prevents deterioration of a light emitting element
An electro-optic device includes a substrate that has a first surface and an end face crossing the first surface; a light emitting element that is disposed on the first surface; a planarization layer that covers the light emitting element; and a first inorganic sealing layer that is disposed on the planarization layer. An outer edge of the first inorganic sealing layer is disposed between an outer edge of the planarization layer and a first region where the light emitting element is disposed. |
| US10164210B2 |
Functional film
A functional film has a support which has a value of retardation of equal to or less than 50 nm; a protective inorganic film which is formed on the support; one or more combinations, each of which is composed of an organic film as an underlayer and an inorganic film, formed on the protective inorganic film; and a sealant layer which adheres onto the inorganic film as an uppermost layer by an adhesive layer, has a value of retardation of equal to or less than 300 nm, and has a glass transition temperature lower than that of the support. |
| US10164196B2 |
Aniline derivative, charge-transporting varnish and organic electroluminescent device
Provided is an aniline derivative represented by formula (1). (In formula (1), R1 represents an alkyl group, an alkenyl group, an alkynyl group, an aryl group having 6-20 carbon atoms, a heteroaryl group, or a group represented by formula (2), and R2-R55 independently represent a hydrogen atom, a halogen atom, a nitro group, a cyano group, an aldehyde group, a hydroxy group, a thiol group, a carboxylic acid group, an alkyl group, an alkenyl group, an alkynyl group, an aryl group, a heteroaryl group, etc.) |
| US10164185B2 |
RRAM cell with PMOS access transistor
In some embodiments, the present disclosure relates to a method of operating an RRAM cell having a PMOS access transistor. The method may be performed by turning on a PMOS transistor having a drain terminal coupled to a lower electrode of an RRAM device. A first voltage is provided to a source terminal of the PMOS transistor, and a second voltage is provided to a bulk terminal of the PMOS transistor. The second voltage is larger than the first voltage. A third voltage is provided to an upper electrode of the RRAM device. The third voltage is larger than the first voltage. |
| US10164183B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes at least one bottom electrode, a resistive layer, and a top electrode. The bottom electrode has two opposite sidewalls. The resistive layer is disposed on the bottom electrode, extends past at least one of the two opposite sidewalls of the at least one bottom electrode, and has a variable resistance. The resistive layer is disposed on the bottom electrode and extends past at least one of the two opposite sidewalls of the at least one bottom electrode. |
| US10164181B2 |
Sidewall protection of memory cell
A memory device includes a bottom electrode, a resistance switching element, a top electrode, a spacer and a conductive feature. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching electrode. The spacer abuts the resistance switching element. The conductive feature is over the top electrode. The spacer is at least partially between the conductive feature and the top electrode. |
| US10164174B2 |
Magnetoresistance effect element and magnetic memory
A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface if the layers. The second magnetic layer has a saturation magnetization lower than that of the first magnetic layer, and an interfacial magnetic anisotropy energy density (Ki) at the interface between the first magnetic layer and the first non-magnetic layer is greater than that of an interface between the first non-magnetic layer and second magnetic layers if being disposed adjacent each other. |
| US10164172B2 |
Multi-layered magnetic thin film stack and data storage device having the same
Provided are a multi-layered magnetic thin film stack, a magnetic tunneling junction, and a data storage device. The multi-layered magnetic thin film stack includes a FePd alloy layer including an alloy of iron (Fe) and palladium (Pd); a tunneling barrier layer, which includes MgO and is disposed on the FePd alloy layer; and a Heusler alloy layer disposed between the FePd alloy layer and the tunneling barrier layer, wherein the FePd alloy layer and the Heusler alloy layer constitute a hybrid magnetic layer. |
| US10164171B2 |
Electronic device and method for fabricating the same
The disclosed technology includes an electronic device. The electronic device includes a semiconductor memory, and the semiconductor memory includes a variable resistance element that exhibits different resistance states for storing different data and is structured to include a planar shape including two curved potions of different curvatures. |
| US10164170B2 |
Semiconductor device
A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line. |
| US10164168B2 |
Magnetic memory cell structures, arrays, and semiconductor devices
Methods of forming memory cells, magnetic memory cell structures, and arrays of magnetic memory cell structures are disclosed. Embodiments of the methods include patterning a precursor structure to form a stepped structure including at least an upper discrete feature section and a lower feature section with a broader width, length, or both than the upper discrete feature section. The method uses patterning acts directed along a first axis, e.g., an x-axis, and then along a second axis, e.g., a y-axis, that is perpendicular to or about perpendicular to the first axis. The patterning acts may therefore allow for more uniformity between a plurality of formed, neighboring cell core structures, even at dimensions below about thirty nanometers. Magnetic memory structures and memory cell arrays are also disclosed. |
| US10164165B2 |
Piezoelectric transformer and counter electrode
What is specified is a piezoelectric transformer (10) having a surface structure which has at least one protruding surface structure segment (5), wherein the piezoelectric transformer has a contour (3) and is suitable for discharging a gas in conjunction with a counter electrode (10) for generating a plasma, wherein the surface structure is configured such that the gas discharge takes place at a multiplicity of discharge initiation points (6) on the contour (3). A width of the surface structure segment (5) is smaller than the width of the piezoelectric transformer (1). |
| US10164160B2 |
Luminance pattern shaping using a back-emitting LED and a reflective substrate
A light emitting structure includes a packaged back-emitting light emitting device mounted on a reflective substrate. The properties of the reflective surface may be controlled to provide a desired luminance pattern. In this manner, the creation of a light emitting structure that provides a desired luminance pattern may be independent of the provider of the packaged light emitting device. |
| US10164159B2 |
Light-emitting diode package and method of manufacturing the same
A light-emitting diode (LED) package includes: a reflective structure including a cavity, a bottom portion having a through hole, and a sidewall portion surrounding the cavity and the bottom portion and having an inclined inner side surface; an electrode pad inserted into the through hole; an LED on the bottom portion in the cavity, the LED including a light-emitting structure electrically connected to the electrode pad and a phosphor formed on the light-emitting structure; and a lens structure filling the cavity and formed on the reflective structure. |
| US10164158B2 |
Molded chip fabrication method and apparatus
A method and apparatus for coating a plurality of semiconductor devices that is particularly adapted to coating LEDs with a coating material containing conversion particles. One method according to the invention comprises providing a mold with a formation cavity. A plurality of semiconductor devices are mounted within the mold formation cavity and a curable coating material is injected or otherwise introduced into the mold to fill the mold formation cavity and at least partially cover the semiconductor devices. The coating material is cured so that the semiconductor devices are at least partially embedded in the cured coating material. The cured coating material with the embedded semiconductor devices is removed from the formation cavity. The semiconductor devices are separated so that each is at least partially covered by a layer of the cured coating material. One embodiment of an apparatus according to the invention for coating a plurality of semiconductor devices comprises a mold housing having a formation cavity arranged to hold semiconductor devices. The formation cavity is also arranged so that a curable coating material can be injected into and fills the formation cavity to at least partially covering the semiconductor devices. |
| US10164156B2 |
Structure and formation method of image sensor structure with grid structure
Structures and formation methods of an image sensor structure are provided. The image sensor structure is provided. The image sensor structure includes a substrate, a photodiode component in the substrate, and a grid structure over the substrate. The grid structure includes a bottom dielectric element over the substrate, a reflective element over the bottom dielectric element, and an upper dielectric element over the reflective element. The reflective element has a sidewall which is anti-corrosive in a basic condition and an acidic condition. The image sensor structure also includes a color filter element over the substrate and surrounded by the grid structure. The color filter element is aligned with the photodiode component. |
| US10164154B2 |
Semiconductor light emitting device
The present invention provides a semiconductor light emitting device with a simple structure and capable of improving light extraction efficiency. The semiconductor light emitting device 1 includes a substrate 2, a metal layer 3 on the substrate 2, a light-transmitting conductive layer 4 on the metal layer 3, an insulation layer 30 on the light-transmitting conductive layer 4, and a III-V semiconductor structure 5 on the insulation layer 30. The III-V semiconductor structure 5 includes a light emitting layer 8, a p-type semiconductor layer 9, and an n-type semiconductor layer 10. A refractive index n1 of a p-type GaP contact layer 11 of the p-type semiconductor layer 9, a refractive index n2 of the insulation layer 30, and a refractive index n3 of the light-transmitting conductive layer 4 satisfy the relation: n1>n2 |
| US10164149B1 |
LED panel
An LED panel is disclosed. The LED panel includes LED chips and a mount substrate on which the LED chips are mounted by flip bonding. Each of the LED chips includes a sapphire substrate, a plurality of light emitting cells disposed below the sapphire substrate, and an etched portion formed between the plurality of light emitting cells. Each of the LED chips includes a plurality of color cells formed corresponding to the plurality of light emitting cells on the sapphire substrate to change or maintain the color of light from the corresponding light emitting cells and a plurality of light collecting portions formed corresponding to the plurality of light emitting cells and the plurality of color cells on the bottom surface of the substrate and adapted to collect light from the corresponding light emitting cells on the corresponding color cells. |
| US10164144B2 |
Bond and release layer transfer process
Embodiments transfer thin layers of material utilized in electronic devices (e.g., GaN for optoelectronic devices), from a donor to a handle substrate. Certain embodiments employ bond-and-release system(s) where release occurs along a cleave plane formed by implantation of particles into the donor. Some embodiments may rely upon release by converting components from solid to liquid under carefully controlled thermal conditions (e.g., solder-based materials and/or thermal decomposition of Indium-containing materials). Some embodiments utilize laser-induced film release processes using epitaxially grown or implanted regions as an optically absorptive region. A single bond-and-release sequence may involve processing an exposed N-face of GaN material. Multiple bond-and-release sequences (involving processing an exposed Ga-face of GaN material) may be employed in series, for example utilizing a temporary handle substrate as an intermediary. Particular embodiments form template blanks of high quality GaN suitable for manufacturing High Brightness-Light Emitting Diode (HB-LED) devices. |
| US10164142B2 |
Flip chip light emitting diode and method of manufacturing the same
A flip chip light emitting diode includes a semiconductor layer comprising an epitaxial layer an N-semiconductor layer, a light active layer and a P-semiconductor layer arranged from top to bottom in series. A first electrode mounted on the semiconductor layer. A second electrode mounted on the semiconductor layer. A insulating layer mounted on the semiconductor layer. The N-semiconductor layer protrudes away from the epitaxial layer to form a protruding portion. The light active layer and the P-semiconductor layer mounts on the protruding portion in series. The insulating layer mounts between the first electrode and the protruding portion, the light active layer, the P-semiconductor layer and the second electrode. The flip chip light emitting diode also comprises a supporting portion, the supporting portion is mounted on a top surface of the epitaxial layer by a connecting portion. The connecting portion has same or different materials with the supporting portion. |
| US10164140B2 |
Modular self-tracking micro-concentrator for space power
Technologies for a micro-concentrator modular array. The micro-concentrator modular array may include two or more micro-concentrator solar modules. One or more of the micro-concentrator solar modules may be removable from the micro-concentrator modular array. Micro-concentrator solar modules may be added to a micro-concentrator modular array. One or more of the micro-concentrator solar modules may be electrically and/or mechanically connected to other micro-concentrator solar modules. To facilitate an electrical connection, a conductive connector may be used to connect an electrical output of one micro-concentrator solar module with an electrical input of another micro-concentrator solar module. |
| US10164138B2 |
Photovoltaic module
Photovoltaic module with a negative terminal (5) and a positive terminal (6), and a parallel connection (3, 4) of m sub-modules (2) connected to the negative and the positive terminal (5, 6) of the photovoltaic module (1). Each of the m sub-modules (2) has a string of n series-connected back-contact cells (9), wherein the n cells (9) of each sub-module (2) are arranged in an array. The parallel connection (3, 4) and connections (8) for each string of n series-connected back contact cells (9) are provided in a back conductive sheet, and the back conductive sheet comprises designated areas (7) for the parallel connection (3, 4), corresponding to edge parts of each corresponding sub-module (2). |
| US10164134B2 |
Optoelectronic semiconductor chip
An optoelectronic semiconductor chip is disclosed. In an embodiment the chip includes an active zone with a multi-quantum-well structure, wherein the multi-quantum-well structure comprises multiple quantum-well layers and multiple barrier layers, which are arranged sequentially in an alternating manner along a growth direction, wherein the multi-quantum-well structure has at least one emission region and multiple transport regions which are arranged sequentially in an alternating manner in a direction perpendicular to the growth direction, wherein at least one of the quantum-well layers and the barrier layers are thinner in the transport regions than in the emission regions, and wherein the quantum-well layers in the transport regions and in the emission regions are oriented perpendicularly to the growth direction with exception of a junction region between adjacent transport regions and emission regions. |
| US10164132B2 |
Composite station and method of drilling and fixing for the continuous production of a conductive backsheet with an integrated encapsulating and dielectric layer, for photovoltaic panels of the back-contact type
Composite operating station and method of drilling and fixing for the continuous production of conductive backsheets with an integrated encapsulating and dielectric layer, for photovoltaic panels of the back-contact type. The composite operating station is automated and integrates a plurality of working processes carried out simultaneously in a cyclic sequence. In particular, it is based on a multifunction cylindrical roller which by rotating lays out the film of integrated encapsulating and dielectric material, heats it and presses it on the conductive layer of the supporting backsheet for the purpose of the fixing in a correct position, the roller being provided with openings to enable drilling from outside with a laser device and also to enable the forced suction from inside of the fumes and of the residues by means of an exhaust fan. |
| US10164129B2 |
Solar cell
Discussed is a solar cell including a substrate having a first conductivity type; an emitter layer including a plurality of finger lines connected with an emitter layer; a plurality of rear finger lines connected with a back surface field, wherein the emitter layer includes first areas in contact with the plurality of front finger lines and second areas positioned between the plurality of front finger lines and having a lower doping concentration than that of the first areas, the back surface field includes areas in contact with the plurality of rear finger lines, and the number of the plurality of rear finger lines positioned on a rear surface of the substrate and the number of the plurality of front finger lines positioned on a front surface of the substrate are different. |
| US10164128B2 |
Composition for solar cell electrodes and electrode fabricated using the same
A composition for solar cell electrodes includes silver powder; a silver alloy (AgX) that includes silver (Ag) and a metal (X), the silver alloy having a eutectic point of about 150° C. to about 900° C.; a glass frit; and an organic vehicle. |
| US10164126B2 |
Junction barrier schottky diode with enhanced surge current capability
A semiconductor power rectifier with increased surge current capability is described. A semiconductor layer includes a drift layer having a first conductivity type, at least one pilot region having a second conductivity type different from the first conductivity type, a plurality of stripe-shaped emitter regions having the second conductivity type, and a transition region having the second conductivity type, wherein the at least one pilot region has in any lateral direction parallel to the first main side a width of at least 200 μm and is formed adjacent to the first main side to form a first p-n junction with the drift layer, each emitter region is formed adjacent to the first main side form a second p-n junction with the drift layer, and the transition region is formed adjacent to the first main side to form a third p-n junction with the drift layer. |
| US10164122B2 |
Semiconductor device with transition metal dichalocogenide hetero-structure
A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor. |
| US10164114B2 |
FinFETs and methods of forming FinFETs
An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact. |
| US10164113B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer. |
| US10164112B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate; at least one source/drain feature at least partially disposed in the substrate; an isolation structure disposed on the substrate and includes a first portion; a gate structure disposed on the first portion of the isolation structure and adjacent to the source/drain feature; and at least one gate spacer disposed on a sidewall of the gate structure, in which a top surface of the first portion of the isolation structure is in contact with the gate structure and is higher than a bottommost surface of the gate spacer. |
| US10164111B2 |
Semiconductor device and methods of manufacture
A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material. |
| US10164110B2 |
Finfet including improved epitaxial topology
A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins. |
| US10164109B2 |
Fin field effect transistor (FinFET) device and method for forming the same
A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure. |
| US10164108B2 |
Fin field effect transistor (FinFET) device and method for forming the same
A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure. |
| US10164100B2 |
Formation method and structure semiconductor device with source/drain structures
Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion. |
| US10164099B2 |
Device with diffusion blocking layer in source/drain region
One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration. |
| US10164097B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structures, and a plurality of epitaxy structures. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structures are respectively disposed on the semiconductor fins. The epitaxy structures are separated from each other, and at least one of the epitaxy structures has a substantially round profile. |
| US10164094B2 |
Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof
A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer. |
| US10164093B2 |
Semiconductor device including an epitaxy region
An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench. |
| US10164084B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes: an n+-type drain region made of a wide-bandgap semiconductor material; an n-type epitaxial layer provided on the top surface of the drain region; an n-type first semiconductor region provided at an upper portion of the epitaxial layer and having a higher impurity concentration than the epitaxial layer; an n-type second semiconductor region provided on the first semiconductor region and having a higher impurity concentration than the first semiconductor region; p-type base regions surrounding to include an upper portion in the middle of the second semiconductor region; n-type source regions provided at upper portions of the base regions to form a channel; and a gate electrode which controls a surface potentials of the channels. |
| US10164083B2 |
Silicon carbide semiconductor device and manufacturing method therefor
A silicon carbide semiconductor device includes an ohmic electrode and a Schottky electrode that are in contact with the drain electrode respectively on the drain electrode and are next to each other; a first conductivity type first withstand voltage holding region in contact with the ohmic electrode on the ohmic electrode; a second conductivity type second withstand voltage holding region in contact with the Schottky electrode on the Schottky electrode and is next to the first withstand voltage holding region; a second conductivity type well region in contact onto the first and second withstand voltage holding regions; a first conductivity type source region selectively provided on a surface layer of the well region; and a gate electrode opposite to a channel region defined by the well region sandwiched between the source region and the first withstand voltage holding region, with a gate oxide film interposed therebetween. |
| US10164080B2 |
Electrode pair, method for fabricating the same, substrate for device, and device
Art electrode pair enables the performance of a device to be accurately delivered, a method for manufacturing the same. An electrode pair 10, wherein one electrode 12A and the other electrode 12B are provided on the same plane so as to face each other with a gap 17 therebetween, and portions of the one electrode 12A and the oilier electrode 12B facing each other are respectively curved so as to get away from the plane along a direction nearing each other. This electrode pair 10 is manufactured by preparing, as a sample, a substrate on which a pair of seed electrodes is formed with a space therebetween so as to have an initial gap, immersing the sample in an electroless plating solution, changing the electroless plating solution after a lapse of a certain period of time, and adjusting the number of times of changing. |
| US10164077B2 |
Magnetic majority gate device
The disclosed technology relates generally to spintronics, and more particularly to a magnetic majority gate device. In one aspect, a magnetic majority gate device includes a magnetic propagation layer and at least one input transducer. The magnetic propagation layer includes a plurality of magnetic buses configured to guide propagating magnetic domain walls along longitudinal directions corresponding to elongated directions of the magnetic buses. The plurality of magnetic buses includes a plurality of input magnetic buses, where each of the input magnetic buses has a corresponding input site configured to receive a corresponding input magnetic domain wall. At least one input transducer at a corresponding input site is configured to convert a digital input electrical signal into an input magnetic domain wall, such that a magnetization state of the input magnetic domain wall corresponds to a digital logic state of the digital input electrical signal. The at least one input transducer is configured to inject an in-plane electrical current into the corresponding input magnetic bus if the digital logic state is a predetermined digital logic state. The magnetic propagation layer includes a central region at which the magnetic buses converge and are joined together, such that the central region is configured for an interaction of input magnetic domain walls guided by two or more magnetic buses. The central region includes at least one magnetic constriction configured to locally restrict propagation of propagating magnetic domain walls. |
| US10164072B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions. |
| US10164068B2 |
FinFET structure and method for fabricating the same
A method comprises removing a portion of a fin to form a trench over a lower portion of the fin, wherein the lower portion is formed of a first semiconductor material, growing a second semiconductor material in the trench to form a middle portion of the fin, forming a first carbon doped layer over the middle portion of the fin, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin, replacing outer portions of the upper portion of the fin with a second carbon doped layer and drain/source regions, wherein the first carbon doped layer and the second carbon doped layer are separated by the upper portion of the fin and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer. |
| US10164064B2 |
FinFETs with low source/drain contact resistance
An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion. |
| US10164060B2 |
Work function metal fill for replacement gate fin field effect transistor process
A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse. |
| US10164059B2 |
FinFET device and fabricating method thereof
A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion. |
| US10164058B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided. |
| US10164056B2 |
Vertical field effect transistors with uniform threshold voltage
Provided is a method for forming a semiconductor structure. In one or more embodiments of the invention, the method includes forming a semiconductor fin on a substrate and decreasing a width of the semiconductor fin. The method further includes forming a spacer layer on a surface of the substrate and forming a high dielectric constant layer on exposed surfaces of the semiconductor fin and the spacer layer. The method also includes forming a work function metal layer on the high dielectric constant layer. The method also includes removing portions of the work function metal layer and the high dielectric constant layer to expose portions of the spacer layer. A thickness of the remaining work function metal layer on sidewalls of the semiconductor fin is uniform. |
| US10164054B2 |
Compound semiconductor field effect transistor with self-aligned gate
A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate. |
| US10164051B2 |
Method of cutting metal gate
A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate, forming a first metal-gate line over a first and a second gate regions, applying a first line-cut to separate the first metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming a second metal-gate line over the first sub-metal gate line and the second sub-metal gate line, applying a second line-cut to separate the second metal-gate line into a third sub-metal gate line and a fourth sub-metal gate line such that a gap is formed between the third sub-metal gate line and the fourth sub-metal gate line and forming an isolation region within the gap. |
| US10164050B2 |
Structure and formation method of semiconductor device structure with gate stack
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate. |
| US10164049B2 |
Structure and formation method of semiconductor device with gate stack
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate. |
| US10164047B2 |
High electron mobility transistor structure
A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided. |
| US10164046B2 |
Method for manufacturing semiconductor structure
A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess. |
| US10164042B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer. |
| US10164040B2 |
Gate structure and method for fabricating the same
A method comprises doping a lower portion of a nanowire to form a first drain/source region, wherein the nanowire is formed over a substrate, doping an upper portion of the nanowire to form a second drain/source region, doping a middle portion of the nanowire to form a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, forming a ring-shaped gate structure surrounding a lower portion of the channel region, wherein the ring-shaped gate structure comprises a vertical portion of a first work-function metal layer and depositing a low-resistivity gate metal layer over a horizontal portion of the first work-function metal layer, wherein the low-resistivity gate metal layer is electrically coupled to the vertical portion of the first work-function metal layer through the horizontal portion of the first work-function metal layer. |
| US10164038B2 |
Method of implanting dopants into a group III-nitride structure and device formed
A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material. |
| US10164028B2 |
Thin film transistor, manufacturing method therefor, oxide back plate and display apparatus
Provided are a thin film transistor, a manufacturing method therefor, an oxide back plate and a display apparatus. The thin film transistor comprises: an oxide active layer (4) and source and drain electrodes (6a, 6b) connected to the oxide active layer (4), wherein the source and drain electrodes (6a, 6b) comprise a main portion (M) and a connective portion (C), the main portion (M) being isolated from the active layer (4), and being electrically connected to the active layer (4) via the connective portion (C), and an electrical resistivity of the connective portion (C) is greater than that of the main portion (M). In the thin film transistor provided above, since the main portions of the source and drain electrodes are not in contact with the oxide active layer, a metal with a relatively high electrical conductivity can be used as the source and drain electrodes, without having a relatively great impact on the electrical performance of the oxide active layer. |
| US10164025B2 |
Semiconductor device having termination trench
A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure. |
| US10164020B2 |
Semiconductor device and method manufacturing the same
A semiconductor device may include an n− type layer disposed at a first surface of an n+ type silicon carbide substrate; a p− type region, a p type region, an n+ type region, and a p+ type region disposed at an upper portion in the n− type layer; a gate electrode and a source electrode disposed on the n− type layer and insulated from each other; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the source electrode is in contact with the p− type region, the n+ type region, and the p+ type region, and the source electrode may include an ohmic junction region disposed at a contact portion of the source electrode and the n+ type region and the contact portion of the source region and the p+ type region and a Schottky junction region disposed at the contact portion of the source electrode and the p− type region. |
| US10164015B2 |
Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced. |
| US10164011B2 |
Nitride semiconductor device
A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess. |
| US10164010B1 |
Finfet diffusion break having protective liner in fin insulator
Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator. |
| US10164003B2 |
MIM capacitor and method of forming the same
A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant. |
| US10163999B2 |
Display device
A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion. |
| US10163994B2 |
OLED panel manufacturing method and OLED panel
The invention provides an OLED panel manufacturing method and OLED panel. The method comprises: forming first (21) and second (22) pixel electrodes inside each pixel unit (2); depositing an insulation film by an atomic layer deposition method, and patternizing to form a pixel electrode isolation insulation layer (3); the pixel electrode isolation insulation layer having a longitudinal portion (31) filling between the first (21) and second (22) pixel electrodes, and a latitudinal portion (32) having both ends covering respectively a part of the first pixel electrode (21) closer to the second pixel electrode (22) and a part of the second pixel electrode (22) closer to the first pixel electrode (21); forming a pixel isolation layer (4), and printing LOED elements (5); the invention can increase OLED panel resolution without changing printing accuracy so that the first (21) and second (22) pixel electrodes are completely insulated. |
| US10163992B2 |
Large area mirror display and method of manufacturing the same
A mirror display device includes a mirror module and a display module. The mirror module includes a transparent substrate and a plurality of first mirror patterns. The transparent substrate has a first region and a second region adjacent to the first region. The first mirror patterns are disposed on a surface of the transparent substrate in the first region. The display module includes a display part that emits a light and a plurality of second mirror patterns. The display module is combined with the mirror module on the surface of the transparent substrate in the second region. |
| US10163989B2 |
Display device and electronic device
A display device that has an excellent visibility even under strong light is provided. In the display device, a first display element that reflects visible light and a second display element that emits visible light are between a first substrate and a second substrate. The display device can display an image with high visibility by operating the first display element under strong light and operating the second display element under weak light. Furthermore, a first surface of the second substrate is provided with a touch sensor, and a second surface opposite to the first surface is provided with an anti-reflection layer. Such a structure can sufficiently reduce reflection of external light on the display surface under strong light, further increasing the visibility. |
| US10163988B2 |
Light-emitting apparatus, method for forming light-emitting apparatus, and display apparatus
The present invention provides a light-emitting apparatus, a method for forming a light-emitting apparatus, and a display apparatus. The light-emitting apparatus comprises at least one OLED light-emitting unit and at least one quantum dot light-emitting unit, wherein the at least one quantum dot light-emitting unit and the at least one OLED light-emitting unit are arranged in series. |
| US10163987B2 |
Display device and manufacturing method of a display device
A manufacturing method of a display device according to an embodiment of the present invention includes: the display device including a protection plate having a light transmitting part facing an input or output device, and a display substrate having a display area, a light emitting film forming the step of forming an island-like light emitting film containing a light emitting material, in an area other than the display area in the display substrate; an alignment step of aligning the protection plate and the display substrate with each other; and an attaching step of attaching the protection plate to the display substrate. |
| US10163985B2 |
Subpixel arrangement structure for display device
A subpixel arrangement structure for a display device includes a plurality of unit pixels each having a red subpixel, a green subpixel, and a blue subpixel. The red, green, and blue subpixels form a delta arrangement. Green subpixels are disposed on a plurality of first subpixel arrangement lines, each of which extends along a direction of a first axis. Two red subpixels and two blue subpixels are alternately disposed along the first axis direction on a plurality of second subpixel arrangement lines. Each of the plurality of second subpixel arrangement lines is positioned between every two of the plurality of first subpixel arrangement lines and extends along the first axis direction. |
| US10163984B1 |
Display with embedded components and subpixel windows
A display may have an array of pixels. Each pixel may have a light-emitting diode such as an organic light-emitting diode. The organic light-emitting diodes may each have an anode that is coupled to a thin-film transistor pixel circuit for controlling the anode. Transparent windows may be formed in the display. The windows may be formed by replacing subpixels in some of the pixels with transparent windows. When subpixels are replaced by transparent windows, adjacent subpixels may be overdriven to compensate for lost light from the replaced subpixels. Adjacent subpixels may also be enlarged to help compensate for lost light. An array of electrical components such as an array of light sensors may be aligned with the transparent windows and may be used to measure light passing through the transparent windows. |
| US10163983B1 |
Complementary resistance switchable filler and nonvolatile complementary resistance switchable memory comprising the same
A resistance-switchable material containing: an insulating support; and a complementary resistance switchable filler dispersed in the insulating support, wherein the complementary resistance switchable filler has a core-shell structure containing: a wire-type conductive core containing a conductive material; and an insulating shell formed on the surface of the core and containing an insulating material. Because a first resistive layer, a conductive layer and a second resistive layer are formed as one layer and bipolar conductive filaments are formed on the substantially different resistive layers, the memory can exhibit complementary resistive switching characteristics. In addition, the complementary resistance switchable memory of the present disclosure can be prepared through a simplified process at low cost by introducing a simple process of coating a paste in which a complementary resistance switchable filler and a supporting material are mixed. |
| US10163980B2 |
Resistive memory array and fabricating method thereof
A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure. |
| US10163978B2 |
Memory cell with independently-sized elements
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element. |
| US10163977B1 |
Chalcogenide memory device components and composition
Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium. |
| US10163975B2 |
Light emitting apparatus
A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part. |
| US10163972B2 |
Image sensing device with photon blocking layer and anti-reflective coating
A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer. |
| US10163971B2 |
Image sensor, image capturing apparatus, and forming method
An image sensor comprising a plurality of pixels, each of at least part of the plurality of pixels comprises: a plurality of photoelectric conversion parts; a microlens; and a plurality of interlayer lenses formed between the plurality of photoelectric conversion parts and the microlens and integrally formed to correspond to the plurality of photoelectric conversion parts. The plurality of interlayer lenses cause light incident on the plurality of interlayer lenses to enter the corresponding plurality of photoelectric conversion parts. |
| US10163969B2 |
X-ray sensor and method of manufacturing the same
This invention relates to a direct conversion X-ray sensor and to a method of manufacturing the same. This X-ray sensor includes an array substrate including a pixel electrode formed so as to protrude from a surface thereof at a pixel region; a photoconductive substrate including an upper electrode, and a photoconductive layer formed on a surface of the upper electrode so as to be in contact with the pixel electrode and having a PIN diode structure; and a bonding material filling a space around a contact region of the pixel electrode and the photoconductive layer so as to bond the array substrate and the photoconductive substrate. |
| US10163968B2 |
Multi-junction pixel image sensor with dielectric reflector between photodetection layers
Some embodiments provide a color image sensor and color image sampling method that uses multiple-layer pixels and is capable of producing color images without using absorption color filters (e.g., such as employed in conventional CFAs). In accordance with some embodiments of the color image sensor device and color image sampling method, frequency-dependent reflectors are incorporated between the photodetection layers of multiple-layer (e.g., two layer) pixels. |
| US10163964B2 |
Solid-state imaging element, imaging device, and electronic device
The present technology relates to a solid-state imaging element, an imaging device, and an electronic device that can improve transfer efficiency of a charge accumulation unit (MEM) and can increase the number of saturation electrons Qs. In a case where a charge voltage conversion unit (FD) is connected to a center of a charge accumulation unit (MEM) in each pixel and pixels are arrayed in an array, a column in which photoelectric conversion units (PD) are arrayed and a column including charge voltage conversion units (FD) and pixel transistors are arrayed in parallel. The present technology can be applied to a CMOS image sensor. |
| US10163959B2 |
Image sensor and method for manufacturing the same
An image sensor structure and a method for forming the same are provided. The image sensor structure includes a substrate having a front side and a backside and a light-sensing region formed in the substrate. The image sensor structure further includes a front side isolation structure formed at the front side of the substrate and a backside isolation structure formed at the back side of the substrate. |
| US10163951B2 |
Image sensor device
In some embodiments, the present disclosure relates to an image sensor device. The image sensor device has an isolation well region surrounding a photodetector arranged within a substrate at a first depth. A gate stack is arranged over the isolation well region along a first surface of the substrate. The gate stack defines an edge. A doped isolation feature is arranged within the substrate at a second depth between the isolation well region and the gate stack. The gate stack is vertically over an active area. The doped isolation feature extends from the edge of the gate stack to under the gate stack. |
| US10163947B2 |
Photodiode gate dielectric protection layer
In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer. |
| US10163945B2 |
Printable device wafers with sacrificial layers
Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer. |
| US10163937B2 |
Pixel structure and fabricating method thereof
A pixel structure includes a scan line, a data line, a bump, an active device, and a pixel electrode electrically connected to the active device. The active device includes a gate, a semiconductor layer, a gate insulation layer between the gate and the semiconductor layer, a source, and a drain. The bump has a top surface and side surfaces in periphery of the top surface. The gate covers the bump and electrically connects the scan line. The semiconductor layer is on the top surface and the side surfaces. The source is on at least one of the side surfaces, in contact with the semiconductor layer, and electrically connected to the data line. The drain is on the top surface and in contact with the semiconductor layer, and the drain does not cover the semiconductor layer on a corner section of the bump between the top surface and the side surfaces. |
| US10163934B2 |
Fully-depleted silicon-on-insulator transistors
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage. |
| US10163932B1 |
Memory device based on heterostructures of ferroelectric and two-dimensional materials
A ferroelectric random-access memory structure and processes for fabricating a ferroelectric random-access memory structure are described that includes using a molybdenum sulfide layer. In an implementation, a ferroelectric random-access memory structure in accordance with an exemplary embodiment includes at least one FeFET, which further includes a substrate; a back gate electrode formed on the substrate, the back gate electrode including a conductive layer; a gate dielectric substrate formed on the back gate electrode; a source electrode formed on the gate dielectric substrate; a drain electrode formed on the gate dielectric substrate; and a layered transition metal dichalcogenide disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode. |
| US10163928B2 |
Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described. |
| US10163925B2 |
Integrated circuit device
An integrated circuit device includes a first and a second semiconductor regions, a first electrode provided above the first semiconductor region, a second electrode provided above the second semiconductor region, a first and a second interconnects. The first and the second semiconductor regions are arranged to be separated from each other in a first direction. Longitudinal directions of the first and second semiconductor regions are a second direction. Longitudinal directions of the first and second electrode are a third direction. The first and second interconnects extend in the first direction and are provided in a region including a region directly above the first electrode and a region directly above the second electrode. The first interconnect is connected to the first electrode. The second interconnect is connected to the second electrode. |
| US10163922B2 |
Semiconductor device and method of manufacturing the semiconductor device
In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film. |
| US10163920B2 |
Memory device and memory cell
A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate. |
| US10163918B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns. |
| US10163916B2 |
Compact anti-fuse memory cell using CMOS process
A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N-well, an oxide layer deposited on the N-well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region. |
| US10163914B2 |
Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails
A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process. |
| US10163904B1 |
Semiconductor device structure
A semiconductor device structure is provided. The semiconductor device structure includes a first circuit, a second circuit, and a dielectric dummy gate over a substrate. The first circuit includes a first N-type fin field-effect transistor (FinFET) and a first P-type fin field-effect transistor (FinFET). The second circuit includes a second N-type fin field-effect transistor (FinFET) and a second P-type fin field-effect transistor (FinFET) beside the second N-type FinFET. The dielectric dummy gate is positioned on a common boundary portion shared by the first circuit and the second circuit. The dielectric dummy gate includes a first portion and a second portion. The first portion is positioned between the first N-type FinFET and the second N-type FinFET and formed of a first strain material. The second portion is positioned between the first P-type FinFET and the second P-type FinFET and formed of a second strain material. |
| US10163898B2 |
FinFETs and methods of forming FinFETs
An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure. |
| US10163897B2 |
Inter-level connection for multi-layer structures
Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer. |
| US10163896B2 |
Integrated circuit having a MOM capacitor and method of making same
An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor. |
| US10163893B1 |
Apparatus containing circuit-protection devices
Apparatus including an array of memory cells may include circuit-protection devices that may include first and second circuit-protection units, a first gate having a first source/drain connected to a first node of the first circuit-protection unit, and a second gate having a first source/drain connected to a first node of the second circuit-protection unit, wherein a second source/drain of the first gate is connected to a second source/drain of the second gate. |
| US10163892B2 |
Silicon controlled rectifiers (SCR), methods of manufacture and design structures
Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well. |
| US10163890B2 |
Semiconductor device
A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode. |
| US10163889B2 |
Phase shifter
A phase shifter includes a signal input, a signal output, an ESD protection circuit, first and second signal paths between the signal input and the signal output. The ESD protection circuit includes first and second two port devices, each two port device being switchable between a high impedance state and a low impedance state. The first signal path includes the first two port device of the ESD protection circuit and a first delay line configured to provide a first phase shift to a signal transmitted from the signal input to the signal output via the first signal path. The second signal path includes the second two port device of the ESD protection circuit and a second delay line configured to provide a second phase shift, different from the first phase shift, to the signal transmitted from the signal input to the signal output via the second signal path. |
| US10163888B2 |
Self-biased bidirectional ESD protection circuit
Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation. |
| US10163887B2 |
Method and structure for semiconductor mid-end-of-line (MEOL) process
A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers. |
| US10163886B2 |
Strapping structure of memory circuit
A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer. |
| US10163884B1 |
Cell architecture with intrinsic decoupling capacitor
An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors. |
| US10163882B2 |
Semiconductor device and layout thereof
A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat. |
| US10163880B2 |
Integrated circuit and method of fabricating the same
A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced. |
| US10163877B2 |
System in package process flow
A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate. |
| US10163876B2 |
Semiconductor structure and manufacturing method thereof
A method of manufacturing a structure includes: providing a substrate; forming an adhesive layer over the substrate; forming an interconnect layer comprising a metal line and a metal via over the adhesive layer; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the first semiconductor die being spaced apart from the conductive pillars; bonding a second semiconductor die with the conductive pillars; and removing the substrate and the adhesive layer to expose a conductive portion of the interconnect layer. |
| US10163875B2 |
Method for forming chip package structure with adhesive layer
A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back surface opposite to the front surface. The back surface is in direct contact with the adhesive layer. A first maximum length of the adhesive layer is less than a second maximum length of the chip. The method includes forming a molding compound layer surrounding the chip and the adhesive layer. A first bottom surface of the adhesive layer is substantially coplanar with a second bottom surface of the molding compound layer. The method includes forming a redistribution structure over the chip and the molding compound layer. |
| US10163873B2 |
Package-on-package (PoP) device with integrated passive device in a via
A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor. |
| US10163869B2 |
Transferring method, manufacturing method, device and electronic apparatus of micro-LED
The present invention discloses a transferring method, a manufacturing method, a device and an electronics apparatus of micro-LED. The method for transferring micro-LED at wafer level comprises: temporarily bonding micro-LEDs on a laser-transparent original substrate onto a carrier substrate via a first bonding layer; irradiating the original substrate with laser, to lift-off selected micro-LEDs; performing a partial release on the first bonding layer, to transfer the selected micro-LEDs to the carrier substrate; temporarily bonding the micro-LEDs on the carrier substrate onto a transfer head substrate via a second bonding layer; performing a full release on the first bonding layer, to transfer the micro-LEDs to the transfer head substrate; bonding the micro-LEDs on the transfer head substrate onto a receiving substrate; and removing the transfer head substrate by releasing the second bonding layer, to transfer the micro-LEDs to the receiving substrate. |
| US10163867B2 |
Semiconductor package and manufacturing method thereof
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof. |
| US10163866B2 |
Semiconductor device and method of manufacture
A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package. |
| US10163864B1 |
Vertically stacked wafers and methods of forming same
The disclosure is directed to an integrated circuit stack and method of forming the same. In one embodiment, the integrated circuit stack may include: a plurality of vertically stacked wafers, each wafer including a back side and a front side, the back side of each wafer including a through-semiconductor-via (TSV) within a substrate, and the front side of each wafer including a metal line within a first dielectric, wherein the metal line is connected with the TSV within each wafer; and an inorganic dielectric interposed between adjacent wafers within the plurality of vertically stacked wafer; wherein the plurality of vertically stacked wafers are stacked in a front-to-back orientation such that the TSV on the back side of one wafer is electrically connected to the metal line on the front side of an adjacent wafer by extending through the inorganic dielectric interposed therebetween. |
| US10163863B2 |
Recessed and embedded die coreless package
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands. |
| US10163861B2 |
Semiconductor package for thermal dissipation
A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks. |
| US10163858B1 |
Semiconductor packages and manufacturing methods thereof
Semiconductor packages and manufacturing methods thereof are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer. |
| US10163855B2 |
Semiconductor device and manufacturing method thereof
An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices. |
| US10163853B2 |
Formation method of chip package
Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes forming a package layer to surround the first chip structure and the second chip structure after the formation of the release film. In addition, the method includes removing the release film such that the top surface of the first chip structure, the top surface of the second chip structure, and a top surface of the package layer are exposed. |
| US10163851B2 |
Tri-layer CoWoS structure
A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die. |
| US10163850B2 |
Semiconductor device
A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film. |
| US10163848B2 |
Semiconductor package
A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing. |
| US10163847B2 |
Method for producing semiconductor package
A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump. |
| US10163845B2 |
Method and apparatus for measuring a free air ball size during wire bonding
Disclosed is a method of measuring a free air ball size during a wire bonding process of a wire bonder, which comprises a position sensor and a bonding tool for forming an electrical connection between a semiconductor device and a substrate using a bonding wire. Specifically, the method comprises the steps of: forming a free air ball from a wire tail of the bonding wire; using the position sensor to determine a positional difference between a first and a second position of the bonding tool with respect to a reference position, wherein the first position of the bonding tool is a position of the bonding tool with respect to the reference position when the free air ball contacts a conductive surface; and measuring the free air ball size based on the positional difference of the bonding tool as determined by the position sensor. A wire bonder configured to perform such a method is also disclosed. |
| US10163843B2 |
Semiconductor device structure and manufacturing method
A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature. |
| US10163840B2 |
Methods of fluxless micro-piercing of solder balls, and resulting devices
A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure. |
| US10163839B2 |
Bump on pad (BOP) bonding structure in semiconductor packaged device
The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. |
| US10163833B2 |
Multichip modules and methods of fabrication
In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties. |
| US10163827B1 |
Package structure with protrusion structure
A package structure is provided. The package structure includes a dielectric layer formed over a first substrate and a conductive layer formed in the dielectric layer. The package structure includes an under bump metallurgy (UBM) layer formed over the dielectric layer, and the UBM layer is electrically connected to the conductive layer. The package structure also includes a first protrusion structure formed over the UBM layer, and the first protrusion structure extends upward away from the UBM layer. The package structure further includes a second protrusion structure formed over the UBM layer, and the second protrusion structure extends upward away from the UBM layer. The package structure includes a first conductive connector formed over the first protrusion structure; and a second conductive connector formed over the second protrusion structure. An air gap is formed between the first protrusion structure and the second protrusion structure. |
| US10163824B2 |
Integrated fan-out package and method of fabricating the same
An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided. |
| US10163822B2 |
Chip-on-substrate packaging on carrier
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies. |
| US10163818B2 |
Package structure and method for forming the same
A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer. |
| US10163816B2 |
Structure and formation method of chip package with lid
Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate. The chip package also includes a lid over the semiconductor die. The lid has a number of support structures bonded with the substrate, and the lid has one or more openings between two of the support structures. |
| US10163813B2 |
Chip package structure including redistribution structure and conductive shielding film
A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a grounding line in the dielectric structure. The grounding line includes a main portion and an end enlarged portion connected to the main portion and laterally accessible from the dielectric structure. The chip package structure includes a chip structure over the redistribution structure. The chip package structure includes a conductive shielding film disposed over the chip structure and a first sidewall of the end enlarged portion. The conductive shielding film is electrically connected to the grounding line. A thickness of the end enlarged portion increases from the main portion to the conductive shielding film. |
| US10163812B2 |
Device having substrate with conductive pillars
A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up over and electrically coupled to at least one of the conductive structures. An integrated circuit is disposed over the first surface and electrically coupled to the conductive structures. A molding compound is formed over the first surface of the substrate. |
| US10163811B2 |
Semiconductor package structure based on cascade circuits
A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet. A side of the supporting sheet away from the conductive surface is fixed to the cavity of the shell. |
| US10163810B2 |
Electromagnetic interference shielding for system-in-package technology
Embodiments are generally directed to electromagnetic interference shielding for system-in-package technology. An embodiment of a system-in-package includes a substrate; chips and components attached to the substrate; dielectric molding over the chips and components; and an electromagnetic interference (EMI) shield. The EMI shield formed from a conductive paste, and the EMI shield provides a combined internal EMI shield between chips and components of the system in package and external EMI shield for the system-in-package. |
| US10163809B2 |
Shielding for through-silicon-via noise coupling
In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring. |
| US10163808B2 |
Module with embedded side shield structures and method of fabricating the same
A module includes a circuit package and a top external shield layer. The circuit package includes multiple electronic components on a substrate; at least one side shield structure located at a corresponding at least one side edge region of the circuit package and electrically connected to ground, the at least one side shield structure being positioned on the substrate or on a pad on the substrate; and a molded compound disposed over the substrate, the electronic components, and the at least one side shield structure. The top external shield layer is disposed on a top outer surface of the circuit package and is electrically connected to ground. The at least one side shield structure and the top external shield layer provide an external shield of the module configured to protect the circuit package from external electromagnetic radiation and environmental stress. |
| US10163807B2 |
Alignment pattern for package singulation
A method includes forming an alignment pattern over an insulating layer formed over a carrier. A die is mounted over the carrier and encapsulated. Connectors are formed and the structure is attached to a debond tape. The carrier is removed. A cutting device is aligned to a backside of the insulating layer using the alignment pattern. The first insulating layer and encapsulant are cut from the backside of the insulating layer. Another method includes scanning a backside of a packages structure for an alignment pattern in a first package area of the packages structure. A cutting device is aligned to a cut-line in a non-package area of the packages structure based on the alignment pattern and packages are singulated. An InFO package includes an insulating layer on the backside, the insulating layer having a laser marking thereon. The InFO package also includes an alignment pattern proximate to the insulating layer. |
| US10163804B2 |
Molding structure for wafer level package
A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices. |
| US10163803B1 |
Integrated fan-out packages and methods of forming the same
Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer. |
| US10163797B2 |
Forming interlayer dielectric material by spin-on metal oxide deposition
A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material. |
| US10163794B2 |
Capping layer for improved deposition selectivity
The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for improved reliability. In some embodiments, the integrated chip has a dielectric layer disposed over a semiconductor substrate, and one or more metal layer structures disposed within the dielectric layer. A first capping layer is located over the dielectric layer at positions between the one or more metal layer structures, so that the first capping layer is located along an interface having the one or more metal layer structures interspersed between the first capping layer. A second capping layer is located over the one or more metal layer structures. An etch stop layer is arranged over the first capping layer and the second capping layer and laterally surrounds the second capping layer. |
| US10163790B2 |
Manufacturing method of a semiconductor device and method for creating a layout thereof
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity. |
| US10163786B2 |
Method of forming metal interconnection
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements. |
| US10163783B1 |
Reduced area efuse cell structure
An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing. |
| US10163780B2 |
Wireless charging package with chip integrated in coil center
A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines. |
| US10163778B2 |
Structure and formation method of damascene structure
A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate. The semiconductor device structure further includes a conductive via surrounded by the dielectric layer and electrically connected to the conductive feature. The conductive via has a lower end and an upper end larger than the lower end, and the conductive via has a side surface curved inward. |
| US10163776B2 |
Designing method of capacitive element in multilayer wirings for integrated circuit devices based on statistical process
Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings. |
| US10163772B2 |
Stacked semiconductor device structure and method
A stacked semiconductor device structure includes a first semiconductor device having a first major surface and a second major surface opposite to the first major surface. The second major surface includes a recessed region bounded by sidewall portions, and the sidewall portions have outer surfaces defining peripheral edge segments of the first semiconductor device. A first conductive layer is disposed adjoining at least portions of the recessed region. A second semiconductor device having a third major surface and a fourth major surface opposite to the third major surface includes a first portion that is electrically connected to the first conductive layer within the recessed region, and at least a portion of the second semiconductor device is disposed within the recessed region. |
| US10163771B2 |
Interposer device including at least one transistor and at least one through-substrate via
In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure. |
| US10163770B2 |
Fan-out package structure and method
A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion. |
| US10163768B2 |
Semiconductor structure and method of manufacturing the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar. |
| US10163767B2 |
Semiconductor package
A semiconductor package includes a substrate, a conductive layer, a first surface mount device (SMD) and a bonding wire. The substrate has a t top surface. The first conductive layer is formed on the top surface and has a first conductive element and a first pad separated from each other. The first SMD is mounted on the first pad, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer. |
| US10163760B2 |
Semiconductor device, semiconductor device manufacturing method and semiconductor device mounting structure
A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer. |
| US10163753B2 |
Method for forming interconnect structure of semiconductor device
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer. |
| US10163747B2 |
Semiconductor device and method of controlling warpage in reconstituted wafer
A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate. |
| US10163745B2 |
Package with tilted interface between device die and encapsulating material
A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via. |
| US10163743B2 |
Copper flanged air cavity packages for high frequency devices
An air cavity package includes a flange and a pedestal extending upward from the flange. A dielectric frame is joined to the flange and surrounds the pedestal. The semiconductor die is placed on the pedestal, which reduces the length of the wires joining the die to the leads of the air cavity package. |
| US10163724B2 |
Integrated circuit device and method of manufacturing same
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer. |
| US10163721B2 |
Hybridization fin reveal for uniform fin reveal depth across different fin pitches
A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material. |
| US10163720B2 |
Method of forming source/drain contact
Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material. |
| US10163718B2 |
Semiconductor device and a method for fabricating the same
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer. |
| US10163716B2 |
Symmetric tunnel field effect transistor
The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region. |
| US10163711B2 |
Methods of packaging semiconductor devices including placing semiconductor devices into die caves
Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies. |
| US10163710B2 |
Method of manufacturing semiconductor device by applying molding layer in substrate groove
A method of forming a semiconductor package includes depositing a passivation layer overlying a semiconductor substrate, wherein the semiconductor substrate includes a scribe line region positioned between a first chip region and a second chip region. The method further includes forming a bump overlying the passivation layer on at least one of the first chip region or the second chip region, wherein the bump comprises a copper pillar and a cap layer. The method further includes forming a groove passing through the passivation layer on the scribe line region, wherein the groove extends into the semiconductor substrate to expose a stepped sidewall of the semiconductor substrate. The method further includes applying a molding compound layer to cover the passivation layer and a lower portion of the bump and fill the groove. The method further includes singulating along the scribe line region. |
| US10163708B2 |
Integrated antenna on interposer substrate
Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate. |
| US10163706B2 |
Alignment marks in substrate having through-substrate via (TSV)
A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate. |
| US10163705B2 |
Profile of through via protrusion in 3DIC interconnect
An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner. |
| US10163703B2 |
Method for forming self-aligned contact
A method for forming a self-aligned contact is provided. In an embodiment, a metal gate is formed on a substrate, and a gate spacer is formed adjacent the metal gate. A conductive plug is formed over the substrate, with the gate spacer disposed between the metal gate and the conductive plug. The metal gate and the conductive plug are recessed. A first dielectric layer is deposited over the gate spacer, over the metal gate, over the conductive plug, and along sidewalls of the metal gate. A first opening is formed in the first dielectric layer exposing the metal gate, and a second opening is formed in the first dielectric layer exposing the conductive plug. The first opening and the second opening are filled with a first conductive material. |
| US10163699B2 |
Cu wiring forming method and semiconductor device manufacturing method
A method of forming, on a substrate having on a surface thereof a film having a trench of a preset pattern and a via at a bottom of the trench, a Cu wiring by burying Cu or Cu alloy in the trench and the via includes forming a barrier film (process 2); forming, on a surface of the barrier film, a wetting target layer of Ru or the like (process 3); forming, on a surface of the wetting target layer, a Cu-based seed film by PVD (process 4); filling the via by heating the substrate and flowing the Cu-based seed film into the via (process 5); and forming, on the substrate surface, a Cu-based film made of the Cu or Cu alloy by PVD under a condition where the Cu-based film is flown on the wetting target layer to bury the Cu-based film in the trench (process 6). |
| US10163698B2 |
Interconnect structure and manufacturing method thereof
A method for manufacturing a semiconductor comprises: providing a substrate; forming an opening in a dielectric layer disposed over the substrate; providing a target with a first type atoms; ionizing the first type atoms provided from the target; providing a bias to the substrate for controlling the moving paths of the ionized first type atoms thereby directing the ionized first type atoms in the opening; and forming a first conductive structure from bottom of the opening with the ionized first type atoms under a pre-determined frequency and a pre-determined pressure. |
| US10163696B2 |
Selective cobalt removal for bottom up gapfill
Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The exposed region of cobalt may include an overhang of cobalt on a trench defined on a substrate. The plasma effluents may produce cobalt chloride at the overhang of cobalt. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the overhang of cobalt. |
| US10163692B2 |
Structure and formation method of interconnection structure of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate having a first top surface, and an interconnection line over the first top surface of the substrate. The interconnection line has a sidewall. The semiconductor device structure also includes a first spacer over the sidewall of the interconnection line. The first spacer has a first concave surface which concaves towards the sidewall of the interconnection line. The semiconductor device structure further includes a dielectric layer covering the substrate, the interconnection line and the first spacer. |
| US10163686B2 |
Thermal sensor arrangement and method of making the same
A temperature sensor arrangement in an integrated circuit (IC) includes a sensor array configured to determine a temperature of the IC. The sensor array includes a first transistor having a first terminal, a second terminal and a gate. The temperature sensor array further includes a guard ring region between the sensor array and another circuit of the IC. The guard ring region includes a transistor structure having a first terminal, a second terminal and a gate. The temperature sensor arrangement further includes a thermally conductive element connected to the transistor structure and a first terminal of the first transistor. The thermally conductive element is configured to provide a thermally conductive path from the transistor structure to the first terminal of the first transistor. |
| US10163684B2 |
Fabrication of silicon germanium-on-insulator FinFET
A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration. |
| US10163678B2 |
Sinker with a reduced width
Forming a semiconductor structure by forming a plurality of trenches in a semiconductor material, forming a plurality of non-conductive structures in the plurality of trenches, and forming a doped region of the first conductivity type. The plurality of trenches are spaced apart from each other, have substantially equal depths, and include a first trench and a second trench. The plurality of non-conductive structures include a first non-conductive structure in the first trench and a second non-conductive structure in the second trench. The doped region is formed between the first non-conductive structure and the second non-conductive structure. No region of a second conductivity type lies horizontally in between the first non-conductive structure and the second non-conductive structure. |
| US10163677B2 |
Electrically insulated fin structure(s) with alternative channel materials and fabrication methods
Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure. |
| US10163676B2 |
Apparatus and system for preventing backside peeling defects on semiconductor wafers
A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor. |
| US10163672B2 |
Substrate processing device, method for controlling substrate processing device, and storage medium storing programs
A substrate processing device for processing a substrate, comprising: an image sensor for detecting positions of two corners on at least one diagonal line of a substrate when the substrate is moved to a predetermined position; an illuminating device that can be disposed so as to illuminate the two corners of the substrate on an opposite side of the substrate at the predetermined position to the image sensor; and a control device for determining the position of the substrate, based on the positions of the two corners detected by the image sensor. |
| US10163668B2 |
Thermal dynamic response sensing systems for heaters
A heater system includes a heater assembly, an imaging device and a control system. The heater assembly includes a plurality of heating zones. The imaging device acquires an image of the heater assembly. The control system determines variations in the plurality of heating zones based on the thermal image. |
| US10163667B2 |
Linear wafer drive for handling wafers during semiconductor fabrication
A modular cluster tool is disclosed. According to one embodiment, a system, comprises a wafer transfer station that includes a first vacuum chamber that stores a plurality of semiconductor wafers. The system also includes an equipment front end module interface, and two or more shuttle lock interfaces. |
| US10163666B2 |
Temperature control system for semiconductor manufacturing system
Provided is a temperature control system configured to mix a low temperature heating medium and a high temperature heating medium to supply the heating mediums at a temperature according to a process recipe to an electrostatic chuck (ESC) configured to maintain a temperature and support a wafer in a chamber in which a semiconductor wafer processing process is performed, and a heating medium obtained by mixing a heating medium cooled through a thermoelectric element and a heating medium heated through a heater to a desired target temperature according to a first ratio and a second ratio is provided to a load and recovered from the load, and the heating medium is distributed to the thermoelectric element and the heater according to the first ratio and the second ratio, which are ratios upon the mixing, optimizing power consumption for cooling or heating. |
| US10163664B2 |
Substrate cleaning apparatus and substrate cleaning method
A substrate cleaning apparatus (50) that cleans a substrate (S) includes: circumference supporting members (51) that support and rotate the substrate (S); a sponge (541) having a cleaning surface that is brought into contact with the surface to be cleaned of the substrate (S) being rotated by the circumference supporting members (51), and cleans the surface to be cleaned; an arm (53) that moves the sponge (541) in a radial direction of the substrate (S) while maintaining the cleaning surface in contact with the surface to be cleaned; and a controller (60) that controls the contact pressure of the cleaning surface on the surface to be cleaned. When the sponge (541) is located near the edge of the substrate (S), the controller (60) adjusts the contact pressure to a smaller value than that of when the sponge (541) is located near the center of the substrate (S). |
| US10163660B2 |
Sensor device with media channel between substrates
A sensor device including: a first substrate having a bottom surface and a top surface; a second substrate having a bottom surface and a top surface, a media channel having two vertical sections and a horizontal section, wherein the two vertical sections are through the second substrate, a portion of the bottom surface of the second substrate forms a top surface of the horizontal section, and a portion of the top surface of the first substrate forms a bottom surface of the horizontal section; a sensor chip disposed on one of the two vertical sections of the media channel; and a molding compound covering side surfaces of the first substrate, the second substrate, and the sensor chip. |
| US10163659B1 |
Fin-type field effect transistor and method of forming the same
A FinFET and a method of forming the same are provided. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin. |
| US10163658B2 |
Semiconductor package with multiple molding routing layers and a method of manufacturing the same
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed. |
| US10163655B2 |
Through substrate via liner densification
Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer. |
| US10163652B2 |
Mechanisms for forming patterns using multiple lithography processes
The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench. |
| US10163645B2 |
Method for processing wide-bandgap semiconductor substrate and apparatus therefor
There are provided a processing method for a wide-bandgap semiconductor substrate and an apparatus therefor that use no abrasives or no abrasive grains, or no solution having a large environmental burden at all, can process a single crystal, which is SiC, GaN, AlGaN, or AlN, at a variety of processing speed, can obtain a surface of higher quality than the quality of a surface finished by CMP, and also have an excellent compatibility with a clean room. A catalytic substance having a function of promoting the direct hydrolysis of a work piece (5) or promoting the hydrolysis of an oxide film on the surface of the work piece is used as a processing reference plane (3). In the presence of water (1), the work piece is brought into contact with or extremely close to the processing reference plane at a predetermined pressure. |
| US10163644B2 |
Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature. |
| US10163641B2 |
Memory with a raised dummy feature surrounding a cell region
A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region. The memory cell is present on the cell region. |
| US10163632B2 |
Material composition and process for substrate modification
Provided is a material composition and method for substrate modification. A substrate is patterned to include a plurality of features. The plurality of features includes a first subset of features having one or more substantially inert surfaces. In various embodiments, a priming material is deposited over the substrate, over the plurality of features, and over the one or more substantially inert surfaces. By way of example, the deposited priming material bonds at least to the one or more substantially inert surfaces. Additionally, the deposited priming material provides a modified substrate surface. After depositing the priming material, a layer is spin-coated over the modified substrate surface, where the spin-coated layer is substantially planar. |
| US10163631B2 |
Polymer resin comprising gap filling materials and methods
In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure. |
| US10163628B1 |
Lattice-mismatched semiconductor substrates with defect reduction
A structure includes a substrate including a first semiconductor material; a dielectric feature embedded in the substrate; and a second semiconductor material embedded in the substrate, the second semiconductor material having lattice mismatch to the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls in contact with the dielectric feature, the two lower sidewalls in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric feature being lower than a topmost portion of the two lower sidewalls. |
| US10163626B2 |
Metal gate structure and manufacturing method thereof
An NMOS transistor gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region and lining an inner sidewall of the spacer, a bottom barrier layer conformally disposed on the gate dielectric layer, a work function metal layer disposed on the bottom barrier layer, and a filling metal partially wrapped by the work function metal layer. The bottom barrier layer has an oxygen concentration higher than a nitrogen concentration. The bottom barrier layer is in direct contact with the gate dielectric layer. The bottom barrier layer includes a material selected from Ta, TaN, TaTi, TaTiN and a combination thereof. |
| US10163622B2 |
Substrate cleaning method, substrate processing method, substrate processing system and semiconductor device manufacturing method
Disclosed is a substrate cleaning method. In this substrate cleaning method, a step (step 10) is performed wherein a removal target film and located above a processing target film is patterned; after step 10, a step (step 11) is performed wherein the patterned removal target film is used as an etching mask to perform anisotropic etching on the processing target film; after step 11, a step (step 12) is performed wherein the remaining removal target film on the processing target film is subjected to gas chemical etching; and after step 12, a step (step 14) is performed wherein a target substrate, which includes the surface of the processing target film, is irradiated with gas clusters, thereby cleaning the surface of the processing target film by removing non-reactive or non-volatile residues remaining on the surface of the processing target film. |
| US10163621B1 |
Method and structure for FinFET devices
A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin. |
| US10163620B2 |
Continuous-wave laser-sustained plasma illumination source
An optical system for generating broadband light via light-sustained plasma formation includes a chamber, an illumination source, a set of focusing optics, and a set of collection optics. The chamber is configured to contain a buffer material in a first phase and a plasma-forming material in a second phase. The illumination source generates continuous-wave pump illumination. The set of focusing optics focuses the continuous-wave pump illumination through the buffer material to an interface between the buffer material and the plasma-forming material in order to generate a plasma by excitation of at least the plasma-forming material. The set of collection optics receives broadband radiation emanated from the plasma. |
| US10163617B2 |
Multiplexing of ions for improved sensitivity
Systems and methods are provided for multiplexed precursor ion selection using a filtered noise field (FNF). Two or more different precursor ions are selected using a processor. The processor calculates an FNF waveform. The calculated FNF waveform is applied to a continuous beam of ions using the processor. The processors sends information to a mass spectrometer, which includes an ion source that provides the continuous beam of ions and a first quadrupole that receives the continuous beam of ions, so that the first quadrupole applies the calculated FNF waveform to the continuous beam of ions. The first quadrupole applies the calculated FNF waveform to the continuous beam of ions by applying the calculated FNF waveform between pairs of rods or between pairs of auxiliary electrodes placed between rods. |
| US10163615B2 |
High resolution mobility analysis of large charge-reduced electrospray ions
Achieving high conversion of large multiply charged biological ions into low charge states involves requirements difficult to reconcile when high transmission and good spray quality (resulting in narrow mobility distributions) are sought. These multiple goals are achieved in this invention by partially isolating different regions from each other with electrostatic barriers relatively transparent to ions, such as metallic grids. One such region requires high electric fields for ion generation. The other region, used for ion recombination, is approximately field-free. In an alternative arrangement intended for charge reduction in sub-millisecond times, two sources of ions with opposite polarities are placed contiguously, with a grid in between. In all cases, ion crossing through grids into field free regions is effectively driven by space charge. |
| US10163613B2 |
Deconvolution of mixed spectra
An m/z range of an ion beam is divided into two or more precursor ion mass selection windows. A pattern of two or more different window m/z ranges to be used during two or more successive cycles for at least one precursor ion mass selection window is determined. The pattern includes an initial window m/z range and one or more successively different window m/z ranges. Each of the one or more successively different window m/z ranges includes at least a portion of the initial window m/z range. A tandem mass spectrometer is instructed to select and fragment the two or more precursor ion mass selection windows during each cycle of a plurality of cycles and to repeatedly use the pattern for each group of two or more successive cycles of the plurality of cycles for the selection and fragmentation of the at least one precursor ion mass selection window. |
| US10163609B2 |
Plasma generation for ion implanter
An ion implanter comprises a dissociation chamber in the ion implanter. The dissociation chamber has an input port for receiving a gas and an output port for outputting ions. A vacuum chamber surrounds the dissociation chamber. A plurality of rods or plates of magnetic material are located adjacent to the dissociation chamber on at least two sides of the dissociation chamber. A magnet is magnetically coupled to the plurality of rods or plates of magnetic material. A microwave source is provided for supplying microwaves to the dissociation chamber, so as to cause electron cyclotron resonance in the dissociation chamber to ionize the gas. |
| US10163607B2 |
Temperature control method and plasma processing apparatus
A method for controlling the temperature of a mounting table in a plasma processing apparatus, includes: calculating a first heat input amount according to high frequency power applied in a given process, wherein the first heat input amount is calculated based on a data table, the data table being generated by measuring temperatures so as to find a first relationship between the high frequency power applied in the plasma processing apparatus and the heat input amount to the mounting table; controlling, based on an operation map, the temperature of at least one of the first heating mechanism and the cooling mechanism so that a first temperature difference between the cooling mechanism and the first heating mechanism is within a controllable range corresponding to the first heat input amount, wherein the temperature of the first heating mechanism is controllable upon the first temperature difference falling within the controllable. |
| US10163603B2 |
Particle beam system and method for the particle-optical examination of an object
A particle beam system includes a particle source to produce a first beam of charged particles. The particle beam system also includes a multiple beam producer to produce a plurality of partial beams from a first incident beam of charged particles. The partial beams are spaced apart spatially in a direction perpendicular to a propagation direction of the partial beams. The plurality of partial beams includes at least a first partial beam and a second partial beam. The particle beam system further includes an objective to focus incident partial beams in a first plane so that a first region, on which the first partial beam is incident in the first plane, is separated from a second region, on which a second partial beam is incident. The particle beam system also a detector system including a plurality of detection regions and a projective system. |
| US10163596B2 |
Horizontal-deflection prevention mechanism for high voltage direct current relay
The present invention discloses a horizontal-deflection prevention mechanism for an HVDC relay, comprising a moving contact assembly which comprises a moving reed and moving contacts arranged at left and right ends of the moving reed; an upper section of a pushrod is located above a yoke plate and fixed with the moving reed; a positioning plate is provided on the yoke plate; and a left return spring is connected between a left end of the moving reed and the positioning plate, and a right return spring is connected between a right end of the moving reed and the positioning plate. In the present invention, by the arrangement of a left return spring and a right return spring at the left and right ends of the moving reed at which moving contacts are provided, on one hand, a breaking force can be provided, which allows the moving contacts to quickly separate from the stationary contacts when the moving contacts and the stationary contacts are to be separated from each other, so that the relay makes a response quickly. On the other hand, the left return spring and the right return spring always provide an acting force which prevents the moving reed from rotating horizontally, so as to ensure that the moving contacts and the stationary contacts can come into contact precisely and to thus prevent the occurrence of faults due to the contact between the moving reed and other components. |
| US10163591B2 |
Motor vehicle operating device with sound-generating switching element
An operating device includes a casing, an operating button arranged at the casing for the manual actuation of the operating device, and a printed circuit board that is arranged in the casing. A switching element is mechanically coupled to the operating button and arranged on the printed circuit board. The switching element produces a pronounced sound when the operating button is actuated. To this end, next to the switching element, the printed circuit board is mechanically connected to the casing by at least one support element and each support element is designed to stabilize the printed circuit board against a tremor that is produced by the switching element when producing the sound. |
| US10163590B2 |
Power-circuit breaking device
A power-circuit breaking device includes a receptacle and a plug. The receptacle includes a power terminal and a signal terminal. The plug includes a main terminal and a sub-terminal. The plug includes a plug housing, a lever which is attached to the plug housing, a lock slider which is attached to the plug housing, and a sub-connector which is supported by the lock slider. The plug housing holds the main terminal. The sub-connector holds the sub-terminal. When the lock slider slides, the sub-connector moves. When the lever is located at a closed position, the main terminal is connected to the power terminal. When the lock slider is located at a connected position, the sub-terminal is connected to the signal terminal. |
| US10163587B2 |
Interlock device of withdrawable arc eliminator
The present invention relates to a withdrawable arc eliminator having an interlock function, and more particularly, to a withdrawable arc eliminator having an interlock function capable of preventing insertion or withdrawal of an arc eliminator applied to an electrical panel, in a closed state of the arc eliminator. |
| US10163570B2 |
Power storage device
An electrical double layer capacitor having electrolyte-containing layer between a first polarizable electrode layer and a second polarizable electrode layer. An insulating adhesive portion adheres to a first current collector and a second current collector which at least partially face each other with the electrolyte-containing layer interposed therebetween. The insulating adhesive portion 15 extends around the first and second polarizable electrode layers and the electrolyte-containing layer. A thickness of the electrolyte-containing layer is larger than a difference between a thickness of the insulating adhesive portion and thicknesses of the first and second polarizable electrode layers. |
| US10163559B2 |
Coil component
A terminal electrode includes a base extending along the outer end face of a flange, a mounting part extending from the base along the bottom face of the flange via a first bending part that covers the edge portion where the outer end face and the bottom face meet, and a wire connection part extending from the base along a substantially horizontal face via a second bending part that covers the edge portion where the outer end face and the substantially horizontal face meet, the wire connection part being electrically connected to an end portion of a wire. |
| US10163550B2 |
Superconducting cable and superconducting cable manufacturing method
In order to obtain a highly versatile superconducting cable capable of absorbing differences in thermal contraction amounts that arise between three members, these being a cable core, an inner tube, and an outer tube, and to obtain a superconducting cable manufacturing method of the same, a superconducting cable includes a thermal insulation vacuum tube and a cable core. The thermal insulation vacuum tube includes an inner tube fixed at both ends and having a cooling medium filled inside, and an outer tube disposed at an outer peripheral side of the inner tube with a space between the outer tube and the inner tube maintained at a vacuum, and is configured to include a winding section wound with one or more turns. The cable core is fixed at both ends and disposed inside the inner tube. |
| US10163548B2 |
Power/fiber hybrid cable
The present disclosure relates to a hybrid cable having a jacket with a central portion positioned between left and right portions. The central portion contains at least one optical fiber and the left and right portions contain electrical conductors. The left and right portions can be manually torn from the central portion. |
| US10163540B2 |
Production process for highly conducting and oriented graphene film
A process for producing a highly conducting film of conductor-bonded graphene sheets that are highly oriented, comprising: (a) preparing a graphene dispersion or graphene oxide (GO) gel; (b) depositing the dispersion or gel onto a supporting solid substrate under a shear stress to form a wet layer; (c) drying the wet layer to form a dried layer having oriented graphene sheets or GO molecules with an inter-planar spacing d002 of 0.4 nm to 1.2 nm; (d) heat treating the dried layer at a temperature from 55° C. to 3,200° C. for a desired length of time to produce a porous graphitic film having pores and constituent graphene sheets or a 3D network of graphene pore walls having an inter-planar spacing d002 less than 0.4 nm; and (e) impregnating the porous graphitic film with a conductor material that bonds the constituent graphene sheets or graphene pore walls to form the conducting film. |
| US10163539B2 |
High strength and high conductivity copper alloy rod or wire
A high strength and high conductivity copper rod or wire includes Co of 0.12 to 0.32 mass %, P of 0.042 to 0.095 mass %, Sn of 0.005 to 0.70 mass %, and O of 0.00005 to 0.0050 mass %. A relationship of 3.0≤([Co]−0.007)/([P]−0.008)≤6.2 is satisfied between a content [Co] mass % of Co and a content [P] mass % of P. The remainder includes Cu and inevitable impurities, and the rod or wire is produced by a process including a continuous casting and rolling process. Strength and conductivity of the high strength and high conductivity copper rod or wire are improved by uniform precipitation of a compound of Co and P and by solid solution of Sn. The high strength and high conductivity copper rod or wire is produced by the continuous casting and rolling process, and thus production costs are reduced. |
| US10163536B2 |
Method and apparatus for recovery of radioactive nuclides from spent resin materials
A process for the recovery of a radioisotope from a waste resin of a nuclear power plant comprises the steps of: a) treating a waste resin loaded with at least one radioisotope with an organic acid or alkaline compound to release the at least one radioisotope and to obtain a process solution containing the at least one radioisotope; b) separating the at least one radioisotope from the process solution through a reaction specific to the radioisotope so as to obtain a treated process solution depleted of the at least one radioisotope, wherein said depleted process solution comprises the organic acid or alkaline compound and optionally a non-reacted radioisotope; c) reacting the organic acid or alkaline compound in the depleted process solution from step b) by thermal and/or photochemical oxidation to form gaseous reaction products; and d) reloading the waste resin with the reacted process solution from step c) to bind the non-reacted radioisotope on the waste resin. Further, an apparatus is provided to carry out the above method. |
| US10163533B2 |
Control rod drive mechanism outer diameter seal ultra high pressure cavitation peening
A sealing device is provided to form a sealed region about one or more surfaces to be treated. The sealing device has an open end with a rim configured to matingly engage a treatment surface. The sealing device is braced both vertically and laterally, and the sealed region is flooded and pressurized. A peening nozzle and manipulating tooling are positioned within an interior volume of the sealing device. Pressurized fluid is ejected from the nozzle causing the formation of cavitation bubbles. The nozzle flow causes the cavitation bubbles to settle on the surfaces to be treated. The collapsing impact of the cavitation bubbles imparts compressive stress in the materials of the treatment surfaces. |
| US10163531B2 |
Reactivity control in a molten salt reactor
Methods of controlling the reactivity of a molten salt fission reactor. The molten salt fission reactor comprises a core and a coolant tank (101), the core comprising fuel tubes (103) containing a molten salt fissile fuel, and the coolant tank containing a molten salt coolant (102), wherein the fuel tubes are immersed in the coolant tank. The methods comprise dissolving a neutron absorbing compound in the molten salt coolant, the neutron absorbing compound comprising a halogen and a neutron absorbing element. The first method further comprises reducing the neutron absorbing compound to a salt of the halogen and an insoluble substance comprising the neutron absorbing element, the halogen being fluorine or chlorine, wherein the insoluble substance is not volatile at a temperature of the coolant during operation of the reactor. In the second method the one or more neutron absorbing compounds are chosen such that reduction of the neutron absorbing capacity of the one or more neutron absorbing compounds due to absorption of neutrons compensates for a fall in reactivity of the core in order to control fission rates in the core. Apparatus for implementing the methods are also provided. |
| US10163529B2 |
Display processing method and apparatus
A disclosed method includes: defining two first points in a model cross section of a model of an object and two corresponding second points in an image that is a cross section of the object for a reference time; performing first transforming including expansion or reduction for the model cross section so that a position of a second point is identical to a position of a corresponding first point; superimposing the image and the model cross section after the performing; second transforming a second model cross section for a second time after the reference time, so that positions of two second points in a second image for the second time are almost identical to positions of corresponding two first points in the second model cross section; and superimposing the second image and the second model cross section after the second transforming. |
| US10163525B2 |
Test apparatus based on binary vector
A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT. |
| US10163520B1 |
OTP cell with improved programmability
An integrated circuit OTP memory cell has a programming element with enhanced programmability. The programming element has a doped region at the surface of a semiconductor substrate and a conducting layer partially extending over a surface of the semiconductor surface and along a boundary of the doped region. The conducting layer is displaced from the surface of the doped region and the semiconductor substrate by a thin oxide layer. The partially extending conducting layer provides locations to concentrate electric fields and rupture the gate oxide layer during programming. |
| US10163519B2 |
Semiconductor device, electronic component, and electronic device
A highly reliable semiconductor device is provided. A memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. The first transistor is configured to hold charge corresponding to first data retained in the memory cell when turned off. The data writing circuit is configured to write the first data and correction data to the memory cell. The data reading circuit is configured to read a first voltage value corresponding to the first data, read a second voltage value corresponding to the correction data written to the memory cell, convert a voltage value that is equivalent to a difference between the first voltage value and the second voltage value into corrected first data, and output the corrected first data to the data writing circuit. |
| US10163514B2 |
Methods of operating a memory during a programming operation
Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage while applying the first voltage to a second access line, the first access line coupled to a target memory cell of the programming operation and an unselected memory cell not targeted for the programming operation, and the second access line coupled to memory cells not targeted for the programming operation. After increasing the voltage applied to the first access line, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage and increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage and lower than the third voltage. |
| US10163512B2 |
Semiconductor device capable of effectively eliminating hot holes in a channel and operating method thereof
A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines. |
| US10163508B2 |
Supporting multiple memory types in a memory slot
Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed. |
| US10163507B1 |
Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described. |
| US10163506B2 |
Apparatuses including memory cells and methods of operation of same
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. |
| US10163505B2 |
RRAM array with current limiting element
A resistive random access memory (RRAM) circuit is provided. In some embodiments, the RRAM circuit has a plurality of RRAM cells. A bit-line decoder is configured to concurrently apply a forming signal to the plurality of RRAM cells. A current limiting element is configured to concurrently limit a current of the forming signal applied to the plurality of RRAM cells. |
| US10163504B2 |
Planar variable resistance memory
An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage. |
| US10163502B2 |
Selective performance level modes of operation in a non-volatile memory
In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described. |
| US10163501B2 |
Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level. |
| US10163500B1 |
Sense matching for hard and soft memory reads
Error correction systems and methods for improving sense matching conditions between hard-bit read (HBR) information and soft-bit read (SBR) information. For HBRs, a given set of sense conditions can include a discharged bit line of one or more cells that discharged during a previous HBR. For SBRs, a given set of sense conditions can include loading latches of the sense amplifiers for corresponding cells are with sense results of the previous SBR strobe when the corresponding cells discharged during a previous SBR strobe or loading the latches of the sense amplifiers with sense results of a previous HBR when the corresponding cells discharged during the previous HBR. |
| US10163498B1 |
Reflow protection
Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, up to a threshold amount on a memory array in a reflow-protection mode, and to transition from the reflow-protection mode to a normal-operation mode after the initial data exceeds the threshold amount. |
| US10163497B2 |
Three dimensional dual-port bit cell and method of using same
A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch. |
| US10163496B2 |
Static random access memory (SRAM) tracking cells and methods of forming the same
An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit. |
| US10163494B1 |
Memory device and fabrication method thereof
A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell. |
| US10163493B2 |
SRAM margin recovery during burn-in
Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells. |
| US10163491B2 |
Memory circuit having shared word line
A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates. |
| US10163490B2 |
P-type field-effect transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells, and related memory systems and methods
P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells (“bit cells”). Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance. |
| US10163482B2 |
Ground reference scheme for a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation. |
| US10163481B1 |
Offset cancellation for latching in a memory device
Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor. |
| US10163478B2 |
Magnetic memory devices having memory cells and reference cells with different configurations
A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a reference cell including a first resistance element and a second resistance element configured to be coupled in parallel to a second sensing node, the first resistance element including a first number of reference MTJs and the second resistance element including a second number of reference MTJs different from the first number of reference MTJs. The memory device further includes a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell. In some embodiments, the first number of reference MTJs includes first reference MTJs connected in series and the second number of reference MTJs includes second reference MTJs connected in series. |
| US10163476B2 |
Method of operating tracking circuit
A method of operating a tracking circuit of a memory device includes charging a node of the tracking circuit to a first predetermined voltage level, the first node being electrically coupled with a first load device. A first plurality of tracking cell transistors are activated to discharge the first node toward a second predetermined voltage level. A reset signal is generated based on a signal at the first node. The reset signal may correspond to a waiting period for reading a memory cell of the memory device. |
| US10163475B2 |
Non-volatile memory device having dummy cells and memory system including the same
A non-volatile memory device includes a cell string, a ground select transistor, and at least one dummy cell. The cell string includes at least one memory cell. The at least one dummy cell is provided between the at least one memory cell and the ground select transistor and is connected to a bit line. A controller executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period. |
| US10163472B2 |
Apparatuses and methods for memory operations having variable latencies
Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation. |
| US10163471B2 |
Time tracking with trits
A memory controller circuitry includes a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a global timer index from a global timer having a granularity, G. The timestamp circuitry is further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block. The demarcation voltage (VDM) selection circuitry is to fetch a combined count from a count store. The combined count represents a combined state. The combined state includes a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block. |
| US10163470B2 |
Dual rail memory, memory macro and associated hybrid power supply method
A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages. |
| US10163467B2 |
Multiple endianness compatibility
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes in a non-bit-sequential format. The method includes reordering the bits in each byte of the plurality of bytes such that the plurality of bytes are arranged in a bit-sequential format. |
| US10163465B1 |
Data receiver and controller for DDR memory
A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain. |
| US10163464B2 |
Memory module capable of measuring temperature and system using the same
A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. The thermocouple may be coupled to at least one contact point among a plurality of contact points formed on a region, on which a memory device may be configured to be mounted. The temperature sensor may be coupled to the thermocouple, and may be configured to generate temperature information. |
| US10163463B2 |
Virtual reality system and method of controlling working state thereof
A virtual reality system and a method of controlling working state of the virtual reality system. The virtual reality system comprises a video playing device and a virtual reality glasses box, and the virtual reality glasses box utilizes a screen of the video playing device to play a video content, the method comprises: establishing a wired or wireless connection between the video playing device and the virtual reality glasses box; when the video playing device is placed in the virtual reality glasses box, transmitting information of wearing state of the virtual reality glasses box to the video playing device; and controlling a playing state of the video playing device according to the wearing state of the virtual reality glasses box. The present disclosure controls the working state of the virtual reality device by the action of the user operating the device itself, and the user does not need to employ tedious and complicated operations to control each of the devices, which increases usability, and improves user experience. |
| US10163461B2 |
Magazine management device in which one or more antennas disposed in one antenna base communicate with two or more radio identifiers corresponding to two or more magazine regions
A magazine management device stores a plurality of magazines in which a plurality of optical discs is housed. The magazine management device includes a case that supports the plurality of magazines, a plurality of partitions that divides the case so as to form a plurality of regions in which the magazines can be stored one by one, an antenna that transmits a radio wave for asking a radio identifier provided to the magazine for a response and receives a radio wave of the response transmitted from the radio identifier, and an arithmetic processor that receives information obtained from the radio wave of the response received by the antenna. |
| US10163455B2 |
Detecting pause in audible input to device
A device includes a processor and a memory accessible to the processor and bearing instructions executable by the processor to process an audible input sequence provided by a user of the device, determine that a pause in providing the audible input sequence has occurred at least partially based on a first signal from at least one camera communicating with the device, cease to process the audible input sequence responsive to a determination that the pause has occurred, determine that providing the audible input sequence has resumed based at least partially based on a second signal from the camera, and resume processing of the audible input sequence responsive to a determination that providing the audible input sequence has resumed. |
| US10163453B2 |
Robust voice activity detector system for use with an earphone
An electronic device or method for adjusting a gain on a voice operated control system can include one or more processors and a memory having computer instructions. The instructions, when executed by the one or more processors causes the one or more processors to perform the operations of receiving a first microphone signal, receiving a second microphone signal, updating a slow time weighted ratio of the filtered first and second signals, and updating a fast time weighted ratio of the filtered first and second signals. The one or more processors can further perform the operations of calculating an absolute difference between the fast time weighted ratio and the slow time weighted ratio, comparing the absolute difference with a threshold, and increasing the gain when the absolute difference is greater than the threshold. Other embodiments are disclosed. |
| US10163446B2 |
Audio encoder and decoder
This disclosure falls into the field of audio coding, in particular it is related to the field of spatial audio coding, where the audio information is represented by multiple audio objects including at least one dialog object. In particular the disclosure provides a method and apparatus for enhancing dialog in a decoder in an audio system. Furthermore, this disclosure provides a method and apparatus for encoding such audio objects for allowing dialog to be enhanced by the decoder in the audio system. |
| US10163445B2 |
Apparatus and method encoding/decoding with phase information and residual information
Provided is an apparatus and method of encoding and decoding multiple channel signals based upon phase information and one or more residual signals. |
| US10163441B2 |
Location-based responses to telephone requests
A method for receiving processed information at a remote device is described. The method includes transmitting from the remote device a verbal request to a first information provider and receiving a digital message from the first information provider in response to the transmitted verbal request. The digital message includes a symbolic representation indicator associated with a symbolic representation of the verbal request and data used to control an application. The method also includes transmitting, using the application, the symbolic representation indicator to a second information provider for generating results to be displayed on the remote device. |
| US10163437B1 |
Training models using voice tags
Techniques for training machine-learning algorithms with the aid of voice tags are described herein. An environment may include sensors configured to generate sensor data and devices configured to perform operations. Sensor data as well as indications of actions performed by devices within the environment may be collected over time and analyzed to identify one or more patterns. Over time, a model that includes an association between this sensor data and device actions may be created and trained such that one or more device actions may be automatically initiated in response to identifying sensor data matching the sensor data of the model. To aid in the training, a user may utter a predefined voice tag each time she performs a particular sequence of actions, with the voice tag indicating to the system that temporally proximate sensor data and device-activity data should be used to train a particular model. |
| US10163436B1 |
Training a speech processing system using spoken utterances
Systems, methods, and devices for training a Natural Language Understanding (NLU) component of a system using spoken utterances of individuals are described. A server sends a device, such as a speech-controlled device, a signal that causes the device to output audio soliciting content regarding how a user would speak a particular command for execution by a particular application. The device captures spoken audio and sends it to the server. The server performs speech processing on received audio data to parse the audio data into multiple portions. The server then associates a first portion of the audio data with a command indicator and a second portion of the audio data with a content indicator. The associated data is then used to update how the NLU component determines how utterances triggering the command are spoken. |
| US10163432B2 |
Active noise control using variable step-size adaptation
A system and method (referred to as the system) that actively reduces noise in a vehicle. The system generates one or more control output signals to drive multiple loudspeakers; and adapts multiple control coefficients of a control filter based on multiple secondary path transfer functions. The secondary path transfer functions model the acoustic paths between each loudspeaker and multiple microphones. The multiple control coefficients are time varying and frequency dependent and the rate the plurality control coefficients adapt is based on an adaptive step size based on one or more step size criteria. |
| US10163425B2 |
Chuck structure capable of quickly adjusting placement angle of drumstick and percussion practice assisting device thereof
A chuck structure for fixing a drumstick on a non-circular revolving shaft of a foot drum includes a retractable chuck, two arched plates and a fastening element. The two arched plates clamp the non-circular revolving shaft. An inner arched surface of each arched plate has an inner fastening surface correspondingly clamping the non-circular revolving shaft, and an outer arched surface of each arched plate has a spiked surface. The retractable chuck includes a fastening portion and a rotating portion, which are pivotally connected to each other, clamp the two arched plates, and are penetrated by the drumstick. Each of the fastening portion and a rotating portion has a clamping surface abutting against the spiked surface. The fastening member propels and rotates the rotating portion, so as to allow the retractable chuck, spaced by the two arched plates, to clamp and fasten on the non-circular revolving shaft. |
| US10163420B2 |
System, apparatus and methods for adaptive data transport and optimization of application execution
Elements and processes used to enable the generation and interaction with complex networks, simulations, models, or environments. In some embodiments, this is accomplished by use of a client-server architecture that implements processes to improve data transport efficiency (and hence network usage), reduce latency experienced by users, and optimize the performance of the network, simulation, model or environment with respect to multiple parameters. |
| US10163419B2 |
Image processing to combine virtual object with captured image
There is provided an image processing apparatus including an image processing unit which combines a virtual object with a captured image. The image processing unit determines the virtual object based on a state or a type of an object shown in the captured image. |
| US10163417B2 |
Display panel driving apparatus, method of driving, and display apparatus with first off voltage controlled based on leakage current
A display panel driving apparatus includes a data driving part, a gate driving part and an off voltage controlling part. The data driving part is configured to output a data signal to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel. The off voltage controlling part is configured to receive a first off voltage and a second off voltage applied to the gate driving part to generate the gate signal, measure a leakage current of the gate driving part, and control the first off voltage based on the leakage current. Thus, display quality of a display apparatus including the gate driving part may be enhanced. |
| US10163414B2 |
GOA driving circuit
A GOA driving circuit is provided, which includes a first signal generating module for generating the forward scan control signal based upon a first clock signal and a cascade signal; a control module for controlling an output of the cascade signal based upon the forward scan control signal and the reverse scan control signal; a latch module for latching the cascade signal by the first clock signal and the second clock signal; a processing module and a buffer module. |
| US10163412B2 |
Pixel structure
A pixel structure is provided. The pixel structure includes a scan line and a data line, an active device, a pixel electrode, and a common electrode. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The common electrode is disposed to overlap with the pixel electrode. The common electrode is coupled to the pixel electrode to form a first storage capacitor and a second storage capacitor. The first storage capacitor and the second storage capacitor commonly use the pixel electrode as an upper electrode. |
| US10163406B2 |
Electro-optic displays displaying in dark mode and light mode, and related apparatus and methods
This invention provides methods of and related apparatus for driving an electro-optic display having a plurality of pixels to display white text on a black background (“dark mode”) while reducing edge artifacts, ghosting and flashy updates. The present invention reduces the accumulation of edge artifacts by applying a special waveform transition to edge regions according to an algorithm along with methods to manage the DC imbalance introduced by the special transition. Edge artifact clearing may be achieved by identifying specific edge pixels to receive a special transition called an inverted top-off pulse (“iTop Pulse”) and, since the iTop Pulse is DC imbalanced, to subsequently discharge remnant voltage from the display. This invention further provides methods of and related apparatus for driving an electro-optic display having a plurality of pixels to display white text on a black background (“dark mode”) while reducing the appearance of ghosting due to edge artifacts and flashy updates by identifying specific edge pixels to receive a special transition called an inverted Full Pulse transition (“iFull Pulse”). |
| US10163400B2 |
Display driving apparatus
A display driving apparatus including a lightness adjusting unit, a gamma adjusting unit, a pre-charging voltage adjusting unit and a source driving unit is disclosed. The lightness adjusting unit receives and adjusts a lightness of an image data. The gamma adjusting unit adjusts a gamma voltage corresponding to the image data to generate a source data voltage. The pre-charging voltage adjusting unit calculates a highest data voltage and a lowest data voltage which can be outputted by a source electrode and adjusts a pre-charging voltage accordingly to make the adjusted pre-charging voltage the same with the highest data voltage or the lowest data voltage or only a shifted voltage different from the highest data voltage or the lowest data voltage of the image data. The source driving unit outputs the adjusted pre-charging voltage and the source data voltage to a display panel respectively. |
| US10163398B2 |
Method of driving a display panel and a display apparatus for performing the same
A method of driving a display panel includes adjusting a level of a data sustaining voltage or an on bias voltage during an on bias compensating period, applying the on bias voltage to pixels through data lines during an on bias period, which is subsequent to the on bias compensating period, to adjust a voltage level of control electrodes of driving transistors of the pixels, initiating a voltage of anode electrodes of organic light emitting elements of the pixels during an initiating period, applying data voltages to the pixels through the data lines during a scanning period, and turning on the organic light emitting elements of the pixels during an emission period. |
| US10163393B2 |
Display substrate, display equipment and regional compensation method
A display substrate, a display equipment and a regional compensation method. The display substrate includes a pixel array, a common cathode current detection circuit, and a data signal compensation circuit. The common cathode current detection circuit is configured to detect a total current flowing through each common cathode; the data signal compensation circuit is configured to receive the pixel light emitting current of the first sub-pixel, receive the total current of the common cathode, and calculate compensation data for each of the sub-pixels according to the pixel light emitting current and the total current of the common cathode. |
| US10163387B2 |
Image display device and driving method of the same
An image display device including a light-emitting element configured to emit light corresponding to a current flowing therethrough; a driving element that is connected to the light-emitting element and configured to control light emission of the light-emitting element; and a control unit configured to apply a reverse bias voltage to a first n-type driving element whose the threshold voltage determined at a specific time is equal to or higher than a positive predetermined voltage level for shifting the threshold voltage of the first n-type driving element in a negative direction, and not apply the reverse bias voltage to a second n-type driving element whose the threshold voltage determined at the specific time is lower than the positive predetermined voltage level for shifting the threshold voltage of the second n-type driving element in a positive direction when the light-emitting element does not emit light. |
| US10163384B2 |
Flat panel display
A flat panel display includes: a substrate that includes a display region and a non-display region at a periphery of the display region; a pixel array disposed on the substrate of the display region; an input pad part disposed on the substrate of the non-display region; a bonding pad part disposed on the substrate of the non-display region, the bonding pad part including a plurality of output pads connected to the pixel array and a plurality of input pads connected to the input pad part; and a protective layer disposed on the substrate of the non-display region, the protective layer having openings formed therein that expose portions of the bonding pad part and the input pad part, wherein the opening of the protective layer is smaller than the bonding pad part, wherein the protective layer is thinner at a portion that overlaps the bonding pad part than at other portions. |
| US10163379B2 |
Detection device, detection method and detection system
The present invention provides a detection device, a detection method and a detection system, which are used for detecting damaged condition of a substrate. The detection device includes a probe unit and a judgement unit, and the probe unit includes a probe, a speed detection module and a driving force control module both provided on the probe, wherein the bottom end of the probe is used for contacting with the substrate to be detected; the speed detection module is used for obtaining a real-time speed of the probe in a process of detection and transmitting the real-time speed to the judgement unit; the driving force control module is used for applying a constant driving force to the probe; and the judgement unit is used for receiving the real-time speed of the probe and judging the damaged condition of the substrate to be detected according to the real-time speed. |
| US10163376B2 |
Display assembly
There is provided a display assembly. The assembly includes an elongate mounting member. The mounting member has a top, a bottom spaced-apart from the top, and a plurality of spaced-apart grooves extending from the top to the bottom thereof. The assembly includes a plurality of planar members. Each of the planar member includes image indicia thereon. The planar members are shaped to fit within respective ones of the grooves, whereby the image indicia so arranged conveys a three-dimensional effect. |
| US10163362B2 |
Emotion and mood data input, display, and analysis device
A feeling of each of members forming a group or team and the mood of all the members felt by each member are objectified and recorded. An emotion/mood data input, display, and analysis device includes a controller, a display, an input unit, and a recording unit. The controller includes an input screen generation unit. The input screen generation unit generates a first input screen that allows each of multiple members forming a group to, as an inputter, input whether an emotion or feeling of the each member is cheerful or gloomy, a level of cheerfulness or gloominess, whether the emotion or feeling is strong or weak, and a level of strength or weakness in a bifurcated manner. The display displays the first input screen. The controller captures data through the first input screen displayed on the display and the input unit and records the data in the recording unit. |
| US10163352B2 |
Driving control device
When performing a switch between the lane change control and the lane keeping control, a switching controller of the driving control device sets a transition time-frame for performing the switch, and gradually switches between the lane change control and the lane keeping control during the transition time-frame. |
| US10163339B2 |
Monitoring traffic congestion
Described herein is a framework to monitor traffic congestion. In accordance with one aspect of the framework, the framework receives vehicle data from vehicle data sources located in a region of interest. The framework may determine a sample size and an average speed for an edge of the region of interest based on the vehicle data. Congestion probability may then be determined based on the sample size and average speed. A report may be presented based on the congestion probability. |
| US10163331B2 |
Alarm system with two-way voice
Techniques are described for establishing a two-way voice communication session with an alarm system. The alarm system may establish a two-way voice communication session with an operator associated with a monitoring service that provides monitoring services for alarm events detected by the alarm system. The alarm system also may establish a two-way voice communication session with a notification recipient that is interested in receiving notifications associated with events detected by the alarm system. |
| US10163330B1 |
System and method for securely accessing online systems
The present disclosure relates generally to a method of operating a customer interface device (CID). The method includes: receiving a request from a customer to access a secure portion of an online system; establishing an encrypted channel to an authentication system of the online system. The method also includes: outputting a prompt to the customer to provide a spoken passphrase of the customer; capturing the spoken passphrase of the customer to generate a recording; and providing, via the encrypted channel, credentials of the customer to an authentication system of the online system, wherein the credentials include the recording. The method further includes; receiving, via the encrypted channel, an indication of approval of the credentials of the customer from the authentication system; and establishing, via the encrypted channel, a secure mode pass-through connection to the secure portion of the online system. |
| US10163329B1 |
Home alarm system
Techniques are described for selecting an alarm state based at least in part on determining a security event related to security and automation systems. One method includes receiving, from a sensor, a first indication of a security event at the first location, determining a first threat level based on the security event, and activating a first alarm state based at least in part on the first threat level. |
| US10163328B2 |
SATCOM distressed aircraft tracking system
The invention is a system and method for communicating emergency information from an aircraft in response to an emergency or technical problem detected by monitoring avionics data at an onboard autonomous aircraft SATCOM transceiver activation device, the emergency detection functioning to automatically activate and control an aircraft SATCOM transceiver which then (i) automatically triggers real-time tracking of the aircraft via satellite, (ii) provides aircraft positioning on broadcast distinctive signals and data in designated frequencies; and (iii) monitors, processes, and automatically communicates the avionics data in conformance with ICAO standards for GADSS. |
| US10163327B1 |
Methods of facilitating emergency assistance
In system and methods for loss mitigation, accident data associated with a vehicle accident involving a driver may be collected. The accident data may be analyzed, and a likely severity of the vehicle accident may be determined based upon the analysis of the accident data. A communication related to emergency assistance or an emergency assistance recommendation may be generated based upon the determined likely severity of the vehicle accident, and transmitted, via wireless communication, from one or more remote servers to a mobile device associated with the driver. A wireless communication from the driver indicating approval or modification of the emergency assistance or emergency assistance recommendation may be received. A third party may be notified, via a communication sent from the remote server(s), of requested emergency assistance as approved or modified by the driver. An estimated insurance claim may also be generated based upon vehicle accident likely severity. |
| US10163322B2 |
Wireless communication between patient beds and equipment for checking compatibility
A system comprises a patient bed having a reader to read wireless signals. In some embodiments a wound dressing has a transmitter that transmits wireless signals to the reader of the patient bed. In other embodiments, a garment has a transmitter that transmits wireless signals to the reader of the patient bed. In still further embodiments, other medical equipment has a transmitter that transmits wireless signals to the reader of the patient bed. |
| US10163312B2 |
Autonomously operating light emitting devices providing detection and warning of hazardous condition on path of travel
A system is disclosed comprising a plurality of light emitting devices located along a path of travel, each light emitting device comprising a light emitting source, a sensor, a communication module, and a processor, wherein when a first one of the plurality of light emitting devices is activated, the processor in the first light emitting device is configured to detect one or more physical structures surrounding the first light emitting device, detect one or more other light emitting devices, and based at least in part on the detection of the one or more physical structures and the one or more other light emitting devices, determine a location of the first light emitting device with respect to the path of travel. |
| US10163311B2 |
Systems for tracking medications
The present disclosure relates to integrated systems, methods and apparatuses for assisting individuals in managing acute life-threatening conditions. A system in accordance with the current disclosure may comprise an electronic circuit configured to be attached to a container of a medication and one or more devices in communication with the electronic circuit in a private network. In an aspect, the one or more devices may work in concert to determine the safety level of an individual based on predetermined usage settings. In some aspects, the system may be configured to determine whether a medication would expire before its manufactured expiry date. In another aspect, the system may assist an individual in locating a medication. In a further aspect, the system may determine whether an individual is having an anaphylactic reaction. In some aspects, the system may detect a known allergen and alert the individual. |
| US10163310B2 |
Alarm panel
A fire alarm panel comprises a panel interface. The panel interface includes a display screen, a plurality of discrete condition lights separate from the display screen, and a touchscreen panel extending across both the display screen and the plurality of condition lights. |
| US10163303B1 |
Cash slot machine augmented with secondary currency
A method, apparatus, and computer readable storage to implement an augmented game system. A player can play an online game and accumulate loyalty points without have to pay cash. The player can enter a physical casino and play an electronic gaming machine which can retrieve the player's information from the online game including the number of loyalty points the player has and any other incentives or game add-ons the player would be entitled to. The player would then play a physical game on the electronic game normally (by depositing cash and playing) but the game play would be augmented by virtue of the player having the loyalty points or other incentives or add-ons. For example, the game can be augmented by giving the player a better paytable. |
| US10163302B2 |
Gaming system and method for providing a variable award in association with a virtual currency purchase
A gaming system which enables a player to purchase an amount of virtual currency from an online casino wherein the purchased virtual currency includes a predetermined component and a variable component. |
| US10163301B2 |
Gaming systems, gaming devices and methods having time based games and magnitudes associated with wagering events in the time based games
A gaming system receives a total wager for a game session which occurs over a designated period of time. The game session includes a plurality of different wagering events. Each of the wagering events is associated with one of a plurality of different magnitudes. For each of the plurality of different wagering events, the gaming system determines: a portion of the total wager amount, and a wager by modifying the determined portion by the magnitude associated with that wagering event. The gaming system causes the wagering event to occur, determines at least one outcome for the wagering event, determines any awards based on the determined wager and the at least one determined outcome, and provides any of the determined awards to the player. |
| US10163300B2 |
System and method for enabling a player proxy to execute a gaming event
The gaming system that includes a first gaming machine operated by a first player at a first location and a second gaming machine operated by a second player at a second location. The second location is remote from the first. The first gaming machine is configured to present a game to the first player upon receipt of a wager from the first player. The second gaming machine is configured to present the game to the second player upon receipt of a wager from the second player. The gaming system further includes a processor programmed to receive a request to execute a game play event for the first player. In response to the request, the processor is configured to execute the game play event for the first player and the second player. |
| US10163298B2 |
Wagering game wearables
A wagering game system and its operations are described herein. In some embodiments, the operations can include detecting that one or more wearable computers are within a proximity range to a wagering game machine. In some examples, the operations further include determining one or more characteristics associated with the one or more wearable computers in response to the detecting that the one or more wearable computers are within the proximity range to the wagering game machine. In some examples, the operations further include providing a feature associated with a wagering game based on the one or more characteristics of the one or more wearable computers. |
| US10163295B2 |
Gaming machine, gaming machine control method, and gaming machine program for generating 3D sound associated with displayed elements
A gaming machine for providing a game to a player is described herein. The gaming machine includes a housing, a sound reproduction system coupled to the housing, a display device, and a gaming controller. The sound reproduction system is configured to generate sound features associated with the game and to emit 3D sound effects within a listening space associated with the gaming machine. The gaming controller randomly determines an outcome of the game and display the outcome on the display device, detects a triggering condition occurring in the outcome of the game, and determines a game feature in response to detecting the triggering condition and causes the sound reproduction system to generate a sound feature including a 3D sound effect traveling along a sound path orientated with respect to a listening reference point defined within the listening space to facilitate simulating a game element moving within the listening space. |
| US10163293B2 |
Networked vendor for workplace or controlled environment
Aspects of the invention described herein provide an apparatus and method for networked vending. According to embodiments described herein, a vending machine is provided that may be installed and managed by the venue in which it is installed. Consumers may purchase vending products from the vending machine using cashless accounts managed by an external device in communication with the vendor. The venue may manage the inventory for the vending machine by placing orders for single product inserts to be loaded in the vending machine. |
| US10163289B2 |
Systems and methods for secure lock systems with redundant access control
Systems and methods for providing secure locks having redundant access channels are disclosed. In some embodiments of the invention, the smart lock has a hardware processor, a power source, a cylinder, a button that forms a rose knob, and a rose protector. The rose knob and rose protector protect and conceal the hardware processor, the power source, and the cylinder. The rose protector forms an annular groove that slidably interlocks with the rose knob. The rose knob has a plurality of redundant access channels for receiving authentication information. The redundant access channels may include a biometric scanner for receiving biometric information, a passcode keypad for entering a token, or a wireless transceiver for receiving a token from a mobile device and transmitting a response to the mobile device. When the user cannot open the lock through the first redundant access channel, the smart lock is configured to allow access through a second access channel. |
| US10163288B2 |
Access control using portable electronic devices
To control access to a predetermined service or area, a system receives an activation signal indicative of a user's activation of an access code. As a result of receiving the activation signal, the system sends a verification code to a portable electronic device of the user. An access terminal receives the verification code. Access to the predetermined service or area is granted if the verification code is received at the access terminal meeting one of several predetermined conditions. One condition requires that the verification code is provided to the access terminal within a limited validity time. |
| US10163283B2 |
Method and apparatus for finding and accessing a vehicle fueling station, including an electric vehicle charging station
A control system and method are provided for a station to dispense fuel to a vehicle, including an electric vehicle, without requiring dedicated access to a communications network, with the advantage that authorization for fleet vehicles or individuals can be obtained from an access management system, using a portable, wireless device, such as a smart phone or a dashboard appliance. The authorization is wirelessly relayed to the station by the wireless device, to enable the dispensing of fuel. Subsequently, a log comprising the transaction is provided to the access management system, through the same or a different wireless, mobile computing device. The log may also report status and other events, such as load shedding. |
| US10163280B1 |
Method and system for displaying and using PID graph indicators
An example method includes receiving, at a computing system, parameters from a vehicle, wherein the parameters correspond to a set of associated parameter identifiers (PIDs), and determining, by the computing system, one or more thresholds for one or more PIDs of the set of associated PIDs. The example method additionally includes determining, by the computing system, one or more indicators displayable on a first graph of parameters corresponding to a first PID of the set of associated PIDs. For instance, at least one indicator of the one or more indicators represents a parameter corresponding to a second PID of the set of associated PIDs breaching a threshold associated with the second PID. The example method further includes displaying, by the computing system on a graphical user interface, the first graph of parameters corresponding to the first PID and the one or more indicators on the first graph. |
| US10163273B2 |
Method and system for operating mobile applications in a vehicle
In various embodiments, a user interacts with remotely executing mobile applications from a vehicle. The vehicle may include at least one computer that includes a human machine interface (HMI) for control by the user. The mobile applications may be executing on an application server that is remote from the vehicle and communicating with the at least one computer. Further, the mobile applications may be configured to receive inputs from and transmit outputs to the at least one computer. An HMI application executing on the at least one computer may enable the provisioning of one or more services of the HMI to the mobile applications so that inputs and/or outputs to the mobile applications may be exchanged. Vehicle-based operation of the mobile applications from the at least one computer via the HMI may thus be enabled. |
| US10163271B1 |
System for multimedia spatial annotation, visualization, and recommendation
A system configured to provide a three-dimensional representation of a physical environment. The three-dimensional representation including annotation data associated with particular objects and/or viewpoints of the three-dimensional representation. In some cases, the viewpoints may be rendered using image data associated with a photograph captured from a corresponding viewpoint within the physical environment. |
| US10163269B2 |
Identifying augmented reality visuals influencing user behavior in virtual-commerce environments
Certain embodiments involve enhancing personalization of a virtual-commerce environment by identifying an augmented-reality visual of the virtual-commerce environment. For example, a system obtains a data set that indicates a plurality of augmented-reality visuals generated in a virtual-commerce environment and provided for view by a user. The system obtains data indicating a triggering user input that corresponds to a predetermined user input provideable by the user as the user views an augmented-reality visual of the plurality of augmented-reality visuals. The system obtains data indicating a user input provided by the user. The system compares the user input to the triggering user input to determine a correspondence (e.g., a similarity) between the user input and the triggering user input. The system identifies a particular augmented-reality visual of the plurality of augmented-reality visuals that is viewed by the user based on the correspondence and stores the identified augmented-reality visual. |
| US10163267B2 |
Sharing links in an augmented reality environment
Various embodiments provide methods and systems for users and business owners to share content and/or links to visual elements of a place at a physical location, and, in response to a user device pointing at a tagged place, causing the content and/or links to the visual elements of the place to be presented on the user device. In some embodiments, content and links are tied to specific objects at a place based at least in part upon one of Global Positioning System (GPS) locations, Inertial Measurement Unit (IMU) orientations, compass data, or one or more visual matching algorithms. Once the content and links are attached to the specific objects of the place, they can be discovered by a user with a portable device pointing at the specific objects in the real world. |
| US10163264B2 |
Method and apparatus for multiple mode interface
Each of a world space, a sphere space, and a display space are adapted to accept at least one entity therein, the entity being a virtual reality entity or an augmented reality entity. For world space, translation by a viewer substantially corresponds with translation with respect to world space, and rotation by the viewer substantially corresponds with rotation with respect to world space. For sphere space, translation by the viewer corresponds with substantially zero translation with respect to sphere space, and rotation by the viewer substantially corresponds with rotation with respect to sphere space. For display space, translation by the viewer corresponds with substantially zero translation with respect to display space, and rotation by the viewer corresponds with substantially zero rotation with respect to display space. Exceptions for translating, rotating, and/or resizing any of world space, sphere space, and display space may be invoked. |
| US10163262B2 |
Systems and methods for navigating through airways in a virtual bronchoscopy view
Systems and methods for displaying virtual bronchoscopy views while navigating through an airway of a virtual bronchoscopy are disclosed. The method comprises determining a first location and a first direction at the first location, storing the first location and the first direction in memory, displaying a first virtual camera view corresponding to the first location, determining a second location corresponding to movement through the airway of the virtual bronchoscopy, storing the second location in the memory, displaying a second virtual camera view corresponding to the second location, determining a second direction based on the first location and the second location, storing the second direction in the memory, determining a third location corresponding to further movement through the virtual bronchoscopy, and determining whether the further movement is in a forward direction or a backward direction. |
| US10163260B2 |
Methods and apparatus for building a three-dimensional model from multiple data sets
Methods and apparatus for a map tool displaying a three-dimensional view of a map based on a three-dimensional model of the surrounding environment. The three-dimensional map view of a map may be based on a model constructed from multiple data sets, where the multiple data sets include mapping information for an overlapping area of the map displayed in the map view. For example, one data set may include two-dimensional data including object footprints, where the object footprints may be extruded into a three-dimensional object based on data from a data set composed of three-dimensional data. In this example, the three-dimensional data may include height information that corresponds to the two-dimensional object, where the height may be obtained by correlating the location of the two-dimensional object within the three-dimensional data. |
| US10163254B2 |
Rendering of digital images on a substrate
Techniques and systems are described to render digital images on a defined substrate. In an example, a three-dimensional model is generated of the digital image as disposed on a substrate. Generation of the model includes application of a three-dimensional model of a surface of the substrate to the digital image and addition of material properties of the substrate to the three-dimensional model of the digital image). A viewing direction is detected of the three-dimensional model of the digital image, the detecting based on one or more sensors of the computing device. An effect of light is also ascertained on the three-dimensional model of the digital image having the material properties of the substrate at the detected viewing direction. The three-dimensional model of the digital image is rendered based on the detected viewing direction and the ascertained effect of light for display by the computing device. |
| US10163245B2 |
Multi-mode animation system
Animations are displayed on a user interface (UI) of a computing device using one of multiple different animation system modes, each animation system mode operating in a different manner to determine how to change the display for an animation. The animation can be on a particular object that is displayed by the computing device (e.g., scrolling a list, moving an icon or character from one location to another) and/or can be on the display as a whole (e.g., panning or scrolling a view of the whole display). The multi-mode animation system operates to select an animation system mode on a frame by frame basis. For each frame of content being displayed on the display device, the multi-mode animation system selects an appropriate one of the animation system modes to use for generating the content of that frame. |
| US10163244B2 |
Creating reusable and configurable digital whiteboard animations
Methods and systems for creating animation elements from digital drawings. In particular, one or more embodiments detect a digital drawing input stream including a plurality of strokes. One or more embodiments identify a plurality of stroke points for each stroke from the plurality of strokes, and determine a plurality of timestamps for the plurality of stroke points. One or more embodiments generate an animation element based on the plurality of stroke points and the plurality of timestamps. One or more embodiments also receive a selection to insert the animation element into a user interface, and insert the animation element with associated drawing time information and stroke point information into the user interface in response to the received selection. |
| US10163242B2 |
Energy grid data platform
Techniques are disclosed for an energy grid data platform through which information associated with an electrical grid can be accessed by one or more entities. In some embodiments, an energy grid data platform includes one or more modeling engines configured to receive data associated with an electrical grid and generate data models describing various aspects of the electrical grid. For example an electrical grid model describing the state of the electrical grid at one or more points of connection may be based at least in part on data received from sensors at the edge of the electrical grid. As another example, a physical grid model describing the physical arrangement and logical relationships between physical objects associated with the electrical grid can be generated based at least in part on received imagery data. In some embodiments, aspects of an electrical grid model and physical grid model can be combined into an operational grid model that associates real-time operating information with the certain identified physical objects associated with the electrical grid. Information based on the one or more generated models of the electrical grid can be accessed via the energy grid platform as a cloud-based service, for example, via a web interface or an augmented reality display device. |