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US10164122B2 Semiconductor device with transition metal dichalocogenide hetero-structure
A method includes depositing a first transition metal film having a first transition metal on a substrate and performing a first sulfurization process to the first transition metal film, thereby forming a first transition metal sulfide film. The method further includes depositing a second transition metal film having a second transition metal on the first transition metal sulfide film and performing a second sulfurization process to the second transition metal film, thereby forming a second transition metal sulfide film. The first and the second transition metals are different. The method further includes forming a gate stack, and source and drain features over the second transition metal sulfide film. The gate stack is interposed between the source and drain features. The gate stack, source and drain features, the first transition metal sulfide film and the second transition metal sulfide film are configured to function as a hetero-structure transistor.
US10164114B2 FinFETs and methods of forming FinFETs
An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
US10164113B2 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-κ dielectric layer and a gate electrode. The high-κ dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-κ dielectric layer.
US10164112B2 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate; at least one source/drain feature at least partially disposed in the substrate; an isolation structure disposed on the substrate and includes a first portion; a gate structure disposed on the first portion of the isolation structure and adjacent to the source/drain feature; and at least one gate spacer disposed on a sidewall of the gate structure, in which a top surface of the first portion of the isolation structure is in contact with the gate structure and is higher than a bottommost surface of the gate spacer.
US10164111B2 Semiconductor device and methods of manufacture
A semiconductor device and method of manufacture are provided. In an embodiment a first contact is formed to a source/drain region and a dielectric layer is formed over the first contact. An opening is formed to expose the first contact, and the opening is lined with a dielectric material. A second contact is formed in electrical contact with the first contact through the dielectric material.
US10164110B2 Finfet including improved epitaxial topology
A semiconductor device includes a semiconductor substrate having a plurality of semiconductor fins formed on an upper surface thereof. An epitaxial material is formed on the upper surface of the semiconductor substrate and on an outer surface of the semiconductor fins. The epitaxial material includes an epi upper surface having a lower region that contacts the semiconductor fins and an upper region formed above the lower region. The upper region extends parallel with an upper surface of the semiconductor fins.
US10164109B2 Fin field effect transistor (FinFET) device and method for forming the same
A fin field effect transistor (FinFET) device structure and method for forming the FinFET device structure are provided. The FinFET structure includes a substrate, and the substrate includes a core region and an I/O region. The FinFET structure includes a first etched fin structure formed in the core region, and a second etched fin structure formed in the I/O region. The FinFET structure further includes a plurality of gate stack structures formed over the first etched fin structure and the second etched fin structure, and a width of the first etched fin structure is smaller than a width of the second etched fin structure.
US10164108B2 Fin field effect transistor (FinFET) device and method for forming the same
A fin field effect transistor (FinFET) device structure and method for forming FinFET device structure are provided. The FinFET structure includes a substrate and an isolation structure formed on the substrate. The FinFET structure also includes a fin structure extending above the substrate, and the fin structure is embedded in the isolation structure. The FinFET structure further includes an epitaxial structure formed on the fin structure, the epitaxial structure has a pentagon-like shape, and an interface between the epitaxial structure and the fin structure is lower than a top surface of the isolation structure.
US10164100B2 Formation method and structure semiconductor device with source/drain structures
Structures and formation methods of a semiconductor device are provided. The semiconductor device structure includes a substrate and a gate structure over the substrate. The semiconductor device structure also includes a source/drain structure near the gate structure. The source/drain structure has an inner portion and an outer portion surrounding an entirety of the inner portion. The inner portion has a greater average dopant concentration than that of the outer portion.
US10164099B2 Device with diffusion blocking layer in source/drain region
One illustrative device disclosed herein includes, among other things, a fin defined on a substrate. A gate electrode structure is positioned above the fin in a channel region. A source/drain region is defined in the fin. The source/drain region includes a first epitaxial semiconductor material. The first epitaxial semiconductor material includes a dopant species having a first concentration. A diffusion blocking layer is positioned above the first epitaxial semiconductor material. A second epitaxial semiconductor material is positioned above the diffusion blocking layer. The second epitaxial semiconductor material includes the dopant species having a second concentration greater than the first concentration.
US10164097B2 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least one first isolation structure, at least two second isolation structures, and a plurality of epitaxy structures. The substrate has a plurality of semiconductor fins therein. The first isolation structure is disposed between the semiconductor fins. The semiconductor fins are disposed between the second isolation structures, and the second isolation structures extend into the substrate further than the first isolation structure. The epitaxy structures are respectively disposed on the semiconductor fins. The epitaxy structures are separated from each other, and at least one of the epitaxy structures has a substantially round profile.
US10164094B2 Semiconductor device including memory and logic circuit having FETs with ferroelectric layer and manufacturing methods thereof
A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.
US10164093B2 Semiconductor device including an epitaxy region
An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.
US10164084B2 Semiconductor device and method of manufacturing the same
A semiconductor device includes: an n+-type drain region made of a wide-bandgap semiconductor material; an n-type epitaxial layer provided on the top surface of the drain region; an n-type first semiconductor region provided at an upper portion of the epitaxial layer and having a higher impurity concentration than the epitaxial layer; an n-type second semiconductor region provided on the first semiconductor region and having a higher impurity concentration than the first semiconductor region; p-type base regions surrounding to include an upper portion in the middle of the second semiconductor region; n-type source regions provided at upper portions of the base regions to form a channel; and a gate electrode which controls a surface potentials of the channels.
US10164083B2 Silicon carbide semiconductor device and manufacturing method therefor
A silicon carbide semiconductor device includes an ohmic electrode and a Schottky electrode that are in contact with the drain electrode respectively on the drain electrode and are next to each other; a first conductivity type first withstand voltage holding region in contact with the ohmic electrode on the ohmic electrode; a second conductivity type second withstand voltage holding region in contact with the Schottky electrode on the Schottky electrode and is next to the first withstand voltage holding region; a second conductivity type well region in contact onto the first and second withstand voltage holding regions; a first conductivity type source region selectively provided on a surface layer of the well region; and a gate electrode opposite to a channel region defined by the well region sandwiched between the source region and the first withstand voltage holding region, with a gate oxide film interposed therebetween.
US10164080B2 Electrode pair, method for fabricating the same, substrate for device, and device
Art electrode pair enables the performance of a device to be accurately delivered, a method for manufacturing the same. An electrode pair 10, wherein one electrode 12A and the other electrode 12B are provided on the same plane so as to face each other with a gap 17 therebetween, and portions of the one electrode 12A and the oilier electrode 12B facing each other are respectively curved so as to get away from the plane along a direction nearing each other. This electrode pair 10 is manufactured by preparing, as a sample, a substrate on which a pair of seed electrodes is formed with a space therebetween so as to have an initial gap, immersing the sample in an electroless plating solution, changing the electroless plating solution after a lapse of a certain period of time, and adjusting the number of times of changing.
US10164077B2 Magnetic majority gate device
The disclosed technology relates generally to spintronics, and more particularly to a magnetic majority gate device. In one aspect, a magnetic majority gate device includes a magnetic propagation layer and at least one input transducer. The magnetic propagation layer includes a plurality of magnetic buses configured to guide propagating magnetic domain walls along longitudinal directions corresponding to elongated directions of the magnetic buses. The plurality of magnetic buses includes a plurality of input magnetic buses, where each of the input magnetic buses has a corresponding input site configured to receive a corresponding input magnetic domain wall. At least one input transducer at a corresponding input site is configured to convert a digital input electrical signal into an input magnetic domain wall, such that a magnetization state of the input magnetic domain wall corresponds to a digital logic state of the digital input electrical signal. The at least one input transducer is configured to inject an in-plane electrical current into the corresponding input magnetic bus if the digital logic state is a predetermined digital logic state. The magnetic propagation layer includes a central region at which the magnetic buses converge and are joined together, such that the central region is configured for an interaction of input magnetic domain walls guided by two or more magnetic buses. The central region includes at least one magnetic constriction configured to locally restrict propagation of propagating magnetic domain walls.
US10164072B2 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
US10164068B2 FinFET structure and method for fabricating the same
A method comprises removing a portion of a fin to form a trench over a lower portion of the fin, wherein the lower portion is formed of a first semiconductor material, growing a second semiconductor material in the trench to form a middle portion of the fin, forming a first carbon doped layer over the middle portion of the fin, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin, replacing outer portions of the upper portion of the fin with a second carbon doped layer and drain/source regions, wherein the first carbon doped layer and the second carbon doped layer are separated by the upper portion of the fin and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.
US10164064B2 FinFETs with low source/drain contact resistance
An integrated circuit structure includes a semiconductor substrate, insulation regions extending into the semiconductor substrate, with the insulation regions including first top surfaces and second top surfaces lower than the first top surfaces, a semiconductor fin over the first top surfaces of the insulation regions, a gate stack on a top surface and sidewalls of the semiconductor fin, and a source/drain region on a side of the gate stack. The source/drain region includes a first portion having opposite sidewalls that are substantially parallel to each other, with the first portion being lower than the first top surfaces and higher than the second top surfaces of the insulation regions, and a second portion over the first portion, with the second portion being wider than the first portion.
US10164060B2 Work function metal fill for replacement gate fin field effect transistor process
A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.
US10164059B2 FinFET device and fabricating method thereof
A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
US10164058B2 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device with a high radiation tolerance is provided. A semiconductor device comprising a semiconductor substrate, a first body region and a second body region provided on a front surface side of the semiconductor substrate, a neck portion provided between the first body region and the second body region, a first source region formed within the first body region and a second source region formed within the second body region, a first gate electrode provided to face the first body region between the first source region and the neck portion, a second gate electrode provided to face the second body region between the second source region and the neck portion, and an insulating film continuously provided between the first gate electrode and the semiconductor substrate, between the second gate electrode and the semiconductor substrate, and on the front surface side of the neck portion, is provided.
US10164056B2 Vertical field effect transistors with uniform threshold voltage
Provided is a method for forming a semiconductor structure. In one or more embodiments of the invention, the method includes forming a semiconductor fin on a substrate and decreasing a width of the semiconductor fin. The method further includes forming a spacer layer on a surface of the substrate and forming a high dielectric constant layer on exposed surfaces of the semiconductor fin and the spacer layer. The method also includes forming a work function metal layer on the high dielectric constant layer. The method also includes removing portions of the work function metal layer and the high dielectric constant layer to expose portions of the spacer layer. A thickness of the remaining work function metal layer on sidewalls of the semiconductor fin is uniform.
US10164054B2 Compound semiconductor field effect transistor with self-aligned gate
A compound semiconductor field effect transistor (FET) may include a channel layer. The semiconductor FET may also include an oxide layer, partially surrounded by a passivation layer, on the channel layer. The semiconductor FET may also include a first dielectric layer on the oxide layer. The semiconductor FET may also include a second dielectric layer on the first dielectric layer. The semiconductor FET may further include a gate, comprising a base gate through the oxide layer and the first dielectric layer, and a head gate in the second dielectric layer and electrically coupled to the base gate.
US10164051B2 Method of cutting metal gate
A method for fabricating a semiconductor device includes forming a first fin and a second fin on a substrate, forming a first metal-gate line over a first and a second gate regions, applying a first line-cut to separate the first metal-gate line into a first sub-metal gate line and a second sub-metal gate line and forming a second metal-gate line over the first sub-metal gate line and the second sub-metal gate line, applying a second line-cut to separate the second metal-gate line into a third sub-metal gate line and a fourth sub-metal gate line such that a gap is formed between the third sub-metal gate line and the fourth sub-metal gate line and forming an isolation region within the gap.
US10164050B2 Structure and formation method of semiconductor device structure with gate stack
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a gate electrode over the semiconductor substrate. The semiconductor device structure also includes a source/drain structure adjacent to the gate electrode. The semiconductor device structure further includes a spacer element over a sidewall of the gate electrode, and the spacer element has an upper portion having a first exterior surface and a lower portion having a second exterior surface. Lateral distances between the first exterior surface and the sidewall of the gate electrode are substantially the same. Lateral distances between the second exterior surface and the sidewall of the gate electrode increase along a direction from a top of the lower portion towards the semiconductor substrate.
US10164049B2 Structure and formation method of semiconductor device with gate stack
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.
US10164047B2 High electron mobility transistor structure
A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
US10164046B2 Method for manufacturing semiconductor structure
A method for manufacturing a semiconductor structure includes forming a first dielectric layer on a gate structure and a source drain structure. A recess is formed at least partially in the first dielectric layer. A protection layer is formed at least on a sidewall of the recess. The recess is deepened to expose the source drain structure. A bottom conductor is formed in the recess and is electrically connected to the source drain structure. The protection layer is removed to form a gap between the bottom conductor and the sidewall of the recess.
US10164042B2 Semiconductor device and manufacturing method thereof
A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.
US10164040B2 Gate structure and method for fabricating the same
A method comprises doping a lower portion of a nanowire to form a first drain/source region, wherein the nanowire is formed over a substrate, doping an upper portion of the nanowire to form a second drain/source region, doping a middle portion of the nanowire to form a channel region, wherein the channel region is between the first drain/source region and the second drain/source region, forming a ring-shaped gate structure surrounding a lower portion of the channel region, wherein the ring-shaped gate structure comprises a vertical portion of a first work-function metal layer and depositing a low-resistivity gate metal layer over a horizontal portion of the first work-function metal layer, wherein the low-resistivity gate metal layer is electrically coupled to the vertical portion of the first work-function metal layer through the horizontal portion of the first work-function metal layer.
US10164038B2 Method of implanting dopants into a group III-nitride structure and device formed
A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.
US10164028B2 Thin film transistor, manufacturing method therefor, oxide back plate and display apparatus
Provided are a thin film transistor, a manufacturing method therefor, an oxide back plate and a display apparatus. The thin film transistor comprises: an oxide active layer (4) and source and drain electrodes (6a, 6b) connected to the oxide active layer (4), wherein the source and drain electrodes (6a, 6b) comprise a main portion (M) and a connective portion (C), the main portion (M) being isolated from the active layer (4), and being electrically connected to the active layer (4) via the connective portion (C), and an electrical resistivity of the connective portion (C) is greater than that of the main portion (M). In the thin film transistor provided above, since the main portions of the source and drain electrodes are not in contact with the oxide active layer, a metal with a relatively high electrical conductivity can be used as the source and drain electrodes, without having a relatively great impact on the electrical performance of the oxide active layer.
US10164025B2 Semiconductor device having termination trench
A semiconductor device comprises a semiconductor substrate structure comprising a cell region and an edge termination region surrounding the cell region. Further it comprises a plurality of needle-shaped cell trenches within the cell region reaching from a surface of the semiconductor substrate structure into the substrate structure and an edge termination trench within the edge termination region surrounding the cell region at the surface of the semiconductor substrate structure.
US10164020B2 Semiconductor device and method manufacturing the same
A semiconductor device may include an n− type layer disposed at a first surface of an n+ type silicon carbide substrate; a p− type region, a p type region, an n+ type region, and a p+ type region disposed at an upper portion in the n− type layer; a gate electrode and a source electrode disposed on the n− type layer and insulated from each other; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the source electrode is in contact with the p− type region, the n+ type region, and the p+ type region, and the source electrode may include an ohmic junction region disposed at a contact portion of the source electrode and the n+ type region and the contact portion of the source region and the p+ type region and a Schottky junction region disposed at the contact portion of the source electrode and the p− type region.
US10164015B2 Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
US10164011B2 Nitride semiconductor device
A nitride semiconductor device includes a substrate; a nitride semiconductor layered structure disposed on the substrate and having a channel region; a first electrode and a second electrode both disposed on the nitride semiconductor layered structure; a first p-type nitride semiconductor layer disposed between the first electrode and the second electrode; and a first gate electrode disposed on the first p-type nitride semiconductor layer. The nitride semiconductor layered structure includes a first recess. The first p-type nitride semiconductor layer is at least partially disposed inside the first recess, and is separated from a side surface of the first recess.
US10164010B1 Finfet diffusion break having protective liner in fin insulator
Methods form integrated circuit structures that include a semiconductor layer having at least one fin. At least three gate stacks contact, and are spaced along, the top of the fin. An insulator in trenches in the fin contacts the first and third of the gate stacks, and extends into the fin from the first and third gate stacks. Source and drain regions in the fin are adjacent a second of the gate stacks. The second gate stack is between the first and third gate stacks along the top of the fin. Additionally, a protective liner is in the trench between a top portion of the insulator a bottom portion of the insulator.
US10164003B2 MIM capacitor and method of forming the same
A method of forming a metal-insulator-metal capacitor is provided. The method includes forming a first metal plate over a semiconductor substrate, forming a first dielectric layer with a first dielectric constant on a surface of the first metal plate, forming a second dielectric layer with a second dielectric constant on a surface of the first dielectric layer, forming a third dielectric layer with a third dielectric constant on a surface of the second dielectric layer, and forming a second metal plate on a surface of the third dielectric layer. The second dielectric constant is different from the first dielectric constant and different from the third dielectric constant.
US10163999B2 Display device
A display device includes a substrate including a display area and a peripheral area disposed around the display area. The peripheral area includes a bending region and a contact region adjacent to the bending region. A first connection line includes a first portion disposed in the contact region, and a second portion disposed in both the bending region and the contact region, and including a first layer and a second layer. At least part of the second layer of the second portion overlaps the first layer of the second portion. In the contact region, the first layer of the second portion is electrically connected to the first portion, and the second layer of the second portion is electrically connected to the first layer of the second portion.
US10163994B2 OLED panel manufacturing method and OLED panel
The invention provides an OLED panel manufacturing method and OLED panel. The method comprises: forming first (21) and second (22) pixel electrodes inside each pixel unit (2); depositing an insulation film by an atomic layer deposition method, and patternizing to form a pixel electrode isolation insulation layer (3); the pixel electrode isolation insulation layer having a longitudinal portion (31) filling between the first (21) and second (22) pixel electrodes, and a latitudinal portion (32) having both ends covering respectively a part of the first pixel electrode (21) closer to the second pixel electrode (22) and a part of the second pixel electrode (22) closer to the first pixel electrode (21); forming a pixel isolation layer (4), and printing LOED elements (5); the invention can increase OLED panel resolution without changing printing accuracy so that the first (21) and second (22) pixel electrodes are completely insulated.
US10163992B2 Large area mirror display and method of manufacturing the same
A mirror display device includes a mirror module and a display module. The mirror module includes a transparent substrate and a plurality of first mirror patterns. The transparent substrate has a first region and a second region adjacent to the first region. The first mirror patterns are disposed on a surface of the transparent substrate in the first region. The display module includes a display part that emits a light and a plurality of second mirror patterns. The display module is combined with the mirror module on the surface of the transparent substrate in the second region.
US10163989B2 Display device and electronic device
A display device that has an excellent visibility even under strong light is provided. In the display device, a first display element that reflects visible light and a second display element that emits visible light are between a first substrate and a second substrate. The display device can display an image with high visibility by operating the first display element under strong light and operating the second display element under weak light. Furthermore, a first surface of the second substrate is provided with a touch sensor, and a second surface opposite to the first surface is provided with an anti-reflection layer. Such a structure can sufficiently reduce reflection of external light on the display surface under strong light, further increasing the visibility.
US10163988B2 Light-emitting apparatus, method for forming light-emitting apparatus, and display apparatus
The present invention provides a light-emitting apparatus, a method for forming a light-emitting apparatus, and a display apparatus. The light-emitting apparatus comprises at least one OLED light-emitting unit and at least one quantum dot light-emitting unit, wherein the at least one quantum dot light-emitting unit and the at least one OLED light-emitting unit are arranged in series.
US10163987B2 Display device and manufacturing method of a display device
A manufacturing method of a display device according to an embodiment of the present invention includes: the display device including a protection plate having a light transmitting part facing an input or output device, and a display substrate having a display area, a light emitting film forming the step of forming an island-like light emitting film containing a light emitting material, in an area other than the display area in the display substrate; an alignment step of aligning the protection plate and the display substrate with each other; and an attaching step of attaching the protection plate to the display substrate.
US10163985B2 Subpixel arrangement structure for display device
A subpixel arrangement structure for a display device includes a plurality of unit pixels each having a red subpixel, a green subpixel, and a blue subpixel. The red, green, and blue subpixels form a delta arrangement. Green subpixels are disposed on a plurality of first subpixel arrangement lines, each of which extends along a direction of a first axis. Two red subpixels and two blue subpixels are alternately disposed along the first axis direction on a plurality of second subpixel arrangement lines. Each of the plurality of second subpixel arrangement lines is positioned between every two of the plurality of first subpixel arrangement lines and extends along the first axis direction.
US10163984B1 Display with embedded components and subpixel windows
A display may have an array of pixels. Each pixel may have a light-emitting diode such as an organic light-emitting diode. The organic light-emitting diodes may each have an anode that is coupled to a thin-film transistor pixel circuit for controlling the anode. Transparent windows may be formed in the display. The windows may be formed by replacing subpixels in some of the pixels with transparent windows. When subpixels are replaced by transparent windows, adjacent subpixels may be overdriven to compensate for lost light from the replaced subpixels. Adjacent subpixels may also be enlarged to help compensate for lost light. An array of electrical components such as an array of light sensors may be aligned with the transparent windows and may be used to measure light passing through the transparent windows.
US10163983B1 Complementary resistance switchable filler and nonvolatile complementary resistance switchable memory comprising the same
A resistance-switchable material containing: an insulating support; and a complementary resistance switchable filler dispersed in the insulating support, wherein the complementary resistance switchable filler has a core-shell structure containing: a wire-type conductive core containing a conductive material; and an insulating shell formed on the surface of the core and containing an insulating material. Because a first resistive layer, a conductive layer and a second resistive layer are formed as one layer and bipolar conductive filaments are formed on the substantially different resistive layers, the memory can exhibit complementary resistive switching characteristics. In addition, the complementary resistance switchable memory of the present disclosure can be prepared through a simplified process at low cost by introducing a simple process of coating a paste in which a complementary resistance switchable filler and a supporting material are mixed.
US10163980B2 Resistive memory array and fabricating method thereof
A method of fabricating a resistive memory array includes forming a plurality of insulators and a conductive structure on a first substrate, performing a resistor-forming process to transform the insulators into a plurality of resistors, polishing the conductive structure to expose a plurality of contact points respectively electrically connected to the resistors, providing a second substrate having a plurality of transistors and a plurality of interconnect pads, bonding respectively the interconnect pads and the contact points, and removing the first substrate from the resistors and the conductive structure.
US10163978B2 Memory cell with independently-sized elements
Memory cell architectures and methods of forming the same are provided. An example memory cell can include a switch element and a memory element formed in series with the switch element. A smallest lateral dimension of the switch element is different than a smallest lateral dimension of the memory element.
US10163977B1 Chalcogenide memory device components and composition
Systems, devices, and methods related to or that employ chalcogenide memory components and compositions are described. A memory device, such as a selector device, may be made of a chalcogenide material composition. A chalcogenide material may have a composition that includes one or more elements from the boron group, such as boron, aluminum, gallium, indium, or thallium. A selector device, for instance, may have a composition of selenium, arsenic, and at least one of boron, aluminum, gallium, indium, or thallium. The selector device may also be composed of germanium or silicon, or both. The relative amount of boron, aluminum, gallium, indium, or thallium may affect a threshold voltage of a memory component, and the relative amount may be selected accordingly. A memory component may, for instance have a composition that includes selenium, arsenic, and some combination of germanium, silicon, and at least one of boron, aluminum, gallium, indium, or thallium.
US10163975B2 Light emitting apparatus
A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at least one semiconductor light emitting device disposed on the top surface of the light-transmissive substrate, a reflective part disposed over the semiconductor light emitting device to reflect light from the semiconductor light emitting device toward the light-transmissive substrate, and a first wavelength converter disposed between the light-transmissive substrate and the reflective part.
US10163972B2 Image sensing device with photon blocking layer and anti-reflective coating
A method of forming a semiconductor image sensing device includes: providing a semiconductor substrate; forming a radiation sensitive region and a peripheral region in the semiconductor substrate, wherein the peripheral region surrounds the radiation sensitive region and includes a top surface projected from a backside of the semiconductor substrate and a sidewall coplanar with a sidewall of the semiconductor substrate and perpendicular to the top surface; forming a photon blocking spacer in the peripheral region, wherein the photon blocking spacer covers a portion of the sidewall of the peripheral region; and forming an anti reflective coating adjacent to the photon blocking layer.
US10163971B2 Image sensor, image capturing apparatus, and forming method
An image sensor comprising a plurality of pixels, each of at least part of the plurality of pixels comprises: a plurality of photoelectric conversion parts; a microlens; and a plurality of interlayer lenses formed between the plurality of photoelectric conversion parts and the microlens and integrally formed to correspond to the plurality of photoelectric conversion parts. The plurality of interlayer lenses cause light incident on the plurality of interlayer lenses to enter the corresponding plurality of photoelectric conversion parts.
US10163969B2 X-ray sensor and method of manufacturing the same
This invention relates to a direct conversion X-ray sensor and to a method of manufacturing the same. This X-ray sensor includes an array substrate including a pixel electrode formed so as to protrude from a surface thereof at a pixel region; a photoconductive substrate including an upper electrode, and a photoconductive layer formed on a surface of the upper electrode so as to be in contact with the pixel electrode and having a PIN diode structure; and a bonding material filling a space around a contact region of the pixel electrode and the photoconductive layer so as to bond the array substrate and the photoconductive substrate.
US10163968B2 Multi-junction pixel image sensor with dielectric reflector between photodetection layers
Some embodiments provide a color image sensor and color image sampling method that uses multiple-layer pixels and is capable of producing color images without using absorption color filters (e.g., such as employed in conventional CFAs). In accordance with some embodiments of the color image sensor device and color image sampling method, frequency-dependent reflectors are incorporated between the photodetection layers of multiple-layer (e.g., two layer) pixels.
US10163964B2 Solid-state imaging element, imaging device, and electronic device
The present technology relates to a solid-state imaging element, an imaging device, and an electronic device that can improve transfer efficiency of a charge accumulation unit (MEM) and can increase the number of saturation electrons Qs. In a case where a charge voltage conversion unit (FD) is connected to a center of a charge accumulation unit (MEM) in each pixel and pixels are arrayed in an array, a column in which photoelectric conversion units (PD) are arrayed and a column including charge voltage conversion units (FD) and pixel transistors are arrayed in parallel. The present technology can be applied to a CMOS image sensor.
US10163959B2 Image sensor and method for manufacturing the same
An image sensor structure and a method for forming the same are provided. The image sensor structure includes a substrate having a front side and a backside and a light-sensing region formed in the substrate. The image sensor structure further includes a front side isolation structure formed at the front side of the substrate and a backside isolation structure formed at the back side of the substrate.
US10163951B2 Image sensor device
In some embodiments, the present disclosure relates to an image sensor device. The image sensor device has an isolation well region surrounding a photodetector arranged within a substrate at a first depth. A gate stack is arranged over the isolation well region along a first surface of the substrate. The gate stack defines an edge. A doped isolation feature is arranged within the substrate at a second depth between the isolation well region and the gate stack. The gate stack is vertically over an active area. The doped isolation feature extends from the edge of the gate stack to under the gate stack.
US10163947B2 Photodiode gate dielectric protection layer
In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method is performed by forming a gate dielectric layer over a substrate, and selectively forming a gate material over the gate dielectric layer. A gate dielectric protection layer is formed over the gate dielectric layer, and a first sidewall spacer is formed over the gate dielectric protection layer and flanking a side of the gate material. The gate dielectric protection layer continuously extends from between the first sidewall spacer and the gate dielectric layer to outside of the first sidewall spacer.
US10163945B2 Printable device wafers with sacrificial layers
Methods of forming integrated circuit devices include forming a sacrificial layer on a handling substrate and forming a semiconductor active layer on the sacrificial layer. The semiconductor active layer and the sacrificial layer may be selectively etched in sequence to define an semiconductor-on-insulator (SOI) substrate, which includes a first portion of the semiconductor active layer. A multi-layer electrical interconnect network may be formed on the SOI substrate. This multi-layer electrical interconnect network may be encapsulated by an inorganic capping layer that contacts an upper surface of the first portion of the semiconductor active layer. The capping layer and the first portion of the semiconductor active layer may be selectively etched to thereby expose the sacrificial layer. The sacrificial layer may be selectively removed from between the first portion of the semiconductor active layer and the handling substrate to thereby define a suspended integrated circuit chip encapsulated by the capping layer.
US10163937B2 Pixel structure and fabricating method thereof
A pixel structure includes a scan line, a data line, a bump, an active device, and a pixel electrode electrically connected to the active device. The active device includes a gate, a semiconductor layer, a gate insulation layer between the gate and the semiconductor layer, a source, and a drain. The bump has a top surface and side surfaces in periphery of the top surface. The gate covers the bump and electrically connects the scan line. The semiconductor layer is on the top surface and the side surfaces. The source is on at least one of the side surfaces, in contact with the semiconductor layer, and electrically connected to the data line. The drain is on the top surface and in contact with the semiconductor layer, and the drain does not cover the semiconductor layer on a corner section of the bump between the top surface and the side surfaces.
US10163934B2 Fully-depleted silicon-on-insulator transistors
A fully-depleted silicon-on-insulator (FDSOI) semiconductor structure includes: a first PFET, a second PFET, and a third PFET each having a different threshold voltage and each being over an n-well that is biased to a first voltage; and a first NFET, a second NFET, and a third NFET each having a different threshold voltage and each being over a p-type substrate that is biased to a second voltage. The second voltage is different than the first voltage.
US10163932B1 Memory device based on heterostructures of ferroelectric and two-dimensional materials
A ferroelectric random-access memory structure and processes for fabricating a ferroelectric random-access memory structure are described that includes using a molybdenum sulfide layer. In an implementation, a ferroelectric random-access memory structure in accordance with an exemplary embodiment includes at least one FeFET, which further includes a substrate; a back gate electrode formed on the substrate, the back gate electrode including a conductive layer; a gate dielectric substrate formed on the back gate electrode; a source electrode formed on the gate dielectric substrate; a drain electrode formed on the gate dielectric substrate; and a layered transition metal dichalcogenide disposed on the gate dielectric substrate and contacting the source electrode and the drain electrode.
US10163928B2 Memory having memory cell string and coupling components
Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.
US10163925B2 Integrated circuit device
An integrated circuit device includes a first and a second semiconductor regions, a first electrode provided above the first semiconductor region, a second electrode provided above the second semiconductor region, a first and a second interconnects. The first and the second semiconductor regions are arranged to be separated from each other in a first direction. Longitudinal directions of the first and second semiconductor regions are a second direction. Longitudinal directions of the first and second electrode are a third direction. The first and second interconnects extend in the first direction and are provided in a region including a region directly above the first electrode and a region directly above the second electrode. The first interconnect is connected to the first electrode. The second interconnect is connected to the second electrode.
US10163922B2 Semiconductor device and method of manufacturing the semiconductor device
In a MONOS memory, withstand voltage is increased between a control gate electrode over an ONO film having a charge accumulating part and a semiconductor substrate. When a silicon film is processed to form a control gate electrode, dry etching is performed for a relatively long time, thereby a recess is formed in a sidewall of the control gate electrode. Subsequently, the control gate electrode is subjected to dry oxidation treatment to form an insulating film on the sidewall of the control gate electrode including the recess, thereby an end of the bottom of the control gate electrode is separated from an end of the top of the ONO film.
US10163920B2 Memory device and memory cell
A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.
US10163918B2 Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate including a plurality of active regions divided by a plurality of trenches, a plurality of tunnel insulating layer patterns formed over the active regions, a plurality of conductive film patterns formed over the tunnel insulating film patterns, a plurality of first isolation layers formed on sidewalls and bottom surfaces of the trenches, and a plurality of second isolation layers formed between the conductive film patterns.
US10163916B2 Compact anti-fuse memory cell using CMOS process
A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N-well and an anti-fuse cell formed on the N-well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N-well, an oxide layer deposited on the N-well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.
US10163914B2 Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails
A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.
US10163904B1 Semiconductor device structure
A semiconductor device structure is provided. The semiconductor device structure includes a first circuit, a second circuit, and a dielectric dummy gate over a substrate. The first circuit includes a first N-type fin field-effect transistor (FinFET) and a first P-type fin field-effect transistor (FinFET). The second circuit includes a second N-type fin field-effect transistor (FinFET) and a second P-type fin field-effect transistor (FinFET) beside the second N-type FinFET. The dielectric dummy gate is positioned on a common boundary portion shared by the first circuit and the second circuit. The dielectric dummy gate includes a first portion and a second portion. The first portion is positioned between the first N-type FinFET and the second N-type FinFET and formed of a first strain material. The second portion is positioned between the first P-type FinFET and the second P-type FinFET and formed of a second strain material.
US10163898B2 FinFETs and methods of forming FinFETs
An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a first portion of the isolation region being between the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a gate seal spacer on sidewalls of the gate structure, a first portion of the gate seal spacer being on the first portion of the isolation region between the first fin and the second fin, and a source/drain region on the first fin and the second fin adjacent the gate structure.
US10163897B2 Inter-level connection for multi-layer structures
Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a second device layer and an inter-level connection structure. The first device layer includes a first conductive layer and a first dielectric layer formed on the first conductive layer, the first device layer being formed on a substrate. The second device layer includes a second conductive layer, the second device layer being formed on the first device layer. The inter-level connection structure includes one or more conductive materials and configured to electrically connect to the first conductive layer and the second conductive layer, the inter-level connection structure penetrating at least part of the first dielectric layer. The first conductive layer is configured to electrically connect to a first electrode structure of a first semiconductor device within the first device layer.
US10163896B2 Integrated circuit having a MOM capacitor and method of making same
An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
US10163893B1 Apparatus containing circuit-protection devices
Apparatus including an array of memory cells may include circuit-protection devices that may include first and second circuit-protection units, a first gate having a first source/drain connected to a first node of the first circuit-protection unit, and a second gate having a first source/drain connected to a first node of the second circuit-protection unit, wherein a second source/drain of the first gate is connected to a second source/drain of the second gate.
US10163892B2 Silicon controlled rectifiers (SCR), methods of manufacture and design structures
Silicon controlled rectifiers (SCR), methods of manufacture and design structures are disclosed herein. The method includes forming a common P-well on a buried insulator layer of a silicon on insulator (SOI) wafer. The method further includes forming a plurality of silicon controlled rectifiers (SCR) in the P-well such that N+ diffusion cathodes of each of the plurality of SCRs are coupled together by the common P-well.
US10163890B2 Semiconductor device
A semiconductor device provided herein includes: a semiconductor substrate; an upper main electrode located above the semiconductor substrate; a sense anode electrode located above the semiconductor substrate; a first resistance layer located above the semiconductor substrate, having resistivity higher than resistivities of the upper main electrode and the sense anode electrode, and connecting the upper main electrode and the sense anode electrode; and a lower main electrode located below the semiconductor substrate. The semiconductor substrate includes a switching element and a sense diode. The switching element is connected between the upper main electrode and the lower main electrode. The sense diode includes a p-type first anode region connected to the sense anode electrode and an n-type first cathode region connected to the lower main electrode.
US10163889B2 Phase shifter
A phase shifter includes a signal input, a signal output, an ESD protection circuit, first and second signal paths between the signal input and the signal output. The ESD protection circuit includes first and second two port devices, each two port device being switchable between a high impedance state and a low impedance state. The first signal path includes the first two port device of the ESD protection circuit and a first delay line configured to provide a first phase shift to a signal transmitted from the signal input to the signal output via the first signal path. The second signal path includes the second two port device of the ESD protection circuit and a second delay line configured to provide a second phase shift, different from the first phase shift, to the signal transmitted from the signal input to the signal output via the second signal path.
US10163888B2 Self-biased bidirectional ESD protection circuit
Disclosed examples provide an ESD protection circuit including a protection structure to selectively conduct current between a first terminal at a protected node and a second terminal at a reference node in response to the protected node voltage and a control voltage signal rising above a trigger voltage during an ESD event, and a bias circuit configured to bias a protection structure control terminal at a control voltage corresponding to a higher one of a first voltage of the first terminal and a second voltage of the second terminal to control the trigger voltage of the ESD protection structure to keep the ESD protection structure off during normal operation.
US10163887B2 Method and structure for semiconductor mid-end-of-line (MEOL) process
A semiconductor device includes a first gate stack over an insulator, a second gate stack over an active region, a first dielectric layer over the first and second gate stacks, a second dielectric layer over the first dielectric layer, and a metal layer over the first and second gate stacks. The first and second dielectric layers include different materials. The metal layer contacts the second gate stack by penetrating at least the first and second dielectric layers and is isolated from the first gate stack by at least the first and second dielectric layers.
US10163886B2 Strapping structure of memory circuit
A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping line segment electrically coupled with a pass device of the first memory cell; and a second word line strapping line segment. The second memory cell includes a first word line strapping line segment; and a second word line strapping line segment electrically coupled with a pass device of the second memory cell. The first word line strapping line segment of the first memory cell and the first word line strapping line segment of the second memory cell are connected with each other at a first interconnection layer. The second word line strapping line segment of the first memory cell and the second word line strapping line segment of the second memory cell are connected with each other at the first interconnection layer.
US10163884B1 Cell architecture with intrinsic decoupling capacitor
An IC includes an array of cells and a first set of endcap cells. The array of cells includes a first set of Mx layer power interconnects coupled to a first voltage, a first set of Mx layer interconnects, a second set of Mx layer power interconnects coupled to a second voltage source, and a second set of Mx layer interconnects. The first set of endcap cells includes first and second sets of Mx+1 layer interconnects. The first set of Mx+1 layer interconnects is coupled to the first set of Mx layer power interconnects and to the second set of Mx layer interconnects to provide a first set of decoupling capacitors. The second set of Mx+1 layer interconnects is coupled to the second set of Mx layer power interconnects and to the first set of Mx layer interconnects to provide a second set of decoupling capacitors.
US10163882B2 Semiconductor device and layout thereof
A semiconductor device includes a substrate and fins. The fins are formed on a first area and a second area of the substrate. The first area includes a first recess. The second area is located with respect to the first area. The first recess is disposed at a side of the first area, and faces the second area. A projection area of the first recess on a side of the second area is substantially flat.
US10163880B2 Integrated circuit and method of fabricating the same
A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.
US10163877B2 System in package process flow
A method comprises connecting a substrate having a plurality of integrated circuit (IC) dies to a package substrate, so that the package substrate extends beyond at least two edges of the substrate, leaving first and second edge portions of the package substrate having exposed contacts. The first and second edge portions meet at a first corner of the package substrate. At least a first upper die package is placed over the substrate, so that first and second edge portions of the first upper die package extend beyond the at least two edges of the substrate. Pads on the first and second edge portions of the first upper die package are connected to the contacts of the first and second edge portions of the package substrate.
US10163876B2 Semiconductor structure and manufacturing method thereof
A method of manufacturing a structure includes: providing a substrate; forming an adhesive layer over the substrate; forming an interconnect layer comprising a metal line and a metal via over the adhesive layer; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the first semiconductor die being spaced apart from the conductive pillars; bonding a second semiconductor die with the conductive pillars; and removing the substrate and the adhesive layer to expose a conductive portion of the interconnect layer.
US10163875B2 Method for forming chip package structure with adhesive layer
A method for forming a chip package structure is provided. The method includes forming a chip on an adhesive layer. The chip has a front surface and a back surface opposite to the front surface. The back surface is in direct contact with the adhesive layer. A first maximum length of the adhesive layer is less than a second maximum length of the chip. The method includes forming a molding compound layer surrounding the chip and the adhesive layer. A first bottom surface of the adhesive layer is substantially coplanar with a second bottom surface of the molding compound layer. The method includes forming a redistribution structure over the chip and the molding compound layer.
US10163873B2 Package-on-package (PoP) device with integrated passive device in a via
A package for a use in a package-on-package (PoP) device and a method of forming is provided. The package includes a substrate, a polymer layer formed on the substrate, a first via formed in the polymer layer, and a material disposed in the first via to form a first passive device. The material may be a high dielectric constant dielectric material in order to form a capacitor or a resistive material to form a resistor.
US10163869B2 Transferring method, manufacturing method, device and electronic apparatus of micro-LED
The present invention discloses a transferring method, a manufacturing method, a device and an electronics apparatus of micro-LED. The method for transferring micro-LED at wafer level comprises: temporarily bonding micro-LEDs on a laser-transparent original substrate onto a carrier substrate via a first bonding layer; irradiating the original substrate with laser, to lift-off selected micro-LEDs; performing a partial release on the first bonding layer, to transfer the selected micro-LEDs to the carrier substrate; temporarily bonding the micro-LEDs on the carrier substrate onto a transfer head substrate via a second bonding layer; performing a full release on the first bonding layer, to transfer the micro-LEDs to the transfer head substrate; bonding the micro-LEDs on the transfer head substrate onto a receiving substrate; and removing the transfer head substrate by releasing the second bonding layer, to transfer the micro-LEDs to the receiving substrate.
US10163867B2 Semiconductor package and manufacturing method thereof
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.
US10163866B2 Semiconductor device and method of manufacture
A semiconductor device and method that utilize a surface device are provided. In an embodiment a fuse line comprises an underbump metallization which has two separate, electrically isolated parts. The two parts are bridged by an external connector, such as a solder ball in order to electrically connect the surface device. When, after testing, the surface device is determined to be defective, the fuse line may be disconnected by removing the external connector from the two separate parts, electrically isolating the surface device. In another embodiment the surface is located beneath a package within an integrated fan out package or is part of a multi-fan out package.
US10163864B1 Vertically stacked wafers and methods of forming same
The disclosure is directed to an integrated circuit stack and method of forming the same. In one embodiment, the integrated circuit stack may include: a plurality of vertically stacked wafers, each wafer including a back side and a front side, the back side of each wafer including a through-semiconductor-via (TSV) within a substrate, and the front side of each wafer including a metal line within a first dielectric, wherein the metal line is connected with the TSV within each wafer; and an inorganic dielectric interposed between adjacent wafers within the plurality of vertically stacked wafer; wherein the plurality of vertically stacked wafers are stacked in a front-to-back orientation such that the TSV on the back side of one wafer is electrically connected to the metal line on the front side of an adjacent wafer by extending through the inorganic dielectric interposed therebetween.
US10163863B2 Recessed and embedded die coreless package
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a cavity in a plating material to hold a die, attaching the die in the cavity, forming a dielectric material adjacent the die, forming vias in the dielectric material adjacent the die, forming PoP lands in the vias, forming interconnects in the vias, and then removing the plating material to expose the PoP lands and die, wherein the die is disposed above the PoP lands.
US10163861B2 Semiconductor package for thermal dissipation
A first package is bonded to a first substrate with first external connections and second external connections. The second external connections are formed using materials that are different than the first external connections in order to provide a thermal pathway from the first package. In a particular embodiment the first external connections are solder balls and the second external connections are copper blocks.
US10163858B1 Semiconductor packages and manufacturing methods thereof
Semiconductor packages and manufacturing methods thereof are provided. One of the semiconductor packages includes a first chip, a second chip and a molding compound. The first chip has at least one first via and a protection layer thereon, and the at least one first via is formed in the protection layer. The second chip has at least one second via thereon. The molding layer encapsulates the first and second chips. The at least one second via is disposed in and contact with the molding layer, and top surfaces of the protection layer, the at least one first via and the at least one second via are substantially coplanar with a top surface of the molding layer.
US10163855B2 Semiconductor device and manufacturing method thereof
An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various electronic devices, and methods of making thereof, that comprise a permanently coupled carrier that enhances reliability of the electronic devices.
US10163853B2 Formation method of chip package
Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes forming a package layer to surround the first chip structure and the second chip structure after the formation of the release film. In addition, the method includes removing the release film such that the top surface of the first chip structure, the top surface of the second chip structure, and a top surface of the package layer are exposed.
US10163851B2 Tri-layer CoWoS structure
A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
US10163850B2 Semiconductor device
A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.
US10163848B2 Semiconductor package
A semiconductor package, a manufacturing method for the semiconductor package and a printing module used thereof are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias, a polymeric cover film covering the molding compound and the die and polymeric dam structures disposed aside the connectors. The polymeric cover film and the polymeric dam structures are formed by printing.
US10163847B2 Method for producing semiconductor package
A method for producing a semiconductor package is a method for producing a semiconductor package in which a plurality of semiconductor chips, each of which includes a substrate, conductive portions formed on the substrate, and microbumps formed on the conductive portions, are laminated, which includes a heating process of causing a reducing gas to flow in an inert atmosphere into a space where the semiconductor chips are arranged and heated at or higher than a temperature of a melting point of the microbump, and in the heating process, a pressure application member is mounted on the microbump.
US10163845B2 Method and apparatus for measuring a free air ball size during wire bonding
Disclosed is a method of measuring a free air ball size during a wire bonding process of a wire bonder, which comprises a position sensor and a bonding tool for forming an electrical connection between a semiconductor device and a substrate using a bonding wire. Specifically, the method comprises the steps of: forming a free air ball from a wire tail of the bonding wire; using the position sensor to determine a positional difference between a first and a second position of the bonding tool with respect to a reference position, wherein the first position of the bonding tool is a position of the bonding tool with respect to the reference position when the free air ball contacts a conductive surface; and measuring the free air ball size based on the positional difference of the bonding tool as determined by the position sensor. A wire bonder configured to perform such a method is also disclosed.
US10163843B2 Semiconductor device structure and manufacturing method
A semiconductor device structure and a manufacturing method are provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the semiconductor substrate. The semiconductor device structure also includes a conductive trace over the dielectric layer. The semiconductor device structure further includes a conductive feature over the conductive trace, and a width of the conductive feature is substantially equal to or larger than a maximum width of the conductive trace. In addition, the semiconductor device structure includes a conductive bump over the conductive feature.
US10163840B2 Methods of fluxless micro-piercing of solder balls, and resulting devices
A method of establishing conductive connections is disclosed. The method includes providing an integrated circuit die having a plurality of solder balls each of which has an oxide layer on an outer surface of the solder ball. The method also includes performing a heating process to heat at least the solder balls and applying a force causing each of a plurality of piercing bond structures on a substrate to pierce one of the solder balls and its associated oxide layer to thereby establish a conductive connection between the solder ball and the piercing bond structure.
US10163839B2 Bump on pad (BOP) bonding structure in semiconductor packaged device
The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints.
US10163833B2 Multichip modules and methods of fabrication
In a multi-chip module (MCM), a “super” chip (110N) is attached to multiple “plain” chips (110F′ “super” and “plain” chips can be any chips). The super chip is positioned above the wiring board (WB) but below at least some of plain chips (110F). The plain chips overlap the super chip. Further, the plain chips' low speed IOs can be connected to the WB by long direct connections such as bond wires (e.g. BVAs) or solder stacks; such connections can be placed side by side with the super chip. Such connections can be long, so the super chip is not required to be thin. Also, if through-substrate vias (TSVs) are omitted, the manufacturing yield is high and the manufacturing cost is low. Other structures are provided that combine the short and long direct connections to obtain desired physical and electrical properties.
US10163827B1 Package structure with protrusion structure
A package structure is provided. The package structure includes a dielectric layer formed over a first substrate and a conductive layer formed in the dielectric layer. The package structure includes an under bump metallurgy (UBM) layer formed over the dielectric layer, and the UBM layer is electrically connected to the conductive layer. The package structure also includes a first protrusion structure formed over the UBM layer, and the first protrusion structure extends upward away from the UBM layer. The package structure further includes a second protrusion structure formed over the UBM layer, and the second protrusion structure extends upward away from the UBM layer. The package structure includes a first conductive connector formed over the first protrusion structure; and a second conductive connector formed over the second protrusion structure. An air gap is formed between the first protrusion structure and the second protrusion structure.
US10163824B2 Integrated fan-out package and method of fabricating the same
An integrated fan-out package including an insulating encapsulation, a radio frequency integrated circuit (RF-IC), an antenna, a ground conductor, and a redistribution circuit structure is provided. The integrated circuit includes a plurality of conductive terminals. The RF-IC, the antenna, and the ground conductor are embedded in the insulating encapsulation. The ground conductor is between the RF-IC and the antenna. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the conductive terminals, the antenna, and the ground conductor. A method of fabricating the integrated fan-out package is also provided.
US10163822B2 Chip-on-substrate packaging on carrier
A method includes mounting a wafer-level package substrate over a carrier, and pre-cutting the wafer-level package substrate to form trenches extending from a top surface of the wafer-level package substrate into the wafer-level package substrate. A plurality of dies is bonded over the wafer-level package substrate. The plurality of dies is molded in a molding material to form a wafer-level package, with the wafer-level package including the wafer-level package substrate, the plurality of dies, and the molding material. The carrier is detached from the wafer-level package. The wafer-level package is sawed into a plurality of packages, with each of the plurality of packages including a portion of the wafer-level package substrate and one of the plurality of dies.
US10163818B2 Package structure and method for forming the same
A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer.
US10163816B2 Structure and formation method of chip package with lid
Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate. The chip package also includes a lid over the semiconductor die. The lid has a number of support structures bonded with the substrate, and the lid has one or more openings between two of the support structures.
US10163813B2 Chip package structure including redistribution structure and conductive shielding film
A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a grounding line in the dielectric structure. The grounding line includes a main portion and an end enlarged portion connected to the main portion and laterally accessible from the dielectric structure. The chip package structure includes a chip structure over the redistribution structure. The chip package structure includes a conductive shielding film disposed over the chip structure and a first sidewall of the end enlarged portion. The conductive shielding film is electrically connected to the grounding line. A thickness of the end enlarged portion increases from the main portion to the conductive shielding film.
US10163812B2 Device having substrate with conductive pillars
A device includes a substrate that includes conductive structures and has a first surface that is opposite to a second surface. Conductive pillars are built up over and electrically coupled to at least one of the conductive structures. An integrated circuit is disposed over the first surface and electrically coupled to the conductive structures. A molding compound is formed over the first surface of the substrate.
US10163811B2 Semiconductor package structure based on cascade circuits
A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a low-voltage enhancement type semiconductor transistor comprising a source electrode, a gate electrode and a drain electrode; a shell comprising a cavity for receiving the high-voltage depletion type semiconductor transistor and the low-voltage enhancement type semiconductor transistor, and a high-voltage terminal, a first low-voltage terminal and a second low-voltage terminal; and cascade circuits comprising a supporting sheet having a conductive surface. The source electrode of the high-voltage depletion type transistor and the drain electrode of the low-voltage enhancement type semiconductor transistor are fixed to the conductive surface of the supporting sheet and electrically connected to each other through the conductive surface of the supporting sheet. A side of the supporting sheet away from the conductive surface is fixed to the cavity of the shell.
US10163810B2 Electromagnetic interference shielding for system-in-package technology
Embodiments are generally directed to electromagnetic interference shielding for system-in-package technology. An embodiment of a system-in-package includes a substrate; chips and components attached to the substrate; dielectric molding over the chips and components; and an electromagnetic interference (EMI) shield. The EMI shield formed from a conductive paste, and the EMI shield provides a combined internal EMI shield between chips and components of the system in package and external EMI shield for the system-in-package.
US10163809B2 Shielding for through-silicon-via noise coupling
In some embodiments, an integrated circuit device includes a semiconductor substrate. An active area is disposed in the semiconductor substrate. A first guard ring is disposed in the semiconductor substrate and entirely surrounds the active area. The first guard ring has a first conductivity type. A via penetrates through the semiconductor substrate and is spaced apart from the active area such that the via is disposed outside of the first guard ring. A second guard ring is disposed in the semiconductor substrate and entirely surrounds the via and the first guard ring. The second guard ring has the first conductivity type and is disjoint from the first guard ring.
US10163808B2 Module with embedded side shield structures and method of fabricating the same
A module includes a circuit package and a top external shield layer. The circuit package includes multiple electronic components on a substrate; at least one side shield structure located at a corresponding at least one side edge region of the circuit package and electrically connected to ground, the at least one side shield structure being positioned on the substrate or on a pad on the substrate; and a molded compound disposed over the substrate, the electronic components, and the at least one side shield structure. The top external shield layer is disposed on a top outer surface of the circuit package and is electrically connected to ground. The at least one side shield structure and the top external shield layer provide an external shield of the module configured to protect the circuit package from external electromagnetic radiation and environmental stress.
US10163807B2 Alignment pattern for package singulation
A method includes forming an alignment pattern over an insulating layer formed over a carrier. A die is mounted over the carrier and encapsulated. Connectors are formed and the structure is attached to a debond tape. The carrier is removed. A cutting device is aligned to a backside of the insulating layer using the alignment pattern. The first insulating layer and encapsulant are cut from the backside of the insulating layer. Another method includes scanning a backside of a packages structure for an alignment pattern in a first package area of the packages structure. A cutting device is aligned to a cut-line in a non-package area of the packages structure based on the alignment pattern and packages are singulated. An InFO package includes an insulating layer on the backside, the insulating layer having a laser marking thereon. The InFO package also includes an alignment pattern proximate to the insulating layer.
US10163804B2 Molding structure for wafer level package
A method in which microelectronic devices are attached to a substrate surface, wherein spaces interpose neighboring ones of the microelectronic devices. Each microelectronic device has an outermost surface that is substantially parallel to the substrate surface. The substrate is closed in a transfer molding cavity of a transfer molding apparatus such that an internal surface of the transfer molding cavity contacts a substantial portion of each of the outermost surfaces of the microelectronic devices. A molding compound is subsequently injected into the transfer molding cavity, including into the spaces between ones of the plurality of microelectronic devices.
US10163803B1 Integrated fan-out packages and methods of forming the same
Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first die, at least one through integrated fan-out via and a molding layer. The at least one through integrated fan-out via is aside the first die and includes a seed layer and a metal layer. The molding layer encapsulates the at least one through integrated fan-out via and the first die. Besides, the seed layer surrounds a sidewall of the metal layer and is between the metal layer and the molding layer.
US10163797B2 Forming interlayer dielectric material by spin-on metal oxide deposition
A plurality of high-k metal gate (HKMG) structures is formed over a substrate. The (HKMG) structures are separated by a plurality of gaps. The HKMG structures each include a first dielectric layer at an upper surface of the HKMG structure. The gaps are filled with a first conductive material. A portion of the first conductive material is removed in each of the gaps through an etching-back process. A metal oxide layer is formed using a spin-on deposition process. The metal oxide layer is formed over the (HKMG) structures and over the first conductive material. A second dielectric layer is formed over the metal oxide layer. An opening is etched in the second dielectric layer. The opening is etched through the second dielectric layer and through the metal oxide layer. The opening is filled with a second conductive material.
US10163794B2 Capping layer for improved deposition selectivity
The present disclosure relates to an integrated chip having a back-end-of-the-line (BEOL) metal interconnect structure with capping layers that provide for improved reliability. In some embodiments, the integrated chip has a dielectric layer disposed over a semiconductor substrate, and one or more metal layer structures disposed within the dielectric layer. A first capping layer is located over the dielectric layer at positions between the one or more metal layer structures, so that the first capping layer is located along an interface having the one or more metal layer structures interspersed between the first capping layer. A second capping layer is located over the one or more metal layer structures. An etch stop layer is arranged over the first capping layer and the second capping layer and laterally surrounds the second capping layer.
US10163790B2 Manufacturing method of a semiconductor device and method for creating a layout thereof
A method for manufacturing a semiconductor device of one embodiment of the present invention includes: forming an insulation layer to be processed over a substrate; forming a first sacrificial layer in a first area over the substrate, the first sacrificial layer being patterned to form in the first area a functioning wiring connected to an element; forming a second sacrificial layer in a second area over the substrate, the second sacrificial layer being patterned to form in the second area a dummy wiring; forming a third sacrificial layer at a side wall of the first sacrificial layer and forming a fourth sacrificial layer at a side wall of the second sacrificial layer, the third sacrificial layer and the fourth sacrificial layer being separated; forming a concavity by etching the insulation layer to be processed using the third sacrificial layer and the fourth sacrificial layer as a mask; and filling a conductive material in the concavity.
US10163786B2 Method of forming metal interconnection
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first conductive feature; a dielectric layer surrounding sidewalls of the second conductive feature; and a first barrier layer interposed between the second conductive feature and the dielectric layer and in physical contact with both the second conductive feature and the dielectric layer. The first barrier layer and the dielectric layer comprise at least two common elements.
US10163783B1 Reduced area efuse cell structure
An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
US10163780B2 Wireless charging package with chip integrated in coil center
A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die. A coil extends from the top surface to a bottom surface of the encapsulating material, and the device die is in the region encircled by the coil. At least one dielectric layer is formed over the encapsulating material and the coil. A plurality of redistribution lines is in the at least one dielectric layer. The coil is electrically coupled to the device die through the plurality of redistribution lines.
US10163778B2 Structure and formation method of damascene structure
A structure and a formation method of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive feature over the semiconductor substrate. The semiconductor device structure also includes a dielectric layer over the conductive feature and the semiconductor substrate. The semiconductor device structure further includes a conductive via surrounded by the dielectric layer and electrically connected to the conductive feature. The conductive via has a lower end and an upper end larger than the lower end, and the conductive via has a side surface curved inward.
US10163776B2 Designing method of capacitive element in multilayer wirings for integrated circuit devices based on statistical process
Disclosed herein is a capacitive element formed by multilayer wirings, wherein a total capacitance, intralayer capacitance and interlayer capacitance are calculated for a plurality of device structures by changing parameters relating to the multilayer wirings in an integrated circuit, a device structure is identified, from among the plurality of device structures, whose difference in the total capacitance between the device structures is equal to or less than a predetermined level and at least either of whose ratio of the intralayer capacitance to the total capacitance or ratio of the interlayer capacitance to the total capacitance satisfies a predetermined condition, and the parameters of the device structure satisfying the predetermined condition are determined as the parameters of the multilayer wirings.
US10163772B2 Stacked semiconductor device structure and method
A stacked semiconductor device structure includes a first semiconductor device having a first major surface and a second major surface opposite to the first major surface. The second major surface includes a recessed region bounded by sidewall portions, and the sidewall portions have outer surfaces defining peripheral edge segments of the first semiconductor device. A first conductive layer is disposed adjoining at least portions of the recessed region. A second semiconductor device having a third major surface and a fourth major surface opposite to the third major surface includes a first portion that is electrically connected to the first conductive layer within the recessed region, and at least a portion of the second semiconductor device is disposed within the recessed region.
US10163771B2 Interposer device including at least one transistor and at least one through-substrate via
In a particular aspect, a device includes a substrate including at least one through-substrate via. A metal structure is disposed on a surface of the substrate. The device further includes a semiconductor layer bonded to the substrate. The semiconductor layer includes at least one complimentary metal-oxide-semiconductor (CMOS) transistor and a metal disposed within a second via. The metal is in direct contact with the metal structure.
US10163770B2 Fan-out package structure and method
A device comprises a semiconductor structure in a molding compound layer, a first polymer layer on the molding compound layer, a second polymer layer on the first polymer layer, a first interconnect structure having a first via portion in the first polymer layer and a first metal line portion in the second polymer layer, a third polymer layer on the second polymer layer, a fourth polymer layer on the third polymer layer and a second interconnect structure having a second via portion in the third polymer layer and a second metal line portion in the fourth polymer layer, wherein the second via portion is vertically aligned with the first via portion.
US10163768B2 Semiconductor structure and method of manufacturing the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar.
US10163767B2 Semiconductor package
A semiconductor package includes a substrate, a conductive layer, a first surface mount device (SMD) and a bonding wire. The substrate has a t top surface. The first conductive layer is formed on the top surface and has a first conductive element and a first pad separated from each other. The first SMD is mounted on the first pad, overlapping with but electrically isolated from the first conductive element. The first bonding wire electrically connects the first SMD with the first conductive layer.
US10163760B2 Semiconductor device, semiconductor device manufacturing method and semiconductor device mounting structure
A semiconductor device includes a plurality of die pad sections, a plurality of semiconductor chips, each of which is arranged in each of the die pad sections, a resin encapsulation portion having a recess portion for exposing at least a portion of the die pad sections, the resin encapsulation portion configured to cover the die pad sections and the semiconductor chips, and a heat radiation layer arranged in the recess portion. The heat radiation layer includes an elastic layer exposed toward a direction in which the recess portion is opened. The heat radiation layer directly faces at least a portion of the die pad sections. The elastic layer overlaps with at least a portion of the die pad sections when seen in a thickness direction of the heat radiation layer.
US10163753B2 Method for forming interconnect structure of semiconductor device
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an opening in the dielectric layer. The method also includes forming a catalyst layer over a sidewall of the opening and forming a conductive element directly on the catalyst layer. The catalyst layer is capable of lowering a formation temperature of the conductive element. The method further includes removing a portion of the conductive element such that the conductive element is within a space surrounded by the catalyst layer.
US10163747B2 Semiconductor device and method of controlling warpage in reconstituted wafer
A semiconductor device has a substrate with a plurality of active semiconductor die disposed over a first portion of the substrate and a plurality of non-functional semiconductor die disposed over a second portion of the substrate while leaving a predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die. The predetermined area of the substrate devoid of the active semiconductor die and non-functional semiconductor die includes a central area, checkerboard pattern, linear, or diagonal area of the substrate. The substrate can be a circular shape or rectangular shape. An encapsulant is deposited over the active semiconductor die, non-functional semiconductor die, and substrate. An interconnect structure is formed over the semiconductor die. The absence of active semiconductor die and non-functional semiconductor die from the predetermined areas of the substrate reduces bending stress in that area of the substrate.
US10163745B2 Package with tilted interface between device die and encapsulating material
A method includes forming a polymer layer covering a metal via in a wafer, grooving the wafer to form a trench, wherein the trench extends from a top surface of the polymer layer into the wafer, and performing a die-saw on the wafer to separate the wafer into a plurality of device dies. A kerf passes through the trench. One of the device dies is placed over a carrier. An encapsulating material is dispensed over and around the device die. The method further includes pressing and curing the encapsulating material. After the encapsulating material is cured, a sidewall of the polymer layer is tilted. A planarization is performed on the encapsulating material until the polymer layer and the metal via are exposed. A redistribution line is formed over and electrically coupled to the metal via.
US10163743B2 Copper flanged air cavity packages for high frequency devices
An air cavity package includes a flange and a pedestal extending upward from the flange. A dielectric frame is joined to the flange and surrounds the pedestal. The semiconductor die is placed on the pedestal, which reduces the length of the wires joining the die to the leads of the air cavity package.
US10163724B2 Integrated circuit device and method of manufacturing same
An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved protection for the bottom portion of the gate structure. In some embodiments, the method achieves improved protection for gate structure bottom by forming a recess on either side of the gate structure and placing spacers on the side walls of the gate structure, so that the spacers protect the portion of the gate structure below the gate dielectric layer.
US10163721B2 Hybridization fin reveal for uniform fin reveal depth across different fin pitches
A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.
US10163720B2 Method of forming source/drain contact
Methods for fabricating semiconductor devices are disclosed. An exemplary method includes forming first spacers along sidewalls of a gate structure that is disposed over a substrate and between source/drain features. A first dielectric layer is formed over the substrate and recessed to expose upper portions of the first spacers. A spacer layer is then formed over the upper portions of the first spacers. A second dielectric layer is formed over the spacer layer, and a patterned masking layer is formed over the second dielectric layer. The second dielectric layer, the spacer layer, and the first dielectric layer are patterned. For example, exposed portions of the second dielectric layer, the spacer layer (forming second spacers disposed along the upper portions of the first spacers), and the first dielectric layer are etched to form a trench exposing the gate structure and the source/drain features. The trench is filled with a conductive material.
US10163718B2 Semiconductor device and a method for fabricating the same
In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
US10163716B2 Symmetric tunnel field effect transistor
The present disclosure relates to semiconductor structures and, more particularly, to a symmetric tunnel field effect transistor and methods of manufacture. The structure includes a gate structure including a source region and a drain region both of which comprise a doped VO2 region.
US10163711B2 Methods of packaging semiconductor devices including placing semiconductor devices into die caves
Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a carrier wafer, providing a plurality of dies, and forming a die cave material over the carrier wafer. A plurality of die caves is formed in the die cave material. At least one of the plurality of dies is placed within each of the plurality of die caves in the die cave material. A plurality of packages is formed, each of the plurality of packages being formed over a respective at least one of the plurality of dies.
US10163710B2 Method of manufacturing semiconductor device by applying molding layer in substrate groove
A method of forming a semiconductor package includes depositing a passivation layer overlying a semiconductor substrate, wherein the semiconductor substrate includes a scribe line region positioned between a first chip region and a second chip region. The method further includes forming a bump overlying the passivation layer on at least one of the first chip region or the second chip region, wherein the bump comprises a copper pillar and a cap layer. The method further includes forming a groove passing through the passivation layer on the scribe line region, wherein the groove extends into the semiconductor substrate to expose a stepped sidewall of the semiconductor substrate. The method further includes applying a molding compound layer to cover the passivation layer and a lower portion of the bump and fill the groove. The method further includes singulating along the scribe line region.
US10163708B2 Integrated antenna on interposer substrate
Some embodiments relate to a semiconductor module having an integrated antenna structure. The semiconductor module has an excitable element and a first ground plane disposed between a substrate and the excitable element. A second ground plane is separated from the first ground plane by the substrate. The second ground plane is coupled to the first ground plane by one or more through-substrate vias (TSVs) that extend through the substrate.
US10163706B2 Alignment marks in substrate having through-substrate via (TSV)
A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
US10163705B2 Profile of through via protrusion in 3DIC interconnect
An interconnect structure for an integrated circuit, such as a three dimensional integrated circuit (3DIC), and a method of forming the same is provided. An example interconnect structure includes a substrate, a through via extending through the substrate, and a liner disposed between the substrate and the through via. The substrate includes a tapered profile portion. The tapered profile portion abuts the liner.
US10163703B2 Method for forming self-aligned contact
A method for forming a self-aligned contact is provided. In an embodiment, a metal gate is formed on a substrate, and a gate spacer is formed adjacent the metal gate. A conductive plug is formed over the substrate, with the gate spacer disposed between the metal gate and the conductive plug. The metal gate and the conductive plug are recessed. A first dielectric layer is deposited over the gate spacer, over the metal gate, over the conductive plug, and along sidewalls of the metal gate. A first opening is formed in the first dielectric layer exposing the metal gate, and a second opening is formed in the first dielectric layer exposing the conductive plug. The first opening and the second opening are filled with a first conductive material.
US10163699B2 Cu wiring forming method and semiconductor device manufacturing method
A method of forming, on a substrate having on a surface thereof a film having a trench of a preset pattern and a via at a bottom of the trench, a Cu wiring by burying Cu or Cu alloy in the trench and the via includes forming a barrier film (process 2); forming, on a surface of the barrier film, a wetting target layer of Ru or the like (process 3); forming, on a surface of the wetting target layer, a Cu-based seed film by PVD (process 4); filling the via by heating the substrate and flowing the Cu-based seed film into the via (process 5); and forming, on the substrate surface, a Cu-based film made of the Cu or Cu alloy by PVD under a condition where the Cu-based film is flown on the wetting target layer to bury the Cu-based film in the trench (process 6).
US10163698B2 Interconnect structure and manufacturing method thereof
A method for manufacturing a semiconductor comprises: providing a substrate; forming an opening in a dielectric layer disposed over the substrate; providing a target with a first type atoms; ionizing the first type atoms provided from the target; providing a bias to the substrate for controlling the moving paths of the ionized first type atoms thereby directing the ionized first type atoms in the opening; and forming a first conductive structure from bottom of the opening with the ionized first type atoms under a pre-determined frequency and a pre-determined pressure.
US10163696B2 Selective cobalt removal for bottom up gapfill
Exemplary methods for removing cobalt material may include flowing a chlorine-containing precursor into a processing region of a semiconductor processing chamber. The methods may include forming a plasma of the chlorine-containing precursor to produce plasma effluents. The methods may also include contacting an exposed region of cobalt with the plasma effluents. The exposed region of cobalt may include an overhang of cobalt on a trench defined on a substrate. The plasma effluents may produce cobalt chloride at the overhang of cobalt. The methods may include flowing a nitrogen-containing precursor into the processing region of the semiconductor processing chamber. The methods may further include contacting the cobalt chloride with the nitrogen-containing precursor. The methods may also include recessing the overhang of cobalt.
US10163692B2 Structure and formation method of interconnection structure of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a substrate having a first top surface, and an interconnection line over the first top surface of the substrate. The interconnection line has a sidewall. The semiconductor device structure also includes a first spacer over the sidewall of the interconnection line. The first spacer has a first concave surface which concaves towards the sidewall of the interconnection line. The semiconductor device structure further includes a dielectric layer covering the substrate, the interconnection line and the first spacer.
US10163686B2 Thermal sensor arrangement and method of making the same
A temperature sensor arrangement in an integrated circuit (IC) includes a sensor array configured to determine a temperature of the IC. The sensor array includes a first transistor having a first terminal, a second terminal and a gate. The temperature sensor array further includes a guard ring region between the sensor array and another circuit of the IC. The guard ring region includes a transistor structure having a first terminal, a second terminal and a gate. The temperature sensor arrangement further includes a thermally conductive element connected to the transistor structure and a first terminal of the first transistor. The thermally conductive element is configured to provide a thermally conductive path from the transistor structure to the first terminal of the first transistor.
US10163684B2 Fabrication of silicon germanium-on-insulator FinFET
A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.
US10163678B2 Sinker with a reduced width
Forming a semiconductor structure by forming a plurality of trenches in a semiconductor material, forming a plurality of non-conductive structures in the plurality of trenches, and forming a doped region of the first conductivity type. The plurality of trenches are spaced apart from each other, have substantially equal depths, and include a first trench and a second trench. The plurality of non-conductive structures include a first non-conductive structure in the first trench and a second non-conductive structure in the second trench. The doped region is formed between the first non-conductive structure and the second non-conductive structure. No region of a second conductivity type lies horizontally in between the first non-conductive structure and the second non-conductive structure.
US10163677B2 Electrically insulated fin structure(s) with alternative channel materials and fabrication methods
Semiconductor structures and fabrication methods are provided which includes, for instance, fabricating a semiconductor fin structure by: providing a fin structure extending above a substrate, the fin structure including a first fin portion, a second fin portion disposed over the first fin portion, and an interface between the first and the second fin portions, where the first fin portion and the second fin portion are lattice mismatched within the fin structure; and modifying, in part, the fin structure to obtain a modified fin structure, the modifying including selectively oxidizing the interface to form an isolation region within the modified fin structure, where the isolation region electrically insulates the first fin portion from the second fin portion, while maintaining structural stability of the modified fin structure.
US10163676B2 Apparatus and system for preventing backside peeling defects on semiconductor wafers
A apparatus includes a susceptor and a non-reactive gas source. The susceptor has through holes and a wafer support surface. Each through hole includes a lift pin and a lift pin head. The lift pin has a vertical degree of motion in the through hole to lift up or place a wafer on the susceptor. The lift pin head has at least one flow channel structure running from its first surface at least partially exposed to a bottom side of the susceptor through its second surface exposed to a top side of the susceptor wherein the lift pin. The non-reactive gas source is configured to flow a gas to a backside of the wafer through the flow channel structure through the bottom side of the susceptor.
US10163672B2 Substrate processing device, method for controlling substrate processing device, and storage medium storing programs
A substrate processing device for processing a substrate, comprising: an image sensor for detecting positions of two corners on at least one diagonal line of a substrate when the substrate is moved to a predetermined position; an illuminating device that can be disposed so as to illuminate the two corners of the substrate on an opposite side of the substrate at the predetermined position to the image sensor; and a control device for determining the position of the substrate, based on the positions of the two corners detected by the image sensor.
US10163668B2 Thermal dynamic response sensing systems for heaters
A heater system includes a heater assembly, an imaging device and a control system. The heater assembly includes a plurality of heating zones. The imaging device acquires an image of the heater assembly. The control system determines variations in the plurality of heating zones based on the thermal image.
US10163667B2 Linear wafer drive for handling wafers during semiconductor fabrication
A modular cluster tool is disclosed. According to one embodiment, a system, comprises a wafer transfer station that includes a first vacuum chamber that stores a plurality of semiconductor wafers. The system also includes an equipment front end module interface, and two or more shuttle lock interfaces.
US10163666B2 Temperature control system for semiconductor manufacturing system
Provided is a temperature control system configured to mix a low temperature heating medium and a high temperature heating medium to supply the heating mediums at a temperature according to a process recipe to an electrostatic chuck (ESC) configured to maintain a temperature and support a wafer in a chamber in which a semiconductor wafer processing process is performed, and a heating medium obtained by mixing a heating medium cooled through a thermoelectric element and a heating medium heated through a heater to a desired target temperature according to a first ratio and a second ratio is provided to a load and recovered from the load, and the heating medium is distributed to the thermoelectric element and the heater according to the first ratio and the second ratio, which are ratios upon the mixing, optimizing power consumption for cooling or heating.
US10163664B2 Substrate cleaning apparatus and substrate cleaning method
A substrate cleaning apparatus (50) that cleans a substrate (S) includes: circumference supporting members (51) that support and rotate the substrate (S); a sponge (541) having a cleaning surface that is brought into contact with the surface to be cleaned of the substrate (S) being rotated by the circumference supporting members (51), and cleans the surface to be cleaned; an arm (53) that moves the sponge (541) in a radial direction of the substrate (S) while maintaining the cleaning surface in contact with the surface to be cleaned; and a controller (60) that controls the contact pressure of the cleaning surface on the surface to be cleaned. When the sponge (541) is located near the edge of the substrate (S), the controller (60) adjusts the contact pressure to a smaller value than that of when the sponge (541) is located near the center of the substrate (S).
US10163660B2 Sensor device with media channel between substrates
A sensor device including: a first substrate having a bottom surface and a top surface; a second substrate having a bottom surface and a top surface, a media channel having two vertical sections and a horizontal section, wherein the two vertical sections are through the second substrate, a portion of the bottom surface of the second substrate forms a top surface of the horizontal section, and a portion of the top surface of the first substrate forms a bottom surface of the horizontal section; a sensor chip disposed on one of the two vertical sections of the media channel; and a molding compound covering side surfaces of the first substrate, the second substrate, and the sensor chip.
US10163659B1 Fin-type field effect transistor and method of forming the same
A FinFET and a method of forming the same are provided. The FinFET includes a substrate, a buffer layer, an insulating layer, a fin and a gate. A buffer layer is disposed over the substrate, and includes a recess without penetrating the buffer layer. The insulating layer is disposed over the buffer layer, and includes a plurality of isolation structures and a trench between the isolation structures. The fin is disposed in the recess of the buffer layer and the trench of the insulating layer. The gate is disposed across the fin.
US10163658B2 Semiconductor package with multiple molding routing layers and a method of manufacturing the same
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.
US10163655B2 Through substrate via liner densification
Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through substrate via through at least a portion of a substrate, forming a first liner layer in the through substrate via, and densifying the first liner layer. The example method may further include forming a second liner layer on the first liner layer, and densifying the second liner layer.
US10163652B2 Mechanisms for forming patterns using multiple lithography processes
The present disclosure provides a method for forming patterns in a semiconductor device. In accordance with some embodiments, the method includes providing a substrate and a patterning-target layer formed over the substrate; forming a first cut pattern in a first hard mask layer formed over the patterning-target layer; forming a second cut pattern in a second hard mask layer formed over the patterning layer, the first hard mask layer having a different etching selectivity from the second hard mask layer; selectively removing a portion of the second cut pattern in the second hard mask layer and a portion of the patterning-target layer within a first trench; and selectively removing a portion of the first cut pattern in the first hard mask layer and a portion of the patterning-target layer within a second trench.
US10163645B2 Method for processing wide-bandgap semiconductor substrate and apparatus therefor
There are provided a processing method for a wide-bandgap semiconductor substrate and an apparatus therefor that use no abrasives or no abrasive grains, or no solution having a large environmental burden at all, can process a single crystal, which is SiC, GaN, AlGaN, or AlN, at a variety of processing speed, can obtain a surface of higher quality than the quality of a surface finished by CMP, and also have an excellent compatibility with a clean room. A catalytic substance having a function of promoting the direct hydrolysis of a work piece (5) or promoting the hydrolysis of an oxide film on the surface of the work piece is used as a processing reference plane (3). In the presence of water (1), the work piece is brought into contact with or extremely close to the processing reference plane at a predetermined pressure.
US10163644B2 Interconnect structure including a conductive feature and a barrier layer on sidewalls and a bottom surface of the conductive feature and method of forming the same
An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
US10163641B2 Memory with a raised dummy feature surrounding a cell region
A semiconductor structure includes a semiconductor substrate, at least one raised dummy feature, and at least one memory cell. The raised dummy feature is present on the semiconductor substrate and defines a cell region and a non-cell region outside of the cell region on the semiconductor substrate, and the raised dummy feature has at least one opening communicating the cell region with the non-cell region. The memory cell is present on the cell region.
US10163632B2 Material composition and process for substrate modification
Provided is a material composition and method for substrate modification. A substrate is patterned to include a plurality of features. The plurality of features includes a first subset of features having one or more substantially inert surfaces. In various embodiments, a priming material is deposited over the substrate, over the plurality of features, and over the one or more substantially inert surfaces. By way of example, the deposited priming material bonds at least to the one or more substantially inert surfaces. Additionally, the deposited priming material provides a modified substrate surface. After depositing the priming material, a layer is spin-coated over the modified substrate surface, where the spin-coated layer is substantially planar.
US10163631B2 Polymer resin comprising gap filling materials and methods
In accordance with an embodiment a bottom anti-reflective layer comprises a surface energy modification group which modifies the surface energy of the polymer resin to more closely match a surface energy of an underlying material in order to help fill gaps between structures. The surface energy of the polymer resin may be modified by either using a surface energy modifying group or else by using an inorganic structure.
US10163628B1 Lattice-mismatched semiconductor substrates with defect reduction
A structure includes a substrate including a first semiconductor material; a dielectric feature embedded in the substrate; and a second semiconductor material embedded in the substrate, the second semiconductor material having lattice mismatch to the first semiconductor material, the second semiconductor material having two upper sidewalls and two lower sidewalls, the two upper sidewalls in contact with the dielectric feature, the two lower sidewalls in contact with the substrate, the two lower sidewalls being non-perpendicular to a top surface of the substrate, a bottommost portion of the dielectric feature being lower than a topmost portion of the two lower sidewalls.
US10163626B2 Metal gate structure and manufacturing method thereof
An NMOS transistor gate structure includes at least one spacer defining a gate region over a semiconductor substrate, a gate dielectric layer disposed on the gate region and lining an inner sidewall of the spacer, a bottom barrier layer conformally disposed on the gate dielectric layer, a work function metal layer disposed on the bottom barrier layer, and a filling metal partially wrapped by the work function metal layer. The bottom barrier layer has an oxygen concentration higher than a nitrogen concentration. The bottom barrier layer is in direct contact with the gate dielectric layer. The bottom barrier layer includes a material selected from Ta, TaN, TaTi, TaTiN and a combination thereof.
US10163622B2 Substrate cleaning method, substrate processing method, substrate processing system and semiconductor device manufacturing method
Disclosed is a substrate cleaning method. In this substrate cleaning method, a step (step 10) is performed wherein a removal target film and located above a processing target film is patterned; after step 10, a step (step 11) is performed wherein the patterned removal target film is used as an etching mask to perform anisotropic etching on the processing target film; after step 11, a step (step 12) is performed wherein the remaining removal target film on the processing target film is subjected to gas chemical etching; and after step 12, a step (step 14) is performed wherein a target substrate, which includes the surface of the processing target film, is irradiated with gas clusters, thereby cleaning the surface of the processing target film by removing non-reactive or non-volatile residues remaining on the surface of the processing target film.
US10163621B1 Method and structure for FinFET devices
A semiconductor device and a method of forming the same are disclosed. The method includes receiving a semiconductor substrate and a fin extending from the semiconductor substrate; forming multiple dielectric layers conformally covering the fin, the multiple dielectric layers including a first charged dielectric layer having net fixed first-type charges and a second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges, the first-type charges having a first sheet density and the second-type charges having a second sheet density, the first charged dielectric layer being interposed between the fin and the second charged dielectric layer; patterning the multiple dielectric layers, thereby exposing a first portion of the fin, wherein a second portion of the fin is surrounded by at least a portion of the first charged dielectric layer; and forming a gate structure engaging the first portion of the fin.
US10163620B2 Continuous-wave laser-sustained plasma illumination source
An optical system for generating broadband light via light-sustained plasma formation includes a chamber, an illumination source, a set of focusing optics, and a set of collection optics. The chamber is configured to contain a buffer material in a first phase and a plasma-forming material in a second phase. The illumination source generates continuous-wave pump illumination. The set of focusing optics focuses the continuous-wave pump illumination through the buffer material to an interface between the buffer material and the plasma-forming material in order to generate a plasma by excitation of at least the plasma-forming material. The set of collection optics receives broadband radiation emanated from the plasma.
US10163617B2 Multiplexing of ions for improved sensitivity
Systems and methods are provided for multiplexed precursor ion selection using a filtered noise field (FNF). Two or more different precursor ions are selected using a processor. The processor calculates an FNF waveform. The calculated FNF waveform is applied to a continuous beam of ions using the processor. The processors sends information to a mass spectrometer, which includes an ion source that provides the continuous beam of ions and a first quadrupole that receives the continuous beam of ions, so that the first quadrupole applies the calculated FNF waveform to the continuous beam of ions. The first quadrupole applies the calculated FNF waveform to the continuous beam of ions by applying the calculated FNF waveform between pairs of rods or between pairs of auxiliary electrodes placed between rods.
US10163615B2 High resolution mobility analysis of large charge-reduced electrospray ions
Achieving high conversion of large multiply charged biological ions into low charge states involves requirements difficult to reconcile when high transmission and good spray quality (resulting in narrow mobility distributions) are sought. These multiple goals are achieved in this invention by partially isolating different regions from each other with electrostatic barriers relatively transparent to ions, such as metallic grids. One such region requires high electric fields for ion generation. The other region, used for ion recombination, is approximately field-free. In an alternative arrangement intended for charge reduction in sub-millisecond times, two sources of ions with opposite polarities are placed contiguously, with a grid in between. In all cases, ion crossing through grids into field free regions is effectively driven by space charge.
US10163613B2 Deconvolution of mixed spectra
An m/z range of an ion beam is divided into two or more precursor ion mass selection windows. A pattern of two or more different window m/z ranges to be used during two or more successive cycles for at least one precursor ion mass selection window is determined. The pattern includes an initial window m/z range and one or more successively different window m/z ranges. Each of the one or more successively different window m/z ranges includes at least a portion of the initial window m/z range. A tandem mass spectrometer is instructed to select and fragment the two or more precursor ion mass selection windows during each cycle of a plurality of cycles and to repeatedly use the pattern for each group of two or more successive cycles of the plurality of cycles for the selection and fragmentation of the at least one precursor ion mass selection window.
US10163609B2 Plasma generation for ion implanter
An ion implanter comprises a dissociation chamber in the ion implanter. The dissociation chamber has an input port for receiving a gas and an output port for outputting ions. A vacuum chamber surrounds the dissociation chamber. A plurality of rods or plates of magnetic material are located adjacent to the dissociation chamber on at least two sides of the dissociation chamber. A magnet is magnetically coupled to the plurality of rods or plates of magnetic material. A microwave source is provided for supplying microwaves to the dissociation chamber, so as to cause electron cyclotron resonance in the dissociation chamber to ionize the gas.
US10163607B2 Temperature control method and plasma processing apparatus
A method for controlling the temperature of a mounting table in a plasma processing apparatus, includes: calculating a first heat input amount according to high frequency power applied in a given process, wherein the first heat input amount is calculated based on a data table, the data table being generated by measuring temperatures so as to find a first relationship between the high frequency power applied in the plasma processing apparatus and the heat input amount to the mounting table; controlling, based on an operation map, the temperature of at least one of the first heating mechanism and the cooling mechanism so that a first temperature difference between the cooling mechanism and the first heating mechanism is within a controllable range corresponding to the first heat input amount, wherein the temperature of the first heating mechanism is controllable upon the first temperature difference falling within the controllable.
US10163603B2 Particle beam system and method for the particle-optical examination of an object
A particle beam system includes a particle source to produce a first beam of charged particles. The particle beam system also includes a multiple beam producer to produce a plurality of partial beams from a first incident beam of charged particles. The partial beams are spaced apart spatially in a direction perpendicular to a propagation direction of the partial beams. The plurality of partial beams includes at least a first partial beam and a second partial beam. The particle beam system further includes an objective to focus incident partial beams in a first plane so that a first region, on which the first partial beam is incident in the first plane, is separated from a second region, on which a second partial beam is incident. The particle beam system also a detector system including a plurality of detection regions and a projective system.
US10163596B2 Horizontal-deflection prevention mechanism for high voltage direct current relay
The present invention discloses a horizontal-deflection prevention mechanism for an HVDC relay, comprising a moving contact assembly which comprises a moving reed and moving contacts arranged at left and right ends of the moving reed; an upper section of a pushrod is located above a yoke plate and fixed with the moving reed; a positioning plate is provided on the yoke plate; and a left return spring is connected between a left end of the moving reed and the positioning plate, and a right return spring is connected between a right end of the moving reed and the positioning plate. In the present invention, by the arrangement of a left return spring and a right return spring at the left and right ends of the moving reed at which moving contacts are provided, on one hand, a breaking force can be provided, which allows the moving contacts to quickly separate from the stationary contacts when the moving contacts and the stationary contacts are to be separated from each other, so that the relay makes a response quickly. On the other hand, the left return spring and the right return spring always provide an acting force which prevents the moving reed from rotating horizontally, so as to ensure that the moving contacts and the stationary contacts can come into contact precisely and to thus prevent the occurrence of faults due to the contact between the moving reed and other components.
US10163591B2 Motor vehicle operating device with sound-generating switching element
An operating device includes a casing, an operating button arranged at the casing for the manual actuation of the operating device, and a printed circuit board that is arranged in the casing. A switching element is mechanically coupled to the operating button and arranged on the printed circuit board. The switching element produces a pronounced sound when the operating button is actuated. To this end, next to the switching element, the printed circuit board is mechanically connected to the casing by at least one support element and each support element is designed to stabilize the printed circuit board against a tremor that is produced by the switching element when producing the sound.
US10163590B2 Power-circuit breaking device
A power-circuit breaking device includes a receptacle and a plug. The receptacle includes a power terminal and a signal terminal. The plug includes a main terminal and a sub-terminal. The plug includes a plug housing, a lever which is attached to the plug housing, a lock slider which is attached to the plug housing, and a sub-connector which is supported by the lock slider. The plug housing holds the main terminal. The sub-connector holds the sub-terminal. When the lock slider slides, the sub-connector moves. When the lever is located at a closed position, the main terminal is connected to the power terminal. When the lock slider is located at a connected position, the sub-terminal is connected to the signal terminal.
US10163587B2 Interlock device of withdrawable arc eliminator
The present invention relates to a withdrawable arc eliminator having an interlock function, and more particularly, to a withdrawable arc eliminator having an interlock function capable of preventing insertion or withdrawal of an arc eliminator applied to an electrical panel, in a closed state of the arc eliminator.
US10163570B2 Power storage device
An electrical double layer capacitor having electrolyte-containing layer between a first polarizable electrode layer and a second polarizable electrode layer. An insulating adhesive portion adheres to a first current collector and a second current collector which at least partially face each other with the electrolyte-containing layer interposed therebetween. The insulating adhesive portion 15 extends around the first and second polarizable electrode layers and the electrolyte-containing layer. A thickness of the electrolyte-containing layer is larger than a difference between a thickness of the insulating adhesive portion and thicknesses of the first and second polarizable electrode layers.
US10163559B2 Coil component
A terminal electrode includes a base extending along the outer end face of a flange, a mounting part extending from the base along the bottom face of the flange via a first bending part that covers the edge portion where the outer end face and the bottom face meet, and a wire connection part extending from the base along a substantially horizontal face via a second bending part that covers the edge portion where the outer end face and the substantially horizontal face meet, the wire connection part being electrically connected to an end portion of a wire.
US10163550B2 Superconducting cable and superconducting cable manufacturing method
In order to obtain a highly versatile superconducting cable capable of absorbing differences in thermal contraction amounts that arise between three members, these being a cable core, an inner tube, and an outer tube, and to obtain a superconducting cable manufacturing method of the same, a superconducting cable includes a thermal insulation vacuum tube and a cable core. The thermal insulation vacuum tube includes an inner tube fixed at both ends and having a cooling medium filled inside, and an outer tube disposed at an outer peripheral side of the inner tube with a space between the outer tube and the inner tube maintained at a vacuum, and is configured to include a winding section wound with one or more turns. The cable core is fixed at both ends and disposed inside the inner tube.
US10163548B2 Power/fiber hybrid cable
The present disclosure relates to a hybrid cable having a jacket with a central portion positioned between left and right portions. The central portion contains at least one optical fiber and the left and right portions contain electrical conductors. The left and right portions can be manually torn from the central portion.
US10163540B2 Production process for highly conducting and oriented graphene film
A process for producing a highly conducting film of conductor-bonded graphene sheets that are highly oriented, comprising: (a) preparing a graphene dispersion or graphene oxide (GO) gel; (b) depositing the dispersion or gel onto a supporting solid substrate under a shear stress to form a wet layer; (c) drying the wet layer to form a dried layer having oriented graphene sheets or GO molecules with an inter-planar spacing d002 of 0.4 nm to 1.2 nm; (d) heat treating the dried layer at a temperature from 55° C. to 3,200° C. for a desired length of time to produce a porous graphitic film having pores and constituent graphene sheets or a 3D network of graphene pore walls having an inter-planar spacing d002 less than 0.4 nm; and (e) impregnating the porous graphitic film with a conductor material that bonds the constituent graphene sheets or graphene pore walls to form the conducting film.
US10163539B2 High strength and high conductivity copper alloy rod or wire
A high strength and high conductivity copper rod or wire includes Co of 0.12 to 0.32 mass %, P of 0.042 to 0.095 mass %, Sn of 0.005 to 0.70 mass %, and O of 0.00005 to 0.0050 mass %. A relationship of 3.0≤([Co]−0.007)/([P]−0.008)≤6.2 is satisfied between a content [Co] mass % of Co and a content [P] mass % of P. The remainder includes Cu and inevitable impurities, and the rod or wire is produced by a process including a continuous casting and rolling process. Strength and conductivity of the high strength and high conductivity copper rod or wire are improved by uniform precipitation of a compound of Co and P and by solid solution of Sn. The high strength and high conductivity copper rod or wire is produced by the continuous casting and rolling process, and thus production costs are reduced.
US10163536B2 Method and apparatus for recovery of radioactive nuclides from spent resin materials
A process for the recovery of a radioisotope from a waste resin of a nuclear power plant comprises the steps of: a) treating a waste resin loaded with at least one radioisotope with an organic acid or alkaline compound to release the at least one radioisotope and to obtain a process solution containing the at least one radioisotope; b) separating the at least one radioisotope from the process solution through a reaction specific to the radioisotope so as to obtain a treated process solution depleted of the at least one radioisotope, wherein said depleted process solution comprises the organic acid or alkaline compound and optionally a non-reacted radioisotope; c) reacting the organic acid or alkaline compound in the depleted process solution from step b) by thermal and/or photochemical oxidation to form gaseous reaction products; and d) reloading the waste resin with the reacted process solution from step c) to bind the non-reacted radioisotope on the waste resin. Further, an apparatus is provided to carry out the above method.
US10163533B2 Control rod drive mechanism outer diameter seal ultra high pressure cavitation peening
A sealing device is provided to form a sealed region about one or more surfaces to be treated. The sealing device has an open end with a rim configured to matingly engage a treatment surface. The sealing device is braced both vertically and laterally, and the sealed region is flooded and pressurized. A peening nozzle and manipulating tooling are positioned within an interior volume of the sealing device. Pressurized fluid is ejected from the nozzle causing the formation of cavitation bubbles. The nozzle flow causes the cavitation bubbles to settle on the surfaces to be treated. The collapsing impact of the cavitation bubbles imparts compressive stress in the materials of the treatment surfaces.
US10163531B2 Reactivity control in a molten salt reactor
Methods of controlling the reactivity of a molten salt fission reactor. The molten salt fission reactor comprises a core and a coolant tank (101), the core comprising fuel tubes (103) containing a molten salt fissile fuel, and the coolant tank containing a molten salt coolant (102), wherein the fuel tubes are immersed in the coolant tank. The methods comprise dissolving a neutron absorbing compound in the molten salt coolant, the neutron absorbing compound comprising a halogen and a neutron absorbing element. The first method further comprises reducing the neutron absorbing compound to a salt of the halogen and an insoluble substance comprising the neutron absorbing element, the halogen being fluorine or chlorine, wherein the insoluble substance is not volatile at a temperature of the coolant during operation of the reactor. In the second method the one or more neutron absorbing compounds are chosen such that reduction of the neutron absorbing capacity of the one or more neutron absorbing compounds due to absorption of neutrons compensates for a fall in reactivity of the core in order to control fission rates in the core. Apparatus for implementing the methods are also provided.
US10163529B2 Display processing method and apparatus
A disclosed method includes: defining two first points in a model cross section of a model of an object and two corresponding second points in an image that is a cross section of the object for a reference time; performing first transforming including expansion or reduction for the model cross section so that a position of a second point is identical to a position of a corresponding first point; superimposing the image and the model cross section after the performing; second transforming a second model cross section for a second time after the reference time, so that positions of two second points in a second image for the second time are almost identical to positions of corresponding two first points in the second model cross section; and superimposing the second image and the second model cross section after the second transforming.
US10163525B2 Test apparatus based on binary vector
A test apparatus includes a device under test (DUT) configured to exchange data using a serial interface protocol and a test controller configured to receive a binary vector corresponding to a physical layer of the serial interface protocol from an external device and to buffer and transmit the received binary vector to the DUT.
US10163520B1 OTP cell with improved programmability
An integrated circuit OTP memory cell has a programming element with enhanced programmability. The programming element has a doped region at the surface of a semiconductor substrate and a conducting layer partially extending over a surface of the semiconductor surface and along a boundary of the doped region. The conducting layer is displaced from the surface of the doped region and the semiconductor substrate by a thin oxide layer. The partially extending conducting layer provides locations to concentrate electric fields and rupture the gate oxide layer during programming.
US10163519B2 Semiconductor device, electronic component, and electronic device
A highly reliable semiconductor device is provided. A memory cell includes a first transistor and a second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. The first transistor is configured to hold charge corresponding to first data retained in the memory cell when turned off. The data writing circuit is configured to write the first data and correction data to the memory cell. The data reading circuit is configured to read a first voltage value corresponding to the first data, read a second voltage value corresponding to the correction data written to the memory cell, convert a voltage value that is equivalent to a difference between the first voltage value and the second voltage value into corrected first data, and output the corrected first data to the data writing circuit.
US10163514B2 Methods of operating a memory during a programming operation
Methods of operating a memory include increasing a voltage applied to a first access line from a first voltage to a second voltage higher than the first voltage while applying the first voltage to a second access line, the first access line coupled to a target memory cell of the programming operation and an unselected memory cell not targeted for the programming operation, and the second access line coupled to memory cells not targeted for the programming operation. After increasing the voltage applied to the first access line, increasing the voltage applied to the first access line from the second voltage to a third voltage higher than the second voltage and increasing a voltage applied to the second access line from the first voltage to a fourth voltage higher than the first voltage and lower than the third voltage.
US10163512B2 Semiconductor device capable of effectively eliminating hot holes in a channel and operating method thereof
A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines.
US10163508B2 Supporting multiple memory types in a memory slot
Methods and apparatus related to supporting both DDR (Double Data Rate) and NVM (Non-Volatile Memory) DIMM (Dual Inline Memory Module) on the same memory slot are described. In one embodiment, a DIMM comprises volatile memory and non-volatile memory, and data is communicated with the volatile memory and the non-volatile memory via a single memory slot. Other embodiments are also disclosed and claimed.
US10163507B1 Apparatuses and methods including memory access in cross point memory
Some embodiments include apparatuses and methods having a memory cell, first and second conductive lines configured to access the memory cell, and a switch configured to apply a signal to one of the first and second conductive lines. In at least one of such embodiments, the switch can include a phase change material. Other embodiments including additional apparatuses and methods are described.
US10163506B2 Apparatuses including memory cells and methods of operation of same
Disclosed herein is a memory cell including a memory element and a selector device. The memory cell may be programmed with a programming pulse having a first polarity and read with a read pulse having a second polarity. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities. The memory cell may exhibit reduced voltage drift and/or threshold voltage distribution. Described herein is a memory cell that acts as both a memory element and a selector device. The memory cell may be programmed with a programming pulse having first and second portions. The first and second portions may have different magnitudes and polarities.
US10163505B2 RRAM array with current limiting element
A resistive random access memory (RRAM) circuit is provided. In some embodiments, the RRAM circuit has a plurality of RRAM cells. A bit-line decoder is configured to concurrently apply a forming signal to the plurality of RRAM cells. A current limiting element is configured to concurrently limit a current of the forming signal applied to the plurality of RRAM cells.
US10163504B2 Planar variable resistance memory
An example memory device includes a planar semiconductor substrate layer; a planar variable resistance layer disposed above the planar semiconductor substrate layer; a planar channel layer disposed above the planar variable resistance layer; and one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.
US10163502B2 Selective performance level modes of operation in a non-volatile memory
In one embodiment, a non-volatile memory is controlled in a selectable read mode in response to commands from a processor. Selectable read modes may include a default read memory mode, for example, and a performance read memory mode having a shorter read pulse and a reduced read latency than the default read memory mode, for example. In one embodiment, the performance read memory mode may also have refresh operations at an increased frequency compared to that of the default read mode. Other aspects and advantages are described.
US10163501B2 Apparatuses, memories, and methods for address decoding and selecting an access line
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.
US10163500B1 Sense matching for hard and soft memory reads
Error correction systems and methods for improving sense matching conditions between hard-bit read (HBR) information and soft-bit read (SBR) information. For HBRs, a given set of sense conditions can include a discharged bit line of one or more cells that discharged during a previous HBR. For SBRs, a given set of sense conditions can include loading latches of the sense amplifiers for corresponding cells are with sense results of the previous SBR strobe when the corresponding cells discharged during a previous SBR strobe or loading the latches of the sense amplifiers with sense results of a previous HBR when the corresponding cells discharged during the previous HBR.
US10163498B1 Reflow protection
Devices and techniques to reduce corruption of preloaded data during assembly are disclosed herein. A memory device can perform operations to store received data, including preloaded data, up to a threshold amount on a memory array in a reflow-protection mode, and to transition from the reflow-protection mode to a normal-operation mode after the initial data exceeds the threshold amount.
US10163497B2 Three dimensional dual-port bit cell and method of using same
A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.
US10163496B2 Static random access memory (SRAM) tracking cells and methods of forming the same
An embodiment static random access memory (SRAM) array includes a writable SRAM cell disposed in a first row of the SRAM array and an SRAM read current tracking cell in the first row of the SRAM array. The SRAM current tracking cell includes a first read pull-down transistor and a first read pass-gate transistor. The first read pull-down transistor includes a first gate electrically connected to a first positive supply voltage line; a first source/drain electrically connected to a first ground line; and a second source/drain. The first read pass-gate transistor includes a third source/drain electrically connected to the second source/drain and a fourth source/drain electrically connected to a read tracking bit line (BL). The read tracking BL is electrically connected to a read sense amplifier timing control circuit.
US10163494B1 Memory device and fabrication method thereof
A device includes a memory bit cell and a retention circuit. The memory bit cell includes a first metal line and a second metal line. The first metal line is disposed in a first metal layer and configured to receive a retention voltage. The second metal line is disposed in the first metal layer and configured to receive a first reference voltage lower than the retention voltage. The retention circuit includes a third metal line. The third metal line is disposed in the first metal layer and configured to transmit the retention voltage to the first metal line. A distance between the second metal line and the third metal line is less than a length of the memory bit cell.
US10163493B2 SRAM margin recovery during burn-in
Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
US10163491B2 Memory circuit having shared word line
A memory circuit includes first and second memory cells. The first memory cell has an access port having a pass gate. The second memory cell also has an access port having a pass gate. The first and second memory cells abut one another along a column direction. The circuit includes at least one conductive structure over the first and second memory cells. The conductive structure may be two interconnected conductive lines. The conductive structure extends along a row direction in a conductive layer and is electrically coupled to the gate terminals of the pass gates.
US10163490B2 P-type field-effect transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells, and related memory systems and methods
P-type Field-effect Transistor (PFET)-based sense amplifiers for reading PFET pass-gate memory bit cells (“bit cells”). Related methods and systems are also disclosed. Sense amplifiers are provided in a memory system to sense bit line voltage(s) of the bit cells for reading the data stored in the bit cells. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type Field-effect Transistor (NFET) drive current due for like-dimensioned FETs. In this regard, in one aspect, PFET-based sense amplifiers are provided in a memory system to increase memory read times to the bit cells, and thus improve memory read performance.
US10163482B2 Ground reference scheme for a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.
US10163481B1 Offset cancellation for latching in a memory device
Methods, systems, and devices for offset cancellation for latching in memory devices are described. A memory device may include a sense component comprising a first and second transistor. In some cases, a memory device may further include a first capacitor coupled to the first transistor and a second capacitor coupled to the second transistor and a first switching component coupled between a voltage source and the first capacitor and the second capacitor. For example, the first switching component may be activated, a reference voltage may be applied to the sense component, and the first switching component may then be deactivated. In some examples, a voltage offset may be measured across both the first and the second capacitor.
US10163478B2 Magnetic memory devices having memory cells and reference cells with different configurations
A semiconductor memory device includes a memory cell including a memory magnetic tunnel junction (MTJ) configured to be coupled to a first sensing node and a reference cell including a first resistance element and a second resistance element configured to be coupled in parallel to a second sensing node, the first resistance element including a first number of reference MTJs and the second resistance element including a second number of reference MTJs different from the first number of reference MTJs. The memory device further includes a sensing circuit configured to be coupled to the first and second sensing nodes and to detect a difference in resistance between the memory cell and the reference cell. In some embodiments, the first number of reference MTJs includes first reference MTJs connected in series and the second number of reference MTJs includes second reference MTJs connected in series.
US10163476B2 Method of operating tracking circuit
A method of operating a tracking circuit of a memory device includes charging a node of the tracking circuit to a first predetermined voltage level, the first node being electrically coupled with a first load device. A first plurality of tracking cell transistors are activated to discharge the first node toward a second predetermined voltage level. A reset signal is generated based on a signal at the first node. The reset signal may correspond to a waiting period for reading a memory cell of the memory device.
US10163475B2 Non-volatile memory device having dummy cells and memory system including the same
A non-volatile memory device includes a cell string, a ground select transistor, and at least one dummy cell. The cell string includes at least one memory cell. The at least one dummy cell is provided between the at least one memory cell and the ground select transistor and is connected to a bit line. A controller executes dummy cell control logic configured to control a gate voltage of the at least one dummy cell to be lower than a threshold voltage of the at least one dummy cell in at least a part of a pre-charge period.
US10163472B2 Apparatuses and methods for memory operations having variable latencies
Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and perform a memory operation responsive to the memory instruction. The memory is further configured to provide an acknowledgement indicative of an end of the variable latency period wherein the acknowledgement includes information related to an acceptance of a memory instruction. Data associated with the memory instruction is exchanged with the memory following the acknowledgement. In an example method a read instruction and an address from which read data is to be read is received. A write operation is suspended responsive to the read instruction and an acknowledgement indicative of an end of the variable latency period is provided. Read data for the read instruction is provided and the write operation is continued to be suspended for a hold-off period following completion of the read operation.
US10163471B2 Time tracking with trits
A memory controller circuitry includes a timestamp circuitry and a demarcation voltage (VDM) selection circuitry. The timestamp circuitry is to capture a global timer index from a global timer having a granularity, G. The timestamp circuitry is further to fetch a timestamp for a memory block that includes a group of sub-blocks that includes a target sub-block. The demarcation voltage (VDM) selection circuitry is to fetch a combined count from a count store. The combined count represents a combined state. The combined state includes a target individual state of the target sub-block and a respective individual state of each of at least one other sub-block of the group of sub-blocks included in the memory block.
US10163470B2 Dual rail memory, memory macro and associated hybrid power supply method
A dual rail memory operable at a first voltage and a second voltage is disclosed. The dual rail memory includes: a memory array operates at the first voltage; a word line driver circuit configured to drive a word line of the memory array to the first voltage; a data path configured to transmit an input data signal or an output data signal, wherein the data path includes a first level shifter for transferring the input data signal from the second voltage to the first voltage; and a control circuit configured to provide control signals to the memory array, the word line driver circuit and the data path, wherein the control circuit includes a second level shifter for transferring an input control signal from the second voltage to the first voltage; wherein the data path and the control circuit are configured to operate at both the first and second voltages.
US10163467B2 Multiple endianness compatibility
Examples of the present disclosure provide apparatuses and methods for multiple endianness compatibility. An example method comprises receiving a plurality of bytes in a non-bit-sequential format. The method includes reordering the bits in each byte of the plurality of bytes such that the plurality of bytes are arranged in a bit-sequential format.
US10163465B1 Data receiver and controller for DDR memory
A data receiver for a double data rate (DDR) memory includes a first stage circuit and a second stage circuit. The first stage circuit is deployed for receiving a single-ended signal from the DDR memory and converting the single-ended signal into a pair of differential signals. The second stage circuit, coupled to the first stage circuit, is deployed for receiving the differential signals from the first stage circuit and converting the differential signals into an output signal. Both of the first stage circuit and the second stage circuit are implemented in a core voltage domain.
US10163464B2 Memory module capable of measuring temperature and system using the same
A memory module may be provided. The memory module may include a thermocouple and a temperature sensor. The thermocouple may be coupled to at least one contact point among a plurality of contact points formed on a region, on which a memory device may be configured to be mounted. The temperature sensor may be coupled to the thermocouple, and may be configured to generate temperature information.
US10163463B2 Virtual reality system and method of controlling working state thereof
A virtual reality system and a method of controlling working state of the virtual reality system. The virtual reality system comprises a video playing device and a virtual reality glasses box, and the virtual reality glasses box utilizes a screen of the video playing device to play a video content, the method comprises: establishing a wired or wireless connection between the video playing device and the virtual reality glasses box; when the video playing device is placed in the virtual reality glasses box, transmitting information of wearing state of the virtual reality glasses box to the video playing device; and controlling a playing state of the video playing device according to the wearing state of the virtual reality glasses box. The present disclosure controls the working state of the virtual reality device by the action of the user operating the device itself, and the user does not need to employ tedious and complicated operations to control each of the devices, which increases usability, and improves user experience.
US10163461B2 Magazine management device in which one or more antennas disposed in one antenna base communicate with two or more radio identifiers corresponding to two or more magazine regions
A magazine management device stores a plurality of magazines in which a plurality of optical discs is housed. The magazine management device includes a case that supports the plurality of magazines, a plurality of partitions that divides the case so as to form a plurality of regions in which the magazines can be stored one by one, an antenna that transmits a radio wave for asking a radio identifier provided to the magazine for a response and receives a radio wave of the response transmitted from the radio identifier, and an arithmetic processor that receives information obtained from the radio wave of the response received by the antenna.
US10163455B2 Detecting pause in audible input to device
A device includes a processor and a memory accessible to the processor and bearing instructions executable by the processor to process an audible input sequence provided by a user of the device, determine that a pause in providing the audible input sequence has occurred at least partially based on a first signal from at least one camera communicating with the device, cease to process the audible input sequence responsive to a determination that the pause has occurred, determine that providing the audible input sequence has resumed based at least partially based on a second signal from the camera, and resume processing of the audible input sequence responsive to a determination that providing the audible input sequence has resumed.
US10163453B2 Robust voice activity detector system for use with an earphone
An electronic device or method for adjusting a gain on a voice operated control system can include one or more processors and a memory having computer instructions. The instructions, when executed by the one or more processors causes the one or more processors to perform the operations of receiving a first microphone signal, receiving a second microphone signal, updating a slow time weighted ratio of the filtered first and second signals, and updating a fast time weighted ratio of the filtered first and second signals. The one or more processors can further perform the operations of calculating an absolute difference between the fast time weighted ratio and the slow time weighted ratio, comparing the absolute difference with a threshold, and increasing the gain when the absolute difference is greater than the threshold. Other embodiments are disclosed.
US10163446B2 Audio encoder and decoder
This disclosure falls into the field of audio coding, in particular it is related to the field of spatial audio coding, where the audio information is represented by multiple audio objects including at least one dialog object. In particular the disclosure provides a method and apparatus for enhancing dialog in a decoder in an audio system. Furthermore, this disclosure provides a method and apparatus for encoding such audio objects for allowing dialog to be enhanced by the decoder in the audio system.
US10163445B2 Apparatus and method encoding/decoding with phase information and residual information
Provided is an apparatus and method of encoding and decoding multiple channel signals based upon phase information and one or more residual signals.
US10163441B2 Location-based responses to telephone requests
A method for receiving processed information at a remote device is described. The method includes transmitting from the remote device a verbal request to a first information provider and receiving a digital message from the first information provider in response to the transmitted verbal request. The digital message includes a symbolic representation indicator associated with a symbolic representation of the verbal request and data used to control an application. The method also includes transmitting, using the application, the symbolic representation indicator to a second information provider for generating results to be displayed on the remote device.
US10163437B1 Training models using voice tags
Techniques for training machine-learning algorithms with the aid of voice tags are described herein. An environment may include sensors configured to generate sensor data and devices configured to perform operations. Sensor data as well as indications of actions performed by devices within the environment may be collected over time and analyzed to identify one or more patterns. Over time, a model that includes an association between this sensor data and device actions may be created and trained such that one or more device actions may be automatically initiated in response to identifying sensor data matching the sensor data of the model. To aid in the training, a user may utter a predefined voice tag each time she performs a particular sequence of actions, with the voice tag indicating to the system that temporally proximate sensor data and device-activity data should be used to train a particular model.
US10163436B1 Training a speech processing system using spoken utterances
Systems, methods, and devices for training a Natural Language Understanding (NLU) component of a system using spoken utterances of individuals are described. A server sends a device, such as a speech-controlled device, a signal that causes the device to output audio soliciting content regarding how a user would speak a particular command for execution by a particular application. The device captures spoken audio and sends it to the server. The server performs speech processing on received audio data to parse the audio data into multiple portions. The server then associates a first portion of the audio data with a command indicator and a second portion of the audio data with a content indicator. The associated data is then used to update how the NLU component determines how utterances triggering the command are spoken.
US10163432B2 Active noise control using variable step-size adaptation
A system and method (referred to as the system) that actively reduces noise in a vehicle. The system generates one or more control output signals to drive multiple loudspeakers; and adapts multiple control coefficients of a control filter based on multiple secondary path transfer functions. The secondary path transfer functions model the acoustic paths between each loudspeaker and multiple microphones. The multiple control coefficients are time varying and frequency dependent and the rate the plurality control coefficients adapt is based on an adaptive step size based on one or more step size criteria.
US10163425B2 Chuck structure capable of quickly adjusting placement angle of drumstick and percussion practice assisting device thereof
A chuck structure for fixing a drumstick on a non-circular revolving shaft of a foot drum includes a retractable chuck, two arched plates and a fastening element. The two arched plates clamp the non-circular revolving shaft. An inner arched surface of each arched plate has an inner fastening surface correspondingly clamping the non-circular revolving shaft, and an outer arched surface of each arched plate has a spiked surface. The retractable chuck includes a fastening portion and a rotating portion, which are pivotally connected to each other, clamp the two arched plates, and are penetrated by the drumstick. Each of the fastening portion and a rotating portion has a clamping surface abutting against the spiked surface. The fastening member propels and rotates the rotating portion, so as to allow the retractable chuck, spaced by the two arched plates, to clamp and fasten on the non-circular revolving shaft.
US10163420B2 System, apparatus and methods for adaptive data transport and optimization of application execution
Elements and processes used to enable the generation and interaction with complex networks, simulations, models, or environments. In some embodiments, this is accomplished by use of a client-server architecture that implements processes to improve data transport efficiency (and hence network usage), reduce latency experienced by users, and optimize the performance of the network, simulation, model or environment with respect to multiple parameters.
US10163419B2 Image processing to combine virtual object with captured image
There is provided an image processing apparatus including an image processing unit which combines a virtual object with a captured image. The image processing unit determines the virtual object based on a state or a type of an object shown in the captured image.
US10163417B2 Display panel driving apparatus, method of driving, and display apparatus with first off voltage controlled based on leakage current
A display panel driving apparatus includes a data driving part, a gate driving part and an off voltage controlling part. The data driving part is configured to output a data signal to a data line of a display panel. The gate driving part is configured to output a gate signal to a gate line of the display panel. The off voltage controlling part is configured to receive a first off voltage and a second off voltage applied to the gate driving part to generate the gate signal, measure a leakage current of the gate driving part, and control the first off voltage based on the leakage current. Thus, display quality of a display apparatus including the gate driving part may be enhanced.
US10163414B2 GOA driving circuit
A GOA driving circuit is provided, which includes a first signal generating module for generating the forward scan control signal based upon a first clock signal and a cascade signal; a control module for controlling an output of the cascade signal based upon the forward scan control signal and the reverse scan control signal; a latch module for latching the cascade signal by the first clock signal and the second clock signal; a processing module and a buffer module.
US10163412B2 Pixel structure
A pixel structure is provided. The pixel structure includes a scan line and a data line, an active device, a pixel electrode, and a common electrode. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The common electrode is disposed to overlap with the pixel electrode. The common electrode is coupled to the pixel electrode to form a first storage capacitor and a second storage capacitor. The first storage capacitor and the second storage capacitor commonly use the pixel electrode as an upper electrode.
US10163406B2 Electro-optic displays displaying in dark mode and light mode, and related apparatus and methods
This invention provides methods of and related apparatus for driving an electro-optic display having a plurality of pixels to display white text on a black background (“dark mode”) while reducing edge artifacts, ghosting and flashy updates. The present invention reduces the accumulation of edge artifacts by applying a special waveform transition to edge regions according to an algorithm along with methods to manage the DC imbalance introduced by the special transition. Edge artifact clearing may be achieved by identifying specific edge pixels to receive a special transition called an inverted top-off pulse (“iTop Pulse”) and, since the iTop Pulse is DC imbalanced, to subsequently discharge remnant voltage from the display. This invention further provides methods of and related apparatus for driving an electro-optic display having a plurality of pixels to display white text on a black background (“dark mode”) while reducing the appearance of ghosting due to edge artifacts and flashy updates by identifying specific edge pixels to receive a special transition called an inverted Full Pulse transition (“iFull Pulse”).
US10163400B2 Display driving apparatus
A display driving apparatus including a lightness adjusting unit, a gamma adjusting unit, a pre-charging voltage adjusting unit and a source driving unit is disclosed. The lightness adjusting unit receives and adjusts a lightness of an image data. The gamma adjusting unit adjusts a gamma voltage corresponding to the image data to generate a source data voltage. The pre-charging voltage adjusting unit calculates a highest data voltage and a lowest data voltage which can be outputted by a source electrode and adjusts a pre-charging voltage accordingly to make the adjusted pre-charging voltage the same with the highest data voltage or the lowest data voltage or only a shifted voltage different from the highest data voltage or the lowest data voltage of the image data. The source driving unit outputs the adjusted pre-charging voltage and the source data voltage to a display panel respectively.
US10163398B2 Method of driving a display panel and a display apparatus for performing the same
A method of driving a display panel includes adjusting a level of a data sustaining voltage or an on bias voltage during an on bias compensating period, applying the on bias voltage to pixels through data lines during an on bias period, which is subsequent to the on bias compensating period, to adjust a voltage level of control electrodes of driving transistors of the pixels, initiating a voltage of anode electrodes of organic light emitting elements of the pixels during an initiating period, applying data voltages to the pixels through the data lines during a scanning period, and turning on the organic light emitting elements of the pixels during an emission period.
US10163393B2 Display substrate, display equipment and regional compensation method
A display substrate, a display equipment and a regional compensation method. The display substrate includes a pixel array, a common cathode current detection circuit, and a data signal compensation circuit. The common cathode current detection circuit is configured to detect a total current flowing through each common cathode; the data signal compensation circuit is configured to receive the pixel light emitting current of the first sub-pixel, receive the total current of the common cathode, and calculate compensation data for each of the sub-pixels according to the pixel light emitting current and the total current of the common cathode.
US10163387B2 Image display device and driving method of the same
An image display device including a light-emitting element configured to emit light corresponding to a current flowing therethrough; a driving element that is connected to the light-emitting element and configured to control light emission of the light-emitting element; and a control unit configured to apply a reverse bias voltage to a first n-type driving element whose the threshold voltage determined at a specific time is equal to or higher than a positive predetermined voltage level for shifting the threshold voltage of the first n-type driving element in a negative direction, and not apply the reverse bias voltage to a second n-type driving element whose the threshold voltage determined at the specific time is lower than the positive predetermined voltage level for shifting the threshold voltage of the second n-type driving element in a positive direction when the light-emitting element does not emit light.
US10163384B2 Flat panel display
A flat panel display includes: a substrate that includes a display region and a non-display region at a periphery of the display region; a pixel array disposed on the substrate of the display region; an input pad part disposed on the substrate of the non-display region; a bonding pad part disposed on the substrate of the non-display region, the bonding pad part including a plurality of output pads connected to the pixel array and a plurality of input pads connected to the input pad part; and a protective layer disposed on the substrate of the non-display region, the protective layer having openings formed therein that expose portions of the bonding pad part and the input pad part, wherein the opening of the protective layer is smaller than the bonding pad part, wherein the protective layer is thinner at a portion that overlaps the bonding pad part than at other portions.
US10163379B2 Detection device, detection method and detection system
The present invention provides a detection device, a detection method and a detection system, which are used for detecting damaged condition of a substrate. The detection device includes a probe unit and a judgement unit, and the probe unit includes a probe, a speed detection module and a driving force control module both provided on the probe, wherein the bottom end of the probe is used for contacting with the substrate to be detected; the speed detection module is used for obtaining a real-time speed of the probe in a process of detection and transmitting the real-time speed to the judgement unit; the driving force control module is used for applying a constant driving force to the probe; and the judgement unit is used for receiving the real-time speed of the probe and judging the damaged condition of the substrate to be detected according to the real-time speed.
US10163376B2 Display assembly
There is provided a display assembly. The assembly includes an elongate mounting member. The mounting member has a top, a bottom spaced-apart from the top, and a plurality of spaced-apart grooves extending from the top to the bottom thereof. The assembly includes a plurality of planar members. Each of the planar member includes image indicia thereon. The planar members are shaped to fit within respective ones of the grooves, whereby the image indicia so arranged conveys a three-dimensional effect.
US10163362B2 Emotion and mood data input, display, and analysis device
A feeling of each of members forming a group or team and the mood of all the members felt by each member are objectified and recorded. An emotion/mood data input, display, and analysis device includes a controller, a display, an input unit, and a recording unit. The controller includes an input screen generation unit. The input screen generation unit generates a first input screen that allows each of multiple members forming a group to, as an inputter, input whether an emotion or feeling of the each member is cheerful or gloomy, a level of cheerfulness or gloominess, whether the emotion or feeling is strong or weak, and a level of strength or weakness in a bifurcated manner. The display displays the first input screen. The controller captures data through the first input screen displayed on the display and the input unit and records the data in the recording unit.
US10163352B2 Driving control device
When performing a switch between the lane change control and the lane keeping control, a switching controller of the driving control device sets a transition time-frame for performing the switch, and gradually switches between the lane change control and the lane keeping control during the transition time-frame.
US10163339B2 Monitoring traffic congestion
Described herein is a framework to monitor traffic congestion. In accordance with one aspect of the framework, the framework receives vehicle data from vehicle data sources located in a region of interest. The framework may determine a sample size and an average speed for an edge of the region of interest based on the vehicle data. Congestion probability may then be determined based on the sample size and average speed. A report may be presented based on the congestion probability.
US10163331B2 Alarm system with two-way voice
Techniques are described for establishing a two-way voice communication session with an alarm system. The alarm system may establish a two-way voice communication session with an operator associated with a monitoring service that provides monitoring services for alarm events detected by the alarm system. The alarm system also may establish a two-way voice communication session with a notification recipient that is interested in receiving notifications associated with events detected by the alarm system.
US10163330B1 System and method for securely accessing online systems
The present disclosure relates generally to a method of operating a customer interface device (CID). The method includes: receiving a request from a customer to access a secure portion of an online system; establishing an encrypted channel to an authentication system of the online system. The method also includes: outputting a prompt to the customer to provide a spoken passphrase of the customer; capturing the spoken passphrase of the customer to generate a recording; and providing, via the encrypted channel, credentials of the customer to an authentication system of the online system, wherein the credentials include the recording. The method further includes; receiving, via the encrypted channel, an indication of approval of the credentials of the customer from the authentication system; and establishing, via the encrypted channel, a secure mode pass-through connection to the secure portion of the online system.
US10163329B1 Home alarm system
Techniques are described for selecting an alarm state based at least in part on determining a security event related to security and automation systems. One method includes receiving, from a sensor, a first indication of a security event at the first location, determining a first threat level based on the security event, and activating a first alarm state based at least in part on the first threat level.
US10163328B2 SATCOM distressed aircraft tracking system
The invention is a system and method for communicating emergency information from an aircraft in response to an emergency or technical problem detected by monitoring avionics data at an onboard autonomous aircraft SATCOM transceiver activation device, the emergency detection functioning to automatically activate and control an aircraft SATCOM transceiver which then (i) automatically triggers real-time tracking of the aircraft via satellite, (ii) provides aircraft positioning on broadcast distinctive signals and data in designated frequencies; and (iii) monitors, processes, and automatically communicates the avionics data in conformance with ICAO standards for GADSS.
US10163327B1 Methods of facilitating emergency assistance
In system and methods for loss mitigation, accident data associated with a vehicle accident involving a driver may be collected. The accident data may be analyzed, and a likely severity of the vehicle accident may be determined based upon the analysis of the accident data. A communication related to emergency assistance or an emergency assistance recommendation may be generated based upon the determined likely severity of the vehicle accident, and transmitted, via wireless communication, from one or more remote servers to a mobile device associated with the driver. A wireless communication from the driver indicating approval or modification of the emergency assistance or emergency assistance recommendation may be received. A third party may be notified, via a communication sent from the remote server(s), of requested emergency assistance as approved or modified by the driver. An estimated insurance claim may also be generated based upon vehicle accident likely severity.
US10163322B2 Wireless communication between patient beds and equipment for checking compatibility
A system comprises a patient bed having a reader to read wireless signals. In some embodiments a wound dressing has a transmitter that transmits wireless signals to the reader of the patient bed. In other embodiments, a garment has a transmitter that transmits wireless signals to the reader of the patient bed. In still further embodiments, other medical equipment has a transmitter that transmits wireless signals to the reader of the patient bed.
US10163312B2 Autonomously operating light emitting devices providing detection and warning of hazardous condition on path of travel
A system is disclosed comprising a plurality of light emitting devices located along a path of travel, each light emitting device comprising a light emitting source, a sensor, a communication module, and a processor, wherein when a first one of the plurality of light emitting devices is activated, the processor in the first light emitting device is configured to detect one or more physical structures surrounding the first light emitting device, detect one or more other light emitting devices, and based at least in part on the detection of the one or more physical structures and the one or more other light emitting devices, determine a location of the first light emitting device with respect to the path of travel.
US10163311B2 Systems for tracking medications
The present disclosure relates to integrated systems, methods and apparatuses for assisting individuals in managing acute life-threatening conditions. A system in accordance with the current disclosure may comprise an electronic circuit configured to be attached to a container of a medication and one or more devices in communication with the electronic circuit in a private network. In an aspect, the one or more devices may work in concert to determine the safety level of an individual based on predetermined usage settings. In some aspects, the system may be configured to determine whether a medication would expire before its manufactured expiry date. In another aspect, the system may assist an individual in locating a medication. In a further aspect, the system may determine whether an individual is having an anaphylactic reaction. In some aspects, the system may detect a known allergen and alert the individual.
US10163310B2 Alarm panel
A fire alarm panel comprises a panel interface. The panel interface includes a display screen, a plurality of discrete condition lights separate from the display screen, and a touchscreen panel extending across both the display screen and the plurality of condition lights.
US10163303B1 Cash slot machine augmented with secondary currency
A method, apparatus, and computer readable storage to implement an augmented game system. A player can play an online game and accumulate loyalty points without have to pay cash. The player can enter a physical casino and play an electronic gaming machine which can retrieve the player's information from the online game including the number of loyalty points the player has and any other incentives or game add-ons the player would be entitled to. The player would then play a physical game on the electronic game normally (by depositing cash and playing) but the game play would be augmented by virtue of the player having the loyalty points or other incentives or add-ons. For example, the game can be augmented by giving the player a better paytable.
US10163302B2 Gaming system and method for providing a variable award in association with a virtual currency purchase
A gaming system which enables a player to purchase an amount of virtual currency from an online casino wherein the purchased virtual currency includes a predetermined component and a variable component.
US10163301B2 Gaming systems, gaming devices and methods having time based games and magnitudes associated with wagering events in the time based games
A gaming system receives a total wager for a game session which occurs over a designated period of time. The game session includes a plurality of different wagering events. Each of the wagering events is associated with one of a plurality of different magnitudes. For each of the plurality of different wagering events, the gaming system determines: a portion of the total wager amount, and a wager by modifying the determined portion by the magnitude associated with that wagering event. The gaming system causes the wagering event to occur, determines at least one outcome for the wagering event, determines any awards based on the determined wager and the at least one determined outcome, and provides any of the determined awards to the player.
US10163300B2 System and method for enabling a player proxy to execute a gaming event
The gaming system that includes a first gaming machine operated by a first player at a first location and a second gaming machine operated by a second player at a second location. The second location is remote from the first. The first gaming machine is configured to present a game to the first player upon receipt of a wager from the first player. The second gaming machine is configured to present the game to the second player upon receipt of a wager from the second player. The gaming system further includes a processor programmed to receive a request to execute a game play event for the first player. In response to the request, the processor is configured to execute the game play event for the first player and the second player.
US10163298B2 Wagering game wearables
A wagering game system and its operations are described herein. In some embodiments, the operations can include detecting that one or more wearable computers are within a proximity range to a wagering game machine. In some examples, the operations further include determining one or more characteristics associated with the one or more wearable computers in response to the detecting that the one or more wearable computers are within the proximity range to the wagering game machine. In some examples, the operations further include providing a feature associated with a wagering game based on the one or more characteristics of the one or more wearable computers.
US10163295B2 Gaming machine, gaming machine control method, and gaming machine program for generating 3D sound associated with displayed elements
A gaming machine for providing a game to a player is described herein. The gaming machine includes a housing, a sound reproduction system coupled to the housing, a display device, and a gaming controller. The sound reproduction system is configured to generate sound features associated with the game and to emit 3D sound effects within a listening space associated with the gaming machine. The gaming controller randomly determines an outcome of the game and display the outcome on the display device, detects a triggering condition occurring in the outcome of the game, and determines a game feature in response to detecting the triggering condition and causes the sound reproduction system to generate a sound feature including a 3D sound effect traveling along a sound path orientated with respect to a listening reference point defined within the listening space to facilitate simulating a game element moving within the listening space.
US10163293B2 Networked vendor for workplace or controlled environment
Aspects of the invention described herein provide an apparatus and method for networked vending. According to embodiments described herein, a vending machine is provided that may be installed and managed by the venue in which it is installed. Consumers may purchase vending products from the vending machine using cashless accounts managed by an external device in communication with the vendor. The venue may manage the inventory for the vending machine by placing orders for single product inserts to be loaded in the vending machine.
US10163289B2 Systems and methods for secure lock systems with redundant access control
Systems and methods for providing secure locks having redundant access channels are disclosed. In some embodiments of the invention, the smart lock has a hardware processor, a power source, a cylinder, a button that forms a rose knob, and a rose protector. The rose knob and rose protector protect and conceal the hardware processor, the power source, and the cylinder. The rose protector forms an annular groove that slidably interlocks with the rose knob. The rose knob has a plurality of redundant access channels for receiving authentication information. The redundant access channels may include a biometric scanner for receiving biometric information, a passcode keypad for entering a token, or a wireless transceiver for receiving a token from a mobile device and transmitting a response to the mobile device. When the user cannot open the lock through the first redundant access channel, the smart lock is configured to allow access through a second access channel.
US10163288B2 Access control using portable electronic devices
To control access to a predetermined service or area, a system receives an activation signal indicative of a user's activation of an access code. As a result of receiving the activation signal, the system sends a verification code to a portable electronic device of the user. An access terminal receives the verification code. Access to the predetermined service or area is granted if the verification code is received at the access terminal meeting one of several predetermined conditions. One condition requires that the verification code is provided to the access terminal within a limited validity time.
US10163283B2 Method and apparatus for finding and accessing a vehicle fueling station, including an electric vehicle charging station
A control system and method are provided for a station to dispense fuel to a vehicle, including an electric vehicle, without requiring dedicated access to a communications network, with the advantage that authorization for fleet vehicles or individuals can be obtained from an access management system, using a portable, wireless device, such as a smart phone or a dashboard appliance. The authorization is wirelessly relayed to the station by the wireless device, to enable the dispensing of fuel. Subsequently, a log comprising the transaction is provided to the access management system, through the same or a different wireless, mobile computing device. The log may also report status and other events, such as load shedding.
US10163280B1 Method and system for displaying and using PID graph indicators
An example method includes receiving, at a computing system, parameters from a vehicle, wherein the parameters correspond to a set of associated parameter identifiers (PIDs), and determining, by the computing system, one or more thresholds for one or more PIDs of the set of associated PIDs. The example method additionally includes determining, by the computing system, one or more indicators displayable on a first graph of parameters corresponding to a first PID of the set of associated PIDs. For instance, at least one indicator of the one or more indicators represents a parameter corresponding to a second PID of the set of associated PIDs breaching a threshold associated with the second PID. The example method further includes displaying, by the computing system on a graphical user interface, the first graph of parameters corresponding to the first PID and the one or more indicators on the first graph.
US10163273B2 Method and system for operating mobile applications in a vehicle
In various embodiments, a user interacts with remotely executing mobile applications from a vehicle. The vehicle may include at least one computer that includes a human machine interface (HMI) for control by the user. The mobile applications may be executing on an application server that is remote from the vehicle and communicating with the at least one computer. Further, the mobile applications may be configured to receive inputs from and transmit outputs to the at least one computer. An HMI application executing on the at least one computer may enable the provisioning of one or more services of the HMI to the mobile applications so that inputs and/or outputs to the mobile applications may be exchanged. Vehicle-based operation of the mobile applications from the at least one computer via the HMI may thus be enabled.
US10163271B1 System for multimedia spatial annotation, visualization, and recommendation
A system configured to provide a three-dimensional representation of a physical environment. The three-dimensional representation including annotation data associated with particular objects and/or viewpoints of the three-dimensional representation. In some cases, the viewpoints may be rendered using image data associated with a photograph captured from a corresponding viewpoint within the physical environment.
US10163269B2 Identifying augmented reality visuals influencing user behavior in virtual-commerce environments
Certain embodiments involve enhancing personalization of a virtual-commerce environment by identifying an augmented-reality visual of the virtual-commerce environment. For example, a system obtains a data set that indicates a plurality of augmented-reality visuals generated in a virtual-commerce environment and provided for view by a user. The system obtains data indicating a triggering user input that corresponds to a predetermined user input provideable by the user as the user views an augmented-reality visual of the plurality of augmented-reality visuals. The system obtains data indicating a user input provided by the user. The system compares the user input to the triggering user input to determine a correspondence (e.g., a similarity) between the user input and the triggering user input. The system identifies a particular augmented-reality visual of the plurality of augmented-reality visuals that is viewed by the user based on the correspondence and stores the identified augmented-reality visual.
US10163267B2 Sharing links in an augmented reality environment
Various embodiments provide methods and systems for users and business owners to share content and/or links to visual elements of a place at a physical location, and, in response to a user device pointing at a tagged place, causing the content and/or links to the visual elements of the place to be presented on the user device. In some embodiments, content and links are tied to specific objects at a place based at least in part upon one of Global Positioning System (GPS) locations, Inertial Measurement Unit (IMU) orientations, compass data, or one or more visual matching algorithms. Once the content and links are attached to the specific objects of the place, they can be discovered by a user with a portable device pointing at the specific objects in the real world.
US10163264B2 Method and apparatus for multiple mode interface
Each of a world space, a sphere space, and a display space are adapted to accept at least one entity therein, the entity being a virtual reality entity or an augmented reality entity. For world space, translation by a viewer substantially corresponds with translation with respect to world space, and rotation by the viewer substantially corresponds with rotation with respect to world space. For sphere space, translation by the viewer corresponds with substantially zero translation with respect to sphere space, and rotation by the viewer substantially corresponds with rotation with respect to sphere space. For display space, translation by the viewer corresponds with substantially zero translation with respect to display space, and rotation by the viewer corresponds with substantially zero rotation with respect to display space. Exceptions for translating, rotating, and/or resizing any of world space, sphere space, and display space may be invoked.
US10163262B2 Systems and methods for navigating through airways in a virtual bronchoscopy view
Systems and methods for displaying virtual bronchoscopy views while navigating through an airway of a virtual bronchoscopy are disclosed. The method comprises determining a first location and a first direction at the first location, storing the first location and the first direction in memory, displaying a first virtual camera view corresponding to the first location, determining a second location corresponding to movement through the airway of the virtual bronchoscopy, storing the second location in the memory, displaying a second virtual camera view corresponding to the second location, determining a second direction based on the first location and the second location, storing the second direction in the memory, determining a third location corresponding to further movement through the virtual bronchoscopy, and determining whether the further movement is in a forward direction or a backward direction.
US10163260B2 Methods and apparatus for building a three-dimensional model from multiple data sets
Methods and apparatus for a map tool displaying a three-dimensional view of a map based on a three-dimensional model of the surrounding environment. The three-dimensional map view of a map may be based on a model constructed from multiple data sets, where the multiple data sets include mapping information for an overlapping area of the map displayed in the map view. For example, one data set may include two-dimensional data including object footprints, where the object footprints may be extruded into a three-dimensional object based on data from a data set composed of three-dimensional data. In this example, the three-dimensional data may include height information that corresponds to the two-dimensional object, where the height may be obtained by correlating the location of the two-dimensional object within the three-dimensional data.
US10163254B2 Rendering of digital images on a substrate
Techniques and systems are described to render digital images on a defined substrate. In an example, a three-dimensional model is generated of the digital image as disposed on a substrate. Generation of the model includes application of a three-dimensional model of a surface of the substrate to the digital image and addition of material properties of the substrate to the three-dimensional model of the digital image). A viewing direction is detected of the three-dimensional model of the digital image, the detecting based on one or more sensors of the computing device. An effect of light is also ascertained on the three-dimensional model of the digital image having the material properties of the substrate at the detected viewing direction. The three-dimensional model of the digital image is rendered based on the detected viewing direction and the ascertained effect of light for display by the computing device.
US10163245B2 Multi-mode animation system
Animations are displayed on a user interface (UI) of a computing device using one of multiple different animation system modes, each animation system mode operating in a different manner to determine how to change the display for an animation. The animation can be on a particular object that is displayed by the computing device (e.g., scrolling a list, moving an icon or character from one location to another) and/or can be on the display as a whole (e.g., panning or scrolling a view of the whole display). The multi-mode animation system operates to select an animation system mode on a frame by frame basis. For each frame of content being displayed on the display device, the multi-mode animation system selects an appropriate one of the animation system modes to use for generating the content of that frame.
US10163244B2 Creating reusable and configurable digital whiteboard animations
Methods and systems for creating animation elements from digital drawings. In particular, one or more embodiments detect a digital drawing input stream including a plurality of strokes. One or more embodiments identify a plurality of stroke points for each stroke from the plurality of strokes, and determine a plurality of timestamps for the plurality of stroke points. One or more embodiments generate an animation element based on the plurality of stroke points and the plurality of timestamps. One or more embodiments also receive a selection to insert the animation element into a user interface, and insert the animation element with associated drawing time information and stroke point information into the user interface in response to the received selection.
US10163242B2 Energy grid data platform
Techniques are disclosed for an energy grid data platform through which information associated with an electrical grid can be accessed by one or more entities. In some embodiments, an energy grid data platform includes one or more modeling engines configured to receive data associated with an electrical grid and generate data models describing various aspects of the electrical grid. For example an electrical grid model describing the state of the electrical grid at one or more points of connection may be based at least in part on data received from sensors at the edge of the electrical grid. As another example, a physical grid model describing the physical arrangement and logical relationships between physical objects associated with the electrical grid can be generated based at least in part on received imagery data. In some embodiments, aspects of an electrical grid model and physical grid model can be combined into an operational grid model that associates real-time operating information with the certain identified physical objects associated with the electrical grid. Information based on the one or more generated models of the electrical grid can be accessed via the energy grid platform as a cloud-based service, for example, via a web interface or an augmented reality display device.
US10163235B2 Line and area chart performance by data filtering
Systems and methods are disclosed that, in various embodiments, improve chart performance by data filtering. In one aspect, the disclosed techniques allow all visible local maxima and minima to be rendered without having their values altered. In another aspect, the disclosed techniques filter data by skipping points evenly. In some embodiments, every horizontal pixel contains two points, so the line is visually uniform. This can dramatically enhance visualizations where data point intervals are uneven (e.g., having “mixed frequency”). Using a two point per pixel approach, the disclosed techniques ensure that a resulting simplified line looks almost identical to the original line by drawing at the limit of the screen resolution. The disclosed techniques allow for an algorithmic complexity of O(n), which is significantly faster than existing solutions.
US10163233B2 Image reconstruction
Methods and apparatus, including computer programs encoded on a computer storage medium, for image reconstruction are provided. According to an example of the methods, an image reconstruction may be performed to generate a first set of reconstructed data with a first set of projection data comprising a plurality of first projection data each corresponding to a respective projection angle of a plurality of projection angles. A second set of projection data comprising second projection data for each projection angle may be generated with the first set of reconstructed data. The first set of projection data may be corrected based on a shifting distance between the first projection data and the second projection data for each projection angle. Then, a second set of reconstructed data may be generated with the corrected first set of projection data, and a reconstructed image may be generated according to the second set of reconstructed data.
US10163232B2 Tomographic reconstruction system
A tomography system having a central processing unit, a system memory communicatively connected to the central processing unit, and a hardware acceleration unit communicatively connected to the central processing unit and the system memory, the hardware accelerator configured to perform at least a portion of an MBIR process on computer tomography data. The hardware accelerator unit may include one or more voxel evaluation modules which evaluate an updated value of a voxel given a voxel location in a reconstructed volume. By processing voxel data for voxels in a voxel neighborhood, processing time is reduces.
US10163231B2 Magnetic resonance imaging apparatus and image processing apparatus
A magnetic resonance (MR) imaging apparatus of embodiments includes processing circuitry. The processing circuitry generates a third k-space data group including a first k-space data group and a second k-space data group, by adding the second k-space data group that is arranged in a second range adjacent to a first range, to the first k-space data group that is arranged in the first range and that is undersampled along at least one of the axes in k-space as well as in any axis that is different from the axes in the k-space. The processing circuitry generates an MR image group by performing a reconstruction process on the third k-space data group.
US10163230B2 System and method for applying a reflectance modifying agent to change a person's appearance based on a digital image
A computer-controlled system determines attributes of a frexel, which is an area of human skin, and applies a reflectance modifying agent (RMA) at the pixel level to automatically change the appearance of human features based on one or more digital images. The change may be based on a digital image of the same frexel, for as seen in a prior digital photograph captured previously by the computer-controlled system. The system scans the frexel and uses feature recognition software to compare the person's current features in the frexel with that person's features in the digital image. It then calculates enhancements to the make the current features appear more like the features in the digital image, and it applies the RMA to the frexel to accomplish the enhancements. Or the change may be based on a digital image of another person, through the application of RMAs.
US10163228B2 Medical imaging apparatus and method of operating same
Provided is a medical imaging apparatus including: an image processor configured to extract properties that an object has with respect to at least one feature, based on a plurality of medical images of the object; and a controller configured to control a display to display a first medical image from among the plurality of medical images and the extracted properties and display a first property shown in the first medical image from among the properties and a second property not shown in the first medical image in such a manner that the first property and the second property are distinguished from each other.
US10163227B1 Image file compression using dummy data for non-salient portions of images
A computer-implemented method is provided for retrieving an image from a user in a desired format and for detecting a compression efficiency for the image. When the compression efficiency is above a pre-selected threshold the computer-implemented method includes obtaining a saliency representation of the image, capturing a feature description of a non-salient portion of the image, flattening the non-salient portion in a new image, storing the new image in a selected format in a memory and storing a background descriptor for the image in the memory.
US10163226B2 Online calibration of a motor vehicle camera system
The invention relates to a method for calibrating a camera system (7) of a motor vehicle (1). At least one camera (8-11) respectively sequentially generates camera images (21-28) from an environment (2) of the motor vehicle (1). A computing device (12) generates a virtual view (14) of the environment (2) from a virtual perspective from the camera images (21-28) by means of a projection (P). In traveling, the computing device (12) passes at least once a calibration cycle for each camera (8-11). Based on current projection parameters (30) of the projection (P), therein, camera images (23, 24) of the camera (9) are transformed. Motion vectors are determined from it. For at least one geometric characteristic of the motion vectors, a reference value is set. From a difference between the at least one geometric characteristic of the motion vectors and the respective corresponding reference value, an error value is determined. Depending on the error value, new projection parameters are determined (30).
US10163223B2 Automatic analyser
A two-dimensional code is attached to a location of a reagent storage unit which is visually recognizable from the outside, and a coordinate position of the two-dimensional code in a coordinate system of the two-dimensional code and coordinate information of an installation position of a reagent bottle are held. After that, an image of the two-dimensional code is captured by a portable terminal so that a coordinate system of an image capture unit of the portable terminal is converted into the coordinate system of the two-dimensional code using AR technology. The coordinate information of the installation position of the reagent bottle in the coordinate system of the two-dimensional code is regarded as positional coordinates in the captured image on the basis of the conversion, thereby ascertaining the position of the reagent bottle on the captured image and displaying the ascertained position on a display unit.
US10163221B1 Measuring geometric evolution of a high velocity projectile using automated flight video analysis
Systems and methods are provided to quantify the geometric change of a projectile during ballistic flight using a camera/tracker video system. Image processing tools are used to segment the shape of the projectile in each frame of a launch video, which allows the length to be calculated with sub-pixel accuracy. Subsequent automated analysis uses a baseline length history of a constant length projectile to correct for variations in measured length due to system layout and camera location.
US10163220B2 Efficient hybrid method for ego-motion from videos captured using an aerial camera
Described is a system for compensating for ego-motion during video processing. The system generates an initial estimate of camera ego-motion of a moving camera for consecutive image frame pairs of a video of a scene using a projected correlation method, the camera configured to capture the video from a moving platform. An optimal estimation of camera ego-motion is generated using the initial estimate as an input to a valley search method or an alternate line search method. All independent moving objects are detected in the scene using the described hybrid method at superior performance compared to existing methods while saving computational cost.
US10163216B2 Automatic mode switching in a volume dimensioner
Dimensioners and methods for dimensioning an object includes capturing, using a dimensioning system with a single sensor, at least one range image of at least one field-of-view, and calculating dimensional data of the range images and storing the results. Wherein, the number of views captured of the object is automatically determined based on one of three modes. The first mode is used if the object is a cuboid, or has no protrusions and only one obtuse angle that does not face the point of view, where it captures a single view of the object. The second mode is used if the object includes a single obtuse angle, and no protrusions, where it captures two views of the object. The third mode is used if the object includes a protrusion and/or more than one obtuse angle, overhang, protrusion, or combinations thereof, where it captures more than two views of the object.
US10163214B2 Device and method for analyzing thermal images
This invention provides a device and method for analyzing thermal images, which relates to a thermal imaging device and an applied field of infrared detection. The conventional thermal imaging device is excessively dependent on subjective experience of users to set an analysis area of a thermal image during photographing, causing complicated operation and a discrete analysis result. In the invention, a reference image reflecting predetermined morphological characters of a photographed body is superimposed and displayed in an infrared thermal image, and is as a visual reference of the photographed thermal image, thereby allowing the set analysis area to be convenient for photographing the next similar body, to reduce setting operation of the users. The body thermal image may be analyzed via the analysis area corresponding to the reference image according to a specified analysis mode, to acquire an analysis result. Thereby, the common users can achieve the better photographing level.
US10163212B2 Video processing system and method for deformation insensitive tracking of objects in a sequence of image frames
Various aspects of a video processing system and method are provided for object tracking in a sequence of image frames are disclosed herein. The video processing system includes one or more circuits in an electronic device that acquires the sequence of image frames, which comprises at least a current image frame and a next image frame including an object. A distribution of first pixel values in a first image space associated with a first region, which corresponds to the object in the current image frame, is determined. Based on the distribution, the current image frame is transformed to a modified current image frame that includes at least a second region that corresponds to the first region and is associated with second pixel values in a second image space. Based on one or more features extracted as a template associated with the second region, the object is tracked in the next image frame.
US10163211B2 System and method for enhanced visualization of multiple low contrast objects within an imaged subject
A method for enhancing the visualization of a plurality of objects within an imaged subject. The method includes acquiring a plurality of images of the plurality of objects disposed in the imaged subject and supported by a plurality of guide wires; generating a complex deformation field based at least in part on a plurality of landmarks disposed in the plurality of images; and generating a composite image based at least in part on the complex deformation field. The complex deformation field models deformation induced on the plurality of objects by at least two or more guide wires of the plurality.
US10163209B2 Medical image processing apparatus, medical image processing method, and X-ray CT apparatus
A medical image processing apparatus according to an embodiment includes processing circuitry. The processing circuitry acquires image data including image data of a blood vessel of a subject. The processing circuitry performs analysis related to the blood vessel by using the image data, and specifies a region of interest in the blood vessel based on a result of the analysis. The processing circuitry performs fluid analysis on a region other than the region of interest at a first accuracy, and performs fluid analysis on the region of interest at a second accuracy that is higher than the first accuracy.
US10163208B2 Evaluation of carotid plaque using contrast enhanced ultrasonic imaging
An ultrasound system and method are described for acquiring a sequence of ultrasound images of the carotid artery during the delivery of a contrast agent. Plaque in the images is identified and a time-intensity curve is calculated for pixels in the images. The intensity values before and after the arrival of contrast are compared to identify pixels or groups of pixels having perfusion. An anatomical image may be formed showing areas in an image of the plaque of the intensity and presence of perfusion, or the perfusion may be quantified by determining the percentage of pixels in the plaque image which exhibit perfusion. The extent and degree of perfusion is an indicator of the risk of plaque particulates in the blood stream which may lead to stroke-related symptoms.
US10163204B2 Tracking-based 3D model enhancement
A method for enhancing a three-dimensional (3D) reconstruction of an object comprises obtaining a signal indicative of a static 3D reconstruction of an object disposed in a tracking space, co-registering the 3D reconstruction to the 3D tracking space, collecting enhancement data from a tracked tool disposed in the 3D tracking space, and adding real-time features of the object to the static 3D reconstruction using the enhancement data. A system for enhancing data obtained by a medical system includes an electronic control unit configured to receive a first signal for a static 3D reconstruction of an organ, co-register the static 3D reconstruction to a 3D tracking space for a tracked tool, receive a second signal for enhancement data generated by the tracked tool operating within a region of interest of the organ, and add real-time features of the area of interest to the static 3D reconstruction using the enhancement data.
US10163200B2 Detection of items in an object
This disclosure relates to a system and method for detecting an item having at least one symmetry property inside an inspection object based on at least one transmission image. The method includes the steps: (a) detection of edges of individual items contained in the transmission image in order to produce an edge image; and (b) detection of the item by determining a symmetry line that can be associated with an item with at least one symmetry property contained in the transmission image based on pairs of edge picture elements of the edge image that are positioned symmetrically to each other relative to the symmetry line; and in step (b), in determining the symmetry line in the edge image, the only edge picture elements that are taken into account are those for which the symmetry line lies in an item contained in the transmission image, to which item the edge belongs.
US10163199B2 Recirculating aquaculture system and treatment method for aquatic species
A recirculating aquaculture system automatically controls ammonia, bacteria, solids, and feed quantity available to a captive species in a closed, water-based habitat. Functionally Independent processing loops operate in parallel on recirculating water streams, to control each of ammonia, bacteria, solids, and feed. The same or similar components, such as an electrolytic cell, may service one or more functional loops.
US10163192B2 Image encoding apparatus and method of controlling the same
This invention enables compression-coding of image data of a Bayer arrangement more efficiently. For this purpose, an encoding apparatus includes a generation unit which generates, from G0 and G1 component data of the image data of the Bayer arrangement, a GL plane formed from low-frequency component data of a G component and a GH plane formed from high-frequency component data of the G component, a luminance/color difference transforming unit which generates, from R and B component data of the image data of the Bayer arrangement and the GL plane, a luminance plane, a first color difference plane, and a second color difference plane, and an encoding unit which encodes the luminance plane, the first color difference plane, the second color difference plane, and the GH plane.
US10163191B2 Method of scaling up image
A method for scaling up an image in a display device includes acquiring luminance data and color data of a plurality of pixels in the image; generating high frequency components according to the luminance data of a first pixel and a plurality of second pixels adjacent to the first pixel in each set of adjacent pixels among the plurality of pixels; adjusting the high frequency components corresponding to each set of adjacent pixels, for making a sum of the high frequency components corresponding to each set of adjacent pixels to be within a predetermined range; and transforming the luminance data of the first pixel, the high frequency components and duplicating the color data of the first pixel in each set of adjacent pixels, to generate image data of a plurality of scaling-up points between the first pixel and each of plurality of second pixels in each set of adjacent pixels.
US10163190B2 Screen display ratio adjusting apparatus and method
A screen display ratio adjusting apparatus includes a handheld device and a display device. The handheld device includes an application module which obtains an image of a pre-stored picture being displayed on a display interface of the display device (“test picture”). The pre-stored picture includes a first section and a second section. The application module calculates respective lengths and widths of the first and second sections from the test picture. The application module further calculates a display size ratio between the first section and the second section, and adjusts a display size of the first section. The display device is then configured to display the first section in an adjusted size. A screen display ratio adjusting method is also provided.
US10163189B2 Automatically enabling a read-only cache in a language in which two arrays in two different variables may alias each other
A method and system are provided for executing, by a processor including a read-only cache, a program having a plurality of variables including a first variable and a second variable. Each variable is for executing a respective read operation or a respective write operation for an object. The method includes providing a first code that uses the read-only cache and a second code that does not use the read-only cache. The method further includes determining, by the processor, whether a first object designated by the first variable is aliased or not aliased with a second object designated by the second variable. The method also includes executing, by the processor, the first code when the first object is not aliased with the second object, and the second code when the first object is aliased with the second object.
US10163188B2 Method and apparatus for arranging pixels of picture in storage units each having storage size not divisible by pixel size
A buffer write method for a buffer, including a plurality of M-bit storage units, has following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; calculating a corresponding start address of the buffer for the pixel data of the first N-bit pixels; and storing the first N-bit pixels of the picture according to the calculated start address of the buffer in the M-bit storage units by a buffer controller. The storing step includes fully storing at least one of the first N-bit pixels in one of the M-bit storage units storage units, wherein M and N are positive integers, and M is not divisible by N.
US10163186B2 Management of a plurality of graphic cards
The invention notably relates to a computer-implemented method for modifying a number of graphic cards used for rendering a scene, a graphic card comprising one or more graphic processing units. The method comprises providing a scene that is already loaded in a render engine, the scene comprising at least one graphic data to be used for rendering a view of the scene; modifying an abstract graphic resource for a graphic resource of the at least one graphic data, the abstract graphic resource storing an identifier of the graphic resource for each graphic card, by adding a new identifier of the said graphic resource for each newly added graphic card; transferring, on each newly added graphic card, the said at least one graphic data already stored on one of the graphic cards.
US10163184B2 Graphics performance for complex user interfaces
Techniques for providing enhanced graphics in a user interface by efficiently using enhanced graphics resources. A computing device displays the enhanced graphics in an upper view of the user interface and the enhanced graphics resources identify a visual region in which the enhanced graphics are positioned. The computing device accesses the enhanced graphics resources to identify and store a hit test region based on the visual region. The hit test region is stored separately from the enhanced graphics resources for hit testing. When a hit is received in the user interface, the computing device determines whether the upper view or lower view will respond to the hit based on the hit test region that is stored separately from the enhanced graphics resources.
US10163182B2 Command input method and display system
A command input method includes: converting an original pixel data into command embedded pixel data based on a command to control a device, the command being embedded in the command embedded pixel data; transmitting the command embedded pixel data from a host to the device; extracting the command from the command embedded pixel data; and controlling the device according to the extracted command.
US10163180B2 Adaptive memory address scanning based on surface format for graphics processing
This disclosure describes an adaptive memory address scanning technique that defines an address scanning pattern, to be used for a particular surface, based on one or more properties of the surface. In addition, a number, shape, and arrangement of sub-primitives of a surface to process in parallel may be determined. In one example of the disclosure, a memory accessing method for graphics processing comprises, determining, by a graphics processing unit (GPU), properties of a surface, determining, by the GPU, a memory address scanning technique based on the determined properties of the surface, and performing, by the GPU, at least one of a read or a write of data associated with the surface in a memory based on the determined memory address scanning technique.
US10163179B2 Method and apparatus for intelligent cloud-based graphics updates
An apparatus and method are described for cloud-based graphics updates. For example, one embodiment of an apparatus comprises a system optimization agent to detect a graphics application installed on the apparatus, the system optimization agent to responsively transmit, over a network, information related to the graphics application including a new graphics application or a new version of an existing graphics application. The apparatus may further comprise the system optimization agent to receive, over the network, optimized program code comprising one or more optimizations to specified portions of a graphics driver, where the one or more optimizations relate to the graphics application. The apparatus may further comprise the system optimization agent to install and enable only those specified portions of the graphics driver for which optimizations have been received, where the installation and enablement triggers at least one of increased user experience and increased performance relating to the graphics application.
US10163175B2 System and method for improving healthcare through social robotics
A computerized system comprising a social robot for interacting with a patient in order to improve the patient's adherence to a health or medical regime. A patient is instructed to perform a health activity (e.g., take medication, step on scale, measure glucose, play a game) at certain intervals in order to reach a specified goal or expected result. The results of the health activity are recorded in a wireless health device and transmitted to a computer. The computer interprets the result of health activity and communicates an action to the robot. If the patient performs the activity within a specified interval and results are consistent with the specified goal or expected result, the robot communicates relief or pleasure. If the patient does not perform the activity within a specified interval, or if the results are not consistent with the specified goal or expected result, the robot communicates anxiety, disappointment or exhibits symptoms of an effect such as hunger or illness.
US10163174B2 Methods, systems, and computer program products for evaluating a patient in a pediatric intensive care unit
Methods, systems, and computer program products for evaluating a patient in a pediatric intensive care unit (PICU) are disclosed. According to one aspect, a method may include collecting physiological data associated with a patient upon admission to a PICU and at least once after admission to the PICU. The physiological data may be associated with a statistical model, and a risk of mortality of the patient may be continually determined.
US10163173B1 Methods for generating a cover photo with user provided pictures
A method for generating a cover photo for presenting on a profile page includes receiving a request from a user to generate a cover photo for presenting on a profile page of the user account. A user interface identifying a plurality of slots for inserting the pictures/assets selected by the user, is presented at the profile page in response to the request. User selection of pictures/assets for placement in the plurality of slots at the user interface, is received. The pictures/assets are examined for assembling the selected picture/asset into a mosaic. The examination determines open slots that are available for inserting the pictures/assets and a sequence of insertion of the pictures/assets into each of the open slots in the user interface. A unified cover photo is generated by stitching together the one or more pictures/assets selected by the user based on sequence of insertion obtained through examination.
US10163170B2 Method and system for designing a product configuration
An authoring environment is provided by which a modeler can design a product configuration model from which a user interface is generated, the latter of which is user-interactable (or customer-interactable) for product configuration. A plurality of options offered for a particular product are definable, and states, which can correspond to respective user interface screens, for example, are definable, which refer to defined options. The modeler can use the authoring environment to associate groups of one or more previously defined options with respective ones of the defined states, for example, for population of the screens to which the states correspond with the associated group of options. The authoring environment provides for the modeler to be able to define transition rules between the defined states/screens. A modeler engine converts the model designed using the authoring environment into a product configuration usable by customers.
US10163169B2 Wage index navigator system
A healthcare wage index reporting method and system providing questions and tasks to collect information for filling out a wage index and occupational mix report; receiving responses; processing the responses to complete the report; checking the responses to detect errors; generating error notices; tracking progress; and generating a completed report for submission. Electronic data files, including PUFs, can be imported to complete the report, or to pre-populate responses, and the system can generate notifications of differences between the report and the imported file. A dashboard can display progress, and current results. The system can save supporting documents, and supply templates for supporting information. The system can generate prompts based on responses, and determine future questions based on past responses. The system can generate various user-requested reports and can include bulletin board functionality.
US10163168B2 System for selective rendering of multiple alternating images on a graphical user interface
A system provides on a graphical user interface user-selectable options corresponding to a first type and a second type of enhanced coverage options, available for a covered property, each of the enhanced coverage options providing one or more improvements to a property covered under a property insurance policy, in accordance with universal design principles, in the event of an incurred loss to the covered property. Responsive to user selection of a type, alternating images including an image of a damaged property and an image of the damaged property after repair and an improvement in accordance with universal design principles corresponding to the selected type of enhanced coverage option, are displayed.
US10163167B1 Systems and methods for vehicle accident detection based on intelligent micro devices
Intelligent micro devices on a vehicle can be scanned or read using a reading device. A map or data indicative of the micro devices on the vehicle can be generated by scanning the vehicle. The data or map may be used to determine loss or transfer of one or more micro devices on the vehicle. An accident associated with the vehicle can be determined based on loss or transfer of one or more the micro devices. The micro devices can store data associated with the vehicle, including an identity of the vehicle and a history of the vehicle. The micro devices can be read to determine the identity of the vehicle or another vehicle involved in the accident.
US10163165B1 Systems and methods for impact resistant and photovoltaic windows
An impact-resistant, photovoltaic (IRPV) window system is provided. The system may include an IRPV window coupled to a structure, a controller, and an insurance computing device. The IRPV window may include an impact resistant (IR) layer, a photovoltaic (PV) material that may generate an electrical output, and an electrode coupled to the PV material that may receive the electrical output. The IRPV window may permit a portion of visible light to pass through the IRPV window. The controller may monitor the electrical output and generate a solar profile of the structure based upon the electrical output. The insurance computing device may receive the solar profile and determine if an insurance policy associated with the structure is eligible for a policy adjustment and/or an insurance reward or discount offer.
US10163163B1 System and method to adjust insurance rate based on real-time data about potential vehicle operator impairment
A method includes receiving data about potential impairment of a vehicle operator, wherein the data about potential impairment is generated by: (i) monitoring the vehicle operator with a first optical sensor, and (ii) monitoring an environment ahead of a vehicle operated by the vehicle operator with a second optical sensor. The computer-implemented method further includes assigning a plurality of scores based on the data about potential impairment, wherein each of the plurality of scores corresponds to a respective impairment indicator, and determining an impairment score for the vehicle operator by performing a mathematical operation on the plurality of scores, the impairment score summarizing a level of impairment of the vehicle operator.
US10163155B2 Method and system for obtaining credit
A communications system enabling a first wireless subscriber in need of an instant credit line to use a creditee module on a portable wireless communication device to request credit from a second subscriber that has available credit at a financial institution. The second subscriber uses a creditor module on their device to generate rules for the extension of a credit line guaranteed by the financial institution of the second subscriber. If the rules are met, a credit authorization code is generated by the system and forwarded to the creditee module of the first subscriber's device such that the code can be subsequently used to complete a transaction initiated by the first subscriber to pay a vendor. The vendor may employ a vendor's module to access the issued credit as prescribed by the creditor module.
US10163152B1 Notification of computing capacity status
One or more computing instances are instantiated and allocated to customers. The computing instances have a modifiable interruptibility property that is operable to allow a computing instance to be terminated or reallocated from a first customer to a second customer. Requests for additional computing instances having modifiable interruptibility properties are received. Information pertaining to the instantiated computing instances and requested additional computing instances is provided. The information may include a current status of the instantiated computing instances or requested additional computing resources.
US10163144B1 Extracting data from a catalog
Techniques for extracting unstructured quantitative data may be provided. For example, a process may attempt to extract unstructured quantitative data to form structured data. This quantitative data may be used for searchable ordering of items in an electronic marketplace. For example, a process may attempt to find common attributes amongst several item descriptions. The common attributes may be recognized in the unstructured data, stored as structured data, and incorporated with a network page to allow the user to search for a particular item with a particular attribute. The desired attribute can help narrow a set of results from a search query.
US10163142B2 System and method for estimating bags necessary for items purchased by a consumer
A system and method for estimating a number of bags used in a purchase is disclosed. A method can comprise receiving a transmission indicating an intention by a consumer to purchase an item. Information about the item is retrieved from a database. The information about the item is associated with the consumer in a transaction. The number of bags used for the transaction is estimated. The estimation can be created using the weight and volume of a transaction. The estimation can also take into consideration the fragility, crushability, temperature-sensitivity, or cross-contamination possibility of the item. The estimated number of bags is forwarded to a mobile device. The estimated number of bags is used to determine the likelihood of unpurchased items being taken by the consumer. Other embodiments are also disclosed herein.
US10163140B2 Online merchants to third party warehouse providers broker and order fulfillment system
An online merchants to third party warehouse providers broker and order fulfillment system is coupled with different third party warehouse providers that each operate one or more third party warehouses and a plurality of online merchants that use the services provided by the third party warehouse providers. The online merchants to third party warehouse providers broker and order fulfillment system includes an order fulfillment server to provide a common merchant interface to the services provided by the third party warehouse providers, a common warehouse interface to allow each of the different third party warehouse provider to communicate with the order fulfillment server in a common way including the status of the services they provide and allows each of the different third party warehouse providers to review all services requested by them, and a system operator interface to allow system operators to manage the third party warehouses including creating disaster recovery plans in case of a warehouse failure and generating a reverse invoice for each third party warehouse.
US10163138B2 Communication management system, communication system, communication control method, and recording medium
Example embodiments of the present invention include a communication management system, which stores, for each one of one or more values of quality parameter of content data, an additional charge fee to be added to a basic charge fee for providing a service to transmit content data having the value of quality parameter, receives a request for changing the quality parameter of content data from a currently set value to a value selected by a user at a communication terminal, obtains an additional charge fee associated with the selected value of quality parameter from the memory, and calculates an updated charge fee for transmitting content data having the selected value of quality parameter based on the obtained additional charge fee, and transmits the updated charge fee to the communication terminal for display to the user.
US10163131B2 Three dimensional proximity recommendation system
In various example embodiments, systems and methods to provide proximity recommendations are provided. In example embodiments, data representing prioritized recommendations for a user is received. The data representing the prioritized recommendations is used to generated a composite visual representation by embedding select prioritized recommendations into a visual representation. The composite visual representation presents a higher prioritized recommendation in a more spatially prominent manner than a lower prioritized recommendation. The composite visual representation is then presented to the user.
US10163127B2 Spatiotemporal marketing associated with events based on intended user ingress and egress modes and paths
A method to perform spatiotemporal events marketing includes: presenting, by a server, an interface on a display of a customer device, wherein the interface comprises a selectable list of times in which an event is to occur, determining, by the server, a route to the event or from the event, by a user of the customer device; and presenting, by the server, a selectable list of offers in the interface, wherein the list of offers is based on the selected time, a location of the event, and the route.
US10163125B2 Systems and methods for conducting dynamic media lift studies concurrently with operating online advertising campaigns
Systems and methods are disclosed for conducting media lift studies for online advertising concurrently with operating an advertising campaign. While operating an advertising campaign for a first advertiser/client focused primarily on a set of intended ads and a specific targeted viewer audience, a non-intended ad is occasionally substituted to run in an ad slot, and is tracked as belonging to the first advertiser/client. The non-intended ad can be for example one of: an ad for a second advertiser/client; an alternate ad for the first advertiser/client; or a blank/unrelated ad. After the campaign, attribution results for the intended ads are adjusted according to those for non-intended ads to provide an indication of net media lift resulting from the intended ads—typically at no additional cost to the first advertiser/client. Analysis results may also be compared between different attribution data providers to determine which provide the more accurate attribution data.
US10163121B2 System and method for targeted marketing and consumer resource management
Systems and methods are provided for providing targeted marketing to goods and services provides and consumer resource management services to consumers. An example system and method for targeted marketing comprises collecting transaction data from point-of-sale (POS) terminals and using a consumer identifier in the transaction data to access stored information about the consumer. This information may be used to target offers and advertisement to the consumer. In an example system for consumer resource management, a consumer may configure a consumer account on the enterprise infrastructure via a web-site. The consumer may use the consumer account to purchase and configure gift cards that may be used for purchasing goods and services. A universal transaction identifier may be associated with the consumer account and used to purchase goods and services from more than one selected goods and services providers.
US10163118B2 Method and apparatus for associating user engagement data received from a user with portions of a webpage visited by the user
A method for associating user engagement data with various features of a product associated with a webpage is provided. The method includes detecting a visit to a portion of the webpage by a user. The webpage includes features of the product. A feature from the portion of the webpage is then determined using keyword of the feature. The portion includes the keyword of the feature. A user engagement input is then received for entire webpage from the first user. The webpage includes only one user interface option to provide the user engagement input of a particular type, at an instance, for entire webpage. The user engagement input is associated with the feature and not associated with other features on the webpage. A report indicating association of the user engagement input with the feature and non-association of the user engagement input with other features on the webpage is then generated.
US10163117B2 System, method, and computer program product for model-based data analysis
A system, method, and computer program product for a model-based data analysis system is disclosed. The method includes the steps of receiving information from one or more respondents that includes at least one response to a question included in a first survey, updating a model based on the received information, and generating a second survey based on the updated model. The method may be implemented by a server application communicating with a client application via a network.
US10163111B2 Virtual photorealistic digital actor system for remote service of customers
A system for remote servicing of customers includes an interactive display unit at the customer location providing two-way audio/visual communication with a remote service/sales agent, wherein communication inputted by the agent is delivered to customers via a virtual Digital Actor on the display. The system also provides for remote customer service using physical mannequins with interactive capability having two-way audio visual communication ability with the remote agent, wherein communication inputted by the remote service or sales agent is delivered to customers using the physical mannequin. A web solution integrates the virtual Digital Actor system into a business website. A smart phone solution provides the remote service to customers via an App. In another embodiment, the Digital Actor is instead displayed as a 3D hologram. The Digital Actor is also used in an e-learning solution, in a movie studio suite, and as a presenter on TV, online, or other broadcasting applications.
US10163110B2 Product couponing and sampling method
A targeted method for providing coupons and samples to consumers, that provides extensive feedback to manufacturers, identifies consumers that represent a desired demographic profile, enables a convenient consumer couponing experience, controls and contains fraud through the use of expiration methods and location data.
US10163107B1 Technical fallback infrastructure
In some examples, methods and systems may institute technical fallback by determining, by a payment processing system, and based on analysis of the communication status indicator and the data obtained when a magnetic stripe of the payment object is introduced in magnetic stripe object reader, whether the payment object was swiped while an EMV object reader was communicatively coupled to the POS terminal. If the magnetic stripe of the payment object was swiped while the EMV object reader was connected to the POS terminal, the payment processing system extracts a transaction count indicating a number of times the customer has attempted to insert a chip of the payment object into the EMV object reader prior to swiping magstripe. By comparing the transaction count with a threshold count, the payment processing system authorizes the payment transaction as a technical fallback transaction if the transaction count is greater than the threshold count.
US10163106B2 Systems and methods using a data structure summarizing item information in authorization request messages for communication in transactions involving multiple items
A system and method includes an authorization request message configured with information about transaction amounts of items aggregated according to item categories and applicable rates for the items in the respective categories. Based on the information provided in the authorization request, a transaction handler is configured to compute a modified transaction amount for the transaction by reducing the transaction amount of items in one or more of the categories, without reducing the transaction amount(s) of items in one or more other categories, and computing a total transaction amount based on the reduction and the applicable rates.
US10163102B2 Method and system for using social networks to verify entity affiliations and identities
Login credentials for at least one website, such as a social networking website, are received from a user purporting to act on behalf of an entity, for example, in the context of registering the entity with a system for electronic bill payment. Social data relating to the entity is retrieved from the websites using the login credentials. The social data comprises a plurality of social connections, each reflecting a respective relationship between the entity and a respective third party. A plurality of relevant social connections comprising at least a subset of the plurality of social connections is determined, each social connection of the plurality of relevant social connections reflecting a relationship to a respective third party that is deemed to be reliable. A reliability rating of the entity is then determined based on the plurality of relevant social connections.
US10163101B1 Electronic commerce using a transaction network
The present invention is directed to a transaction network that facilitates and simplifies purchase transactions between any number of customers and any number of merchants. The transaction network is primarily utilized in the sale and purchase of digital content via a network such as the Internet. The transaction network registers and authenticates customer purchase activities and maintains customer account data including payment information. Once registered, a customer will generally not register again for further purchase activities at participating merchant sites. Additionally, the transaction network provides a single, central authentication mechanism for all participating merchant sites using a single customer identifier and password. Further, the transaction network accumulates purchase information across all of the merchant sites and the ultimate payment processing of those purchase transactions. Payment processing generally occurs on a periodic basis, enabling the accumulation of multiple purchase transactions within a participating customer's account. The network additionally preferably provides customers with centralized, automated services for customer account management, product refunds, subscription management and multiple purchasing accounts linked to the same payment account.
US10163098B2 Using both social media and non-social media information to identify anomalous behavior
A method, system and computer program product for identifying anomalous behavior (e.g., suspicious transactions). Information from at least one social media source (e.g., a posting) and from at least one non-social media source (e.g., a booking) are monitored. A transaction (e.g., credit card transaction) involving a user is identified. The monitored information is then analyzed to identify one or more characteristics (e.g., location of the user) of the user. A rating of invalidity of the transaction is generated based on the one or more characteristics, where the rating of invalidity refers to the likelihood that the transaction is likely to be anomaly, such as a suspicious transaction. If the rating exceeds a threshold, then an anomaly may be said to have occurred. By identifying anomalous behavior using both social media and non-social media sources, anomalous activities that truly occurred will be more accurately detected.
US10163097B2 Method and system for contactless financial transactions
A method and system are proposed for financial purchase transactions between a merchant and an employee in possession of a contactless credential device such as a proximity card ordinarily used for access to commercial facilities as in the case of electronically controlled doors and the like. The merchant is provided with a contactless reader device adapted to discern credential device codes. In response to presentation of the credential device at the merchant reader device for the purposes of a financial purchase transaction, the credential device code is discerned using the merchant reader device, the credential device code, together with details of the financial purchase transaction, is electronically communicated to a transaction facilitator, a credit/debit account corresponding to said employee is identified according to a stored database correlation with the credential device code, and the financial purchase transactions details are processed against the identified credit/debit account in order to authorize the financial purchase transaction.
US10163089B2 Systems and methods for providing consumer facing point-of-sale interfaces
Systems, apparatus, methods, and non-transitory media for providing point-of-sale functionality are discussed herein. Some embodiments may include a system including a merchant device and a consumer facing device. The merchant device may include a merchant display device configured to present interactive displays of a merchant facing interface configured to be used by merchants. The consumer facing device may be configured to present interactive displays of a consumer facing interface configured to be used by consumers. The point-of-sale system may be configured to facilitate financial transactions and other forms of consumer service. For example, merchant inputs provided via the merchant facing interface (e.g., entered menu items) may be shown on the consumer facing interface. In another example, consumer inputs provided via the consumer facing interface be sent to the merchant device and/or otherwise used by the merchant device to facilitate a financial transaction, among other things.
US10163088B2 Embedded document within an application
Data structures, methods, program products and systems for creating and executing an executable file for the Binary Runtime Environment for Wireless (BREW) where the file is capable of causing presentation of a document embedded in the file on a BREW system.
US10163087B2 Systems and method for selling content over a network
A method to generate revenue from supplied content is provided. Content is provided to a consumer via a network by providing a content service that allows the consumer to select and retrieve content as a package together with a clearing of the selectable content to an operator used by the consumer to select and retrieve the content via the network. Any content selected by the consumer is supplied directly to the consumer via the operator. The operator is charged for the supplied content.
US10163086B2 Universal payments dashboard
A universal payments dashboard system provides eCommerce merchants with an easy to integrate web page (inline frame) that displays all alternative payment button options that consumers can use on the merchant website(s) to pay for the purchase. Such merchants can display the dashboard on their shopping cart page(s) and on their checkout page(s) at the point where users select the payment option. The dashboard communicates with a payment dashboard provider to complete the payment for the transaction, including any consumer interaction such as entering checking account information, personal details, etc. Upon completing the payment for the order, the dashboard provides the merchant with the completed order information (e.g., a prepaid order) along with all the payment information. The dashboard supports all alternative payment options, payment transaction notifications to enable single cash register functionality and work in conjunction with alternative payment initiatives.
US10163083B2 Account activity management system
Embodiments of the invention are directed to systems, methods and computer program products for use in streamlining customer finance and customer money management platforms and providing electronic financial management. An exemplary apparatus may be configured to provide access to a funds transfer management portal that interfaces with at least one database to access a customer's financial information for use in presenting account activity associated with at least one of the customer's accounts maintained by a financial institution. The system receives a request to view account activity in which the request specifies a format for viewing the account activity. In response to receiving the request, the system retrieves data related to one or more funds transfers associated with the at least one account and present the account activity in the requested format for viewing the account activity.
US10163081B2 Method and system for automatically collecting payment for a credit account
A method for automatically collecting payment for a credit account includes determining if a credit account is delinquent and determining the number of days the credit account is delinquent. The method includes automatically collecting a first amount from a first account if the number of days the credit account is delinquent comprises at least a first number of days and crediting the credit account the first amount. The first account may comprise a checking account, and the first number of days may comprise twenty days.
US10163077B2 Proxy for asynchronous meeting participation
Embodiments described herein relate to enabling a lightweight way of recording and sharing video messages intended to provide input to a future meeting that cannot be personally attended. A person who cannot attend the meeting pre-records their thoughts and remarks for the meeting as video clips for presentation at the meeting. A physical device with at least a display is presented at the meeting. The physically present participants can play the pre-recorded clips on the device. Video of participants' responses to the clips is recorded and made available so that the represented attendee can view the participants' responses.
US10163075B2 Bulk event scheduling
A system can provide for scheduling of a collection of events for a user of the system by including a non-transitory memory storing user information comprising schedule information for a plurality of users and including a hardware processor in communication with the non-transitory memory. The hardware processor accesses schedule information of a first user of the plurality of users and accesses schedule information for a subset of users of the plurality of users, each of the subset of users being associated with the first user. The processor also receives selections from the first user regarding at least two events and determines events from a plurality of potential events that satisfy the selections and that optimize potential participation of the subset of users associated with the first user.
US10163069B2 Autonomous delivery of items
Proposed is an autonomous vehicle (AV) for delivering an item to a recipient at a delivery location in a trusted manner. The AV includes: a sensor system adapted to detect, while the autonomous vehicle is travelling to the delivery location, a value of a property of at least one of: the autonomous vehicle, and the item. The AV further includes a data store adapted to store authentication data for verifying the trustworthiness of the item, the authentication data being based on the value detected. The AV further includes a recipient verification unit adapted to verify the identity of the recipient and to generate a verification signal indicative of whether the identity of the recipient is verified. The AV further includes a communication unit adapted to communicate stored authentication data to an authentication system for verification.
US10163068B2 Manual station systems and methods
A pharmaceutical filling system for a high volume pharmacy is described. The system can include a manual pick/pack device and method. The system may include a rotation assembly, a left door and a right door, both positioned below the rotation assembly, a left divider positioned below the left door, and a right divider positioned below the right door, and a left gathering table positioned below the left divider, and a right gathering table positioned below the right divider. The system may also include a control device in electronic communication with the rotation assembly, the doors and the dividers for control of same.
US10163066B1 Allocating computing resources based on service-level requests
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for allocating resources. In one aspect, a method includes identifying a first set of computing resources used to provide the first computing service. A first resource level bid is determined for each particular computing resource of the set of computing resources. A competing request statement can be identified based on the competing request statement's second computing service requiring a proper subset of the first set of computing resources. The second computing service can be at a different level within a request hierarchy than the first computing service. A second resource level bid can be determined for each computing resource of the proper subset of resources using a competing bid for the second computing service. A determination can be made that allocation of the first set of computing resources to the first resource requester meets an allocation objective.
US10163059B2 Conversation branching for more efficient resolution
A method for conversation branching may include storing a plurality of messages communicated in an online conversation and generating a fingerprint for each message. The fingerprint for each message may be stored in a lookup table. The method may also include detecting a new message from one of the users and processing the new message to generate an artifact that correlates to the new message. The lookup table may be queried using the artifact to determine a similarity between the new message and each of the stored messages. One or more proposed reply messages to the new message may be generated for branching the online conversation to a new conversation point that corresponds to a selected one of the one or more proposed reply messages. The one or more proposed reply messages are based on one of the stored messages that has a closest similarity to the new message.
US10163058B2 Method, system and device for inferring a mobile user's current context and proactively providing assistance
A device, method and system for automatically inferring a mobile user's current context includes applying a user activity knowledge base to real-time inputs and stored user-specific information to determine a current situation. Automated reasoning is used to infer a user-specific context of the current situation. Automated candidate actions may be generated and performed in accordance with the current situation and user-specific context.
US10163057B2 Cognitive media content
A method, system and computer-usable medium for providing composite cognitive insights comprising receiving streams of data from a plurality of data sources; processing the streams of data from the plurality of data sources, the processing the streams of data from the plurality of data sources performing data enriching and generating a sub-graph for incorporation into a cognitive graph; processing the cognitive graph, the processing the cognitive graph providing a plurality of individual cognitive insights; generating a composite cognitive insight, the composite cognitive insight being composed of the plurality of individual cognitive insights; and, providing the composite cognitive insight to a user via a set of cognitive media content.
US10163053B2 Coded tags encoded using different magnetic materials and systems of detecting coded tags
A coded tag includes a substrate. The coded tag includes a first magnetic material associated with the substrate. The first magnetic material has a first magnetic characteristic and encodes first information. The coded tag includes a second magnetic material associated with the substrate. The second magnetic material encodes second information and has a second magnetic characteristic that is different from the first magnetic characteristic.
US10163051B1 Portable card with transaction display function
A portable card with transaction display function includes a card body; a microprocessor arranged on the card body; a contact communication unit, a transaction display mode control unit and a power supply unit having a contactless RF antenna, all arranged on the card body and electrically connected to the microprocessor; a transaction display unit arranged on the card body and electrically connected to the transaction display mode control unit. When making a contactless transaction, approach the card body to a read module and the contactless RF antenna of the power supply unit reads electromagnetic wave from the read module and gets induced electric current to enable the transaction. When making a contact transaction, insert the card body into a card reader for the latter to read the contact communication unit and enable the transaction. During the transaction, the transaction display unit will output a transaction message as a notice.
US10163047B2 Manufacturing method for portable data carriers
A method for manufacturing a portable data carrier by means of a continuous manufacturing method, comprises the steps: providing at least one foil as a rolled good, unrolling at least one first foil, with at least a first foil being coated at least partly with an adhesive on at least one side, with at least the first foil being scored on at least one side along at least one creasing edge, with at least the first foil being folded up in precise fit along at least one creasing edge and bonded, with the foil being folded up in the direction of the side which is coated with adhesive, with the side coated with adhesive being arranged on the opposite side of the foil which has at least one scored creasing edge along which it is folded.
US10163043B2 System and method for facilitating logo-recognition training of a recognition model
In certain embodiments, training of a prediction model (e.g., recognition or other prediction model) may be facilitated via a training set generated based on one or more logos or other graphics. In some embodiments, graphics information associated with a logo or graphic (e.g., to be recognized via a recognition model) may be obtained. Training media items (e.g., images, videos, etc.) may be generated based on the graphics information, where each of the training media items includes (i) content other than the logo and (ii) a given representation of the logo integrated with the other content. The training media items may be processed via the recognition model to generate predictions (related to recognition of the logo or graphic for the training media items). The recognition model may be updated based on (i) the generated predictions and (ii) corresponding reference indications (related to recognition of the logo for the training media items).
US10163041B2 Automatic canonical digital image selection method and apparatus
Disclosed are systems and methods for automatic selection of canonical digital images from a large corpus of digital images, such as the corpus of digital images available on the web, for an entity, such as and without limitation a person, a point of interest, object, etc. The automated, unsupervised approach for selecting a diverse set of high quality, canonical digital images, is well suited for processing a large corpus of digital images. A set of canonical digital images identified for an entity can be retrieved in response to a digital image request for digital images depicting the entity.
US10163039B2 Information processing apparatus, method for processing information, and recording medium
An information processing apparatus includes a set specifying unit, a clustering unit, an image selection unit, and an image arrangement unit. The set specifying unit specifies a set of images from among a plurality of images under a predetermined condition. The clustering unit classifies, after the set of images is specified by the set specifying unit, the plurality of images into any of the same number of clusters as that of image layout regions. The image selection unit collectively selects images that constitute the set of images from among the images included in the clusters generated by the clustering unit. The image arrangement unit arranges, in the image layout regions that correspond to the clusters one-to-one, the images constituting the set of images selected from the clusters by the image selection unit.
US10163035B2 Edge detecting apparatus and edge detecting method
An edge detecting apparatus according to the present invention includes: a first determining unit configured to determine, based on an input image, at least one of a distance between local maximum pixels which are pixels of which gradation values are local maximum values and a distance between local minimum pixels which are pixels of which gradation values are local minimum values; and a detecting unit configured to detect an edge from the input image with a detection sensitivity based on the distance determined by the first determining unit.
US10163033B2 Vehicle classification and vehicle pose estimation
A method of classifying a work machine within a worksite is provided. The method may include receiving one or more captured images of the work machine from one or more image capture devices, identifying at least two classifiers within the captured images of the work machine, determining spatial relationships between the classifiers within the captured images, determining a classification and a pose of the work machine based on the spatial relationships, and displaying analytics based on the classification and the pose of the work machine.
US10163029B2 On-camera image processing based on image luminance data
A camera system processes images based on image luminance data. The camera system includes an image sensor, an image pipeline, an encoder and a memory. The image sensor converts light incident upon the image sensor into raw image data. The image pipeline converts raw image data into color-space image data and calculates luminance levels of the color-space image data. The encoder can determine one or more of quantization levels, determining GOP structure or reference frame spacing for the color-space image data based on the luminance levels. The memory stores the color-space image data and the luminance levels.
US10163027B2 Apparatus for and method of processing image based on object region
An image processing apparatus includes an image data acquisition unit configured to acquire image data, a distance information acquisition unit configured to acquire distance information corresponding to the image data, a detection unit configured to detect one or more object regions, each representing an object, from the image data based on the distance information, an extraction unit configured to extract an object region representing an object which does not overlap a specific three-dimensional region, from among detected object regions, based on the distance information, and an image processing unit configured to perform image processing for the image data based on the extracted object region.
US10163026B2 Method and apparatus for recovering a vehicle identification number from an image
Some aspects of the invention relate to a mobile apparatus including an image sensor configured to convert an optical image into an electrical signal. The optical image includes an image of a vehicle license plate. The mobile apparatus includes a license plate detector configured to process the electrical signal to recover information from the vehicle license plate image. The mobile apparatus includes an interface configured to transmit the vehicle license plate information to a remote apparatus and receive a vehicle identification number corresponding to the vehicle license plate image in response to the transmission.
US10163023B2 Apparatus and system for processing currency bills and financial documents and method for using the same
A document processing device convertible between a first configuration and a second configuration includes an input receptacle, a transport mechanism, a scanner, and a convertible output area. The input receptacle is configured to receive documents including currency bills therein. The transport mechanism is configured to transport the documents along a transport path from the input receptacle. The scanner is positioned along the transport path and is configured to scan at least a portion of each of the documents transported to generate data associated therewith. The convertible output area is configured to be selectively coupled with a first output assembly and a second output assembly.
US10163019B1 Arabic handwriting recognition system and method
A system, a non-transitory computer readable medium, and a method for Arabic handwriting recognition are provided. The method includes acquiring an input image representative of a handwritten Arabic text from a user, partitioning the input image into a plurality of regions, determining a bag of features representation for each region of the plurality of regions, modeling each region independently by multi stream discrete Hidden Markov Model (HMM), and identifying a text based on the HMM models.
US10163017B2 Systems and methods for vehicle signal light detection
Systems and methods are provided for analyzing vehicle signal lights in order to operate an autonomous vehicle. A method includes receiving an image from a camera regarding a vehicle proximate to the autonomous vehicle. Data from a lidar sensor regarding the proximate vehicle is used to determine object information for identifying a subsection within the camera image. The identified subsection corresponds to an area of the proximate vehicle containing one or more vehicle signals. One or more vehicle signal lights of the proximate vehicle is located by using the identified camera image subsection as an area of focus.
US10163014B2 Method for monitoring the visual behavior of a person
The disclosed embodiments include a method for monitoring the visual behavior of a person. In one embodiment, the method includes a person activity data providing step during which person activity data indicative of an activity of the person are provided; a person visual behavior data providing step during which person visual behavior data indicative of the visual behavior of the person related to said activity of the person are provided; reference visual behavior providing step during which a reference visual behavior data indicative of the reference visual behavior of the person based on said activity of the person are provided; and a comparing step during which the person visual behavior data and the reference visual behavior data are compared so as to deduce whether the person visual behavior is adapted with respect to said activity of the person.
US10163011B2 Estimating pose in 3D space
Methods and devices for estimating position of a device within a 3D environment are described. Embodiments of the methods include sequentially receiving multiple image segments forming an image representing a field of view (FOV) comprising a portion of the environment. The image includes multiple sparse points that are identifiable based in part on a corresponding subset of image segments of the multiple image segments. The method also includes sequentially identifying one or more sparse points of the multiple sparse points when each subset of image segments corresponding to the one or more sparse points is received and estimating a position of the device in the environment based on the identified the one or more sparse points.
US10163005B2 Document structure analysis device with image processing
A mail processing apparatus includes a data retrieving section for retrieving sample data from e-mail and/or a network NW, a signalizing section for converting the sample data form the data retrieving section into n-value, a sample storage section for storing n-value data converted by the signalizing section, a signal processing section for comparing the n-value sample data stored in the sample storage section with an inputted e-mail to judge whether or not the e-mail is spam mail based on the degree of similarity, and a spam storing section for storing the spam mail based on the judgment result.
US10163004B2 Inferring stroke information from an image
A method for character recognition. The method includes: obtaining a plurality of character segments extracted from an image; determining a first character bounding box including a first set of the plurality of character segments and a second character bounding box including a second set of the plurality of character segments; determining an ordering for the first set based on a plurality of texture properties for the first set; determining a plurality of directions of the first set based on a plurality of brush widths and a plurality of intensities for the first set; and executing character recognition for the first character bounding box by sending the first set, the plurality of directions for the first set, and the ordering for the first set to an intelligent character recognition (ICR) engine.
US10163002B2 Pedestrian detection system and method
A pedestrian detection system including a camera device and a cloud server. The cloud server includes an entrance node and a compute node unit including a plurality of compute nodes. The entrance node is configured to receive image data from the camera device, to divide the image data into a plurality of subordinate task areas, and to extract a percent of the subordinate task areas. The compute node unit is configured to receive the percent of the subordinate task areas from the entrance node, and processes simultaneously the percent of the subordinate task areas. Therefore, an efficiency of processing image of pedestrian can be improved.
US10163000B2 Method and apparatus for determining type of movement of object in video
A method and corresponding apparatus include extracting a movement trajectory feature of an object from an input video. The method and corresponding apparatus also include coding the extracted movement trajectory feature, and determining a type of a movement of the object based on the coded movement trajectory feature.
US10162994B2 Capacitive fingerprint sensing apparatus
A capacitive fingerprint sensing apparatus includes sensing electrodes, a sensing driver and a processing module. Under a first self-capacitive sensing mode, the sensing driver combines M adjacent sensing electrodes to form a first sensing electrode set to perform a first self-capacitive sensing to obtain a first self-capacitive fingerprint sensing signal; under a second self-capacitive sensing mode, the sensing driver combines N adjacent sensing electrodes to form a second sensing electrode set to perform a second self-capacitive sensing to obtain a second self-capacitive fingerprint sensing signal. M and N are positive integers larger than 1. The processing module generates a first self-capacitive fingerprint pattern and a second self-capacitive fingerprint pattern according to first self-capacitive fingerprint sensing signal and second self-capacitive fingerprint sensing signal and combines them into a third self-capacitive fingerprint pattern. The M adjacent sensing electrodes and the N adjacent sensing electrodes share at least one sensing electrode.
US10162992B2 Systems and methods to determine kinematical parameters using RFID tags
Systems and methods to determine kinematical parameters of physical objects using radio frequency identification (RFID) tags attached to the objects. In one embodiment, one of a population of RFID tags is selectively instructed by an RFID reader to backscatter the interrogating electromagnetic wave and thus allow the RFID reader to measure the position, speed, acceleration, and/or jerk of the object to which the tag is attached. The RFID reader combines the signal representing the backscattered interrogating electromagnetic wave and the signal representing the interrogating electromagnetic wave transmitted by the RFID reader to determine or monitor one or more of the kinematical parameters of the object.
US10162991B2 Method and system to identify coal characteristics at the mine
A composition is provided that includes a carbonaceous feed material to be combusted to generate an off-gas and an identifier. The identifier is associated with a predetermined composition, characteristic or property of the feed material or the off-gas.
US10162990B2 Analog heterogeneous connectivity tags and methods and systems to configure the tags
Analog heterogeneous tags and methods and systems to configure the tags are described. The present invention relates to the field of electronic devices and more particularly to electronic tag devices using analog technology. Embodiments herein disclose a tag that can work in at least one of transmit only, receive only or transmit/receive modes and can transmit/receive using a plurality of communication technologies without the complex stack functionality with minimal hardware and memory requirements, wherein the tag uses I/Q samples corresponding to each technology pre-stored on the tag. Embodiments herein also disclose methods and systems for configuring the electronic tags using a configuration device, wherein the configuration device provides the I/Q samples of each technology to the tag.
US10162988B2 Radio frequency transmission method and device thereof
A radio frequency transmission method and a device thereof are provided. The method includes: transmitting a radio frequency command by a radio frequency reader; receiving the radio frequency command by a radio frequency tag, wherein the radio frequency command includes bits; determining a logic level of each of the bits based upon a time length of each of the bits at a voltage level of a voltage waveform by the radio frequency tag; and determining whether to transmit a response signal in response to the radio frequency reader based upon the logic level of each of the bits by the radio frequency tag.
US10162986B2 Techniques of improving KVM security under KVM sharing
In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a service processor. The service processor receives a KVM console flow from a host. The service processor redirects the KVM console flow to a first destination console. The service processor redirects a video stream, without a keyboard stream and a mouse stream, of the KVM console flow to a second destination console. The service processor detects that the first destination console is disconnected from the service processor. The service processor invokes a privilege-checking event at the host.
US10162979B2 Discovering availability of digital media from multiple sources
Disclosed are various embodiments for discovering availability of digital media titles from multiple digital media service providers. A user account can indicate a relationship with one or more of the digital media service providers. For selected digital media service providers, availability of the digital media title for viewing by the user account can be determined. Relationship information for the user account can be retrieved to determine if a specified digital media title is available for viewing from a digital media service provider. The information about accessibility of the specified digital media title can be prepared and sent to a client device.
US10162975B2 Secure computing system
A computer system with multiple security levels, the system comprising a high-power processing device (130), a low-power processing device (110), and an interface unit (120) comprising functions for moving classified information between the high-power device (130) and the low-power device (110) according to formal rules for confidentiality and/or integrity. Additional security aspects, e.g. availability, may readily be accommodated. A method for implementing multiple levels of security along a number of independent security axes on the system is also disclosed.
US10162969B2 Dynamic quantification of cyber-security risks in a control system
A system and method for analyzing cyber-security risk inter-dependencies in a control system having networked devices. The system includes a central server that has a processor and a memory device in communication with the processor. The memory device stores inter-device dependencies and quantified individual risks for each of the networked devices. The memory device also stores a dynamic quantification of risk (DQR) program. The central server is programmed to implement the DQR program. Responsive to observed cyber behavior, the central server changes one or more of the quantified individual risks to generate at least one modified quantified individual risk. The inter-device dependencies for a first of the networked devices and the quantified individual risk for at least one other of the networked devices reflecting the modified quantified individual risk are used to dynamically modify the quantified individual risk for the first device to generate an inter-device modified quantified individual risk.
US10162968B1 System and method for securely updating a registered device using a development system and a release management system operated by an update provider and an update publisher
A method of updating a registered device using a development system and a release management system. The method includes: building an update package; signing the update package using a provider signing key, wherein a first digital signature is included in the update package; encrypting the signed update package using a publisher public key; requesting, by an update client on the device, an update package; preparing, by the update service, a set of signed update packages for the device; reencrypting and resigning, by the update service, the signed update package by decrypting the initial encryption using a publisher private key of the update publisher, signing the update package using a signing key of the update publisher, and finally encrypting the update package using a device public key from the device certificate, for final encryption of the update package; and decrypting the encrypted update package using a device private key.
US10162966B1 Anti-malware system with evasion code detection and rectification
A malware detection system for evaluating sample programs for malware incorporates an evasion code detector. The evasion code detector includes semantic patterns for identifying conditional statements and other features employed by evasion code. The system inserts breakpoints at conditional statements, compares expected and actual evaluated values of conditional variables of the conditional statements, and changes the execution path of the sample program based on the comparison. Changing the execution path of the sample program to an expected execution path counteracts the evasion code, allowing for the true nature of the sample program to be revealed during runtime.
US10162965B2 Portable media system with virus blocker and method of operation thereof
A portable media system for a host computer system and method of operation thereof includes: metadata programming in the portable media system, the metadata programming for constructing metadata of a file in the portable media system; and construction programming for constructing new metadata in the portable media system in response to a new file loaded into the portable media system.
US10162962B1 Systems and methods for detecting credential theft
The disclosed computer-implemented method for detecting credential theft may include (i) monitoring a secured computing system's credential store that may include at least one sensitive credential that may be used to facilitate authentication of a user that is attempting to access the secured computing system, (ii) gathering, while monitoring the credential store, primary evidence of an attempted theft of the sensitive credential from the credential store, (iii) gathering corroborating evidence of the attempted theft of the sensitive credential, and (iv) performing a security action in response to gathering the primary evidence and the corroborating evidence of the attempted theft. The primary evidence of the attempted theft of the sensitive credential may include evidence of any suspicious access of the sensitive credential from the credential store that occurs outside of a procedure of authenticating the user. Various other methods, systems, and computer-readable media are also disclosed.
US10162960B2 Method and system for interoperable identity and interoperable credentials
The present teaching relates to generating an identifier for a person. In one example, an actual name of the person is received. The identity of the person that is associated with the actual name of the person is proved at a pre-determined level of assurance (LOA) required by an identity management system. When the identity of the person has been proved, a peripheral name is solicited from the person. An identifier that includes the actual name and the peripheral name of the person is created. Whether the identifier is unique is determined. The steps of soliciting, creating, and determining are repeated until the identifier is unique. The peripheral name is associated with the person. The identifier is associated with the person.
US10162959B2 Method and apparatus for providing subscriber identity module-based data encryption and remote management of portable storage devices
Portable storage devices and methods for remotely managing such portable storage devices are disclosed. For example, a method receives a request from an endpoint device to send a command to a portable storage device. The method then authenticates the endpoint device that has sent the request. The method then transmits the command wirelessly to the portable storage device. Similarly, a portable storage device includes a processor and a computer-readable medium in communication with the processor, the computer-readable medium to store instructions. The instructions, when executed by the processor, cause the processor to perform operations that include: wirelessly receiving a command related to an access of a memory of the portable storage device, verifying an authenticity of the command and executing the command when the authenticity of the command is verified.
US10162947B2 Methods and systems for generating history data of system use and replay mode for identifying security events showing data and user bindings
Devices and methods are presented for managing data security. One example method includes receiving user identification information from a screen of a device that is connectable to a database of secure information. The method includes authenticating the user identification information, the authenticating includes capturing image data of a user associated with the user identification information. The method provides access to the database of secure information upon authenticating the user identification information. The method records data of user interactive input and viewed images displayed on the screen while the access provided. The method stores audit data for the user when accessing the database of secure information, the audit data being associated with a history of use by the user. The audit data including a plurality of events associated with the use. The method enables replay of the audit data for at least one of the plurality of events associated with the use.
US10162946B2 Data management system, data management method, and recording medium storing data management program
A data management system includes a detecting apparatus that detects an information processing apparatus and a server apparatus that controls access to data by the information processing apparatus. The detecting apparatus detects the information processing apparatus located within a predetermined area. The server apparatus includes a transmitter that transfers data to the detected information processing apparatus, the data being associated with access authority indicating whether or not the information processing apparatus is allowed to access the data, and circuitry that controls an access to the data from the detected information processing apparatus in accordance with the access authority associated with the data.
US10162944B2 Library style media DRM APIs in a hosted architecture
Systems and methods are provided for digital rights management of licensed media content. Client library components and server library components provide digital rights management services. A client-side hosting application accesses client library functionality through invocation of client application programming interfaces (APIs). A server-side hosting application accesses server library functionality through invocation of server APIs. Licenses for specific media content can be requested and issued, and appropriately licensed media content can be played. Client and server library components can function essentially absent direct communication, such as that employing a transport layer. Communications between client and server library components can be carried by the hosting applications.
US10162942B2 System and method of extending the linear dynamic range of event counting
A method and apparatus for photon, ion or particle counting described that provides seven orders of magnitude of linear dynamic range (LDR) for a single detector. By explicitly considering the log-normal probability distribution in voltage transients as a function of the number of photons, ions or particles present, the binomial distribution of observed counts for a given threshold, the mean number of photons, ions or particles can be determined well beyond the conventional limit.
US10162934B2 Data de-duplication system using genome formats conversion
A computer-implemented method for data-deduplication of genome data that is in different file formats is described. Representative data from different genome file formats is conformed to a selected file format and compared. Duplicate files are identified and duplicate files are released, with at least one file copy being retained.
US10162932B2 Method and system for multi-scale anatomical and functional modeling of coronary circulation
A method and system for multi-scale anatomical and functional modeling of coronary circulation is disclosed. A patient-specific anatomical model of coronary arteries and the heart is generated from medical image data of a patient. A multi-scale functional model of coronary circulation is generated based on the patient-specific anatomical model. Blood flow is simulated in at least one stenosis region of at least one coronary artery using the multi-scale function model of coronary circulation. Hemodynamic quantities, such as fractional flow reserve (FFR), are computed to determine a functional assessment of the stenosis, and virtual intervention simulations are performed using the multi-scale function model of coronary circulation for decision support and intervention planning.
US10162931B2 Method of forming serpentine resistor
A method of forming a serpentine resistor includes: setting a total length of a schematic resistor to make the schematic resistor to have a first resistance according to a sheet resistance; forming, by using a processor, a serpentine layer corresponding to the schematic resistor, forming, by using the processor, a dummy layer over a portion of the serpentine layer to form a modified serpentine layer, measuring, by using the processor, a modified length of the modified serpentine layer, and comparing, by using the processor, the total length and the modified length to generate a comparison result.
US10162930B2 Method of adjusting metal line pitch
A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.
US10162925B2 Cell layout of semiconductor device
A cell layout, a cell layout library and a synthesizing method are disclosed. The cell layout includes a cell block and a tapping connector. The cell block has a pin. The pin being disposed at a Nth metal layer in the cell layout. The tapping connector is disposed at a (N+1)th metal layer and a (N+2)th metal layer and stacked above the pin of the cell block. The tapping connector is electrically connected to the pin and forms an equivalent tapping point of the pin of the cell block. N is a positive integer greater than or equal to 1.
US10162923B2 State assignment method with probabilistic pairwise swap search
A method and system for optimizing state assignments for a finite state machine. The method generates a random initial state assignment for each of a plurality of states of the finite state machine, determines an initial cost associated with the random initial state assignments, identifies a code swap to explore as a function of a code swap probability. Further, the method calculates a cost for the code swap when one or more criteria is satisfied, updates the code swap probability as a function of the cost of the code swap and a best cost, performs the code swap when the cost of the swap is smaller than the best cost and/or a current cost to optimize the state assignments, and outputs optimized state assignments.
US10162922B2 Hybrid clock gating methodology for high performance cores
A computer-implemented method for generating a circuit design is provided according to certain aspects. The method includes determining a gating efficiency of first gate-enable logic, determining a gating efficiency of second gate-enable logic, and determining one of the first gate-enable logic and the second gate-enable logic having a greater one of the determined gating efficiencies. The method also includes placing the determined one of the first gate-enable logic and the second gate-enable logic in clock gating logic of the circuit design, and placing another one of the first gate-enable logic and the second gate-enable in data gating logic of the circuit design.
US10162921B2 Logic repository service
The following description is directed to a logic repository service. In one example, a method of a logic repository service can include receiving a first request to generate configuration data for configurable hardware using a specification for application logic of the configurable hardware. The method can include generating the configuration data for the configurable hardware. The configuration data can include data for implementing the application logic. The method can include receiving a second request to download the configuration data to a host server computer comprising the configurable hardware. The method can include transmitting the configuration data to the host server computer in response to the second request so that the configurable hardware is configured with the host logic and the application logic.
US10162919B1 Method and apparatus for improving a design for a system during compilation by performing network replacement
A method for designing a system on a target device includes identifying an exclusive-OR (XOR) network in a design for the system that matches an XOR network in a library. The XOR network in the design is replaced with a preferred XOR network in the library.
US10162918B1 Integrated circuit retiming with selective modeling of flip-flop secondary signals
An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform register retiming in the circuit design, whereby registers are moved across one or more portions of the combinational logic. The candidate registers to be retimed may have a different number or different types of secondary signals. In such scenarios, a selective modeling operation may be performed according to a predetermined precedence scheme to remove and model the differing secondary signals, thereby producing comparable registers with the same number and type of secondary signals. The comparable registers can then be retimed across the corresponding combinational logic. Backward or forward retiming operations may be performed in this way to achieve optimal circuit performance. During retiming adjacent combinational logic may also be combined to help minimize circuit area.
US10162917B1 Method and system for implementing selective transformation for low power verification
Disclosed is an improved approach to implement selective transformations of circuit components for performing verification. The approach looks at the observability of components to downstream properties to determine whether transformations are needed. The verification system leverages the knowledge about the behavior of the domains/components to identify only a subset of components that really need to undergo transformation.
US10162916B1 Timing verification in a programmable circuit design using variation factors
Disclosed approaches for processing a circuit design targeted to a programmable integrated circuit (IC) include inputting the circuit design to a programmed processor. Each path of the circuit design specifies a plurality of circuit elements of the programmable IC. For each circuit element specified in a path of the plurality of paths the processor looks up in a memory a mean delay associated with the circuit element, looks up a sigma factor associated with the circuit element, and looks up a delta factor associated with the circuit element. The processor determines a delay of the path as a function of the mean delay, sigma factor, and delta factor of each circuit element in the path.
US10162910B2 Method and apparatus for configuring wiring
A method and apparatus for determining settings of wires in an electrical system are provided. The method includes setting a first wire setting of a wire from among a plurality of wires to a pin setting of a pin attached to the wire if the pin has a pin setting; setting the first wire setting to a first connector setting of a first connector attached to the pin if the pin does not have a pin setting and the connector setting includes a default setting; and setting the first wire setting to at least one from among: a second pin setting of a second pin attached to the wire from among the plurality of pins; and a second connector setting of a second connector attached to the second pin if the pin does not have a pin setting and the first connector setting does not have a default setting.
US10162907B2 Ordering items within a list component of an application card based on bias parameters
A card server that provides a card object to a mobile computing device in response to receiving a card request from the mobile computing device. The mobile computing device can utilize the card object to display an application card at the mobile computing device. The application card may include one or more list components. A list component may include multiple items. The card object may specify the items in the list component. Additionally, the card object may specify a display order for the items in the list component. The display order may indicate a sequence in which the items are to be rendered. The card server can determine the display order for the items based on user preferences associated with a user of the mobile computing device, and/or a search history of the user.
US10162904B2 Capturing and managing knowledge from social networking interactions
Presenting a marking element in a social networking interaction where the marking element includes a question specifier and an answer specifier, creating a knowledge element in response to a user activating the marking element on the social networking interaction or a portion thereof, and presenting a knowledge element indicator in the social networking interaction.
US10162902B2 Cognitive recapitulation of social media content
A feedback value of a user is received, the feedback value corresponding to a content of a current post on a social media service. The content is analyzed to determine a context of the current post. A range of feedback values is computed corresponding to the context. When the feedback value is outside the range of feedback values, a set of contents is computed, the set of contents spanning a period prior to a time of the current post, and the set of contents corresponding to the context. The set of contents omits another post that is within the period and is related to the current post. A recap timeline is constructed using the set of contents and rendered relative to the current post.
US10162898B2 Method and apparatus for searching
A terminal includes a first input interface configured to acquire first search information of a first data type, and a second input interface configured to acquire second search information of a second data type, the first data type being different from the second data type. The terminal further includes a searcher configured to identify whether search information is acquired from at least one among the first input interface and the second input interface, and acquire a search result from data storage based on the search information, in response to the searcher identifying that the search information is acquired from at least one among the first input interface and the second input interface. The terminal further includes an output interface configured to provide the search result.
US10162888B2 System and method for audio identification
Various aspects of a system and a method for accessing information associated with a sample of background audio in a computing device are disclosed herein. The computing device records, at predetermined time intervals, a sample of background audio in a vicinity of the computing device. The computing device transmits the recorded sample of background audio to a server computing device. The recorded sample of background audio and a metadata associated with the recorded sample of background audio is stored at the server computing device. The computing device accesses information associated with the recorded sample of background audio from the server computing device. The information is determined by the server computing device based on the recorded sample of background audio.
US10162885B2 Automated self-service user support based on ontology analysis
A method for providing information to a user in response to a received user query. A natural language analysis generates substrings relevant to an input user query pertaining to a problem a user experiences with a product or service. An ontology analysis outputs: terms of an ontology matching the relevant generated substrings; and relationships between the terms. Elements of a perfect or complete query are captured and include information pertaining to the user's problem. The input user query is refined based on the outputted terms and relationships between the terms. A search query is performed, based on the refined user query. The results of the search are provided to the user.
US10162882B2 Automatically linking text to concepts in a knowledge base
According to an aspect, automatically linking text to concepts in a knowledge base using differential analysis includes receiving a text string and selecting, based on contents of the text string, a plurality of data sources that correspond to concepts in the knowledge base. In a further aspect, automatically linking the text to the concepts includes calculating, for each of the selected data sources, a probability that the text string is output by a language model built using the selected data source, calculating a probability that the text string is output by a generic language model, calculating link confidence scores for each concept based on a differential analysis of the probabilities, and creating a link from the text string to one of the concepts in the knowledge base. The creating is based on a link confidence score of the concept being more than a threshold value away from a prescribed threshold.
US10162881B2 Machine-assisted key discovery and join generation
Embodiments are directed towards managing data. Attributes of model fields of a plurality of model objects may be analyzed. If the analysis of the attributes discovers primary key fields in the model objects, the characteristics of the primary keys may be compared with the characteristics of other model objects. If affirmative results of the comparison indicate that one or more foreign key fields may be in the other model objects, one or more relationships that associate the primary key fields with the foreign key fields may be provided. And, a system model may be provided based on the relationships and the model objects that include the primary key fields and the model objects that include the foreign key fields.
US10162878B2 System and method for agglomerative clustering
An information handling system performs a method for finding a nearest neighbor of a point. In some embodiments, the method may be used for agglomerative clustering. The method includes projecting a space Θ of a first dimension with a first distance μ to a space P of a second, smaller dimension with a distance μ′ by a projection function p. For all pairs of points v1 and v2 in Θ, μ′ (p(v1), p(v2))≤μ(v1, v2), where p is the function that projects points in Θ to points in P. The method also includes selecting a point v in Θ and performing a search for its nearest neighbor in Θ by projecting v to P and locating a set S of nearest neighbors in P of p(v). A search is then performed in Θ of a set of S′ of points that project onto the points in S.
US10162865B2 Generating image tags
The technology described herein provides an efficient mechanism for generating image tags. Image data from a plurality of sources may be analyzed to identify relevant text items from the aggregated data. The relevant text items may be keywords describing a subject of an image, an entity of an image, a location of an image, or the like. From the aggregated image data, one or more image tags may be generated and stored as an offline dataset with an image identifier. Upon detecting a prompt such as a user issuing a search query for an image, the image identifier is used to perform a look up of the image and associated image tags to be provided.
US10162864B2 Reader application system utilizing article scoring and clustering
Aspects of the present disclosure involve a mobile or computer reader application that obtains articles or other computer files from a central database and displays the articles to a user of the device. In addition to providing the articles to the reader application, an article providing system may also determine the quality or popularity of particular articles and provide the most popular articles to users of the system. In one embodiment, the system may receive one or more anonymous interaction metrics from one or more devices connected to the system. The anonymous interaction metrics may be associated with a particular article and provide some indication of a user's engagement with the article. The system utilizes these interaction metrics or measurements to set or adjust a score or ranking associated with the particular article. The score may then be utilized by the system to rank the article in relation to other articles available through the system to provide the most popular or highest ranked articles to users of the system.
US10162863B2 Interactive display of aggregated search result information
A method, system, and processor-readable storage medium are directed towards generating a report derived from data, such as event data, stored on a plurality of distributed nodes. In one embodiment the analysis is generated using a “divide and conquer” algorithm, such that each distributed node analyzes locally stored event data while an aggregating node combines these analysis results to generate the report. In one embodiment, each distributed node also transmits a list of event data references associated with the analysis result to the aggregating node. The aggregating node may then generate a global ordered list of data references based on the list of event data references received from each distributed node. Subsequently, in response to a user selection of a range of global event data, the report may dynamically retrieve event data from one or more distributed nodes for display according to the global order.
US10162862B2 Devices, systems, and methods to synchronize simultaneous DMA parallel processing of a single data stream by multiple devices
Disclosed are methods and devices, among which is a system that includes a device that includes one or more pattern-recognition processors in a pattern-recognition cluster, for example. One of the one or more pattern-recognition processors may be initialized to perform as a direct memory access master device able to control the remaining pattern-recognition processors for synchronized processing of a data stream.
US10162860B2 Selectivity estimation for query execution planning in a database
A computer-implemented method of estimating selectivity of a query may include generating, for data stored in a database in a memory, a one-dimensional value distribution for each of a plurality of attributes of the data. A multidimensional histogram may be generated, wherein the multidimensional histogram includes the one-dimensional value distributions for the plurality of attributes of the data. The multidimensional histogram may be converted to a one-dimensional histogram by assigning each bucket of the multidimensional histogram to corresponding buckets of the one-dimensional histogram and ordering the corresponding buckets according to a space-filling curve. One or more bucket ranges of the one-dimensional histogram may be determined by mapping the query conditions on the one-dimensional histogram. The selectivity of the query may be estimated by estimating how many data values in the one or more bucket ranges will meet the query conditions.
US10162857B2 Optimized inequality join method
The optimized inequality join method is a method for joining relational tables on input inequality conditions. The optimized inequality join method is a relatively fast inequality join method using permutation arrays to store positional information for sorted attributed values. Additionally, space efficient bit arrays are used to enable optimization, such as Bloom filter indices, thus providing faster computation of the join results. The method may be used, for example, for joining various inequalities associated with a variety of measured environmental conditions for raising an alarm when certain conditions are met.
US10162855B2 Systems and methods for optimizing data analysis
Methods and systems are provided for optimizing data analysis. An example method for optimizing a computer for performing queries of a database can include determining a number of distinct members in a lowest hierarchy level of each hierarchy dimension and determining a unique hierarchy identifier for such distinct member; determining the hierarchy dimension with the fewest number of distinct members in its lowest level; ranking the hierarchy dimensions by the number of distinct members in the lowest level; generating a first hypergraph tree for the hierarchy dimension with the fewest number of distinct members in its lowest level; and generating an additional hypergraph tree for a hierarchy dimension having more than the fewest number of distinct members in its lowest level. Each hypergraph tree includes multiple nodes and each node corresponds to one of the unique hierarchy identifiers. The additional hypergraph tree includes fewer tiers than the first hypergraph tree.
US10162851B2 Methods and systems for performing cross store joins in a multi-tenant store
Methods and systems for performing cross store joins in a multi-tenant store are described. In one embodiment, such a method includes retrieving data from a multi-tenant database system having a relational data store and a non-relational data store, receiving a request specifying data to be retrieved from the multi-tenant database system, retrieving, based on the request, one or more locations of the data to be retrieved, generating a database query based on the request, in which the database query specifies a plurality of data elements to be retrieved, the plurality of data elements including one or more data elements residing within the non-relational data store and one or more other data elements residing within the relational data store, and executing the database query against the multi-tenant database system to retrieve the data.
US10162850B1 Clause discovery for validation of documents
Embodiments are directed to managing documents where clauses in a document may be identified. Evaluations of the clauses may be provided based on evaluators and machine learning (ML) models that assign each of the clauses to a category and a confidence score. Actions associated with the clauses may be monitored including updates to content of the clauses. Inconsistent evaluations associated with the clauses be identified. The ML models may be retrained based on the content of the clauses associated with the inconsistent evaluations.
US10162849B1 System, method, and computer program for automatic database validation associated with a software test
A system, method, and computer program product are provided for automatic database validation associated with a software test. In use, an indication that a user is beginning a software test that utilizes one or more databases is received. A first configuration snapshot of the one or more databases is recorded in response to receiving the indication that the user is beginning the software test, prior to the user beginning the software test. Additionally, an indication that the user has finished the software test is received. A second configuration snapshot of the one or more databases is recorded in response to receiving the indication that the user has finished the software test. The first configuration snapshot of the one or more databases is automatically compared to the second configuration snapshot of the one or more databases. Further, changes that occurred in the one or more databases resulting from the software test are automatically identified, based on the comparing of the first configuration snapshot of the one or more databases to the second configuration snapshot of the one or more databases. The changes that occurred in the one or more databases resulting from the software test are displayed utilizing at least one user interface. Still yet, the changes that occurred in the one or more databases resulting from the software test are automatically compared to past changes that occurred in the one or more databases resulting from a past software test. A difference in the changes that occurred in the one or more databases resulting from the software test and the past changes that occurred in the one or more databases resulting from the past software test is automatically identified, based on comparing the changes that occurred in the one or more databases resulting from the software test and the past changes that occurred in the one or more databases resulting from the past software test. Moreover, an indication of the difference in the changes that occurred in the one or more databases resulting from the software test and the past changes that occurred in the one or more databases resulting from the past software test is displayed utilizing the at least one user interface.
US10162845B2 Management of long-running locks and transactions on database tables
An exclusive lock is acquired on each of an outer database ownership table and an inner database ownership table to obtain ownership of a database. The exclusive locks are converted to a pair of overlapping shared locks on each of the outer database ownership table and the inner database ownership table, where release and re-acquisition of each of the pair of overlapping shared locks on the outer database ownership table and the inner database ownership table permits database maintenance operations to be performed while maintaining the ownership of the database.
US10162838B2 Location refinement
Methods and apparatus related to associating location data with one or more entities. Location data from, for example, mobile devices carried by users, may indicate a first entity as being associated with the given location data. However, one or more affirmative user inputs may indicate that a second entity is additionally, and/or alternatively associated with location data. Accordingly, location data may be associated with the second entity. In some implementations the first entity may be dissociated from the first location data. In some implementations second location data may be identified as being associated with the first entity and the second location data may be associated with the first entity.
US10162836B1 Parallel file system with striped metadata
Metadata associated with a plurality of sub-files associated with a single shared file is stored in a parallel file system. A plurality of processes generate a shared file. A compute node implements a Parallel Log Structured File System (PLFS) library to store at least one portion of the shared file and metadata for the at least one portion of the shared file on one or more of the plurality of object storage servers. The compute node is further configured to store the metadata by striping the metadata across a plurality of subdirectories of the shared file. The metadata is optionally striped across the plurality of subdirectories in a round-robin manner. The plurality of subdirectories are stored on one or more of the object storage servers. Write and read processes optionally communicate using a message passing interface. A given write process optionally writes metadata for a given portion of the shared file to an index file in a particular one of the subdirectories corresponding to the given portion.
US10162835B2 Proactive management of a plurality of storage arrays in a multi-array system
Proactive management of a plurality of storage arrays in a multi-array system, including: comparing one or more conditions of a particular storage array to conditions of other storage arrays in the multi-array system; and generating an action recommendation based on the comparison, the action recommendation specifying one or more actions for improving the conditions of the particular storage array relative to the conditions of the other storage arrays.
US10162830B2 Systems and methods for dynamic partitioning in distributed environments
Methods, systems, and computer-readable media are disclosed for dynamic partitioning in distributed computing environments. One method includes: receiving a first data set and a second data set; mapping the first data set into a first set of key-value pairs; mapping the second data set into a second set of key-value pairs; estimating, using a sketch, a frequency count for each key based on the first set of key-value pairs and the second set of key-value pairs; determining whether the estimated frequency count for each key is greater than or equal to a predetermined threshold; and partitioning the key when the estimated frequency count for the key is greater than or equal to the predetermined threshold.
US10162829B2 Adaptive parallel data processing
Adaptive parallel data processing techniques are described. In one or more embodiments, a request is received to process a data file. The data file is split into multiple portions and sent to multiple nodes, where each node is configured to process a respective portion of the data file. Responsive to an amount of processing of the data file being completed, at least one of the multiple portions of the data file is dynamically split into multiple sub-portions. The sub-portions are submitted to one or more of the multiple nodes for processing of the sub-portions.
US10162820B2 Suggested keywords
A method and system to suggest keywords to a social network member is described. A suggested keywords system, in one example embodiment, examines phrases that appear in profiles maintained by the on-line social networking system that are similar to the target profile and identifies those words and phrases that are most prominent in these profiles, utilizing a graph-based approach. These most prominent words and phrases may be presented to the target member as suggested keywords to be included in the member's professional summary.
US10162819B2 Change detection in a string repository for translated content
A technique for translating text strings includes receiving a source language text string from an application, determining that a translated text string that includes a translation in a target language of the source language text string is not available for use by the application, transmitting the source language text string to a translation service for translation, receiving the translated text string from the translation service, and causing the translated text string to be available for use by the application.
US10162814B2 Conversation processing method, conversation management system and computer device
The present invention provides a conversation processing method, a conversation management system and a computer device. The method comprises: acquiring task-related user requirement data; updating a user conversation state based on the user requirement data and a pre-configured task-related task parameter; generating at least one piece of candidate action data according to the user conversation state; and generating response text data according to the at least one piece of candidate action data. The expandability of the conversation management system is improved by customizing the conversion service related to the task in the conversation system.
US10162813B2 Dialogue evaluation via multiple hypothesis ranking
In language evaluation systems, user expressions are often evaluated by speech recognizers and language parsers, and among several possible translations, a highest-probability translation is selected and added to a dialog sequence. However, such systems may exhibit inadequacies by discarding alternative translations that may initially exhibit a lower probability, but that may have a higher probability when evaluated in the full context of the dialog, including subsequent expressions. Presented herein are techniques for communicating with a user by formulating a dialog hypothesis set identifying hypothesis probabilities for a set of dialog hypotheses, using generative and/or discriminative models, and repeatedly re-ranks the dialog hypotheses based on subsequent expressions. Additionally, knowledge sources may inform a model-based with a pre-knowledge fetch that facilitates pruning of the hypothesis search space at an early stage, thereby enhancing the accuracy of language parsing while also reducing the latency of the expression evaluation and economizing computing resources.
US10162804B2 Object resizing with content reflow
Briefly, in accordance with one or more embodiments, content of a file such as text content may be reflowed in response to a resizing of an object also included in the file.
US10162801B2 Measurement apparatus and data processing method
A measurement apparatus is used in cooperation with another equivalent measurement apparatus. Each measurement apparatus includes a change amount calculator for calculating a change amount of measured values, an average value generator for generating a first internal average value based on the change amount, and a communication unit for receiving a second internal average value that was generated by at least one other measurement apparatus. The average value generator generates a third internal average value, using a computation result based on at least the first and second internal average values.
US10162795B2 Processor for changing weight of costs needed in reconfigurable circuit
A processor controls a reconfigurable circuit capable of dynamically reconfiguring a circuit which achieves a task of a computer, the processor executes a process having determining, when reconfiguring each of circuits which achieve a plurality of tasks in the reconfigurable circuit, assigned times of time sharing of the plurality of tasks or priority processing ranks of the plurality of tasks based on costs needed in the reconfigurable circuit for respective circuits which achieve the plurality of tasks.
US10162792B2 Method and system for high precision time synchronization
In one embodiment, a dedicated time processing device inserted into a peripheral bus coupling or embedded with at least some of the rest of system components (e.g., processor, memory) of a data processing system to synchronize a system clock of the data processing system. The peripheral bus can be a Peripheral Component Interface (PCI) bus, a PCI Express (PCIe) link, a PCI extended (PCI-X) bus, or the like. The time processing device receives high precision time from a high precision time source, such as global positioning system (GPS) time source. The time processing device decodes and processes the received time and stores the time in an internal time register. The time processing device further includes an interface to allow an external component (e.g., a processor) to retrieve with low latency the time stored in the time register for the purpose of synchronizing the system clock.
US10162778B2 Universal serial bus emulation layer
A universal serial bus stack may use an emulation layer to grant a non-universal serial bus device access to universal serial bus drivers and applications. The universal serial bus stack may exchange a device communication at an emulation layer. The universal serial bus stack may translate between a universal serial bus communication and the device communication at the emulation layer, and then may exchange the universal serial bus communication at a universal serial bus client interface.
US10162774B2 Intelligent voltage regulator
A voltage regulator includes a programming interface via which programming instructions may be applied to a processor of the voltage regulator. The voltage regulator operates the processor according to the programming instructions to select one of multiple active internally-generated analog voltage levels to determine an output voltage level of the voltage regulator.
US10162769B2 Method and apparatus for transmitting and receiving data using HDMI
A method and device for transmitting and receiving data using HDMI (High-Definition Multimedia Interface) are disclosed. The method, if performed by a source device, includes: receiving a request from a sink device to transmit data processing capability information indicating whether the source device is capable of processing user-input data or not; transmitting the data processing capability information to the sink device; and receiving the user-input data from the sink device.
US10162768B2 Display system employing applications and operating system(s) loaded from detachable device using internal processor of display device or external processor of detachable device
A method, a device, and a non-transitory computer readable medium for performing external processing on a display device are presented. An application is executed on the display device. Data is sent from the application to an external processor in direct communication with the display device, if the application requires additional processing capabilities than is available on the display device. Data is received from the external processor and the processed data is displayed on the display device.
US10162763B2 Invalidation of translation look-aside buffer entries by a guest operating system
Embodiments disclose techniques for enabling a guest operating system (OS) to directly invalidate entries in a translation lookaside buffer (TLB). In one embodiment, the guest OS receives one or more invalidation credits for invalidating translation entries in a translation lookaside buffer (TLB) from a hypervisor. The guest OS decrements one invalidation credit from the one or more invalidation credits after invalidating a translation entry in the TLB. Upon determining that there are no remaining invalidation credits, the guest OS requests additional invalidation credits from the hypervisor. The hypervisor may choose to allocate the additional invalidation credits, based upon a determination of whether or not the guest OS is a rogue OS that poses a threat or risk to other guest OS in a computing system.
US10162755B2 Techniques for implementing barriers to efficiently support cumulativity in a weakly-ordered memory system
A technique for operating a cache memory of a data processing system includes creating respective pollution vectors to track which of multiple concurrent threads executed by an associated processor core are currently polluted by a store operation resident in the cache memory. Dependencies in a dependency data structure of a store queue of the cache memory are set based on the pollution vectors to reduce unnecessary ordering effects. Store operations are dispatched from the store queue in accordance with the dependencies indicated by the dependency data structure.
US10162746B2 Allocating additional requested storage space for a data set in a first managed space in a second managed space
Provided are a computer program product, system, and method for allocating additional requested storage space for a data set in a first managed space in a second managed space. A request for additional storage space is received for a requested data set stored in a first managed space in the storage. A revised amount of storage space for the requested data set comprises at least an amount of space currently allocated to the requested data set in the first managed space and the requested additional storage space. If the revised amount of storage space exceeds a value, then allocation is made of the revised amount of storage space in allocated storage space in a second managed space of the storage. The data set is stored in the allocated storage space in the second managed space.
US10162745B2 System and method of transfer of control between memory locations
Disclosed are system and method for controlling execution of a program. An example method includes determining a memory sector for storing at least a portion of execution instructions of the computer program in virtual memory address space; determining, in the virtual memory address space, one or more pages that contain code instructions and data associated with the memory sector; creating a duplicate of the virtual memory address space comprising the memory sector and the one or more pages; tagging the memory sector and the one or more pages in both the virtual memory address space and its duplicate; receiving a notification to transfer execution of the computer program between different memory sectors while executing instructions stored in either the virtual memory address space or its duplicate; and transferring execution of the computer program to a memory location other than the one in which the notification was received.
US10162742B2 System and method for end to end performance response time measurement based on graphic recognition
Software testing techniques based on image recognition are disclosed. In various embodiments, a programmatically implemented image classifier is trained to recognize a screen shot image as being associated with a transaction end condition of a transaction. A test script configured to initiate an iteration of the transaction is run. A start time of the iteration of the transaction is recorded. Screen shot images are generated during performance of the iteration of the transaction to capture a series of screen shot images of at least a portion of a user interface display associated with the iteration of the transaction. The image classifier is used to find an earliest-captured image that matches the transaction end condition. A time associated with the matched image is used as a transaction end time to compute an end-to-end time to perform the iteration of the transaction.
US10162741B2 Automatically correcting GUI automation using machine learning
A mechanism is provided in a data processing system comprising at least one processor and at least one memory, the at least one memory comprising instructions executed by the at least one processor to cause the at least one processor to implement a user interface automation tool. The user interface automation tool executes a script to perform automation functions on user interface controls in a user interface of an application. Responsive to automation of a given user interface control failing, the user interface automation tool identifies a candidate user interface control that is the same as a user interface control expected in the script using a machine learning model. The user interface automation tool corrects the script to refer to the candidate user interface control to form a corrected script. The user interface automation tool performs a user interface function on the candidate user interface control according the corrected script.
US10162737B2 Emulating a user performing spatial gestures
Examples disclosed herein provide tools for capturing spatial gestures performed by a user and scripting the gestures for testing an application under test. Scripts may be produced by capturing movement of extremities of a skeletal body corresponding to the user, wherein the movement is captured according to a change in coordinates of the extremities from an original position. The movement of the extremities may be matched to a predefined gesture found in a gesture database. A script may be generated from the matched predefined gesture with reference to the extremities captured and coordinates of the extremities from the original position, such that the user is emulated.
US10162735B2 Distributed system test automation framework
Described herein is a method for testing distributed systems. The method includes receiving, by a processing device, a software testing executable script. The method also includes appending, by a processing device, the software testing executable script to a list of executable scripts. The method also includes defining, by a processing device, a test environment including a management node and a testable component of a distributed network. The method also includes establishing, over the distributed network, a trusted connection between the management node and the testable component. The method also includes receiving, at the management node, an identifier of the software testing executable script, an identifier of a target for executing the software testing executable script, and a schedule for executing the software testing executable script. The method also includes executing, by the management node, in view of the schedule, the identified software testing executable script with respect to the target.
US10162731B2 Conditional breakpoint on call stack during debugging at runtime
A method for debugging and executable is disclosed herein. The method begins by receiving one or more breakpoints defining one or more attributes of a call stack in the executable. The processor receives the executable in a debug environment. The processor executes the executable in the debug environment. The processor halts execution of the executable upon detection of a breakpoint contained in the executable.
US10162726B2 Managing computing resources
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium are disclosed. In one aspect, a method includes filtering a first plurality of requests based on one or more criteria to generate first filtered requests, the first plurality of requests being associated with a first query plan that is associated with a first instance, identifying a first application associated with at least a portion of the first filtered requests, and determining a quantity of cores used by the first application based at least in part on the portion of the first filtered requests associated with the first application.
US10162721B2 Workload shifting in a database system using hint-based routing
A computer system is configured to provide a database system. The computer system comprises one or more processors, a primary database system implemented by the one or more processors, and a secondary database system implemented by the one or more processors. The secondary database system is configured as a hot-standby system for the primary database system. The secondary database system is capable of providing at least a minimum amount of essential functionality of the primary database system during a disruption to the primary database system. The primary database system is configured by programming instructions, executable on the computer system, to cause the one or more processors to determine from a query request from a client application directed to the primary database system that workload from a query may be shifted to the secondary database system and instruct the client application to direct the secondary database system to execute the query. Related apparatus, systems, techniques and articles are also described.
US10162720B2 Copy-on-read process in disaster recovery
Systems and program products are configured to perform a method for copy-on-read in disaster recovery (DR). The method includes: making a DR storage volume available at a DR system for read access before all data from a corresponding primary storage volume has been copied to the DR storage volume; maintaining a record of regions of the DR storage volume; and responsive to receiving a read request for data at the DR system: looking up the record of regions of the DR storage volume to determine available data for the read request; reading any available data from the DR storage volume; for any data unavailable at the DR storage volume, obtaining the unavailable data from the corresponding primary storage volume; updating the DR storage volume with obtained data; supplying obtained data to the read request; and updating the record of regions of the DR storage volume for regions of obtained data.
US10162719B2 Ordering device, data processing device, ordering method, computer program product, and multiplex system
According to an embodiment, an ordering device determines a processing order of pieces of data in each computer in a multiplex system. The device includes a preliminary elector and a confidence elector. The preliminary elector is configured to generate, when a vote having the current order number, the current round number, and a nominated state is acquired from a primary computer, a vote that includes data included in the acquired vote, the current order number, a round number following the current round number, and a winning-assured state. The confidence elector is configured to determine, when a vote having the current order number, the current round number, and the winning-assured state is acquired for identical data from each of a threshold or more of the computers, data included in the acquired vote to be data to be processed at the current order number.
US10162717B2 Synchronization of a disaster-recovery system
A method and associated systems for synchronizing a disaster-recovery system of a database. A processor identifies transactions that affect data blocks of a database and records each change in a vector form. For each block, the processor determines a more efficient way to communicate changes made to the block by a subset of the identified transactions. If fewer resources are needed to communicate an updated image of the entire changed block than would be needed to instead communicate a related set of change vectors that identify changes made to the block by the subset of transactions, then the processor communicates the updated image to the disaster-recovery system. Otherwise, the processor instead communicates the related change vectors to the disaster-recovery system. The processor repeats these determinations and communications for each block of the database that was changed by an identified transaction.
US10162716B2 Hybrid SCM-DRAM transactional storage engine for fast data recovery
A data recovery system and method are disclosed. Primary data is stored a database in byte-addressable NVRAM, where the database includes one or more persistent tables of data in a byte-addressable, RAM format, and a persistent memory allocator that maps persistent memory pointers of the persistent memory to virtual memory pointers of a virtual memory associated with the database. Secondary data is stored in volatile DRAM. A failure recovery includes recovering the persistent memory allocator, mapping the persistent memory to the virtual memory to recover primary data using their persistent memory pointers, translating the persistent memory pointers to virtual memory pointers, undoing changes to the primary data made by unfinished transactions of the query execution at the time of failure of one of the one or more queries, and reconstructing the secondary data from the primary data.
US10162713B2 Persistent application activation and timer notifications
The present invention extends to methods, systems, and computer program products for persistent application activation and timer notifications. A durable instance manager, instance execution hosts, and an instance store interoperate to transition instances between executing and persisted states. System properties are associated with an instance. System properties can define re-activation conditions, that when satisfied, indicate that an instance is to be re-activated for execution. System properties can define timers as well as indications that instances are in a persisted but ready to run state.
US10162711B1 Data locality control for deduplication
A method for data locality control in a deduplication system is provided. The method includes forming a fingerprint cache from a backup image corresponding to a first backup operation. The method includes removing one or more fingerprints from inclusion in the fingerprint cache, in response to the one or more fingerprints having a data segment locality, in a container, less than a threshold of data segment locality. The container has one or more data segments corresponding to the one or more fingerprints. The method includes applying the fingerprint cache, with the one or more fingerprints removed from inclusion therein, to a second backup operation, wherein at least one method operation is executed through a processor.
US10162707B2 Operating method for application program and electronic device supporting the same
An electronic device including a memory storing an application program that provides a guide about a user action, collects information on a performance of the user action, or collects information on a user state. A processor connected to the memory is configured to execute the application program, to detect a cause by which the application program is stopped, and to automatically reexecute the application program or to provide a user interface for receiving a user input for the reexecution of the application program on the basis of at least a portion of the detected cause.
US10162706B2 Declustered raid array having redundant domains
Embodiments of the present invention disclose a method, computer program product, and system for managing a RAID array of data storage devices. The declustered RAID array is configured to tolerate a predetermined number of failing data storage devices. The declustered RAID array of data storage devices is split into a plurality of regions, each of the plurality of regions is divided into a plurality of sets, and each of the sets of the plurality of sets utilizes a different combination of the data storage devices. The declustered RAID array provisions a plurality of LUNs from respective sets of each of the plurality of regions, and in response to a failure of one or more of the plurality of data storage devices, up to the predetermined number of failing data storage devices, the RAID array rebuilds at least one copy of each of the plurality of virtual LUNs.
US10162703B2 Methods of correcting data errors and semiconductor devices used therein
A semiconductor device correcting data errors using a hamming code is provided. The hamming code is realized by an error check matrix, and the error check matrix includes a first sub-matrix and a second sub-matrix. The first sub-matrix includes column vectors having an odd weight. The second sub-matrix includes an up matrix and a down matrix. Each of the up matrix and the down matrix includes column vectors having an odd weight.
US10162701B2 MCU with processor-independent memory fault detection
An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.
US10162698B2 System and method for automated issue remediation for information technology infrastructure
A system and method for extensible, protective, and verifiable automated issue remediation for information technology infrastructure comprises invoking an application programming interface to obtain at least one issue object corresponding to an alert generated by a monitoring system; matching the issue object to at least one diagnosis plugin of a plurality of diagnosis plugins; obtaining a prescription object from the diagnosis plugin, the prescription object comprising a remedy; and invoking the remedy after verifying the remedy is authorized to proceed.
US10162696B2 Dependency monitoring
Dependency monitoring can include monitoring a first application and a second application for un-expected behavior. Dependency monitoring can also include receiving a description of a number of dependencies between a number of applications wherein the description of the number of dependencies is created before monitoring of the first application and the second application begins. Dependency monitoring can include sending a message to an information technology (IT) personnel, wherein the message identifies a dependency from the number of dependencies between the first application and the second application based on the description of the number of dependencies.
US10162695B2 Information processing apparatus and fault diagnosis method
An information processing apparatus and a fault diagnosis method for monitoring signals relating to the start of a CPU to determine that a failure occurs, in a case where a predetermined signal is not output within a predetermined time period after the output of a predetermined signal, and determine the failure type based on the signal states at the time of the occurrence of the failure to display information corresponding to the failure type.
US10162693B1 Evaluation of mobile device state and performance metrics for diagnosis and troubleshooting of performance issues
A method of troubleshooting a mobile device receiving at a diagnostic server an initial snapshot of characteristics from a mobile device, wherein the initial snapshot includes metrics that will identify the mobile device, elements that will expose a performance issue related to the mobile device, and metrics that enable determination of a corrective action for remedying the performance issues, determining with a diagnostic processor the performance issue based on the initial snapshot, receiving at an evaluating server an after-care snapshot of the characteristics from the mobile device after a corrective action has been performed on the mobile device, and determining with an evaluating processor whether the corrective action remedied the performance issue based on the after-care snapshot.
US10162692B2 Rainbow event drop detection system
In one embodiment, data received from one or more streaming data sources may be monitored by one or more devices. A rate of change in flow of the data received from the one or more streaming data sources may be ascertained. It may be determined whether the rate of change in flow of the data received from the one or more streaming data sources exceeds a threshold rate. Transmission of an alert may be initiated according to a result of determining whether the rate of change in the flow of the data received from the one or more streaming data sources exceeds the threshold rate.
US10162685B2 System and method for intelligent task management and routing
Systems and methods are shown for routing task objects to multiple agents that involve analyzing content of each task object in an input buffer to determine a classification relevant to the content of the task object that is added to task object metadata, which is placed in a second buffer. Objects in the second buffer are analyzed and the classification in the object metadata used to search workforce management data representing agent characteristics to identify agents who match the classification. A routing strategy is applied to the object to select an agent and the object is routed to the agent's workbin. Another aspect involves organizing workbin tasks objects by priority, according to recent system conditions excluding objects that cannot presently be processed based on a workflow strategy or status data, and presenting remaining objects based on order of priority, or re-arranging objects between workbins based on recent status info.
US10162684B2 CPU resource management in computer cluster
Embodiments of the present invention relate to CPU resource management in a computer cluster. A master node selects a CPU core of at least one compute node for an application from a computer cluster, and allocates a portion of resource of the CPU core to the application. The master node re-allocates a new portion of the resource of the CPU core to the application, in response to a trigger event for re-allocation.
US10162682B2 Automatically scaling up physical resources in a computing infrastructure
A processing device determines that utilization of a resource that is executing a workload meets a utilization threshold. The resource is part of multiple resources in a cluster. The processing device determines that no other resource of the cluster has available capacity for a transfer of a workload or a portion of a workload from the resource to the other resource, and determines a change to implement in a physical configuration of the cluster in view of no other resource having available capacity. The processing device sends a message over a network to implement the change, without user interaction, to the physical configuration of the cluster. The change includes adding a new physical resources to the cluster.
US10162679B2 Method and system for assigning a computational block of a software program to cores of a multi-processor system
A method for assigning a computational block of a software program to cores of a multi-processor system includes: evaluating a first number of available cores of a first type of the multi-processor system and a second number of available cores of a second type of the multi-processor system; determining a first number of loops of the computational block for binding with the cores of the first type and a second number of loops of the computational block for binding with the cores of the second type; binding the first number of loops with the cores of the first type and binding the second number of loops with the cores of the second type; and executing the loops of the computational block according to the binding.
US10162675B2 Parallel processing system
A first process scheduler and a second process scheduler are configured to be able to communicate with each other. The first process scheduler is configured to, in accordance with the processing status of a second process processing part detected by the second process scheduler, control the operation of a first process processing part executing a process associated with a process shown by the processing status. The second process scheduler is configured to, in accordance with the processing status of the first process processing part detected by the first process scheduler, control the operation of the second process processing part executing a process associated with a process shown by the processing status.
US10162673B2 Controller preventing communication collisions between parallel control programs
A controller enables execution of control programs in parallel using a multi-core processor in shorter cycles without causing communication collisions. The controller executes control programs in multiple cycles. In accordance with the priorities assigned to a control program 1 and a control program 2, the controller controls the timing to execute communication associated with the control program 2 without colliding with communication with external devices associated with the control program 1.
US10162672B2 Generating data streams from pre-existing data sets
Systems and methods are described for transforming a data set within a data source into a series of task calls to an on-demand code execution environment or other distributed code execution environment. Such environments utilize pre-initialized virtual machine instances to enable execution of user-specified code in a rapid manner, without delays typically caused by initialization of the virtual machine instances, and are often used to process data in near-real time, as it is created. However, limitations in computing resources may inhibit a user from utilizing an on-demand code execution environment to simultaneously process a large, existing data set. The present application provides a task generation system that can iteratively retrieve data items from an existing data set and generate corresponding task calls to the on-demand computing environment, while ensuring that at least one task call for each data item within the existing data set is made.
US10162669B2 Dynamic relocation of applications in a cloud application service model
Software that performs the following steps is provided: (i) running an application on a first virtual machine on a first physical server, with the application including a first plurality of independently migratable elements, including a first independently migratable element that utilizes a first resource on the first virtual machine and a second independently migratable element that utilizes a second resource on the first virtual machine; and (ii) on condition that a first migration condition exists, migrating the first independently migratable element to a second virtual machine on a second physical server, such that the first independently migratable element is able to utilize a resource that is similar to the first resource on the second virtual machine on the second physical server while the second independently migratable element remains able to utilize the second resource on the first virtual machine on the first physical server.
US10162665B1 Hypervisor assisted control of CPU access to externally managed physical memory
A memory management module receives a request to access a page in a memory, sends the request to a memory controller controlling the memory if the page is available in the memory, and if the page is unavailable, (i) does not send the request to the memory controller, and (ii) generates a first exception. A hypervisor intercepts the first exception and sends a second exception to an operating system. The operating system includes a handler to, in response to the second exception, selectively request the memory controller to obtain the page from a storage device into the memory, and to suspend execution of a first thread issuing the request on a processor until the page becomes available in the memory; and a kernel to schedule execution of a second thread on the processor until the page becomes available, or to idle the processor until the page becomes available.
US10162664B2 Composite virtual machine template for virtualized computing environment
Composite virtual machine templates may be used in the deployment of virtual machines into virtualized computing environments. A composite virtual machine template may define a plurality of deployment attributes for use in a virtual machine deployment, and at least some of these deployment attributes may be determined through references to other virtual machine templates and included in the composite virtual machine template.
US10162661B2 Interdependent virtual machine management
Exemplary methods, apparatuses, and systems determine a list of virtual machines to be subject to a corrective action. When one or more of the listed virtual machines have dependencies upon other virtual machines, network connections, or storage devices, the determination of the list includes determining that the dependencies of the one or more virtual machines have been met. An attempt to restart or take another corrective action for the first virtual machine within the list is made. A second virtual machine that is currently deployed and running or powered off or paused in response to the corrective action for the first virtual machine is determined to be dependent upon the first virtual machine. In response to the second virtual machine's dependencies having been met by the attempt to restart or take corrective action for the first virtual machine, the second virtual machine is added to the list of virtual machines.
US10162660B2 Application-level processor parameter management
Embodiments relate to application-level processor parameter management. An aspect includes granting, by a hypervisor of a computer system, access to an operating parameter of a processor of the computer system to an application that is running on the computer system. Another aspect includes, based on the granting of access to the operating parameter, receiving, by an optimization function in the computer system from the application, a request to adjust the operating parameter. Another aspect includes determining an adjusted value for the operating parameter during execution of the application. Another aspect includes setting the operating parameter to the adjusted value in a parameter register of the processor. Another aspect includes executing the application according to the parameter register by the processor.
US10162659B2 Embedded processor with virtualized security controls using guest identifications, a common kernel address space and operational permissions
A method includes assigning unique guest identifications to different guests, specifying an address region and permissions for the different guests and controlling a guest jump from one physical memory segment to a second physical memory segment through operational permissions defined in a root memory management unit that supports guest isolation and protection.
US10162655B2 Hypervisor context switching using TLB tags in processors having more than two hierarchical privilege levels
In a virtualized computer system operable in more than two hierarchical privilege levels, components of a hypervisor, which include a virtual machine kernel and virtual machine monitors (VMMs), are assigned to different privilege levels. The virtual machine kernel operates at a low privilege level to be able to exploit certain features provided by the low privilege level, and the VMMs operate at a high privilege level to support execution of virtual machines. Upon determining that a context switch from the virtual machine kernel to a VMM is to be performed, the computer system exits the low privilege level, and enters the high privilege level to execute a trampoline that supports context switches to VMMs, such as state changes, and then the VMM. The trampoline is deactivated after execution control is switched to the VMM.
US10162654B2 Network policy implementation with multiple interfaces
The transmission of data on computer networks according to one or more policies is disclosed. A policy may specify, among other things, various parameters which are to be followed when transmitting initiating network traffic. Multiple network interfaces may be installed on a server to enable transmission of data from the single server according a number of discrete configuration settings implicated by the various policies. The multiple network interfaces may correspond to separate physical components, with each component configured independently to implement a feature of a policy. The multiple network interfaces may also correspond to a single physical component that exposes multiple network interfaces, both to the network and to the server on which it is installed.
US10162644B2 Shielding real-time workloads from OS jitter due to expedited grace periods
A technique for shielding real-time workloads from operating system (OS) jitter due to expedited read-copy update (RCU) grace periods. In accordance with the disclosed technique, a kernel parameter is set to indicate that expedited RCU grace periods are to be suppressed. The kernel parameter is checked to see if it is set. A normal non-expedited RCU grace period is invoked in response to attempted invocation of an expedited RCU grace period if the check reveals that the kernel parameter is set.
US10162639B2 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
US10162637B2 Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
Instructions and logic provide SIMD permute controls with leading zero count functionality. Some embodiments include processors with a register with a plurality of data fields, each of the data fields to store a second plurality of bits. A destination register has corresponding data fields, each of these data fields to store a count of the number of most significant contiguous bits set to zero for corresponding data fields. Responsive to decoding a vector leading zero count instruction, execution units count the number of most significant contiguous bits set to zero for each of data fields in the register, and store the counts in corresponding data fields of the first destination register. Vector leading zero count instructions can be used to generate permute controls and completion masks to be used along with the set of permute controls, to resolve dependencies in gather-modify-scatter SIMD operations.
US10162636B2 Control apparatus, integrated circuit and management method for stack
A control apparatus, an integrated circuit, and a management method for a stack are provided. The management method for the stack includes: obtaining an instruction of running a task with a first function; changing a pointer of the stack in an internal memory from pointing to an internal memory to an external memory before executing the first function, wherein the stack in the internal memory is used by the task; executing the first function, wherein first temporary information that is needed to be stored during a period of executing the first function is stored into the external memory pointed to by the pointer of stack; and adjusting the pointer of the stack to point to the internal memory after finishing executing the first function. According to the above-mentioned management method for the stack, the cost is reduced, and low power consumption can be achieved.
US10162633B2 Shift instruction
An apparatus has processing circuitry comprising multiplier circuitry for performing multiplication on a pair of input operands. In response to a shift instruction specifying at least one shift amount and a source operand comprising at least one data element, the source operand and a shift operand determined in dependence on the shift amount are provided as input operands to the multiplier circuitry and the multiplier circuitry is controlled to perform at least one multiplication which is equivalent to shifting a corresponding data element of the source operand by a number of bits specified by a corresponding shift amount to generate a shift result value.
US10162629B1 Compiler independent identification of application components
Disclosed are various embodiments for compiler independent identification of application components. A procedure in a compiled binary application is identified. Then, a first compiler independent hash value for the procedure is generated, the compiler independent hash value representing a set of memory dereferences occurring in a heap, and the set of memory dereferences relying in part on a set of inputs for the procedure. Next, it is determined whether the first compiler independent hash value matches a second compiler independent hash value associated with a known procedure in a known source code file.
US10162628B2 Transactional distributed data analysis and transformation
A data analysis and transformation engine provides a service that automatically analyzes, formats, and/or reviews changes made to collection of artifacts stored in one or more source control systems in accordance with a user's instructions in a coordinated manner. A user subscribes to the data analysis and transformation engine with instructions on the user's preference for formatting, reviewing, and analyzing an artifact after the artifact was modified and checked into a source control system.
US10162626B2 Ordered cache tiering for program build files
Technologies that allow for a significant reduction in the time required to incrementally build large computer programs, and increase in the scale of build systems that perform builds. The time reduction is caused by reducing the time required for processing systems in a distributed build system to acquire files needed for the respective processing system to perform their respective part of the build. The scale increase comes from relying on local processing systems instead of centralized processing systems. This is done by establishing a tier of cache locations on which appropriate files for a build may be found by the appropriate processing system. A system may be established that allows for the processor systems to validate that the files have not been tampered with by using signatures, and were appropriately identified.
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