Document Document Title
US10110568B2 Keyless access to laptop
A method including transmitting, by a mobile device, a first encrypted gadget token over a wireless link to an Information Handling System (IHS). The method further including transmitting, by the IHS, an encrypted system token based on the first decrypted gadget token over the wireless link to the mobile device, transmitting, by the mobile device, a second encrypted gadget token based on the decrypted system token over the wireless link to the IHS, authenticating, by the IHS, the second decrypted gadget token, and unlocking the IHS based on the second authenticated gadget token.
US10110565B2 Network security processing
A method, and associated system, for security processing of a request for a resource in a network security system. The request for the resource and a duplicate of request for the resource are forwarded to a first proxy server and a second proxy server, respectively. A first output including the received request, and a second output including the duplicate of the received request, are received from first proxy server and the second proxy server, respectively. A determination is made of whether the first output and the second output differ; if not the received request or the duplicate of the received request is transmitted to a web server for satisfying the request; if so a first alarm is generated and transmission to the web server of the received request and the duplicate of the received request is blocked.
US10110564B2 Detecting application state using a DNS-controlled proxy
Detecting an application state using a DNS-controlled proxy is described. In one or more embodiments, a proxy on a computer establishes a first secure connection with a browser and the proxy establishes a second secure connection with a web server. The proxy forwards a request for a test asset from the browser to the web server. In response to the request, the web server responds with the test asset, which is sent via the proxy to the browser. The browser attempts to load the test asset to determine if a desktop application is installed and running on the computer.
US10110560B2 Management for communication ports
When an application is installed, a list of one or more communication ports used by the application is received. In addition, a list of communication ports that are currently open in a firewall is received. The two lists are compared to determine if there is a conflict. In response to finding a conflict, a control port option is taken. For example, a control port option may be: 1) where a port management window is displayed that allows the administrator to change the list of one or more communication ports and/or the list of communication ports currently in use, 2) where an auto configuration option window is displayed, or 3) where open communication ports are automatically selected to resolve the conflict. If a conflict is not found, a message is sent to a firewall to automatically open the one or more communication ports for the application.
US10110558B2 Processing of finite automata based on memory hierarchy
At least one processor may be operatively coupled to a plurality of memories and a node cache and configured to walk nodes of a per-pattern non-deterministic finite automaton (NFA). Nodes of the per-pattern NFA may be stored amongst one or more of the plurality of memories based on a node distribution determined as a function of hierarchical levels mapped to the plurality of memories and per-pattern NFA storage allocation settings configured for the hierarchical levels, optimizing run time performance of the walk.
US10110557B2 FTP application layer packet filtering method, device and computer storage medium
Disclosed is a method for Application Specific Packet Filter (ASPF) of a File Transfer Protocol (FTP), including the following steps: when a Transmission Control Protocol (TCP) connection of an FTP control channel is established, a first TCP Synchronous (TCP SYN) packet sent by a client is obtained and forwarded to an FTP server; it is detected whether a response packet from the FTP server is a TCP Synchronize-Acknowledgment (SYN+ACK) packet, and if not, the response packet is discarded; it is detected whether a response packet from the client is an ACK TCP packet, and if not, the response packet is discarded; and a data flow table is created to record and update an FTP state. A device for ASPF of a FTP is also provided. The method and device can avoid and stop the attacks from the FTP application layer, and ensure safe and reliable transmission of an FTP service.
US10110553B2 Adaptive prefix delegation
Adaptive prefix delegation that facilitates delegating prefixes from one device to another. The prefix delegation may be adaptively implemented to enable delegation router to make decision regarding characteristics of prefixes to be delegated. The adaptive prefix delegation may be automatically or dynamically preformed according to particularly operation capabilities of each delegating device.
US10110544B2 Method and system for classifying a question
A method, implemented on at least one computing device, each of which has at least one processor, storage, and a communication platform connected to a network for classifying a question is disclosed. A question is received from a person. A question pattern is determined. A model selected based on the question is retrieved. Further, a decision is made as to whether the question is a personal question based on the question pattern and the selected model.
US10110542B2 Wearable computing—augmented reality and presentation of social information
A method of presenting on a device of a user of a social-networking system information about other users of the social-networking system is disclosed. A location of the user of a social-networking system is determined. Locations of the additional users of the social-networking system are determined. A subset of the additional users of the social networking system is selected based on the location of the user and the locations of the additional users and based on information stored in a profile of the user in comparison to information stored in profiles of the additional users. Instructions are transmitted to a device of a user, the instructions instructing the device to display in a condensed visual form the subset of the information stored in the profiles of the additional users.
US10110537B2 Method and device for notifying information of social client
The present disclosure provides a method and a device for notifying information of a social client. The method comprises: updating information of the social client; extracting information of a client contained in an associated client list of the social client identified as a specified category, and notifying the updated information of the social client to the specified category of client; and filtering out the information of the client contained in the associated client list of the social client identified as the specified category, and notifying the updated information of the social client to the rest of clients contained in the associated client list. The present disclosure ensures some specified categories of associated clients of a social client can be notified of information, thereby enabling effective synchronization of information of the social client and improving the information processing efficiency of the social client.
US10110536B2 System for managing event notifications to client devices
An online content management service can manage distribution of event notifications to client devices based on notification keys. Client devices can register with the content management service to receive event notifications associated with one or more specific notification keys of interest. The content management service can receive information about events, determine a notification key for each event, and selectively send notifications to clients that are registered for that notification key. The content management service can store event notifications for client devices that are generated during a period when the client device is not in communication with the content management service and can send the missed event notifications to the client device when the client device reestablishes communication with the content management service.
US10110529B2 Smart email attachment saver
In an approach to save-to location selection, a computing device accesses a metadata file comprising a data table. The computing device successively checks the data table for entries that match a series of features of a file to be saved. If the computing device finds one or more matches, the computing device determines an associated save-to location. If the computing device does not find a match and has exhausted all of the series of features, the computing devices determines a default save-to location. The computing device receives a user selection based on or overriding the determination. The computing device updates the data table with information concerning each of the features of the file and information concerning the user selection.
US10110528B2 System and method for enabling an external-system view of email attachments
A method and email application enable email attachments to be viewed through a system external to the email application itself in accordance with select categories. The email application creates categories and categorizes the email attachments according to such categories. The email application then maps the categories into a format understandable by the external system for category information and provides the mapped categories to the external system in such format. In response to receiving a request from the external system for the contents of one of the mapped categories and in response to such category having no further subcategories, the email application identifies the email attachments under such category and maps the identified email attachments to file names. The file names are then provided to the external system as the contents of such category. If the external system requests the contents of a category that has further subcategories, the email application maps the subcategories into a format understandable to the external system and provides such subcategories to the external system as the contents of such category.The present invention can be used to provide a file-system view of email attachments. In such case, the email application appears as a file system to the operating system of an email user's computer. The created categories are provided to the operating system as the “folders” in the file system. The email attachments are provided as files within such folders.
US10110527B1 Systems and methods for secure data exchange in a distributed collaborative application
A collaborative communication system that includes a plurality of endpoints and interconnecting nodes configured to communicate via messages over interconnecting channels. Each of the plurality of endpoints and/or interconnecting nodes can determine whether to apply protection to the messages on a per message basis and/or base on the interconnecting channel being used. Thus, a balance between adequate protection and use of system resources and bandwidth can be maintained.
US10110525B2 Method and device for interaction between smart watch and WECHAT platform, and smart watch
The present disclosure discloses a method and a device for interaction between a smart watch and a WECHAT platform, and a smart watch. The method comprises: providing a customized browser that is adapted to the smart watch on the smart watch end, wherein the customized browser is able to access a webpage edition WECHAT platform; wirelessly connecting and pairing the smart watch end with a mobile telephone end, and after the pairing is successfully completed, making the smart watch end wirelessly connect to a network side via the mobile telephone end; after WECHAT function on the smart watch starts up, accessing the webpage edition WECHAT platform by the customized browser, and logging in on the webpage edition WECHAT platform according to user information that is bound on the mobile telephone end; and upon receiving a WECHAT message reminder that is pushed by the webpage edition WECHAT platform to the smart watch end, generating a WECHAT replying message according to an instruction that is input by the user, and transmitting the WECHAT replying message to the network end via the wireless connection, to perform WECHAT replying, thereby realizing replying a WECHAT message on the smart watch platform.
US10110523B2 System and method for topic based segregation in instant messaging
In order to be able to discuss multiple topics separately in an electronic chat session, a request to discuss one or more topics in the electronic chat session is detected. In response to detecting the request to discuss the one or more topics in the electronic chat session, a sub-chat session for each of the one or more topics is created within the electronic chat session. Information associated with the sub-chat sessions is sent to the participants of the electronic chat session. This allows each participant to chat separately on each topic via the separate sub-chat sessions; thus creating an individual transcript for each topic.
US10110522B1 Setting sharing options for files using a messaging client
Functionality is disclosed herein for setting sharing options for files using a messaging client. A message interface is displayed that allows a user to compose an electronic message. While the message is being composed, the user may specify sharing options for a file, or files, associated with the message. The sharing options may specify access settings used to identify the users that are allowed to access the file through a sharing service, feedback settings that are used to indicate when feedback is expected, and expiration settings that are used to indicate when sharing of the file expires. The sharing options are communicated from the messaging client to the sharing service. The sharing service may utilize the sharing options to control the manner in which the file, or files, is shared.
US10110521B2 Communication support system
A communication support system among a plurality of users within a hierarchical structure is disclosed herein. An electronic note may be transcribed using a computing device within an active session that has other authorized users. The communication support system may determine other devices authorized to receive electronic notes, at the end of each session all information is permanently deleted. Notes may be sent based a chain of command of those users in a session. Notes will be relayed based on an authorization level of each client computing devices and will be relayed when certain criteria are satisfied. The electronic note may be transmitted to a second client computing device based on the authorization level and the criteria being satisfied. The second computing device may then approve of and forward the electronic note to a relatively higher client computing device within the hierarchy, such as a third client computing device.
US10110516B2 Computer-readable recording medium, switch controlling apparatus, and method of controlling a switch
A non-transitory computer readable recording medium having stored therein a switch controlling program causing a computer to execute a process includes acquiring port information on a switch that comprises a plurality of first and second ports, where the port information including connection destinations of the second ports and being acquired for each of the second ports before swapping the switch for another switch; instructing to close the first ports of the another switch after the switch is swapped; acquiring the port information on the another switch for each of the second ports after the swapping; determining whether there exists the second port whose connection destination is unchanged before and after the swapping; and instructing to open the first port of the another switch, where data being transferred between the opened first port and the second port whose connection destination is unchanged before and after the swapping.
US10110515B2 Packet scheduling using hierarchical scheduling process
System and method of data routing according to a hierarchical scheduling process. Incoming data traffic is allocated to various queues of a buffer. A scheduling tree has a top level for queues, a bottom level for egress ports, and a plurality of intermediate levels corresponding to different granularities with respect to service categories. Each queue is assigned to a particular node in each intermediate level of the scheduling tree. The scheduling tree traverses through multiple scheduling stages from the bottom to the top level to select a winner node in each level based on a variety of fairness and differentiating variables. As a result, a queue associated with the winner nodes in various levels is selected and data from the queue is read out and sent to the selected egress port for transmission.
US10110513B2 Multi-chassis switch having a modular center stage chassis
A system may comprise a first group of switches, each switch including a first group of inputs and outputs, and a first group of controllers, each controller being independent from one another and corresponding to a switch of the first group of switches, to selectively control the switch to connect the switch's inputs with outputs. The first group of switches and controllers may be installed in a chassis. The system may comprise a second group of switches, each switch including a second group of inputs and outputs, and a second group of controllers, each controller corresponding to a switch of the second group of switches, to selectively control the switch to connect the switch's inputs with outputs. The second group of controllers may control and connect, via a group of control links, to the first group of controllers.
US10110511B2 Resource prioritization and communication-channel establishment
A resource prioritization system and method for processing request communications by prioritizing resources based on obtainment parameters and establishing communication channels. The resource prioritization system and method may receive a request from a user device. The request can include content related to a request specification and can be associated with a request location. The resource prioritization system and method can process the request to identify one or more resources having one or more characteristics corresponding to the request content and associated with resource locations near the user location. A communication channel can then be established between the user device and a device associated with an identified resource, such that the user can submit queries to the resource and receive query responses.
US10110505B2 Methods and apparatus to manage and execute actions in computing environments using a graphical user interface
Methods and apparatus to manage and execute action in computing environments are disclosed. An example system includes a virtual machine resource platform to host a virtual compute node; and a resource manager to: install an interface to receive an adapter configured to initiate an action that operates on the virtual compute node, install the adapter by processing an adapter definition to identify an action specified by the adapter, trigger an alert based on collected data associated with the virtual compute node, in response to the alert, trigger the action to be executed using a parameter extracted from the collected data, and execute the action to operate on the compute node.
US10110500B2 Systems and methods for management of cloud exchanges
A method involving receiving application monitoring data for a first application executing in a first cloud provider and a second application executing in a second cloud provider, wherein both the first and second cloud providers communication via a cloud exchange, performing traffic latency analytics using the received application monitoring data, determining, based on the traffic latency analytics, that a peering agreement between the first cloud provider and the cloud exchange should be moved to a Central office Re-architected as a Data Center (CORD), requesting a Path Computation Engine to find the CORD that meets a required set of criteria, establishing a private link between the CORD and the cloud exchange, moving the at least one peering agreement to be between the first cloud provider and the CORD, and forwarding at least a portion of the traffic originating from the first application in the first cloud provider directly via the CORD.
US10110499B2 QoS in a system with end-to-end flow control and QoS aware buffer allocation
The present disclosure is directed to Quality of Service (QoS) and handshake protocols to facilitate endpoint bandwidth allocation among one or more agents in a Network on Chip (NoC) for an endpoint agent. The QoS policy and handshake protocols may involve the use of credits for buffer allocation which are sent to agents in the NoC to compel the acceptance of data and the allocation of an appropriate buffer. Messages sent to the agent may also have a priority associated with the message, wherein higher priority messages have automatic bandwidth allocation and lower priority messages are processed using a handshake protocol.
US10110495B1 Multi-access edge computing (MEC) service provision based on local cost measurements
Embodiments herein may include systems, apparatuses, methods, and computer-readable media, for a multi-access edge computing (MEC) system. An apparatus for MEC may include a communication interface, a local cost measurements module, and a service allocation module. The communication interface may receive, from a UE, a request for a service to be provided to the UE. The local cost measurements module may collect a set of local cost measurements for the service. The service allocation module may determine to allocate the service to a MEC host based on an allocation policy related to a cost for the MEC host to provide the service or a cost for a service provider to provide the service in view of the one or more local cost measurements. Other embodiments may be described and/or claimed.
US10110487B1 Signaling priority information for encapsulated packets
In one example, an edge routing device of a service provider network includes one or more network interfaces configured to send and receive packets and a processing unit configured to retrieve, from a packet received via the one or more network interfaces, priority data from an Internet protocol (IP) header of the packet, form a first tag including a first set of data in a first priority field of the first tag, wherein the first set of data represents a first portion of the priority data, form a second tag including a second set of data in a second priority field of the second tag, wherein the second set of data represents a second portion of the priority data, encapsulate the packet with the first tag and the second tag, and forward, via the one or more network interfaces, the encapsulated packet.
US10110483B2 Method and apparatus for creation of global network overlay with global parameters defining an end-to-end network
In one embodiment, a method includes receiving at a virtual controller operating at a network device, global parameters for a plurality of virtual machines located in a first network site and in communication with a second network site through a switch, converting at the virtual controller, the global parameters into global overlay network parameters, and transmitting the global overlay network parameters to the switch for use in automatically creating a global network overlay. The global overlay network parameters define an end-to-end network extending from the virtual machines in the first network site to a plurality of virtual machines in the second network site. An apparatus and logic are also disclosed herein.
US10110482B2 Technique for network service availability
A technique for triggering an association between a Media Access Control (MAC) address and a switch port is provided. The association allows forwarding data frames including the MAC address as destination MAC address via the associated switch port. Related methods include receiving a data frame originating from a node. The data frame includes a MAC address of the originating note as source MAC address. The data frame is stored including the MAC address. The data frame is successfully sent towards a first switch port. In response to a failure of a first link towards the first switch port, the stored data frame is resent towards a seconds switch port that is different from the first switch port for triggering the association between the second switch port and the MAC address of the originating node.
US10110471B1 Asymmetric dynamic routing
A method for dynamic routing is provided. Status information of a multichannel video and data distribution service (MVDDS) channel from customer premises equipment (CPE) is received. The status information is evaluated to determine if data destined for the CPE over the MVDDS channel should be routed over a secondary channel. Data destined for the CPE is route over the secondary channel when the data is determined to be routed over the secondary channel.
US10110470B2 Preventing data traffic loops associated with designated forwarder selection
A device may receive a route identifier that includes a range identifier or a configuration identifier. The range identifier may identify a range of broadcast domain identifiers associated with a first device. The configuration identifier may identify an Ethernet segment identifier (ESI) configuration of the first device. The device may identify the range identifier or the configuration identifier included in the route identifier. The device may select a designated forwarder from among multiple devices based on the range of broadcast domain identifiers or based on identifying the configuration identifier. The designated forwarder may be the same designated forwarder selected by at least one other device.
US10110469B2 Detecting and preventing network loops
Systems, methods, and non-transitory computer-readable storage media for detecting network loops. In some embodiments, a system can identify a port that is in a blocking state. The blocking state can be for dropping one or more types of packets and preventing the port from forwarding the one or more types of packets. The system can determine a number of packets transmitted through the port by a hardware layer on the system and a number of control packets transmitted through the port by a software layer on the system. The system can determine whether the number of packets is greater than the number of control packets. When the number of packets is greater than the number of control packets, the system can determine that the blocking state has failed to prevent the port from forwarding the one or more types of packets.
US10110466B2 Optical communication system with distributed wet plant manager
A wet plant manager (WPM) platform is disclosed in accordance with an embodiment of the present disclosure, and supports management of Smart Undersea Network Elements (SUNEs) by providing an abstracted view of the same to higher level network management functions within an optical communication system. The optical communication system can include an optical cable system extending between two or more cable landing stations (CLSs). Each CLS may execute a respective instance of a WPM platform service, with the collective WPM platform performing self-coordination such that only one instance of a WPM service is “active” at any given time. The active WPM service supports a plurality of network topologies architected around SUNEs and “bridges” them such that requests to communicate with a particular SUNE get handled in a transparent manner without the requesters specific knowledge of which command/response (CR) telemetry path was utilized to satisfy the request.
US10110465B2 Distributed HSRP gateway in VxLAN flood and learn environment with faster convergence
A method of supporting N active, distributed HSRP gateways in a virtual Extensible local area network. The method includes: joining by HSRP active, HSRP standby, HSRP listen gateways a special virtual Extensible LAN tunnel endpoint address; advertising by HSRP active, HSRP standby, HSRP listen gateways its address; assigning priority to HSRP active, HSRP standby, HSRP listen gateways; determining the liveliness of the HSRP active gateway; and the HSRP active gateway sourcing Hello with HSRP VMAC in the inner layer 2 header, and the special virtual Extensible LAN tunnel endpoint address in the outer Layer 3 address; replying by the HSRP active gateway to a broadcast ARP to an HSRP Virtual IP address; forwarding packets destined to Virtual MAC by any of HSRP active, HSRP standby, HSRP listen gateways and replying by HSRP active, HSRP standby, HSRP listen gateways to a unicast ARP to an HSRP Virtual IP address.
US10110464B2 Method of monitoring and warning for configuring routing in a cluster comprising static communication links and computer program implementing that method
The method relates to the monitoring of at least one routing parameter for a cluster including nodes and switches, static communication links connecting nodes and switches. Each switch includes several output ports. After having selected at least one switch, a number of routes per port is calculated for each port of each switch selected, routes being defined during a routing step for each connecting one node to another. A mean number of routes per port is then calculated for the at least one selected switch. Each number of routes per port calculated is then compared with the mean number of routes per port calculated and, in response to this comparison, a potential imbalance of routing of the cluster is notified.
US10110455B2 Service latency monitoring using two way active measurement protocol
A device may establish a communication session, with a client device, for monitoring a latency of a service. The device may receive, from the client device, a request for a monitored service list. The monitored service list may identify one or more services for which service latency monitoring is supported. The device may provide, to the client device, the monitored service list. The device may receive, from the client device, a service latency monitoring session request that may identify the service to be monitored. The device may establish, with the client device, the service latency monitoring session based on the service latency monitoring session request. The device may cause the service to be performed. The device may generate information for determining the latency of the service. The device may transmit, to the client device and via the service latency monitoring session, the information for determining the latency of the service.
US10110454B2 Fast detection and identification of lost packets
The invention provides a packet loss detection system that in near-real time detects packet loss and reports the identities of the lost packets. The identities of the lost packets are based on a set of packet-specific information that includes five-tuple flow information of the packet and other unique packet identifiers. A set of meters are placed at various vantage points in the network, each meter generates digests summarizing all the traffic passing through itself. The digests are exported to a collector/analyzer, which decodes the digests and performs an analysis to detect packet losses and to determine the lost packets' identities. The collector compares between the traffic digests generated by all the meters surrounding the segment. Mismatches among the digests indicate packet losses. The collector restores the identifiers of the lost packets by further decoding the mismatches between the digests.
US10110444B2 Model driven service state machine linkage methodology and system
Novel tools and techniques are provided for implementing model driven service state machine linkage functionality amongst different machines and/or networks. In some embodiments, a computing system of a first network associated with a first entity might establish a communication link with a node of a second network associated with a second entity. The computing system might determine whether there is a common network resource state schema between the two networks, and, if so, might identify available versions, then negotiate which version to use as common version. The computing system might retrieve network state information for the two networks, might generate a user interface that incorporates and presents the network state information for the two disparate networks consistent with the common version of the common schema, and might send the user interface to a user device of a user for display of the network state information of the two disparate networks.
US10110442B2 Hierarchical data surfacing configurations with automatic updates
User interactions are detected that customize and create new versions of the configuration of a selected data surfacing solution. The customizations and new versions are saved as changes (or deltas) to the selected data surfacing solution. The selected data surfacing solution, with the customization deltas, is identified as a unique solution and saved as a node in a solution hierarchy that has the selected solution as its ancestor node. The selected data surfacing solution, with new version (upgrade) deltas, is identified as a new version of the selected solution and saved as a new version in the same node in a solution hierarchy. The node in the hierarchy corresponding to the selected solution with the customization and upgrade deltas inherits a configuration corresponding to the ancestor node.
US10110441B2 Network identifier translation
Translating an identifier is provided. One or more processors receives text that includes a portion of text. One or more processors identifies an identifier of an element of a network, wherein identifying the element is based, at least in part, on the portion of text. One or more processors determines one or more details of the element, wherein determining the one or more details is based, at least in part, on the identifier. One or more processors modifies a presentation of the text, wherein modifying the presentation is based, at least in part, on the one or more details of the element.
US10110440B2 Detecting network conditions based on derivatives of event trending
Embodiments relate systems and methods for detecting network conditions based on derivatives of event trending. In embodiments, a network management server can monitor the status and operation of network machines, such as servers or targets, as well as network transmission hardware (e.g. routers). Streams of network operation data from those sources can be captured and stored. The management server or other logic can examine the network operation data to identify trend lines for network conditions, such as application faults, attempted intrusions, or other events or conditions. trend line data can be treated to generate second or other higher-order derivatives, such as third-order derivatives representing the rate of change of acceleration (or jerk) in the time series of one or more conditions. The presence of acceleration or jerk for one or more trend lines, such as attempted network intrusions, can reflect an event and trigger a flag or other automated response.
US10110439B2 Identifying critical nodes in a wireless network using network topology
In an embodiment, a method of identifying critical nodes in a wireless network from a network topology graph for the network, the wireless network comprising a plurality of nodes and a plurality of links between the nodes, and the network topology graph for the network indicating the plurality of links between the nodes comprises: selecting each node in turn as a candidate node, and for each candidate node: generating a network topology graph for a sub-network comprising all of the nodes of the wireless network except the candidate node; determining from the network topology graph for the sub-network if the sub-network is fully reachable; and generating an indication that the candidate node is a critical node if the sub-network is not fully reachable.
US10110436B2 Systems and methods for providing content and services on a network system
Systems and methods for managing and providing content and services on a network system. Aspects of the invention include controlling user perceived connection speed. Other aspects of the invention include authorization and authentication components that determine access rights of client computers. Additional aspects include systems and methods for directing client computers to select connection speed. The disclosed systems and methods may be used in numerous network system applications.
US10110434B2 Cloud orchestrated cloud connector upgrades
Presented herein are techniques for orchestrating an update of an on-premises cloud connector from a cloud-based software platform. In particular, a first version of a first cloud connector is running in an active-active configuration across first and second nodes in an on-premises cluster. The first cloud connector is associated with user subscriptions to a first on-premises application and the first cloud connector connects the first on-premises application to a first cloud service hosted at a cloud-based software platform application. The first cloud connector is updated from the first version to a second version on each of the first and second nodes in a sequential manner. The update of the first cloud connector from the first version to the second version is initiated at the cloud-based software platform.
US10110430B2 Intelligent agent features for wearable personal communication nodes
Systems, methods, apparatus and software enable intelligent agent features for user nodes that are members of a communication group. Instructions instantiate an intelligent agent node as a member of the communication group. Each intelligent agent node can be instantiated by a communication group management system, an intelligent agent system and/or by one or more of the communication group members, for example by executing software on one or more computing systems or devices. A variety of services and other assistance can be provided by intelligent agent member nodes, including recording communications, auditing communications, providing audio transcription, annotating media, and paging communication devices, including communication nodes that are not members of the communication group. Communications between personal communication nodes and any intelligent agents can be secure.
US10110427B2 Distributing content based on weights associated with users specified by content provider systems
A content publishing system receives content items from content provider systems for providing to users. The content publishing system further receives mapping tables from the content provider systems specifying weights for users of the content provider systems. The content publishing system provides content items to users based on the user specific weights received from the content provider systems. As a result, a content provider system can identify users that are likely to be interested in specific content items and assigns weights to these users to adjust the likelihood of the users receiving appropriate content items via the content publishing system.
US10110425B2 Differentiated service-based graceful degradation layer
The differentiated service-based graceful degradation layer (DSGDL) allows cloud-based architectures to operate through and recover from periods of limited capability. The DSGDL protects and continues serving higher priority requests with the best possible response even as the underlying cloud-based services deteriorate. The DSGDL offloads lower priority requests to lower-grade secondary capability that can be dynamically provisioned in order to reserve the best capability for maintaining high priority service (e.g., by re-directing lower priority requests to a slightly out-of-date cached dataset, and reserve the primary consistent database for higher priority requests). The DSGDL 1) implements an overlay network over existing cloud services to route and enforce priority requests, and 2) provisions on-demand computing nodes and sites to provide secondary capability for service requests as needed.
US10110424B1 Node failure recovery tool
A node failure recovery tool includes an interface and one or more processors. The interface is configured to receive a first portion and a second portion of state information from a first node. The one or more processors are configured to determine a time that the first portion of state information was received and store the first portion of state information and the time that the first portion of state information was received. The one or more processors are further configured to determine a time that the second portion of state information was received and start a timer, determine that the timer has expired and that the third portion of state information has not been received, and after determining that the first node has crashed, send a retrieved second portion of state information to the first node so that the first node can recover from the crash.
US10110419B2 Alarm to event tracing
An alarm might not have information helpful to resolve the alarm to its contributing events. Thousands of events can occur in a system in a relatively short period of time, and any number of those events can contribute to various alarms. Tracing contributing events to an alarm can provide some helpful insight or at least efficiently provide a starting point for resolving or investigating an alarm. A system can determine, maintain, and persist associations at least among events, rule instances, and alarms to allow alarm-to-contributory event tracing.
US10110414B2 Communication apparatus, methods, and non-transitory computer-readable media for determining IP addresses for use in different networks
A communication apparatus includes a processor and a memory. The processor executes computer-readable instructions stored in the memory. The instructions instruct the communication apparatus to establish a first network including the communication apparatus and a first device. The instructions instruct the communication apparatus to establish a second network including the communication apparatus and a second device. The instructions instruct the communication apparatus to determine a target IP address. Determining the target IP address includes identifying a particular IP address, which is an IP address of the communication apparatus used in the second type network. Determining the target IP address includes generating the target IP address to be within a particular range using the particular IP address. The particular range is a range of IP addresses that are not available in the second type network. The instructions instruct the communication apparatus to assign the target IP address to the first device.
US10110413B2 Communicating information in a social network system about activities from another domain
In one embodiment, a method is described for tracking information about the activities of users of a social networking system while on another domain by maintaining a profile for each user of the social networking system, each profile identifying a connection to other users of the social networking system and including information about the user, receiving communications from a third party website having a different domain than the social network system, each message communicating an action taken by a user of the social networking system on the third party website, logging the actions taken on the third-party website in the social networking system, each logged action including information about the action, and correlating the logged actions with one or more advertisements presented to the one or more users on the third-party website as well as correlating the logged actions with a user of the social networking system.
US10110412B2 Dynamically allocated computing method and system for distributed node-based interactive workflows
A system and method for leveraging grid computing for node based interactive workflows is disclosed. A server system spawns a server process that receives node graph data and input attributes from a computing device, processes the data, caches the processed data, and transmits the processed data over a network to a computing device. The computing device runs a node graph application instance comprising proxy nodes configured to initiate a request to process node graph data at the server system. The server processed node graph data is displayed on the computing device. A plurality of computing devices may collaborate on a complex node graph where the node graph data processing is distributed over a plurality of servers.
US10110411B2 Device programming with system generation
A secure programming system and method for provisioning and programming a target payload into a programmable device mounted in a programmer. The programmable device can be authenticated before programming to verify the device is a valid device produced by a silicon vendor. The target payload can be programmed into the programmable device and linked with an authorized manufacturer. The programmable device can be verified after programming the target payload by verifying the silicon vendor and the authorized manufacturer.
US10110406B2 Systems and methods for channel interleaving in wireless networks
Methods and apparatuses for providing wireless messages can include, for example, an apparatus configured to provide wireless communication. The apparatus includes a memory that stores instructions and a processor coupled with the memory and configured to execute the instructions to select a dual sub-carrier modulation (DCM) mode or a non-DCM mode. The processor is further configured to select one or more interleaver parameters based on the selection of the DCM mode or the non-DCM mode. The processor is further configured to select a first set of interleaver parameters when the DCM mode is selected and a second set of interleaver parameters, different than the first set of interleaver parameters, when the non-DCM mode is selected. The processor is further configured to apply the one or more interleaver parameters to interleave data of a message. The processor is further configured to provide the message for transmission to a receiving device.
US10110403B2 Systems and methods for transporting digital RF signals
A master unit for use within a distributed antenna system includes: re-sampling devices configured to output re-sampled digital downlink signals by re-sampling digital downlink signals at customized resample rates based on at least one factor, the re-sampled digital downlink signals having a smaller bandwidth than the digital downlink signals; and a framer configured to multiplex the re-sampled digital downlink signals and to generate a first frame that includes the re-sampled digital downlink signals as framed data for transport to one or more remote units of the distributed antenna system, wherein the one or more remote units of the distributed antenna system are configured to transmit radio frequency signals using at least one antenna, wherein the transmitted radio frequency signals are derived from the framed data of the first frame received from the master unit.
US10110402B2 PAM4 signal generation apparatus
A PAM4 signal generation apparatus is provided. The PAM4 signal generation apparatus includes a DFB, two EA modulators, an SOA, a PSR, a direct-current power source, two electrical-signal generators, and two amplitude-limiting amplifiers. The two electrical-signal generators and the two amplitude-limiting amplifiers are used to generate two NRZ electrical signals respectively, the DFB outputs two optical signals, the SOA amplifies an optical power of one of the optical signals, the two EA modulators use the NRZ electrical signals and the optical signals including “a large signal and a small signal” respectively to generate two NRZ optical signals respectively, and the two NRZ optical signals are multiplexed by the PSR to generate a PAM4 electrical signal. According to this apparatus, a linearity requirement is greatly lowered. PAM4 modulation is performed in an optical domain, and this prevents a PAM4 signal from being generated on an electrical signal.
US10110400B2 Wireless device communications system
A device includes circuitry configured to determine feedforward and feedback coefficients for an adaptive frequency-domain decision feedback equalizer (AFD-DFE) based on previously received signals. The equalizer output is determined by applying the feedforward and feedback coefficients of the AFD-DFE to a received signal, and the feedforward and feedback coefficients of the AFD-DFE are updated based on the equalizer output.
US10110399B2 Method of transferring signals via transformers, corresponding circuit and device
A circuit with galvanic isolation includes a series of n cascaded transformers including a first transformer and a last transformer in the series. A transmitter is coupled to the primary winding of the first transformer in the series of cascaded transformers, the transmitter being configured for supplying to the primary winding a transmission signal as a function of an input signal. A receiver is coupled to the secondary winding of the last transformer of the series of cascaded transformers and is configured for receiving at the secondary winding a reception signal transmitted over the series of cascaded transformers. A predistortion module is configured for applying to the transmission signal a predistortion including an (n−1)-fold integration, where n is the number of cascaded transformers, of a transmission signal that would be supplied to the input of a sole transformer present in a single-transformer solution.
US10110398B2 Adaptive receive diversity
A wireless device comprises a primary antenna, a primary transceiver, one or more secondary antennas and one or more receive diversity chains. The receive diversity chains, in some embodiments, include transceiver capability. The wireless device measures and collects various statistics. Based on the statistics, the wireless device enables or disables one or more of the receive diversity chains with respect to a cellular radio access technology (RAT). A disabled receive diversity chain, in some instances is then powered down. During an interval when a receive diversity chain is disabled, the control logic periodically or on an event-driven basis enables a given receive diversity chain to probe channel quality indicator (CQI) and channel rank values. In some embodiments, a time interval for collecting a portion of the statistics, is adapted or backed off in anticipation of use of the receive diversity chain, based on traffic circumstances.
US10110397B2 Method and device for switching tunnels and switch
A method and device for switching tunnels, and a switch are provided. The method includes that: a classid of a service route on a tunnel protection group is set as a first classid, wherein the tunnel protection group includes a first tunnel and a second tunnel; a redirection rule for the service route is determined according to the first classid; and the service route is switched from the first tunnel to the second tunnel according to the redirection rule and tunnel information of the second tunnel. By means of the method, the problem in the relevant art that a time delay is overlong due to respective switching of each service route in layer3 superposed protection is solved, and the time delay of service route switching is reduced.
US10110396B2 Home appliance
A communication apparatus is disclosed. A home appliance includes a driving unit to drive a component of the home appliance, a controller configured to control the driving unit, and a communication unit to connect to an access point apparatus based on network related information, and the communication unit to connect to a server via the connected access point apparatus, wherein in response to a predetermined event, the communication unit to provide, to the server, a single data packet that includes a plurality of attribute data and values of the attribute data. Accordingly, it is possible to easily exchange data with the server.
US10110394B2 Electronic apparatus and method of controlling the same
A home server of a home network system is provided. The home server includes a communication interface configured to communicate with a plurality of devices, included in the home network system, and a server of an internet network; and a controller configured to extract a conditional sentence from a webpage of the server, the conditional sentence including a condition and an action, and configured to generate a rule for controlling at least one of the plurality of devices to perform the action of the conditional sentence in response to the condition of the conditional sentence being satisfied.
US10110393B2 Protocol switching over multi-network interface
This application is directed to protocol switching over multi-network interface, specifically switching between mirroring and streaming protocols using one L2 connection established between a source multimedia device and a sink multimedia device, depending on the application and/or multimedia content and as facilitated by a controller device.
US10110390B1 Collaboration using shared documents for processing distributed data
A data analysis system stores in-memory representation of a distributed data structure across a plurality of processors of a parallel or distributed system. Client applications interact with the in-memory distributed data structure to process queries using the in-memory distributed data structure and to modify the in-memory distributed data structure. The data analysis system creates uniform resource identifier (URI) to identify each in-memory distributed data structure. The URI can be communicated from one client application to another application using communication mechanisms outside the data analysis system, for example, by email, thereby allowing other client devices to interact with a particular in-memory distributed data structure. The in-memory distributed data structure can be a machine learning model that is trained by one client device and executed by another client device. A client application can interact with the in-memory distributed data structure using different programming languages.
US10110383B1 Managing embedded and remote encryption keys on data storage systems
The techniques presented herein provide managing embedded and external key management systems in a data storage system. An embedded encryption key management system is selected. A first unique signature is generated using a time parameter and a randomly generated value. A backup copy of the lockbox is created, wherein access to the backup copy of the lockbox requires providing a minimum number of unique data storage system values. The encryption key management system is switched to external. A second unique signature is generated for use with the local lockbox, wherein the signature generated using a time parameter and a randomly generated value. The encryption key management system is switched back to embedded and a third unique signature is generated for use with the local lockbox, wherein the signature is generated using a time parameter and a randomly generated value.
US10110382B1 Durable cryptographic keys
Cryptographic keys are durably stored for an amount of time. A cryptographic key is encrypted so as to be decryptable using another cryptographic key that has a limited lifetime. The other cryptographic key can be used to decrypt the encrypted cryptographic key to restore the cryptographic key during the lifetime of the other cryptographic key. After the lifetime of the other cryptographic key, if a copy of the cryptographic key is lost (e.g., inadvertently and unrecoverably deleted from memory), the cryptographic key becomes irrecoverable.
US10110375B2 Cryptographic device and secret key protection method
A cryptographic device and a secret key protection method are provided. The cryptographic device protects a secret key of the cryptographic device when processing a message. The cryptographic device includes: a secret key protection circuit, configured to generate an anti-crack protection signal according to the message and the secret key by a hash calculation circuit; and a cryptographic processor, configured to process the message and the secret key according to the anti-crack protection signal to generate an encrypted message.
US10110374B2 Preventing pattern recognition in electronic code book encryption
In general, in one aspect, noise is injected into a bitmap associated with content to be presented on a display to create a noisy bitmap. The noisy bitmap is encrypted using electronic code book (ECB) encryption. The resulting ciphertext does not include recognizable patterns from the content as is typical with ECB encryption. The injection of noise may include modifying pixel values for at least a subset of pixels in the bitmap. The pixel values may be modified by using a counter, a known modification pattern, or a random number generator. The bitmap may be analyzed to determine how the bitmap can be modified to maximize the randomness of the bitmap while ensuring that the noisy bitmap is visually perceptually similar when presented. The noise may be injected into a block of pixels prior to the block being encrypted.
US10110373B2 System and method for manipulating both the plaintext and ciphertext of an encryption process prior to dissemination to an intended recipient
This technology manipulates both the plaintext and ciphertext before and after encryption respectively and prior to dissemination to recipients. The manipulation mitigates the possibility of discovery of the encryption key(s) and/or encryption parameters. Even if all of the encryption parameters are known and the encryption key is made available, considerable information would still need to be obtained to enable the recipient to be able to properly decrypt an encrypted message.
US10110368B2 Clock synchronization
In an example embodiment disclosed herein, a first clock is allowed to synchronize with a second clock as long as the time difference between the first and second clocks is less than a predefined limit. If the time difference between the clocks is not less than the predefined limit, the first clock does not synchronize with the second clock until a predefined activity has occurred.
US10110365B2 Method and apparatus for transmitting control information in wireless communication system
The present invention relates to a wireless communication system. Specifically, the present invention relates to a method for transmitting, by a terminal, control information in an FDD cell, and an apparatus therefor, the method comprising the steps of: receiving sub-frame reconfiguration information for a UL CC; receiving, on the FDD cell, a PDCCH including DCI; receiving, on the FDD cell, a PDSCH indicated by the PDCCH; and transmitting, in sub-frame n on the UL CC, HARQ-ACK information on the PDSCH, wherein the index of a PUCCH resource used in transmitting the HARQ-ACK information is determined by n(1)PUCCH=nCCE+N(1)PUCCH or n(1)PUCCH=nCCE+N(1)PUCCH+offset.
US10110364B2 Method for terminal for transmitting uplink data in FDR communication environment
Disclosed are a method and a terminal for transmitting data, the method comprising the steps of: determining, during FDR communication with a base station, an overlap region from among a resource region for transmitting an uplink data channel, the overlap region being the resource region for a downlink control channel received from the base station; mitigating the effects of self-interference in the overlap region due to an uplink communication; and transmitting the uplink data channel by means of the overlap region for which the effects of self-interference have been mitigated and the region excluding the overlap region from among the resource region for transmitting the uplink data channel.
US10110363B2 Low latency in time division duplexing
Methods, systems, and devices for wireless communication are described. A wireless system utilizing one or more time-division duplexing (TDD) configured carriers may utilize a dual transmission time interval (TTI) structure (e.g., at the subframe level and symbol-level). The symbol level TTIs may be referred to as low latency (LL) TTIs, and may be organized within LL subframes. A LL subframe may be a subframe that is scheduled for transmissions in one direction (e.g., uplink or downlink, according to a TDD configuration) and may include multiple LL symbols scheduled for both uplink (UL) and downlink (DL) transmissions. Guard periods may be scheduled between adjacent LL symbols that have opposite directions of transmission to enable user equipment (UEs) to transition from receiving mode to transmit mode (or vice versa). The LL subframes may be transparent to receiving devices that do not support LL operations.
US10110362B2 Wireless device sounding procedure
A wireless device receives at least one message comprising configuration parameters of a plurality of cells grouped into a plurality of physical uplink control channel (PUCCH) groups. The wireless device transmits, in a subframe and in a first PUCCH group, at least one SRS employing a sounding procedure for the first PUCCH group. The sounding procedure may depend, at least in part, on transmissions of a physical uplink shared channel (PUSCH) or a PUCCH in the first PUCCH group and may be independent of transmissions of PUCCH and PUSCH in a second PUCCH group. The plurality of cells may be in the same timing advance group.
US10110360B2 Recovery mechanism for ROHC with lost initialization and refresh messages
A recovery mechanism for robust header compression (ROHC) is disclosed for wireless communication systems. The ROHC recovery mechanism may allow a receiver and/or transmitter in the wireless systems to establish or reestablish a context of a packet transmission session when an initialization and refresh message is lost. In the ROHC recovery mechanism, upon receiving a compressed packet that is not associated with a context, a receiver sends a message to a transmitter suggesting the transmitter to transition to another mode. Upon receiving a subsequent packet transmission that is not associated with a context, the receiver sends another message indicating that a context has not been established or has been lost. The transmitter may then send the receiver necessary information to establish a context for the packet transmission session.
US10110356B2 Mobile communication system, base station and user equipment
The present invention relates to a mobile communication system having a coordinated communication mode in which radio communication is performed between a user equipment and a plurality of base stations in a coordinated manner and an uncoordinated communication mode in which radio communication is performed between a user equipment and a base station without coordinating with another base station, in which radio communication is performed by selectively using any of the coordinated communication mode and the uncoordinated communication mode. The coordinated communication in which radio communication is performed between a user equipment and a plurality of base stations in a coordinated manner and the uncoordinated communication in which radio communication is performed between a user equipment and a base station without coordinating with another base station are selectively used in an appropriate manner, with the result that a mobile communication system capable of exerting its performance in accordance with a situation can be provided.
US10110355B2 Uplink transmission on unlicensed radio frequency band component carriers
Methods and apparatus for using an unlicensed radio frequency band component carrier for uplink transmission are disclosed. A wireless communication device receives a carrier aggregation configuration, which can include at least one licensed radio frequency band component carrier and at least one unlicensed radio frequency band component carrier. The wireless communication device establishes a set of radio bearers and associates an unlicensed radio frequency band permission level with each of the radio bearers. The wireless communication device multiplexes uplink traffic for the radio bearers on the at least one licensed radio frequency band component carrier and the at least one unlicensed radio frequency band component carrier based at least in part on the unlicensed radio frequency band permission levels associated with the radio bearers.
US10110351B2 Communication method and apparatus for controlling data transmission and retransmission of mobile station at base station
Disclosed is a communication method for controlling data transmission of a mobile station at a base station. The method comprises the steps of: determining, by the base station, a transmission operation to be performed by the mobile station in next transmission time interval based on HARQ and schedule result; sending, in a downlink by the base station, an ACK/NACK packet, an indicator indicating the type of the transmission by the mobile station and a resource use command for the used resource based on the determined transmission operation; receiving, by the mobile station, the ACK/NACK packet, the indicator and the resource use command sent from the base station, and performing respective transmission operations according to the received ACK/NACK packet, indicator and resource use command without using any data-associated signaling in an uplink.
US10110350B2 Method and system for flow control
Managing the end-to-end reliability in the delivery with acknowledgment of data from a source node (10) to a group of destination nodes (21-23), including the steps of marking messages (1) transmitted from the source node (10); upon transmission of a message, incrementation of an overall sequence number; identification of the overall sequence number of a message transmitted by which the source node has not received an acknowledgment; and calculation of the difference between the overall sequence number of the next message to be transmitted and the identified overall sequence number. If the calculated difference is equal to a predefined threshold, suspend the transmission of messages from the source node (10) to the group of destination nodes (21-23) and conclude the presence of an error in the delivery of data.
US10110348B2 Apparatus and method for multimedia content transmissions in multi-channel wireless networks
Methods and apparatuses are disclosed for encoding and transmitting video or multimedia content in wireless communications networks. The methods include encoding a block of input symbols using upper layer rateless forward error correction (FEC) codes to generate a plurality of encoded packets. The rateless FEC codes may be layer-aware or may incorporate unequal error protection (UEP). The input symbols represent one or more layers of scalable encoded video or multimedia content. Each of the plurality of encoded packets is transmitted over a selected one of a plurality of wireless channels. The wireless channel is selected based on an importance level of the input symbols in the encoded packet exceeding a threshold. The threshold may vary dynamically based on conditions in the networks.
US10110345B2 Path sort techniques in a polar code successive cancellation list decoder
Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both ûφ=0 and ûφ=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.
US10110341B2 Data processing method, precoding method, and communication device
An encoder outputs a first bit sequence having N bits. A mapper generates a first complex signal s1 and a second complex signal s2 with use of bit sequence having X+Y bits included in an input second bit sequence, where X indicates the number of bits used to generate the first complex signal s1, and Y indicates the number of bits used to generate the second complex signal s2. A bit length adjuster is provided after the encoder, and performs bit length adjustment on the first bit sequence such that the second bit sequence has a bit length that is a multiple of X+Y, and outputs the first bit sequence after the bit length adjustment as the second bit sequence. As a result, a problem between a codeword length of a block code and the number of bits necessary to perform mapping by a set of modulation schemes is solved.
US10110340B1 System, apparatus and method for generating and transmitting an interruption signal to a substantially autonomous vehicle
Novel apparatus and methods for generating and transmitting an interruption signal to a request for a substantially autonomous vehicle taxi-service based on user-supplied input are presented. The disclosure provides an efficient technique for interrupting an initial request for a substantially autonomous vehicle taxi-service and in some embodiments, further enables for the rescheduling of the request for a substantially autonomous vehicle taxi-service to a future point in time based upon user supplied input.
US10110338B2 Apparatus and method for detecting optical signal
An optical signal detecting apparatus and method. The optical signal detecting apparatus includes an optical demultiplexer configured to demultiplex an input optical signal into a first optical signal having a first band wavelength and a second optical signal having a second band wavelength, a first optical detector configured to detect the first optical signal, and a second optical detector configured to detect the second optical signal, and the optical demultiplexer, the first optical detector, and the second optical detector may be provided in a TO-CAN package.
US10110335B2 Latency-optimized physical coding sublayer
A system for reducing latency in a networking application includes a first clock domain operating at a first clock frequency, where a media access control (MAC) sublayer sends data to a physical coding sublayer (PCS) utilizing the first clock domain. The system also includes a second clock domain operating at a second clock frequency, where data is transmitted on one or more physical medium attachment (PMA) lanes utilizing the second clock domain, and where the first clock frequency and the second clock frequency have a fixed ratio. Data is transmitted from the first clock domain to the second clock domain without buffering the data.
US10110334B2 High speed serializer using quadrature clocks
Techniques efficiently serialize multiple data streams using quadrature clocks. Serializer employs first, second, third, and fourth clock signals. Serializer receives multiple data streams via registers, with each of four paths comprising a register, buffer, and switch, with registers of first and fourth paths associated with third clock signal, and registers of second and third paths associated with first clock signal, and with switches of first and fourth paths associated with first clock signal, and switches of second and third paths associated with third clock signal. Switches of first and second paths transfer respective data bits to fifth switch via another buffer, wherein fifth switch is associated with a delayed second clock signal of a time delay component (TDC). Switches of third and fourth paths transfer respective data bits to sixth switch via another buffer, wherein sixth switch is associated with a delayed fourth clock signal of TDC.
US10110331B2 Radio communication devices and methods for controlling a radio communication device
According to various embodiments, a radio communication device may be provided. The radio communication device may include: a receiver configured to receive from a first further radio communication device first information indicating a Received Signal Strength Indication in the first further radio communication device and configured to receive from a second further radio communication device second information indicating a Received Signal Strength Indication in the second further radio communication device; a selection circuit configured to select the first further radio communication device or the second further radio communication device based on the first information and the second information; and a pairing request circuit configured to send a request for pairing to the selected further radio communication device.
US10110326B1 Multi-probe anechoic chamber (MPAC) over-the-air (OTA) test system having a radio channel (RC) emulator that has a dynamically-variable channel model, and methods
An MPAC OTA test system and method are provided that can be used to perform radiated testing of 5G BSs and 5G UEs. The arrangement and number of active probe antennas in the anechoic chamber can be selected based at least in part on a simulation of the channel model of the RC emulator to improve testing while also reducing the overall number of probe antennas that are needed and reducing the channel resources of the RC emulator of the MPAC OTA test system, thereby allowing the overall complexity and cost of the MPAC OTA test system to be reduced.
US10110323B2 Systems and methods for transmitting data from an underwater station
The systems and methods described herein include releasable storage devices that can surface with data. The devices include data storage, an antenna, battery and means to propel the device to the surface or into the atmosphere. In certain embodiments, it is a USB memory stick, a battery, suitable buoyancy, and an antenna. In certain embodiments, the systems and methods described herein include a rocket to boost the system out of the water to a higher altitude. Once the system is airborne, it can transmit data to a ship or satellite via radio communications, via other line of site methods such as optical, or may be captured by an aircraft such as a UAV.
US10110317B1 Apparatus and methods for transmitter skew and bias error compensation in an optical communication system
Apparatus and method for compensating for transmitter errors in an optical communication system are provided. In certain configurations herein, a receiver is provided for processing an analog signal vector representing an optical signal received from a transmitter. The receiver includes an analog front-end that converts the analog signal vector into a digital signal vector including a digital representation of an I component and a Q component of the optical signal. The receiver further includes a digital signal processing circuit configured to process the digital signal vector to recover data, and the digital signal processing circuit includes a transmitter error compensation system that compensates the digital signal vector for at least one of a transmit skew error of the transmitter or a modulator biasing error of the transmitter.
US10110306B2 Interference cancellation methods and apparatus
Methods and apparatus for interference cancelation in a radio frequency communications device are described. In various embodiments a signal to be transmitted in converted into an optical signal and processed using an optical filter assembly including one or more optical filters to generate an optical interference cancelation signal. The optical interference cancelation signal is converted into an analog radio frequency interference cancelation signal using an optical to electrical converter prior to the analog radio frequency interference cancelation signal being combined with a received signal to cancel interference, e.g., self interference. The optical filter assembly can include a large number of taps, e.g., 30, 50, 100 or more. Each tap may be implemented as a separate optical filter or series of optical filters. Delays and/or gain of the optical filters can be controlled dynamically based on channel estimates which may change due to changes in the environment and/or communications device position.
US10110304B2 Communication device and inspection method
A communication device includes: an optical-communication circuit that is capable of performing optical communication with a different communication device and transmits a first electric signal to the different communication device at a startup time of the communication device; an electro-communication circuit that is capable of performing electro communication with the different communication device and receives a second electric signal transmitted from the different communication device in response to the first electric signal; and a control circuit that transmits error information indicating an error in the optical communication to a device after the second electric signal is received by the electro-communication circuit.
US10110300B2 Bandwidth management across logical groupings of access points in a shared access broadband network
Systems and methods provide bandwidth management on the inroute of a satellite network. Inroute group managers (IGMs) monitor bandwidth usage in each terminal group (TG) under each of the IGMs, and report this bandwidth usage to a bandwidth manager. Upon receipt of the reported bandwidth usage from each of the IGMs, the bandwidth manager compares the bandwidth usage and minimum/maximum throughput rates associated with each TG. The bandwidth manager calculates scaling factors that it transmits to each of the IGMs to allow the IGMs to allocate bandwidth accordingly.
US10110299B2 Method and system for mobile delivery of broadcast content
A satellite dish assembly may comprise a broadcast receive module and a basestation module. The broadcast receive module may be operable to receive a satellite signal, recover media carried in the satellite signal, and output the media. The basestation module may be operable to accept the media output by the broadcast receive module and transmit the media in accordance with one or more wireless protocols. In being conveyed from the broadcast receive module to the basestation, the media content may not traverse any wide area network connection. The one or more wireless protocols may comprise one or more of: a cellular protocol and IEEE 802.11 protocol. The satellite dish assembly may comprise a routing module that may be operable to route data between the broadcast receive module, the basestation, and a gateway.
US10110298B2 Techniques for providing broadcast services on spot beam satellites
Techniques for providing broadcast services on spot beam satellite are provided. These techniques enable the mission of a spot beam satellite system to be changed from providing spot beam transmission to broadcast transmissions, and vice versa, without requiring that the satellite be reconfigured. Broadcast data may be encoded and transmitted concurrently on a plurality of spot beams. According to some embodiments, the broadcast data may be encoded using a space-time code and/or forward error corrected (FEC) encoded to enable a receiver to correct errors in the signal received from the spot beam satellite.
US10110294B2 Adaptive use of receiver diversity
A method for adaptively disabling receiver diversity is provided. The method can include a wireless communication device determining an active data traffic pattern; defining a threshold channel quality metric based at least in part on a threshold channel quality needed to support a threshold quality of service for the active data traffic pattern; comparing a measured channel quality to the threshold channel quality metric; and disabling receiver diversity in an instance in which the measured channel quality metric satisfies the threshold channel quality metric.
US10110292B2 Method and apparatus for transmitting channel state information
A method for transmitting channel status information of a user equipment (UE) in a wireless communication system. The UE reports first channel information to a base station periodically; and reports second channel information to the base station periodically. The first channel information and the second channel information are pieces of information combined to indicate one precoding matrix. The second channel information reported in a specific subframe is calculated based on last reported first channel information. A channel quality indicator (CQI) reported in the specific subframe is calculated based on one precoding matrix indicated by the last reported first channel information and the second channel information reported in the specific subframe.
US10110291B2 Method and apparatus for efficient channel state information dissemination for MU-MIMO transmission schemes based on outdated channel state information
A method and apparatus is disclosed herein for channel state information dissemination for multi-user (MU) multiple-input multiple-output (MIMO) (MU-MIMO) transmission schemes based on outdated channel state information. In one embodiment, a method for disseminating channel state information (CSI) coefficients from a first user terminal, where each CSI coefficient corresponds to the CSI previously observed by the first user terminal during transmission resource blocks used by a base station to communicate information to a second set comprising at least one user terminal and not including the first user terminal, comprises: broadcasting by the base station the channel state information (CSI) of each user terminal in the second set of user terminals, on the subset of transmission resources used by the base station to communicate information to each user terminal in the second set; receiving observations of these transmissions by the first user terminal; performing, at first user terminal, eavesdropper channel selection of a subset of CSI coefficients between the base station and the eavesdropping first-user terminal for uplink CSI feedback, the subset chosen out of the set of CSI coefficients between base station and the first user-terminal on the transmission resources used by the base station to communicate information to each user terminal in the second set; scheduling the subset of the selected CSI coefficients for uplink transmission; and transmitting the subset of the selected CSI coefficients via the uplink transmission.
US10110288B2 Frequency division duplex (FDD) return link transmit diversity systems, methods and devices using forward link side information
A Frequency Division Duplex (FDD) wireless terminal includes spaced-apart antennas that are configured to transmit over a return link and to receive over a forward link that is spaced apart from the return link in frequency. The FDD wireless terminal is configured to selectively refrain from transmitting over the return link from at least one of the spaced-apart antennas of the FDD wireless terminal in response to differentials in forward link power that is received at the spaced-apart antennas of the FDD wireless terminal, that are caused, for example, by blocking appendages of a user of the wireless terminal. Related methods are also described.
US10110285B2 Pilot scheme for a MIMO communication system
The present invention employs a pilot scheme for frequency division multiple access (FDM) communication systems, such as single carrier FDM communication systems. A given transmit time interval will include numerous traffic symbols and two or more short pilot symbols, which are spaced apart from one another by at least one traffic symbol and will have a Fourier transform length that is less than the Fourier transform length of any given traffic symbol. Multiple transmitters will generate pilot information and modulate the pilot information onto sub-carriers of the short pilot symbols in an orthogonal manner. Each transmitter may use different sub-carriers within the time and frequency domain, which is encompassed by the short pilot symbols within the transmit time interval. Alternatively, each transmitter may uniquely encode the pilot information using a unique code division multiplexed code and modulate the encoded pilot information onto common sub-carriers of the short pilot symbols.
US10110281B2 Near field communication device
A near field communication (NFC) device capable of operating by being powered by the field includes an NFC module for generating an electromagnetic carrier signal and modulating the carrier signal according to data to be transmitted, and an antenna circuit coupled to and driven by said NFC module with the modulated carrier signal. An electromagnetic compatibility (EMC) filter of the NFC device is coupled to the NFC module via output terminals of said NFC module. A powered by the field circuit of the NFC device is adapted to harvest energy from an external field to power said NFC device. The power by the field circuit is coupled to said EMC filter via one or more impedance elements. The NFC device is adapted to be able to operate in one of a reader mode, a battery supplied card mode, and a powered by the field card mode.
US10110273B2 Interference mitigation in wireless communication systems
A wireless communication assembly stores configuration parameter sets for predefined spectral masks, including: a single channel mask for a base channel bandwidth, and defining target power levels for each of a base in-band bandwidth, base transition bandwidths, and a base floor bandwidth; and a bonded channel mask for a multiple of the base channel bandwidth, and defining target power levels for each of a bonded in-band bandwidth equivalent to the sum of the base in-band bandwidth and the base channel bandwidth, and bonded transition and floor bandwidths that are multiples of the base transition and floor bandwidths. A radio controller selects predefined channels each having the base channel bandwidth, for transmitting data to a recipient station; retrieves selected one of the configuration parameter sets based on the number of selected channels; and applies the selected configuration parameter set to data for transmission to the recipient station.
US10110271B2 Circuits and methods for biasing switch body
Described herein are circuits and methods for improving switch performance when overdriving the gate by adding a delay on a PMOS gate voltage such that it can turn on the PMOS during switch state transition to allow charge/discharge of the switch body voltage faster and it can turn off once the process is complete. For example, back-to-back diodes can be used to separate the PMOS gate and drain. This can reduce leakage current and can reduce or eliminate the potential for breakdown of the switch.
US10110259B1 Band selection switch apparatus of power amplifier system
A band selection switch apparatus includes: a first switch including a first series switch disposed between a transmission input terminal and a first transmission and reception terminal; a second switch including a second series switch disposed between the transmission input terminal and a first transmission terminal; and a third switch including a third series switch disposed between a first reception output terminal and the first transmission and reception terminal. The first series switch includes a first series switch circuit including first series switch elements connected between the transmission input terminal and a first intermediate node, a second series switch circuit including second series switch elements connected between the first intermediate node and the first transmission and reception terminal, and a first shunt switch circuit including first shunt switch elements connected between the first intermediate node and a ground.
US10110258B2 Accelerated erasure coding for storage systems
A method for generating coded fragments comprises receiving data to be encoded, splitting the data into a plurality of data fragments, identifying a first group of data fragments from among the plurality of data fragments using a coding matrix, summing the data fragments within the first group of data fragments to generate a first group sum, and using the first group sum to calculate at least a portion of two or more coded fragments.
US10110249B2 Column-layered message-passing LDPC decoder
In an illustrative example, a decoder includes a variable node unit (VNU) that includes a variable-to-check lookup table circuit configured to output a variable-to-check message corresponding to a check node. The VNU also includes a hard-decision lookup table circuit configured to output a hard decision value corresponding to a variable node. The decoder also includes a check node unit (CNU) responsive to the variable-to-check message and configured to generate an updated check-to-variable message.
US10110246B1 Δ-Σ methods for frequency deviation measurement of know nominal frequency value
Disclosed are three methods for precise measurement of frequency deviation of known nominal frequency. Delta adder method (DA), comprising of delta-sigma modulator, delta-adder, delay line, low-pass filter, and zero crossing detector. The second method (DA+RE), comprising of delta-sigma modulator, circuit for squaring delta-sigma bit-stream, delta-adder, low-pass filter, and zero-crossing detector. The third method comprises of reference delta-sigma modulator for synchronization of two or more dislocated frequency sources of known nominal frequency.
US10110245B2 Apparatus for interpolating between a first signal edge and a second signal edge, a method for controlling such apparatus, and an interpolation cell for a digital-to-time converter
An apparatus for interpolating between a first signal edge and a second signal edge is provided. The apparatus includes a plurality of interpolation cells coupled to a common node. At least one of the plurality of interpolation cells is configured to supply, based on a control word, the first signal edge and/or the second signal edge to the common node. Further, the apparatus includes a control circuit configured to activate all of the plurality interpolation cells in a first mode of operation, and to deactivate part of the plurality of interpolation cells in a second mode of operation.
US10110243B1 Successive approximation register analog-to-digital converter capable of accelerating reset
A successive approximation register analog-to-digital converter capable of accelerating reset comprises: a sampling circuit generating at least one output signal(s) according to at least one input signal(s); a comparator generating at least one comparator output signal(s) according to the at least one output signal(s) and a reset signal; a control circuit controlling the operation of the sampling circuit according to the at least one comparator output signal(s) or the equivalent thereof, and generating the reset signal; a first reset wire circuit outputting the reset signal to the comparator so that a first circuit of the comparator is reset when the value of the reset signal is a first value; and a second reset wire circuit outputting the reset signal to the comparator so that a second circuit of the comparator is synchronously reset when the value of the reset signal is the first value.
US10110238B2 Frequency divider, phase-locked loop, transceiver, radio station and method of frequency dividing
An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided. The electronic circuit comprises a first frequency divider arranged to receive the oscillating signal and output N frequency divided signals of different phases, a second frequency divider arranged to receive one of the N signals and frequency divide the received signal by a value given by a first control signal provided to the second frequency divider, N latch circuits each being arranged to receive a respective one of the N signals at a clocking input of the respective latch circuit and to receive an output of the second frequency divider at an input of the respective latch circuit, a multiplexer circuit arranged to receive outputs of the N latch circuits and to output a signal, on which the output signal is based, selected from the received signals based on a second control signal provided to the multiplexer circuit, and a control circuit arranged to provide the first control signal and the second control signal based on the divide ratio. A phase-locked loop circuit, a transceiver circuit, a radio station, and a method of frequency dividing an oscillating signal are also provided.
US10110237B2 System and a method for detecting loss of phase lock
A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.
US10110232B2 Multiplexer and latch system
A memory includes a clock generator and a multiplexing latch circuit. The clock generator is configured to generate a first latching clock signal and a second latching clock signal based on a multiplexing select signal and a clock signal, and to transmit the first latching clock signal and the second latching clock signal. The multiplexing latch circuit is configured to select the first data or the second data based on the first latching clock signal and the second latching clock signal, and to store and output the selected data.
US10110231B1 Level shifter for a wide low-voltage supply range
A voltage translator translates an input signal to an output signal spanning a wide range of low voltages. An input buffer receives the input signal. A level shifter provides an output control signal. A gate control circuit provides gate control signals. An output buffer provides the output signal. The level shifter includes a pair of cross coupled P-type metal oxide silicon (PMOS) transistors each in series with an N-type metal oxide silicon (NMOS) transistor. A third NMOS transistor is coupled between an upper rail and a drain of one PMOS transistor; the gate of the third NMOS transistor is controlled by a first input control signal. A fourth NMOS transistor is coupled between the upper rail and a drain of the other PMOS transistor; the gate of the fourth NMOS transistor is controlled by a second input control signal.
US10110227B2 Internal voltage generation circuit
An internal voltage generation circuit includes a comparison circuit, a driving signal generation circuit and a driving circuit. The comparison circuit generates a comparison signal from an internal voltage in response to a reference voltage. The driving signal generation circuit generates a pull-up driving signal and a pull-down driving signal having different duty ratios in response to the comparison signal. The driving circuit drives the internal voltage in response to the pull-up driving signal and the pull-down driving signal.
US10110226B2 Architecture, system, method, and computer-accessible medium for expedited-compaction for scan power reduction
Exemplary method, computer-accessible medium, and test configuration can be provided for testing at least one flip-flop. For example, the exemplary test configuration can include at least one scan-out channel having a plurality of regions and a plurality of compactors associated with the plurality of regions. Further, exemplary method, computer-accessible medium, and test configuration can be provided for testing at least on flip-flop that in which at least one scan-out channel having a plurality of regions, a plurality of compactors, and associating the plurality of compactors with the plurality of regions can be provided.
US10110224B2 Triaxial photoconductive switch module
Methods, systems, and devices describe triaxial photoconductive switch modules that include a center conductor, an inner conductor, an outer conductor, a high voltage capacitor that is formed between the center conductor and the inner conductor, and a photoconductive switch that is formed between the center conductor and a section of the outer conductor. The disclosed triaxial photoconductive switch modules include low inductance current paths that lead to high current efficiencies. Furthermore, the disclosed triaxial photoconductive switch modules eliminate or reduce parasitic capacitance problems of existing systems.
US10110223B2 Single ended-to-differential converter
A single-ended-to-differential converter for driving an LVDS (Low Voltage Differential Signaling) driving circuit includes a first converting circuit, a second converting circuit, and a controller. The first converting circuit converts an input signal into a first output signal. The first converting circuit has a tunable delay time. The second converting circuit converts the input signal into a second output signal. The second converting circuit has a fixed delay time. The controller generates a first control signal and a second control signal according to the first output signal and the second output signal, so as to adjust the tunable delay time of the first converting circuit.
US10110222B2 Drive unit
A drive unit includes a first transistor, a second transistor, a current source that is connected to a high-potential-side electrode of the first transistor, and delivers constant current, a current control circuit configured to perform control to start of charging of the gates of the first and second transistors using the current source, and a gate charge circuit that charges the gates of the first and second transistors, separately from the current source.
US10110221B1 Power transistor control signal gating
A half bridge GaN circuit is disclosed. The circuit includes a low side power switch, a high side power switch, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a receiver input reset circuit configured to simultaneously receive first and second signals, wherein the first signal corresponds with the high side power switch being turned on, wherein the first signal corresponds with the high side power switch controller turning on the high side power switch, wherein the second signal corresponds with the high side power switch controller turning off the high side power switch, and wherein the receiver input reset circuit is further configured, in response to the first and second signals, to prevent the high side power switch from becoming non-conductive.
US10110216B1 Over voltage protection of a transistor device
An once a channel voltage exceeds a threshold, when the transistor is in an OFF state. This is over-voltage protection circuit for a transistor is presented. This circuit acts to switch on the transistor achieved with internal components which are integrated with the transistor, avoiding the need for external diodes or Zener structures. The circuit has a transistor with a control terminal, a first current carrying terminal and a second current carrying terminal. The over-voltage protection circuit has a level shifter arranged to feed back a level-shifted version of a channel voltage between said first and second current carrying terminals to the control terminal. The level shifter allows the switching threshold voltage of the transistor to be crossed when a predetermined value of the channel voltage is crossed.
US10110213B2 Semiconductor device
Provided is a semiconductor device which is testable even with an inspection apparatus having low current drivability, and includes an output terminal which is also used as a test terminal and an output driver having high current drivability. The semiconductor device includes a plurality of voltage determination circuits connected to the output terminal of the semiconductor device, and have threshold values that are different from each other, an encoding circuit connected to the plurality of voltage determination circuits, and configured to output an encoded signal, and a mode switching circuit configured to output a mode signal to an internal circuit depending on the encoded signal and a signal from the internal circuit.
US10110211B1 Semiconductor integrated circuit
A synchronous circuit may be provided. The synchronous circuit may include a first buffer configured to receive an input signal and control the transition timing of an output signal based on a control code. The synchronous circuit may include a delay circuit configured to control a delay time based on the control code to constantly maintain a time that the input signal received by the first buffer arrives at a synchronizing circuit.
US10110210B2 Apparatus and method for strobe centering for source synchronous links
Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes a data path to receive data information based on timing of a data capture clock signal, a clock path including a delay circuit to apply a time delay to an input clock signal and generate a delayed clock signal, a clock tree circuit to provide the data capture clock signal and a first feedback clock signal based on the delayed clock signal, a circuitry including latches to sample the input clock signal based on timing of the feedback clock signal and provide sampled information, and a controller to control the delay circuit based on the sampled information in order to cause the data capture clock signal to be out of phase with the input clock signal by one-fourth of a period of the input clock signal.
US10110206B2 Voltage controlled current path, a voltage clamp, and an electronic component including a voltage clamp
According to a first aspect of this disclosure there is provided a voltage controlled current path. The voltage controlled current path comprises a first stage arranged to conduct current once the voltage at an input node of the first stage exceeds a threshold value. The amount of current that passes through the first stage is a function of the voltage at the input node. A second stage is arranged to pass a current that is a function of the current passing through the first stage.
US10110200B2 Surface acoustic wave filters with substrate thickness selected from plural non-contiguous thickness ranges
Surface acoustic wave (SAW) filters and methods of fabricating SAW filters are disclosed. A filter includes a piezoelectric wafer having a thickness within one of a plurality of noncontiguous thickness ranges that define piezoelectric wafers upon which filter circuits meeting predetermined requirements can be fabricated according to a predetermined design using a predetermined fabrication process, and a filter circuit fabricated on the piezoelectric substrate according to the predetermined design using the predetermined fabrication process.
US10110198B1 Integrated quartz MEMS tuning fork resonator/oscillator
A piezoelectric quartz tuning fork resonator having a pair of tines formed from a common quartz plate, with a middle electrode and two outer electrodes being disposed at or on top and bottom surfaces of each of the pair of tines and interconnected such that the outer electrodes at or on the top and bottom surfaces of a first one of the pair of tines are connected in common with the middle electrodes on the top and bottom surfaces of a second one of the pair of tines and further interconnected such that the outer electrodes at or on the top and bottom surfaces of the second one of the pair of tines are connected in common with the middle electrodes on the top and bottom surfaces of the first one of the pair of tines.
US10110195B2 CMOS tuner and related tuning algorithm for a passive adaptive antenna matching network suitable for use with agile RF transceivers
A novel and useful adaptive antenna tuner and associated calibration mechanism for passive adaptive antenna matching networks. The tuner is suitable for use with cellular antennas and in one embodiment uses MEMS based tunable devices. The tuner contains voltage and current sensors inserted before the antenna matching network. The sensed complex impedance generates one or more update control signals for the tuning algorithm which drives the MEMS-based tunable devices.
US10110192B2 Electronic component
An electronic component includes a multilayer body and a first resonator. The multilayer body includes insulating layers stacked on each other in a stacking direction. The first resonator includes a first inductor and a first capacitor disposed in the multilayer body. The first inductor is defined by a conductive layer disposed on an insulating layer of the plurality of insulating layers and an interlayer connecting conductor which passes through an insulating layer of the plurality of insulating layers in the stacking direction connected to each other so that the first inductor preferably has a helical or substantially helical shape as viewed from a first direction perpendicular or substantially perpendicular to the stacking direction. A certain portion of the first inductor is located on a predetermined plane perpendicular or substantially perpendicular to the first direction, and a remaining portion of the first inductor is displaced from the predetermined plane in the first direction.
US10110189B2 Structure and method of manufacture for acoustic resonator or filter devices using improved fabrication conditions and perimeter structure modifications
A method of manufacture for an acoustic resonator or filter device. In an example, the present method can include forming metal electrodes with different geometric areas and profile shapes coupled to a piezoelectric layer overlying a substrate. These metal electrodes can also be formed within cavities of the piezoelectric layer or the substrate with varying geometric areas. Combined with specific dimensional ratios and ion implantations, such techniques can increase device performance metrics. In an example, the present method can include forming various types of perimeter structures surrounding the metal electrodes, which can be on top or bottom of the piezoelectric layer. These perimeter structures can use various combinations of modifications to shape, material, and continuity. These perimeter structures can also be combined with sandbar structures, piezoelectric layer cavities, the geometric variations previously discussed to improve device performance metrics.
US10110188B2 Structure and method of manufacture for acoustic resonator or filter devices using improved fabrication conditions and perimeter structure modifications
A method of manufacture for an acoustic resonator or filter device. In an example, the present method can include forming metal electrodes with different geometric areas and profile shapes coupled to a piezoelectric layer overlying a substrate. These metal electrodes can also be formed within cavities of the piezoelectric layer or the substrate with varying geometric areas. Combined with specific dimensional ratios and ion implantations, such techniques can increase device performance metrics. In an example, the present method can include forming various types of perimeter structures surrounding the metal electrodes, which can be on top or bottom of the piezoelectric layer. These perimeter structures can use various combinations of modifications to shape, material, and continuity. These perimeter structures can also be combined with sandbar structures, piezoelectric layer cavities, the geometric variations previously discussed to improve device performance metrics.
US10110184B2 Power amplification system with reactance compensation
Power amplification system is disclosed. A power amplification system can include a Class-E push-pull amplifier including a transformer balun. The power amplification can further include a reactance compensation circuit coupled to the transformer balun. In some embodiments, the reactance compensation circuit is configured to reduce variation over frequency of a fundamental load impedance of the power amplification system.
US10110179B2 Audio circuit
An audio amplifier includes an operational amplifier, a replica of an output stage of the operational amplifier, and a feedback circuit configured such that, in a normal mode, an output signal of the operational amplifier is fed back to the input side of the operational amplifier, and such that, in a calibration mode, an output signal of the replica is fed back to the input side of the operational amplifier. The calibration circuit cancels out the offset voltage of the audio amplifier. An adjustment circuit changes the offset of the audio amplifier according to a control signal S1. A control circuit adjusts the control signal such that an output signal VS of the replica is within a predetermined target range in a state in which a predetermined voltage is input to the audio amplifier. Memory stores the control signal S2 acquired in the final stage.
US10110171B2 Amplifier
An output signal can be free of any noise component generated from an amplifier disposed in a path, without degradation of the S/N ratio of the output signal. An amplifier includes: a first amplifier that is connected to an input node and generates a first intermediate signal; a feedback resistor that enables feedback of the first intermediate signal to the input node; an attenuator that receives the first intermediate signal and generates a second intermediate signal; a second amplifier that is connected to the input node and generates a third intermediate signal; a third amplifier that is connected to the input node and generates a fourth intermediate signal; and an adder that generates an output signal, using the second intermediate signal, the third intermediate signal, and the fourth intermediate signal.
US10110170B2 Semiconductor package having an isolation wall to reduce electromagnetic coupling
A system and method for packaging a semiconductor device that includes a wall to reduce electromagnetic coupling is presented. A semiconductor device has a substrate on which a first circuit and a second circuit are formed proximate to each other. An isolation wall of electrically conductive material is located between the first circuit and the second circuit, the isolation wall being configured to reduce inductive coupling between the first and second circuits during an operation of the semiconductor device. Several types of isolation walls are presented.
US10110169B2 Apparatus and methods for envelope tracking systems with automatic mode selection
Apparatus and methods for envelope tracking systems with automatic mode selection are provided herein. In certain configurations, a power amplifier system includes a power amplifier that amplifies a radio frequency signal and that receives power from a power amplifier supply voltage. The power amplifier system further includes an envelope tracker that generates the power amplifier supply voltage based on an envelope signal corresponding to an envelope of the radio frequency signal. The envelope tracker includes a signal bandwidth detection circuit that processes the envelope signal to generate a detected bandwidth signal, and a mode control circuit that controls a mode of the error amplifier based on the detected signal bandwidth.
US10110167B2 Down-conversion mixer
A down-conversion mixer includes a transconductance unit, a resonant unit and a mixing unit. The transconductance unit converts a differential input voltage signal pair into a differential input current signal pair. The resonant unit provides a negative resistance and a differential auxiliary current signal pair. The mixing unit mixes a combination of the differential input current signal pair and the differential auxiliary current signal pair with a differential oscillatory voltage signal pair to generate a differential mixed voltage signal pair.
US10110160B2 Three-directional photovoltaic module connector
A three-directional photovoltaic module connector. The module connector includes first serial connection portion on each side for connecting two adjacent photovoltaic modules together in a serial, end-to-end connection. The module connector also includes a first parallel connection portion for connecting the two serially connected pairs of adjacent photovoltaic modules together in parallel, that is, side-to-side. The module connector further includes a vertical connection portion for attaching a mounting foot to elevate the photovoltaic module connector above a support surface such as a roof.
US10110159B2 Solar cell module
A solar cell module according to an embodiment includes a solar cell panel including at least one solar cell; and a frame positioned at a periphery of the solar cell panel. The frame includes at least one fixing hole to receive an output cable.
US10110157B2 Machine tool
A machine tool includes a drive unit driving a tool for machining a workpiece, and a control unit controlling the drive unit. The machine tool further includes an abnormality determining unit that determines whether machining can be continued, based on operation information of the drive unit, and a power failure detection unit that switches the power source of the control unit from a normal power supply unit to an emergency power supply unit if power failure is detected, and switches the power source from the emergency power supply unit to the normal power supply unit if recovery of power supply is detected after power failure. The control unit stops operation of the drive unit when power failure is detected, and thereafter, if recovery of power supply is detected, and the abnormality determining unit determines that machining can be continued, the control unit drives the drive unit, thereby automatically resuming machining.
US10110154B2 Controller and a method to drive an inverter circuit for a permanent-magnet synchronous motor
A controller is provided to drive an inverter circuit for a PMSM. The inverter circuit is connected to a battery through a DC link capacitor, and is driven in one safe state during a fault condition. The controller monitors at least one parameter with respective threshold value to drive the inverter circuit in one safe state comprising an active Short Circuit (SC) and a Freewheel (FW). While in FW state, the controller switches from the FW state to the SC state if the at least one parameter is above the respective threshold. While in SC state, the controller controls engine speed to bring the PMSM to a predetermined speed when the stator temperature is more than a threshold temperature value. The controller switches from the SC state to the FW state.
US10110150B2 Primary magnetic flux control method
A primary magnetic flux command value is changed in accordance with a torque of a rotary electric motor to control a current phase of an armature current with respect to a q axis that advances by π/2 with respect to a d axis in phase with a field flux to be a desired phase in accordance with the torque.
US10110145B2 DC to AC converter
A DC-to-AC converter including six phase modules and two capacitors, a transformer with a three-phase primary winding and with two three phase secondary windings, each phase module receiving a DC voltage from a DC voltage bus and capable of transmitting an AC current, and including a transistor, able to modulate the output voltage according to five intensity levels, the first capacitance connected between the positive portion and the midpoint of the DC voltage bus, the second capacitance connected between the negative portion and the midpoint of the DC voltage bus, the first, second and third phase module are linked by their output to a different phase of the first secondary winding. The fourth, fifth and sixth phase module are each linked by their output to a different phase of the second secondary winding of the transformer, the primary winding of the transformer is linked to an electrical power supply network.
US10110142B2 Balancing and/or discharge resistor arrangements
Circuits comprising at least one energy storage device, a resistor and switch arranged in series with the resistor are described. The energy storage device is arranged in parallel with the series connection of the switch and the resistor, and the switch is arranged to selectively switch the resistor into a parallel connection to the energy storage device. In some examples, the switch comprises a series connection of semiconductor switching elements. In some examples, the circuit may comprise a sub-module for use in a multilevel modular converter.
US10110127B2 Method and system for DC-DC voltage converters
On embodiment pertains to an apparatus including a control loop configured to receive an output voltage sense signal. The control loop includes a compensator; a PWM signal generator coupled to an output of the compensator; a reference circuit configured to receive a tracking signal, and which is configured to low bandwidth low pass filter the tracking signal when the tracking signal amplitude becomes substantially constant and representative of an output voltage that is substantially non-zero; and an error amplifier having a first input coupled to an output of the reference circuit, a second input configured to receive the output voltage sense signal, and an output coupled to the compensator.
US10110122B2 Transient performance improvement for constant on-time power converters
Response of a variable frequency switching constant on-time or adaptive on-time controlled power converter to a large step-up or step-down change in load is improved with a simple circuit that detects magnitude and polarity of a change in output voltage and initiates, extends or terminates conduction of power pulses from an input source through said power converter. Both the amplitude and duration of undershoot or overshoot of the transient response are reduced or, alternatively, the capacitance of an output filter may be significantly reduced and still provide comparable transient performance. The fast adaptive on-time control is applicable to multi-phase power converters using phase managers or one or more phase-locked loops for interleaving of power pulses.
US10110120B2 Load adaptable boost DC-DC power converter
A boost DC-DC power converter comprising a semiconductor switch arrangement comprising a plurality of series connected semiconductor switches. A first capacitor is connected between a first intermediate node of a first leg of the semiconductor switch arrangement and a second intermediate node of a second leg of the semiconductor switch arrangement. A control circuit is coupled to respective control terminals of the plurality of semiconductor switches. A load sensor is configured to detect a load current and/or a load voltage of a load circuit connectable to at least a first DC output voltage of the DC-DC power converter. The control circuit being further configured to adjusting one or more operational parameters of the boost DC-DC power converter based on the detected load current and/or load voltage.
US10110119B2 Power supply and method of manufacturing
A multiplier assembly for a power supply and a method of manufacturing the multiplier assembly. The multiplier assembly may be a stack of capacitors and support elements electrically and mechanically coupled together to form a first capacitor string and a second capacitor string. The support elements may electrically and mechanically connect adjacent series capacitors in the first capacitor string. Additionally or alternatively, the support elements may electrically and mechanically connect adjacent series capacitors in the second capacitor string. In one embodiment, the power supply may include drive and feedback circuitry capable of controlling operation of the multiplier assembly.
US10110118B2 Charge pump effect compensation for high frequency isolation transformer in lighting device power supplies
An apparatus (400A, 400B, 400C, 400D, 500A, 500B, 800) supplies power to an output thereof. The apparatus includes: an isolation transformer (110) and a rectifier (120). The isolation transformer has a parasitic capacitance (Cp) between one of its input terminals (1S/1F) and one of its output terminals (2S/2F). The rectifier has a pair of input terminals connected to the output terminals of the isolation transformer, and a pair of output terminals connected across the apparatus' output. The rectifier includes a plurality of diodes (D1/D2/D3/D4) connected in a bridge. The apparatus also includes a compensation device for compensating for an increase in an output voltage across the output of the apparatus due to a charge pump effect of the parasitic capacitance. The compensation device includes at least one compensation capacitor (410, 510/520, 810/812) connected across one of the diodes of the bridge.
US10110117B2 Multilevel power conversion device
A power converter has: switching elements connected in parallel to each of primary-side filter capacitors, freewheel diodes connected in parallel to the switching elements, and snubber resistances connected in parallel to the switching elements. The controller causes stoppage of the power converter by turning off each of the switching elements. After stoppage of the power converter, the controller causes a discharge circuit to operate by turning on a thyristor, thereby discharging the primary-side filter capacitors. By discharging of the primary-side filter capacitors, a secondary-side filter capacitor is discharged via the freewheel diodes.
US10110115B2 Switching power supply device with controlled discharge circuit
A switching power supply device includes: a latch circuit to be set by a latch signal that is generated when an anomaly is detected, the latch circuit stopping the turning ON and OFF of the switching element when set by the latch signal; a pulse generator that receives said latch signal and generates a pulse signal at a prescribed cycle in response to said latch signal; a discharge circuit that is activated every time said pulse signal is provided so as to discharge electric charges stored in the capacitor; and a comparator for undervoltage protection that, when said control power supply voltage decreases to a prescribed operation stop voltage as said capacitor discharges, resets the latch circuit and the pulse generator, respectively.
US10110113B2 Active filter and AC-DC conversion device
An active filter is connected in parallel to a rectifier circuit between a set of AC input lines and a pair of DC buses. The active filter includes a capacitor, a pair of current limiting elements and an inverter. One in the current limiting elements is disposed between one end of the capacitor and one in the DC buses. Other in the current limiting elements is disposed between other end of the capacitor and other in the DC buses. At least one of the current limiting elements is disposed in an orientation to be forward with respect to a DC voltage outputted by the rectifier circuit. The inverter includes: a set of AC-side terminals connected to the set of AC input lines; and a pair of DC-side terminals connected to both ends of the capacitor.
US10110111B2 Signal processor, filter, control circuit for power converter circuit, interconnection inverter system and PWM converter system
A signal processor is configured to perform a process equivalent to performing a series of fixed-to-rotating coordinate conversion, a predetermined process and then rotating-to-fixed coordinate conversion, while maintaining linearity and time-invariance. The signal processor performs a process given by the following matrix G: G = [ F ⁡ ( s + j ⁢ ⁢ ω 0 ) + F ⁡ ( s - j ⁢ ⁢ ω 0 ) 2 F ⁡ ( s + j ⁢ ⁢ ω 0 ) - F ⁡ ( s - j ⁢ ⁢ ω 0 ) 2 ⁢ j - F ⁡ ( s + j ⁢ ⁢ ω 0 ) - F ⁡ ( s - j ⁢ ⁢ ω 0 ) 2 ⁢ j F ⁡ ( s + j ⁢ ⁢ ω 0 ) + F ⁡ ( s - j ⁢ ⁢ ω 0 ) 2 ] where F(s) is a transfer function representing the predetermined process, ω0 is a predetermined angular frequency and j is the imaginary unit.
US10110106B2 Vibration motor with coil and two sets of magnets for improving vibration intensity
A vibration motor is provided in the present disclosure. The vibration motor includes a stationary part, a vibration part and an elastic connector. The stationary part includes a housing providing an accommodating space. The vibration part is suspended within the accommodating space by the elastic connector. The stationary part comprises a coil, and the vibration part comprises a first magnet set and a second magnet set; the first magnet set and the second magnet set are respectively disposed at two opposite sides of the coil to generate a closed magnetic loop. The first magnet set includes a first left magnet, a first middle magnet and a first right magnet, the second magnet set includes a second left magnet, a second middle magnet and a second right magnet which are opposite to the first left magnet, the first middle magnet and the first right magnet respectively.
US10110104B2 Permanent manget synchronous motor
A permanent magnet synchronous motor is provided in the present disclosure. The permanent magnet synchronous motor includes a housing as well as a stator and a rotor received in the housing, the stator surrounding the rotor, wherein the stator comprises a core which surrounds the rotor and is annular and a plurality of coils wound on the core, the plurality of coils are disposed at intervals and distributed in an annular array, the core is composed of a plurality of core blocks spliced with each other, the core block comprises a raised part on the outer wall, and grooves matched with the raised parts in shape and used for positioning the raised parts are formed in the inner wall of the housing.
US10110103B1 Electric drive system enhancement using a DC-DC converter
An electric drive system includes bus rails carrying a bus voltage, an energy storage system (ESS), and a power inverter. The system includes a voltage converter connected to the bus rails and having an inductor coil, semiconductor switches, a bypass switch connected to a positive bus rail, and a capacitor. A polyphase electric machine is electrically connected to the power inverter. A controller executes a method in which operation of the converter is regulated based on power, torque, and speed values of the electric machine. The converter is selectively bypassed by closing the bypass switch under predetermined high-power/high-torque conditions, with the bus voltage adjusted until it is equal to the battery output voltage. The bypass switch is opened and the bus voltage thereafter regulated to a predetermined voltage.
US10110101B2 Single-phase induction motor, hermetic compressor, and refrigeration cycle device
The single-phase induction motor includes a stator fixed in a cylindrical frame by shrink-fitting or press-fitting, a main winding wire and an auxiliary winding wire provided on the stator, and a rotor provided on an inner circumferential side of the stator, in which an arc-shaped arc portion and a linear cutout portion are formed on an outer circumference of the stator, the arc portion is arranged on the outer circumference of the stator in a direction of the main winding wire magnetic pole with respect to the center of the stator, and a relief portion for reducing a contact area between the arc portion and an inner circumferential surface of the frame is formed on the arc portion.
US10110098B2 Integrated system
An integrated system includes a controller, a drive device, a fastening supporting member, and a fixing member. The controller has a controller connector. The drive device has a drive device connector that is connected to the controller connector so that the drive device is electrically coupled to the controller. Via the fastening supporting member, the controller and the drive device are maintained in an electrically coupled state in which the drive device connector is connected to the controller connector. Via the fixing member, the controller and the drive device are maintained in a mechanically coupled state in which the drive device is mechanically coupled to the controller.
US10110096B2 Position sensing system
A position sensing system for a switched reluctance machine, such as that of an Integrated Starter Generator, Turbogenerator or electric Supercharger wherein the system comprises a pair magnets, a magnet carrier, and a sensor element, wherein the sensor element is mounted upon an end of a rotatable shaft of the SR machine, and wherein the sensor element is mounted on a circuit board, and sits in a well formed by the magnets which are arranged such that the magnetic flux follows a path similar to that of a horseshoe magnet, and whereby magnetic flux produced by the magnets is concentrated within the well of the magnet carrier in a direction normal to the axial direction of the shaft of the SR machine.
US10110090B2 Drive arrangement for auxiliary units in the motor vehicle sector
A drive arrangement for auxiliary units in a motor vehicle has a control unit and an electric drive unit that is connected via a transmission arrangement to at least one auxiliary unit. An electric drive unit (8) is connected in terms of drive to at least two auxiliary units (4, 6) by drive trains (12, 16) of a transmission arrangement (10). Clutch members (22, 24) for coupling or decoupling the auxiliary units (4, 6) in terms of drive are provided in the respective drive trains (12, 14).
US10110089B2 Tuning of a kinematic relationship between members
Described herein is a device comprising members in a kinematic relationship. The kinematic relationship is at least partially governed by at least one magnetically induced force that introduces a force threshold that, in effect, provides a threshold to part movement and confers a degree of hysteresis, preventing movement until a sufficiently large energizing force is applied. The effect may be further altered by use of an additional magnetically induced force interaction with at least one further member to urge or slow movement once started and/or to prevent movement once a new position is reached.
US10110088B2 Machine and method for monitoring the state of a safety bearing of a machine
In a method for monitoring a state of a safety bearing of a rotor shaft of a machine, with the rotor shaft being supported by a magnetic bearing and the safety bearing having an outer ring and an inner ring arranged for rotation with respect to the outer ring, the rotor shaft of the machine is caught with the safety bearing when the magnetic bearing of the machine fails. The magnetic bearing is witched off for monitoring the state of the safety bearing. The rotor shaft is rotated with the machine under control of a higher-ranking controller by using a defined motion sequence, and a physical variable of the safety bearing is measured with a sensor.
US10110081B2 Winding system
A winding system for a stator and/or a rotor of an electric machine is disclosed. The winding system comprises several conductor sections, two annular conductors (+, −) on a first side of the winding system, to which the conductor sections are coupled by means of half bridges, and at least one half bridge on an opposite side of the winding system, to which at least one conductor section is connected.
US10110079B2 Wound field generator system featuring combined permanent magnet generator excitation with exciter stator
The present disclosure broadly relates to apparatuses and methods for generating electric power. More particularly, the present disclosure relates to a self-excited electric generator. The self-excited electric generator may include auxiliary windings to provide a source of electricity to an associated generator control unit (GCU). The apparatuses and methods of the present invention may provide added benefits of reducing excitation requirements from the GCU. Thereby, the apparatuses and methods may reduce cost, weight, and size of an electric generator, and may increase reliability of associated systems.
US10110070B2 Wireless power transmitter with array of transmit coils
Techniques for wireless transmitting power are described. An example power transmitting unit includes a magnetic resonance-type transmit coil array comprising a plurality of coil elements, wherein each coil element is tuned to a same resonant frequency. The power transmitting unit also includes a power generating circuitry to deliver current to the transmit coil array to wirelessly power a device within an active wireless charging area of at least one of the plurality of coil elements. Each coil element exhibits a plurality of zero point distances and the spacing between neighboring coil elements corresponds with the plurality of zero point distances.
US10110067B2 Power transmission system
A power transmission system that can prevent a plunge in power transmission efficiency even when there is a positional shift of a power reception antenna with respect to a power transmission antenna. A power transmission system includes: a power transmission antenna that includes a wound power transmission coil that is placed on the ground; a power reception antenna that is disposed in such a way as to face the power transmission antenna, includes a wound power reception coil, and receives electric energy from the power transmission antenna via an electromagnetic field, wherein an area of a first projection plane that is formed by the power transmission coil in a vertical direction with respect to a horizontal plane is larger than an area of a second projection plane that is formed by the power reception coil in the vertical direction with respect to the horizontal plane.
US10110065B2 Electronic circuit for transmitting power from a terminal side to a sensor side and method of use
The present disclosure includes an electronic circuit for use in process automation for transferring electrical energy from a terminal element to a sensor over an inductively coupled interface. The sensor measures the power it receives over the inductive interface and compares this value to a target power value. The difference between the actual and target values is communicated back to the terminal element. The terminal element adjusts its power output to the sensor to minimize this difference. The disclosure includes the use of the electronic circuit and a sensor arrangement comprising the electronic circuit, as well as a method for transmitting power.
US10110059B2 Circuit and device for power switching
A power switching device includes a primary power source, a backup power source, and a power switching circuit, and the power switching circuit can switch rapidly between the two or more power sources. The power switching circuit includes a first switching module, a second switching module, and a control module. The first switching module includes first through fourth relays, and first through fourth driving units. The first switching module also includes a first bidirectional thyristor and a second bidirectional thyristor. A power switching circuit is also provided.
US10110053B2 Battery powered system and method for charging
A unique method for charging a battery includes comparing a parameter to a limit, wherein the parameter relates to previous charging of the battery; determining a current state of the battery; and performing a next charging cycle based on the comparison and/or the current state of the battery. A unique system includes a vehicle, a battery, and a charging system for charging the battery. The charging system includes a controller for determining whether the battery is in short term storage or long term storage; starting a new charge cycle after a first amount of reduction in the charge of the battery if the battery is in short term storage; and starting the new charge cycle after a second amount of reduction in the charge of the battery if the battery is in long term storage.
US10110049B2 Cellular telephone charger
The present disclosure relates to a charger (1, 101, 201) for wirelessly charging a cellular telephone (T). The charger (1, 101, 201) comprises a housing (9, 109, 209) for receiving a portion of the cellular telephone (T), and a charging panel (7, 107, 207) comprising means (30) for wirelessly charging the cellular telephone (T). The charging panel (7, 107, 207) is movably mounted to the housing (9, 109). The charging panel (7, 107, 207) is movable between a non-charging position and a charging position.
US10110045B2 Method for producing an oscillating circuit
A method for producing an electrical oscillating circuit for an inductive charging device, having at least one oscillating circuit component. In a method step, the at least one oscillating circuit component is classified as a function of a structurally caused deviation of a characteristic value of the oscillating circuit component from a nominal value.
US10110044B2 Wireless charging mouse, wireless input apparatus and input method
Disclosed is a wireless charging mouse, comprising a wireless power receiving circuit, a wireless radiating circuit, a displacement detecting circuit and a control circuit. The control circuit is electrically connected to the wireless power receiving circuit, the wireless radiating circuit and the displacement detecting circuit. The wireless power receiving circuit wirelessly receives electromagnetic energy from a charging board. The displacement detecting circuit detects the displacement of the wireless charging mouse. The control circuit receives the electromagnetic energy from the wireless power receiving circuit, and outputs a displacement detecting signal to a wireless receiver through the wireless radiating circuit according to the detected displacement obtained from the displacement detecting circuit. When the electromagnetic energy received by the wireless charging mouse is less than a predetermined electromagnetic energy, the control circuit stops outputting the displacement detecting signal to the wireless receiver.
US10110042B2 Cart for wirelessly recharging mobile computing devices
A cart stores a plurality of mobile computing devices. The cart includes a plurality of slots defined by opposed plates. Each of the slots is configured to accept a corresponding mobile computing device. Each of the plates includes a first transmit coil for wirelessly transmitting power to a receive coil in the corresponding mobile computing device.
US10110041B2 System and method of charging a chemical storage device
A system is provided to allow for charging of a chemical storage device without a rectifier. A gate is used in conjunction with a gate controller. The gate controller monitors input voltage and opens the gate when voltage crosses a zero crossing in a first direction. The gate monitor then closes the gate when the voltage crosses a zero crossing in a second direction. This increases the chances that the output power will have voltage in a single direction. This output power is then fed to a chemical storage device, where it can be stored and used by one or more electronic devices.
US10110037B2 Battery charging circuit, control circuit and associated control method
A battery charging circuit receives an input current, and provides a system voltage and a charging current to charge a battery. A control circuit used to control the battery charging circuit has a charging current control loop providing a compensation signal, an inductor current control loop providing a first loop control signal, and a system voltage control loop providing a second loop control signal. The control circuit provides an inductor current reference signal based on the compensation signal and a designed maximum input current level. And the control circuit provides a control signal based on the first loop control signal the second loop control signal to control the battery charging circuit.
US10110032B2 Charge control circuit using battery voltage tracking, and a device having the same
A charge control circuit includes: a charge current control circuit configured to receive an input voltage at a first node, output a sensing current to a second node, and turn on a power transistor; a comparator configured to compare a voltage level of the second node with a voltage level of a third node, wherein the third node receives a charging current from the power transistor; a current mirror configured to generate a mirror current corresponding to the sensing current; and an amplifier configured to receive a first feedback voltage based on the mirror current, and amplify a difference between the first feedback voltage and a reference voltage to generate a switch control signal, wherein in response to the switch control signal and a plurality of control signals, the charge current control circuit is configured to decrease the sensing current and turn on the power transistor.
US10110028B2 Quick-charging control method and system
A quick charging control method and system are suitable for mobile terminals. The method includes: a first controller obtaining a voltage value of a cell, and sending the voltage value to a second controller; the second controller searching a threshold segment table to find a current regulation instruction matched with a threshold segment containing the voltage value of the cell, and sending the current regulation instruction to a regulation circuit; the regulation circuit performing a current regulation according the current regulation instruction, and outputting a power signal; the second controller sending a second switch-off instruction to the first controller and a second switch circuit respectively if second abnormal charging information is detected; and the second switch circuit, controlling the charging adapter to stop sending the power signal after the current regulation if the second switch circuit receives the second switch-off instruction.
US10110025B2 Enhanced parallel protection circuit
An enhanced parallel protection circuit is provided. A system using separate battery packs in a parallel configuration is arranged with multiple protection circuit modules (PCMs). The PCMs are configured to detect fault conditions, such as over voltage, under voltage, excess current, excess heat, etc. Individual PCMs can be configured to control associated switches and/or other components. When a fault condition is detected by an individual PCM, the individual PCM triggers one or more associated switches to shut down one or more components. In addition, by the use of the techniques disclosed herein, the individual PCM can also trigger switches that are controlled by other PCMs. Configurations disclosed herein mitigate occurrences where a multi-PCM device is operating after at least one PCM has shut down. Configurations disclosed herein provide safeguards and redundant protection in scenarios where a fault event is detected by one PCM and not detected by another PCM in a parallel configuration.
US10110021B2 Balancing device and electrical storage device
There is provided a balancing device that equalizes voltages between storage cells of a battery composed of a plurality of series-connected storage cells or voltages between electrical storage modules composed of a plurality of series-connected storage cells of the battery. The balancing device equalizes voltages between the energy storage modules by transferring electric power between the electrical storage modules through an element to which all of the electrical storage modules are connected, the transferring being realized by on-off control of current supply to each of the electrical storage modules, the on-off control being performed with a first duty cycle. Further, the balancing device introduces a period in which the on-off control is performed with a second duty cycle, the second duty cycle being different from the first duty cycle. Furthermore, the balancing device measures a voltage applied to each of the capacitance elements C1 and C2 which connect between the terminals of the electrical storage modules respectively. Furthermore, the balancing device determines the presence of an open circuit in lines which connect the capacitance elements C1 and C2 and the electrical storage modules, the determination being performed based on change of the voltages during the period which are applied to the capacitance elements C1 and C2.
US10110019B2 Battery with communication interface
A standard two terminal battery package is configured to communicate with an external charger or load, without requiring modification to the battery mechanics and/or high current circuit components integral with the battery. A transmitter and receiver (transceiver) are incorporated into the battery housing. An associated battery charger and/or load, e.g., tool, appliance, vacuum, etc., has a corresponding transceiver configured to communicate with the battery transceiver. A microcontroller may be coupled to the transceiver. Serial number verification between the battery and tool load can be verified. Sensors for temperature, voltage, pressure and pH may be coupled between the battery and microcontroller for monitoring battery temperature, voltage charge and condition during operation or charging thereof. Information from these sensors and more may be communicated from the battery to the load or battery charger. Furthermore, the battery charger may communicate over the Internet for battery operational history collection and theft identification.
US10110016B2 Electrical conversion and distribution system for an aircraft
The invention relates to an electrical conversion and distribution system for an aircraft, the system comprising a synchronous starter-generator (ENG S/G) intended to be coupled to an aircraft engine, a rectifier (R) capable of transforming alternating voltage into direct voltage, an auxiliary synchronous starter-generator (AUX S/G) intended to be coupled to an auxiliary power group, a first, a second and a third power converter (CV1, CV2, CV3) capable of transforming direct voltage into alternating voltage or vice versa, and at least one battery (BATT).
US10110015B2 Electrical conversion and distribution system for an aircraft
The invention relates to an electrical conversion and distribution system for an aircraft, the system comprising at least one synchronous starter-generator (S/G1, S/G2) intended to be coupled to an engine (Engine1) of the aircraft, at least one conversion path comprising a plurality of power converters (CVn, CV′n) associated with switching means suitable for supplying at least one charge (CAC1, CAC2, CAC3, CAC4, P1, P2) from at least one source (S/G1, S/G2, AUX S/G1, AUX S/G2, GPU1, GPU2), and at least one distribution path suitable for supplying electrical charges (CT1n, SW1n, CT2n, SW2n).
US10110013B2 Downhole switch assemblies and methods
A switch assembly includes one or more solid state semiconductor switches configured to be disposed within a downhole pipe assembly. The one or more switches are configured to operate in a closed state to conduct electric current supplied by a power source disposed above a surface to pumps disposed beneath the surface to cause the pumps to extract a resource from beneath the surface via the pipe assembly. The one or more switches also are configured to operate in an open state to stop conducting the electric current from the power source to the pumps.
US10110008B2 Micro grid stabilization device
A micro grid stabilization device coupled to a DC bus and an AC bus in parallel is provided. A DC power generation apparatus provides power to the DC bus. An AC power generation apparatus provides power to the AC bus. A converter is coupled between the DC bus and the AC bus to transform the voltage of the DC bus and provide the transformed voltage to the AC bus. When the voltage of the DC bus or the AC bus is unstable, the micro grid stabilization device provides power to at least one of the DC bus and the AC bus to stabilize the power of the DC bus and the AC bus.
US10110002B2 Automated demand response system
A system and method for reducing an electrical load in a facility with a building automation system, includes first receiving information for a demand response event from an automated demand response server at an automated demand response client. After receipt of a new demand response event, the system determines a plurality of devices of the building automation system to be controlled during the demand response event. Next, the system prepares a schedule of control actions for the plurality of devices during the demand response event. The system then sends control messages to the building automation system to execute the control actions for the plurality of devices according to the schedule of control actions for the demand response event.
US10109999B2 Technology for extending a radio frequency (RF) bandwidth of an envelope tracking (ET) power amplifier (PA)
An envelope tracking power supply (ET PS) transmission line switch can be operable between an ET PS and a radio frequency (RF) power amplifier (PA). The ET PS transmission line switch assembly can include a quarter wavelength (¼λ) transmission line configured for high impedance at a specified low RF and a switch coupled to a specified point on the quarter wavelength transmission line to generate a high frequency quarter wavelength transmission line when the switch is toggled. The quarter wavelength transmission line is configured to be coupled to a voltage output of the ET PS and a RF output of the RF PA. The high frequency quarter wavelength transmission line is configured for high impedance at a specified high RF, and the specified high RF is higher than the specified low RF.
US10109996B2 Method and system for detecting miswiring of a power supply for a domestic appliance
A system for detecting miswiring in an AC power supply for an appliance may comprise a voltage sensor sensing the voltage of a first hot line of the power supply for powering light electrical loads, a phase sensor sensing the phase difference between the first and a second hot line powering heavy electrical loads therebetween, and a control module coupling to the phase and voltage sensors. The control module may identify a first fault condition indicating that the second hot line and a neutral line are reversed when the voltage of the first hot line exceeds a threshold, and may identify a second fault condition indicating that the first hot line and the neutral line are reversed when the phase signal is within a phase threshold measured from 0 degrees. The system may disconnect different electrical loads from the power supply in the first and the second fault conditions.
US10109993B2 Surge protection device
A circuit protection device includes a metal oxide varistor (MOV), a spring terminal and a thermal disconnect coupling the spring terminal to the MOV. A gas discharge tube (GDT) is coupled to the MOV. The spring terminal is biased such that upon occurrence of an overvoltage condition, heat generated by the MOV melts the thermal disconnect and allows the spring terminal to be displaced away from the MOV, thereby creating an opening circuit.
US10109988B2 Balancing and synchronizing device for machines for laying cables
Balancing and synchronizing device for a plant (10) comprising one or more brake machines (12) for laying cables (11), each of which comprises a plurality of unwinding members each provided with at least a pair of capstans (14). The device comprises a plurality of control units (22, 22a), configured to automatically adjust the unwinding tension of each individual cable (11), and user interface means (18), independently connected to each control unit (22, 22a), so as to set predetermined functional and operating parameters of each pair of capstans (14). Each control unit (22, 22a) is connected to detector elements (21) of a corresponding pair of capstans (14). The device comprises a data transmission and reception line (25) to which the control units (22, 22a) are connected for at least a part of the laying cycle. The device comprises at least a main control unit (22a) provided with synchronization command means (30) to command, by means of the data transmission and reception network (25), the other control units (22) for the synchronized balancing and drive of the relative pairs of capstans (14), on the basis of specific functional and operating parameters set by the user interface means (18a) of the main control unit (22a) and of the signals received from the position detector elements (21).
US10109986B2 Prechamber spark plug for a gas-powered internal combustion engine, and method for manufacturing same
A prechamber spark plug for a gas-powered internal combustion engine, having a metallic body, an insulator, a center electrode, at least one ground electrode, a cap, and a sleeve. The cap is arranged at a front end of the spark plug and shields the center and ground electrodes from a combustion chamber after the prechamber spark plug is installed in the internal combustion engine, and the cap delimits a prechamber in which the center electrode and the ground electrode are located from the combustion chamber. The cap has at least one opening that permits gas exchange between the prechamber and the space outside of the prechamber. The cap is mounted on the sleeve, which surrounds a section of the body, contains external threads for screwing into the internal combustion engine, and is joined to the body. In addition, a method for manufacturing the aforementioned spark plug is described.
US10109985B2 Semiconductor igniter plug for an aircraft turbomachine, comprising scoops for discharging possible fuel residues
An igniter plug for an aircraft turbomachine includes an external electrode, an internal electrode, as well as a semiconducting body arranged between the external electrode and the internal electrode and set back from these electrodes so as to define an electrical arc forming cavity, the bottom of which is formed by an axial end surface of the semiconducting body. The free end of the external electrode is equipped with at least one scoop for discharging possible fuel residues present in the cavity.
US10109981B2 Asymmetric optical waveguide grating resonators and DBR lasers
Monolithic asymmetric optical waveguide grating resonators including an asymmetric resonant grating are disposed in a waveguide. A first grating strength is provided along a first grating length, and a second grating strength, higher than the first grating strength, is provided along a second grating length. In advantageous embodiments, the effective refractive index along first grating length is substantially matched to the effective refractive index along second grating length through proper design of waveguide and grating parameters. A well-matched effective index of refraction may permit the resonant grating to operate in a highly asymmetric single longitudinal mode (SLM). In further embodiments, an asymmetric monolithic DFB laser diode includes front and back grating sections having waveguide and grating parameters for highly asymmetric operation.
US10109980B2 Optical semiconductor element and laser device assembly
Provided is an optical semiconductor element including: a stacked structure body 20 formed of a first compound semiconductor layer 21, a third compound semiconductor layer (active layer) 23, and a second compound semiconductor layer 22. A fundamental mode waveguide region 40 with a waveguide width W1, a free propagation region 50 with a width larger than W1, and a light emitting region 60 having a tapered shape (flared shape) with a width increasing toward a light emitting end surface 25 are arranged in sequence.
US10109977B2 Laser light source device
An optical unit is retained by a hole provided at a base member. The optical unit includes a laser light emitting element and a lens. The base member is provided with a guide part that is used for determining the position of the laser light emitting element in the hole of the base member.
US10109976B2 Divided pulse lasers
Methods, systems, and devices are disclosed for divided-pulse lasers. In one aspect, a pulsed laser is provided to include a laser cavity including an optical amplifier and a plurality of optical dividing elements and configured to direct a laser pulse of linearly polarized light into the plurality of optical dividing elements to divide the light of the laser pulse into a sequence of divided pulses each having a pulse energy being a portion of the energy of the laser pulse before entry of the optical dividing elements, to subsequently direct the divided pulses into the optical amplifier to produce amplified divided pulses. The laser cavity is configured to direct the amplified divided pulses back into the plurality of optical dividing elements for a second time in an opposite direction to recombine the amplified divided pulses into a single laser pulse with greater pulse energy as an output pulse of the laser cavity.
US10109973B2 Insulating busbar and manufacturing method
To realize an insulating busbar that has both low inductance and high withstand voltage, provided is an insulating busbar that connects to a module on which is mounted a semiconductor chip, including a plurality of circuit conductors; a plurality of connection terminals that respectively electrically connect the circuit conductors to the module; and an insulating resin portion that is formed integrally between each of the circuit conductors and at least a portion of a region around each connection terminal and does not have any gaps between the circuit semiconductors.
US10109972B2 Terminal crimping device
A terminal crimping device that crimps a terminal to a component includes a terminal feeder feeding one or more pre-formed terminals on a generally horizontal feed plane and a ram moving a drive crimper along a generally vertical crimp stroke. The drive crimper engages the pre-formed terminal at the feed plane and transfers the terminal to a crimp zone below the feed plane and remote from the terminal strip to crimp the terminal to the component.
US10109964B2 Jack device
A jack device includes an insertion portion configured to receive a plug through an open end along a first axis. The insertion portion has an opening and a terminal. The opening has a predetermined depth from the open end to an inside of the insertion portion. The opening has a first inner surface that is increasingly away from the first axis from the inside to the open end, and a second inner surface whose distance from a certain point on the first axis is shorter than a distance between the first inner surface and the certain point. The terminal is located further inside than the opening in a direction of the first axis and is opposite to the second inner surface in a direction crossing the first axis. The terminal comes into pressure contact with the plug when the plug is inserted into the insertion portion.
US10109963B2 Slide connector
A slide connector includes a garment-side connector portion and a module-side connector portion, the garment-side connector portion includes a garment-side connector body, first contacts having contact surfaces parallel to a fitting plane, and a locking portion having a locking surface, the module-side connector portion includes a module-side connector body, spring type second contacts having contact portions displaceable in a direction orthogonal to the fitting plane, and a portion to be locked, one of the garment-side connector portion and the module-side connector portion having an elastically deformable waterproof member that is located in the fitting plane and has a closed shape surrounding the contact surfaces of the first contacts or the second contacts.
US10109960B2 Cable attachment device and connection assembly for measuring cable temperature
An attachment device for cables is described herein. This attachment device includes a central body formed of a plastic material and defining a cavity configured to receive a temperature probe and a plurality of straps extending from the central body, each strap of the a plurality of straps configured to secure a cable to the central body, wherein the central body defines a wall having a first side configured to be in contact with the temperature probe and a second side in contact with a cable. This attachment device may notably be used in an electrical connection assembly having a connector, a temperature sensor disposed within the device, and at least two cables.
US10109952B2 Electrical connector assembly with axial connection assist
A connector includes a first housing, a second housing, a mate assist slider, and a cam gear. The first-housing has a first outer surface. The second housing is configured to mate with the first housing, and the second housing includes a pin extending from a second outer surface. The connector also includes a mate assist slider moveable from an unmated position to a mated position. The connector also includes a cam gear mounted to the first outer surface. The cam gear moves in response to a movement of the mate-assist-slider from the unmated position to the mated position. The cam gear has a cam slot with an inertial detent. A vibratory feedback is provided to an assembler indicative of a properly positioned connector housing when the pin is moved past the inertial detent.
US10109951B1 Electrical connection structure and electronic apparatus using the same
An electrical connection structure includes a housing, a connector, a pushing component and a lifting component. The housing has a top portion, a bottom portion and a groove between the top portion and the bottom portion. The connector is disposed in the groove. The pushing component is disposed in the groove and a part thereof is exposed from the opening of the top portion. The lifting component is disposed in the groove and connected between the pushing component and the connector. When the electrical connection structure is connected to the electronic device, the electronic device pushes the pushing component to move in a first direction toward the bottom portion, so that the pushing component drives the lifting component to move in a second direction opposite to the first direction and toward the top portion, so that the lifting component lifts up the connector to be connected to the connection interface.
US10109947B2 System and method for sealing electrical terminals
A system and device for sealing a plurality of electrical wires to a wire attachment portion of an electrical terminal, wherein the device further includes a first piece of heat shrink tubing having a predetermined length, wherein the first piece of heat shrink tubing has been placed over the plurality of electrical wires such that one end thereof extends over the wire attachment portion of the electrical terminal; a second piece of heat shrink tubing having a predetermined length, wherein the second piece of heat shrink tubing has a smaller diameter than the first piece of heat shrink tubing, and wherein the second piece of heat shrink tubing is placed partially inside the end of the first piece of heat shrink tubing that extends over the wire attachment portion of the electrical terminal; and a band of adhesive placed within the first piece of heat shrink tubing adjacent to the second piece of heat shrink tubing.
US10109945B2 Active cover plates
A variety of active cover plate configurations with prongs configured to contact side screw terminals of electrical receptacles are described.
US10109938B2 Flex circuit connector configuration
An electronic system of a device includes first and second circuit boards and a flexible connector configured to electrically connect the first and second circuit boards. The flexible connector includes a serpentine portion that includes first, second and third legs. The first leg that extends in a first direction, the second leg extends in a second direction opposite of the first direction, and the third leg extends in the first direction. The first, second and third legs are configured in a common plane when the device is in an operational state.
US10109932B2 Electrical clamps
The present disclosure provides electrical clamps that can easily attach to a variety of shaped objects, such as fence posts and other objects for the purpose of establishing an electrical connection or conductive path between the electrical clamp, an object the electrical clamp is secured to, and a conductor attached to the electrical clamp. The electrical clamp utilizes an adjustable saddle construction that can be secured to the geometry of objects, such as a square, rectangular, round or oval geometry of the object, and a clamp cap construction that can electrically couple one or more conductors to the electrical clamp.
US10109931B2 Cover element for an electrical connector
A cover for an electrical connector comprises a cylindrical disc including a first cover surface, an opposite second cover surface, and a barrel surface extending between the first cover surface and the second cover surface. The first cover surface has a convex form. In a state in which the cover is mounted on the electrical connector, the first cover surface forms a portion of an outer surface of the electrical connector and the second cover surface faces an inner side of the electrical connector.
US10109930B2 Wire connection assembly with telescopic binding screw
A wire connection assembly comprises a connector body and a binding screw. The connector body forms a wire receiving chamber and has a threaded bore extending perpendicular to the wire receiving chamber. The binding screw has an inner bolt and an outer bolt. The inner bolt includes an outer thread and an inner breaking point. The outer bolt includes an inner thread engaging the outer thread, a threaded section engaging the threaded bore, and an outer breaking point.
US10109926B2 Antenna radiator, antenna and mobile terminal
An antenna comprises: a circuit board; an antenna radiator, wherein the antenna radiator is provided with a first gap, a second gap, a first grounding piece, a second grounding piece and a feed piece, the first gap and the second gap forming a first inverted-F antenna connected to the first grounding piece and a second inverted-F antenna connected to the second grounding piece on the antenna radiator, and the feed piece being respectively connected to the first inverted-F antenna and the second inverted-F antenna; and an antenna frequency reconstruction system, wherein the antenna frequency reconstruction system is provided on the circuit board, the antenna frequency reconstruction system is respectively connected to the first grounding piece and the second grounding piece and is grounded, and the antenna frequency reconstruction system switches one of the first grounding piece and the second grounding piece to be grounded. Also provided are an antenna radiator and a mobile terminal.
US10109925B1 Dual feed slot antenna
A dual feed slot antenna can include a ground plane formed with an aperture, and first feed and second feeds extending into the aperture. The first feed and second feed can extend into the aperture so that the first feed and second feed are coincident and out of phase with other. The first feed and said second feed can define a U-shaped stub, with a respective stub length, a stub width, a crossbar and a pair of stub tines defining a stub separation extending from the crossbar. The first feed and second feed can extend into the aperture so that each of the stub tines from a first feed are coincident the stub tines from the second feed. With this configuration, and with further selection of the said respective stub lengths, stub widths and stub separations, a symmetric omnidirectional radiation can be established for the antenna.
US10109923B2 Complex antenna
A complex antenna configured to transmit or receive radio-frequency signals includes a first antenna unit and a second antenna unit. The first antenna unit is fixed to the second antenna unit with a first included angle, and the complex antenna does not have a closed annular structure.
US10109922B2 Capacitive-fed monopole antenna
A monopole antenna structure disclosed herein includes a ceramic block with a metallic surface coupled to a feed structure and a planar radiation element electrically floating relative to the ceramic block. The planar radiation element is in a parallel plane alignment with the metallic surface of the ceramic block. When the feed structure provides signal of one or more select frequencies to the metallic surface of the ceramic block, the ceramic block radiates (e.g., transmits a carrier wave) and in turn, excites the planar radiation element to re-radiate the signal.
US10109920B2 Metasurface antenna
An antenna is provided including an electromagnetic metasurface. The electromagnetic characteristics of the antenna are dynamically tunable.
US10109917B2 Cupped antenna
Described embodiments provide a cupped antenna for transmitting and receiving radio signals. The cupped antenna includes a cup having a rear surface and one or more side surfaces. The rear surface and side surfaces define a cavity having a first radiating element of the cupped antenna disposed within it. The first radiating element is coupled to a first feed circuit. The one or more side surfaces have one or more indentations disposed therein. The one or more indentations are configured to reduce a size and weight of the cup. The one or more indentations also provide an opening within an aperture of the cupped antenna such that an additional antenna can be disposed within the opening.
US10109915B2 Planar near-field calibration of digital arrays using element plane wave spectra
A calibration method, applicable to element-level digital arrays operating in the receive mode, which utilizes the individual element plane wave spectra obtained from a single planar near-field scan. The method generates highly accurate near-field measurement derived amplitude and phase calibration of both large and small digital arrays as a function of array scan. The present disclosure provides digital array calibration methods and their potential uses in satellites and directional arrays.
US10109910B2 Antenna device with accurate beam elevation control useable on an automated vehicle
An antenna device includes a plurality of conductive pads that are conductively coupled to each other. A first one of the pads is connected with a first conductive strip. The first conductive strip is not connected to an adjacent second pad. A second conductive strip and a third conductive strip connect the first pad to the second pad. A slot is aligned with the first conductive strip to direct energy from a transceiver at the first conductive strip. The first pad and others in series with it radiate energy based on the energy received by the first conductive strip. The second and third conductive strips conduct energy from the first pad to the second pad. The second pad and others in series with it radiate energy based on the energy received by the second pad. One example use of the antenna device is on an automated vehicle.
US10109908B2 Antenna module and electronic devices comprising the same
An antenna module and an electronic device are provided. The antenna module may include a first case including a case surface, wherein at least one antenna protection part is disposed on the first case, and wherein the at least one antenna projection part is formed to be distinguishable from the case surface, an antenna including a pattern, wherein at least a part of the pattern of the antenna is adjacently disposed to the antenna protection part.
US10109907B2 Multi-mode cavity filter
A multi-mode cavity filter, including two dielectric resonator bodies, the first incorporating a piece of dielectric material having a shape to support a first resonant mode and a second substantially degenerate resonant mode; the second also including a piece of dielectric material; the piece of dielectric material having a shape to support a first resonant mode; a layer of conductive material in contact with and covering both of the dielectric resonator bodies; an aperture in the layer at the interface of the first and second dielectric resonator bodies, for transferring signals from the second dielectric resonator body to the first, transferring signals from the first dielectric resonator body to the second and/or outputting signals from the first dielectric resonator body, the aperture being arranged for coupling signals to the first and second resonant modes in parallel, and/or coupling signals from the first and second resonant modes in parallel.
US10109905B2 Multi-mode resonator
The present invention relates to a multi-mode resonator comprising: a housing in which a cavity corresponding to a substantially single accommodating space is arranged; and multiple resonance ribs which are arranged at a predetermined interval therebetween in the cavity, have lower ends fixed to a floor surface of the housing, have upper ends facing each other, and generate a resonance signal by multiple coupling therebetween.
US10109900B2 Battery management apparatus and battery management method
A battery management apparatus for a battery including battery units, the apparatus including a voltage sensor configured to sense a voltage of each of the battery units; a phase difference calculator configured to calculate a phase difference between the voltage of each of the battery units and a reference voltage; and a temperature controller configured to control a temperature of each of the battery units based on the calculated phase difference.
US10109899B1 Control of current in parallel battery strings
A battery assembly has a first battery string including a first plurality of cells connected in series. A second battery string is connected in parallel to the first battery string and includes a second plurality of cells connected in series. A fluid channel is operatively connected to the first and the second battery strings and includes a fluid flowing within. A controller is operatively connected to the first and the second battery strings. The controller is configured to determine a desired temperature differential between the first and the second temperatures of the battery strings based at least partially on a respective strength status of the first and the second battery strings. The controller is configured to control the first and the second currents, via the fluid in the fluid channel, based at least partially on the desired temperature differential.
US10109896B2 Heat insulating member and battery cover
A heat insulating member includes a wall member. The wall member includes a high-density portion provided at one end edge in a direction orthogonal to a thickness direction of the wall member and having density of above 0.45 g/cm3 and a low-density portion provided midway in the direction orthogonal to the thickness direction, having heat-insulating properties, and having density of 0.45 g/cm3 or less. The high-density portion is provided over the entire one end edge and the thickness of the high-density portion is thinner than that of the low-density portion.
US10109891B2 Lithium battery
A lithium battery including a positive electrode, a negative electrode containing lithium, and a non-aqueous electrolyte having lithium ion conductivity. The positive electrode includes at least one of a manganese oxide and a fluorinated graphite. A powdery or fibrous carbon material adheres to at least part of a surface of the negative electrode, the surface facing the positive electrode. The non-aqueous electrolyte includes a non-aqueous solvent, a solute, and an additive. The solute includes LiClO4, and the additive is LiBF4. The ratio of LiBF4 is, for example, 1 to 100 parts by mass, relative to 100 parts by mass of the solute.
US10109888B2 Serviceable battery pack
A fail safe battery pack is disclosed and claimed wherein first and second housings are affixed together. A plurality of battery cells reside within and fixedly engage the first and the second housings. First and second printed circuit boards (PCBs) reside within first and second lattice structures of the first and second housings. A variable bias device resides in the first and/or second lattice structure of the first and second housing and engages the first and/or second PCBs. When the bias of the variable bias device is sufficiently large it overcomes a plurality of fixed mechanically biased devices operating between the PCB and the plurality of battery cells and tending to separate same and causes the PCB to electrically communicate with the plurality of battery cells. When the bias of the variable bias device is sufficiently small, the plurality of fixed mechanically biased devices separates the PCB and the plurality of battery cells rendering the battery cells in an electrically safe condition.
US10109886B2 Lithium-sulfur batteries
A lithium-sulfur electrochemical cell includes a cathode including elemental sulfur; an anode including elemental lithium; and an electrolyte including a salt and a non-polar fluorinated ether solvent. Alternatively, a lithium-sulfur electrochemical cell may include an anode; an electrolyte; and a cathode including a polytetrafluoroethylene-coated carbon paper and sulfur.
US10109885B2 Complex electrolytes and other compositions for metal-ion batteries
Batteries such as Li-ion batteries are provided that comprise anode and cathode electrodes, an electrolyte ionically coupling the anode and the cathode, and a separator electrically separating the anode and the cathode. In some designs, the electrolyte may comprise, for example, a mixture of (i) a Li-ion salt with (ii) at least one other metal salt having a metal with a standard reduction potential below −2.3 V vs. Standard Hydrogen Electrode (SHE). In other designs, the electrolyte may be disposed in conjunction with an electrolyte solvent that comprises, for example, about 10 to about 100 wt. % ether. In still other designs, the battery may further comprise anode and cathode interfacial layers (e.g., solid electrolyte interphase (SEI)) disposed between the respective electrode and the electrolyte and having different types of fragments of electrolyte solvent molecules as compared to each other.
US10109884B2 Non-aqueous electrolyte secondary battery
A non-aqueous electrolyte secondary battery is capable of suppressing a local reaction of a negative electrode active material due to the electrolyte during charging and discharging and improving a capacity retention ratio of a using a carbon material such as artificial graphite particles for the negative electrode active material. The non-aqueous electrolyte secondary battery includes a negative electrode containing a carbon-based negative electrode active material, an electrolyte layer, and a positive electrode containing a positive electrode active material, and having a tap density of the negative electrode active material of 0.96 g/cc or more.
US10109881B2 Secondary battery and method of manufacturing the same
A secondary battery and method of manufacturing the same are disclosed. In one aspect, the secondary battery includes an electrode assembly including a first current collector, a second current collector, and an isolation layer interposed between the first and second current collectors, the first current collector, the second current collector, and the isolation layer being wound, each of the first and second current collectors including a body portion and an extension portion extending from the body portion, and the extension portions of the first and second current collectors extending in substantially opposite directions. The battery also includes a first auxiliary current collector formed over the electrode assembly and electrically connected to the extension portion of the first current collector. The battery further includes a second auxiliary current collector formed below the electrode assembly and electrically connected to the extension portion of the second current collector.
US10109875B2 Fuel cell system and desulfurization system
One embodiment of the present invention is a unique fuel cell system. Another embodiment is a unique desulfurization system. Yet another embodiment is a method of operating a fuel cell system. Other embodiments include apparatuses, systems, devices, hardware, methods, and combinations for fuel cell systems and desulfurization systems. Further embodiments, forms, features, aspects, benefits, and advantages of the present application will become apparent from the description and figures provided herewith.
US10109871B2 Method of forming a bipolar separator assembly
A method of forming a bipolar separator assembly for use in a fuel cell assembly includes a step of forming an anode-side sub-assembly, which comprises sub-steps of: providing an anode current collector, providing a plate member, first and second opposing end segments and third and fourth opposing end segments, positioning said plate member so that said anode current collector abuts the first surface of the plate member, providing first and second anode wet seal members, and releasably securing the first and second anode wet seal members to the plate member; a step of forming a cathode-side sub-assembly, which comprises sub-steps of: providing a cathode current collector; providing first and second cathode wet seal members; and releasably securing the first and second cathode wet seal members to the cathode current collector; and a step of assembling the cathode-side sub-assembly with the anode-side sub-assembly.
US10109868B2 Gas channel forming plate for fuel cell and fuel cell stack
A gas channel forming plate includes protrusions, which extend parallel with each other, gas channels that are respectively located between each adjacent pair of the protrusions, and water channels, which are respectively formed on the back surface of each protrusion. Each protrusion includes first communication portions and second communication portions. Each first communication portion includes a first opening. Each second communication portion includes a second opening. The second communication portions of each protrusion constitute an expanding region, in which the opening area of the second opening in each second communication portion is greater than the opening area of the first opening of each first communication portion, to limit introduction of water to the water channel on the back side of the protrusion using capillary action by the second communication portions.
US10109867B2 Solid oxide fuel cell with flexible fuel rod support structure
A rod assembly and method for supporting rods includes opposing end plates for supporting opposing ends of a plurality of solid oxide fuel cell rods with each rod comprising a hollow gas conduit passing there through. Each rod end is supported by an annular flexure configured to provide a gas/liquid tight seal between the rod ends and the end plates. Each annular flexure includes a flexible portion surrounding the rod end such that forces imparted to either or both of the rod and the end plate act to elastically deform the annular flexure without damaging the rods. The rod assembly operates and a Solid Oxide Fuel Cell (SOFC) with operating temperatures of 500 to 1000° C.
US10109864B2 Diatomaceous energy storage devices
An energy storage device can include a cathode having a first plurality of frustules, where the first plurality of frustules can include nanostructures having an oxide of manganese. The energy storage device can include an anode comprising a second plurality of frustules, where the second plurality of frustules can include nanostructures having zinc oxide. A frustule can have a plurality of nanostructures on at least one surface, where the plurality of nanostructures can include an oxide of manganese. A frustule can have a plurality of nanostructures on at least one surface, where the plurality of nanostructures can include zinc oxide. An electrode for an energy storage device includes a plurality of frustules, where each of the plurality of frustules can have a plurality of nanostructures formed on at least one surface.
US10109863B2 Composite binder composition for secondary battery, cathode and lithium battery containing the binder composition
In an aspect, a binder composition, a cathode including the same, and a lithium battery including the cathode, wherein the binder composition includes a first fluorine containing binder including a polar functional group; a second fluorine containing binder not including a polar functional group; and a non-fluorine containing binder including a repeating unit resulting from polymerization of an acryl monomer and a repeating unit resulting from polymerization of an olefin monomer, wherein the first fluorine containing binder is a vinylidene fluoride containing binder is provided.
US10109861B2 Cathode material for lithium-ion secondary battery, cathode for lithium-ion secondary battery, and lithium-ion secondary battery
A cathode material for a lithium-ion secondary battery of the present invention includes central particles represented by LixAyMzPO4 and a carbonaceous film that coats surfaces of the central particles, an average value of R values (I1580/I1360), which are ratios of a peak intensity (I1580) of a spectrum at a frequency band of 1,580±50 cm−1 to a peak intensity (I1360) of the spectrum at a frequency band of 1,360±50 cm−1 in a Raman spectrum analysis, measured at five points is 0.80 or more and 1.10 or less, and a standard deviation of the R values measured at five points is 0.010 or less.
US10109858B1 Method for preparing electrolytic manganese dioxide
Disclosed herein is an improved cathode material prepared from high purity electrolytic manganese dioxide. Also disclosed is a method for preparing high purity MnO2 and converting MnO2 particles to Mn2O3.
US10109855B2 Hydrogen storage alloys
Hydrogen storage alloys comprising a metal oxide containing ≥60 at % oxygen; and/or comprising a metal region adjacent to a boundary region, which boundary region comprises at least one channel; and/or comprising a metal region adjacent to a boundary region, where the boundary region has a length and an average width, where the average width is from about 12 nm to about 1100 nm; and/or comprising a metal oxide zone comprising a metal oxide, which oxide zone is aligned with at least one channel; and/or comprising a Ni/Cr metal oxide have improved electrochemical properties, for instance improved low temperature electrochemical performance.
US10109854B2 Positive electrode active material for nonaqueous electrolyte secondary batteries and nonaqueous electrolyte secondary battery
A positive electrode active material for use in nonaqueous electrolyte secondary batteries. The active material is composed of particles each formed by the gathering of grains that comprises at least one metal element selected from the group consisting of Ta and Nb. One of the particles has a compression fracture strength of 500 MPa or more. The grain diameter in the (110) vector direction of the particles is 100 nm to 300 nm.
US10109851B2 Composite cathode active material, method of preparing the same, and cathode and lithium battery including the composite cathode active material
A composite cathode active material includes a material capable of intercalating or deintercalating lithium; and a solid ion conductor. A cathode and a lithium battery each include the composite cathode active material. A method of preparing a composite cathode active material includes: mixing a core including a cathode active material and a solid ion conductor; and forming a coating layer including the solid ion conductor on the core utilizing a dry method.
US10109850B2 Electrode active material, preparation method thereof, and electrode and lithium battery containing the same
An electrode active material includes a core capable of intercalating and deintercalating lithium; and a surface treatment layer disposed on at least a portion of a surface of the core, wherein the surface treatment layer includes a lithium-free oxide having a spinel structure, and an intensity of an X-ray diffraction peak corresponding to impurity phase of the lithium-free oxide, when measured using Cu—Kα radiation, is at a noise level of an X-ray diffraction spectrum or less.
US10109849B2 Nickel composite hydroxide, cathode active material for non-aqueous electrolyte secondary battery, and methods for producing these
A nickel composite hydroxide having a volume-average particle size of the secondary particles of 8.0 μm to 50.0 μm is obtained, by obtaining a nickel composite hydroxide slurry in a primary crystallization process by providing an aqueous solution having at least a nickel salt and a neutralizer into a reaction vessel while continuously stirring in a state of not containing a complex ion formation agent, and controlling the crystallization reaction so that the ratio of the volume-average particles size of secondary particles with respect to that of the secondary particles finally obtained is 0.2 to 0.6, and producing the nickel composite hydroxide in a secondary crystallization process by continuing the crystallization process while keeping the amount of the obtained slurry constant, continuously removing only the liquid component of the slurry, and performing control so that the slurry has a temperature of 70° C. to 90° C. and a pH value at a standard liquid temperature of 25° C. of 10.0 to 11.0.
US10109847B2 Sulfur-carbon composite material, its application in lithium-sulfur battery and method for preparing said composite material
The present invention provides a sulfur-carbon composite material, said composite material comprising a porous carbon substrate containing both micropores and mesopores and sulfur, wherein the sulfur is only contained in the micropores of the carbon substrate. Moreover, a lithium-sulfur battery with its cathode comprising said sulfur-carbon composite material and the method for preparing such material is also provided.
US10109844B2 Dual weld plug for an electrochemical cell
The present invention is directed to an electrochemical cell having plate electrodes housed inside a mating “clamshell” casing. When mated together, the casing components are form-fitting with respect to the internal battery structure so as to reduce the overall size of the electrochemical package. A header assembly containing both a glass-to-metal seal opening for a terminal lead and an electrolyte fill opening is used in conjunction with the clamshell casing. The electrolyte fill opening is constructed with an elongated opening with at least two different radii. A first and second sealing element is welded within the electrolyte fill opening at different depths within the header to block the flow of electrolyte and form a hermetic seal.
US10109842B2 Battery cell
A battery cell includes: an electrode assembly; a pouch case accommodating the electrode assembly therein; and an electrode lead including an outer lead protruding to an outside of the pouch case and an inner lead disposed between the outer lead and the electrode assembly, accommodated in the pouch case, and cut by expansion force of the pouch case.
US10109840B2 Rechargeable battery pack having a contact plate for connection to a load
A rechargeable battery pack includes at least one individual cell which is accommodated in a cell holder and is in electrical contact on a contact side via a cell connector. An electric load is to be connected via a contact plate which has a plurality of plug-type connections, wherein the contact plate is located on one side face of the cell holder. In order to compensate positional tolerances between the plug-type connections of the contact plate and external connection contacts, a mount for the contact plate is provided on one side face of the cell holder, in which mount the contact plate is mounted so as to be displaceable in a displacement direction. The electrical connection between the individual cell and the contact plate is embodied by an elastic contact strip, wherein the contact strip is embodied so as to be resilient in a sprung fashion in the displacement direction of the contact plate.
US10109837B2 Secondary battery
A secondary battery includes an electrode assembly including a first uncoated portion extending in a first direction, and a second uncoated portion extending in a second direction opposite to the first direction; a case accommodating the electrode assembly; a first terminal extending to an outside of the case and being connected to the first uncoated portion; a first cover plate coupled to the first terminal and closing the case in the first direction, the first terminal being insulated from the case; a connection plate connected between the second uncoated portion and the case; and a second cover plate covering the connection plate and closing the case in the second direction.
US10109833B2 Separator for rechargeable battery and rechargeable battery including the same
A separator for a rechargeable battery includes a porous substrate and a heat-resistance layer on at least one surface of the porous substrate. The heat-resistance layer includes a binder having a cross-linked structure, a sphere-shaped filler, and a plate-shaped filler, and the plate-shaped filler is included in a smaller amount than the sphere-shaped filler in the heat-resistance layer. A rechargeable battery includes the separator.
US10109820B2 Array substrate and manufacturing method thereof, and display device
The present invention discloses an array substrate and a manufacturing method thereof, and a display device, wherein the array substrate comprises a base substrate and an electroluminescent device disposed above the base substrate, the array substrate further comprises an additive layer between the base substrate and the electroluminescent device, with a plurality of protrusions being formed on a contact surface of the additive layer with the electroluminescent device, refractive index of the additive layer being less than or equal to that of the base substrate. Light generated by the electroluminescent device successively transmits through the additive layer and the base substrate so as to exit from the array substrate. In the technical solutions of the present invention, by arranging the additive layer between the base substrate and the electroluminescent device, the total amount of light “refracted” from the electroluminescent device into the base substrate can be effectively increased.
US10109819B2 Light-emitting device
A mirror device has a plurality of organic EL elements and a plurality of metal mirror surface portions that are divided by banks made of a light-transmissive dielectric material and aligned on a substrate. Each of the organic EL elements has an organic layer that is formed between a light-transmissive electrode and a reflection electrode and contains a light-emitting layer. Each of the metal mirror surface portions and each of the organic EL elements or each group of the metal mirror surface portions and each group of the organic EL elements are alternately disposed.
US10109818B2 Plastic substrate
The present application relates to a plastic substrate, a method for producing same, an organic electronic device, and display light source and lighting apparatus. The plastic substrate according to the present application has superb light extraction efficiency and exhibits an excellent surface roughness characteristic. Furthermore, the method for producing the plastic substrate according to the present application can produce the plastic substrate by means of a process in which scattering components are added secondarily. Moreover, the plastic substrate according to the present application can be utilized as a substrate for an organic electronic device, and the organic electronic device can be utilized as display light source and lighting apparatus.
US10109817B2 Organic light emitting device
Disclosed is an organic light emitting device. The organic light emitting device includes a first emission unit configured to include a common blue emission material layer which is included in common in a plurality of pixels emitting lights having different wavelength ranges, a second emission unit configured to include a red emission material layer, a green emission material layer, and a blue emission material layer which respectively emit lights having different wavelength ranges, a charge generation layer disposed between the first emission unit and the second emission unit, a first electrode formed as a reflective electrode, and configured to supply an electric charge having a first polarity to the first emission unit and the second emission unit, and a second electrode formed as a semi-transmissive electrode, and configured to supply an electric charge having a second polarity to the first emission unit and the second emission unit.
US10109809B2 Flexible substrate
A flexible substrate includes a polymer substrate and a plurality of water and oxygen barrier layers provided on the polymer substrate. A planarization layer is provided between the adjacent water and oxygen barrier layers. The planarization layer includes a plurality of planarization units separated in a first direction and a second direction. A projection of the planarization unit in the planarization layer projected on the polymer substrate covers a gap between projections of adjacent planarization units in an adjacent planarization layer projected on the polymer substrate, and projection regions partially overlap. The adjacent planarization layers can cover the gap between the planarization units to prevent the water and oxygen horizontal from penetrating to ensure that the flexible substrate can be cut into any size within the range lager than the size of the planarization unit.
US10109806B2 Organometallic complex, light-emitting element, light-emitting device, electronic appliance, and lighting device
A light-emitting element including a phosphorescent organometallic complex is provided. The organometallic complex emits phosphorescence in the yellow green to orange wavelength range and has high emission efficiency and high reliability. Thus, the organometallic complex that exhibits phosphorescence is provided. The organometallic complex, in which nitrogen at the 3-position of a pyrimidine ring is coordinated to a metal, a carbazole skeleton is bonded to the 4-position of the pyrimidine ring, and the carbazole skeleton is bonded to the metal, is used as an emission center. The metal is preferably a Group 9 element or a Group 10 element, more preferably iridium.
US10109805B2 Organic-inorganic hybrid perovskite nanocrystal particle light emitting body having two-dimensional structure, method for producing same, and light emitting device using same
Provided are an organic-inorganic-hybrid perovskite nanocrystal particle light-emitter having a two-dimensional structure, a method for producing the same, and a light emitting device using the same. The organic-inorganic-hybrid perovskite nanocrystal particle light-emitter having a two-dimensional structure comprises an organic-inorganic-hybrid perovskite nanocrystal structure having a two-dimensional structure which can be dispersed in an organic solvent. Accordingly, the nanocrystal particle light-emitter comprises an organic-inorganic-hybrid perovskite nanocrystal having a crystal structure combining FCC and BCC; forms a lamellar structure where organic planes and inorganic planes are accumulated in an alternating manner; and can exhibit high color purity by confining excitons in the inorganic planes. In addition, since the exciton diffusion distance decreases and exciton binding energy increases, it is possible to prevent exciton annihilation caused by thermal ionization and delocalization of charge carriers, such that the nanocrystal particle light-emitter can have high luminescence efficiency at room temperature.
US10109802B2 Carbazole-based gumbos for highly efficient blue OLEDs
Various examples are provided for carbazole-based GUMBOS (group of uniform materials based on organic salts), and its application in organic light emitting diodes (OLEDs). In one example, a composition includes a solid phase carbazole-based GUMBOS (group of uniform materials based on organic salts) comprising a counterion such as, e.g., trifluoromethanesulfonate ([Otf]), bis-(trifluoromethanesulfonyl)imide ([NTf2]), bis-(pentafluoroethylsulfonyl)imide ([BETI]), tetrafluoroborate (BF4), hexafluorophosphate (PF6), and/or thiocyanate (SCN). The carbazole-based GUMBOS can include carbazoleimidazole-based GUMBOS or 3,6-diBDC carbazolium-based GUMBOS. In another example, a method includes preparing a biphasic solution; separating a layer of DCM from the biphasic solution after stirring; washing the DCM with water to remove byproducts; and evaporating the DCM to form a solid phase carbazoleimidazole-based GUMBOS. Preparing the biphasic solution can include carbazoleimidazolium iodide (CM) dissolved in dichloromethane (DCM) and a dissolved salt including a sodium salt or a lithium salt.
US10109801B2 Compound for organic electric element, organic electric element comprising the same and electronic device thereof
Provided are a compound of Formula 1 and an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and electronic device comprising the organic electric element, wherein the luminous efficiency and life span can be improved and the driving voltage of the organic electronic device can be lowered by comprising the compound represented by Formula 1 in the organic material layer.
US10109800B2 Organic electroluminescent element, display device and lighting device
Disclosed is an organic electroluminescent device having long life, while exhibiting high luminous efficiency. Also disclosed are an illuminating device and a display, each using such an organic electroluminescent device. In the organic electroluminescent device, a compound represented by the general formula (A) which is suitable as a host material for a phosphorescent metal complex is used at least in one sublayer of a light-emitting layer.
US10109797B2 Method of fabricating display device
A display device includes a display area, a test pad, a plurality of first test transistors, and at least one outline. The display area includes pixels coupled to data lines and scan lines. The test pad receives a test signal. The first test transistors are coupled between the data lines of the display area and the test pad. The at least one outline is coupled between one of the first test transistors and the test pad. The at least one outline is located in a non-display area outside the display area.
US10109792B2 Switching device and resistive random access memory including the same
A switching device includes a first electrode and a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. The electrolyte layer includes a first layer charged with negative charges and a second layer charged with positive charges.
US10109791B2 Nonvolatile memory device and method of fabricating the same
The nonvolatile memory device includes a semiconductor substrate, a first and a second diffusion regions formed under a surface of the semiconductor substrate, a storage layer formed on the semiconductor substrate, a gate stacked on the storage layer, wherein the first diffusion region may at least one of active regions being separated by a part of the semiconductor substrate forming a channel region, wherein the second diffusion region may include an active region intersecting the gate insulating layer, wherein the storage layer may include an insulating layer or a variable resistor, and may service as a data storage layer to store data, and may be selected by a structure including the first and the second diffusion regions.
US10109790B2 Method for manufacturing mixed-dimension and void-free MRAM structure
A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.
US10109789B2 Methods for additive formation of a STT MRAM stack
Disclosed herein are methods for additive formation of a STT-MRAM metal stack using a deposition process through a pre-patterned template that skims away metal ions that are less likely to enable anisotropic deposition on a substrate. The pre-patterned template is formed from a film stack using patterning techniques to form an opening in the film stack that exposes portions of an underlying substrate where a MTJ will be formed for an MRAM cell. The film stack cavity may be exposed to etch processes that selectively pull back the sidewall, such that other layers in the film stack protrude into the cavity. Additional treatments to the other layers may alter the opening sizes in the other layers. Metal deposited through the cavity such that metal ions with anisotropic characteristics will be skimmed away before reaching the substrate.
US10109787B2 Well-based vertical hall element with enhanced magnetic sensitivity
A vertical Hall element and method of fabricating are disclosed. The method includes forming a buried region having a first conductivity type in a substrate having a second conductivity type and implanting a dopant of the first conductivity type into a well region between the top surface of the substrate and the buried region. The buried region has a doping concentration increasing with an increasing depth from a top surface of the substrate and the well region has a doping concentration decreasing from the top surface of the substrate to the buried region. The method includes forming first through fifth contacts on the well region. First and second contacts define a conductive path and second and third contacts define another conductive path through the well region. The fourth contact is formed between first and second contacts and the fifth contact is formed between second and third contacts.
US10109782B2 Piezoelectric element and piezoelectric actuator
A piezoelectric element includes a piezoelectric body, an external electrode, and an internal electrode. The piezoelectric body includes first and second main surfaces opposing each other. The external electrode is disposed on the first main surface and has a first polarity. The internal electrode is disposed in the piezoelectric body to oppose the external electrode in a direction in which the first main surface and the second main surface oppose each other and has a second polarity different from the first polarity. A region from the internal electrode to the external electrode in the piezoelectric body is a polarizing region, and a region from the internal electrode to the second main surface in the piezoelectric body is a non-polarizing region.
US10109776B2 Light emitting device having curved light emitting element
A light emitting device includes a substrate, a light emitting element, and an insulating resin member. The light emitting element has an upper surface and a lower surface opposite to the upper surface and is provided on the substrate so that the lower surface faces the substrate. The insulating resin member is provided between the light emitting element and the substrate and includes a first resin member and a second resin member. The first resin member is provided in a first region. The second resin member is provided in a second region different from the first region and has hardness different from hardness of the first resin member. A height from the substrate to the upper surface of the light emitting element facing the first resin member is different from a height from the substrate to the upper surface of the light emitting element facing the second resin member.
US10109770B2 Method for manufacturing light emitting diode
A light emitting diode includes a first electrode, a second electrode, and an epitaxial structure. The epitaxial structure is arranged on the first electrode, and electrically connects with the first electrode and the second electrode. The second electrode surrounds periphery of the epitaxial structure to reflect light from the epitaxial structure out from the top of the epitaxial structure. A method for manufacturing the light emitting diode is also presented. The light emitting diode and the method increase lighting efficiency of the light emitting diode.
US10109767B2 Method of growing n-type nitride semiconductor, light emitting diode and method of fabricating the same
A light emitting diode includes: an n-type nitride semiconductor layer; an active layer over the n-type nitride semiconductor layer; and a p-type nitride semiconductor layer over the active layer. The n-type nitride semiconductor layer includes: an n-type nitride layer; a first intermediate layer over the n-type nitride layer; an n-type modulation-doped layer over the first intermediate layer. The light emitting diodes includes a second intermediate layer over the n-type modulation-doped layer. The second intermediate layer includes a sub-layer having a higher n-type doping concentration that an n-type doping concentration of the n-type modulation-doped layer.
US10109766B2 Light emitting device and method for manufacturing same
A light-emitting device includes lead frames, a light-emitting element placed on a bottom of a recessed portion formed at one of the lead frames, and a light-transmitting resin covering the light-emitting element. The lead frames have a covered region which is covered with the light-transmitting resin and an exposed region exposed out of the light-transmitting resin. The light-emitting device has a gap between the lead frame and the light-transmitting resin at an inner side surface of the recessed portion, the gap having a width longer than a main wavelength of light from the light-emitting element. The lead frame is in close contact with the light-transmitting resin at an end of the covered region, which is located in a boundary with the exposed region or in the vicinity of the boundary within the covered region.
US10109762B2 Light source and optical coherence tomography apparatus including the light source
A light source includes an upper electrode layer, a lower electrode layer, and an active layer interposed therebetween. At least one of the upper and lower electrode layers is divided into a plurality of electrodes separated from each other in an in-plane direction of the active layer. The separated electrodes independently inject current into a plurality of different regions in the active layer. The light source emits light by injecting current from the upper and lower electrode layers into the active layer, guide the light in the in-plane direction, and output the light. The plurality of different regions in the active layer include a first region not including a light exit end and a second region including the light exit end, and the second region is configured to emit light of at least first-order level. The active layer has an asymmetric multiple quantum well structure.
US10109757B2 Solar cell system
A solar cell system includes a number of P-N junction cells, a number of inner electrodes, a first collecting electrode, a second collecting electrode and a reflector. The number of the P-N junction cells is M. M is equal to or greater than 2. The M P-N junction cells are arranged from a first P-N junction cell to an Mth P-N junction cell along the straight line. The P-N junction cells are arranged in series along a straight line. The number of the inner electrodes is M−1. At least one inner electrode includes a plurality of carbon nanotubes. A photoreceptive surface is parallel to the straight line. A reflector is located on an emitting surface opposite to the photoreceptive surface.
US10109755B2 Capping layers for improved crystallization
Techniques for fabrication of kesterite Cu—Zn—Sn—(Se,S) films and improved photovoltaic devices based on these films are provided. In one aspect, a method of fabricating a kesterite film having a formula Cu2−xZn1+ySn(S1−zSez)4+q, wherein 0≤x≤1; 0≤y≤1; 0≤z≤1; and −1≤q≤1 is provided. The method includes the following steps. A substrate is provided. A bulk precursor layer is formed on the substrate, the bulk precursor layer comprising Cu, Zn, Sn and at least one of S and Se. A capping layer is formed on the bulk precursor layer, the capping layer comprising at least one of Sn, S and Se. The bulk precursor layer and the capping layer are annealed under conditions sufficient to produce the kesterite film having values of x, y, z and q for any given part of the film that deviate from average values of x, y, z and q throughout the film by less than 20 percent.
US10109753B2 Compound micro-transfer-printed optical filter device
Embodiments of the present invention provide a compound optical filter device comprising a semiconductor substrate having an optical transducer formed on the semiconductor substrate, the optical transducer responsive to light to produce a signal or responsive to a signal to emit light. An optical filter comprises a filter substrate separate and independent from the semiconductor substrate and one or more optical filter layers disposed on the filter substrate. The filter substrate is micro-transfer printed on or over the semiconductor substrate or on layers formed over the semiconductor substrate and over the optical transducer to optically filter the light to which the optical transducer is responsive or to optically filter the light emitted by the optical transducer. In further embodiments, the optical filter is an interference filter and the semiconductor substrate includes active components that can control or operate the optical transducer.
US10109752B2 Nanowire-modified graphene and methods of making and using same
A transparent electrode can include a graphene sheet on a substrate, a layer including a conductive polymer disposed over the graphene sheet, and a plurality of semiconducting nanowires, such as ZnO nanowires, disposed over the layer including the conductive polymer.
US10109748B2 High-mobility multiple-gate transistor with improved on-to-off current ratio
A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region.
US10109747B2 Semiconductor memory devices and methods of fabricating the same
A semiconductor memory device and a method of fabricating the same. The device includes a plurality of gates vertically stacked on a top surface of a substrate with an epitaxial layer formed in the substrate, a vertical channel vertically penetrating the gates to be electrically connected to the epitaxial layer, and a memory layer provided between the vertical channel and the gates. The epitaxial layer has a top surface positioned at a level between a bottom surface of the lowermost one of the gates and the top surface of the substrate.
US10109746B2 Graphene transistor and ternary logic device using the same
Disclosed is a graphene transistor using graphene as a channel region and a logic device using the same. A doping metal layer is provided over a graphene channel of the graphene transistor. The doping metal layer has a work function higher or lower than that of the graphene. When the doping metal layer has a work function lower than that of the graphene, the graphene, which is below the doping metal layer, is doped with an n-type. Also, when the doping metal layer has a work function higher than that of the graphene, the graphene, which is below the doping metal layer, is doped with a p-type. As described above, various aspects of junction may be implemented in the graphene channel, and three states may be obtained from a single transistor.
US10109745B2 Method of manufacturing flexible display
A method of manufacturing a flexible display is disclosed. In one aspect, the method includes attaching a protective film to a flexible display panel. The flexible display panel includes a bending region along which the flexible display panel is configured to be bent. The method also includes removing a portion of the protective film that corresponds to the bending region and bending the flexible display panel along the bending region.
US10109743B2 Oxide semiconductor film, semiconductor device, and manufacturing method of semiconductor device
A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used. In a transistor using an oxide semiconductor film for an active layer, a microvoid is provided in a source region and a drain region adjacent to a channel region. By providing a microvoid in the source region and the drain region formed in an oxide semiconductor film, hydrogen contained in the channel region of an oxide semiconductor film can be captured in the microvoid.
US10109742B2 Semiconductor device including fin structures and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a fin structure over a substrate. The fin structure has a top surface and side surfaces and the top surface is located at a height H0 measured from the substrate. An insulating layer is formed over the fin structure and the substrate. In the first recessing, the insulating layer is recessed to a height T1 from the substrate, so that an upper portion of the fin structure is exposed from the insulating layer. A semiconductor layer is formed over the exposed upper portion. After forming the semiconductor layer, in the second recessing, the insulating layer is recessed to a height T2 from the substrate, so that a middle portion of the fin structure is exposed from the insulating layer. A gate structure is formed over the upper portion with the semiconductor layer and the exposed middle portion of the fin structure.
US10109736B2 Superlattice buffer structure for gallium nitride transistors
A transistor with a multi-strained layer superlattice (SLS) structure is provided. A first strained layer superlattice (SLS) layer is arranged over a substrate. A first buffer layer is arranged over the first SLS layer and includes dopants configured to increase a resistance of the first buffer layer. A second SLS layer is arranged over the first buffer layer. A second buffer layer is arranged over the second SLS layer and includes dopants configured to increase a resistance of the second buffer layer. A channel layer is arranged over the second buffer layer. An active layer is arranged over and directly abuts the channel layer. The channel and active layers collectively define a heterojunction. A method for manufacturing the transistor is also provided.
US10109733B2 Semiconductor device for power transistor
In a semiconductor device, in a gate insulating film which is formed on/over an inner wall of a trench, the film thickness of a part of a gate insulating film formed so as to cover a corner of the trench is made thicker than the film thickness of a part of the gate insulating film part formed on/over a side face of the trench.
US10109731B2 Power MOSFET and method for manufacturing the same
A power MOSFET includes an insulating layer, a first conductivity type doping layer situated on a bottom of the insulating layer, a second conductivity type body situated on a bottom of the first conductivity type doping layer, a gate electrode adjacent to the bottom of the insulating layer and covered with an insulating film in other regions and projected to penetrate the second conductivity type body, and a source electrode including a first region situated on a top of the insulating layer and a second region in contact with the first conductivity type doping layer by penetrating the insulating layer.
US10109727B2 Semiconductor device
A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer and an AlGaN layer and is formed with a recessed portion, on the substrate; a gate structure part that includes a gate insulating film and a gate electrode formed in the recessed portion; and a source electrode and a drain electrode on opposite sides of the gate structure part on the channel forming layer. The AlGaN layer includes a first AlGaN layer that has an Al mixed crystal ratio determining a two dimensional electron gas density, and a second AlGaN layer that has an Al mixed crystal ratio smaller than that of the first AlGaN layer to induce negative fixed charge, and is disposed in contact with the gate structure part and spaced from the source electrode and the drain electrode.
US10109722B2 Etch-resistant spacer formation on gate structure
The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.
US10109721B2 Horizontal gate-all-around device having wrapped-around source and drain
Various semiconductor devices, such as horizontal gate-all-around devices, and methods of fabricating such are disclosed herein. An exemplary semiconductor device includes a fin structure having a channel region disposed between a first source/drain region and a second source/drain region. The fin structure includes a first nanowire and a second nanowire disposed in the channel region, the first source/drain region, and the second source/drain region. The fin structure further includes an epitaxial layer that wraps the first nanowire and the second nanowire in the first source/drain region and the second source/drain region. A gate is disposed over the channel region of the fin structure, such that the gate wraps the first nanowire and the second nanowire in the channel region. In some implementations, the first nanowire, the second nanowire, and the epitaxial layer combine to have a vertical bar-like shape in the first source/drain region and the second source/drain region.
US10109718B2 Method for manufacturing a semiconductor device
A semiconductor component and a method for manufacturing the semiconductor component, wherein the semiconductor component includes a transient voltage suppression structure that includes at least two diodes and a Zener diode. In accordance with embodiments, a semiconductor material is provided that includes an epitaxial layer. The at least two diodes and the Zener diode are created at the surface of the epitaxial layer, where the at least two diodes may be adjacent to the Zener diode.
US10109716B2 Turnable breakdown voltage RF FET devices
A tunable breakdown voltage RF MESFET and/or MOSFET and methods of manufacture are disclosed. The method includes forming a first line and a second line on an underlying gate dielectric material. The second line has a width tuned to a breakdown voltage. The method further includes forming sidewall spacers on sidewalls of the first and second line such that the space between first and second line is pinched-off by the dielectric spacers. The method further includes forming source and drain regions adjacent outer edges of the first line and the second line, and removing at least the second line to form an opening between the sidewall spacers of the second line and to expose the underlying gate dielectric material. The method further includes depositing a layer of material on the underlying gate dielectric material within the opening, and forming contacts to a gate structure and the source and drain regions.
US10109713B2 Fabrication of single or multiple gate field plates
A process for fabricating single or multiple gate field plates using consecutive steps of dielectric material deposition/growth, dielectric material etch and metal evaporation on the surface of a field effect transistors. This fabrication process permits a tight control on the field plate operation since dielectric material deposition/growth is typically a well controllable process. Moreover, the dielectric material deposited on the device surface does not need to be removed from the device intrinsic regions: this essentially enables the realization of field-plated devices without the need of low-damage dielectric material dry/wet etches. Using multiple gate field plates also reduces gate resistance by multiple connections, thus improving performances of large periphery and/or sub-micron gate devices.
US10109711B2 CMOS FinFET device having strained SiGe fins and a strained Si cladding layer on the NMOS channel
Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
US10109710B2 Semiconductor device having germanium layer as channel region and method for manufacturing the same
A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
US10109703B2 Display device
A display device having a display region and a peripheral region in contact with the display region above a substrate is provided. The display region has a plurality of pixels each including a transistor, an insulating film above the transistor, a pixel electrode arranged above the insulating film and electrically connected to the transistor, and a common electrode above the insulating film, a video signal line and a gate signal line electrically connected to the transistor, and liquid crystal layer above the plurality of pixels. The peripheral region has a terminal electrically connected to the video signal line, a wiring arranged parallel to the gate wiring between the display region and the terminal, and a plurality of first electrodes above the wiring. The insulating film covers the wiring, and the wiring is electrically connected to the plurality of first electrodes via an opening in the insulating film.
US10109701B2 Organic EL display device
An organic EL display device includes: a lower electrode; an upper electrode; a first organic layer which is disposed between the lower electrode and the upper electrode and is formed of a plurality of layers including a light emitting layer formed of an organic material that emits light; a metal wire that extends between the pixels within the display region; and a second organic layer which is formed of a plurality of layers the same as that of the first organic layer and which comes into contact with a part of the metal wire and does not come into contact with the first organic layer. The upper electrode comes into contact with the metal wire in the periphery of the second organic layer. Accordingly, it is possible to uniformize the potential of the upper electrode without reducing the light emission area.
US10109700B2 Organic light emitting display device and method of manufacturing the same
Discussed are an organic light emitting display device and a method of manufacturing the same. The organic light emitting display device according to an embodiment includes a substrate including an active area and a pad area, a thin film transistor (TFT) in the active area of the substrate, an anode electrode on the TFT, an organic emission layer on the anode electrode, a cathode electrode on the organic emission layer, an auxiliary electrode connected to the cathode electrode and disposed on the same layer as the anode electrode, a signal pad in the pad area of the substrate, and a pad electrode connected to the signal pad to cover a top of the signal pad for preventing the top of the signal pad from being corroded. The TFT includes a gate electrode. The signal pad is disposed on the same layer as the gate electrode.
US10109697B2 Display module
Organic EL display module including a pixel disposed in respective intersections between a plurality of scanning lines and a plurality of data lines, which lines are aligned in a matrix, and a current supply line that supplies electric current to the pixel, wherein the pixel includes an active device selected by the scanning line, a data storage device that stores a data signal that is supplied from the data line by control of the active device, and an organic light emitting device that emits light by the electric current supplied by the current supply line according to the data signal stored in the data storage device, wherein the data storage device provides a lower electrode, an insulating layer and an upper electrode, and wherein the lower electrode has a same layer with a channel layer of the active device and the upper electrode is made of a metal material.
US10109687B2 Display device with touch sensor
A sealing member containing conductive particles and disposed in a seal region is formed between a display panel and a touch panel. A laminated structure formed on the display panel includes a first detection lines. The first detection lines extend from the seal region to a connection region and are connected through the conductive particles to terminals of second detection lines formed on the touch panel. A peripheral edge of the organic barrier is located inward from the conductive particles of the sealing member. The above described structure can facilitate a work for connecting external lines such as FPC to the display panel and the touch panel. Further, the structure can secure stability of electrical connection between the external lines and the touch panel.
US10109685B2 Organic light emitting display
An organic light emitting display including a substrate, a first electrode and a second electrode on the substrate and facing each other, at least two organic light emitting layers between the first electrode and the second electrode, and at least two color filters on the second electrode, the organic light emitting layers emitting a first color light, and the color filters emitting a second color light and a third color light.
US10109682B2 Production of transistor arrays
A method of producing a transistor array, comprising an array of addressing conductors each providing the source electrodes of a respective set of transistors and at least part of a conductive connection between a respective driver terminal and said source electrodes; wherein the method comprises: forming a conductor layer on a support; and displacing a plurality of portions of said conductor layer relative to other portions of said conductor layer to create from said conductor layer at least (i) said array of addressing conductors and an array of drain conductors at said first level, (ii) conductor element islands in transistor channel regions at a second level, and (iii) one or more further conductor elements at a third level.
US10109681B2 Vertical memory structure with array interconnects and method for producing the same
Disclosed herein is a method and apparatus for fabricating a memory device. The memory device has a vertical stack of alternating layers of conductive and insulating layers wherein a top layer and a bottom layer are insulating layers. A plurality of vias is formed through the vertical stack from the top layer to the bottom layer. A memory layer disposed adjacent the conductive layers in the vias. A selector device disposed adjacent the memory layer wherein the selector device comprises multiple layers of dissimilar metal oxides. A lateral electrical contact to the memory layer through the conductive layer. And a top contact electrically connected to the conductive layer through a portion of the memory layer and the portion of the memory layer wherein the portion of the memory layer is configured to store data therein.
US10109680B1 Methods and apparatus for three-dimensional nonvolatile memory
A method is provided that includes forming a word line above a substrate, forming a bit line above the substrate, forming a nonvolatile memory material between the word line and the bit line, the nonvolatile memory material including a semiconductor material layer and a conductive oxide material layer, forming a barrier material layer between the semiconductor material layer and the conductive oxide material layer, and forming a memory cell including the nonvolatile memory material at an intersection of the bit line and the word line. The word line is disposed in a first direction, the bit line is disposed in a second direction perpendicular to the first direction. The barrier material layer has an ionic conductivity of greater than about 0.1 Siemens/cm @ 1000° C.
US10109674B2 Semiconductor metallization structure
A method of fabrication of a device includes forming a first metallization layer that is coupled to a logic device of the device. The method further includes forming a second metallization layer that is coupled to a magnetoresistive random access memory (MRAM) module of the device. The second metallization layer is independent of the first metallization layer.
US10109670B2 Optical sensor having a curved detection surface
An optical detector with a curved detection surface is provided, including a photosensitive sensor; a support imposing a curvature on the photosensitive sensor; and a glue layer, provided between the photosensitive sensor and the support, with a thickness higher than 50 μm. The glue layer with a high thickness enables requirements imposed on the sensor to be reduced, with an equal radius of curvature, and thus a minimum radius of curvature of the photosensitive sensor to be reduced, thereby compensating for significant defects of an imaging system located upstream.
US10109669B2 Solid-state imaging device and electronic apparatus
The present technology relates to a solid-state imaging device and an electronic apparatus that perform a stable overflow from a photodiode and prevent Qs from decreasing and color mixing from occurring. A solid-state imaging device according to an aspect of the present technology includes, at a light receiving surface side of a semiconductor substrate, a charge retention part that generates and retains a charge in response to incident light, an OFD into which the charge saturated at the charge retention part is discharged, and a potential barrier that becomes a barrier of the charge that flows from the charge retention part to the OFD, the OFD including a low concentration OFD and a high concentration OFD having different impurity concentrations of the same type, and the high concentration OFD and the potential barrier being formed at a distance. For example, the present technology is applicable to a CMOS image sensor.
US10109666B2 Pad structure for backside illuminated (BSI) image sensors
A pad structure with a contact via array for high bond structure is provided. In some embodiments, a semiconductor substrate comprises a pad opening. An interconnect structure is under the semiconductor substrate, and comprises an interlayer dielectric (ILD) layer, a wiring layer, and the contact via array. The wiring layer and the contact via array are in the ILD layer. Further, the contact via array borders the wiring layer and is between the wiring layer and the semiconductor substrate. A pad covers the contact via array in the pad opening, and protrudes into the ILD layer to contact the wiring layer on opposite sides of the contact via array. A method for manufacturing the pad structure, as well as an image sensor with the pad structure, are also provided.
US10109658B2 LED chip mounting apparatus and method of manufacturing display apparatus by using the LED chip mounting apparatus
A light emitting diode chip mounting apparatus includes a guide plate including a first surface and a second surface opposite to the first surface, the second surface including at least one first tunnel that extends in a first direction, wherein the first tunnel defines a concave portion and the second surface includes a convex portion adjacent to the concave portion. The first tunnel is sized to accommodate a light emitting diode chip flowing therethrough.
US10109657B2 Display device
A display device may include a light shield layer on a first substrate; a buffer layer on the light shield layer; a semiconductor layer on the buffer layer; a first insulating layer on the semiconductor layer; a gate metal layer on the first insulating layer; a second insulating layer having a contact hole on the gate metal layer and exposing a portion of the gate metal layer; and a source drain metal layer on the second insulating layer and in contact with the gate metal layer through the contact hole, wherein the semiconductor layer includes an auxiliary contact hole located in an area corresponding to the contact hole.
US10109653B2 Array substrate, manufacturing method thereof and display device
An array substrate, a manufacturing method thereof and a display device are provided. The array substrate includes: a base substrate; a thin-film transistor and a first conductive layer formed on the base substrate; and a passivation layer formed on the TFT and the first conductive layer. The TFT includes a source electrode and a drain electrode; the first conductive layer is arranged in the same layer with the source electrode and the drain electrode; a second conductive layer is disposed on a side of the first conductive layer opposite to the passivation layer; the passivation layer is provided with a through hole penetrating therethrough; and an orthographic projection of the through hole on the base substrate falls within an orthographic projection of the first conductive layer on the base substrate and falls within an orthographic projection of the second conductive layer on the base substrate.
US10109649B2 Organic light-emitting display apparatus for improving an adhesion of a sealing member
An organic light-emitting display apparatus includes a first substrate corresponding to a display area and a periphery area, a second substrate facing the first substrate, a first metal layer at the periphery area of the first substrate, and defining a plurality of first holes, a second metal layer on the first metal layer, and defining a plurality of second holes that are differently sized than the first holes, a third metal layer on the second metal layer, and defining a plurality of third holes that are differently sized than the second holes, and a sealing member bonding the first substrate and the second substrate, and filling a partial region of the first, second, and third holes.
US10109648B2 Semiconductor layer structure
The present disclosure a semiconductor layer structure having an insulating substrate and a semiconductor layer formed on the insulating substrate. The semiconductor layer includes a source signal access terminal, a drain signal access terminal, a first semiconductor layer pattern and a second semiconductor layer pattern; the first semiconductor layer pattern and the second semiconductor layer pattern formed between the source signal access terminal and the drain signal access terminal in parallel. The present disclosure also provides a method for fabricating a semiconductor layer structure.
US10109647B2 MOTFT with un-patterned etch-stop
A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.
US10109645B2 Semiconductor devices
A semiconductor device includes a first device isolation layer defining active regions spaced apart from each other along a first direction on a substrate, second device isolation layers defining a plurality of active patterns protruding from the substrate, the second device isolation layers extending in the first direction to be spaced apart from each other in a second direction and connected to the first device isolation layer, a gate structure extending in the second direction on the first device isolation layer between the active regions, a top surface of the second device isolation layer being lower than a top surface of the active pattern, a top surface of the first device isolation layer being higher than the top surface of the active pattern, and at least part of a bottom surface of the gate structure being higher than the top surface of the active pattern.
US10109644B2 Memory device
In one embodiment, the semiconductor device includes a substrate having an impurity region, and the substrate and the impurity region have a different impurity characteristic. The semiconductor device further includes a stack of alternating first interlayer insulating layers and gate electrode layers on the substrate; at least one second interlayer insulating layer formed on the stack; a plurality of bit lines formed on the second interlayer insulating layer; and a first plurality of channel structures formed through the stack on the substrate. The first plurality of channel structures are electrically connected to respective ones of the plurality of bit lines. A second plurality of channel structures are formed through the stack on the impurity region, and the second plurality of channel structures are electrically insulated from the plurality of bit lines.
US10109637B1 Cross couple structure for vertical transistors
The disclosure provides integrated circuit (IC) structure including: a substrate; a shallow trench isolation (STI) positioned between the first and second regions of the substrate; a first transistor with a channel region is positioned on the first region of the substrate, and spacer positioned on the first region of the substrate and the STI; and a gate metal positioned on the spacer. The gate metal includes a gate contact region positioned over the first source/drain region of the substrate, and surrounding the channel region. Across-couple region extends laterally from the gate contact region to the source/drain region of a second transistor formed on the second region of the substrate.
US10109636B2 Active contact and gate contact interconnect for mitigating adjacent gate electrode shortages
A method of forming an active contact-gate contact interconnect including forming a first gate contact to a first gate electrode in an active region in a substrate, forming a first active contact to another portion of the first active region. The first gate contact and the first active contact include an approximately equal surface area, and forming an interconnect between the first active contact and the first gate contact. The interconnect includes a first metal wire in a first metal layer electrically connecting the first active contact to the first gate contact. The method may also include forming a second metal wire in the first metal layer configured to electrically connect a third metal wire in a second metal layer to an external contact to a second active region in the substrate, the external contact including the approximately equal surface area.
US10109634B2 Semiconductor device having air gap and method for manufacturing the same, memory cell having the same and electronic device having the same
A method for fabricating a semiconductor device may include: forming a plurality of first isolation trenches and a plurality of line-shaped active regions by etching a semiconductor substrate; forming a line-shaped device isolation region in each of the plurality of first isolation trenches; forming a plurality of second isolation trenches extending in a second direction by etching the plurality of line-shaped active regions and the plurality of line-shaped device isolation regions; forming a connection trench to connect the plurality of second isolation trenches to each other; forming a shielding line in each of the plurality of second isolation trenches; and forming a shielding line interconnection in the connection trench.
US10109632B2 Semiconductor device and manufacturing method of the same
A semiconductor device includes a buffer layer formed with a semiconductor adapted to produce piezoelectric polarization, and a channel layer stacked on the buffer layer, wherein a two-dimensional hole gas, generated in the channel layer by piezoelectric polarization of the buffer layer, is used as a carrier of the channel layer. On a complementary semiconductor device, the semiconductor device described above and an n-type field effect transistor are formed on the same compound semiconductor substrate. Also, a level shift circuit is manufactured by using the semiconductor device. Further, a semiconductor device manufacturing method includes forming a compound semiconductor base portion, forming a buffer layer on the base portion, forming a channel layer on the buffer layer, forming a gate on the channel layer, and forming a drain and source with the gate therebetween on the channel layer.
US10109631B2 Semiconductor device
A semiconductor device includes an insulating layer on a substrate, a channel region on the insulating layer, a gate structure on the insulating layer, the gate structure crossing the channel region, source/drain regions on the insulating layer, the source/drain regions being spaced apart from each other with the gate structure interposed therebetween, the channel region connecting the source/drain regions to each other, and contact plugs connected to the source/drain regions, respectively. The channel region includes a plurality of semiconductor patterns that are vertically spaced apart from each other on the insulating layer, the insulating layer includes first recess regions that are adjacent to the source/drain regions, respectively, and the contact plugs include lower portions provided into the first recess regions, respectively.
US10109630B2 Semiconductor device and method of forming the same
The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.
US10109629B2 Semiconductor devices including gate structures with oxygen capturing films
A semiconductor device includes: a semiconductor substrate including an active region and a gate structure on the active region. The gate structure includes a gate insulating film; a work function adjusting film on the first gate insulating film; a separation film on the work function adjusting film; and an oxygen capturing film on the separation film and configured to capture oxygen introduced from the outside of the first gate structure. The oxygen capturing film is spaced apart from a top surface of the first gate insulating film by about 70 Å to about 80 Å.
US10109627B2 Enlarging spacer thickness by forming a dielectric layer over a recessed interlayer dielectric
A method of fabricating a semiconductor device is provided. The method may include steps of receiving a device that includes a source/drain, a gate, a gate spacer formed on a sidewall of the gate, and a dielectric component formed over the source/drain, forming a recess in a top surface of the dielectric component; forming a dielectric layer over the top surface of the dielectric component and over the recess, such that a portion of the dielectric layer assumes a recessed shape; and etching a contact hole through the dielectric layer and the dielectric component, the contact hole exposing the source/drain.
US10109626B2 Semiconductor device and method of manufacturing same
To provide a semiconductor device having an element isolation structure formed in the main surface of a semiconductor substrate, having a space in a trench, and prevented from having deteriorated performance due to an increase in the height of the top portion of the space. A trench portion is formed in the main surface of a semiconductor substrate by using a hard-mask insulating film. A first insulating film that covers the upper surface of the hard-mask insulating film and the surface of the trench portion is formed, followed by etch-back of the first insulating film to expose the upper surface of the hard-mask insulating film. Then, second and third insulating films that cover the upper surface of the hard-mask insulating film and the surface of the trench portion are formed to form a space in the trench portion.
US10109624B2 Semiconductor device comprising transistor cell units with different threshold voltages
An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units. Each of the transistor cell units comprises a control terminal and first and second load terminals, respectively. The transistor cell units are electrically connected in parallel, and the control terminals of the transistor cells units are electrically connected. A first group of the transistor cell units includes a first threshold voltage. A second group of the transistor cell units includes a second threshold voltage larger than the first threshold voltage. A channel width of a transistor cell unit of the first group is smaller than a channel width of a transistor cell unit of the second group.
US10109612B2 Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices
Tools and systems for processing semiconductor devices, and methods of processing semiconductor devices are disclosed. In some embodiments, a method of using a tool for processing semiconductor devices includes a tool with a second material disposed over a first material, and a plurality of apertures disposed within the first material and the second material. The second material comprises a higher reflectivity than the first material. Each of the apertures is adapted to retain a package component over a support during an exposure to energy.
US10109611B2 Semiconductor device
An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.
US10109610B2 Wire bonding systems and related methods
A wire bond system. Implementations may include: a bond wire including copper (Cu), a bond pad including aluminum (Al) and a sacrificial anode electrically coupled with the bond pad, where the sacrificial anode includes one or more elements having a standard electrode potential below a standard electrode potential of Al.
US10109608B2 Semiconductor package
The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.
US10109606B2 Remapped packaged extracted die
A remapped extracted die is provided. The remapped extracted die includes an extracted die removed from a previous integrated circuit package. The extracted die includes a plurality of original bond pads having locations that do not correspond to desired pin assignments of a new package base and an interposer, bonded to the extracted die. The interposer includes first bond pads configured to receive new bond wires from the plurality of original bond pads, and second bond pads corresponding to desired pin assignments of the new package base, each individually electrically coupled to one of the first bond pads and configured to receive new bond wires from package leads or downbonds of the new package base.
US10109605B2 Polymer layers embedded with metal pads for heat dissipation
An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.
US10109604B2 Package with embedded electronic components and a waveguide cavity through the package cover, antenna apparatus including package, and method of manufacturing the same
A package for embedding one or more electronic components comprises a carrier structure a silicon-based carrier layer, one or more electronic components embedded in one or more cavities formed in the carrier layer, and a cover structure arranged on top of the carrier structure. The cover structure comprises a cover layer and one or more cavities formed in the cover layer. An antenna element and/or a waveguide for connection to an antenna element is formed in and/or on top of the cover layer and coupled to the one or more cavities.
US10109601B2 Integrated circuit with detection of thinning via the back face and decoupling capacitors
A semiconductor substrate has a back face and a front face and includes a semiconductor well that is electrically isolated from the semiconductor substrate. A device is configured to detect a thinning of the semiconductor substrate from the back face. The device includes at least one trench that extends within the semiconductor well between two peripheral locations from the front face down to a location situated at a distance from a bottom of the semiconductor well. The trench is electrically isolated from the semiconductor well. A detection circuit is configured to measure a physical quantity representative of well electrical resistance between two contact areas respectively situated on either side of the at least one first trench.
US10109600B1 Crackstop structures
The present disclosure relates to semiconductor structures and, more particularly, to continuous crackstop structures and methods of manufacture. The structure includes a continuous crackstop having a wall which switches back (switchbacks) on itself multiple times to form an enclosure about an active area of a chip.
US10109596B2 Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes: providing, on a substrate, a first magnetic substrate including a base, a first side wall portion and a second side wall portion at opposed ends of the base, the sidewall portions extending from the base, providing a semiconductor chip over the base at a location between the first side wall portion and the second side wall portion, providing a plate-like magnetic substrate having a second surface, the second surface provided with a resin thereon, and positioning the plate-like magnetic substrate having a second surface with the resin thereon such that the second surface faces the base of the first magnetic substrate. Then the plate like magnetic substrate is moved in the direction of the first magnetic substrate to contact the second surface of the plate like magnetic substrate with the first side wall portion and the second side wall portion.
US10109594B2 Semiconductor device with an isolation structure coupled to a cover of the semiconductor device
A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.
US10109593B2 Self shielded system in package (SiP) modules
A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield may be formed over the SiP. The metal shield may be electrically coupled to a ground layer in a printed circuit board (PCB) to form the EMI shield around the SiP. The substrate of the SiP may include at least some metallization along vertical walls in the end portions of the substrate. The metallization may provide a large contact area for coupling the metal shield to a ground ring coupled to the ground layer in the PCB. The metallization along the vertical walls in the end portions of the substrate may be formed as through-metal vias in a common substrate before singulation to form the SiP.
US10109592B2 Semiconductor chip with electrically conducting layer
A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface. An electrical contact area is exposed at the side wall surface of the semiconductor chip. An electrically conducting layer covers at least partially the second main surface and the electrical contact area.
US10109590B2 Indexing of electronic devices distributed on different chips
A method for indexing electronic devices includes: forming first chips in a first wafer, forming second chips in a second wafer, forming the electronic devices by coupling each first chip with a corresponding second chip, and forming an index on each electronic device. The index is indicative of a position of the corresponding first chip in the first wafer. The step of forming an index includes forming a first portion of the index on the first chip, and forming a second portion of the index on the second chip.
US10109588B2 Electronic component package and package-on-package structure including the same
An electronic component package includes a frame containing a metal or ceramic based material and having a through-hole, an electronic component disposed in the through-hole, an insulating part at least covering upper portions of the frame and the electronic component, a bonding part at least partially disposed between the frame and the insulating part, and a redistribution part disposed at one side of the frame and the electronic component.
US10109587B1 Integrated circuit packaging system with substrate and method of manufacture thereof
An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate including: a first trace layer, an encapsulation on the first trace layer, the first trace layer having a surface exposed from the encapsulation with a rough texture characteristic of removal of a conductive carrier coating, a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace layer; and an integrated circuit die attached to the substrate.
US10109585B2 Formation of advanced interconnects including a set of metal conductor structures in a patterned dielectric layer
An integrated circuit device includes a substrate including a patterned dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed over the set of features in the patterned dielectric. A ruthenium cobalt alloy layer is disposed over the adhesion promoting layer. A metal layer is disposed over the ruthenium cobalt alloy layer filling the set of features.
US10109579B2 Semiconductor device including a porous dielectric layer, and method of forming the semiconductor device
A method of forming a semiconductor device, includes forming a conductive layer in a recessed portion of a porous dielectric layer, partially removing a top portion of the conductive layer while maintaining a height of the porous dielectric layer, forming a conformal cap layer on the porous dielectric layer and the conductive layer in the recessed portion, polishing the conformal cap layer to form a gap in the conformal cap layer, such that an upper surface of the porous dielectric layer is exposed through the gap and an upper surface of the conductive layer is protected by the cap layer, and performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer.
US10109578B2 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and an interconnect portion. The interconnect portion is provided in the stacked body and extends in a stacking direction of a plurality of electrode layers and a first direction crossing the stacking direction. The interconnect portion includes a first portion located in a first region of the stacked body that the plurality of columnar portions is provided and a second portion located in a second region of the stacked body adjacent to the first region in the first direction, the first portion having a first width, the second portion having a second width larger than the first width.
US10109571B2 Wiring substrate and manufacturing method of wiring substrate
A wiring substrate includes a laminated sheet including a first conductor pattern, an inorganic dielectric layer, and a second conductor pattern. The first conductor pattern, the inorganic dielectric layer, and the second conductor pattern are laminated in this order. Also, the first conductor pattern is divided into a plurality of regions.
US10109566B2 Semiconductor package
A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.
US10109564B2 Wafer level chip scale semiconductor package
This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity formed therein; forming electrical contacts at a base portion and sidewalls portions of the cavity; placing a semiconductor die in the base of the cavity; connecting bond pads of the semiconductor die to the electrical contacts; encapsulating the semiconductor die; and removing the carrier to expose the electrical contacts, such that the electrical contacts are arranged directly on the encapsulation material.
US10109563B2 Modified leadframe design with adhesive overflow recesses
The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
US10109562B2 Leadframe and chip package comprising a leadframe
A leadframe includes first and second parts separated from each other, and each comprises at least one anchoring hole. The first part comprises a mounting area, the second part comprises an edge line facing the first part which is curved, and the first part comprises first, second and third portions each having a maximum width, wherein the mounting area is arranged at the third portion, and the third portion follows the second portion and the second portion follows the first portion in a direction of a longitudinal extent of the first part such that the third portion faces the second part.
US10109558B2 High impact resistant heat sink
A heat sink mounting configuration is provided that is configured to prevent the heat sink from damaging ball grid arrays (BGA) of an application specific integrated circuit (ASIC) mounted on a printed circuit board (PCB) when the line card is subjected to vibrations and shocks. The heat sink mounting configuration may include a set of screws configured to be at least partially disposed within the apertures of the heat sink to secure the heat sink to the PCB. The mounting configuration includes a resilient member and a spacer disposed around the screws proximate to the apertures. The resilient members are configured to bias the heat sink against the ASIC to maintain the heat sink in contact with the ASIC. The spacers are configured to prevent the heat sink from impacting the ASIC with forces large enough to damage the BGA when the line card is subjected to vibrations and shocks.
US10109557B2 Electronic device having sealed heat-generation element
An electronic device includes: a resin substrate that includes insulation resin on which wiring made of conductive material is provided; a heat-generation element that is a circuit element mounted on a first surface of the resin substrate, and is operated to generate heat; and a sealing resin that is provided on the first surface, and seals the heat-generation element. An opposite surface of the sealing resin opposite to a surface of the sealing resin in contact with the first surface is thermally connected to a heat radiation member and mounted on the heat radiation member. Each of the resin substrate and the sealing resin has a bend shape convex toward the opposite surface when each of surrounding temperatures is a normal temperature and has a linear expansion coefficient for maintaining a bend shape convex toward the opposite surface when each of the surrounding temperatures is a high temperature.
US10109553B2 Integrated circuit heat dissipation using nanostructures
An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.
US10109550B2 Wafer-level package with enhanced performance
The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.
US10109546B2 Process of encapsulating electronic components
In order to carry out the encapsulation of electronic components, the invention proposes to cover the electronic components (7) with a heat-polymerisable material corresponding to a composition comprising a diimide constituent and a diamine constituent, in which the diimide constituent has been predissolved in the diamine constituent, and to heat the assembly obtained under conditions suitable for carrying out the curing of the material by an addition polymerization reaction between said diimide constituent and the diamine constituent. The invention finds an application in particular in the field of electronic power modules.
US10109544B2 Baseplate for an electronic module
Various embodiments provide an electronic module comprising a baseplate. A recess is formed in one main surface of the baseplate, wherein the recess is adapted to accommodate an electronic chip. The electronic chip is attached to a substrate or carrier and is placed in the recess.
US10109543B2 Semiconductor module and resin case
A semiconductor module includes a base substrate, a semiconductor element provided on the front surface side of the base substrate, and a resin case bonded to the front surface of the base substrate and enclosing a region in which the semiconductor element is provided, wherein the resin case has a depressed portion formed in a height direction away from the base substrate in a bottom surface bonded to the base substrate, and a connection hole that connects the depressed portion and the exterior of the resin case.
US10109541B2 Board for electronic component package, electronic component package, and method of manufacturing board for electronic component package
A board for an electronic component package includes a wiring part on which an electronic component is disposed, wherein the wiring part includes an insulating layer, a signal transferring wiring electrically connected to the electronic component, and an electrical testing wiring electrically disconnected from the electronic component, and the electrical testing wiring includes conductive patterns formed on both surfaces of the wiring part, and conductive vias electrically connecting the conductive patterns to each other.
US10109538B2 Measuring device and method for measuring layer thicknesses and defects in a wafer stack
The invention relates to a measurement means and a method for measuring and/or acquiring layer thicknesses and/or voids of one or more layers of a wafer stack on a plurality of measuring points distributed on the wafer stack and a corresponding wafer processing device.
US10109533B1 Nanosheet devices with CMOS epitaxy and method of forming
This disclosure relates to a method of forming nanosheet devices including: forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer; growing a pair of epitaxial regions adjacent to the first and second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions; covering the first nanosheet stack with a mask; and forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to the epitaxial regions on the second nanosheet stack.
US10109531B1 Semiconductor structure having a bump lower than a substrate base and a width of the bump larger than a width of fin shaped structures, and manufacturing method thereof
A semiconductor structure includes a substrate, a plurality of fin shaped structures, a trench, and a first bump. The substrate has a base, and the fin shaped structures protrude from the base. The trench is recessed from the base of the substrate. The first bump is disposed within the trench and protrudes from a bottom surface of the trench. A topmost portion of the first bump is lower than the base, and a width of the first bump is larger than a width of each of the fin shaped structures.
US10109530B2 Semiconductor arrangement and formation thereof
A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
US10109522B2 Method for forming semiconductor structure
One or more techniques or systems for forming a semiconductor structure having a gap are provided herein. In some embodiments, a gap is formed between a first etch stop layer (ESL) and an ESL seal region. For example, the gap is formed by removing a portion of a low-k (LK) dielectric region above an oxide region and removing the oxide region. In some embodiments, the oxide region below the LK dielectric region facilitates removal of the LK dielectric region, at least because the oxide region enhances a bottom etch rate of a bottom of the LK dielectric region such that the bottom etch rate is similar to a wall etch rate of a wall of the LK dielectric region.
US10109521B1 Method to prevent cobalt recess
A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.
US10109520B2 Methods for depositing dielectric barrier layers and aluminum containing etch stop layers
In some embodiments, a method of forming an interconnect structure includes selectively depositing a barrier layer atop a substrate having one or more exposed metal surfaces and one or more exposed dielectric surfaces, wherein a thickness of the barrier layer atop the one or more exposed metal surfaces is greater than the thickness of the barrier layer atop the one or more exposed dielectric surfaces. In some embodiments, a method of forming an interconnect structure includes depositing an etch stop layer comprising aluminum atop a substrate via a physical vapor deposition process; and depositing a barrier layer atop the etch stop layer via a chemical vapor deposition process, wherein the substrate is transferred from a physical vapor deposition chamber after depositing the etch stop layer to a chemical vapor deposition chamber without exposing the substrate to atmosphere.
US10109519B2 Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A conductive feature over a substrate is provided. A first dielectric layer is deposited over the conductive feature and the substrate. A via-forming-trench (VFT) is formed in the first dielectric layer to expose the conductive feature and the substrate around the conductive feature. The VFT is filled in by a sacrificial layer. A via-opening is formed in the sacrificial layer to expose the conductive feature. A metal plug is formed in the via-opening to connect to the conductive feature. The sacrificial layer is removed to form a surrounding-vacancy around metal plug and the conductive feature. A second dielectric layer is deposited over the substrate to seal a portion of the surrounding-vacancy to form an enclosure-air-gap all around the metal plug and the conductive feature.
US10109518B1 Pickup unit and pickup system of semiconductor device including the same
A pickup apparatus includes a plurality of pickers sliding along a first direction and a space adjuster including a plurality of space adjusting plates. Each picker includes a protruding portion combined with a picker body, and each of the space adjusting plates is between a respective pair of adjacent pickers. The protruding portion of each picker contacts sidewalls of adjacent space adjusting plates. At least one of the space adjusting plates moves along a second direction crossing the first direction. A width in the first direction of each space adjusting plate varies along the second direction.
US10109515B2 Hand unit and transfer method
A hand unit of a robot arm includes a U-shaped placement portion on which a semiconductor wafer is placed. The hand unit includes, on one end side of the placement portion, a first support portion configured to support the semiconductor wafer at a first support height and a second support portion configured to support the semiconductor wafer at a second support height, and includes, on the other end side of the placement portion, a third support portion configured to support the semiconductor wafer at the first support height and a fourth support portion configured to support the semiconductor wafer at the second support height. The hand unit further includes a first driving unit configured to move the third support portion and/or the fourth support portion forward and backward with respect to the first support portion and the second support portion.
US10109513B2 Substrate treating apparatus
A substrate treating apparatus includes a treating section for treating substrates, and an interface section disposed adjacent the treating section and adjacent an exposing machine provided separately from the apparatus. The interface section has a first treating-section-side transport mechanism, a second treating-section-side transport mechanism, and an exposing-machine-side transport mechanism. Each of the first and second treating-section-side transport mechanisms is arranged to receive the substrates from the treating section, pass the substrates to the exposing-machine-side transport mechanism, receive the substrates from the exposing-machine-side transport mechanism and pass the substrates to the treating section. The exposing-machine-side transport mechanism is arranged to receive the substrates from the first and second treating-section-side transport mechanisms, transport the substrates to the exposing machine, receive the substrates after exposing treatment from the exposing machine, and pass the substrates to the first and second treating-section-side transport mechanisms.
US10109512B2 Photovoltaic cell with porous semiconductor regions for anchoring contact terminals, electrolitic and etching modules, and related production line
A photovoltaic cell is proposed. The photovoltaic cell includes a substrate of semiconductor material, and a plurality of contact terminals each one arranged on a corresponding contact area of the substrate for collecting electric charges being generated in the substrate by the light. For at least one of the contact areas, the substrate includes at least one porous semiconductor region extending from the contact area into the substrate for anchoring the whole corresponding contact terminal on the substrate. In the solution according to an embodiment of the invention, each porous semiconductor region has a porosity decreasing moving away from the contact area inwards the substrate. An etching module and an electrolytic module for processing photovoltaic cells, a production line for producing photovoltaic cells, and a process for producing photovoltaic cells are also proposed.
US10109511B2 Post-processing apparatus of solar cell
A post-processing apparatus of a solar cell carries out a post-processing operation including a main period for heat-treating a solar cell including a semiconductor substrate while providing light to the solar cell. The post-processing apparatus includes a main section to carry out the main period. The main section includes a first heat source unit to provide heat to the semiconductor substrate and a light source unit to provide light to the semiconductor substrate. The first heat source unit and the light source unit are positioned in the main section. The light source unit includes a light source constituted by a plasma lighting system (PLS).
US10109508B2 Substrate processing device and method of manufacturing semiconductor device
A substrate processing device includes a bath configured to accommodate a plurality of substrates and configured to store a liquid for etching the plurality of substrates, a plurality of bubble generators configured to generate bubbles in the liquid, the bubble generators provided so as to correspond to each of the plurality of substrates, a measurement device configured to measure the generation state of the bubbles of at least one of the plurality of bubble generators, and a control device configured to individually control at least one of the plurality of bubble generators based on the measurement result of the measurement device.
US10109503B2 Method of manufacturing semiconductor package device
A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a carrier. The carrier has a first surface and a second surface opposite to the first surface. The carrier includes an inner core layer and an exterior clad layer, and the inner core layer is covered by the exterior clad layer.
US10109502B2 Semiconductor package with reduced parasitic coupling effects and process for making the same
The present disclosure relates to a semiconductor package with reduced parasitic coupling effects, and a process for making the same. The disclosed semiconductor package includes a thinned flip-chip die and a first mold compound component with a dielectric constant no more than 7. The thinned flip-chip die includes a back-end-of-line (BEOL) layer with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, a device layer over the upper surface of the BEOL layer, and a buried oxide (BOX) layer over the device layer. The BEOL layer includes a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion. Herein, the first mold compound component extends through the BOX layer and the device layer to the first surface portion.
US10109500B2 Semiconductor device and manufacturing method thereof
A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.
US10109495B2 Plasma etching method for selectively etching silicon oxide with respect to silicon nitride
An etching method is provided for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride by performing plasma processing on a target object including the first region and the second region. In the etch method, first, a plasma of a processing gas including a fluorocarbon gas is generated in a processing chamber where the target object is accommodated. Next, the plasma of the processing gas including the fluorocarbon gas is further generated in the processing chamber where the target object is accommodated. Next, the first region is etched by radicals of fluorocarbon contained in a deposit which is formed on the target object by the generation and the further generation of the plasma of the processing gas containing the fluorocarbon gas. A high frequency powers used for the plasma generation is smaller than a high frequency power used for plasma further generation.
US10109494B2 FinFet spacer etch with no fin recess and no gate-spacer pull-down
A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state.
US10109493B2 Composite abrasive particles for chemical mechanical planarization composition and method of use thereof
Chemical Mechanical Planarization (CMP) polishing compositions comprising composite particles, such as ceria coated silica particles, offer low dishing, low defects, and high removal rate for polishing oxide films. Chemical Mechanical Planarization (CMP) polishing compositions have shown excellent performance using soft polishing pad.
US10109491B2 Vertical FET with selective atomic layer deposition gate
Vertical channel field effect transistors include a bottom source/drain layer. One or more vertical channels are formed on the bottom source/drain layer. A horizontal seed layer is formed around the one or more vertical channels. A metal gate is formed directly on the seed layer. A top source/drain is formed layer above the one or more vertical channels and the metal gate.
US10109484B2 Method for producing nanocrystals with controlled dimensions and density
Method for producing nanocrystals of semiconductor, comprising at least: ion bombardment of a thin layer of semiconductor arranged on at least one dielectric layer, achieving at least one among an implantation of ions of at least one chemical element of rare gas type and an implantation of ions of at least one semiconductor element of same nature as that of the thin layer, in at least one part of the thickness of the thin layer; annealing of the thin layer achieving a dewetting of the semiconductor of the thin layer and forming, on the dielectric layer, nanocrystals of semiconductor.
US10109481B2 Aluminum-nitride buffer and active layers by physical vapor deposition
Embodiments of the invention described herein generally relate to an apparatus and methods for forming high quality buffer layers and Group III-V layers that are used to form a useful semiconductor device, such as a power device, light emitting diode (LED), laser diode (LD) or other useful device. Embodiments of the invention may also include an apparatus and methods for forming high quality buffer layers, Group III-V layers and electrode layers that are used to form a useful semiconductor device. In some embodiments, an apparatus and method includes the use of one or more cluster tools having one or more physical vapor deposition (PVD) chambers that are adapted to deposit a high quality aluminum nitride (AlN) buffer layer that has a high crystalline orientation on a surface of a plurality of substrates at the same time.
US10109480B2 Selective nanoscale growth of lattice mismatched materials
Exemplary embodiments provide materials and methods of forming high-quality semiconductor devices using lattice-mismatched materials. In one embodiment, a composite film including one or more substantially-single-particle-thick nanoparticle layers can be deposited over a substrate as a nanoscale selective growth mask for epitaxially growing lattice-mismatched materials over the substrate.
US10109479B1 Method of making a semiconductor device with a buried insulating layer formed by annealing a superlattice
A method for making a semiconductor device may include forming a superlattice on a semiconductor substrate including a respective plurality of stacked groups of layers. Each group of layers may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Further, at least some semiconductor atoms from opposing base semiconductor portions may be chemically bound together through the at least one non-semiconductor monolayer therebetween. The method may further include epitaxially forming a semiconductor layer on the superlattice, and annealing the superlattice to form a buried insulating layer in which the at least some semiconductor atoms are no longer chemically bound together through the at least one non-semiconductor monolayer therebetween.
US10109476B2 Substrate processing method for depositing a barrier layer to prevent photoresist poisoning
A method for depositing a barrier layer includes a) arranging a substrate including a nitride layer in a processing chamber; b) setting a process temperature in the processing chamber to a predetermined process temperature range; c) setting a process pressure in the processing chamber to a predetermined process pressure range; d) supplying at least one of a gas and a vapor including an organosilane precursor species; and e) depositing a barrier layer on the nitride layer. The barrier layer reduces diffusion of nitrogen-containing groups in the nitride layer into a photoresist layer that is subsequently deposited on the nitride layer.
US10109475B2 Semiconductor wafer and method of reducing wafer thickness with asymmetric edge support ring encompassing wafer scribe mark
A semiconductor wafer has a base material with a first thickness and first and second surfaces. A wafer scribe mark is disposed on the first surface of the base material. A portion of an interior region of the second surface of the base material is removed to a second thickness less than the first thickness, while leaving an edge support ring of the base material of the first thickness and an asymmetric width around the semiconductor wafer. The second thickness of the base material is less than 75 micrometers. The wafer scribe mark is disposed within the edge support ring. The removed portion of the interior region of the second surface of the base material is vertically offset from the wafer scribe mark. A width of the edge support ring is wider to encompass the wafer scribe mark and narrower elsewhere around the semiconductor wafer.
US10109474B1 Method for fabricating handling wafer
A method for fabricating handling wafer includes providing a substrate, having a front side and a back side. The front side of the substrate is disposed on a supporting pin. A first oxide layer is formed surrounding the substrate. A portion of the first oxide layer is removed to expose the front side of the substrate. An alignment mark is formed on the front side of the substrate.
US10109469B2 Method of generating electron transfer dissociation reagent ions
A method of mass spectrometry is disclosed wherein ions are subjected to an electron detachment, electron capture or electron transfer process in order to form ions having a different charge state. At least some of the ions having a different charge state are caused to interact with analyte ions to cause at least some of the analyte ions to fragment to form daughter, fragment or product ions.
US10109466B2 Support unit and apparatus for treating substrate
Provided is a support unit. The support unit includes a support plate having a top surface in which a measurement groove is defined and on which a substrate is placed, and a sensor for measuring a pressure in the measurement groove in the state where the substrate is placed on the support plate. The measurement groove has a main measurement groove that extends from a central area of the support plate up to an edge area of the support plate.
US10109465B2 Coil filament for plasma enhanced chemical vapor deposition source
A vapor deposition source that includes a substantially vertical plate to which first and second filament posts are coupled. The vapor deposition source also includes a filament having a first end and a second end. The filament provides a substantially concentric source of electrons. The first end of the filament is connected to the first filament post and the second end of the filament is connected to the second filament post. The first end of the filament is substantially vertically aligned with the second end of the filament when the filament is connected to the first and second posts.
US10109463B2 Microwave automatic matcher and plasma processing apparatus
A microwave automatic matcher includes a movable body, a driving unit, a matching control unit, a reflection coefficient measuring unit, and a setting unit. The matching control unit consecutively moves the movable body from a start position in one direction by a distance of a difference between the start position and the target position in a matching operation carried out for the plasma process and then variably controls the position of the movable body until the measurement of the reflection coefficient obtained by the reflection coefficient measuring unit falls within the first neighboring range by monitoring the measurement of the reflection coefficient.
US10109453B2 Electron beam masks for compressive sensors
Transmission microscopy imaging systems include a mask and/or other modulator situated to encode image beams, e.g., by deflecting the image beam with respect to the mask and/or sensor. The beam is modulated/masked either before or after transmission through a sample to induce a spatially and/or temporally encoded signal by modifying any of the beam/image components including the phase/coherence, intensity, or position of the beam at the sensor. For example, a mask can be placed/translated through the beam so that several masked beams are received by a sensor during a single sensor integration time. Images associated with multiple mask displacements are then used to reconstruct a video sequence using a compressive sensing method. Another example of masked modulation involves a mechanism for phase-retrieval, whereby the beam is modulated by a set of different masks in the image plane and each masked image is recorded in the diffraction plane.
US10109451B2 Apparatus configured for enhanced vacuum ultraviolet (VUV) spectral radiant flux and system having the apparatus
A charge control apparatus for controlling charge on a substrate in a vacuum chamber is described. The apparatus includes a light source emitting a beam of radiation having a divergence; a mirror configured to reflect the beam of radiation, wherein a curvature of a mirror surface of the curved mirror is configured to reduce the divergence of the beam of radiation; and a mirror support configured to rotatably support the curved mirror, wherein a rotation of the mirror varies the direction of the beam of radiation.
US10109450B2 X-ray tube with structurally supported planar emitter
A cathode head can include: an insulating member on a base; an electron emitter with a planar emitter surface formed by a plurality of elongate rungs connected together through a plurality of turns from a first emitter end to a second emitter end so as to form a serpentine emitter pattern; a plurality of elongate legs extending from the plurality of turns at an angle relative to the planar emitter surface, each of the legs being coupled with the insulating member; an elongate first lead leg at the first emitter end and an elongate second lead leg at the second emitter end; a first electrical lead and a second electrical lead extending from the base; and a first electrical coupler coupling the first electrical lead to the first lead leg and a second electrical coupler coupling the second electrical lead to the second lead leg.
US10109444B2 Electronic module for protecting a HVDC converter from current surges of energy discharges from a capacitor of the converter
An electronic module for protecting power semiconductor devices of an HVDC converter against high current surges and damaging electrical discharges includes a capacitor, a short circuit device, a movable portion, a short circuit portion and a spring element. The short circuit device is connected in parallel with the capacitor and has first and second busbars. The movable portion is connected to the first busbar and the short circuit portion is connected to the second busbar. The spring element is arranged between the movable portion and the short circuit portion. When a short circuit current flows through the first busbar, an electromagnetic force between the busbars causes the first busbar to repel the second busbar and move towards the short circuit portion. The latter provides a short circuit path connecting the first busbar to the second busbar short circuiting the capacitor and bypassing the power semiconductor devices of the HVDC converter.
US10109440B2 Safety switch
The invention relates to a safety switch (2) with a redundant input structure and with a redundant output structure. The safety switch (2) is designed for integration into a series connection (1) of safety switches (2); the safety switch (2) has devices for detecting and adjusting the operating mode in the series connection (1). The safety switch (2) is designed for replacement in the series connection (1) during its operation.
US10109435B1 Interchangeable electrical assembly with tactile switch and illumination device
An interchangeable electrical assembly provides a tactile switch that selectively opens and closes a circuit for operating myriad styles of illumination devices. The tactile switch detachably mates with, and regulates conduction of direct current to the illumination device. The tactile switch also provides tactile feedback of an operating position. A wire carries a 12 volt direct current into a switch housing. A conductive member receives the direct current. A cap receives a force to axially displace the conductive member while providing tactile feedback to the position of the conductive member. A contact pin operatively connects to the conductive member. A spring biases the conductive member to disengage from the contact pin. The cap selectively displaces the conductive member to engage the contact pin. An illumination device detachably mates with tactile switch, and includes a conducting shaft, an inverter for converting direct current to alternating current, and circuitry to generate illumination.
US10109425B2 Multilayer capacitor, method for manufacturing the same, and electronic device using same
Disclosed herein are a multilayer capacitor, a method for manufacturing the same, and an electronic device using the same. A multilayer capacitor including internal electrodes stacked in a dielectric so as to be spaced apart from each other, alternately connected to external electrodes formed on both sides of the dielectric, and formed so that width sizes of connection sections connected to the external electrodes are decreased as compared with those of overlapped sections overlapped with each other while vertically neighboring to each other in at least portions of a stacked structure is suggested. In addition, an electronic device using the multilayer capacitor and a method for manufacturing the multilayer capacitor are suggested.
US10109422B2 Film capacitor
A film capacitor includes: a capacitor element in which a metallikon electrode is formed at an end; a bus bar connected with the metallikon electrode; a case having a container for housing the capacitor element and the bus bar; a lid member which covers an opening of the container; and a heat conducting member disposed between the bus bar and the lid member. The lid member has a protrusion on a side facing the heat conducting member, the protrusion is in contact with the heat conducting member, and the heat conducting member is in contact with the bus bar.
US10109421B2 Polymerization method for preparing conductive polymer
A improved process for preparing a conductive polymer dispersion is provided as is an improved method for making capacitors using the conductive polymer. The process includes providing a monomer solution and shearing the monomer solution with a rotor-stator mixing system comprising a perforated stator screen having perforations thereby forming droplets of said monomer. The droplets of monomer are then polymerized during shearing to form the conductive polymer dispersion.
US10109417B2 Laminated iron core and method of manufacturing laminated iron core with caulking protrusion
There is provided a laminated iron core including a plurality of piled iron core pieces, each piled iron core pieces being blanked from at least two piled sheet materials and sequentially laminated on other piled iron core pieces, wherein the piled iron core pieces adjacent in a direction of lamination are interlocked together by a plurality of caulking parts provided in each piled iron core pieces. Each of the plurality of caulking parts includes a caulking protrusion formed in one side and a caulking fitting groove formed in the other side to which the caulking protrusion is fitted, and the caulking protrusion is allowed to protrude to the caulking fitting groove of the piled iron core pieces adjacent thereto in the direction of lamination, and a width of the caulking protrusion is larger than an inner width of the caulking fitting groove.
US10109415B2 Wireless power receiver and external inductor connected thereto
Disclosed is an external inductor that is connected to a wireless power receiver. The external inductor may include a conductor including at least one main slit, a first connecting unit that connects a first point of the conductor and the wireless power receiver with each other, and a second connecting unit that connects a second point of the conductor and the wireless power receiver with each other.
US10109411B2 Coil component
A coil component has a first surface and a second surface facing each other. The coil component has a coil conductor formed into a spiral shape, an insulating resin layer covering the coil conductor, a magnetic resin layer disposed on the first surface side of the insulating resin layer without being disposed on the second surface side of the insulating resin layer, and an external terminal disposed at least on one surface on the first surface side of the magnetic resin layer and electrically connected to the coil conductor. The magnetic resin layer is made of a composite material of a resin and a metal magnetic powder. The external terminal includes a metal film contacting the resin and the metal magnetic powder of the magnetic resin layer.
US10109410B2 Out of plane structures and methods for making out of plane structures
A method for forming an out of plane structure includes depositing a layer of an elastic material on a substrate wherein the elastic material has an intrinsic stress profile. The layer of elastic material is photolithographically patterned into at least two spaced-apart elastic members. An electrically non-conductive tether layer joins the elastic members. A portion of the substrate is etched under the elastic members to release a free end of each elastic member, while leaving an anchor portion of each elastic member fixed to the substrate. The stress profile of the elastic members biases the free ends of the elastic members away from the substrate forming loops. The structure is electroplated by applying a voltage having a first polarity between an anode and the structure while the structure is in an electroplating bath. Subsequent to the electroplating, the polarity of the voltage between the anode and the structure is reversed.
US10109406B2 Iron powder for dust core and insulation-coated iron powder for dust core
Iron powder for dust cores that is appropriate for manufacturing a dust core with low iron loss is obtained by setting the oxygen content in the powder to be 0.05 mass % or more to 0.20 mass % or less, and in a cross-section of the powder, setting the area ratio of inclusions to the matrix phase to be 0.4% or less.
US10109403B2 R-T-B based sintered magnet and motor
The present invention provides an R-T-B based sintered magnet that inhibits the demagnetization rate at high temperature even when less or no heavy rare earth elements such as Dy, Tb and the like are used. The R-T-B based sintered magnet comprises R2T14B crystal grains and two-grain boundary parts between the R2T14B crystal grains. Two-grain boundary parts formed by a phase containing R, Cu, Co, Ga and Fe with a ratio of 40≤R≤70, 1≤Co≤10, 5≤Cu≤50, 1≤Ga≤15, and 1≤Fe≤40 (wherein, R+Cu+Co+Ga+Fe=100, and R is at least one selected from rare earth elements) exists in the magnet.
US10109402B2 Rare earth based magnet
The present invention provides a rare earth based magnet that inhibits the high temperature demagnetization rate even when less or no heavy rare earth elements such as Dy, Tb and the like than before are used. The rare earth based magnet according to the present invention is a sintered magnet which includes R2T14B crystal grains as main phase and grain boundary phases between the R2T14B crystal grains. When the grain boundary phase surrounded by three or more main phase crystal grains is regarded as the grain boundary multi-point, the microstructure of the sintered body is controlled so that the ratio of the grain boundary triple-point surrounded by three main phase crystal grains in all grain boundary multi-points to be specified value or less.
US10109401B2 Method for increasing coercive force of magnets
The present invention provides a method for improving coercive force of magnets, this method comprises steps as follows: S2) coating step: coating a coating material on the surface of a magnet and drying it; and S3) infiltrating step: heat treating the magnet obtained from the coating step S2). The coating material comprises (1) metal calcium particles and (2) particles of a material containing a rare earth element; the rare earth element is at least one selected from Praseodymium, Neodymium, Gadolinium, Terbium, Dysprosium, Holmium, Erbium, Thulium, Ytterbium and Lutetium. The method of the present invention can significantly increase coercive force of a permanent magnet material, while remanence and magnetic energy product hardly decrease. In addition, the method of the present invention can significantly decrease the amount of a rare earth element, and accordingly, decrease the production cost.
US10109400B2 Carbon nanotube thin film laminate resistive heater
Laminated resistive heaters comprising a carbon nanotube layer are described. The invention also includes methods of making laminated resistive heaters and applications using the resistive heaters.
US10109396B2 Electrical characteristics of shielded electrical cables
A shielded electrical cable includes one or more conductor sets extending along a length of the cable and being spaced apart from each other along a width of the cable. Each conductor set has one or more conductors having a size no greater than 24 AWG and each conductor set has an insertion loss of less than about −20 dB/meter over a frequency range of 0 to 20 GHz. First and second shielding films are disposed on opposite sides of the cable, the first and second films including cover portions and pinched portions arranged such that, in transverse cross section, the cover portions of the first and second films in combination substantially surround each conductor set, and the pinched portions of the first and second films in combination form pinched portions of the cable on each side of each conductor.
US10109395B2 Connection unit for an actively cooled cable
A connection unit for a fluid-cooled electric cable is provided, the connection unit comprising a housing, which has a cable connecting opening, a fluid inlet opening and a fluid outlet opening.
US10109390B2 Conductive film, and touch panel, display, touch sensor, and solar cell using the same
A conductive film includes a film substrate and a conductive layer formed on at least one surface of the film substrate. The film substrate and the conductive film have elongation of 10% or more. Ten-point average roughness Rz of the surface of the film substrate on at least a conductive layer side is 0.05 to 0.5 μm, and an average interval Sm of unevenness is 0.1 to 1 μm.
US10109389B2 Rectangular insulated wire, coil and electrical and electronic device
A rectangular insulated wire includes a rectangular conductor having a generally rectangular cross section and a plurality of baked-coating resin layers disposed to cover the rectangular conductor. Each of the plurality of baked-coating resin layers is formed of at least one resin selected from a group comprising a polyester-based resin including a trihydric or tetrahydric alcohol constituent, a polyester imide resin, a polyamide-imide resin and a polyimide resin. An adhesion strength between the plurality of baked-coating resin layers is greater than or equal to 5 g/mm and less than or equal to 10 g/mm.
US10109384B2 System for generation of useful electrical power from isotopic emissions
Particles emitted by radio-isotopic by-products of nuclear fission are used as a power source at the cathode of a magnetron system. Particles include high energy electrons having a large associated EMF. In the system a radial electrical vector E, between the cathode and anode, interacts with an axial magnetic vector B vector to produce an E×B force that rotates the particles about the system axis. These emissions are within a set range of velocities. The angular velocity and geometry of a rotating field, known as a space charge wheel (SCW), may be modulated by an external RF inputs to cavities of an anode block and the use of concentric biasing grids between the cathode and anode block. The SCW induces LC values into cavities of the anode, exciting them and producing electrons resonance which may be used to generate power.
US10109383B1 Target assembly and nuclide production system
Target assembly for an isotope production system. The target assembly includes a target body having a production chamber and a beam cavity that is adjacent to the production chamber. The production chamber is configured to hold a target material. The beam cavity is configured to receive a particle beam that is incident on the production chamber. The target assembly also includes a target foil positioned to separate the beam cavity and the production chamber. The target foil has a side that is exposed to the production chamber such that the target foil is in contact with the target material during isotope production. The target foil includes a material layer having a nickel-based superalloy composition.
US10109378B2 Method for fabrication of fully ceramic microencapsulation nuclear fuel
Currently, the commercial fuel of choice, UO2-zircaloy, is economical due to an established and simple fabrication process. However, the alternatives to the UO2-zircaloy that may improve on system safety are sought. The fully ceramic microencapsulated (FCM) fuel system that is potentially inherently safe fuel and is an improvement on the UO2-zircaloy system is prohibitively expensive because of the known methods to produce it. Disclosed herein is a new production route and fixturing that produces identical or superior FCM fuel consistent with mass production by providing a plurality of tristructural-isotropic fuel particles; mixing the plurality of tristructural-isotropic fuel particles with ceramic powder to form a mixture; placing the mixture in a die; and applying a current to the die so as to sinter the mixture by direct current sintering into a fuel element.
US10109377B2 System and method for facilitating delivery of patient-care
A computer-implemented method for facilitating delivery of patient-care in adherence with a standard of care clinical protocol is described. The method includes monitoring, by a computing device, patient information indicative of a clinical condition, based on a clinical protocol that comprises patient-care instructions that must be completed within a time period. The method further includes providing, by the computing device, the patient-care instructions to a user based on a result of the monitoring. The method also includes determining, by the computing device, adherence to the clinical protocol based on a result of at least one of the providing patient care instructions and the patient information; and for a determination that the clinical protocol has not been adhered to, providing a recommended action request that calibrates the patient care instructions in compliance with the clinical protocol.
US10109376B2 Measuring apparatus
Measuring apparatus (1) for tracking human and/or animal tissues comprising: a working area (2) for receiving a tissue; a detecting unit (5) configured to detect a unique tissue code provided with the tissue placed on the working area (2); a measuring unit (9) configured to automatically measure quantitative properties of the tissue placed on the working area (2); and a processing and storing unit (22) configured to automatically link the quantitative properties with the tissue code and to automatically store the so linked quantitative properties and tissue code such that the quantitative properties can be retrieved based on the tissue code.
US10109375B1 De-identifying medical history information for medical underwriting
A computer-implemented method includes producing information that characterizes a group of individuals from a set of private data representing characteristics of the individuals. The identity of the individuals is unattainable from the produced information. The method also includes providing the produced information to report the characteristics of the group.
US10109371B2 Test method of semiconductor device
The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.
US10109370B2 Template copy to cache
A template of instructions may be copied from a non-volatile memory (NVM) to a plurality of cache lines of an instruction cache of a processor. The instructions of the templates copied to the instruction cache may be executed. The templates may include a conditional branch instruction to determine if to proceed to a next template of the plurality of copied templates.
US10109366B2 Memory device with a fuse protection circuit
A memory device includes a memory circuit and a fuse protection circuit. The memory circuit includes a memory cell and a program line. The memory cell includes a fuse. The program line is configured to receive a program voltage for programming the fuse. The fuse protection circuit is coupled to the memory circuit and is configured to prevent unintentional programming of the fuse.
US10109364B2 Non-volatile memory cell having multiple signal pathways to provide access to an antifuse of the memory cell
A non-volatile memory cell, having an antifuse for storing data, is disclosed for use in a non-volatile data storage device. The non-volatile memory cell includes multiple redundant signal pathways to provide redundant access to the antifuse. During operation, the non-volatile memory cell can access the antifuse using a first signal pathway from among the multiple redundant signal pathways. However, when the first signal pathway is inoperable, the non-volatile memory cell is able to access the antifuse using a second signal pathway from among the multiple redundant signal pathways. The non-volatile memory cell is fabricated using a continuous region of one or more diffusion layers to allow efficient connection to other non-volatile memory cells to form an array of memory cells for the non-volatile data storage device.
US10109362B2 Semiconductor device and method for operating the same
A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.
US10109356B2 Method and apparatus for stressing a non-volatile memory
A method and memory for stressing a plurality of non-volatile memory cells is provided. The method includes entering a memory cell stressing mode and providing one or more erase stress pulses to the plurality of non-volatile memory cells; determining that a threshold voltage of at least a subset of the plurality of non-volatile memory cells has a first relationship that is either greater than or less than a first predetermined voltage; providing one or more program stress pulses to the plurality of memory cells; and determining that the threshold voltage of at least a subset of the plurality of memory cells has a second relationship to a second predetermined voltage that is different than the first relationship.
US10109350B2 Ferroelectric memory device
In one embodiment, a device is described for using ferroelectric material in a memory cell. In another embodiment, a method of operating a ferroelectric memory cell is described. Other embodiments are likewise described.
US10109347B2 Variable resistance memory with lattice array using enclosing transistors
A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.
US10109345B2 Write assist for memories with resistive bit lines
Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.
US10109342B2 Dram architecture to reduce row activation circuitry power and peripheral leakage and related methods
A semiconductor device may include a plurality of memory cells, and at least one peripheral circuit coupled to the plurality of memory cells and comprising a superlattice. The superlattice may include a plurality of stacked groups of layers with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer thereon constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include a first power switching device configured to couple the at least one peripheral circuit to a first voltage supply during a first operating mode, and a second power switching device configured to couple the at least one peripheral circuit to a second voltage supply lower than the first voltage supply during a second operating mode.
US10109339B1 Memory devices with selective page-based refresh
Several embodiments of memory devices and systems with selective page-based refresh are disclosed herein. In one embodiment, a memory device includes a controller operably coupled to a main memory having at least one memory region comprising a plurality of memory pages. The controller is configured to track, in one or more refresh schedule tables stored on the memory device and/or on a host device, a subset of memory pages in the plurality of memory pages having an refresh schedule. In some embodiments, the controller is further configured to refresh the subset of memory pages in accordance with the refresh schedule.
US10109332B2 Magnetic memory device
According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a first nonmagnetic layer, a second magnetic layer, a first conductive region, a first insulating region, and a controller. The conductive layer includes a first element. The conductive layer includes a first portion, a second portion, a third portion between the first portion and the second portion, and a fourth portion between the second portion and the third portion. The first conductive region includes a second element different from the first element. The first conductive region is provided between the second magnetic layer and the third portion. The first insulating region includes a first insulating substance. The first insulating substance is an insulating compound of the second element. The controller is electrically connected to the first portion and the second portion. The controller implements a first operation and a second operation.
US10109326B2 Semiconductor devices
A semiconductor device includes a latch signal generation circuit latching an external signal in synchronization with an internal clock signal to generate a latch signal, a test pulse generation circuit buffering the internal clock signal according to the latch signal to generate a test pulse signal, and a test period signal generation circuit generating a test period signal which is enabled, in response to a pulse of the test pulse signal, to execute a predetermined function.
US10109319B2 Digital media editing
Implementations are directed to providing a digital media editing environment for editing at least a portion of a digital video using a mobile device, establishing communication between the mobile device and a data source, receiving, from the data source, a first portion of the digital video, the first portion including a first set of frames including less than all frames of the digital video, applying an edit to the first portion of the digital video, while less than all frames of the first digital video are stored on the mobile device, subsequent to applying the at least one edit, receiving, from the data source, a second portion of the digital video, the second portion including a second set of frames, and storing an edited digital video including at least one frame of the first set of frames, at least one frame of the second set of frames, and the edit.
US10109318B2 Low bandwidth consumption online content editing
Various embodiments of the invention provide systems and methods for low bandwidth consumption online content editing, where user-created content comprising high definition/quality content is created or modified at an online content editing server according to instructions from an online content editor client, and where a proxy version of the resulting user-created content is provided to online content editor client to facilitate review or further editing of the user-created content from the online content editor client. In some embodiments, the online content editing server utilizes proxy content during creation and modification operations on the user-created content, and replaces such proxy content with corresponding higher definition/quality content, possibly when the user-created content is published for consumption, or when the user has paid for the higher quality content.
US10109316B2 Method and apparatus for playing back recorded video
A method and an apparatus for playing back recorded video from a temporal position within a temporal range of the recorded video is disclosed. The recorded video including intra frames and inter frames and the recorded video including video sequences having different frame rates. The method comprises receiving a request for playing back the recorded video from a specific temporal position recorded in the recorded video, identifying an intra frame at an earlier temporal position in the recorded video than the specific temporal position received in the request, playing back the recorded video in a first mode from the identified intra frame, and playing back the recorded video in a second mode from the specific temporal position in the recorded video when the playing back of the recorded video in the first mode have arrived at the specific temporal position of in the recorded video.
US10109311B2 Motor including base portion and vent passage and disk drive apparatus provided with same
A stationary portion includes a stator unit including coils in an annular shape with a central axis as a center; a base portion below the stator unit; and a housing defining an interior space in which a rotating portion, a bearing portion, and the stator unit are accommodated. The base portion includes a through hole extending through the base portion in an axial direction to join an outside of the housing and the interior space to each other; a sheet covering an upper opening of the through hole to close the through hole; a filler covering a lower opening of the through hole; and a vent passage defined in at least one of the base portion and the sheet to join the through hole and the interior space to each other.
US10109306B2 Method of correcting head suspension, method of manufacturing head suspension, head suspension and method of processing thin plate
A method corrects a head suspension by irradiating an objective part of the head suspension with a laser beam before or after mounting a read/write head on the head suspension. The method can precisely correct the head suspension even when correcting the head suspension a plurality of times. The method includes drawing, with the laser beam, a straight line of predetermined length on the objective part and repeating this process a plurality of times in such a way that the direction of a straight line drawn this time crosses the direction of a straight line drawn last time.
US10109305B2 Co-located gimbal-based DSA disk drive suspension with traces routed around slider pad
A suspension having a DSA structure on a gimbaled flexure includes a loadbeam and a flexure attached to the loadbeam. The flexure includes a metal layer with a pair of spring arms, a tongue including a slider mounting surface, and a pair of struts connecting the pair of spring arms to the tongue. The suspension further includes a pair of traces including one or more insulated conductors and being routed around opposite sides of the slider mounting surface, over the pair of struts to a set of terminal contacts on a distal portion of the tongue. The suspension also includes a motor mounted on the flexure, the motor having opposite lateral ends, the motor orientated laterally across the flexure such that the opposite lateral ends of the motor are on opposite lateral sides of the flexure. Electrical activation of the motor rotates the slider mounting surface relative to the loadbeam.
US10109303B2 Devices including a near field transducer (NFT), at least one cladding layer and interlayer there between
A device that includes a near field transducer (NFT); at least one cladding layer adjacent the NFT; and a carbon interlayer positioned between the NFT and the at least one cladding layer.
US10109302B1 Magnetic recording head with spin torque oscillator, head gimbal assembly and magnetic recording apparatus
A magnetic recording head is provided with a main magnetic pole that generates a recording magnetic field to be applied to a magnetic recording medium from an end surface which makes a portion of an air bearing surface, a trailing shield that is placed by interposing a write gap at a trailing side of the main magnetic pole, a spin torque oscillator that is placed within the write gap to be between the main magnetic pole and the trailing shield, and two side shields that are placed at both sides of the main magnetic pole in the cross track direction, and when viewed from the air bearing surface side, at least a portion of the trailing-side end surfaces of the side shields are offset toward a leading-side of the main magnetic pole from the leading-side end surface of the spin torque oscillator.
US10109299B2 Sound processing apparatus, sound processing method, and storage medium
A sound processing apparatus includes a detection unit adapted to detect a situation of a subject to be imaged from image data generated by imaging the subject to be imaged by an imaging unit; an extraction unit adapted to extract a feature amount of a sound from sound data generated by a sound acquisition unit corresponding to the imaging unit; and a determination unit adapted to execute a process of comparing the feature amount of the sound extracted by the extraction unit with a feature amount of a specific sound in accordance with the situation of the subject to be imaged detected by the detection unit, thereby determining whether the sound contains the specific sound.
US10109298B2 Information processing apparatus, computer readable storage medium, and information processing method
An information processing apparatus including: a memory, and a processor coupled to the memory and the processor configured to: detect a plurality of sounds in sound data captured in a space within a specified period, classify the plurality of sounds into a plurality of kinds of sound based on similarities of the plurality of sounds respectively, and determine a state of a person in the space within the specified period based on counts of the plurality of kinds of sound.
US10109294B1 Adaptive echo cancellation
Systems and methods for disabling adaptive echo cancellation functionality for a temporal window are provided herein. In some embodiments, audio data may be received by a voice activated electronic device, where the audio data may include an utterance of a wakeword that may be subsequently followed by additional speech. A start time of when the wakeword began to be uttered may be determined by the voice activated electronic device, and the voice activated electronic device may also send the audio data to a backend system. Adaptive echo cancellation functionality may be disabled at the start time. The backend system may determine an end time of the speech, and may provide an indication to the voice activated electronic device of the end time, which in turn may cause the voice activated electronic device to enable the adaptive echo cancellation functionality at the end time.
US10109292B1 Audio systems with active feedback acoustic echo cancellation
An audio system includes an external microphone to receive a near-end audio content and a loudspeaker transducer and a corresponding enclosure defining an acoustic chamber. An internal pressure-gradient microphone is positioned in the acoustic chamber to detect a radiated output from the loudspeaker transducer. The audio system also includes a processor and a memory having instructions that, when executed by the processor, cause the audio system to receive a near-end signal from the external microphone and a reference signal from the internal microphone. The instructions, when executed, further cause the processor to cause the audio system to filter the reference signal from the near-end signal to define a clean near-end signal, and to emit the clean near-end signal. Related principles are described by way of reference to method and apparatus examples.
US10109288B2 Dynamic range and peak control in audio using nonlinear filters
An audio encoding device is described herein. The audio encoding device includes a compressor that is based on a nonlinear filter. In particular, the nonlinear filter may be selected from the class of edge-preserving smoothing filters, which avoids common artifacts of conventional compressors. Edge-preserving smoothing filters have been used in image processing algorithms for their de-noising properties while preserving edges in the image. These properties are useful for audio compression because macro-dynamic loudness changes can be tracked precisely while micro-dynamic loudness changes can be ignored for the compression. Due to these advantages, more aggressive compression can be achieved with less distortion.
US10109286B2 Speech synthesizer, audio watermarking information detection apparatus, speech synthesizing method, audio watermarking information detection method, and computer program product
According to an embodiment, a speech synthesizer includes a source generator, a phase modulator, and a vocal tract filter unit. The source generator generates a source signal by using a fundamental frequency sequence and a pulse signal. The phase modulator modulates, with respect to the source signal generated by the source generator, a phase of the pulse signal at each pitch mark based on audio watermarking information. The vocal tract filter unit generates a speech signal by using a spectrum parameter sequence with respect to the source signal in which the phase of the pulse signal is modulated by the phase modulator.
US10109283B2 Bit allocating, audio encoding and decoding
A bit allocating method is provided that includes determining the allocated number of bits in decimal point units based on each frequency band so that a Signal-to-Noise Ratio (SNR) of a spectrum existing in a predetermined frequency band is maximized within a range of the allowable number of bits for a given frame; and adjusting the allocated number of bits based on each frequency band.
US10109280B2 Blind diarization of recorded calls with arbitrary number of speakers
In a method of diarization of audio data, audio data is segmented into a plurality of utterances. Each utterance is represented as an utterance model representative of a plurality of feature vectors. The utterance models are clustered. A plurality of speaker models are constructed from the clustered utterance models. A hidden Markov model is constructed of the plurality of speaker models. A sequence of identified speaker models is decoded.
US10109275B2 Word hash language model
A language model may be used in a variety of natural language processing tasks, such as speech recognition, machine translation, sentence completion, part-of-speech tagging, parsing, handwriting recognition, or information retrieval. A natural language processing task may use a vocabulary of words, and a word hash vector may be created for each word in the vocabulary. A sequence of input words may be received, and a hash vector may be obtained for each word in the sequence. A language model may process the hash vectors for the sequence of input words to generate an output hash vector that describes words that are likely to follow the sequence of input words. One or words may then be selected using the output word hash vector and used for a natural language processing task.
US10109273B1 Efficient generation of personalized spoken language understanding models
Features are disclosed for maintaining data that can be used to personalize spoken language understanding models, such as speech recognition or natural language understanding models. The personalization data can be used to update the models based on some or all of the data. The data may be obtained from various data sources, such as applications or services used by the user. Personalized spoken language understanding models may be generated or updated based on updates to the personalization data or some other portion of the stored personalization data. Generation of personalized spoken language understanding models may be prioritized such that the generation process accommodates multiple users.
US10109269B2 High and low frequency sound absorption assembly
A sound-absorption assembly comprises a tubular-shaped body having ends closed respectively by first and second microperforated tensioned flexible sheets and at least one planar diaphragm disposed inside the tubular body between the microperforated flexible sheets so as to delimit two spaces between said sheets.
US10109266B1 Automatically adjusting keyboard divide
In the present invention, a user is capable of choosing manually or automatically a point on a chosen keyboard where a division will occur. For musical/artistic reasons, this point must regularly change. To accommodate this need, the user can store that location in an existing preset/restore system and recall it upon demand with other settings.
US10109263B1 System for support and resonation of a musical instrument
This is a universal support system for bar percussion instruments. It can support any size and type bar percussion instrument, in any size snare basket, with any snare basket arm bracket variations. When used in a snare basket having a ball joint, the system can tilt the bar percussion instrument into infinitely many positions, enabling performance art never before possible with this type of instrument.
US10109262B2 Apparatus and method for double reed assembly
A method for assembling a double reed mouthpiece for use within an oboe utilizes heat shrink tubing to affix a folded cane to the staple of the mouthpiece. The staple is mounted on a ligating stand having a heatshield that protects a cork sleeve around the staple. Heat shrink tubing and a folded cane are then placed over the exposed proximal end of the staple. A clamp holds the folded cane in place. Heated air is used to ligate and affix the folded cane to the staple. The heatshield prevents damage to the cork sleeve. The heat shrink tubing securely affixes the folded cane to the staple.
US10109256B2 Display panel
A driver IC has a rectangular shape, and includes a first input terminal group in which first input terminals are disposed at intervals along a first long side, that is opposite a side that faces a display section, from a first short side. A second input terminal group is provided in which second input terminals are disposed at intervals along a second long side that faces the display section, from the first short side. An output terminal group is provided in which output terminals that output signals to the display section are disposed at intervals along the second long side from a position, which is spaced apart for a predetermined distance from where the second input terminals are disposed, to a second short side. A terminal group is not provided at positions that oppose the output terminal group at the first long side.
US10109254B2 Video processing circuit, video processing method, electro-optical device, and electronic apparatus
A video processing circuit detects a boundary between a first pixel to which an application voltage which is a first voltage is applied, and a second pixel to which an application voltage which is a second voltage higher than the first voltage is applied, based on a video signal indicating a video which alternately switches a first video and a second video which is obtained by moving in parallel with the first video for each unit frame, corrects the application voltage such that a fringe electric field occurring at the boundary is decreased, when determining a boundary detected by the boundary detection unit in a kth unit frame does not exist in a (k−2)th unit frame, and the boundary is a boundary which is moved from a (k−1)th unit frame to the kth unit frame, and outputs the corrected video signal such that the liquid crystal panel is driven.
US10109252B2 Gate driving circuit and a display device including the gate driving circuit
A gate driving circuit includes driving stages. Each of the driving stages applies each of gate signals to each of gate lines of a display panel. A k-th (k is a natural number equal to or greater than 2) driving stage includes a first output transistor, a capacitor, and first and second control transistor. The first output transistor includes a control electrode connected to a first node, an input electrode receiving a clock signal, and an output electrode outputting a k-th gate signal. The capacitor is connected between the output electrode of the first output transistor and the control electrode of the first output transistor. The first control transistor applies a first control signal to a second node to control a voltage of the first node before the k-th gate signal is output. The second control transistor is diode-connected between the second node and the first node.
US10109250B2 Shift register and driving method thereof, gate driving circuit and display apparatus
There are presented a shift register and a driving method thereof, a gate driving circuit and a display apparatus. The shift register includes a first feedback module and a pull-down module, wherein the first feedback module comprises at least two feedback units, control terminals of respective feedback units are connected to different control points respectively, each feedback unit has an input terminal connected to a first level input terminal and an output terminal connected to a first node, the first node is connected to a control terminal of the pull-down module, and the pull-down module has an input terminal connected to the first level input terminal and an output terminal connected to a signal output terminal of the shift register. The shift register is used to enhance noise resistance capability of the shift register.
US10109249B2 Display device
According to one embodiment, a display device includes substrates with pixels, a pixel electrode in each of the pixels, a display select circuit connected to the electrode, which supplies display and non-display voltages, a power line to which first and second voltages are supplied, a memory device connected to the power line and the display select circuit, a voltage select circuit which selects a voltage to be supplied to the power line from the first and second voltages, and a clock circuit which generates a clock signal. The memory device controls the display select circuit using the first and second voltages, and the first voltage select circuit selects the first or second voltages in synchronism with the clock signal.
US10109248B2 Method and device for adjusting liquid crystal display
A method for adjusting a liquid crystal display, includes: changing a voltage applied by a source circuit of the liquid crystal display, and measuring transmittance of the liquid crystal display at different values of the applied voltage; determining, according to a corresponding relationship between the applied voltage and the measured transmittance, a critical applied voltage that corresponds to a maximum measured transmittance of the liquid crystal display; and determining an operating voltage of the source circuit according to the critical applied voltage, and adjusting the applied voltage to the operating voltage.
US10109242B2 Display device and finder device
This finder display device is provided with a liquid crystal panel, a backlight, and a light source driving section. The backlight has a light guide having a side near which first to sixth light sources are disposed. The light source driving section sets the first and fifth light sources as a first sub-light source group, the second and sixth light sources as a second sub-light source group, and the third and fourth light sources as a third sub-light source group, and periodically supplies driving pulses to the first to third sub-light source groups at respectively different timings. The light source driving section controls the amounts of light of the light source groups by changing the pulse widths of the driving pulses.
US10109240B2 Displays with multiple scanning modes
An electronic device may include a display such as a light-emitting diode display. The electronic device may be a head-mounted device that provides a virtual reality or augmented reality environment to a user. To reduce artifacts in the display, a display may be operable in both a normal scanning mode and a partial scanning mode. In the normal scanning mode, every row of the display may be scanned in each frame. In the partial scanning mode, only a subset of the rows of the display may be scanned in each frame. The display may have a higher refresh rate in the partial scanning mode than in the normal scanning mode. The gate driver circuitry may include a shift register that includes a plurality of register circuits. At least one register circuit may have a first input and a second input that is different than the first input.
US10109235B2 Compensation circuit, AMOLED structure and display device
The present invention relates to the field of display apparatus, more specifically, to a compensation circuit, an AMOLED structure and a display device. Said circuit comprises a plurality of pixel units, each for the plurality of pixel units includes at least one light emitter, and each of said pixel units comprises: an anode initialization signal interface, a CST initialization port, a data control port and an enable signal control port. Compared with the prior art, the advantages of the present invention are: according to the invention, there is no need to individually set up an anode initialization signal line, the umber of the signal lines are reduced from 4 to 3, which is benefit for achieving the design of the product HPPI. And the signal control lines reduce the space occupied by jumper wire during the connection process, which is benefit to the design of narrow border products.
US10109230B2 Systems and methods for storing digital content
System and method for storing digital content for display on a display device, comprising at least one digital content item, configured to be displayed on the display device, and a service cloud comprising a secure storage system, configured to store digital content, a communication controller, configured to communicate with the display device, a provisioning engine, configured to control the provisioning of digital content on the display device, a service management system, configured to collect data reflecting operational status of the display device, a server, configured to interface with an application running on a computer with memory and processor for selection and control of digital content for display, an ingestion engine, configured to control importation of digital content, an external content gateway, configured to transfer digital content from outside the service cloud to the display device, and a live data feed gateway, configured to provide over-the-top content to the display devices.
US10109229B2 Display panel driving circuit and compensation method thereof
The present invention provides a display panel driving circuit and compensation method thereof. The display panel driving circuit comprises a near end load, a far end load, an operating circuit and a pre-charging control circuit. The operating circuit is configured to receive display data. The pre-charging control circuit is coupled to the near end load and the far end load respectively. The pre-charging control circuit outputs a first signal and a second signal to the near end load and the far end load respectively according to the display data that a first waveform from the near end load is the same as a second waveform from the far end load.
US10109227B2 Apparatus for controlling brightness of mobile phone screen
Embodiments of the present invention provide an apparatus for controlling brightness of a mobile phone screen, which includes: a mobile phone screen light source, a silicon-controlled dimmer, a rectifier processing module, a first constant current controller processing module, a second constant current controller processing module, an electrolytic capacitor processing module, and a third constant current controller processing module, since the first constant current controller processing module can be used to provide an anode forward current necessary to sustain conduction of the silicon-controlled dimmer, the problem of screen flickering in a switch changeover state can be avoided.
US10109224B1 Methods and devices for using aerial vehicles to create graphic displays and reconfigurable 3D structures
Assemblies for creating graphic displays and art are disclosed. The assemblies include at least one vehicle that is capable of flight; a series of light emitting elements independently affixed to the vehicle or mounted to one or more radially extending elements; an axis around which the radially extending elements are configured to rotate; and at least one motor that is configured to cause the axis and the radially extending elements to rotate. Rotation of the radially extending elements generates a graphic display produced by the light emitting elements (through a “persistence of vision” optical illusion). Methods of using such assemblies are also disclosed, such as methods for producing a graphic display (including aggregated graphic displays), methods for creating three-dimensional structures, and methods for camouflaging aerial vehicles and other objects.
US10109220B2 Instrument skill instruction and training system
Technology is described for a system to provide skill training in various fields, including professional fields involving hand-held instruments. The system senses a user's manipulation of an instrument or tool using various sensors, e.g., for a dental tool, an array of pressure sensors in the tool's tip, grip sensors, and sensors to track the position and movement of the tool. The system includes lessons to train users in the proper methods to manipulate the tool and provides guidance and feedback based on the user's performance to build the user's skills, prevent injury, and document competency.
US10109212B2 Processing system and display device
According to one embodiment, an processing system comprises a memory, a receiver, and a transmitter. The memory stores first target information indicating a first target related to a first user, second target information indicating a second target related to a second user, a first rate indicating an achievement rate in a case where the first user has achieved the first target, and a second rate indicating an achievement rate in a case where the second user has achieved the second target. The receiving unit receives first situation information of the first user and second situation information of the second user. The transmitting unit transmits display information obtained by combining a first degree of achievement of the first target derived from the first situation information, a second degree of achievement of the second target derived from the second situation information, the first rate, and the second rate.
US10109208B2 LIDAR-based vehicle distance measurement system
A system and method for determining the distance between at least one point on a vehicle and at least one projected area off of the vehicle includes receiving, with a processor, sensor signals indicative of LIDAR data for the projected area off the vehicle; applying, with the processor, a linear estimation algorithm to filter out noise within the LIDAR data and define a surface plane for the projected area; evaluating, with the processor, the LIDAR data against a vehicle state model; determining, with the processor, the distance between the at least one point on the vehicle and the at least one projected area off the vehicle; and commanding a response in the vehicle controls.
US10109206B2 Flight control apparatus and unmanned aerial vehicle equipped with same
A flight control apparatus that prevents an unmanned aerial vehicle from deviating from a predetermined flight-permitted area and is able to forcibly restrain it even when abnormality is present in the flight environment and the operation of the respective mechanisms of the vehicle, and an unmanned aerial vehicle equipped with this apparatus. The apparatus includes current position acquiring means for acquiring a flight position of the vehicle, flight-permitted area storing means, and deviation preventing means, wherein it forcibly makes the body unable to fly when: the current position acquiring means has become unable to acquire the position of the body, the flight position of the body is in the vicinity of the boundaries between the flight-permitted area and space external thereto or keeps out of the flight-permitted area for a predetermined time or longer, or the body has moved away a predetermined distance or more from the flight-permitted area.
US10109203B2 Methods and systems for presenting en route diversion destinations
Methods and systems are provided for indicating suggested or recommended diversion destinations with respect to segments of a planned route of travel. One exemplary method of presenting potential diversion airports for an aircraft involves identifying a flight path segment of a plurality of flight path segments between a departure location and a destination location based on a flight plan from the departure location to the destination location and identifying a subset of airports satisfying one or more filtering criteria with respect to the flight path segment. From among that subset, a recommended diversion airport is identified based on a viability ranking of the subset of airports with respect to the flight path segment and indication of the recommended diversion airport for the flight path segment is provided to a pilot or other user.
US10109202B2 Method and system for determining a vertical trajectory of an aircraft
A method and system for determining in real time a vertical trajectory of an aircraft is provided. The method includes a step for providing an initial vertical trajectory comprising an initial phase for changing flight level according to a first slope, between a first point at a first altitude, and a second point at a second altitude, at least one step for modifying the vertical trajectory, comprising a phase for detecting a triggering element when the aircraft is at the first altitude, when said triggering element is detected, and a phase for determining a modified vertical trajectory, said modified vertical trajectory comprising a modified phase for changing flight level according to a second predefined slope, from a modified point at said first altitude, distinct from said first point, to said second altitude.
US10109200B1 Graphical multi-layer light alert display and control method thereof
A multi-layer light alert display apparatus and control method thereof are provided. The apparatus includes: an illumination device configured to illuminate a graphic generating layer, a plurality of graphic generating layers, each graphic generating layer of the plurality of graphic generating layers being configured to generate a graphic, and a controller configured to control the illumination device to allow light to pass through at least one graphic generating layer of the plurality of graphic generating layers so that the light causes a graphic corresponding to the at least one graphic generating layer to be displayed on a surface.
US10109195B2 Selectively controlling a self-driving vehicle's access to a roadway
A processor-implemented method and/or computer program product selectively blocks a self-driving vehicle's access to a roadway. A vehicle interrogation hardware device receives an autonomous capability signal from an approaching self-driving vehicle. One or more processors compare the predefined roadway conditions to current roadway conditions of the access-controlled roadway. In response to the predefined roadway conditions matching the current roadway conditions of the access-controlled roadway within a predetermined range, the processor(s) determine whether the level of autonomous capability of the approaching self-driving vehicle is adequate to safely maneuver the approaching self-driving vehicle through the current roadway conditions of the access-controlled roadway. In response determining that the level of autonomous capability of the self-driving vehicle is not adequate to safely maneuver the approaching self-driving vehicle through the current roadway conditions of the access-controlled roadway, an automatic barricade controlling device positions an automatic barricade to block the approaching self-driving vehicle from accessing the access-controlled roadway.
US10109191B2 Method of quickly detecting road distress
In various embodiments, the invention involves methods and systems suitable for roadway monitoring, mapping, and maintenance. The probability of a road distress is calculated by combining various sources of data, and automatic alerts are generated to request mobilization of a road repair resource. Various methods are included to increase the accuracy of the probability calculations.
US10109190B1 Emergency vehicle warning system
An emergency vehicle warning system is a portable electronic device that detects emergency signals coming from emergency vehicles within a given radius and generates a warning in the form of audible signals, vibration, and/or lights within the vehicle to provide advanced warning to the occupants of the vehicle providing additional time to pull safely over to the side of the road to avoid accidents or tickets that may result from the failure to yield to emergency vehicles.
US10109187B2 Vehicle detection apparatus
Apparatus is disclosed for monitoring use of a carriageway, the carriageway having two or more lanes (12, 14, 16) for use by vehicles travelling in a single direction A, the apparatus including: a pair of inductive loops (20abc, 22abc) on or in the surface of each lane (12, 14, 16), the loops in the pair being positioned substantially side-by-side across the lane (12, 14, 16) and the pairs of loops (18a, 18b, 18c) being positioned substantially side-by-side across the carriageway, each pair of loops (18abc) substantially extending across the full width of the lane (12, 14, 16), and each loop having a length in the direction of vehicle travel which is substantially shorter than the width of the loop across the lane; a loop controller associated with each loop, each loop controller energising its associated loop and carrying out measurements of the inductance of its associated loop; and processing means for receiving the measurements from the loop controllers, and for using the measurements for calculating the estimated position of vehicle(s) on the carriageway.
US10109184B2 Probe based variable speed sign value
Systems, methods, and apparatuses are disclosed for predicting or estimating the value of a variable speed sign (VSS). A variable speed sign is identified. Probe data is collected at one or more vehicles in proximity to the variable speed sign. The speeds of the vehicles are included in or derived from the probe data. A statistical analysis is performed on the probe data. A speed limit value for the variable speed sign is determined based on the statistical analysis.
US10109181B2 Gesture-based control device for controlling an electrical load
A control device such as a wall-mounted device, a remote control device, or a retrofit remote control device is configured to control one or more electrical loads in a load control system. The control device includes a gesture-based user interface for applying advanced control over the one or more electrical loads. The types of control include absolute and relative control, intensity and color control, preset, zone, or operational mode selection, etc. Feedback is provided on the control device regarding a status of the one or more electrical loads or the control device.
US10109180B1 Wireless hall light box
An apparatus includes a wireless transceiver and a processor. The wireless transceiver may be configured to communicate wirelessly via a wireless network with an annunciator remotely located from the apparatus and a plurality of call light boxes remotely located from the apparatus. The processor may be configured to (i) control reception of an alarm message from one or more of the call light boxes in response to an event, (ii) illuminate a hall indicator in response to reception of the alarm message, (iii) receive a cancellation message from at least one of (a) one or more of the call light boxes and (b) the annunciator that cancels the event, and (iv) extinguish the hall indicator in response to cancellation of the event. The hall indicator may change color over time until the event is canceled.
US10109170B2 Method and system for implementing alarms for medical device through mobile device
Provided are a method and system for implementing alarms for a medical device through a mobile device. The method includes: storing details of examination of a specimen (hereinafter, referred to as examination details) in the medical device, wherein the storing is performed by the medical device; accessing the medical device and establishing a connection with the medical device, wherein the accessing and the establishing of the connection is performed by the mobile device; reading the examination details stored in the medical device, wherein the reading is performed by the mobile device; analyzing the read examination details, wherein the analyzing is performed by the mobile device; and implementing an alarm if the result of analysis satisfies a predetermined criterion, wherein the implementing is performed by the mobile device.
US10109168B1 Motion localization based on channel response characteristics
In a general aspect, detected motion is localized based on channel response characteristics. In some aspects, channel responses based on wireless signals transmitted through a space between wireless communication devices are obtained. A motion detection process is executed to detect motion of an object in the space based on the channel responses, and the channel responses are analyzed to identify a location of the detected motion within one of a plurality of regions within the space.
US10109167B1 Motion localization in a wireless mesh network based on motion indicator values
In a general aspect, a location of detected motion in a space is determined. In some aspects, motion of an object in a space is detected based on wireless signals communicated through the space by a wireless communication system that includes multiple wireless communication devices. Each wireless signal is transmitted and received by a respective pair of the wireless communication devices. Motion indicator values are computed for the respective wireless communication devices. The motion indicator value for each individual wireless communication device represents a degree of motion detected by the individual wireless communication device based on a subset of the wireless signals transmitted or received by the individual wireless communication device. A location of the detected motion in the space is determined based on the motion indicator values.
US10109166B1 System and method for a security checkpoint using radio signals
A security device for monitoring the radio frequency signals generated by mobile phones and similar mobile computing and communication devices. The security device employs an antennae array and computer process that are configured to detect and provide a “fingerprint” for a mobile device based on the unique identifiers contained with the radio and other wireless signals utilized by such mobile device. The “fingerprint” that is obtained can be used to keep track of mobile devices as those devices enter and leave the area of the security device. Moreover, the security device can provide an alert when any new, foreign, or otherwise unrecognized device is within range of the security device and share “fingerprints” and alerts with other security devices in its network.
US10109165B2 Notification device
The present disclosure relates to notification devices. The teachings thereof may be embodied in methods and devices for providing an alarm signal, e.g., a notification device having multiple different alarm strengths comprising: a housing with a viewing opening; an alarm component which emits an alarm signal; a drive circuit comprising a drive end and a setting end, the drive end connected to the alarm component; and a replaceable jump wire assembly comprising a mark and a conductive element with a one-to-one correspondence between the mark and an electrical characteristic of the conductive element. The drive circuit may determine an alarm signal strength in response to an input of the setting end. Each replaceable jump wire assembly may be connected to the setting end of the drive circuit and, when connected, display the mark for viewing through the viewing opening.
US10109164B2 Notification and alert method for person(s) and/or devices(s)
Systems and methods of notification and alert activation and delivery via transmission to users wearing technology designed for single and/or multiple media types are contemplated in which (a) a communication pathway is established, for instance either a wireless receiver and/or transceiver and/or a physical (e.g., wired) connection, that (b) allows an activation method type to provide an alert/notification to one-to-many persons (i.e., users) and/or, one-to-many devices in an addressable manner. The overall method consists of devices (including for example, wearable media with external and/or integrated delivery technology) that are actively listening on a communication pathway. If an activation method is utilized over the communication pathway and an activation is designated for specific device(s) assigned within the communication pathway, then a delivery method for that device(s) is invoked that processes and delivers the non-primary media (audio and visual) based on the command type, any local settings and the media type transmitted.
US10109162B2 Haptic effect enabled system using fluid
A haptic effect enabled system generates a haptic effect using an electric potential responsive fluid. A haptic enabled apparatus includes a fluid and a substrate. The fluid is responsive to an electric field. The substrate is at least partially flexible and defines a channel. The fluid is positioned within at least a portion of the channel. A portion of the substrate proximal to the fluid is stiffer than a portion of the substrate spaced from the fluid, thereby creating a haptic effect.
US10109157B1 Networked gaming system enabling a plurality of player stations to play independent games with dealer assisting display
A system, apparatus, and computer readable storage to implement a networked blackjack game that enables a plurality of players to wager on one or more dealers at different dealing stations dealing independent games simultaneously. A live video is captured on each dealing station and simulcast to player stations where players are playing at. Players can bet on any combination of the games that are being broadcast. Players at player stations can be playing in a tournament mode or in regular play using the same dealer stations. A touch screen display can be used at each dealer/dealing station in order to instruct the dealer as to which actions the dealer should take, such as dealing cards, etc.
US10109155B2 Operating a distributed computer system for a duration-limited poker tournament
Described herein are techniques for operating a distributed computer system to implement a duration-limited online poker tournament. Also described herein are particular techniques for operating a distributed computer system to implement such a duration-limited online poker tournament. In some embodiments, a duration-limited online poker tournament is operated such that each player begins with a set number of funds, but those funds are not themselves used during gameplay. Rather, in the tournament each player is allotted a number of chips and, at an outset of each hand, each player's chips are reset to this number, regardless of the chips won or lost in preceding hands. At the end of the tournament, a player's winnings or losses may be determined based on the chips won or lost across the hands of the tournament.
US10109150B2 Method of gaming, a gaming system and a game controller
Method and systems of gaming are provided herein. One method includes receiving a credit wager to initiate play of a base game. The method also includes awarding, in a feature game, at least two game rounds including at least an initial game round and a subsequent game round. The method also includes generating a plurality of candidate game outcomes for a plurality of game rounds, and determining, for each of the plurality of candidate game outcomes, an expected benefit to be gained from the respective candidate game outcome when generating a subsequent game outcome in the subsequent game round. The method still further includes selecting a candidate game round of the plurality of candidate game rounds having a candidate game outcome of the plurality of candidate game outcomes associated with a greatest expected benefit, and displaying the selected candidate game round on a display as the initial game round.
US10109148B2 Casino operations management system with player cage and multi-transaction log
A system and computer program for managing casino operations. The system includes a player cage module configured to manage financial transactions between the player and casino, including cash transactions for each player. The player cage module includes a cashier interface that stores information regarding all transactions performed by a cashier during a time period. The system further includes a multi transaction log module configured to store multiple transactions for an individual player and to merge transactions for each said individual player, the multi transaction log being further configured to identify unknown players based on at least one image received of each unknown player. The system permits tracking and reporting of suspicious transactions. The system further permits tracking and reporting when a player's transactions exceed a reporting threshold.
US10109145B2 Apparatus and method for distributing ophthalmic lenses
An apparatus for dispensing ophthalmic lens packages having a pushing means and methods of its use are described herein.
US10109144B2 Complex beverage grabbing vending machine and method for selling beverages through the same
A complex beverage grabbing vending machine includes a machine table and a plurality of bottle mounting frames. The machine table is configured with an accommodation space having a drop port with a detection element, and the upper side of the accommodation a crown block track to which a gripper with non-slip elements is coupled pivotally; the gripper is configured with a hanging line capable of wound to shorten or unwound to elongate; the machine table is further configured with an operation station having an operation lever and operation button, coin slot in electric communication with the operation station and gripper, refund button, and an extract port in communication the drop port; the bottle mounting frames each having a plurality of mounting holes are configured in the accommodation space. Whereby, the present invention is capable of beverage sale and has game fun.
US10109142B2 System and method for selective encryption of input data during a retail transaction
A retail environment having retail terminals with data entry point devices selectively encrypts input received by the data entry point devices and passes the encrypted data to a security module. The selective encryption is based on whether or not sensitive or confidential information, such as a personal identification number (PIN) associated with a debit card, is being input. To prevent hacking of the software of the retail terminal, content destined for display on the retail terminal is authenticated prior to display. In this manner, the retail terminal may be assured that confidential information is input only when desired, and thus may be encrypted only as needed.
US10109141B2 Method and apparatus for establishing trust in smart card readers
A method for managing a smart card system includes testing a smart card reader for trustworthiness. An indication of the trustworthiness is provided via a smart card.
US10109132B2 Sampling method and sampling apparatus for anti-counterfeiting information about cash note
Disclosed are a sampling method for anti-counterfeiting information about a cash note, and a sampling apparatus for anti-counterfeiting information about a cash note, which executes the method. The sampling method for anti-counterfeiting information about a cash note comprises: through differences collected between sensors, utilizing a law of the differences to restore spatially coupled power-frequency of low-frequency electromagnetic interference signals acquired by an effective signal sensor (21); and then performing common-mode signal elimination on voltage waveform data corresponding to the anti-counterfeiting information, thereby thoroughly elimination the spatially coupled power-frequency or low-frequency electromagnetic interferences that magnetic signal sensors suffer from during the collection of magnetic anti-counterfeiting signals.
US10109131B2 Sensor device including magnetoresistive sensor element and pre-magnetization device
A measuring device for measuring magnetic properties of the surroundings of the device includes at least one magnetoresistive element extending in a line direction, and a support field device generating a magnetic support field in an area over the line direction. A pre-magnetization device of one or more magnets is arranged at a distance from the sensor line in a direction vertical to the line direction and extending parallel to the line direction. The pre-magnetization device is arranged relative to the sensor line such that the fields of the pre-magnetization device and the support magnetic field overlap to provide an overlapping magnetic field with a field strength component pointing in the line direction that is greater at one location on the sensor line than the strength of a field component pointing vertically toward the line direction and not in the direction of the height of the magnetoresistive element.
US10109128B2 Access control system to interference area
An access control system configured to manage access of a worker to an interference area that the worker and a robot share, includes the indicating lamps which are disposed at least in four directions from a center of the interference area, a door which opens and closes a gate of the interference area, a lock device which locks and unlocks the door, and a control device which controls the indicating lamps and the lock device corresponding to the operation of the robot.
US10109117B2 Aircraft performance computation
A computer implemented method of computing performance for an aircraft, comprises the steps of collecting data from a plurality of data sources comprising data sources of avionics type and external data sources of non-avionics type; processing the data collected in an electronic device of EFB or electronic flight bag type; and undertaking the performance computation. Developments describe the extraction of data from images or audio streams; the manipulation of data of alarm, INOP, aircraft status, air conditioning and anti-ice, runway, ATIS, meteorological and/or NOTAM type; the interfaces with an FPS or flight planning system and/or a CMS or centralized maintenance system. System aspects and software aspects are described.
US10109115B2 Modifying vehicle fault diagnosis based on statistical analysis of past service inquiries
A system and method of modifying a vehicle service database includes: accessing a database containing previously-received symptom text that has been associated with a vehicle identifier and one or more vehicular service solutions for the previously-received symptom text; determining a statistical likelihood that one or more additional vehicular service solutions apply to previously-received symptom text based on a correlation between the previously-received symptom text and additional vehicular service solutions; determining that the statistical likelihood is above a predetermined threshold; and associating the previously-received symptom text with the additional vehicular service solutions.
US10109114B1 Technologies for merging three-dimensional models of dental impressions
Technologies for merging three-dimensional models of dental impressions include a computing device that generates multiple three-dimensional models that are each indicative of a dental impression of a user's dental arch. The models may be generated by scanning the dental impressions. The computing device determines whether a model is indicative of the complete anatomy of the user's arch and, if not, merges multiple models with a merge strategy to generate a merged model. The models may be merged by aligning geometry of the models, selecting geometry from one of the models using the merge strategy, and generating the merged model that includes the selected geometry. The merge strategy may include selecting from the model associated with the dental impression that includes the most detail of the user's anatomy or selecting from the model with the greatest depth.
US10109109B2 Method for inspecting a security document
The invention relates to a method for inspecting a security document (10), the use of an augmented reality system (20) for inspecting a security document (10) as well as an augmented reality system (20). One or more first items of information of the security document (10) are captured by means of an augmented reality system (20), in particular a pair of smartglasses. The one or more first items of information are then checked by comparison with a database (40). Furthermore, one or more of the results of the check of the one or more first items of information are stored and/or one or more of the results of the check of the one or more first items of information are output by means of the augmented reality system (20).
US10109105B2 Method for immediate boolean operations using geometric facets
A method for performing Boolean operations using a computer to create geometric models from primary geometric objects and their facets, comprises mapping rendering facets to extended triangles that contain neighbors, building intersection lines, splitting each triangle through which an intersection line passes, determining each triangle is obscure or visible, and regrouping the triangles to form one or more geometric objects. This method does not utilize the most popular data structures CSG and B-REP in CAD/CG/Solid Modeling systems, but has the advantages of both CSG and B-REP: easy to implement and so flexible that it can handle concave and convex geometric shapes, swept and extruded geometric objects, and it is able to generate variant and editable models.
US10109100B2 Adaptive sampling of pixels
Adaptive sampling of pixels is disclosed. In some embodiments, an initial rendering of a scene that determines texture at each portion of the scene is generated, and a ray traced rendering of the scene is generated by tracing an initial sample of rays. The following steps are iterated until all portions of the ray traced rendering satisfy a noise threshold: subtract the initial rendering of the scene from the ray traced rendering of the scene to determine a measure of noise at each portion of the ray traced rendering and trace another sample of rays in the ray traced rendering for each portion of the ray traced rendering that does not satisfy the noise threshold. The completed ray traced rendering is outputted. Different portions of the completed ray traced rendering are sampled with different numbers of samples of rays.
US10109098B2 Systems and methods for displaying representative images
A system, method, and computer program product for displaying representative images within a collection viewer is disclosed. The method comprises receiving an indication of a new orientation for the collection viewer, displaying a sequence of animation frames that depict an in-place rotation animation for the representative images, generating a rotation angle in a sequence of rotation angles, and displaying a rendered representative image for each of the two or more representative images by rendering the two or more representative images, wherein each rendered representative image is rotated according to the rotation angle.
US10109096B2 Facilitating dynamic across-network location determination using augmented reality display devices
An augmented reality system includes a central server, a local server an augmented reality user device. The central server includes account information for a customer and institution information. The institution information includes employee specialty data and employee office data. The local server includes location information for the customer and a plurality of employees. The augmented reality user device displays account information and displays a location of one of the employees.