| Document | Document Title |
|---|---|
| US09942108B2 |
Network service aware routers, and applications thereof
In an embodiment, a computer-implemented method provides a service on a network. The method includes the following steps: (a) requesting, on a router, executable instructions from a remote server, the executable instructions specifying how the router is to operate to provide a service requested for a user of the network; (b) receiving the instructions; (c) initializing, on the router, a thread to execute the received instructions; (d) determining that a configuration of the router has changed; and (e) when the configuration of the router is determined to have changed, executing, on the initialized thread, the instructions to apply the service in accordance with the change in the router's configuration. |
| US09942107B2 |
Computer system including plural computer nodes synchronized with each other
A computer system includes a plurality of computer nodes, each including an external communications unit. An application unit executes processing in accordance with a processing request. A synchronization unit establishes synchronization of the processing between each computer node and other computer nodes. The processing is executed by each computer node, and an inter-node communications unit executes transmission/reception of information between each computer node and the other computer nodes. The synchronization unit transmits the processing request to the other computer nodes via the inter-node communications unit, the processing request being received by the external communications unit. Also, the synchronization unit receives processing requests from the other computer nodes as well via the inter-node communications unit. Based on the number of the computer nodes that have received the same processing request via the external communications units, the synchronization unit selects a processing request that should be executed by the application unit. |
| US09942104B2 |
Network connectivity wizard to support automated creation of customized configurations for virtual private cloud computing networks
A user-defined virtual private cloud computing network is provided that includes a user interface for selecting a plurality of network connectivity features for designing the user-defined virtual private cloud computing network. The virtual private cloud computing network includes tangible storage elements and tangible computing elements selected from a cloud computing network service provider using the user interface, using the user interface each network. The tangible storage elements and tangible computing elements are connected in accordance with network element configuration statements that instantiate actions particular to defined network connectivity features in accordance with defined usage rules. The virtual provide cloud computing network is configured and implemented in accordance with the selected network connectivity features using the tangible storage elements and tangible computing elements. |
| US09942101B2 |
Method and system for collecting topology information
A method of providing topology information about a network to a topology manager is disclosed. The network includes a plurality of sensors each having a sensor ID, and the method includes performing the following steps at each of the plurality of sensors: receiving a stream of packets and identifying a topology trace packet in the stream of packets, wherein the topology trace packet has a destination address and an ID of a previous sensor, including the sensor ID in the topology trace packet, sending the topology trace packet to the destination address, forming a report message so as to include the sensor ID, the previous sensor ID, sending the report to the topology manager; and, providing network addresses of adjacent nodes to the topology manager. |
| US09942098B2 |
Appliance node clusters
An appliance interconnection system and method. The system includes a high speed private local area network (LAN) and a logical cluster of appliances comprising a plurality of physical sub-clusters of appliance nodes. Each node of the appliance nodes includes a different generation node. The plurality of sub-clusters are interconnected via the high speed private LAN. A sub-cluster (N) of the plurality of physical sub-clusters comprises a first plurality of nodes of the appliance nodes. The sub-cluster (N) is associated with a plurality of (M) generation appliances of the logical cluster of appliances. Each appliance of the plurality of (M) generation appliances comprises a same type of appliance. (N) comprises a first cluster number and (M) comprises a first generation number of a first generation. The plurality of sub-clusters, in combination, form a single logical cluster. |
| US09942096B2 |
Abstraction layer and distribution scope for a logical switch router architecture
A tool for forwarding plane support in a distributed system utilizing a three-tiered architecture. The tool receives one or more messages, wherein the one or more messages include a plurality of state information. The tool determines a distribution scope for the one or more messages based, at least in part, on the plurality of state information. The tool determines a destination endpoint ID for the one or more messages, wherein the destination endpoint ID identifies one or more switch units to receive the one or more messages. The tool sends the one or more messages to a forwarding plane agent for distribution to the one or more switch units based, at least in part, on the distribution scope and the destination endpoint ID. |
| US09942095B2 |
Methods and apparatus for selecting a master virtual processor within a switch fabric element
In some embodiments, an apparatus comprises a processing module, disposed within a first switch fabric element, configured to detect a second switch fabric element having a routing module when the second switch fabric element is operatively coupled to the first switch fabric element. The processing module is configured to define a virtual processing module configured to be operatively coupled to the second switch fabric element. The virtual processing module is configured to receive a request from the second switch fabric element for forwarding information and the virtual processing module is configured to send the forwarding information to the routing module. |
| US09942094B1 |
Trusted execution environment-based UICC update
The use of a Trusted Execution Environment (TEE) of a user device to perform Universal Integrated Circuit Card (UICC) update may replace the conventional use of multiple SMS messages to update the UICC of a user device. A UICC update request may be sent to a UICC update service of a wireless communication network via a communication session by a trusted update application that is executing in the TEE. Subsequently, the UICC update service may send a UICC update file to the user device via the communication session for storage in the TEE. A copy of the UICC update file is then transferred from the TEE to modem software of a modem in the user device. The modem software chunks the UICC update files into multiple UICC update data chunks. The data chunks are sent by the modem software to the UICC to update the UICC. |
| US09942090B2 |
Predicting one or more system loss events and proactive system recovery
Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to predicting a system loss event and/or proactive system recovery. Aspects of the present disclosure relate to techniques and apparatus for system loss event (e.g., radio link failure event) geo-coding and proactive system recovery. According to certain aspects, a user equipment (UE) may generate and store information about one or more system loss events associated with the UE. The UE may then predict one or more other system loss events associated with the UE based on this information and take action, based on the prediction to continue communication of the UE. |
| US09942089B2 |
Network resources management by a cloud consumer
A method, hardware device, and/or computer program product manages network resources. A cloud service provider hypervisor server that supports a cloud service provider hypervisor receives a cloud consumer's management information base (MIB) via an application program interface. The cloud consumer's MIB is a portable MIB that is capable of being loaded into multiple cloud service provider hypervisors. A trap receiver in the cloud service provider hypervisor server receives a Simple Network Management Protocol (SNMP) trap from a resource described by the cloud consumer's MIB. The SNMP trap is an SNMP message that describes an event in the resource. The cloud service provider hypervisor server transfers the SNMP trap to a cloud consumer without any interpretation of the SNMP trap by the cloud service provider hypervisor. |
| US09942088B2 |
Fault detection method, gateway, user equipment, and communications system
Embodiments of the present invention provide a fault detection method. The method includes discovering that a fault occurs in a DNS server or a service server related to a UE, and performing, by a gateway, fault detection on the DNS server or the service server. The method also includes, after the fault is rectified, instructing the UE to establish a connection to the DNS server or the service server. Correspondingly, the embodiments of the present invention further provide a gateway, a UE, and a communications system. |
| US09942086B2 |
Apparatus and method for detecting cause of radio link failure or handover failure in mobile communication system
A terminal, a Base Station (BS) and a method for detecting a cause of a Radio Link Failure (RLF) or handover failure are provided. The method includes determining whether an RLF or a handover failure occurs, performing a process of a connection re-establishment or connection establishment to enter a connection mode after encountering the RLF or the handover failure, and transmitting an RLF information report to a BS after entering the connection mode. |
| US09942082B2 |
Modulation and coding for a high altitude platform
Modulation and coding for a high altitude platform is disclosed. An example apparatus includes a gateway antenna configured to communicate with a ground-based gateway station and user antennas configured to provide communication coverage among a plurality of terminals within a specified area on the ground or in the air. Each user antenna is configured to communicate with a cell within the specified area. The example apparatus also includes a processor configured to demodulate and decode a first modulation scheme and a first coding scheme used for a feeder link provided by the gateway antenna, and apply at least a second modulation scheme and a second coding scheme for user links provided in spot beams by the user antennas. The first modulation scheme and the first coding scheme are configured to be relatively more spectrally efficient compared to the second modulation scheme and the second coding scheme for the user links. |
| US09942078B2 |
Methods and apparatus for simultaneous estimation of frequency offset and channel response for MU-MIMO OFDMA
Methods and apparatus are provided for simultaneous estimation of frequency offset and channel response for a communication system, such as a MU-MIMO communication system. An iterative method is provided for estimating frequency offset and channel response for a plurality of frequency resources. The channel response is estimated for a set of users sharing a given one of the frequency resources. In addition, the frequency offset is estimated for the users in the set, wherein the channel response and frequency offset of users not in the set are maintained at their latest updated values. Initially, the channel response of a user can be an ideal channel response and the frequency offset can be approximately zero. |
| US09942074B1 |
Wireless devices and systems including examples of mixing coefficient data specific to a processing mode selection
Examples described herein include systems and methods which include wireless devices and systems with examples of mixing input data with coefficient data specific to a processing mode selection. For example, a computing system with processing units may mix the input data for a transmission in a radio frequency (RF) wireless domain with the coefficient data to generate output data that is representative of the transmission being processed according to a specific processing mode selection. The processing mode selection may include a single processing mode, a multi-processing mode, or a full processing mode. The processing mode selection may be associated with an aspect of a wireless protocol. Examples of systems and methods described herein may facilitate the processing of data for 5G wireless communications in a power-efficient and time-efficient manner. |
| US09942072B1 |
Communications device with adaptive demodulator for PSK and FSK modulations and related methods
A wireless communications device may include a wireless receiver, and an adaptive demodulator coupled to the wireless receiver. The adaptive demodulator is configured to apply first and second bandpass filters to amplitude information of a received signal at first and second frequency bands, respectively, and classify the received signal as one of a PSK modulation type, a second PSK modulation type, and a third FSK modulation type based upon whether a tone exists in the amplitude information of the received signal in one or more of the first and second frequency bands. The adaptive demodulator is configured to adjust a demodulating parameter based upon a classified modulation type of the received signal. |
| US09942062B2 |
Unlock detector, unlock-detecting method and clock and data recovery circuit
An unlock detector includes a checker, an accumulator, and a comparator. The accumulator is electrically connected to the checker, and the comparator is electrically connected to the accumulator. The checker includes several checking units. The checker is configured to receive a sampled data signal and a sampled edge signal, and to check the sampled data signal and the sampled edge signal via the checking units to generate several checking results. The accumulator is configured to generate a counting value in a manner of counting according to the checking results. The comparator is configured to compare the counting value with a threshold to generate an unlock-detecting result. |
| US09942061B2 |
Multipath selection method and device, and storage medium
Disclosed are a multipath selection method and device, and a storage medium. The method includes that: a correlation sequence between a received signal and a local reference signal is acquired by means of a correlation calculation method; a power spectrum of the correlation sequence and an average noise power of the received signal are acquired; according to the average noise power of the received signal, the power spectrum of the correlation sequence is divided into at least one first multipath component area and a second multipath component area according to a pre-set dividing rule; the at least one first multipath component area is searched according to a pre-set first noise threshold, so as to acquire a valid multipath component signal in the at least one first multipath component area; and the second multipath component area is searched according to a pre-set second noise threshold, so as to acquire a valid multipath component signal in the second multipath component area. |
| US09942056B2 |
Methods and systems for automatically monitoring user activity
A method for home automation system is described. In one embodiment, the method may include receiving input regarding a list of predetermined activities. The method may further include receiving monitored activity data of at least one authorized user. The method may further include comparing the received monitored activity data with the received input regarding the list of predetermined activities, and operating at least one aspect of the home automation system based, at least in part, on the comparing. |
| US09942053B2 |
Bit indexed explicit replication using internet protocol version 6
Various systems and methods for performing bit indexed explicit replication (BIER) using IPv6. For example, one method involves receiving, at a node, a packet that includes an IP header. The packet also includes a multicast forwarding entry. The method also involves comparing the multicast forwarding entry with forwarding information stored by the node and selecting a neighbor based on the comparing. The method further includes forwarding the packet to the neighbor. |
| US09942052B2 |
Method and apparatus for providing sponsoring service between user equipments
Provided is a method by a user equipment (UE) for providing a sponsoring service in a wireless communication system, the method comprising: determining at least one UE to be provided with the sponsoring service, accessing to a server providing the sponsoring service, and registering to the server providing the sponsoring service; and transmitting a request of the sponsoring service comprising identification information of the at least one UE, to the server providing the sponsoring service. |
| US09942050B2 |
Method and apparatus for bulk authentication and load balancing of networked devices
A new approach is proposed that contemplates systems and methods to support bulk authentication of a device associated with a user to all cloud-based services the device intends to access in one transaction instead of authenticating the device against each of the services individually. First, the device generates and transmits to one or more authentication service clusters an authentication request that includes its identification and authentication credentials in order to access to a plurality of services. Upon receiving the authentication request, the authentication service cluster(s) authenticate the device for all of the services to be accessed based on the information in the authentication request. Once the device is authenticated, the authentication service cluster(s) then retrieve entitlement information of the services to be accessed by the device, and identify the service clusters/nodes that the device will connect to for the services with the fastest response time. |
| US09942047B2 |
Controlling application access to mobile device functions
There is described a method of controlling application access to predetermined functions of a mobile device. The described method comprises (a) providing a set of keys, each key corresponding to one of the predetermined functions, (b) receiving an application from an application provider together with information identifying a set of needed functions, and (c) generating a signed application by signing the received application with each of the keys that correspond to one of the needed functions identified by the received information. There is also described a device for controlling application access and a system for controlling and authenticating application access. Furthermore, there is described a computer program and a computer program product. |
| US09942045B2 |
System and method for performing secure communications
A server and method for providing a content selection is provided. The server receives content targeting parameters and obtains content items from at least one content site based on the content targeting parameters. The server can further identify content descriptors for the content items and generate a first content cluster from a subset of the content items based on the content descriptors. The server can further generate a second content cluster from a second subset of the content items based on the content descriptors and rank the first and the second content clusters in an order of usefulness. The ranking of the content clusters can be based on at least one of an importance of content, a recentness of the content items and a size of the content cluster. |
| US09942040B1 |
Refreshing public parameters in lattice-based cryptographic protocols
In a general aspect, a parameter is refreshed in a lattice-based cryptography system. In some aspects, a first value of a public parameter is obtained. The first value of the public parameter may have been previously used in an execution of a lattice-based cryptography protocol. A second value of the public parameter is generated based on the first value of the public parameter and random information. The second value of the public parameter is used in an execution of the lattice-based cryptography protocol. |
| US09942034B2 |
Confidential communication management
Systems and methods are provided for confidential communication management. For instance, a server computer can include a protected server key identifier in a response message to a client computer. The protected server key identifier can include a server key identifier that identifies a server private key used to encrypt the response message. The client computer can pass the protected server key back in a subsequent request, so that the server computer can identify the proper server private key to use for decrypting the request message. In another example, a message may include encrypted protocol data (e.g., cipher suite) and separately encrypted payload data. The encrypted payload data can include a plurality of individually encrypted payload data elements. |
| US09942029B2 |
Adaptive envelope extracting apparatus, signal decoding apparatus and short-distance contactless communication apparatus applying the adaptive envelope extracting apparatus, and method thereof
An envelope extracting apparatus includes: a clock extracting device arranged to extract a clock signal of a receiving modulation signal according to a first biasing voltage; and an edge detecting device arranged to generate a detecting signal to indicate an envelope edge of the receiving modulation signal according to a delayed clock signal of the clock signal and a second biasing voltage; wherein the second biasing voltage or a delay time of the clock signal is adjustable. |
| US09942028B1 |
Serial transmitter with feed forward equalizer and timing calibration
A timing error detection circuit for calibrating a serial transmitter is disclosed. The circuit includes a data source configured to provide data for serial transmission and a clock source configured to produce N versions of a sampling clock that are at N different phases of the sampling clock. The detection circuit has a first sampler configured to sample the data source by using a first phase of the sampling clock to generate a first sampled signal and a second sampler configured to sample the data source by using a second phase of the sampling clock to generate a second sampled signal. The detection circuit also includes a first comparator configured to compare the first and second sampled signals to generate a difference signal and a first low-pass filter configured to filter the difference signal to generate an average difference voltage. A second comparator in the detection circuit is configured to compare the average difference voltage with a reference voltage. |
| US09942023B2 |
Systems and methods for signaling in an increased carrier monitoring wireless communication environment
Systems and methods for signaling in an increased carrier monitoring wireless communication environment are disclosed herein. In some embodiments, a user equipment (UE) may include control circuitry to configure the UE for increased carrier monitoring; determine, based on a first signal received from a network apparatus, whether a reduced performance group carrier is configured; determine, based on a second signal received from the network apparatus, whether a scaling factor is configured; and in response to a determination that no reduced performance group carrier is configured and a determination that no scaling factor is configured, allow the UE to monitor fewer carriers than required by increased carrier monitoring. Other embodiments may be disclosed and/or claimed. |
| US09942015B2 |
OFDMA indication and communication in WLANs
This disclosure relates to orthogonal frequency division multiple access (OFDMA) communication in wireless local area networks (WLANs). According to some embodiments, an indication may be transmitted to receiving devices that a first frame is an OFDMA frame. Channel information indicating allocation of bandwidth portions of the first frame to respective receiving devices may also be transmitted to the receiving devices. The first frame may be transmitted to the receiving devices, including transmitting data to each respective receiving device on the bandwidth portion(s) allocated to the respective receiving device. |
| US09942014B1 |
Cooperative multimedia communication method and system thereof
Provided is a cooperative multimedia communication system. The source node includes a first hierarchical modulation constellation diagram, modulates two data streams and transmits a first signal and a second signal. The relay node includes a protection-level-exchanging modulation and a second hierarchical modulation constellation diagram, modulates the second signal to generate a third signal and transmits the third signal. The destination node receives the first signal and the third signal and performs optimal decoding. The present disclosure designs a pair of optimal hierarchical constellation diagrams respectively for the source node and the relay node. Moreover, the present disclosure further provides a cooperative multimedia communication method. |
| US09942010B1 |
Methods and systems for enabling communications from a station to an access point using an orthogonal frequency division multiple access (OFDMA) communication scheme
Methods and systems are disclosed for performing contention based uplink (UL) orthogonal frequency division multiple access (OFDMA). The method may include receiving, from an access point using a channel, a first signal including an indication of a first time and a plurality of sub-channels of the channel. The method may include modifying a counter value in response to determining that the first time has been reached. The method may include selecting a sub-channel of the plurality of sub-channels in response to determining the counter value is equal to a threshold value. The method may include transmitting a second signal to the access point using the sub-channel. The methods and systems disclosed herein may be used by stations to associate with the access point. |
| US09942007B2 |
Method and apparatus for time-based fast ACK/NACK response operation with enhanced general packet radio service 2 uplink
A method and apparatus for time-based fast positive acknowledgement (ACK)/negative acknowledgement (NACK) reporting (FANR) operation with enhanced general packet radio service 2 uplink (HUGE) are disclosed. A wireless transmit/receive unit (WTRU) configures downlink FANR operation and EGPRS-2 mode uplink transmission not to be in conflict. A modulation and coding scheme (MCS) for the EGPRS-2 mode may be limited to an MCS containing at most two RLC data blocks. Alternatively, three or more piggybacked ACK/NACK (PAN) bits may be used for a time-based FANR operation if an EGPRS-2 mode is configured. Alternatively, at least one PAN bit may indicate an ACK/NACK for a group of RLC data blocks. The number of PAN bits for a time-based FANR operation may be configured by the network. The downlink FANR operation may be dynamically switched between time-based and SSN-based. |
| US09942002B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
The present invention provides a method of transmitting broadcast signals. The method includes, formatting, by an input formatting block, input streams into plural PLPs (Physical Layer Pipes); encoding, by an encoder, data in the plural PLPs; time interleaving, by a time interleaver, the encoded data in the plural PLPs, wherein the time interleaving includes: cell interleaving, by a cell interleaver, the encoded data by permuting cells in a FEC (Forward Error Correction) block in the plural PLPs; frame mapping, by a framer, the time interleaved data onto at least one signal frame; and waveform modulating, by a waveform block, the mapped data in the at least one signal frame and transmitting, by the waveform block, broadcast signals having the modulated data. |
| US09942000B2 |
Broadcast receiving apparatus and signal processing method thereof
A broadcast receiving apparatus and a signal processing method thereof are provided. The broadcast receiving apparatus includes a receiver configured to receive a data stream comprising a plurality of physical layer pipes (PLPs); a demodulator configured to output at least one generic packet corresponding to each of the plurality of PLPs and additional information on the at least one generic packet by demodulating the plurality of PLPs; and a signal processor configured to process the at least one generic packet based on the output additional information. |
| US09941997B2 |
Method and system for data-driven, variable-rate, channel quality indicator for LTE non-real-time bursty traffic
A method and system, in a long term evolution architecture utilizing adaptive modulation and coding requiring periodic channel quality indication reports, the method having the steps of: waiting for an idle channel indication; and upon detection of the idle channel indication, decreasing the rate of periodic channel quality indication reports. |
| US09941994B2 |
Wavelength shift elimination during spectral inversion in optical networks
Methods and systems are provided for wavelength shift elimination during spectral inversion in optical networks. The method includes receiving an input optical signal, and generating a combined optical signal by combining, by Bragg scattering, the input optical signal having an input wavelength with a first pump signal having a first wavelength. The method further includes converting the combined optical signal into an output optical signal, by phase-conjugation, using a second pump signal having a second wavelength. The output optical signal has the same wavelength as the input optical signal. |
| US09941993B2 |
Method and apparatus for optical transmitter and receiver redundancy within a directionless optical node
Example embodiments of the present invention relate to an optical node comprising of at least two degrees, a plurality of directionless add/drop ports, a plurality of primary WDM transmitters and receivers, and at least one protection WDM transmitter and receiver, wherein the at least one protection WDM transmitter and receiver can transmit and receive in place of any of the plurality of primary WDM transmitters and receivers. |
| US09941992B2 |
Method and apparatus for efficient network utilization using superchannels
The disclosure relates to technology for constructing an optical network. A central node is selected among a plurality of nodes in the optical network, and each of the nodes is connected to the central node via a set of superchannels, wherein each of the superchannels includes sub-carriers and has a same data rate. The network resources between the central node and each of the plurality of nodes are managed by dynamically allocating the sub-carrier bandwidths to support communication among the plurality of nodes via the superchannels, and wavelength selective switching is performed among the superchannels at the central node. |
| US09941991B2 |
Method and system for controlling spectral occupancy
Aspects of the disclosure provide systems and methods which avoid the negative effects of Spectral Hole Burning when spectral changes are made for an optical communication system (OCS). Embodiments of the disclosure are directed to methods and systems which preform spectral holes for the range of wavelength channels expected to be used in the OCS. Embodiments include a configurable idle tone source for providing power to each of a set of idle tone wavelengths distributed across the spectral band used in the optical communication system. The configurable idle tone source is communicatively coupled to an output fiber of an optical network element and controlled such that optical power is present in the output optical fiber at each one of the set of idle tone wavelengths. |
| US09941989B2 |
Coded imaging and multi-user communications systems
A coded imaging and multi-user communications systems using novel codes, algorithms to develop such codes, and technological implementations to use the codes for various types of systems involving multiple (or single) transmitters and multiple (or single) receivers of signals (which could include but are not limited to electromagnetic radiation, acoustic waves, other types of waves or data) as a function of time-or-space. |
| US09941987B2 |
Single knob pre-amplifier gain-trim and fader
According to a first aspect of the embodiments, a microphone mixer is provided comprising: an input adapted to receive differential microphone (mic) output signals; a gain-trim circuit adapted to receive the differential mic output signals, and which includes a substantially fully differential amplifier adapted to amplify the received differential mic output signals through use of a gain-trim output adjustment device that provides a variable gain amount ranging from a first gain-trim gain value to a second gain-trim gain value, to produce differential gain-trim circuit output signals; a fader circuit adapted to receive the differential gain-trim circuit output signals, and which includes a differential amplifier adapted to attenuate the received differential gain-trim circuit output signals through use of a fader output adjustment device that provides a variable gain amount ranging from a first fader gain value to a second fader value; and a common adjustment apparatus that mechanically ties the gain-trim output adjustment device with the fader output adjustment device such that the first gain-trim gain value and first fader gain value are obtained substantially simultaneously at a first position of the common adjustment apparatus, and the second gain-trim gain value and second fader gain value are obtained substantially simultaneously at a second position of the common adjustment apparatus. |
| US09941986B2 |
Configurable, highly-integrated satellite receiver
A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters. |
| US09941985B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
The present invention provides a method of transmitting broadcast signals. The method includes, formatting input streams into Data Pipe, DP, data; Low-Density Parity-Check, LDPC, encoding the DP data according to a code rate; bit interleaving the LDPC encoded DP data; mapping the bit interleaved DP data onto constellations according to one of QAM (Quadrature Amplitude Modulation), NUQ (Non-Uniform QAM) or NUC (Non-Uniform Constellation); Multi-Input Multi-Output, MIMO, encoding the mapped DP data by using a MIMO encoding matrix having a MIMO encoding parameter; building at least one signal frame by mapping the MIMO encoded DP data; and modulating data in the built signal frame by an Orthogonal Frequency Division Multiplexing, OFDM, method and transmitting the broadcast signals having the modulated data. |
| US09941981B2 |
Body coupled communication device
Body coupled communication device (200; 201) arranged to receive signals via a body transmission channel (260), the device (200) comprising —two couplers (202, 204) arranged to receive a body-coupled signal from the body transmission channel (260), the body transmission channel (260) being formed by a body of a user (150) when the body is in the direct vicinity of the couplers (202, 204), —a receiver amplifier (206) coupled to at least one of the two couplers, —an inductance (220) for matching the impedance of the receiver amplifier, the inductance being arranged in parallel to the couplers. |
| US09941980B2 |
Body coupled communication device with synchronization
A body-coupled communication device (201) adapted to receive signals via a body transmission channel (160), the first device comprising couplers (102) arranged to receive a body-coupled signal, a synchronization-indicator (272) to storing a level of synchronization between the first device and a second device, and a band-pass filter (250) arranged to filter the received body-coupled signal depending on the synchronization level, the band-pass filter being arranged to allow passage of frequencies in a frequency-interval around a tunable filter frequency, wherein the frequency-interval is narrow if the synchronization-level is high and wherein the frequency-interval is broad if the synchronization-level is low. |
| US09941978B2 |
Acoustic channel-based data communications method
It discloses an acoustic channel-based data communications method which performs channel coding on an original data signal using a CRC coding method and a BCH coding method to obtain a coded sequence; modulates the coded sequence using a preset audio sequence symbol set via a symbol mapping method to obtain a digital audio signal; selects a channel frequency band according to characteristics of a transmitting equipment and interference between frequency bands; and converts the digital audio signal into an analog audio signal through a digital-to-analog converter and transmits the signal to a channel for transmission according to the selected channel frequency band. |
| US09941972B2 |
Optical transmitter and control method
An optical transmitter has an array of laser diodes, which output optical signals from a forward end, and controls the power of the optical signals. The optical transmitter has photodiodes detecting the optical power of optical signals from a reverse end and a LD-DRV unit that supplies to the laser diodes, bias current amplitude modulated to a predetermined frequency that differs from that of the drive signal of the laser diodes. The optical transmitter has a frequency analyzing unit that separates a signal detected by a photodiode, into an optical signal component from a target laser diode and crosstalk optical signal components received from other laser diodes; and a control unit that computes for each detected signal, a ratio of the crosstalk optical signal components to the optical signal component, and performs based on the ratio, a computation to remove the crosstalk optical signal components from the detected signal. |
| US09941965B2 |
Laser and optical charging and communications device and method of use
Techniques for charging and optical communication with electronic devices are provided. Specifically, systems and methods to provide charging through laser or optical means and to provide optical communications are presented. Even more specifically, in one embodiment, the systems and methods comprise standard USB interfaces, USB protocols and USB connectors. |
| US09941963B2 |
Non-linear propagation impairment equalization
A method (10) of non-linear propagation impairment equalization, the method comprising the steps of: a. receiving (12) communications traffic carried by an optical communications signal transmitted over an optical communications link; b. generating (14) a time dependent filter representation of a nonlinear time-variant impulse response of the inverse of the optical communications link; and c. applying (16) the time dependent filter representation to the received communications traffic to form non-linear propagation impairment equalized communications traffic. An optical communications link nonlinear propagation impairment equalizer and optical communications signal receiver apparatus are also provided. |
| US09941962B2 |
Free space optical data transmission for secure computing
An apparatus and method for computer network security based on Free-Space Optical Interconnections (FSOI) for board-to-board information transmission. The addition of a controllable, interlocked shutter system creates air-gapped isolation of the boards, allowing for increased obfuscation, and enhanced security. |
| US09941948B2 |
Method of reporting channel state and apparatus therefor
A method of reporting a channel state, which is reported by a terminal configured to transmit and receive data while hopping in a unit of the specific number of resource blocks (RBs) in a wireless communication system, includes receiving a random access response including an aperiodic channel state report request in response to a transmitted random access preamble, calculating channel state information according to the aperiodic channel state report request in consideration of the number of repetitive transmissions for the terminal, and reporting the calculated channel state information to a base station. In this case, the number of repetitive transmissions for the terminal may be determined by a predetermined or signaled value. |
| US09941947B2 |
Method and apparatus for open loop transmission in a multiple antenna wireless communication system
The invention concerns a method for precoding in an open loop transmission communications system. The method includes precoding data at each of M REs with a precoding matrix, precoding each of DM-RSs with one column of a precoding matrix which is same as that used for precoding M data REs. The method is distinguished by using at least L≥2 different precoding matrices from a set of precoding matrices W to precode the M REs and the E allocated REs such that REs precoded with a first precoding matrix are interleaved with REs precoded with at least one additional, different precoding matrix and the number of used precoding matrices L is adapted to the transmission rank r and number N of available DM-RS. |
| US09941943B1 |
Coordinate descent detector and precoder for multiple-input multiple-output (MIMO) system
A system includes an integrated circuit configured to communicating data in a channel. A channel matrix for the channel including a plurality of columns is received. A preprocessing step is performed, using a preprocessing unit, to compute a plurality of preprocessed column values corresponding to respective columns. An update step is performed, using an update unit, to update an estimation vector using a plurality of outer-loop iterations of an outer loop. Each outer-loop iteration updates the estimation vector using the plurality of preprocessed column values. An access link process is performed using the estimation vector. |
| US09941930B2 |
Conductive layer of a large surface for distribution of power using capacitive power transfer
An article of manufacture for supplying a power to a load connected in a capacitive power transfer system comprises a sheet (210) of a non-conductive material; and a plurality of conductive stripes (220), each two adjacent conductive stripes being electrically insulated from each other, wherein the sheet forms an insulating layer of the capacitive power transfer system and the plurality of conductive stripes form at least a pair of transmitter electrodes of the capacitive power transfer system. |
| US09941923B2 |
Radio transceiver circuit
The disclosure relates to transceivers incorporating a transmit-receive switching circuit, embodiments of which include a radio transceiver circuit comprising: a first amplifier for amplifying signals received from an antenna via an antenna connection; a second amplifier for amplifying signals to be transmitted by the antenna via the antenna connection; and a switching circuit connected between an input of the first amplifier and the antenna connection, the switching circuit comprising a capacitor, a switching element and an impedance matching element, wherein the switching element is configured to connect a node between the capacitor and the impedance matching element to a signal ground when the transceiver is in a transmit mode. |
| US09941921B2 |
Modular wireless communications platform
A modular wireless communications platform is provided. The modular wireless communications platform has a modular host unit and a modular remote unit in communication with the modular host unit. The modular host unit and remote unit include a serial radio frequency communicator configured to convert serial digital data into RF sampled data and configured to convert RF sampled data into serial digital data. The modular host unit and remote unit also include an interface coupled to the serial radio frequency communicator and configured to allow transfer of the RF sampled data from the serial radio frequency communicator to a digital to analog radio frequency transceiver module. |
| US09941919B2 |
Case for a computing device
A system for protecting an electronic device and securely and conveniently carrying tangible portable contents therewith. The system may include a resilient portion dimensioned to detachably receive the electronic device by a continuous perimetral edge. The electronic device may be secured thereto by an inwardly extending, retaining lip of the perimetral edge. A rigid portion may be detachably connected to a rear surface of the resilient portion opposite the electronic device. The rigid portion may be dimensioned to shield at least part of the rear surface of the rigid portion. A cavity may be defined between the rigid portion and the rear surface of the resilient portion when the rigid portion is in a closed position. The cavity is operable to secure the tangible contents in the closed position and receive the tangible contents in an opened position. |
| US09941917B2 |
Base station
An embodiment of the present invention discloses a base station, including: a baseband unit, a radio remote unit, a power supply device, a signal transmission device, and a backup power supply device. The baseband unit and the radio remote unit are mounted on an antenna tower or a pole. At least one of the power supply device, the signal transmission device, or the backup power supply device is also mounted on the antenna tower or the pole. |
| US09941913B2 |
Filtering device for a PMR portable mobile terminal, and mobile terminal
A filtering device intended for being connected to a portable mobile terminal compatible with a PMR network having a wide range of receiving frequencies Bi, includes a fastening system for fastening to the mobile terminal, a first radio-frequency connector intended for engaging with a radio-frequency connector of the mobile terminal, a first channel including a first filter for filtering a first receiving useful band Bui included within the band Bi, and a second radio-frequency connector intended for engaging with a removable RF antenna to transmit or receive radio-frequency signals. |
| US09941910B2 |
Method and apparatus for antenna tuning and power consumption management in a communication device
A system that incorporates teachings of the subject disclosure may include, for example, a controller that determines a radiated throughput for at least one of an uplink throughput or a downlink throughput of the communication device, reduces transmit power for the communication device responsive to the radiated throughput satisfying a predetermined throughput range, and tunes a matching network of the communication device responsive to the radiated throughput not satisfying the predetermined throughput range. Other embodiments are disclosed. |
| US09941896B2 |
Analog to digital converter error rate reduction
An analog-to-digital converter (ADC) may include a comparator and a metastability detector. The comparator may be configured to compare an input signal to a reference signal to determine whether the input signal exceeds the reference signal. The comparator may also be configured to output a comparator output based on the determination. An ADC output may be based at least in part on the comparator output. The metastability detector may be coupled to the comparator and may be configured to determine, based at least in part on the comparator output, that the comparator is operating under metastable conditions and may output a metastability detector output. |
| US09941882B1 |
Tristate multiplexers with immunity to aging effects
An integrated circuit with programmable logic is provided. The programmable logic may include multiplexers that are actively used by a custom logic design or unused. To ensure that these multiplexers do not suffer from aging effects when they are not in use, the multiplexers may be provided with aging prevention circuitry. In particular, such a multiplexer may include an input selection stage that is coupled in series with a tristate buffer stage. The input selection stage may include pass transistors or full CMOS transmission gates. The tristate buffer stage may include at least two pairs of output driving transistors, with gates that are selectively shorted when the multiplexer is activated using additional transmission gate circuits. The aging prevention circuitry may include tie-off transistors that are activated to drive the gate-to-source voltages of the output driving transistors to zero volts whenever the multiplexer is not in use. |
| US09941876B2 |
Bootstrap diode circuits
Bootstrap diode circuits are disclosed. Example bootstrap diode circuits disclosed herein include a first diode having a first diode input coupled to a voltage supply and a first diode output. Disclosed bootstrap diode circuits additionally include a second diode having a second diode input coupled to the first diode output and a second diode output and a plurality of zener diodes coupled in series. The plurality of series-coupled zener diodes are further coupled in parallel with the second diode. |
| US09941874B2 |
Switching unit and power supply circuit
A switching unit of an embodiment includes a first switching element of normally-on type, a second switching element of normally-off type having a non-reference potential side conductive terminal connected to a reference potential side conductive terminal of the first switching element, a resistive element having one end connected to a conduction control terminal of the first switching element; a series capacitor connected between the other end of the resistive element and a conduction control terminal of the second switching element; and a diode having an anode connected to the other end of the resistive element and a cathode connected to a common junction of the first switching element and the second switching element. |
| US09941866B2 |
Apparatus for design for testability of multiport register arrays
In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port. |
| US09941859B2 |
Ladder-type filter, duplexer, and module
A ladder-type filter includes: one or more series resonators connected in series between an input terminal and an output terminal; one or more parallel resonators connected in parallel between the input terminal and the output terminal; divided parallel resonators formed by serially dividing at least one parallel resonator of the one or more parallel resonators; and an inductor of which a first end is coupled to a first node located in a path from the input terminal to the output terminal through the one or more series resonators, and of which a second end is coupled to a second node located between the divided parallel resonators. |
| US09941858B2 |
Electricoacoustic component with structured conductor and dielectric layer
An electroacoustic component includes a substrate configured to carry acoustic waves. The electroacoustic component can be a guided bulk acoustic wave (GBAW) device, for example. A structured electric conductive layer is arranged on the substrate and an electrically dielectric layer (for example, aluminum oxide) is also arranged over the substrate. |
| US09941852B1 |
Operation amplifiers with offset cancellation
A semiconductor device includes an operational transconductance amplifier (OTA) with a matched pair of transistors including a first transistor and a second transistor, and configuration units that include a first set of switches, a second set of switches, and an input transistor. Gain adjustment circuitry is coupled to adjust gain of the OTA. Measurement circuitry is coupled to measure offset in the OTA. Control logic is configured to operate the first and second sets of switches to couple input transistors of a first group of the configuration units to the first transistor of the matched pair of transistors, and to couple input transistors of a remaining group of the configuration units to the second transistor of the matched pair of transistors. Settings of the first and second sets of switches are selected to minimize the offset. |
| US09941851B2 |
Amplifier circuit and method
An amplifier arrangement comprises N amplifier stages 101 to 10N, wherein N is an integer equal or greater than five. The amplifier arrangement comprises a cascade of quarter wavelength transmission line segments 111 to 11M coupled between an output of an amplifier of a first amplifier stage and an output node 15 of the amplifier arrangement. At least one intermediate junction 12 in the cascade of quarter wavelength transmission line segments comprises: a first amplifier coupled directly to the intermediate junction 12; and a second amplifier coupled to the same intermediate junction 12 via a connecting quarter wavelength trans mission line 131. |
| US09941850B1 |
Fully differential operational amplifier
A fully differential operational amplifier is provided. The amplifier has input nodes and includes a differential input stage for receiving input signals over the input nodes and providing output signals on first and second intermediary nodes. The amplifier includes a fully differential amplification stage having positive and negative inputs coupled to the first and second intermediary nodes, respectively. The amplifier includes a first compensation transistor having conduction terminals coupled to the first intermediary node and a first node, and a control terminal coupled to a negative output of the fully differential amplification stage. The amplifier includes a second compensation transistor having conduction terminals coupled to the second intermediary node and a second node, and a control terminal coupled to a positive output of the fully differential amplification stage. The amplifier includes positive and negative output stages for providing amplifier outputs and feeding the outputs back to the amplifier. |
| US09941843B2 |
Amplifier dynamic bias adjustment for envelope tracking
An envelope tracking amplifier having stacked transistors is presented. The envelope tracking amplifier uses dynamic bias voltages at one or more gates of the stacked transistors in addition to a dynamic bias voltage at a drain of a transistor. |
| US09941842B2 |
Amplifier bias circuit
A power amplifier bias circuit having high dynamic range and low memory is disclosed. In an exemplary embodiment, an apparatus includes an output stage configured to generate a biased RF signal based on a first DC signal and a filtered signal. The apparatus also includes a low pass filter configured to filter the biased RF signal to generate the filtered signal. |
| US09941841B2 |
Clipping distortion mitigation systems and methods
An audio system includes a processor including an input configured to: receive a baseband audio signal and modulate the baseband audio signal to create a modulated audio signal comprising audio signal frequency components in a first frequency range; clip the modulated audio signal to create a clipped, modulated audio signal the clipped modulated audio signal comprising the audio signal frequency components in the first range and further comprising distortion frequency components outside the first frequency range. The system can further be configured to filter the clipped, modulated audio signal to remove frequency components outside the first frequency to remove distortion components outside that frequency range. |
| US09941839B2 |
Electronic component, electronic apparatus, and moving object
An electronic component includes a wiring substrate, a heating element, a first support, a second support, and a container. The heating element, the first support, and the second support are electrically connected to the wiring substrate. Each of the first support and the second support includes a protrusion portion, and the protrusion portion of the second support is shorter than the protrusion portion of the first support. |
| US09941833B2 |
Converter for hybrid electric vehicle system
Provided is a converter for an HEV system. The converter includes a PCB, a PWM (IC) mounted on the PCB to output a plurality of PWM signals including a first PWM signal and a second PWM signal, a plurality of MOSFETs mounted on the PCB, the plurality of MOSFETs including a first MOSFET, which performs a switching operation according to the first PWM signal, and a second MOSFET which performs a switching operation according to the second PWM signal, and a plurality of inductors including a first inductor, which is magnetized according to the switching operation of the first MOSFET to operate in one phase, and a second inductor which is magnetized according to the switching operation of the second MOSFET to operate in other one phase. |
| US09941828B2 |
System and method for stabilizing sub-synchronous interaction of a wind turbine generator
The present disclosure is directed to a system and method for stabilizing sub-synchronous interaction (SSI) of a wind turbine generator connected to a power grid. More specifically, the method includes measuring an alternating-current (a-c) quantity of the power grid. Another step includes converting the a-c quantity to a d-q quantity and providing the d-q quantity to a d-q control loop within the controller. Another step includes altering, with a symmetric control component, a transfer function of the d-q control loop. The method also includes generating at least one d-q reference signal for the wind turbine generator based on the altered transfer function so as to achieve symmetric control of the generator. A further step includes generating a control signal for the generator based, at least in part, on the at least one d-q reference signal. The method also includes operating the generator based on the control signal. |
| US09941827B2 |
High voltage DC power generating system including selectively removable neutral node
A high voltage DC electric power generating system includes a poly-phase permanent magnet generator having at least one control winding and a plurality of power windings. Each of the power windings is a phase of the poly-phase permanent magnet generator. A passive rectifier connects a switch to an input of each of the power windings such that the switch is a neutral node in a closed state and a disconnect in an open state. |
| US09941820B2 |
Force modification system for wave energy convertors
A device for generating electrical energy from mechanical motion includes a buoy housing and at least one force modifier disposed at least partially within the interior of the buoy housing. The force modifier receives an input force and applies a modified force to another component. The force modifier includes a hydraulic system and the hydraulic system includes a first hydraulic piston having a first area and a second hydraulic piston having a second area, where the first area and the second area are not equal. |
| US09941817B2 |
Ultrasonic transducer and ultrasonic diagnostic equipment using the same
High transfer sound pressure and high reception sensitivity are realized, and reliability is improved in terms of long term operation, in a capacitive detector-type ultrasonic transducer (CMUT). The ultrasonic transducer, which has a lower electrode (201), a hollow portion (202) that is formed on the lower electrode and surrounded by insulating films (209,208), an upper electrode (205) that is formed on the hollow portion, and a plurality of insulating film projections (204) that are formed in the hollow portion (202), comprises a plurality of rigid members (203) that are formed on the hollow portion, either the lower electrode (201) and/or the upper electrode (205) is disposed in a position that does not overlap with the insulating film projections (204) when viewed from the upper surface by carving out the portion that overlaps with the insulating film projections (204), and the respective rigid members (203) are disposed such that a region is present that overlaps with the insulating film projections (204) when viewed from the upper surface. |
| US09941814B2 |
Method for detecting islanding in grid connected power generation systems and related DC/AC converter apparatus
Method for detecting an islanding condition of a grid connected energy conversion system and related DC/AC converter apparatus, adapted to optimize performance in terms of preservation of the power quality, provide synchronized perturbation for all the inverters of a plant, provide shut down capability within the time requested by utilities and safety standards and provide immunity to grid frequency fluctuations. |
| US09941811B2 |
Load control device for high-efficiency loads
A load control device for controlling power delivered from an AC power source to an electrical load includes a thyristor, a first current path for conducting current through a gate terminal of the thyristor, and a control circuit for controlling the first current path to conduct a pulse of current through the gate terminal to render the thyristor conductive at a firing time during a present half cycle. The first current path is able to conduct at least one other pulse of current through the gate terminal between the firing time, and a second time that occurs before an end of the present half-cycle, but is prevented from conducting pulses of current between the second time and the end of the present half-cycle. The load control device includes a second current path for conducting current through the electrical load if the thyristor becomes and remains non-conductive during the present half-cycle. |
| US09941810B2 |
Power conversion device for converting AC power into DC power
A power conversion device includes a rectifier circuit that converts an AC power from an AC power supply, into a DC power, a short-circuit unit that short-circuits the AC power supply via a reactor connected between the AC power supply and the rectifier circuit, a control unit that generates a plurality of drive signals to control the short-circuit unit in a half cycle of the AC power supply, and a smoothing capacitor. The control unit stepwise varies threshold values that limit a value of a power-supply current of the AC power supply, in an on-section or an off-section of the plurality of drive signals. |
| US09941806B2 |
Modulation method for the boost converter operating mode of a push-pull converter
The invention relates to a method for modulating the boost converter operating mode of a push-pull converter having a low-voltage-side circuit, having a first low-voltage-side switching device and a second low-voltage-side switching device; having a transformer having a high-voltage-side winding; and having a high-voltage-side circuit, which is configured as a full-bridge rectifier, having a first and a second rectification element which form a first half-bridge and a third and a fourth rectification element which form a second half-bridge; wherein the method comprises the steps of closing the first low-voltage-side switching device while simultaneously short-circuiting the high-voltage-side winding via the first or the fourth rectification element during a first time segment; opening the rectification element used for short-circuiting the high-voltage-side winding during a second time segment; opening the first low-voltage-side switching device and closing the second low-voltage-side switching device while simultaneously short-circuiting the high-voltage-side winding via the third or the fourth rectification element in the second half-bridge during a third time segment; and opening the rectification element used for short-circuiting the high-voltage-side winding during a fourth time segment. |
| US09941805B2 |
Frequency and duty cycle strategies for DC/DC converters
A method for controlling a DC/DC converter includes the steps of: controlling and keeping an output voltage of the DC/DC converter to stabilize at a first value according to a first interval of an input voltage of the DC/DC converter; controlling and keeping the output voltage of the DC/DC converter to stabilize at a second value according to a second interval of the input voltage of the DC/DC converter; controlling the second value of the output voltage to be greater than the first value; and controlling a switching frequency or a duty cycle of the DC/DC converter within a first predetermined range in the first and second intervals. |
| US09941800B2 |
Measuring input voltages from reference windings of power converters with limited on-time
The disclosed embodiments provide a system that operates switched-mode power supplies, such as flyback converters. The power supplies may comprise isolated or non-isolated power converters. During operation, the system senses an on-time of a primary switch in the power converter. Upon detecting that the on-time does not exceed an on-time threshold within a first pre-specified period that spans one or more switching cycles, the system extends the on-time during a subsequent switching cycle to at least meet the on-time threshold. The system may then measure the voltage on one or more reference windings of the power converter during the on-time of the subsequent switching cycle, wherein the reference winding may comprise, e.g., an auxiliary winding of the primary winding of the power converter or a secondary winding of the power converter (e.g., in the case of isolated power converters utilizing a transformer). |
| US09941795B1 |
Circuits and method for extracting average load current in DC-DC switching converters
An average load current calculator circuit configured for determining an average load current within an at least one phase switch mode power converter (SMPC) having at least one peak/valley detector receives an inductor current sense signal and determines and holds a peak or valley amplitude of the inductor current sense signal. A current corrector circuit receives an input voltage and an output voltage of the SMPC and an inductance value of the inductor of the SMPC for determining an average correction current of the peak or valley amplitude of the current sense. An average current generator receives the peak or valley amplitude of the current sense signal and the average correction current for determining the instantaneous average load current within a switch mode power converter (SMPC) by additively combining the peak or valley amplitude of the current sense signal and the average correction current. |
| US09941793B2 |
Snubber for voltage regulation
A voltage regulator includes circuitry for regulating a voltage output of the voltage regulator and a snubber circuit. The snubber circuit includes a switching device which is controlled to electronically connect or disconnect the snubber circuit with the circuitry of the voltage regulator device. The switching device may be controlled by a controller based on one or more parameters indicating a load of the voltage regulator device. |
| US09941792B2 |
DC offset correction for inductor current ripple based, constant-on-time DC-DC converters
Embodiments of a circuit for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter are disclosed. The circuit includes a ripple generation circuit coupled to a reference voltage input and to a sense voltage input, and having a reference voltage output to form a main loop. The circuit also includes a DC error correction circuit connected between the reference voltage input and the sense voltage input, and the reference voltage output of the ripple generation circuit. The DC error correction circuit includes a coarse DC error correction loop coupled between the sense voltage input and the reference voltage output and a fine DC error correction loop coupled between the reference voltage input and the reference voltage output. A method for controlling DC offset error for an inductor current ripple based, constant-on time DC-DC converter, is also disclosed. |
| US09941791B1 |
Fast transient response for switching regulators
The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, an output voltage of a switching regulator operating in a discontinuous mode is monitored via a comparator coupled directly to an output of the switching regulator. In response to the output voltage falling below a predefined threshold, a high-side switch is activated to provide current to a load connected to the output of the switching regulator. The switching regulator is then transitioned from the discontinuous mode of operation to a continuous mode of operation to control subsequent operation of the high-side switch. This can be effective to mitigate a drop in the output voltage of the switching regulator when an amount of current consumed by the load increases (e.g., a load step). |
| US09941790B2 |
DC-to-DC converter
A method and an apparatus for DC-to-DC conversion are provided. The apparatus is a DC-to-DC converter including a first feedback current control circuit coupled to a first voltage output of the DC-to-DC converter. The first feedback current control circuit is configured to generate a first control current based on a voltage difference between a first reference voltage and the first voltage output of the DC-to-DC converter. The apparatus further includes a constant charge comparator coupled to the first feedback current control circuit and configured to compare an integrated error signal to a threshold to generate a comparison result, the integrated error signal comprising an integration of a first error signal over time, the first error signal based on the first control current. |
| US09941789B2 |
Feedforward circuit for DC-to-DC converters with digital voltage control loop
A method may comprise receiving a first clock signal; receiving a digital duty cycle value; using the first clock signal and digital duty cycle value to generate a digital pulse width modulation (DPWM) signal having a plurality of discrete steps to control a switch of a switched-mode power supply; and using a voltage control circuit to modify a duration of each of the plurality of discrete steps of the DPWM signal, wherein the voltage control circuit is configured to receive an analog voltage input. |
| US09941784B1 |
Power factor correction current sense with shunt switching circuit
A power converter is provided with a totem-pole power factor correction (PFC) circuit for bridgeless line rectification, and current sensing circuit that can be selectively disabled to reduce unwanted current sense signal components and undesirable current transformer voltage stresses. The totem-pole PFC has at least a first leg with first and second switching elements coupled in series. A PFC inductor is coupled between an AC input on a first end and a node between the switching elements. The current sensing circuit includes a first transformer winding coupled in series with the first switching element, a second transformer winding magnetically coupled to the first winding and configured to deliver current from the first winding to a current sense terminal during an active phase for the first switching element, and a shunt circuit configured to disable the current sensing circuit during a freewheeling phase for the first switching element. |
| US09941783B2 |
Electronic device and soft start module
An electronic device is provided. The electronic device includes a power supply module, a system load, a soft start unit, a unidirectional conducting unit and a connector. The system load is electrically coupled with the power supply module. The soft start unit is electrically coupled with the system load and the power supply module. The unidirectional conducting unit is electrically coupled between the soft start unit and the power supply module, so as to prevent the energy from the power supply module from entering the soft start unit. The connector has a power input terminal. The power input terminal is electrically coupled with the soft start unit. |
| US09941782B2 |
Power supply device and method for limiting an output current of a power supply device
A switched-mode power supply system and method for converting an input voltage into an output voltage, including at least one switching stage controlled by a pulse-width modulation circuit in a clocked manner, and a control circuit that influences a pulse-width modulation circuit to vary the level of the output voltage, characterized by the provision of a current limiting circuit which, after a threshold voltage has been exceeded, limits the power supply output current first to an elevated maximum current for a first period of time, and thereafter to a regular maximum current. The control circuit is such that the first period of time for which the output current is limited to the elevated maximum current is dependent on the level of the output current. |
| US09941775B2 |
D-ring implementation in skewed rotor assembly
An assembly includes multiple adjoined rotor sections each having multiple poles and multiple void rows therethrough that are radially distributed in each of the poles. The rotor sections are skewed in a circumferential direction. The assembly also has multiple conductive rings that substantially surround one of the void rows. A method of assembly and electric machines and vehicles using the assembly are also disclosed. Aspects reduce torque ripple in electric machines and allow for encoderless/sensorless operation in an electric machine using the rotor assembly. The present invention has been described in terms of specific embodiment(s), and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims. |
| US09941772B2 |
Marine propulsion systems
The present invention provides a marine propulsion system that is suitable for any civilian and military marine vessels and which offers operational flexibility. The marine propulsion system includes a pair of ac busbars, each in parallel connection with a power converter. The respective power converters each connected in parallel to a propulsion motor. |
| US09941771B2 |
Electric motor rotor with extended shoulders for bearings
A number of variations may include a product comprising: a rotor core comprising a body, wherein the body includes an inner surface and an outer surface, a first end cap which extends radially from a first end of the body and a second end cap which extends radially from a second end of the body, wherein the first end cap, the second end cap, and the outer surface define an annular cavity; at least one sleeve adjacent at least one of the first end cap or the second end cap; at least one magnet contained within the annular cavity; and at least one bearing operatively attached to the at least one sleeve. |
| US09941769B2 |
Linear reluctance motor device and engine apparatus
A reluctance motor includes a ferromagnetic seat, a non-magnetic sleeve sleeved on the seat, a magnetizing coil wound around the sleeve, a magnetic core surrounding the sleeve, a ferromagnetic cover covering the sleeve, and a ferromagnetic pseudo piston partly disposed in the sleeve and axially movable relative to the sleeve. |
| US09941768B2 |
Electric drive, vehicle having an electric drive, and method for operating an electric drive
An electric drive, particularly for vehicles, includes at least one first and at least one second electric machine. The electric machines are arranged relative to one another in a manner comparable to the cylinders of a conventional opposed-cylinder internal-combustion engine. |
| US09941767B2 |
Linear actuator and rocking controller for railway vehicle
To provide a compact linear actuator having small back drive force. The linear actuator includes: a hollow rotor that has a magnet fixed to a part of the outer peripheral surface thereof and having an open end and a closed end; a main body that has a hollow structure having an open end and a closed end and rotatably accommodates the rotor in the hollow structure, and is fixed with a stator winding facing the magnet; a linear motion converting section that is arranged in the hollow section of the rotor and is linearly moved in the axial direction by the rotation of the rotor; a linear motion rod that has one end fixed to the linear motion converting section, and the other end extended from the open end of the main body, and has, on the outer periphery thereof, a slide section made to slide in the axial direction with respect to a linear motion seal of the opening of the main body; and a resolver that is configured by a rotator fixed at the radial outer side of the outer peripheral surface of the rotor and on the open end side of the closed end section of the rotor, and a stator fixed to the main body at a part of the angular range on the radial outer side of the rotator, the linear actuator being configured such that the rotor is supported by the main body at the open side and the closed end of the magnet and the stator winding so as to be rotatable about the axis of the rotor, and such that the whole of the hollow rotor is accommodated in the sealed space. |
| US09941766B2 |
Penetrator power connector for an integrated rotary machine
A power connector for an electric motor is disclosed. The power connector includes a flange, a conductor rod, and an insulation sleeve. The conductor rod includes a first portion extending in a first direction from the flange and a second portion extending from the flange in a second direction, opposite the first direction. The second portion includes a lead wire connection end distal to the flange. The insulation sleeve covers the second portion from the flange to the lead wire connection end. The insulation sleeve includes a sleeve outer surface, and a sealing rib extending outward from the sleeve outer surface. |
| US09941759B2 |
Stator winding arrangement of superconducting rotating machine
A unit winding formed by bundling conductor strands in a first slot first sectional region from one end in a stator axial direction toward the other end is turned back so that positions of the insulating conductor strands are inverted in the axial direction. The unit winding is disposed into a second slot third sectional region from the other end in the axial direction toward the one side, and turned back so that the positions of the strands are inverted in a circumferential direction. Then, the turned back unit winding is disposed into the first slot second sectional region from the one end in the axial direction toward the other side, and turned back so that positions of the strands are inverted in the axial direction. The unit winding is disposed in the second slot fourth sectional region from the other end in the axial direction toward the one end. |
| US09941755B2 |
Method and apparatus for transmitting power wirelessly
Disclosed are an apparatus and a method for transmitting power wirelessly. The method for transmitting power wirelessly includes: detecting whether a receiving apparatus moves while wirelessly transmitting the power to the receiving apparatus through magnetic inductive coupling; performing the magnetic inductive coupling with the receiving apparatus for each of two or more primary coils when it is detected that the receiving apparatus moves; and determining whether to change the primary coil connected with the receiving apparatus based on a result of the magnetic inductive coupling. A signal strength message received from the receiving apparatus is received and stored every primary coil magnetically inductively coupled with the receiving apparatus, and it is determined that the received apparatus is connected through a primary coil corresponding to a largest value among signal strength values included in the signal strength message. |
| US09941753B2 |
Power transmission apparatus for detecting relative position of resonators based on a coupling coefficient
A power transmission apparatus oscillates alternating current power at a first frequency (f1) which is lower than a resonant frequency (fr) of the second resonator and at a second frequency (f2) which is higher than the resonant frequency (fr). The power transmission apparatus measures an inductance value Lin (f1) and an inductance value Lin (f2). The inductance value Lin (f1) is measured when the oscillation circuit oscillates alternating current power at the first frequency (f1), and the inductance value Lin (f2) is measured when the oscillation circuit oscillates alternating current power at the second frequency (f2). The power transmission apparatus calculates a coupling coefficient k by using an expression represented by k2=1−Lin(f2)/Lin(f1), to detect relative position of the second resonator to the first resonator on the basis of the coupling coefficient k. |
| US09941744B2 |
Non-contact power supply circuit
A power supply circuit is disclosed. The power supply circuit includes a primary circuit having at least one transmitting coil and a secondary circuit having at least one receiving coil. The primary circuit and secondary circuit are electromagnetically coupled. The total quantity of the at least one transmitting coil and the at least one receiving coil is greater than two. |
| US09941739B2 |
Process bus associated protective control system, merging unit, and calculation device
A protective control system includes an IED (Intelligent Electric Device) and a merging unit. The merging unit receives a current/voltage waveform signal of a power system, and outputs a digitally converted analog data to a process bus via a communication line as a serial signal. The IED is configured to be capable of transmitting a trip instruction to the merging unit using both the process bus and a station bus. The trip instruction is for outputting the trip signal. Preferably, each of the merging unit and the IED includes a switching circuit that makes switching to the station bus when an error is detected in the process bus communication. In the event of the process bus error, communication made by the process bus is switched to communication made by the station bus. Accordingly, reliability of the process bus can be improved. |
| US09941736B1 |
Secondary power system for light standard
A secondary power system for a light standard having primary power system that is operable at a first voltage. The secondary power system includes an electrical outlet, a power supply and an electrical cord. The electrical outlet has at least one receptacle. The electrical outlet is attachable to the light standard. The power supply is capable of converting an input current at the first voltage to an outlet current at a second voltage that is different than the first voltage. The power supply includes a first connection point and a second connection point. The power supply is mountable in an interior of the light standard. The electrical cord has a first end and a second end. The first end is attached to the electrical outlet. The second end is attached to the power supply. |
| US09941734B2 |
Storage battery system and solar power generation system having the same
A solar power generation system includes a storage battery, a solar power generation device that is provided on the side of the storage battery and outputs solar generated power, and a power control device. The power control device includes a variation component extraction unit that extracts a shade variation component from a generated power signal measured by the solar power generation device, a smoothing unit that smoothens the shade variation component obtained by the variation component extraction unit, a system output correction unit that obtains a system output power target value which is a combined output between a discharge output of the storage battery and the solar generated power on the basis of an output signal from the smoothing unit, and a charge/discharge output correction unit that corrects a charge/discharge target value which is a difference between the system output power target value and the generated power signal on the basis of a current time and a state of charge of the storage battery. |
| US09941730B1 |
Wireless charging station
Described herein are example charging stations for wirelessly recharging a variety of mobile devices. In some cases, the charging station is configured to receive a location indication of an antenna within the device, to determine a position of the device within the charging station, and to select an antenna from an array of antennas to provide a recharge signal to the device based on the location indication and the position of the device. |
| US09941729B2 |
Single layer multi mode antenna for wireless power transmission using magnetic field coupling
Various embodiments of a single structure multiple mode antenna are described. The antenna is preferably constructed of a single layer having a first inductor coil that is electrically connected in series with a second inductor coil. The antenna is constructed having a plurality of electrical connections positioned along the first and second inductor coils. A plurality of terminals facilitates connection of the electrical connections thereby providing numerous electrical connection configurations and enables the antenna to be selectively tuned to various frequencies and frequency bands. |
| US09941726B2 |
Protection and management of a power supply output shorted to ground
In some examples, a circuit is configured to receive an input signal and deliver, based on the input signal, a charging current to a capacitor. The circuit may be further configured to receive an output voltage that indicates a charge on the capacitor. The circuit may be further configured to determine that the output voltage is shorted to a reference ground. The circuit may be further configured to reduce, based on determining that the output voltage is shorted to the reference ground, the charging current. |
| US09941725B2 |
Method and electronic device for supplying power to battery
A method and an electronic device for supplying power to a battery are provided. The electronic device includes a housing, a battery disposed inside the housing, and a power management circuit configured to control power supplied from an external power source to the battery. The power management circuit is configured to supply power from the external power source to the battery to apply a substantially constant current to the battery during a first time interval, supply power from the external power source to the battery to maintain a substantially constant voltage in the battery during a second time interval following the first time interval, sense a current value applied to the battery and a voltage value of the battery, and determine a duration of the first time interval based on at least part of the sensed current value and the sensed voltage value. |
| US09941724B2 |
Method and apparatus for controlling charging in electronic device
A method for controlling charging in an electronic device for managing the electronic device, to stably charge a battery is provided. The method includes setting alarm such that a wake up signal is generated after a time elapses when entry into a suspend mode is requested during charging a battery or in a charging stop state, entering the suspend mode, waking-up and determining a state of the battery wake up, and turning-on or -off the battery charging according to the determined state of the battery. |
| US09941714B2 |
Battery system and motor vehicle with battery system
A battery system is described, comprising a battery management unit, a battery cell monitoring unit, at least one battery cell and a safety electronics system for the battery cell. The safety electronics system has a first comparator and an alarm signal output for an alarm signal. The first comparator compares a battery cell voltage of the battery cell to a predetermined threshold voltage value and generates the alarm signal on the basis of the comparison. The battery threshold voltage is lower than the battery cell voltage in normal operation and higher than a critical voltage value. In addition, a motor vehicle with the battery system is described, the battery system being connected to a drive system of the motor vehicle. |
| US09941712B2 |
Electrical storage system
An electrical storage system includes a relay switching between an on state where an electrical storage device (10) is connected to a load and an off state where connection of the electrical storage device with the load is interrupted; a controller controlling an on-off state of the relay; and a current interruption circuit (60) interrupting energization of the electrical storage device. The current interruption circuit includes an alarm circuit (63) outputting an alarm signal indicating that any one electrical storage block is in an overcharged state by comparing a voltage value of each electrical storage block with a threshold; a latch circuit (64) retaining the alarm signal; a transistor (66) causing the relay to switch from the on state to the off state upon reception of an output signal of the latch circuit; and a power supply circuit (63d) generating electric power for operating the latch circuit using electric power of the electrical storage device. |
| US09941708B2 |
Systems, methods, and apparatus for integrated tuning capacitors in charging coil structure
Systems, methods, and apparatus are disclosed for power transfer including a plurality of coil structures located over a ferrite element, the plurality of coil structures configured to generate a high flux region and a low flux region, the low flux region being located between the plurality of coil structures, and a tuning capacitance located directly over the ferrite element in the low flux region. |
| US09941706B2 |
Wireless power safety component
Techniques of providing increased safety for wireless systems are described herein. A wireless power receiving unit includes a first receiving coil to inductively couple to a wireless power transmitting unit having a transmitting coil. A safety component is provided to reduce wireless power received at a second receiving coil from the wireless power transmitting unit. |
| US09941697B1 |
System using a subcircuit shared between capacitors for providing reactive power
Systems and devices that provide a shared detuning, damping, or filtering element to one or more capacitors. A number of circuit branches are coupled in parallel to each other between a first coupling point and a second coupling point. A subcircuit is coupled between the second coupling point and a third coupling point. Each branch includes at least one capacitor that provides reactive power to power systems while the subcircuit is configured to provide detuning, damping, or filtering to the multiple branches. |
| US09941696B2 |
Establishing communication and power sharing links between components of a distributed energy system
Disclosed herein is a method and system for sharing power or energy across various power supply and control modules. More specifically, disclosed herein are systems and methods for distributing energy. As explained herein, the method discloses receiving, at a microgrid, data from a plurality of data sources. The data is then analyzed to forecast power needs associated with the microgrid. Using the data, the microgrid may determine whether and when to share power with the requesting module. |
| US09941694B2 |
Power supply system
A power supply system includes first and second DC power supplies and a power converter. The power converter includes first and third semiconductor elements electrically connected between respective nodes of a first node and a second node and a power line, second and fourth semiconductor elements electrically connected between respective nodes of the first node and the second node and a second power line, a fifth semiconductor element electrically connected between the first and second nodes, and first and second reactors. The first reactor is electrically connected in series with the first DC power supply, between the first node and the second power line. The second reactor is electrically connected in series with the second DC power supply, between the second power line and the second node. A control device controls on and off of the switching element included in the semiconductor element. |
| US09941693B2 |
Method of forming a bus coupler and structure therefor
In one embodiment, a bus coupled includes a voltage control circuit configured to selectively conduct a current from the first current source away from an output of the coupler to regulate a voltage drop across the another current source to a first value. An embodiment of a method of forming a bus coupler may include configuring a circuit to store energy from the input into a first storage element in response to receiving an active portion of an input signal, and to transfer energy from the storage element to the output after termination of the active portion of the input signal. |
| US09941682B2 |
Terminal-equipped wire
A terminal-equipped wire is provided with an insulated wire including a core and an insulation coating covering the periphery of the core, a terminal including a wire connecting portion connected to the insulated wire, a heat shrinkable tube configured to cover the periphery of the wire connecting portion while being shrunk by receiving heat, and a sheet-like intervening member provided between the heat shrinkable tube and the terminal. |
| US09941681B2 |
Chain header with shield design
A cable guiding-protecting chain comprises a plurality of chain members and at least a header. The chain members have a front end and a rear end that are pivotally connected to each other to form a chain. The header is pivotally to the chain member at a distal end of the chain and the header includes a base and a cover. The base has a body with a hole formed therein and a first fastening unit is provided in the hole. The cover has two side walls spaced apart from each other, a top wall connecting the two side walls and a second fastening unit provided to the two side walls, the second fastening unit of the cover is engaged with the first fastening unit of the base in the header so as to allow the two side walls, the top wall and the base to cooperate to define a receiving space through which a cable passes. |
| US09941678B2 |
Electrical connection box
An electrical connection box includes a frame, and a plurality of blocks each provided with a relay and the like and installed in the frame. The block is placed in an upper side in the frame. At least a portion of the block is placed under the block in a manner overlapping with the block. The relay provided to the block is connected to an electrical wire. The electrical wire is drawn horizontally from the block. |
| US09941677B2 |
Electrical wire guide
An electrical wire guide including a plurality of link members that are lined up along one direction, and are coupled together so as to be rotatable relative to each other. The link members are respectively provided with: through holes that extend in an intersection direction intersecting a direction in which the link members are lined up; and lock protrusions that are each provided with a claw that is locked to a peripheral portion around the corresponding through hole and protrudes in the intersection direction. The lock protrusions of the plurality of link members protrude in the same direction. The link members are coupled together by the lock protrusions being locked to the through holes. |
| US09941676B2 |
Cable pulling device with positioning and holding plates
A roller support structure is used during wire or cable installation for substantial labor savings during the wire or cable pulling process and for protection of the wire or cable. The wire or cable is pulled through a cable fitting by installing a roller support structure containing rollers onto the fitting. In some embodiments the rollers are removed from the cable fitting after a cable is pulled through the fitting. For efficient roller removal, the roller support structure has positioning and holding plate pairs. By moving the positioning plates relative to the holding plates, the rollers are held in place or dropped from channels in the holding plates. In another novel embodiment, a cable fitting slide plate structure is used to move a cable through a cable fitting. This structure includes a low friction inside bottom surface plane of arcuate shape for efficient movement of the cable through the fitting. |
| US09941675B2 |
Switch cabinets for use in electrical switchgear and methods of assembling the same
A switch cabinet includes a pair of opposing side panels. At least one side panel of the pair of side panels includes an opening defined therein. The switch cabinet also includes at least one component removal system coupled to the at least one side panel. The component removal system is selectively movable between a first position to prevent withdrawal of an electrical component through the opening and a second position to enable withdrawal of the electrical component through the opening. |
| US09941674B1 |
Systems for motor control center buckets
A control house includes a motor control center. The motor control center includes a body, and the body includes a face. The motor control center also includes a first orientation bucket that is configured to be disposed at least partially within the body at a first plurality of positions. The first position of the first plurality of positions extends a first distance from the face, and the first position of the first plurality of positions is configured to couple the first orientation bucket to first contacts. A second position of the first plurality of positions extends a second distance from the face that is greater than the first distance, and the second position of the first plurality of positions is configured to decouple the orientation bucket from the first contacts. Additionally, the second distance is less than or equal to 160 millimeters. |
| US09941667B2 |
Three-color light source
A three-color light source 1 is a three-color light source that combines red, green, and blue laser light so as to output light. The three-color light source 1 includes a red LD 11, a green LD 12, a blue LD 13, a first collimator lens 61, a second collimator lens 62, a third collimator lens 63, a first wavelength filter 81, a second wavelength filter 82, a carrier 30 that is equipped with the LDs 11 to 13, the collimator lenses 61 to 63, and the wavelength filters 81 and 82, and a TEC 40 that is equipped with the carrier 30. The red LD 11 is formed of a GaAs-based material, and the green LD 12 and the blue LD 13 are formed of GaN-based materials. |
| US09941666B2 |
Method for producing quantum cascade laser and quantum cascade laser
A method for producing a quantum cascade laser includes the steps of forming a laser structure including a mesa structure and a buried region embedding the mesa structure; forming a mask on the laser structure, the mask including a first pattern that defines a λ/4 period distribution Bragg reflector structure and a second pattern that defines a 3λ/4 period distribution Bragg reflector structure; and forming a first distribution Bragg reflector structure, a second distribution Bragg reflector structure, and a semiconductor waveguide structure by dry-etching the laser structure through the mask, the semiconductor waveguide structure including the mesa structure that has first and second end facets. The first distribution Bragg reflector structure is optically coupled to the first end facet. The second distribution Bragg reflector structure is optically coupled to the second end facet. Here, λ denotes a value of an oscillation wavelength of the quantum cascade laser in vacuum. |
| US09941665B1 |
Optical device structure using GaN substrates and growth structures for laser applications
Optical devices having a structured active region configured for selected wavelengths of light emissions are disclosed. |
| US09941664B1 |
Hybrid III-V on silicon laser device with transverse mode filter
A hybrid III-V on silicon laser device includes a layer structure, with a stack of III-V semiconductor gain materials, a silicon waveguide core and a cladding structure. The semiconductor gain materials stack is along a stacking direction, which is perpendicular to a main plane of the stack. The silicon waveguide core extends along a longitudinal direction, parallel to the main plane. The cladding structure extends between said waveguide core and the stack. The device further comprises an optical coupling structure formed in the layer structure. This coupling structure is designed: 1) to allow a hybrid-mode optical coupling of radiation between the stack of III-V semiconductor gain materials and the tapered waveguide core; and 2) to favor a coupling of a fundamental transverse optical mode of said radiation over a coupling of one or more higher-order transverse optical modes of said radiation from the stack into the waveguide core. |
| US09941663B2 |
Hybrid vertical cavity light emitting sources
Vertical cavity light emitting sources that utilize patterned membranes as reflectors are provided. The vertical cavity light emitting sources have a stacked structure that includes an active region disposed between an upper reflector and a lower reflector. The active region, upper reflector and lower reflector can be fabricated from single or multi-layered thin films of solid states materials (“membranes”) that can be separately processed and then stacked to form a vertical cavity light emitting source. |
| US09941661B1 |
System for maintaining the locking range of an injection locked laser array within range of the frequency of a master laser
A system for maintaining the locking range of an injection locked laser array within range of a frequency of a master laser includes first and second photodetectors. An injection locked laser array has a locking frequency range around a free running frequency controlled in response to a control signal. The laser array produces respective beams phase modulated at relative unique frequencies. A mask, has apertures with shapes, sizes, and positions identical to the shapes, sizes and positions of the lasers in the laser array. A first master laser produces a beam at a first frequency coupled to the laser array and illuminating the mask. A second master laser produces a beam at a second frequency separated from the first frequency by substantially the locking range of the laser array coupled to the laser array and illuminating the mask. Optics forms images of the reference beams of the first and second master lasers from the mask to the first and second photodetectors respectively, and forms images of the beams from the laser array to the same locations on the first and second photodetectors as the corresponding reference beams from the mask, A frequency controller, responsive to respective composite signals from the first and second photodetectors, detects modulation harmonics corresponding to each beam from the laser array from the first and second photodetectors and produces a frequency control signal. |
| US09941656B2 |
Polarization-maintaining (PM) double-clad (DC) optical fiber
A double-clad (DC) polarization-maintaining (PM) optical fiber comprises a core, an inner cladding, an outer cladding, and stress rods. The core has a core refractive index (ncore). The inner cladding is located radially exterior to the core and has an inner cladding refractive index (n1), which is less than ncore. The stress rods are located in the inner cladding, and each stress rod has a stress rod refractive index (n2), which is substantially matched to n1. The outer cladding is located radially exterior to the inner cladding. The outer cladding has an outer cladding refractive index (nout), which is less than n1. |
| US09941654B2 |
Fiber-laser pumped crystal-laser
An apparatus for generating and amplifying laser beams at approximately 1 micrometer wavelength is disclosed. The apparatus includes an ytterbium-doped gain-crystal pumped by an ytterbium fiber-laser. The fiber-laser enables a pump wavelength to be selected that minimizes heating of the gain-crystal. The apparatus can be configured for generating and amplifying ultra-fast pulses, utilizing the gain-bandwidth of ytterbium-doped gain-crystals. |
| US09941653B2 |
Optical array comprising a beam splitter
The invention relates to an optical array comprising a splitting element (1) which splits an input beam (E) into at least two partial beams (T1, T2, T3, T4), at least one optical element (V1, V2, V3, V4, MV) through which at least one of the partial beams (T1, T2, T3, T4) propagates, and at least one combining element (4) which spatially superimposes the partial beams (T1, T2, T3, T4) in one output beam (A). The object of the invention is to provide an optical array which is improved over the prior art and which permits effective and simple splitting of the input light beam, in particular a laser beam with pulsed or continuous emission. The invention achieves this object in that the splitting element (1) and/or the combining element (4) each have a partially reflective element (2, 2′) which reflects the radiation of the input beam (E) or of the output beam (A) two or more times, wherein the partially reflective element (2, 2′) has zones (a, b, c, d) of different reflectivity. |
| US09941651B1 |
Systems and methods for generating electric power with an electric motor
The present invention uses a traditional electrical motor with a rotor to generate electricity or power. By manipulating the magnetic fields within a rotor, large amounts of electricity are generated by the rotation of the rotor within an external magnetic field. Oppositely charged rare-earth magnets are placed around the rotor to create a strong magnetic field that the rotor can spin or rotate within. A battery or other power source supplies power to the rotor at positive and negative terminals (brushes) that are connected to commutator. The positive and negative terminals contact the commutator close to each other, such that only a few windings or coils are charged or magnetized, and the remaining windings or coils are free to generate electricity within the external magnetic field. The few coils that are charged in combination with the external magnetic fields create sufficient rotation, while enabling the remaining “free” coils to generate electric power. This power or electricity that is generated is then collected at a terminal about 150-200 degrees from the positive and negative terminals from the power source. The rotor may be offset or closer to one set of magnets, which further improves power generation. |
| US09941647B2 |
Power apparatus with outlet identification capability and outlet identification method of power apparatus
A power apparatus with outlet identification capability and outlet identification method of power apparatus, the outlet identification method uses an identification requirement to enable a power apparatus to identify a plug-in position of at least one powered device, the identification requirement has an internet protocol address and an outlet code of at least one powered device; the power apparatus includes a power distribution equipment, the power distribution equipment has a plurality of outlets, when the power distribution equipment receives an identification requirement, at least one indicator light can be driven to radiate according to the identification requirement, or at least one PDE display can be driven to show an outlet code of the identification requirement. |
| US09941645B2 |
Compact plug assemblies for plug and socket unit isolator systems for motor control centers (MCC)
Circuit breakers with cooperating plug and socket assemblies which are configured as separate spaced apart components, with plugs and sockets held spaced apart from the circuit breaker body, typically above the top of the circuit breaker body. The plug assembly can have a short compact profile and can include pairs of plugs held by an insulated support with a compact spacing between adjacent pairs and upper and lower plugs of each plug pair. The plug assembly can be attached to a racking frame to allow the plug assembly to be retracted during a rack-out action of the unit from a motor control center. |
| US09941641B1 |
Male connector
A new connector with effective shielding function. The new connector includes conductive shielding, a connector body and a set of terminals. The connector body is provided with a cavity within which the set of terminals can be accommodated and is made from plastic cement; the set of terminals are located within the cavity of the connector body. The conductive shielding can be inserted between the connector body and the set of terminals, and specifically includes several shielding bars and conductive areas; the shielding bars are made from metal, and the conductive areas, which are embedded in the shielding bars and connected with the ends of the set of terminals, are made from conductive plastic cement. |
| US09941639B2 |
Shielding arrangement for high-current applications
A shielding system for high-current applications, having a connecting cable that has an insulated conductor (22) and a cable shielding surrounding the insulated conductor, as well as a shielding housing having a feed-through. In addition, the shielding system has a hollow cylindrical and electrically conductive shielding sleeve. The insulated conductor is fed through the shielding sleeve. The shielding sleeve is situated in the area of the feed-through of the shielding housing, so that the shielding housing abuts a jacket surface of the shielding sleeve. The cable shielding lies against a jacket surface of the shielding sleeve. The cable shielding is electrically connected to the shielding housing via the shielding sleeve. |
| US09941638B2 |
Electrical cord having plugs with improved safety features
An electrical cord having improved safety features comprises a plug having a body portion surrounding respective ends of first, second, and third electrical wires. A live receptacle is in electrical communication with the end of the first electrical wire. A neutral receptacle is in electrical communication with the end of the second electrical wire. A ground receptacle is in electrical communication with the end of the third electrical wire. The body portion surrounds and maintains the live, neutral, and ground receptacles in spaced apart orientation corresponding to blades on an electrical plug. An indicator is provided to indicate a state of the plug in which electricity is supplied to the plug in a proper polarity. |
| US09941637B2 |
Connection device
A connection device in the present disclosure, which is a connection device capable of detachably connecting a cable, includes a first terminal to be connected to a second terminal of the cable, a holding mechanism for maintaining a connection state between the first terminal and the second terminal, and a controller that acquires environment information around the connection device and changes holding force of the holding mechanism based on the environment information. |
| US09941635B2 |
Connector housing
A connector housing includes a housing body and a fitting operation lever that has a swinging portion attached to the housing body rotatably. A part of the rib protruding toward the swinging portion narrows an interval between a curved portion of the housing body and the swinging portion to a predetermined value or below. A part of the rib protruding toward a direction separating from a lower surface of the housing body has a flat face. A distance between the rotary axis of the swinging portion and the flat face is larger than a distance between the rotary axis and a part of an outer circumferential edge of the swinging portion. |
| US09941633B2 |
Connector for the connection to the on-board diagnostics of a vehicle
The connector (1) for the connection to the on-board diagnostics of a vehicle, comprising a container body (2) associable with an electronic connection port (A) of an on-board diagnostic system of a vehicle, a plurality of electrical terminals (3) supported by the container body (2) and connectable to corresponding electrical terminals (B) of the connection port (A), at least a protruding element (4) associated with the container body (2) and engageable in correspondence of at least a respective locator element (C) onto the connection port (A), and blocking means (5) of the protruding element (4) in correspondence of the locator element (C), able to prevent undesired disconnections of the connector itself from the connection port (A). |
| US09941628B2 |
Connector assembly
A connector assembly includes first and second connectors. The first connector has a first housing and a first locking portion. The second connector has a second housing and a second locking portion. The first housing is formed with a resiliently supporting portion which rotatably supports the first locking portion. The first locking portion is positioned between a front end and a rear end of the first housing in a mating direction. When the first connector is mated with the second connector, the second locking portion is positioned between the first locking portion and the rear end of the first housing in the mating direction. When seen along the mating direction, the first locking portion and the second locking portion have a first extent and a second extent, respectively, in an orthogonal direction. When the first connector is mated with the second connector, the first extent overlaps with the second extent. |
| US09941624B2 |
Protector for RF connector
A protector for an RF connector includes a first sealing assembly for connection with a cable and a second sealing assembly for connection with a communication equipment. The first sealing assembly includes a sealing ring for matching with a sheath of the cable and a member which has an internal thread or elastic structure for matching with the RF connector. The second sealing assembly is provided with an elastic silicone rubber jacket for connection with the communication equipment. |
| US09941611B2 |
Connection structures for providing a reference potential to a flexible circuit device
Techniques and mechanisms for providing a reference potential with a flexible circuit device. In an embodiment, the flexible circuit device includes a first interconnect to exchange a signal and a second interconnect to exchange a reference potential that facilitates shielding of the signal. The first and second interconnects are variously coupled to a printed circuit board (PCB) via a first contact and a second contact of a hardware interface. During such coupling, a maximum height of the second interconnect from a side of the PCB at the hardware interface is greater than a maximum height of the first interconnect from the side of the PCB at the hardware interface. In another embodiment, a distance of the first contact from an end of the flexible circuit device is different than a distance of the second contact from the end of the flexible circuit device. |
| US09941607B2 |
Coaxial cable connector, carrier-equipped coaxial cable connector, and method for manufacturing coaxial cable connector
There is provided a coaxial cable connector, etc., configured such that the outer conductor shell and the connector carrier are linked by a carrier linkage part provided to part of the edge portion between the distal end and the portion of the outer conductor shell of a coaxial cable connector excluding the crimper, and the connector carrier is disposed on the distal end side of the outer conductor shell (the opposite side from the housing carrier), which simplifies the configuration of the apparatus used to manufacture the coaxial cable connector, and allows the coaxial cable connector to be assembled with the fixing position of the outer conductor shell stabilized while still linked to the connector carrier in the manufacturing process. |
| US09941606B1 |
Coaxial cable connector and method of use thereof
A coaxial cable connector comprises a signal contact member having an inner conductor connecting portion, a grounding contact member, and an insulating housing for supporting the signal contact member and the grounding contact member in a condition of mutual isolation, wherein the insulating housing is provided with a concavity which has a bottom on which the inner conductor connecting portion of the signal contact member is placed and an opening through which the inner conductor of the coaxial cable is caused to come into contact with the inner conductor connecting portion of the signal contact member placed on the bottom of the concavity and is operative to allow an ultrasonic vibration horn to be put into the concavity through the opening of the concavity for applying ultrasonic vibrations to the inner conductor of the coaxial cable put in contact with the inner conductor connecting portion of the signal contact member. |
| US09941604B2 |
Electric receptacle having a mounting strap and a plurality of terminal openings
An electric receptacle includes a housing having a front surface including a socket opening, a back surface opposite the front surface, a first outer edge, and a second outer edge. A neutral terminal is at least partially retained in the housing. A phase terminal is at least partially retained in the housing. A first neutral opening faces the first outer edge and is in communication with the neutral terminal. A second neutral opening faces the back surface and is in communication with the neutral terminal. A first phase opening faces the second outer edge and is in communication with the phase terminal. A second phase opening faces the back surface and is in communication with the phase terminal. A mounting strap can be snap-fit to the housing. |
| US09941602B2 |
Terminal capable of positively scraping off insulating coating of an electric wire
A terminal that is capable of positively scraping off insulation coating of an electric wire. A wire connection portion is formed with a slit. A pair of positioning portions and a pair of supporting portions are disposed with the slit of the wire connection portion therebetween. A spacing between the pair of supporting portions is smaller than a spacing between the pair of positioning portions. Each supporting portion is formed with a corner portion in an end portion thereof toward a positioning portion associated therewith. Each positioning portion is formed with a cutout in an end portion thereof toward the supporting portion. An inner surface of the cutout is continuous with a surface of each corner portion toward the positioning portion. |
| US09941601B2 |
Terminal, wire harness, and wire-harness structure
A transition portion (4) has a surface (14) that is formed extending upward. The surface (14) is a surface formed extending upward so as to face a bottom portion (6a). Specifically, the transition portion (4) has a cross-sectional shape in which upper edge portions of side portions (8a) are bent inward. As the surface (14) approaches a main terminal body (3) from a sealing portion (22), the surface (14) gradually separates away from the bottom portion (6a) and the edge portions of the surface (14) gradually open outward and connect to side portions (8b) of the main terminal body (3). The surface (14) is formed so as to be curved upward, in a cross-section, from the end portion of the sealing portion (22). |
| US09941600B2 |
Ultra low profile conformal antenna system
A low profile conformal high gain multi-beam aircraft antenna includes antenna elements supported by a ground plane to create the low profile conformal high gain multi-beam aircraft antenna. Some of the antenna elements include a feeding waveguide flared in at least one of an h-plane and a v-plane. The antenna elements cooperate to create a gain pattern near a plane of the antenna. |
| US09941592B2 |
Transmitarray unit cell for a reconfigurable antenna
Unit cell including a receive antenna, a transmit antenna, and including first and second radiation surfaces separated from each other by a separation area, a phase-shift circuit comprising switches, each having an on, respectively off, state, wherein the corresponding switch allows, respectively blocks, the flowing of a current between the first and second radiation surfaces; a ground plane; a first printed circuit board including a first surface provided with the receive antenna, and a second opposite surface provided with the ground plane; a wafer of a semiconductor material including a first surface provide with first and second radiation surfaces and wherein the switches are formed in the separation area, monolithically with the transmit antenna. |
| US09941589B2 |
Non-contact communication antenna, communication device, and method for manufacturing non-contact communication antenna
There is provided a non-contact communication antenna including a first antenna pattern that is formed on one surface of a base material, and a second antenna pattern that is formed on a back surface of the one surface of the base material. The first antenna pattern includes a first coil section and a first electrode section. The second antenna pattern includes a second coil section and a second electrode section. Capacitance of the first electrode section and the second electrode section compensates a change in capacitance depending on a formation situation of the first coil section and the second coil section. |
| US09941588B2 |
Antenna with multiple coupled regions
A device includes a plurality of antennas, including one or more active antennas, the antennas being configured in one of a plurality of possible configurations to achieve operation in WAN, LTE, WiFi, or WiMax bands, or a combination thereof. In some embodiments, a passive antenna is utilized with lumped loading to fix the antenna tuning state. A primary and auxiliary radiator can be included in the device and configured for WAN/LTE bands, while additional antennas can be incorporated for WiFi and WiMax bands. Various antenna configurations incorporate the antenna having multiple coupled regions. |
| US09941587B2 |
3×3 Butler matrix and 5×6 Butler matrix
The present invention relates to a 3×3 Butler matrix, comprising a first directional coupler, a second directional coupler, a third directional coupler, a first fixed phase shifter, a second fixed phase shifter and a third fixed phase shifter; and also relates to a 5×6 Butler matrix, comprising a first 3×3 Butler matrix, a second 3×3 Butler matrix, a fourth directional coupler, a fifth directional coupler, a power divider, a fourth fixed phase shifter and a fifth fixed phase shifter. The 3×3 Butler matrix and the 5×6 Butler matrix provided in the present invention have the features of small size, wide frequency band, low loss, high isolation and stable performance, fill the blank of specific technical schemes about the 3×3 Butler matrix and the 5×6 Butler matrix in the prior art, and have broad application prospects and great value. |
| US09941583B2 |
Lightning protection device for an antenna receiver, and aircraft comprising same
A lightning protection device for an antenna receiver includes a shield for a coaxial cable connected to the antenna, and a high-pass filter mounted in series relative to the shield and capable of limiting the low-frequency power flowing in the coaxial cable, including a capacitor and an inductor lower than 1 ohm at the lowest frequency used by the receiver, the capacitor including at least one layer of a conductive material embedded in a printed circuit. The capacitor may be made of a printed circuit including at least two floor plans, each of which is connected to the ground of a connector of the coaxial cable. The printed circuit may include at least one layer of a highly pervious material sandwiched between two layers of a conductive material. |
| US09941582B2 |
Switch module, front-end module, and driving method for switch module
A switch module selects one of a CA mode in which first and second frequency bands are used simultaneously and a non-CA mode in which only one of the first and second frequency bands is used. The switch module includes a first signal path propagating the first frequency band therethrough, a second signal path propagating the second frequency band therethrough, a third signal path simultaneously propagating the first and second frequency bands therethrough, a switch circuit, and a variable adjuster. The switch circuit switches the connection between an antenna device and one of the three signal paths. The variable adjuster adjusts a variable matching circuit for the third signal path when the non-CA mode is selected or adjusts a variable matching circuit for the first signal path or that for the second signal path when the CA mode is selected. |
| US09941578B2 |
Minimal reactance vehicular antenna (MRVA)
An antenna comprising: a hollow conductive chamber having an upper end and a lower end, wherein the lower end is open; a shorting strap electrically connected to the upper end; a conductive center member running through the chamber and electrically connected to the shorting strap; a conductive ground plane having a top surface and a bottom surface, wherein the top surface is separated from the lower end of the chamber by a gap; and a first solid insulator connected to the chamber and the top surface of the ground plane such that the first insulator fills the gap and fills the lower end and an interior portion of the chamber. |
| US09941577B2 |
Antenna, circular polarized patch antenna, and vehicle having the same
An antenna, a circular polarized patch antenna, and a vehicle having the same are provided. The antenna includes a substrate, a ground portion formed on a first surface of the substrate, and a second radiator having a plurality of patches and formed on a second surface of the substrate. In addition, a first radiator is formed in a periphery of the second radiator with a gap from the second radiator and a feeding probe is disposed on the first radiator to enable power to be fed directly fed to the first radiator and to enable power to be fed to the second radiator through coupling. |
| US09941572B2 |
NFC antenna assembly
An NFC antenna assembly is provided. One embodiment of the NFC antenna assembly disclosed herein includes: a metal plate defining a fitting aperture which penetrates through the metal plate in a thickness direction of the metal plate; a mounting sheet disposed in the fitting aperture; an insulating washer disposed in the fitting aperture and surrounding the mounting sheet; and an NFC antenna disposed on the mounting sheet, wherein the mounting sheet comprises a first through slot extended in a radial direction of the mounting sheet, and the metal plate comprises a second through slot extended from the fitting aperture to a periphery of the metal plate. |
| US09941566B2 |
Excitation and use of guided surface wave modes on lossy media
Disclosed are various embodiments for transmitting energy conveyed in the form of a guided surface-waveguide mode along the surface of a lossy medium such as, e.g., a terrestrial medium by exciting a guided surface waveguide probe. |
| US09941563B2 |
Ceramic filter using stepped impedance resonators having an inner cavity with at least one step and taper
Disclosed are embodiments of ceramic radiofrequency filters advantageous as RF components. The ceramic filters can include a ceramic stepped impedance resonator, wherein the inner diameter of the ceramic stepped impedance resonator can vary from one end to another end. The inner diameter can be, for example, tapered, sectioned, or stair-stepped in order to provide different impedances in the ceramic resonator. |
| US09941561B2 |
Systems and methods for high power RF channel selection
A switch is disclosed for selecting a port. The switch includes a dielectric layer, a first circuit, and a second circuit. The first and second circuits are disposed on the dielectric layer and electrically coupled to each other through the dielectric layer. The first circuit includes a set of ports. The switch further includes a control port for receiving a control signal and a plurality of switching elements. The control signal selects at least one of the set of ports to be connected to the second circuit by setting operational states of the plurality of switching elements. |
| US09941560B2 |
Non-contact on-wafer S-parameter measurements of devices at millimeter-wave to terahertz frequencies
A broadband fully micromachined transition from rectangular waveguide to cavity-backed coplanar waveguide line for submillimeter-wave and terahertz application is presented. The cavity-backed coplanar waveguide line is a planar transmission line that is designed and optimized for minimum loss while providing 50 Ohm characteristic impedance. This line is shown to provide less than 0.12 dB/mm loss over the entire J-band. The transition from cavity-backed coplanar waveguide to a reduced-height waveguide is realized in three steps to achieve a broadband response with a topology amenable to silicon micromachining. A novel waveguide probe measurement setup is also introduced and utilized to evaluate the performance of the transitions. |
| US09941558B2 |
Temperature-control device, in particular for a battery of a motor vehicle
A temperature-control device for a battery of a motor vehicle may include a temperature-control plate including at least two rows of elements. Each of the at least two rows of elements may include at least two Peltier elements. Each Peltier element may include a first electric supply connection and a second electric supply connection for supplying each Peltier element with electrical energy. A first electric supply path may be disposed on the temperature-control plate and may define at least one of an open surround and a closed surround around the Peltier elements of the at least two rows of elements. At least one second electric supply path may be disposed on the temperature-control plate and may extend along a direction of extent with respect to an extent of the at least two rows of elements. |
| US09941551B2 |
Touch sensor element for detecting critical situations in a battery cell
A battery cell, in particular a lithium-ion battery cell, is described, which comprises a negative electrode (25), a separator (24) and a positive electrode (23), wherein the battery cell has a touch sensor element (1) for detecting elements resting on the touch sensor element (1) or exerting pressure on the touch sensor element (1). |
| US09941547B2 |
Biomedical energization elements with polymer electrolytes and cavity structures
Designs, strategies and methods to form energization elements comprising polymer electrolytes are described. In some examples, the biocompatible energization elements may be used in a biomedical device. In some further examples, the biocompatible energization elements may be used in a contact lens. |
| US09941546B2 |
Bipolar battery and plate
A bipolar battery plate is utilized for production of a bipolar battery. The bipolar battery plate includes a frame, a substrate, first and second lead layers, and positive and negative active materials. The substrate includes insulative plastic with conductive particles homogeneously dispersed throughout the insulative plastic and exposed along surface of the substrate, the substrate positioned within the frame. The first lead layer is positioned on one side of the substrate, while the second lead layer is positioned on another side of the substrate. The first and second lead layer are electrically connected to each through the conductive particles. The positive active material is positioned on a surface of the first lead layer, and the negative active material positioned on a surface of the second lead layer. |
| US09941542B1 |
Battery assembly techniques
Battery assembly techniques and a corresponding system are disclosed. In various embodiments, the battery assembly techniques include compressing battery cells and inserting the battery cells in a can. Battery cells are stacked and then compressed using pneumatic cylinders that exert pressure on a first external layer of the stacked battery cells. A first portion of the stacked battery cells is released from the pneumatic cylinders while a second portion of the battery cells remains compressed. The first portion of the stacked battery cells is inserted in a can. In various embodiments, friction decreasing materials are added to the stacked battery cells to compress the stacked battery cells or ease insertion. |
| US09941538B2 |
Ion exchange membranes having low in-plane swelling
Disclosed is an ion exchange membrane comprising a film of a perfluorosulfonic acid ionomer in its acid form; the film having a low in-plane swelling, such that the length and/or width of the film changes by less than 10% when the membrane is exposed to water. Further disclosed is an electrochemical device, such as a polymer electrolyte membrane fuel cell, comprising an electrolyte comprising the ion exchange membrane. |
| US09941535B2 |
Fuel cell module
A fuel cell module includes a first area where an exhaust gas combustor and a start-up combustor are provided, an annular second area around the first area where a heat exchanger is provided, an annular third area around the second area where a reformer is provided, an annular fourth area around the third area where an evaporator is provided. A plurality of heat exchange pipes are provided in the heat exchanger around a first partition plate. At least one of the heat exchange pipes has at least one constricted portion. |
| US09941528B2 |
Fuel cell system
A fuel cell system includes a fuel cell module for generating electrical energy by electrochemical reactions of a fuel gas and an oxygen-containing gas, and a condenser for condensing water vapor in an exhaust gas discharged from the fuel cell module by heat exchange between the exhaust gas and a coolant to collect the condensed water and supplying the collected condensed water to the fuel cell module. The condenser includes an air cooling condenser using the oxygen-containing gas as the coolant and a water cooling condenser using hot water stored in a hot water tank as the coolant. A thermoelectric conversion mechanism for performing thermoelectric conversion by a temperature difference between the exhaust gas and the oxygen-containing gas is provided between the air cooling condenser and the water cooling condenser. |
| US09941527B2 |
Gas management systems and methods in a redox flow battery
A method of operating a redox flow battery includes providing a redox flow battery including an anolyte storage tank configured for containing a quantity of anolyte and an anolyte headspace, a catholyte storage tank configured for containing a quantity of a catholyte and a catholyte headspace, and a gas management system comprising at least one open conduit interconnecting the anolyte headspace and the catholyte headspace for free gas exchange between the anolyte and catholyte headspaces, and a passive gas exchange device in gaseous fluid communication with the anolyte headspace, the passive gas exchange device configured to release gas from the anolyte headspace to an exterior battery environment when an interior battery pressure exceeds an exterior battery pressure by a predetermined amount, and operating the battery. |
| US09941525B2 |
SOFC hot box components
Various hot box fuel cell system components are provided, such as heat exchangers, steam generator and other components. |
| US09941521B2 |
Method for producing core-shell catalyst
The disclosure is to provide a method for producing a core-shell catalyst that is able to increase the power generation performance of a membrane electrode assembly. A dispersion is prepared, in which a palladium-containing particle support, in which palladium-containing particles are supported on an electroconductive support, is dispersed in water; hydrogen gas is bubbled into the dispersion; the palladium-containing particles are acid treated after the bubbling; copper is deposited on the surface of the palladium-containing particles by applying a potential that is nobler than the oxidation reduction potential of copper to the palladium-containing particles in a copper ion-containing electrolyte after the acid treatment; and then a shell is formed by substituting the copper deposited on the surface of the palladium-containing particles with platinum by bringing the copper deposited on the surface of the palladium-containing particles into contact with a platinum ion-containing solution. |
| US09941519B2 |
Thin film lithium ion battery
A thin film lithium ion battery includes a cathode electrode, an anode electrode, and a solid electrolyte layer. The solid electrolyte layer is sandwiched between the cathode electrode and the anode electrode. At least one of the cathode electrode and the anode electrode includes a current collector. The current collector is a carbon nanotube layer consisting of a plurality of carbon nanotubes. |
| US09941518B2 |
Cathode binder composition, cathode slurry, cathode, and lithium ion secondary battery
Cathode binder composition having excellent binding properties and oxidation resistance. Also, cathode slurry, cathode, and lithium ion secondary battery produced using the cathode binder composition. The cathode binder composition contains a graft copolymer in which a monomer containing acrylonitrile as the main component is grafted onto polyvinyl alcohol having an average degree of polymerization of 300 to 3000 and a degree of saponification of 70 to 100% by mol. The cathode slurry contains the cathode binder composition, a cathode active material, and a conductive auxiliary. The cathode is produced using the cathode slurry. The lithium ion secondary battery contains a cathode prepared in this manner. |
| US09941512B2 |
Electrode material for non-aqueous electrolyte secondary battery, and electrode for non-aqueous electrolyte secondary battery and non-aqueous electrolyte secondary battery using the same
A core-shell-type electrode material is used as an electrode active material layer of a non-aqueous electrolyte secondary battery, the core-shell-type electrode material having a core part including an electrode active material and a shell part in which a conductive material is contained in a base material formed by a gel-forming polymer having a tensile elongation at break of 10% or more in a gel state. |
| US09941507B2 |
Method and apparatus for production of a thin-film battery
A method for production of a thin-film battery includes providing a mount structure, applying of a first unmasked flow of a first electrode material to the mount structure in order to form a first electrode layer, applying a second unmasked flow of a battery material in order to form a battery layer, and applying a third unmasked flow of a second electrode material in order to form a second electrode layer. The applying steps are repeated in order to produce a thin-film battery which consists of a plurality of first electrode layers, a plurality of battery layers, and a plurality of second electrode layers. |
| US09941506B2 |
Current collector, secondary battery, electronic device, and manufacturing method thereof
Part of an electrode, specifically a current collector and an active material layer, for a secondary battery is subjected to cutting processing to have a complex shape. For example, a stack of the first current collector and the first active material layer has a first slit and a second slit. The first slit extends from a first edge of the stack. The second slit extends from a second edge of the stack, is the slit closest to an electrode tab, and is not parallel or vertical to the longest edge of the current collector. |
| US09941503B2 |
Rechargeable battery having improved current density
A rechargeable battery according to one or more exemplary embodiments includes: a pair of electrode assemblies, each including a first electrode including a coated region, a tab, and a connecting tab, a second electrode including a coated region, a tab, and a connecting tab, and a separator between the first electrode and the second electrode, the first electrode, the separator, and the second electrode being wound; a case accommodating the pair of electrode assemblies; a cap plate at an opening of the case and defining terminal openings; and first and second electrode terminals respectively connected to the tabs of the first and second electrodes and respectively passing through the terminal openings. The pair of electrode assemblies are electrically connected to each other via the connecting tabs. |
| US09941501B2 |
Apparatus for a battery module
A battery module (4) has a large number of battery cells (6). Each battery cell (6) has a contact section (10) with a positive pole (14) and a negative pole (12) on an outer wall of the battery cell (6). An apparatus (20) for the battery module (4) has a terminal sheet (22) and a flat body (24) made of an electrically insulating material. The flat body (24) is between the terminal sheet (22) and the battery cells (6) and has holes (26) registered with the positive poles (14). Contact elements (30) extend from the terminal sheet (22) through the holes (26) in the flat body (24) and electrically connect the terminal sheet (22) to the positive poles (14). |
| US09941499B2 |
Nonaqueous electrolyte secondary battery separator, nonaqueous electrolyte secondary battery laminated separator, nonaqueous electrolyte secondary battery member, and nonaqueous electrolyte secondary battery
Provided is a nonaqueous electrolyte secondary battery separator that has (i) an excellent ion permeability and (ii) reduced occurrence of a leak defect despite a small thickness. The nonaqueous electrolyte secondary battery separator includes a porous film containing polyolefin as a main component, the nonaqueous electrolyte secondary battery separator having a Gurley value within a range of 50 sec/100 cc to 200 sec/100 cc, the nonaqueous electrolyte secondary battery separator having a thickness within a range of 3 μm to 16 μm, the nonaqueous electrolyte secondary battery separator satisfying 0.85≤((SMD/Sm)+(STD/Sm))/2≤0.91. |
| US09941496B2 |
On-board power source device
An on-board power source device comprises power storage modules. In the power storage modules, a plurality of power storage elements are arranged. The power storage module is stacked one upon another. An outlet of a discharge path is provided for discharging gas generated in the respective power storage elements. A frame member extends along the end portion of the power storage modules for fixing the respective upper and lower power storage modules. A bracket locates at the end portion of the power storage modules so as to cover the outlets, for fixing the upper power storage modules to the frame member. The frame member has a discharge space for discharging the gas to the outside of the vehicle. The bracket is provide with a passage part for communicating the outlet of the upper power storage module with the discharge space of the frame member. |
| US09941494B2 |
Battery pack
A battery pack including a battery cell, a plurality of electrode tabs coupled to and extending from terminals of the battery cell, a protect circuit module (PCM) to control charging and discharging of the battery cell, a flexible printed circuit board (FPCB) including a plurality of connection pads coupled to the electrode tabs and electrically coupling the battery cell to the PCM, and a case accommodating the battery cell, the electrode tabs, the PCM, and the FPCB, wherein the case includes a first case accommodating the battery cell and a second case covering the first case, and wherein the first case includes ribs extending toward the second case and has cut-out grooves at regions corresponding to the connection pads. |
| US09941492B2 |
Flexible secondary battery having a bonding portion extending in a lengthwise direction
A flexible secondary battery includes an electrode assembly and external material surrounding the electrode assembly having at least one bonding portion, wherein the external material is bonded to itself at the at least one bonding portion, and the at least one bonding portion extends in a lengthwise direction of the electrode assembly at an edge of the electrode assembly. |
| US09941487B2 |
Glass item, glass item having luminescent-substance particles, device for producing a glass item, method for producing a glass item, and method for producing a glass item having luminescent-substance particles
In various embodiments, glassware is provided. The glassware may include a glass matrix having a surface, a first type of particles, and at least one second type of particles, wherein the particles of the second type have a higher refractive index than the particles of the first type, wherein the particles of the first type are completely surrounded by the glass matrix, such that the surface of the glass matrix is free of particles of the first type, and the particles of the second type are arranged above and/or between the particles of the first type at least partly in the glass matrix at the surface of the glass matrix in order to increase the refractive index of the glassware. |
| US09941474B2 |
Method of manufacturing organic light-emitting diode display
A method of manufacturing an OLED display is disclosed. In one aspect, the method includes providing a donor substrate including a material formed on one surface thereof and heating the material so as to form a barrier thin-film on the donor substrate. The method also includes providing an acceptor substrate and a substrate attached to the acceptor substrate, forming an OLED unit over the substrate, bonding the OLED unit and the barrier thin-film together, and irradiating a laser beam on the barrier thin-film so as to delaminate the donor substrate from the barrier thin-film. |
| US09941473B2 |
Method for closely connecting an organic optoelectronic component to a connection piece, connection structure for force-locking connecting, and optoelectronic component device
Various embodiments relate to a method for closely connecting an organic optoelectronic component to a connection piece, including forming a first cavity in the organic optoelectronic component, wherein the first cavity has at least a first opening, introducing a connecting structure through the first opening into the first cavity, wherein the connecting structure has a first fixing area, wherein the first fixing area is configured partially complementarily to the form of the first cavity, forming a second cavity in a connection piece, wherein the second cavity has at least a second opening, wherein the second cavity is configured partially complementarily to the form of the second fixing area, and introducing a second fixing area through the second opening into the second cavity, and forming a friction-fitting connection of the organic optoelectronic component with the connecting piece once the connecting structure has been introduced into the first and the second cavity. |
| US09941472B2 |
Piezoelectronic device with novel force amplification
A piezoelectronic device with novel force amplification includes a first electrode; a piezoelectric layer disposed on the first electrode; a second electrode disposed on the piezoelectric layer; an insulator disposed on the second electrode; a piezoresistive layer disposed on the insulator; a third electrode disposed on the insulator; a fourth electrode disposed on the insulator; a semi-rigid housing surrounding the layers and the electrodes; wherein the semi-rigid housing is in contact with the first, third, and fourth electrodes and the piezoresistive layer; wherein the semi-rigid housing includes a void. The third and fourth electrodes are on the same plane and separated from each other in the transverse direction by a distance. |
| US09941469B2 |
Double spin filter tunnel junction
A memory device that includes a first magnetic insulating tunnel barrier reference layer present on a first non-magnetic metal electrode, and a free magnetic metal layer present on the first magnetic insulating tunnel barrier reference layer. A second magnetic insulating tunnel barrier reference layer may be present on the free magnetic metal layer, and a second non-magnetic metal electrode may be present on the second magnetic insulating tunnel barrier. The first and second magnetic insulating tunnel barrier reference layers are arranged so that their magnetizations are aligned to be anti-parallel. |
| US09941468B2 |
Magnetoresistance effect element and magnetic memory device
A magnetoresistance effect element (100) includes a heavy metal layer (11) that includes a heavy metal and that is formed to extend in a first direction, a recording layer (12) that includes a ferromagnetic material and that is provided adjacent to the heavy metal layer (11), a barrier layer (13) that includes an insulating material and that is provided on the recording layer (12) with being adjacent to a surface of the recording layer (12) opposite to the heavy metal layer (11), and a reference layer (14) that includes a ferromagnetic material and that is provided adjacent to a surface of the barrier layer (13), the surface being opposite to the recording layer (12). The direction of the magnetization of the reference layer (14) has a component substantially fixed in the first direction, and the direction of the magnetization of the recording layer (12) has a component variable in the first direction. A current having a direction same as the first direction is introduced to the heavy metal layer (11) to thereby enable the magnetization of the recording layer (12) to be inverted. |
| US09941467B1 |
Method and system for providing a low moment CoFeBMo free layer magnetic junction usable in spin transfer torque applications
A magnetic junction and method for providing the magnetic junction are described. The magnetic junction resides on a substrate and is usable in a magnetic device. The magnetic junction includes free and pinned layers separated by a nonmagnetic spacer layer. The free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. The free layer has a free layer perpendicular magnetic anisotropy energy greater than a free layer out-of-plane demagnetization energy. The free layer includes a [CoxFeyBz]uMot layer, where u+t=1, x+y+z=1 and u, t, x, y and z are each nonzero. The [CoxFeyBz]uMot layer has a perpendicular magnetic anisotropy energy greater than its out-of-plane demagnetization energy. |
| US09941461B2 |
Electronic component element and composite module including the same
An electronic component element includes a piezoelectric substrate and a comb-shaped electrode located on one principal surface of the piezoelectric substrate. A support layer is arranged around the comb-shaped electrode. A cover layer is disposed so as to cover the support layer and the comb-shaped electrode. Via-hole electrodes extend through the cover layer and are connected to the comb-shaped electrode. An uneven portion is located on a principal surface of the cover layer that is opposite to a principal surface of the cover layer that is opposed to the comb-shaped electrode. |
| US09941460B2 |
Electronic device
An electronic device includes a sealing plate including a first surface connected to a pressure chamber formation substrate, and a second surface having a drive IC provided thereon. The sealing plate includes a first region in which a plurality of individual connection terminals are arranged, and a second region in a position different from the first region. A plurality of bump electrodes are arranged at a pitch different from a pitch of an individual connection terminals, in a region overlapping a second region, and a wiring group connecting the individual connection terminal and a bump electrode includes a first wiring of which a position of a pass-through wiring relaying the first surface and the second surface is within the first region. A second wiring of which a position of a pass-through wiring connecting the first surface and the second surface is within the second region. |
| US09941456B2 |
Thermoelectric materials and their manufacturing method
Disclosed is a thermoelectric material with excellent thermoelectric conversion performance. The thermoelectric material includes a matrix having Cu and Se, a Cu-containing particle, and an Ag-containing structure. |
| US09941455B2 |
Light emitting diode and light emitting device including the same
Disclosed herein is a light emitting device. The light emitting device is provided to include a light emitting structure, a first electrode pad, a second electrode pad and a heat dissipation pad, and a substrate on which the light emitting diode is mounted. The substrate includes a base; an insulation pattern formed on the base; and a conductive pattern disposed on the insulation pattern. The base includes a post and a groove separating the post from the conductive pattern. An upper surface of the post is placed lower than an upper surface of the conductive pattern, the heat dissipation pad contacts the upper surface of the post, and the first electrode pad and the second electrode pad contact the conductive pattern. With this structure, the light emitting device has excellent properties in terms of electrical stability and heat dissipation efficiency. |
| US09941454B2 |
Light emitting device on a mount with a reflective layer
Embodiments of the invention include a semiconductor light emitting diode (LED) attached to a top surface of a mount. A multi-layer reflector is disposed on the top surface of the mount adjacent to the LED. The multi-layer reflector includes layer pairs of alternating layers of low index of refraction material and high index of refraction material. A portion of the top surface in direct contact with the multi-layer reflector is non-reflective. |
| US09941452B2 |
Display device
A display device is provided. The display device includes a first substrate, a display unit, a second substrate, and a light shielding structure. The display unit is disposed on the first substrate and includes at least one light emitting diode chip. The light shielding structure surrounds the light emitting diode chip of the display units and is located between the first substrate and the second substrate. |
| US09941449B2 |
Light emitting device
A light emitting device includes: a substrate; an electrode pattern formed on the substrate; a light emitting element connected to the electrode pattern; a ridge-shaped resin covering portion which covers a part of the electrode pattern, and which includes a first and second outer edge portions; first and second through holes formed to penetrate through the electrode pattern such that the substrate is exposed; and first and second hole arrays including the first and second through holes arranged along the first and second outer edge portions, respectively. The first and second outer edge portions cover at least a part of the first and second through holes, respectively, and are bonded to the substrate in the first and second through holes, respectively. |
| US09941447B2 |
Semiconductor light emitting device and method for producing the same
A method for producing a semiconductor light emitting device includes providing a light emitting element that includes a semiconductor layer structure on a side of a lower surface of a substrate. The light emitting element is placed on a supporting member via a connecting member so that the semiconductor layer structure of the light emitting element faces the supporting member. Surfaces of the substrate, and the semiconductor layer structure, and a side of the connecting member with a light reflection layer are coated using atomic layer deposition so as to expose at least a part of at least one of an upper surface and a side surface of the substrate as a light-extracting region after the light emitting element is placed on the supporting member. |
| US09941446B2 |
Light-emitting element with first and second light transmissive electrodes and method of manufacturing the same
A method of manufacturing a light-emitting element includes forming a light-transmissive insulating film on a portion of an upper surface of a semiconductor layered body; forming a first light-transmissive electrode to continuously cover the upper surface of the semiconductor layered body and an upper surface of the light-transmissive insulating film; heat-treating the first light-transmissive electrode, and subsequently forming a metal film in at least a portion of a region above the light-transmissive insulating film; forming a second light-transmissive electrode to continuously cover an upper surface of the metal film and an upper surface of the first light-transmissive electrode, the second light-transmissive electrode being electrically connected to the first light-transmissive electrode; and forming a pad electrode in a region where the metal film is disposed in a top view, such that at least a portion of the pad electrode is in contact with an upper surface of the second light-transmissive electrode. |
| US09941442B2 |
Group 13 element nitride crystal substrate and function element
A crystal substrate is composed of a crystal of a nitride of a group 13 element and has a first main face and a second main face. The crystal substrate includes a low carrier concentration region and a high carrier concentration region both extending between the first main face and second main face. The low carrier concentration region has a carrier concentration of 1018/cm3 or lower and a defect density of 107/cm2 or lower. The high carrier concentration region has a carrier concentration of 1019/cm3 or higher and a defect density of 108/cm2 or higher. |
| US09941439B2 |
Optically assist-triggered wide bandgap thyristors having positive temperature coefficients
A thyristor includes a first conductivity type semiconductor layer, a first conductivity type carrier injection layer on the semiconductor layer, a second conductivity type drift layer on the carrier injection layer, a first conductivity type base layer on the drift layer, and a second conductivity type anode region on the base layer. The thickness and doping concentration of the carrier injection layer are selected to reduce minority carrier injection by the carrier injection layer in response to an increase in operating temperature of the thyristor. A cross-over current density at which the thyristor shifts from a negative temperature coefficient of forward voltage to a positive temperature coefficient of forward voltage is thereby reduced. |
| US09941438B2 |
Neutron detection
A neutron detector includes a microchannel plate having a structure that defines a plurality of microchannels, and layers of materials disposed on walls of the microchannels. The layers include a layer of neutron sensitive material, a layer of semiconducting material, and a layer of electron emissive material. For example, the layer of neutron sensitive material can include at least one of hafnium (Hf), samarium (Sm), erbium (Er), neodymium (Nd), tantalum (Ta), lutetium (Lu), europium (Eu), dysposium (Dy), or thulium (Tm). |
| US09941435B2 |
Photovoltaic module and laminate
A photovoltaic module is disclosed. The photovoltaic module has a first side directed toward the sun during normal operation and a second, lower side. The photovoltaic module comprises a perimeter frame and a photovoltaic laminate at least partially enclosed by and supported by the perimeter frame. The photovoltaic laminate comprises a transparent cover layer positioned toward the first side of the photovoltaic module, an upper encapsulant layer beneath and adhering to the cover layer, a plurality of photovoltaic solar cells beneath the upper encapsulant layer, the photovoltaic solar cells electrically interconnected, a lower encapsulant layer beneath the plurality of photovoltaic solar cells, the upper and lower encapsulant layers enclosing the plurality of photovoltaic solar cells, and a homogenous rear environmental protection layer, the rear environmental protection layer adhering to the lower encapsulant layer, the rear environmental protection layer exposed to the ambient environment on the second side of the photovoltaic module. |
| US09941434B2 |
Photoelectric conversion device, solar cell and method for manufacturing photoelectric conversion device
A photoelectric conversion device of an embodiment has a substrate, a bottom electrode comprising an electrode layer on the substrate and an intermediate interface layer, a light absorbing layer on the intermediate interface layer. The electrode layer comprises Mo or W. The intermediate interface layer is a compound thin film of a compound comprising Mo or W and at least one element X selected from the group consisting of S, Se, and Te. The intermediate interface layer has a crystal phase and an amorphous phase with which the crystal phase is covered. |
| US09941430B2 |
Silicon-based quantum dot device
A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the substrate which is configured to provide at least one quantum dot (51, 52: FIG. 5). The layer of silicon or silicon-germanium has a thickness of no more than ten monolayers. The layer of silicon or silicon-germanium may have a thickness of no more than eight or five monolayers. |
| US09941426B2 |
Methods to introduce sub-micrometer, symmetry-breaking surface corrugation to silicon substrates to increase light trapping
Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces. |
| US09941422B2 |
Organic photoelectric conversion element and solar cell using the same
Provided are a transparent conductive film having a simple manufacturing process and high transparency, high photoelectric conversion efficiency, and excellent durability and an organic photoelectric conversion element using this transparent conductive film.The transparent conductive film of the present invention is formed by laminating a ground layer which contains a nitrogen-containing organic compound and a metal thin film layer which contains a metal element of Group 11 of the periodic table and has a thickness of from 2 to 10 nm. In addition, the organic photoelectric conversion element of the present invention has a first electrode, a second electrode, and a photoelectric conversion layer present between the first electrode and the second electrode, and at least one of the first electrode and the second electrode of the organic photoelectric conversion element is a transparent conductive film formed by laminating the ground layer which contains the nitrogen-containing organic compound and the metal thin film layer which contains a metal element of Group 11 of the periodic table and has a thickness of from 2 to 10 nm. |
| US09941415B2 |
Oxide sintered body, sputtering target, and oxide semiconductor thin film obtained using sputtering target
Provided are: a sintered oxide which achieves low carrier density and high carrier mobility when configured as an oxide semiconductor thin-film by using the sputtering method; and a sputtering target using the same. This sintered oxide contains indium, gallium and magnesium as oxides. It is preferable for the gallium content to be 0.20-0.45, inclusive, in terms of an atomic ratio (Ga/(In+Ga)), the magnesium content to be at least 0.0001 and less than 0.05 in terms of an atomic ratio (Mg/(In+Ga+Mg)), and the sintering to occur at 1,200-1,550° C., inclusive. An amorphous oxide semiconductor thin-film obtained by forming this sintered oxide as a sputtering target is capable of achieving a carrier density of less than 3.0×1018 cm−3, and a carrier mobility of 10 cm2V−1 sec−1 or higher. |
| US09941414B2 |
Metal oxide semiconductor device
In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor is prevented. |
| US09941413B2 |
Semiconductor device having different types of thin film transistors
It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first conductive layer over a substrate, a first insulating layer which covers the first conductive layer, an oxide semiconductor layer over the first insulating layer that overlaps with part of the first conductive layer and has a crystal region in a surface part, second and third conductive layers formed in contact with the oxide semiconductor layer, an insulating layer which covers the oxide semiconductor layer and the second and third conductive layers, and a fourth conductive layer over the insulating layer that overlaps with part of the oxide semiconductor layer. |
| US09941411B2 |
Vertical transistor fabrication and devices
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first bottom surface of the first recess; epitaxially growing a second drain from the second bottom surface of a second recess formed in the substrate; growing a channel material epitaxially on the first drain and the second drain; forming troughs in the channel material to form one or more fin channels on the first drain and one or more fin channels on the second drain, wherein the troughs over the first drain extend to the surface of the first drain, and the troughs over the second drain extend to the surface of the second drain; forming a gate structure on each of the one or more fin channels; and growing sources on each of the fin channels associated with the first and second drains. |
| US09941409B2 |
Method for manufacturing a thin film transistor substrate
A thin film transistor substrate includes a semiconductor channel layer made of an oxide semiconductor, protective insulating layers that cover the semiconductor channel layer, a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode. The second source electrode is located on the first source electrode and connected with the semiconductor channel layer through a first contact hole. The second drain electrode is located on the first drain electrode and connected with the semiconductor channel layer through a second contact hole. |
| US09941404B2 |
Tuning strain in semiconductor devices
A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first silicon germanium oxide layer is over the substrate, wherein the first silicon germanium oxide layer has a first germanium percentage. A second silicon germanium oxide layer is over the first silicon germanium oxide layer. The second silicon germanium oxide layer has a second germanium percentage greater than the first germanium percentage. A gate dielectric is on sidewalls and a top surface of the semiconductor layer. A gate electrode is over the gate dielectric. |
| US09941402B2 |
Semiconductor devices and methods for forming a semiconductor device
A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure includes a first doping region at a front side surface of the substrate and a wiring structure electrically connecting the first doping region to a highly doped portion of a common doping region. The common doping region extends from a backside surface of the substrate to at least a part of the front side surface in contact with the wiring structure. An edge termination doping region laterally surrounds the first and second active areas. The edge termination doping region and the first doping region have a first conductivity type, and the common doping region has a second conductivity type. A resistive connection between the edge termination doping region and the first doping region is present at least during reverse operating conditions of the semiconductor device. |
| US09941396B2 |
Semiconductor device and method of manufacturing same
To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of a semiconductor substrate is comprised of a relatively lightly-doped P+ type first collector region and a relatively heavily-doped P++ type second collector region. The P++ type second collector region includes, in plan view, interfaces between a first trench having therein a first linear trench gate electrode and an N+ type emitter region formed on the side surface of the first trench and between a second trench having therein a second linear trench gate electrode and an N+ type emitter region formed on the side surface of the second trench. This enables electrons injected from the surface side of the semiconductor substrate to reach the P++ type second collector region and offset, with them, holes injected from the back surface side of the semiconductor substrate. |
| US09941393B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode. |
| US09941391B2 |
Method of forming vertical transistor having dual bottom spacers
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the substrate to define gaps between the first spacer and the fin structure and depositing a second spacer on the exposed surfaces of the substrate in at least the gaps. |
| US09941386B2 |
Semiconductor device structure with fin structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin structure and a second fin structure over the substrate. There is a gap between the first fin structure and the second fin structure. The semiconductor device structure includes an isolation structure having a thin portion and a thick portion. A first upper portion of the first fin structure and a second upper portion of the second fin structure protrude from the thin portion. The thick portion is partially between the first upper portion and the second upper portion. The semiconductor device structure includes a dummy gate electrode over the thick portion, the first upper portion, and the second upper portion. The semiconductor device structure includes a gate electrode over the first fin structure and the thin portion. |
| US09941385B2 |
Finfet with reduced capacitance
A structure including a gate electrode above and perpendicular to a plurality of semiconductor fins, a pair of spacers disposed on opposing sides of the gate electrode, and a gap fill material above a semiconductor substrate, directly below the gate electrode, and between the plurality of fins, the gate electrode separates the gap fill material from each of the plurality of fins. |
| US09941383B2 |
Fast switching IGBT with embedded emitter shorting contacts and method for making same
Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or grown epitaxial silicon for controlled drift region thickness and fast switching speed. |
| US09941380B2 |
Graphene transistor and related methods
A method and structure for providing high-quality transferred graphene layers for subsequent device fabrication includes transferring graphene onto a hydrophobic surface of a hydrophobic layer and performing a thermal treatment process. In various embodiments, a substrate including an insulating layer is provided, and a hydrophobic layer is formed over the insulating layer. In some examples, a graphene layer is transferred onto the hydrophobic layer. By way of example, the transferred graphene layer has a first carrier mobility. In some embodiments, after transferring the graphene layer, an annealing process is performed, and the annealed graphene layer has a second carrier mobility greater than the first carrier mobility. |
| US09941378B2 |
Air-gap top spacer and self-aligned metal gate for vertical FETs
Methods for forming a transistor include forming a gate conductor in contact with a gate stack. The gate conductor has a top surface that meets a middle point of sidewalls of a sacrificial region of a fin. The sacrificial region of the fin is trimmed to create gaps above the gate stack. A top spacer is formed on the gate conductor. The top spacer includes airgaps above the gate stack. |
| US09941371B2 |
Selective thickening of pFET dielectric
A complementary metal-oxide semiconductor (CMOS) device and a method of fabricating a CMOS device are described. The method includes forming an interfacial layer in a trench on a substrate in both a p-channel field effect transistor (pFET) area of the CMOS device and an n-channel FET (nFET) area of the CMOS device, depositing a high-k dielectric on the interfacial layer in both the pFET area and the nFET area, selectively forming a first metal layer on the high-k dielectric in only the pFET area, and depositing a second metal layer on the first metal layer in the pFET area and on the high-k dielectric in the nFET area. The method also includes performing an anneal that increases a thickness of the interfacial layer in only the pFET area. |
| US09941369B2 |
Memory cell comprising non-self-aligned horizontal and vertical control gates
The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection. |
| US09941362B2 |
Method of manufacturing silicon carbide semiconductor device
A method of manufacturing a silicon carbide semiconductor device. The method includes providing an n-type semiconductor substrate having first and second principal surfaces, introducing an impurity from a first principal surface of the semiconductor substrate at a first position, activating the impurity to form a diffusion layer in the semiconductor substrate at a second position, implanting protons at a third position that is deeper from the first principal surface than the first position, the protons generating crystal defects in a region through which the protons pass, converting by thermal treating the protons into hydrogen induced donors to form an n-type field stop layer at a fourth position deeper from the first principal surface than the second position, reducing by the thermal treating the generated crystal defects to form an n-type crystal defect reduction region, and forming an electrode on the second principal surface after implanting the protons. |
| US09941361B2 |
Method for fabricating semiconductor substrate, semiconductor substrate, and semiconductor device
In a method for fabricating a semiconductor substrate according to an embodiment, an SiC substrate is formed by vapor growth and C (carbon) is introduced into the surface of the SiC substrate to form an n-type SiC layer on the SiC substrate by an epitaxial growth method. |
| US09941359B2 |
Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice. |
| US09941358B2 |
Semiconductor integrated circuit with guard ring
A semiconductor integrated circuit includes a first conduction-type semiconductor region, a second conduction-type first impurity region, and a guard ring formed using a first conduction-type second impurity region so as to form a protection device of an electrostatic protection circuit. The first impurity region is formed inside the semiconductor region to have a rectangular planar structure with long and short sides. The guard ring is formed inside the semiconductor region to surround the periphery of the first impurity region. A weak spot is formed on the short side of the rectangular planar structure of the first impurity region. A plurality of electrical contacts are formed in a first portion of the guard ring which faces the long side of the rectangle. A plurality of electrical contracts are not formed in a second portion of the guard ring which faces the weak spot formed on the short side of the rectangle. |
| US09941355B1 |
Co-integration of elastic and plastic relaxation on the same wafer
An n-doped field effect transistor (nFET) section of an integrated device logic region is provided. The nFET section includes a semiconductor substrate, a layer at least partially formed of silicon germanium (SiGe) disposed on the semiconductor substrate and fin formations. The fin formations are formed on the layer. Each fin formation includes a first fin portion that is at least partially formed of silicon (Si) and a second fin portion that is at least partially formed of hard mask material. The layer is etched to include free surfaces that facilitate elastic relaxation of SiGe therein and a corresponding application of tension in Si of the first fin portion of each of the fin formations. |
| US09941353B2 |
Structure and method for mitigating substrate parasitics in bulk high resistivity substrate technology
A structure includes a field isolation region in a high resistivity substrate, a compensation implant region under the field isolation region in the high resistivity substrate, where the compensation implant region is configured to substantially eliminate a parasitic p-n junction under the field isolation region. The parasitic p-n junction is formed between trapped charges in the field isolation region and the high resistivity substrate. The compensation implant region includes a charge of a first conductivity type to compensate a parasitic charge of a second conductivity type under the field isolation region. The compensation implant region is configured to improve linearity of RF signals propagating through a metallization layer over the field isolation region. The structure further includes a deep trench extending through the field isolation region and the compensation implant region, and a damaged region adjacent the deep trench. |
| US09941352B1 |
Transistor with improved air spacer
A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a gate stack disposed on a substrate. A gate contact is disposed in contact with an end portion of the gate stack. An air gap spacer is disposed in contact with a portion of the gate stack. The end portion of the gate stack is absent the air gap spacer. The method includes forming a gate contact in contact with a gate stack. A spacer surrounding at least a portion of the gate stack is removed after the gate contact has been formed. The removal of the spacer forms a trench surrounding the gate stack and stopping at the gate contact. An air gap spacer is formed within the trench. |
| US09941351B2 |
Vertical power transistor with deep trenches and deep regions surrounding cell array
Various improvements in vertical transistors, such as IGBTs, are disclosed. The improvements include forming periodic highly-doped p-type emitter dots in the top surface region of a growth substrate, followed by growing the various transistor layers, followed by grounding down the bottom surface of the substrate, followed by a wet etch of the bottom surface to expose the heavily doped p+ layer. A metal contact is then formed over the p+ layer. In another improvement, edge termination structures utilize p-dopants implanted in trenches to create deep p-regions for shaping the electric field, and shallow p-regions between the trenches for rapidly removing holes after turn-off. In another improvement, a dual buffer layer using an n-layer and distributed n+ regions improves breakdown voltage and saturation voltage. In another improvement, p-zones of different concentrations in a termination structure are formed by varying pitches of trenches. In another improvement, beveled saw streets increase breakdown voltage. |
| US09941340B2 |
Organic light-emitting diode display including a shielding electrode with reduced crosstalk
An organic light-emitting diode display is disclosed. The display includes a scan line formed over a substrate and configured to carry a scan signal. First and second data lines are adjacent to each other and crossing the scan line. The first and second data lines are configured carry a data voltage. A driving voltage line crossing the scan line is configured to carry a driving voltage, and a switching transistor is electrically connected to the scan line and the data line and includes a switching drain electrode configured to output the data voltage. A driving transistor includes a driving gate electrode and a driving source electrode electrically connected to the switching drain electrode. An OLED is electrically connected to the driving drain electrode of the driving transistor, and a connector is connected to the driving gate electrode of the driving transistor and interposed between the first and second data lines. |
| US09941339B2 |
Organic light-emitting diode (OLED) display
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a plurality of pixels, each including a driving thin film transistor (TFT) formed over a substrate and including a driving gate electrode, a first storage capacitor comprising a first electrode and a second electrode, and a second storage capacitor comprising a third electrode and a fourth electrode. The first electrode is electrically connected to the driving gate electrode and the second electrode is formed over the first electrode and electrically insulated from the first electrode. The third electrode is electrically connected to the first electrode, is formed on a different layer from each of the first and second electrodes, and does not overlap the second electrode. The fourth electrode is formed over the third electrode and electrically insulated from the third electrode. |
| US09941336B2 |
Light emitting display device and method for fabricating the same
The light emitting display device comprises: a substrate including a plurality of pixels that are arranged in a first direction and a second direction that crosses the first direction; a first electrode for each pixel on the substrate; a pixel defining layer on the substrate, the pixel defining layer having an opening for exposing the first electrode; a hole injection layer on the first electrode; a lyophilic pattern extending on the hole injection layer to cover the first electrode and the pixel defining layer that are on a same line in the first direction, and extending up to an outer region of outermost pixels of the plurality of pixels in the first direction; a hole transport layer on the lyophilic pattern; a light emitting layer on the hole transport layer; and a second electrode on the light emitting layer, wherein the lyophilic pattern includes a first lyophilic pattern having a plurality of grooves on one end portion thereof in the first direction and a second lyophilic pattern having a plurality of grooves on another end portion thereof in the first direction, and wherein the first lyophilic pattern and the second lyophilic pattern are alternately arranged in the second direction. |
| US09941329B2 |
Light emitting diodes (LEDs) with integrated CMOS circuits
Disclosed is a multi-color semiconductor LED display with integrated with CMOS circuit components, such as thin film transistors (TFTs). LEDs of the display are disposed on a first major surface of a substrate while CMOS circuit components which are configured as circuitry for operating the display are disposed on a second opposing major surface of the substrate. The CMOS components and LEDs are coupled by through silicon via (TSV) contacts through the substrate. Integrating CMOS components with LED on one substrate enhances compactness of the display. Other advantages include low power and low cost with high brightness and resolution desired for portable applications, including virtual reality and augmented reality applications. |
| US09941327B2 |
Detector module for an imaging system
A detector module for detecting photons includes a detector formed from a semiconductive material, the detector having a first surface, an opposing second surface, and a plurality of sidewalls extending between the first and second surfaces, and a guard band coupled to the sidewalls, the guard band having a length that extends about a circumference of the detector, the guard band having a width that is greater than a thickness of the detector such that an upper rim segment of the guard band projects beyond the first surface of the detector, the upper rim segment being folded over a peripheral region of the first surface along the circumference of the detector, the guard band configured to reduce recombinations proximate to the edges of the detector. |
| US09941321B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate. |
| US09941313B2 |
Method of manufacturing thin film transistor substrate
A method of manufacturing a thin film transistor substrate includes forming a semiconductor pattern on a substrate, wherein the semiconductor pattern includes a first area, a second area, and a third area, wherein the second area and the third area are located on each side of the first area; forming an insulating layer on the substrate to cover the semiconductor pattern; forming a metal pattern layer on the insulating layer using a first photosensitive pattern; doping the semiconductor pattern with first impurities using the first photosensitive pattern; forming a gate electrode by patterning the metal pattern layer using a second photosensitive pattern; and doping the semiconductor pattern with second impurities having a lower concentration than the first impurities. |
| US09941311B2 |
Flexible display device and manufacturing method thereof
Disclosed herein is a flexible display device, including: a substrate that comprises a first surface and a second surface which is an opposite surface to the first surface; a light-emitting device disposed on the first surface; a reduction layer disposed on the second surface; and a barrier layer disposed between the second surface and the reduction layer. |
| US09941309B2 |
Semiconductor device
To provide a semiconductor device including a capacitor whose charge capacity is increased without reducing the aperture ratio. The semiconductor device includes a transistor including a light-transmitting semiconductor film, a capacitor where a dielectric film is provided between a pair of electrodes, an insulating film provided over the light-transmitting semiconductor film, and a light-transmitting conductive film provided over the insulating film. In the capacitor, a metal oxide film containing at least indium (In) or zinc (Zn) and formed on the same surface as the light-transmitting semiconductor film in the transistor serves as one electrode, the light-transmitting conductive film serves as the other electrode, and the insulating film provided over the light-transmitting semiconductor film serves as the dielectric film. |
| US09941308B2 |
Display device and electronic device including the same
It is an object to decrease the number of transistors connected to a capacitor. In a structure, a capacitor and one transistor are included, one electrode of the capacitor is connected to a wiring, and the other electrode of the capacitor is connected to a gate of the transistor. Since a clock signal is input to the wiring, the clock signal is input to the gate of the transistor through the capacitor. Then, on/off of the transistor is controlled by a signal which synchronizes with the clock signal, so that a period when the transistor is on and a period when the transistor is off are repeated. In this manner, deterioration of the transistor can be suppressed. |
| US09941304B2 |
Memory device, semiconductor device, and electronic device
A memory device does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped. |
| US09941303B1 |
Array substrate, display panel and display device
The present application provides an array substrate, a display panel and a display device. The array substrate includes: a substrate; gate lines and data lines located on the substrate, intersecting and insulated from each other, which define a plurality of sub-pixel areas; the sub-pixel areas each comprises: a thin-film transistor; a pixel electrode, a barrier metal electrode. An orthographic projection of the drain electrode on the substrate is located between orthographic projections of two adjacent data lines on the substrate, an orthographic projection of the barrier metal electrode on the substrate is located between the orthographic projection of the drain electrode on the substrate and the orthographic projection of at least one of the two adjacent data lines on the substrate. |
| US09941301B1 |
Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions
Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers. |
| US09941297B2 |
Vertical resistor in 3D memory device with two-tier stack
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack. |
| US09941294B2 |
Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a first gate stack over the semiconductor substrate. The first gate stack includes a first gate and a second gate over the first gate, and the first gate and the second gate are electrically isolated from each other. The semiconductor device structure includes a ring structure surrounding the first gate stack. The ring structure is made of a conductive material. |
| US09941292B2 |
Semiconductor memory device and method for manufacturing same
A semiconductor memory device includes a plurality of first electrode layers stacked in a first direction; a semiconductor layer extending in the first direction in the plurality of first electrode layers; a first insulating layer extending in the first direction along the semiconductor layer between the semiconductor layer and each of the plurality of first electrode layers; a second insulating layer covering the periphery of the plurality of first electrode layers; a resistive body provided on the second insulating layer; and a third insulating layer provided between the resistive body and the second insulating layer, the third insulating layer including the same material as the material of the first insulating layer. |
| US09941291B2 |
Three-dimensional non-volatile memory device
A semiconductor device includes at least one first conductive layer stacked on a substrate where a cell region and a contact region are defined; at least one first slit passing through the first conductive layer, second conductive layers stacked on the first conductive layer; a second slit passing through the first and second conductive layers and connected with one side of the first slit, and a third slit passing through the first and second conductive layers and connected with the other side of the first slit. |
| US09941287B2 |
Three-dimensional static random access memory device structures
Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell. |
| US09941283B2 |
Semiconductor device having fin-type pattern
A semiconductor device is provided. The semiconductor device includes a first fin-type pattern on a substrate, a first interlayer insulating layer on the substrate, covering the first fin-type pattern and including a first trench, the first trench intersecting the first fin-type pattern, a first gate electrode on the first fin-type pattern, filling the first trench, an upper surface of the first gate electrode being coplanar with an upper surface of the first interlayer insulating layer, a capping layer extending along the upper surface of the first interlayer insulating layer and along the upper surface of the first gate electrode, and a second interlayer insulating layer on the capping layer, the second interlayer insulating layer including a material different from that of the capping layer. |
| US09941281B2 |
Semiconductor device
A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height. |
| US09941280B2 |
Semiconductor device using three dimensional channel
According to example embodiments, a semiconductor device includes a first fin, a second fin that is separated from the first fin, and a gate on the first fin and the second fin. The gate crosses the first fin and the second fin. The first fin includes a first doped area at both sides of the gate. The first doped area is configured to have a first voltage applied thereto. The second fin includes a second doped area at both sides of the gate. The second doped area is configured to have a second voltage applied thereto. The second voltage is different than the first voltage. |
| US09941278B2 |
Method and apparatus for placing a gate contact inside an active region of a semiconductor
A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact. |
| US09941277B2 |
Semiconductor devices including increased area contacts
A semiconductor device can include a plurality of active patterns protruding from a substrate and spaced apart on the substrate by first and second distances. A plurality of selective epitaxial growth portions can be each grown on an upper surface of a respective one of the plurality of active patterns. A source/drain contact can be extending across the plurality of selective epitaxial growth portions to remain above top surfaces of first ones of plurality of active patterns that are spaced apart by the first distance between the first ones of plurality of active patterns and can include an extension that extends toward the substrate to below top surfaces of two of the plurality of active patterns that are spaced apart by the second distance between the two of the plurality of active patterns. |
| US09941276B2 |
Method of producing a semiconductor component arrangement comprising a trench transistor
A semiconductor component arrangement method includes producing a trench transistor structure including at least one trench disposed in the semiconductor body and at least one gate electrode disposed in the at least one trench. The method also includes producing a capacitor structure comprising an electrode structure disposed in at least one further trench, the electrode structure comprising at least one electrode. The gate electrode and the at least one electrode of the electrode structure are produced by common process steps. |
| US09941275B2 |
3D semiconductor device and structure
An Integrated Circuit device, including: a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single crystal transistors, where the second layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of the first transistors that cross the first dice lane, where a plurality of the second transistors are circumscribed by a second dice lane of at least 10 microns width, and there are no second conductive connections to the plurality of the second transistors that cross the second dice lane, and at least one thermal conducting path from at least one of the second single crystal transistors to an external surface of the device. |
| US09941274B2 |
Semiconductor device with a switchable and a non-switchable diode region
A semiconductor device includes at least one IGBT cell region, at least one switchable free-wheeling diode region, and at least one non-switchable free-wheeling diode region integrated in the same semiconductor substrate as the at least one IGBT cell region and the at least one switchable free-wheeling diode region. |
| US09941270B2 |
Semiconductor device and design method of same
A semiconductor device includes a semiconductor substrate having a predetermined region in which a standard cell is disposed, and also includes: a first circuit connected to a first ground power line; a second circuit that is connected to a second ground power line and formed from the standard cells; and a protection circuit interposed and connected between the first circuit and the second circuit. The protection circuit includes: a resistor connected in series between the first circuit and the second circuit; and a protector that is interposed and connected between a node of the resistor on the second circuit side and the second ground power line and clamps a potential difference between the node and the second ground power line to a predetermined voltage or lower. The protection circuit is formed in a protection cell disposed in the predetermined region. |
| US09941266B2 |
Semiconductor device
A semiconductor device according to the present invention includes: a substrate; a plurality of trenches formed in the substrate; and a plurality of functional element forming regions arrayed along each of the trenches, including a channel forming region as a current path, wherein the plurality of functional element forming regions includes a first functional element forming region in which the area of the channel forming region per unit area is relatively small and a second functional element forming region in which the area of the channel forming region per unit area is relatively large, and the first functional element forming region is provided at a region where heat generation should be suppressed. |
| US09941264B2 |
Transient overvoltage protection device
In one embodiment, an overvoltage protection device may include a semiconductor substrate comprising an n-type body region. The overvoltage protection device may further include a first p-type region disposed in a first surface region of the semiconductor substrate, and forming a first P/N junction with the n-type body region, and a second p-type region disposed in a second surface region of the semiconductor substrate opposite the first surface, and forming a second P/N junction with the n-type body region, wherein the n-type body region, first p-type region, and second p-type region form a breakdown device having a breakdown voltage greater than 100 V when an external voltage is applied between the first surface region and second surface region. |
| US09941262B2 |
Laser lift-off on isolated III-nitride light islands for inter-substrate LED transfer
A laser liftoff process is provided. A device layer can be provided on a transfer substrate. Channels can be formed through the device layer such that devices comprising remaining portions of the device layer are laterally isolated from one another by the channels. The transfer substrate can be bonded to a target substrate through an adhesion layer. Surface portions of the devices can be removed from an interface region between the transfer substrate and the devices by irradiating a laser beam through the transfer substrate onto the devices. The laser irradiation decomposes the III-V compound semiconductor material. The channels provide escape paths for the gaseous products (such as nitrogen gas) that are generated by the laser irradiation. The transfer substrate is separated from a bonded assembly including the target substrate and remaining portions of the devices. The devices can include a III-V compound semiconductor material. |
| US09941261B2 |
Display device
A display device is disclosed, which comprises: a first substrate; a second substrate disposed adjacent to the first substrate and partially covering the first substrate, wherein the second substrate comprises a second arc edge and a second side, and the second arc edge connects to the second side; a driving unit disposed on a part of the first substrate uncovered with the second substrate; and a compensation panel disposed on the driving unit and comprising a third arc edge and a third side, wherein the third arc edge connects to the third side, wherein the third side corresponds to the second side, and the third arc edge corresponds to the second arc edge. |
| US09941260B2 |
Fan-out package structure having embedded package substrate
A semiconductor package structure is provided. The semiconductor package structure includes a first semiconductor package that includes a first semiconductor die having a first surface and a second surface opposite thereto. A first package substrate is disposed on the first surface of the first semiconductor die. A first molding compound surrounds the first semiconductor die and the first package substrate. A first redistribution layer (RDL) structure is disposed on the first molding compound, in which the first package substrate is interposed and electrically coupled between the first semiconductor die and the first RDL structure. |
| US09941259B2 |
LED module and method for fabricating the same
Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips. |
| US09941254B2 |
Semiconductor device
A semiconductor device 10 includes: multi-layered substrates 12 each having a circuit board 12c; control terminals 14 whose one end is fixed on the circuit board 12c of each multi-layered substrate 12; a resin case 15 which has openings 20 and is arranged to cover the multi-layered substrates 12, through which openings 20 the other ends of the control terminals 14 extend outwardly; and resin blocks 18 which are each inserted into the openings 20 of the resin case 15 and press-fixes the control terminals 14 against the side walls of the respective openings 20. The control terminals 14 each have a low-rigidity portion 14j at a position that is further interior of the resin case 15 than a position where each control terminal 14 is in contact with the resin block 18 in the respective openings 20 of the resin case 15. |
| US09941253B1 |
Semiconductor packages including interconnectors and methods of fabricating the same
A semiconductor package and or method of fabricating a semiconductor package may be provided. The semiconductor package may include a package substrate. The semiconductor package may include a first semiconductor die coupled to the package substrate by first interconnectors. The semiconductor package may include a second semiconductor die coupled to the first semiconductor die by second interconnectors. The second semiconductor die may be coupled to the substrate. |
| US09941251B2 |
3DIC packages with heat dissipation structures
A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first portion overlapped by the first die, and a second portion extending laterally beyond a respective edge of the first die. The package further includes a first Thermal Interface Material (TIM) over and contacting a top surface of the first die, a heat dissipating lid having a first bottom surface contacting the first TIM, a second TIM over and contacting the second portion of the second die, and a heat dissipating ring having a portion over and contacting the second TIM. The heat dissipating lid and the heat dissipating ring are discrete components, and at least one of the heat dissipating lid or the heat dissipating ring has a plurality of fins and a plurality of recesses separating the plurality of fins from each other. |
| US09941248B2 |
Package structures, pop devices and methods of forming the same
Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a plurality of UBM pads, a plurality of connectors and a separator. The redistribution layer structure is electrically connected to the first chip. The UBM pads are electrically connected to the redistribution layer structure. The connectors are electrically connected to the UBM pads. The separator is over the redistribution layer structure and surrounds the connectors. |
| US09941247B2 |
Stack semiconductor device and memory device with driving circuits connected to through-silicon-vias (TSV) in different substrates in a staggered manner
A memory device including a stack semiconductor device including; an upper substrate vertically stacked on a lower substrate, the upper substrate including N upper through-silicon vias (UTSV) and upper driving circuits, and the lower substrate including N lower through-silicon vias (LTSV) and lower driving circuits, wherein each one of the upper driving circuits is stagger-connected between a Kth UTSV and a (K+1)th LTSV, where ‘N’ is a natural number greater than 1, and ‘K’ is a natural number ranging from 1 to (N−1). |
| US09941243B2 |
Wafer-to-wafer bonding structure
A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other. |
| US09941238B2 |
Wiring with external terminal
Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a connection wiring of a ring-shape having comprising a hole and a conductive layer surrounding the hole, the conductive layer including a first connection point and a second connection point that are located so that a straight line between the first connection point and the second connection point crosses over the hole; an external terminal coupled to the first connection point of the conductive layer of the connection wiring; and an internal circuit coupled to the second connection point of the conductive layer of the connection wiring. |
| US09941237B2 |
Semiconductor device and method for making semiconductor device
A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a semiconductor element mounted on the main surface of the substrate and having at least one element pad; a wire having a bonding portion bonded to the element pad; and a sealing resin formed on the main surface of the substrate for covering the wire and at least a portion of the semiconductor element. The semiconductor element has an element exposed side surface that faces in a direction crossing the thickness direction of the substrate and is exposed from the sealing resin. |
| US09941232B2 |
Electronic component device
An electronic component device includes: a lower wiring substrate; an electronic component on the lower wiring substrate; an upper wiring substrate disposed above the lower wiring substrate and the electronic component; a bump conductor disposed between the lower wiring substrate and the upper wiring substrate to electrically connect the lower wiring substrate and the upper wiring substrate; and a sealing resin provided between the lower wiring substrate and the upper wiring substrate to seal the electronic component and the bump conductor. The upper wiring substrate includes: a first wiring layer directly connected to the bump conductor; and a first insulating layer having an opening portion through which the first wiring layer is exposed and disposed to cover the first wiring layer. The first wiring layer and the first insulating layer are not opposed to the electronic component in a thickness direction of the electronic component device. |
| US09941229B2 |
Device including semiconductor chips and method for producing such device
A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip. |
| US09941222B2 |
Integrated circuit with sensor and method of manufacturing such an integrated circuit
Disclosed is an integrated circuit comprising a substrate carrying a plurality of circuit elements; a metallization stack interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion; a passivation stack covering the metallization stack; and a sensor including a sensing material on the passivation stack, said sensor being coupled to the first metal portion by a via extending through the passivation stack. A method of manufacturing such an IC is also disclosed. |
| US09941221B2 |
Warpage control in package-on-package structures
A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate. |
| US09941220B2 |
Integrated circuit
An integrated circuit includes a scribe line, a bonding pad structure and an extension pad structure. The scribe line is disposed on a substrate, and the bonding pad structure and the extension pad structure are both disposed in a dielectric layer on the substrate. The bonding pad structure includes first vias disposed on first metal layers in the dielectric layer. The extension pad structure includes second metal layers and a number of the second metal layer is less than that of the first metal layers. Also, the bonding pad structure has a first region and a second region, and second vias is disposed on the second metal layers in the first region and no vias is disposed on the second metal layers in the second region. |
| US09941219B2 |
Control of warpage using ABF GC cavity for embedded die package
Embodiments include semiconductor device packages and methods of forming such packages. In an embodiment, the package may include a die-side reinforcement layer with a cavity formed through the die-side reinforcement layer. A die having a first side and an opposite second side comprising a device side may be positioned in the cavity with the first side of the die being substantially coplanar with a first side of the die-side reinforcement layer. In an embodiment, a build-up structure may be coupled to a second side of the die. Embodiments include a build-up structure that includes a plurality of alternating layers of patterned conductive material and insulating material. |
| US09941218B2 |
Display apparatus capable of easily acquiring identification about a display panel and a driving chip
A display apparatus is provided including a display panel displaying an image, and a driving chip including a front surface and a rear surface provided with a first marking code, the driving chip being electrically connected with the display panel. The display panel includes an upper substrate, and a lower substrate located facing the upper substrate to include a second marking code, and including a first surface and a second surface facing the first surface. The driving chip is located on the second surface such that a rear surface thereof is closer to the second surface than to the front surface thereof, and wherein the second marking code is provided on the second surface. |
| US09941217B2 |
Mark, method for forming same, and exposure apparatus
A mark forming method includes: forming recessed portion on a mark formation area of a substrate; coating the recessed portion with a polymer layer containing a block copolymer; allowing the polymer layer in the recessed portion to form a self-assembled area; selectively removing a portion of the self-assembled area; and forming a positioning mark by using the self-assembled area from which the portion thereof has been removed. |
| US09941214B2 |
Semiconductor devices, methods of manufacture thereof, and inter-metal dielectric (IMD) structures
Semiconductor devices, methods of manufacture thereof, and IMD structures are disclosed. In some embodiments, a semiconductor device includes an adhesion layer disposed over a workpiece. The adhesion layer has a dielectric constant of about 4.0 or less and includes a substantially homogeneous material. An insulating material layer is disposed over the adhesion layer. The insulating material layer has a dielectric constant of about 2.6 or less. The adhesion layer and the insulating material layer comprise an IMD structure. |
| US09941212B2 |
Nitridized ruthenium layer for formation of cobalt interconnects
An advanced metal conductor structure and a method for constructing the structure are described. A pattern is provided in a dielectric layer. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer disposed over the adhesion promoting layer is deposited. A nitridation process is performed on the ruthenium layer to produce a nitridized ruthenium layer. Using a physical vapor deposition process, a cobalt layer is deposited disposed over the nitridized ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures. In another aspect of the invention, an integrated circuit device is formed using the method. |
| US09941209B2 |
Conductive structures, systems and devices including conductive structures and related methods
Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures. |
| US09941203B2 |
Method of making electrical antifuse
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer. |
| US09941197B2 |
Strip-shaped substrate for producing chip carriers, electronic module with a chip carrier of this type, electronic device with a module of this type, and method for producing a substrate
A strip-shaped substrate made from a film includes a plurality of units for producing chip carriers. Each unit has a chip island for fixing a semiconductor chip, electrodes for electrical connection of the semiconductor chip, and through-openings for structuring the unit. At least one through-opening forms an anchoring edge for a casting compound for encapsulating the semiconductor chip. A surface section of the film abutting the through-opening is chamfered to form the anchoring edge. The anchoring edge protrudes past the side of the film on which the chip island is arranged. |
| US09941190B2 |
Semiconductor device having through-silicon-via and methods of forming the same
Semiconductor devices having a through-silicon-via and methods of forming the same are described herein. As an example, a semiconductor device may include a substrate material, a through-silicon-via protrusion extending from the substrate material, a first dielectric material formed on the substrate material, a second dielectric material formed on the first dielectric material, and an interconnect formed on the through-silicon-via protrusion, where the interconnect formed is in an opening in the second dielectric material. |
| US09941183B2 |
Wall mountable connector with wall covering plate
A wall mountable connector assembly with an optional wall covering plate is disclosed. The wall mountable connector provides electrical connections to each of a plurality of field wires and is configured to provide electrical connections to a thermostat secured to the wall mountable connector. The optional wall covering plate is configured to fit over the wall mountable connector and provide a pleasing appearance. |
| US09941179B2 |
Capacitive measurements of divots in semiconductor devices
Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region. |
| US09941176B2 |
Selective solder bump formation on wafer
A method for selective bump formation on a wafer includes performing a wafer test on the wafer. Known good dies (KGDs) on the wafer are identified based on the wafer test performed. Solder bumps are formed on the KGDs. |
| US09941174B2 |
Semiconductor devices having fin active regions
Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate patterns on the first fin active region, and a first epitaxial region in the first fin active region between the first gate patterns. Sidewalls of the first epitaxial region have first inflection points so that an upper width of the first epitaxial region is greater than a lower width of the first epitaxial region. |
| US09941172B2 |
Method for fabricating semiconductor device including a via hole in a mask pattern
A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming an interlayer insulating layer that comprises a first region and a second region, forming an etch stop pattern for exposing the second region in the first region of the interlayer insulating layer and forming a mask pattern that comprises a first via-hole that exposes an upper surface of the etch stop pattern and a second via-hole that penetrates the interlayer insulating layer on the interlayer insulating layer and the etch stop pattern. |
| US09941171B1 |
Method for fabricating LDMOS with reduced source region
A method for fabricating a semiconductor device including: forming a block layer above a well region of a first doping type in a semiconductor substrate, wherein the block layer has an opening for defining a first region in an upper part of the well region and has sidewalls at sides of the opening; implanting dopants of a second doping type into the well region through the opening of the block layer to form the first region; implanting dopants of the first doping type into the first region in the manner of large-angle-tilt dopants implantation to form a second region for a first transistor, and to form a third region for a second transistor; and forming, for both of the first transistor and the second transistor, a fourth region between the second region and the third region. |
| US09941169B2 |
Organic light emitting diode display device and method of fabricating the same
An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on the first semiconductor layer. The device further includes a storage capacitor including a first capacitor electrode electrically coupled to a drain electrode of the driving thin film transistor, a buffer layer formed on the first capacitor electrode, a second semiconductor layer formed on the buffer layer, and a second capacitor electrode formed on the second semiconductor layer and electrically coupled to a gate electrode of the driving thin film transistor. The device also includes an organic light emitting diode connected to the drain electrode of the driving transistor. The gate insulating layer has at least one hole in a region where the gate insulating layer overlaps the second semiconductor layer, thereby exposing the second semiconductor layer to the second capacitor electrode. |
| US09941168B1 |
Method for manufacturing semiconductor device by epitaxial lift-off using plane dependency of III-V compound
A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate, forming a device layer on the sacrificial layer, patterning the sacrificial layer and the device layer into a shape having an extending portion along a first direction determined based on a surface orientation of the III-V compound of the sacrificial layer, bonding the patterned device layer onto a second substrate, and etching the sacrificial layer by using an etching solution in a state where the device layer is bonded onto the second substrate, to remove the sacrificial layer and the first substrate. Using the method for manufacturing a semiconductor device, it is possible to improve a process yield and increase a process speed by using the difference in etch rates depending on crystal orientation, which is an inherent characteristic of an III-V compound, during an ELO process. |
| US09941160B2 |
Integrated circuits having device contacts and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a conductive plug that at least partially fills a contact seam void. The contact seam void is formed in a contact that extends through an ILD layer of dielectric material overlying a device region. A metallization layer is deposited overlying the contact. |
| US09941156B2 |
Systems and methods to reduce parasitic capacitance
Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive structures and an etch stop layer proximate to the dielectric layer. The etch stop layer may define first and second openings proximate to a region of the dielectric layer between the first and second conductive structures. The device may include first and second airgaps within the region. The device may include a layer of material proximate to (e.g., on, above, or over) the etch stop layer. The layer of material proximate to the etch stop layer may cover the first and second airgaps. |
| US09941154B2 |
Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a semiconductor device. A top portion of the mandrel is exposed prior to formation of the second hardmask layer. The method further includes removing the first sidewall structure to expose a first portion of a first hardmask layer. The method also includes etching the first portion of the first hardmask layer to expose a second portion of a dielectric material. The method also includes etching the second portion of the dielectric material to form a first trench. The method also includes forming a first metal structure within the first trench. |
| US09941153B1 |
Pad structure and manufacturing method thereof
A pad structure including a plurality of material pairs and a plurality of pads is provided. The material pairs are stacked on a substrate to form a stair step structure. A stair step of the stair step structure includes one of material pairs. Each of the material pairs includes a conductive layer and a dielectric layer on the conductive layer. Each of the pads is embedded in one stair step of the stair step structure and exposed by the dielectric layer corresponding to the one stair step and another stair step above the one stair step. A thickness of one of the pads is greater than a thickness of one of the conductive layers. |
| US09941152B2 |
Mechanism for forming metal gate structure
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack formed over the semiconductor substrate. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the metal gate stack includes a metal gate electrode. The semiconductor device further includes a metal oxide structure formed over the insulating layer and in direct contact with the insulating layer. The metal oxide structure includes an oxidized material of the metal gate electrode. |
| US09941149B2 |
Receptacle device, device and method for handling substrate stacks
The invention relates to a retaining system for handling substrate stacks, including a retaining surface for retaining a first substrate, and one or more recesses provided relative to the retaining surface, for retaining first magnetic bodies for securing the first substrate relative to a second substrate that is aligned with the first substrate. Second magnetic bodies are applied on a holding side of the second substrate. |
| US09941148B2 |
Wafer pin chuck fabrication and repair
In a wafer chuck design featuring pins or “mesas” making up the support surface, engineering the pins to have an annular shape, or to contain holes or pits, minimizes sticking of the wafer, and improves wafer settling. In another aspect of the invention is a tool and method for imparting or restoring flatness and roughness to a surface, such as the support surface of a wafer chuck. The tool is shaped such that the contact to the surface being treated is a circle or annulus. The treatment method may take place in a dedicated apparatus, or in-situ in semiconductor fabrication apparatus. The tool is smaller than the diameter of the wafer pin chuck, and may be approximate to the spatial frequency of the high spots to be lapped. The movement of the tool relative to the support surface is such that all areas of the support surface may be processed by the tool, or only those areas needing correction. |
| US09941147B2 |
Transfer apparatus and laser annealing apparatus
A transfer apparatus includes a supporting member, a free electron excitation device and a detection device; the free electrons excitation device is configured to excite semiconductor material of an object to be transferred to generate free electrons, and the detection device is configured to detect whether material of a surface of the transferred object in contact with the support surface of the supporting member is conductive under excitation by the free electron excitation device. A laser annealing apparatus comprising the transfer apparatus is further provided. |
| US09941141B2 |
Guard ring structure of semiconductor arrangement
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring. |
| US09941140B2 |
Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of contact pads disposed over the substrate. The contact pads may be arranged in a ball grid array (BGA), and the may include a plurality of corners. A metal dam is disposed around each of the plurality of corners, such as corners of the BGA. |
| US09941139B2 |
Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. In one embodiment, a material layer is formed over a substrate and a first hard mask (HM) feature is formed over the material layer. The HM feature includes an upper portion having a first width and a lower portion having a second width which is greater than the first width. The method also includes forming spacers along sidewalls of the first HM feature, forming second HM features over the material layer by using the spacers as a first etch mask and forming patterned features in the material layer by using the second HM features as a second etch mask. |
| US09941137B2 |
Substrate planarizing method and dropping amount calculating method
According to one embodiment, a substrate planarizing method includes dropping from above a substrate with topography, resist whose amount is determined in accordance with the volume of a concave portion according to the topography. The distance between a blank template with a flat pressing plane and the substrate is set to a predetermined distance and then the resist is cured. After that, the blank template is released from the resist and the substrate is entirely etched. The amount of resist to be dropped on the substrate is adjusted for units of shot of the substrate. |
| US09941136B1 |
Back end of line (BEOL) method for polymer and biphenyl claddings
A method is provided for creating a chamber on a semiconductor substrate, utilizing wet etching or dry etching, back-filling the chamber with a polymeric compound, and sealing the chamber. |
| US09941135B2 |
Methods of forming a hard mask layer and of fabricating a semiconductor device using the same
A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N2O). A source of carbon and the nitrous oxide (N2O) are introduced to the substrate under a plasma ambient of an inert gas. The amorphous carbon layer has a nitrogen content ranging from about 0.05 at % to about 30 at % and an oxygen content ranging from about 0.05 at % to about 10 at %. In forming a semiconductor device, the hard mask layer is patterned, and a target layer beneath the hard mask layer is etched using the patterned hard mask layer as an etch mask. |
| US09941133B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency power for generating the plasma, a sample stage including an electrode electrostatically chucking the sample, mounting the sample thereon, a DC power supply applying DC voltage to the electrode, and a control device shifting the DC voltage previously set, in a negative direction by a first shift amount during discharge of the plasma, shifting the DC voltage having been shifted in the negative direction by the first shift amount, in a positive direction by a second shift amount after the discharge of the plasma. The first shift amount has a value changing potential over a surface of the sample to 0 V, upon shifting the DC voltage in the positive direction. The second shift amount has a value obtained based on a floating potential of the plasma. |
| US09941132B2 |
Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion inside the stage; a heater inside the stage; a support portion which supports a conveyance carrier between a stage-mounted position on the stage and a transfer position distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, application of voltage to the electrode portion is started in a state that the stage is being heated, and the plasma generation unit generates plasma after at least a part of an outer circumferential portion of a holding sheet holding the conveyance carrier contacts the stage and also after the heating of the stage is stopped. |
| US09941130B2 |
Thin plate separating method
A thin plate is separated from an SiC substrate having a first surface, an opposite second surface, a c-axis extending from the first surface to the second surface, and a c-plane perpendicular to the c-axis. The thin plate is formed by epitaxial growth on the first surface of the SiC substrate. The plate is separated by a separation start point forming step of setting the focal point of a laser beam near the first surface of the SiC substrate from the second surface, and applying the laser beam to the second surface to form a modified layer parallel to the first surface and cracks extending from the modified layer along the c-plane, thus forming a separation start point. An external force is applied to the SiC substrate to separate the thin plate from the SiC substrate at the separation start point. |
| US09941128B2 |
Method of lateral oxidation of NFET and PFET high-k gate stacks
A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack. |
| US09941127B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, and a gate electrode. The gate electrode has a first portion arranged with the second semiconductor region in a direction perpendicular to a first direction extending from the first electrode to the first semiconductor region, and has a second portion on the first portion. The semiconductor also includes a gate insulating layer between the gate electrode and each of the three semiconductor regions. The gate insulating layer extends to the upper surface of the third semiconductor region to form an extending portion. The second portion of the gate electrode protrudes in an upward direction from the upper surface of the extending portion of the gate insulating layer, and a lower part of the second portion of the gate electrode is embedded in the first portion of the gate electrode. |
| US09941123B1 |
Post etch treatment to prevent pattern collapse
A method for etching features in a stack comprising a patterned hardmask over a carbon based mask layer is provided. A pattern is transferred from the patterned hardmask to the carbon based mask layer, comprising providing a flow of a transfer gas comprising an oxygen containing component and at least one of SO2 or COS, forming the transfer gas into a plasma, providing a bias of greater than 10 volts, and stopping the flow of the transfer gas. A post treatment is provided, comprising providing a flow of a post treatment gas comprising at least one of He, Ar, N2, H2, or NH3, wherein the flow is provided to maintain a processing pressure of between 50 mTorr and 500 mTorr inclusive, forming the post treatment gas into a plasma, providing a bias of greater than 20 volts, and stopping the flow of the post treatment gas. |
| US09941122B2 |
Methods of forming staircase-shaped connection structures of three-dimensional semiconductor devices
Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions. |
| US09941121B1 |
Selective dry etch for directed self assembly of block copolymers
Methods for preparing a patterned directed self-assembly layer generally include providing a substrate having a block copolymer layer including a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer. The block polymer layer is exposed to a gas pulsing carbon monoxide polymer. The gas pulsing is configured to provide multiple cycles of an etching plasma and a deposition plasma to selectively remove the second pattern of the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the substrate. |
| US09941119B2 |
Method of forming silicon layer in manufacturing semiconductor device and recording medium
A method of manufacturing a semiconductor device includes alternately performing supplying a first process gas containing silicon and a halogen element to a substrate having a surface on which monocrystalline silicon and an insulation film are exposed and supplying a second process gas containing silicon and not containing a halogen element to the substrate, and supplying a third process gas containing silicon to the substrate, whereby a first silicon film is homo-epitaxially grown on the monocrystalline silicon and a second silicon film differing in crystal structure from the first silicon film is grown on the insulation film. |
| US09941115B2 |
Method for manufacturing semiconductor device
A release layer formed over a substrate; at least one of thin film integrated circuits is formed over the release layer; a film is formed over each of the at least one of thin film integrated circuits; and the release layer is removed by using an etchant; thus, the at least one of thin film integrated circuits is peeled from the substrate. A semiconductor device is formed by sealing the peeled thin film integrated circuit by lamination or the like. |
| US09941113B2 |
Systems and methods for using electrical asymmetry effect to control plasma process space in semiconductor fabrication
Systems and methods are disclosed for plasma enabled film deposition on a wafer in which a plasma is generated using radiofrequency signals of multiple frequencies and in which a phase angle relationship is controlled between the radiofrequency signals of multiple frequencies. In the system, a pedestal is provided to support the wafer. A plasma generation region is formed above the pedestal. An electrode is disposed in proximity to the plasma generation region to provide for transmission of radiofrequency signals into the plasma generation region. A radiofrequency power supply provides multiple radiofrequency signals of different frequencies to the electrode. A lowest of the different frequencies is a base frequency, and each of the different frequencies that is greater than the base frequency is an even harmonic of the base frequency. The radiofrequency power supply provides for variable control of the phase angle relationship between each of the multiple radiofrequency signals. |
| US09941109B2 |
Surface treatment in a chemical mechanical process
A method is presented that includes the step of polishing a wafer positioned on a platen. After polishing the wafer, the method includes initiating a high pressure rinse on the wafer while the wafer is positioned on the platen, wherein the high pressure rinse includes a hydrophilic solution. The wafer is soaked in the hydrophilic solution, and after soaking the wafer, the wafer is cleaned. |
| US09941106B2 |
Quadrupole robustness
An apparatus for filtering ions is disclosed comprising a separation device for separating ions temporally according to a first physico-chemical property and a first quadrupole rod set for filtering ions according to their mass to charge ratio, wherein the first quadrupole rod set comprises a plurality of rods and wherein the first quadrupole rod set is arranged downstream of the separation device. The apparatus further comprises a control system arranged and adapted during a single cycle of separation of the separation device: (i) to operate the first quadrupole rod set in a first resolving mode of operation wherein ions of interest are selected by the first quadrupole rod set; and (ii) to operate the first quadrupole rod set in a second non-resolving or transmission mode of operation at separation times when substantially no ions of interest are present so that substantially no ions impact upon the rods of the first quadrupole rod set. |
| US09941101B2 |
Plasma processing apparatus and upper electrode assembly
A plasma processing apparatus includes supporting members, connecting members and a sliding member. Each of the supporting members is partially disposed in a disc-shaped cooling plate and configured to support an upper electrode in a direction of gravity. Each of the connecting members is partially disposed in the cooling plate and extends in a diametrical direction of the cooling plate to be engaged with the corresponding supporting member. The sliding member is configured to slide the connecting members inward in the diametrical direction of the cooling plate, thereby pushing upward the supporting member and lifting the upper electrode to the cooling plate. |
| US09941097B2 |
Plasma processing apparatus
A plasma processing apparatus includes a processing chamber including a dielectric window; a coil-shaped RF antenna, provided outside the dielectric window; a substrate supporting unit provided in the processing chamber; a processing gas supply unit; an RF power supply unit for supplying an RF power to the RF antenna to generate a plasma of the processing gas by an inductive coupling in the processing chamber, the RF power having an appropriate frequency for RF discharge of the processing gas; a correction coil, provided at a position outside the processing chamber where the correction coil is to be coupled with the RF antenna by an electromagnetic induction, for controlling a plasma density distribution on the substrate in the processing chamber; a switching device provided in a loop of the correction coil; and a switching control unit for on-off controlling the switching device at a desired duty ratio by pulse width modulation. |
| US09941096B2 |
Glancing angle mill
A method and system for forming a planar cross-section view for an electron microscope. The method comprises directing an ion beam from an ion source toward a first surface of a sample to mill at least a portion of the sample; milling the first surface, using the ion beam, to expose a second surface in which the end of the second surface distal to the ion source is milled to a greater depth relative to a reference depth than the end of the first surface proximal to the ion source; directing an electron beam from an electron source to the second surface; and forming an image of the second surface by detecting the interaction of the electron beam with the second surface. Embodiments also include planarzing the first surface of the sample prior to forming a cross-section. |
| US09941086B2 |
Electrical component unit, fusible link unit, and fixing structure
Provided is a fusible link unit (electrical component unit) including a fusible link (electrical component), a battery terminal fixed to an electrode post (electrode) of a battery, and a support member formed as a different body from the battery terminal and fixed to the battery, the support member supporting the fusible link (electrical component), in which the fusible link (electrical component) includes a main link body (main electrical component body) and a power supply terminal made of conductive metal to be exposed from the main link body (main electrical component body) and electrically connected to the electrode post (electrode) through the battery terminal, and the support member supports the main link body (main electrical component body) such that the main link body extends in an orthogonal direction substantially orthogonal to an installation surface portion. |
| US09941085B2 |
Electrical switching apparatus, and movable arm assembly and movable arm therefor
A movable arm is for a movable arm assembly of an electrical switching apparatus. The movable arm assembly includes a first separable contact. The electrical switching apparatus has a housing, an operating handle coupled to the housing, and a second separable contact located internal the housing and being structured to engage the first separable contact. The movable arm includes a first arm member structured to be coupled to the first separable contact; and a second arm member coupled to the first arm member, the second arm member being structured to be coupled to the operating handle. The first arm member is made from a first copper material and the second arm member is made from a second, different copper material. |
| US09941083B2 |
Pressure switch
A pressure switch is disclosed. The pressure switch includes a housing and a pressure-receiving chamber that communicates with a duct to which an operating pressure is supplied. The pressure switch also includes a diaphragm assembly with a diaphragm that is displaced in response to a pressure inside the pressure-receiving chamber. The pressure switch also includes a movable contact that comes into contact with a fixed contact accommodated in a center portion of an inside of the housing when the pressure inside the pressure-receiving chamber is above a certain value. One of the movable contact and the fixed contact has radially diverging contact faces that are arranged such that contact between the fixed contact and the moveable contact can be established with at least two of the radially diverging contact faces at the same time. |
| US09941082B2 |
Float switch assembly
A float switch assembly for detecting fluid levels in a reservoir such as in a Christmas tree stand. When the fluid level drops below a predetermined point, the float switch activates an external circuit which provides a visual and/or audible signal. After the fluid level in the reservoir has been restored to the full position, the switch deactivates the external circuit and the visual and/or audible signal turns off. Also disclosed is a Christmas tree stand in combination with the float switch assembly. |
| US09941081B1 |
Sensor switch and method of assembly thereof
A sensor switch includes an insulated housing having an inner wall surface that defines a through hole. The through hole has a shoulder interconnecting large and small diameter hole sections thereof. A first conductive terminal includes a head portion embedded in the large diameter hole section and having a first contact surface. A plug portion of a second conductive terminal is embedded in the large diameter hole section spaced apart from the head portion and has a second contact surface facing the first contact surface. The inner wall surface and the first and second contact surfaces cooperatively confine a sensing chamber. At least one conductive member is rollably accommodated in the sensing chamber. |
| US09941074B2 |
Key structure and keyboard using the same
A key structure comprises a substrate, a membrane circuit disposed on the substrate, a waterproof structure disposed on the membrane circuit, a keycap, a conduction switch and a scissors structure. The waterproof structure includes a waterproof plate and a waterproof wall with a through hole. The waterproof wall surrounds the through hole and extends opposite to the membrane circuit. An end of the conduction switch passes through the through hole to be disposed on the membrane circuit, and the other end of the conduction switch protrudes from the waterproof wall to be connected to the keycap. The scissors structure includes a first end portion and a second end portion. The first end portion is pivotally connected to the keycap, and the second end portion is pivotally connected to the waterproof wall for the keycap to move up and down relatively to the membrane circuit. |
| US09941073B2 |
Keyboard device
A keyboard device includes a base plate, a key and a membrane circuit board. The key is connected with the base plate. The membrane circuit board is arranged between the key and the base plate. The base plate includes a connecting structure. The connecting structure is protruded upwardly and penetrated through the membrane circuit board. The key includes a keycap and a stabilizer bar. The stabilizer bar is pivotally coupled to the keycap. A hook part of the stabilizer bar is penetrated through a corresponding locking hole of the connecting structure. The membrane circuit board includes an extension part. The extension part is extended from a first side of the locking hole to a second side of the locking hole and penetrated through the locking hole. Consequently, the hook part of the stabilizer bar is movable on the extension part of the membrane circuit board. |
| US09941069B2 |
Switch-type key structure
An improved switch-type key structure includes a support plate, a microswitch, a connection element, and a key cap. The microswitch is fixed onto the support plate and is electrically connected thereto. The connection element is movably disposed on the support plate. The connection element includes a balance portion and a support portion extending downward from the balance portion. The key cap is disposed on the balance portion. The connection element is disposed between the support plate and the key cap through the microswitch, a hook hole corresponding to the support portion is disposed on the support plate, a hook is disposed at a distal end of the support portion, and the hook passes through the hook hole to engage the connection element with the support plate. Accordingly, the key cap is stressed evenly, returns instantly after being depressed, and is prevented from vibrations/wobbles. |
| US09941067B2 |
Key module and slip-on element for a key module
A key module has a housing and a tappet arranged in the housing. The tappet is movable in a linear manner between an upper stop position and a lower stop position in a manner limited by an upper stop and a lower stop, wherein an elastic element arranged in the housing pushes the tappet into the upper stop position, and wherein an actuating force exerted by a user pushes the tappet into the lower stop position and in the process reversibly compresses the elastic element. To reduce impact noises, the lower stop is formed by a first damping element and the upper stop is formed by a second damping element. The slip-on element has a carrier element to which a first damping element for reducing impact noises at the lower stop and a second damping element for reducing impact noises at the upper stop are attached. |
| US09941064B2 |
On-load tap changer, tap-changing transformer for voltage regulation and method for implementing tap changer in the tap-changing transformer
In an on-load tap changer (10) for controlling voltage of a tapped transformer (15) it is provided that the tapped transformer (15) has at least one regulatable phase (16) that has a first winding (20) and a second winding (30); the first winding (20) has a regulating winding (21) with even-numbered winding taps (23) and a main winding (22), and the second winding (30) has a regulating winding (31) with odd-numbered winding taps (33) and a main winding (32); the first winding (20) and the second winding (30) having the regulating windings (21, 31) of the even-numbered and of the odd-numbered winding taps (23, 33), are inductively coupled; the on-load tap changer (10) has a selector (40) for the alternating power-free preselection of the even-numbered or odd-numbered winding taps (23, 33) to be switched. |
| US09941063B2 |
Limit switch and method for producing same
A limit switch having a housing having a box, an attachment hold made in a side surface of the box, having a cylindrical bearing section, a rotating shaft rotatably inserted through the cylindrical bearing section, a cam unit provided in a leading end portion of the rotating shaft, and an operation lever provided in the other end portion of the rotating shaft. Rotational action of the operation lever is converted into vertical action by the cam unit in the box. A contact of a switch main body accommodated in and fixed to the housing is opened and closed. An outer diameter of the cam unit is smaller than an inner diameter of the attachment hole. |
| US09941054B2 |
Integration of embedded thin film capacitors in package substrates
An embedded thin film capacitor and methods of its fabrication are disclosed. The embedded thin film capacitor includes two conductive plates separated by a dielectric layer. In embodiments, the capacitor is enclosed within a package substrate. A method of forming the embedded thin film capacitor includes forming a first insulating layer on a bottom plate and a first trace. A first opening is then formed in a first insulating layer to expose a first region of a bottom plate. An adhesive layer is then formed on the first insulating layer and on top of the exposed first region of the bottom plate. A second opening is formed through the insulating layer and the first insulating layer to expose a second region of the bottom plate. A top plate is formed within the first opening and a via is formed within the second opening. |
| US09941052B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a body and at least two outer electrodes. The body includes first and second main surfaces, an inner layer portion and first and second outer layer portions. In the inner layer portion, dielectric layers and conductive layers are alternately stacked on each other. The second outer layer portion includes an outer portion and an inner portion. A boundary region adjacent to the inner portion in the outer portion inclines toward the first main surface. |
| US09941048B2 |
Non-contact wireless communication coil, transmission coil, and portable wireless terminal
A chargeable communication module is provided, which includes: a wireless power charging coil; a wireless communication coil being electrically isolated from the wireless power charging coil; and a magnetic body. The wireless power charging coil is disposed on a surface of the magnetic body. The wireless communication coil is arranged adjacent to and outside of the wireless power charging coil. At least a portion of the wireless communication coil is disposed on the surface of the magnetic body. |
| US09941046B2 |
Circuit arrangement for reducing a unidirectional flux component in the soft-magnetic core of a transformer
A circuit arrangement for reducing unidirectional flux component in a transformer core includes a compensation winding magnetically coupled to the transformer core, a transductor series connected with the compensation winding in a compensation current path, wherein the compensation current path has two parallel branches each containing a power winding of the transductor and an uncontrolled valve connected in series, where flow directions of the valves run counter to one another, and where each power winding is magnetically coupled to a control winding via a saturable transductor core, and includes a controller to which a detector supplies magnitude and direction information of the unidirectional flux component, and which generates a control variable supplied to each control winding such that the saturation state of the transductor core is variable such that a compensation current is formed in the compensation current path that counteracts the unidirectional flux component in the transformer core. |
| US09941044B2 |
Insulation type step-down converter
An insulation type step-down converter includes first and second step-down transformers each of which includes an input-side coil and an output-side coil. An intermediate portion of the output-side coil of the first step-down transformer and an intermediate portion of the output-side coil of the second step-down transformer are connected to each other. First, second, third, and fourth rectifier elements are connected in series with first, second, third, and fourth output-side coils, respectively. Smoothing coils are connected to the first to fourth output-side coils. The first, second, third, and fourth rectifier elements are connected such that electric currents flow simultaneously in the first output-side coil and the third output-side coil, and electric currents flow simultaneously in the second output-side coil and the fourth output-side coil in a manner alternating with the electric currents in the first output-side coil and the third output-side coil. |
| US09941043B2 |
Core for an electrical induction device
A core for an electrical induction device has a plurality of lamination stacks which are each formed by laminated sheets. The lamination stacks lie on top of each other parallel to the layer plane of the laminated sheets. At least one of the lamination stacks is segmented and has at least two partial lamination stacks, the two partial lamination stacks respectively lying opposite each other with their stack end faces standing transverse, in particular perpendicular, to the layer plane of the laminated sheets. The stack end faces of the two partial lamination stacks have a spacing between each other through which a gap is formed extending between the two partial lamination stacks perpendicular to the layer plane. The gap forms a cooling channel or at least a section of a cooling channel, the channel longitudinal extension thereof extending transversely, in particular, perpendicular to the layer plane of the laminated sheets. |
| US09941041B2 |
Electromechanical assembly controlled by sensed voltage
An electromechanical assembly is provided controlled by voltage across a motor or with an electronic system. The electromechanical assembly includes a control circuit coupled to sense voltage at the motor or within the electronic system, and an electromechanical actuator energized by the voltage sensed by the control circuit. A movable element is movable by the electromechanical actuator from an operational position to a quiesced position when the voltage sensed by the control circuit falls below a quiesced threshold. In certain embodiments, the voltage being sensed is across a motor of an air-moving assembly, which resides within a support structure, or the voltage being sensed is within the electronic system, which resides within the support structure, and the movable element is an interlock element which interlocks to the support structure to prevent removal of one or more components from the structure when sensed voltage is above the quiesced threshold. |
| US09941040B2 |
Soft magnetic core with position-dependent permeability
A soft magnetic core is provided, in which permeabilities that occur at least two different locations of the core are different. A method for producing a soft magnetic core that has different permeabilities at at least two different locations is also provided. |
| US09941039B2 |
Soft magnetic member, reactor, powder for dust core, and method of producing dust core
A soft magnetic member is formed such that, when a differential relative permeability in an applied magnetic field of 100 A/m is represented by a first differential relative permeability μ′L, and when a differential relative permeability in an applied magnetic field of 40 kA/m is represented by a second differential relative permeability μ′H, a ratio of the first differential relative permeability μ′L to the second differential relative permeability μ′H satisfies a relationship of μ′L/μ′H≤10, and a magnetic flux density in an applied magnetic field of 60 kA/m is 1.15 T or higher. |
| US09941031B2 |
Downhole cables with both fiber and copper elements
Provided is a method of manufacturing a downhole cable, the method including, forming a helical shape in an outer circumferential surface of a metal tube, the metal tube having a fiber element housed therein, and stranding a copper element in a helical space formed by the metallic tube. Also provided is a downhole cable including, a metallic tube having a helical space in an outer circumferential surface thereof, wherein the metallic tube has a fiber element housed therein, and a copper element, disposed in a helical space formed by the steel tube. Double-tube and multi-tube configurations of the downhole cable are also provided. |
| US09941030B2 |
Electromagnetic and anti-ballistic shield cable
In general, aspects of this invention relate to electrical cables and, in particular, to a cable with electromagnetic and/or anti-ballistic shielding. According to one aspect, a cable may comprise: a conductor; a continuous metallic sheath surrounding the conductor; and a supplemental sheath layer surrounding the metallic sheath. According to another aspect, a cable may comprise: a conductor; an armor layer surrounding the conductor; a fabric layer surrounding the conductor; and a polymer layer surrounding the conductor. According to yet another aspect, a cable may comprise: a conductor; an inner synthetic strength member surrounding the conductor; a polymer compound positioned between the conductor and the inner synthetic strength member; a polymer layer surrounding the inner synthetic strength member; an armor layer surrounding the polymer layer; an outer synthetic strength member surrounding the armor layer; and a polyolefin layer surrounding the outer synthetic strength member. |
| US09941027B2 |
Process and installation for producing radioisotopes
The invention relates to a method for producing a radioisotope, which method comprises irradiating a volume of radioisotope-precursor fluid contained in a sealed cell of a target using a beam of particles of a given current, which beam is produced by a particle accelerator. The target is cooled and the internal pressure in the sealed cell is measured. During the irradiation, the internal pressure (P) in the sealed cell is allowed to vary freely. The irradiation is interrupted or its intensity is reduced when the internal pressure (P) in the sealed cell departs from a first tolerated range defined depending on various parameters that influence the variation in the internal pressure in the sealed cell during the irradiation. These parameters for example comprise, for a given target, particle beam and radioisotope-precursor fluid: the degree of filling of the hermetic cell, the cooling power used to cool the given target, and the beam current (I). The invention also relates to an installation for implementing the method. |
| US09941022B2 |
Setting a default read signal based on error correction
A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword of the page of data as read with the first discrete read signal. Methods can include reading a page of data from the group of memory cells with a second discrete read signal different than the first discrete read signal and error correcting at least one codeword of the page of data as read with the second discrete read signal. One of the first and the second discrete read signals can be set as a default read signal based at least in part on the respective error corrections. |
| US09941015B2 |
Semiconductor memory device
A semiconductor memory device includes first to third pages, first to the third word lines, and a row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to gates of first to third memory cells in a program verify operation. |
| US09941014B2 |
Nonvolatile memory device, nonvolatile memory system including the same, and method of operating the same
A nonvolatile memory device includes a memory cell array having a normal area and a temporary area. A page buffer stores data to be written to the normal area in a normal program operation and store a temporary data to be written to the temporary area in a temporary program operation. A control logic performs the normal program operation including a plurality of program loops. The control logic receives a suspend command before the normal program operation is completed and determines, in response to the suspend command, whether to complete the normal program operation or to suspend the normal operation and perform the temporary program operation based on a reference value representing a time for performing at least one program loop of the plurality of program loops. |
| US09941013B2 |
Memory device that performs sensing operation during a bit line pre-charge operation to determine adjustment to the bit line charging voltage
A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a plurality of the memory cells, and a control circuit configured to perform a determination operation on the memory cells. During the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged using a bit line charge voltage, and the bit line charge voltage is adjusted based on a result of a first sensing operation that is performed on the first bit line. A second sensing operation is performed on the first bit line after the first sensing operation to determine whether a threshold voltage of the first memory cell is greater than a reference voltage. |
| US09941012B2 |
Twin memory cell interconnection structure
Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection gate. According to the disclosure, two bitlines are provided per column of memory cells. The adjacent twin memory cells of the same column are not connected to the same bitline while the adjacent non-twin memory cells of the same column are connected to the same bitline. |
| US09941007B2 |
Solid state drive architectures
A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes writes to the flash memory. A method for operation of a solid state flash device includes writing, by a CPU, to a solid state drive by sending commands and data to DRAM logical flash using flash commands and formatting. |
| US09941006B1 |
Memory device and method for driving same
A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first direction, a third interconnect extending in a third direction crossing a plane including the first direction and the second direction, a fourth interconnect extending in the third direction, a semiconductor member, a first resistance change film, and a second resistance change film. The semiconductor member is connected between a first end of the second interconnect and the first interconnect. The first resistance change film is connected between a side surface of the second interconnect and the third interconnect. The second resistance change film is connected between a second end of the second interconnect and the fourth interconnect. |
| US09941005B2 |
Fast read speed memory device
A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a common node, and a switching element comprising an input terminal electrically coupled with the common node, the switching element comprising a driver configured to float during one or more operations. |
| US09941003B2 |
Multi-level resistive memory structure
A resistive memory structure comprises a resistive memory element, a resistance block electrically connected to the memory element through an electrical node, and an interpretation circuit electrically connected to the node and configured to interpret a voltage at the node and to indicate a resistive state of the memory element based on the voltage at the node. The interpretation circuit includes one or more active devices, one or more passive devices each electrically connected to a respective one of the active devices, and one or more comparators each electrically connected to a respective one of the active devices. Each of the active devices and the passive device electrically connected thereto are configured to provide a voltage level to the respective comparator to which the active device is connected. The comparator(s) are configured to indicate the resistive state of the memory element based on the provided voltage level(s). |
| US09941001B2 |
Circuits for determining the resistive states of resistive change elements
Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements by sensing current flow. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can determine resistive states of resistive change elements without the need for in situ selection devices or other current controlling devices. According to some aspects of the present disclosure the devices and methods for determining resistive states of resistive change elements can reduce the impact of sneak current when determining resistive states of resistive change elements. |
| US09940994B2 |
Write assist circuit for lowering a memory supply voltage and coupling a memory bit line
A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor. |
| US09940989B2 |
STT-MRAM cell structures
A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free layer, a pinned layer, and a nonmagnetic bridge electrically connecting the free layer and the pinned layer. The shape and/or configuration of the nonmagnetic bridge directs a programming current through the magnetic cell structure such that the cross sectional area of the programming current in the free layer of the structure is less than the cross section of the structure. The decrease in the cross sectional area of the programming current in the free layer enables a lower programming current to reach a critical switching current density in the free layer and switch the magnetization of the free layer, programming the magnetic cell. |
| US09940984B1 |
Shared command address (C/A) bus for multiple memory channels
A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory subsystem. In one embodiment, a memory controller includes hardware logic to generate commands to access a plurality of memory devices via a plurality of channels and input/output (I/O) circuitry to transmit command/address (C/A) information for the commands to the plurality of memory devices over a single C/A bus for the plurality of channels. In one embodiment, double-speed strobe signal lines can also enable reducing the number of pins and signal lines in a memory subsystem. |
| US09940983B2 |
Channel controlling device for improving data reading efficiency
A channel controlling device includes: a multiplexing circuit coupled to multiple channels for selecting a particular channel from the channels to output a channel data according to a selection signal, wherein the channels correspond to multiple predetermined digital numbers; a sorting circuit arranged to sort the predetermined digital numbers to form multiple sorted digital numbers according to a data output order of the channels; and an arbitration circuit, arranged to determine the selection signal according to the plurality of sorted digital numbers. |
| US09940979B2 |
Semiconductor device including a redistribution layer
A semiconductor device may include a first redistribution layer configured to allow for input and output of a first signal through the first redistribution layer. The semiconductor device may include a second redistribution layer configured to allow for input and output of a second signal through the second redistribution layer. The semiconductor device may include a first input/output (I/O) unit configured to input and output the first signal or the second signal through the first I/O unit. The semiconductor device may include a first selection unit configured to selectively couple a connection among the first redistribution layer, the second redistribution layer, and the first I/O unit in response to a logic level of a first selection signal. The semiconductor device may include a first selection signal generation unit configured to generate the first selection signal. |
| US09940976B1 |
Data storage library with component locker for environmental acclimation
A data storage library system and method comprising at least one data storage library, the at least one data storage library comprising one or more library frames associated with the one or more library frames and at least one environmental conditioning unit configured to control one or more environmental conditions within the one or more library frames. At least one component locker is housed in an interior portion of the one or more library frames, and the at least one component locker is configured to retain one or more replacement components for use in the at least one data storage library. |
| US09940969B2 |
Audio/video methods and systems
Audio and or video data is structurally and persistently associated with auxiliary sensor data (e.g., relating to acceleration, orientation or tilt) through use of a unitary data object, such as a modified MPEG file or data stream. In this form, different rendering devices can employ co-conveyed sensor data to alter the audio or video content. Such use of the sensor data may be personalized to different users, e.g., through preference data. For example, accelerometer data can be associated with video data, allowing some users to view a shake-stabilized version of a video, and other users to view the video with such motion artifacts undisturbed. In like fashion, camera parameters, such as focal plane distance, can be co-conveyed with audio/video content—allowing the volume to be diminished (or not, again depending on user preference) when a camera captures audio/video from a distant subject. Some arrangements employ multiple image sensors and/or multiple audio sensors—each also collecting auxiliary data. A great number of other features and arrangements are also detailed. |
| US09940968B2 |
Methods and apparatus to perform speed-enhanced playback of recorded media
Methods, apparatus, systems and articles of manufacture to perform speed-enhanced playback of recorded media are disclosed. An example method includes parsing an audio frame included in the media to determine a number of skip bytes included in the audio frame, identifying the audio frame as a candidate frame when the number of skip bytes satisfies a skip bytes threshold, and calculating a speed-enhanced playback rate for the media based on a plurality of candidate frames identified in the media. |
| US09940967B1 |
Data storage device conditioning write abort based on secondary read signal
A data storage device is disclosed comprising a first disk surface comprising a plurality of servo tracks, a first head actuated over the first disk surface, wherein the first head comprises a first read element, and a second read element. During a write operation first servo data in a first servo track is read using the first read element to generate a first read signal, and the first head is servoed over the first servo track based on the first read signal while writing data to the first disk surface. Second servo data is read using the second read element to generate a second read signal, and the write operation is aborted when the first read signal indicates a shock event is affecting the servoing of the first head and the second read signal confirms the shock event. |
| US09940965B2 |
Thermal management of laser diode mode hopping for heat assisted media recording
A method and apparatus provide for determining a temperature at a junction of a laser diode when the laser diode is operated in a lasing state that facilitates heat-assisted magnetic recording, comparing the junction temperature and an injection current supplied during the lasing state to stored combinations of junction temperature and injection current, and determining a likelihood of mode hopping occurring for the laser diode during the lasing state based on the comparison to stored combinations of junction temperature and injection current. |
| US09940963B1 |
Magnetic media with atom implanted magnetic layer
A method for manufacturing a magnetic media for magnetic data recording that improves smoothness for reduced magnetic spacing, and also improves mechanical integration to improve reliability and lifespan of the data recording system. A magnetic material such as a magnetic recording layer is deposited over underlying layers that include a substrate. A first etching is performed that employs a Xe plasma. A second etching is then performed that employs an Ar plasma. The two step etching process advantageously improves smoothness of the surface of the magnetic layer which allows for a thinner overcoat for reduced magnetic spacing. The two step etching process also results in less head disk crashes, resulting in improved reliability. |
| US09940962B2 |
Low power thermally assisted data recording media
In some embodiments, a thermally assisted data recording medium has a recording layer formed of iron (Fe), platinum (Pt) and a transition metal T selected from a group consisting of Rhodium (Rh), Ruthenium (Ru), Osmium (Os) and Iridium (Ir) to substitute for a portion of the Pt content as FeYPtY-XTX with Y in the range of from about 20 at % to about 80 at % and X in the range of from about 0 at % to about 20 at %. |
| US09940961B2 |
Perpendicular magnetic recording medium
A perpendicular magnetic recording medium includes a non-magnetic substrate; and a magnetic recording layer that includes magnetic crystal grains and a non-magnetic crystal grain boundary that surrounds the magnetic crystal grains, wherein the magnetic crystal grains contain an ordered alloy and the non-magnetic crystal grain boundary contains Ge oxides. The magnetic recording layer may have a granular structure. The magnetic crystal grains may be micronized to be sufficiently ordered and separated, and the perpendicular magnetic recording medium may have a high magnetic anisotropy constant Ku and high coercivity Hc. |
| US09940956B1 |
Apparatus and method for reducing corrosion in capping layer of magnetic recording reader
Aspects of the present disclosure provide a magnetic reader and methods for fabricating the same. The magnetic reader has a capping layer structure that can reduce or impede the corrosion and/or recession of a shield layer of the magnetic reader. In a particular embodiment, the capping layer structure includes a ruthenium (Ru) layer that is configured to impede oxygen interdiffusion between an IrMn antiferromagnetic layer and a Ta cap layer. |
| US09940955B2 |
Tunnel magnetoresistance magnetic sensor with scissor sensor and multi-seed layer configuration
A read head is provided with a scissors sensor. The read head may include a bottom magnetic shield, and a first non-magnetic seed layer, a magnetic seed layer, a second non-magnetic seed layer, an antiferromagnetic layer, a coupling layer, a first free magnetic layer, a spacer layer, and a second free magnetic layer positioned above the bottom magnetic shield, in this order. A pair of magnetic side shield layers may be positioned on respective sides of the second free magnetic layer. |
| US09940953B1 |
Si-based overcoat for heat assisted magnetic recording media
A stack includes a heatsink layer, a magnetic recording layer disposed over the heatsink layer, and a Si-based overcoat layer disposed over the magnetic recording layer. The Si-based overcoat layer is substantially devoid of carbon. |
| US09940952B2 |
Abrasion test methods and devices
A method according to one embodiment includes measuring an initial coating thickness on a tape bearing surface of a module in a carrier, running a tape across the tape bearing surface, and at intervals, measuring a residual thickness of the coating. |
| US09940951B2 |
PMR writer with non-conformal side gaps
A perpendicular magnetic recording (PMR) writer is configured to magnetically record data on a rotatable disk surface. The PMR writer including a pole tip, side shields, an air-bearing surface (ABS) region, a yoke region comprising Silicon Dioxide (SiO2), side gaps and a plurality of throat regions. The side gaps are arranged respectively between the pole tip and the side shields and include SiO2. A side gap width of the plurality of throat regions increases with a side shield throat height above the ABS region for each of the throat regions. The side gap width has a different width variation in each of the throat regions. |
| US09940949B1 |
Dynamic adjustment of expression detection criteria
In a speech-based system, a wake word or other trigger expression is used to preface user speech that is intended as a command. The system receives multiple directional audio signals, each of which emphasizes sound from a different direction. The trigger expression is detected in an individual directional audio signal by comparing a confidence score with a confidence threshold. An individual confidence threshold is specified for each directional audio signal. The confidence thresholds are adjusted during operation of the system based on performance information that is generated during operation of the system. As an example, performance information may include the number of times that the trigger expression has been detected in each of the directional audio signals. |
| US09940942B2 |
Advanced quantizer
The present document relates an audio encoding and decoding system (referred to as an audio codec system). In particular, the present document relates to a transform-based audio codec system which is particularly well suited for voice encoding/decoding. A quantization unit configured to quantize a first coefficient of a block of coefficients is described. The block of coefficients comprises a plurality of coefficients for a plurality of corresponding frequency bins. The quantization unit is configured to provide a set of quantizers. The set of quantizers comprises a plurality of different quantizers associated with a plurality of different signal-to-noise ratios, referred to as SNR, respectively. The plurality of different quantizers includes a noise-filling quantizer; one or more dithered quantizers; and one or more un-dithered quantizers. The quantization unit is further configured to determine an SNR indication indicative of a SNR attributed to the first coefficient, and to select a first quantizer from the set of quantizers, based on the SNR indication. In addition, the quantization unit is configured to quantize the first coefficient using the first quantizer. |
| US09940939B2 |
Audio encoder and decoder
The present disclosure provides methods, devices and computer program products for encoding and decoding of a vector of parameters in an audio coding system. The disclosure further relates to a method and apparatus for reconstructing an audio object in an audio decoding system. According to the disclosure, a modulo differential approach for coding and encoding a vector of a non-periodic quantity may improve the coding efficiency and provide encoders and decoders with less memory requirements. Moreover, an efficient method for encoding and decoding a sparse matrix is provided. |
| US09940936B2 |
Methods and apparatus for detecting a voice command
According to some aspects, a method of monitoring an acoustic environment of a mobile device, at least one computer readable medium encoded with instructions that, when executed, perform such a method and/or a mobile device configured to perform such a method is provided. The method comprises receiving, by the mobile device, acoustic input from the environment of the mobile device, detecting whether the acoustic input includes a voice command from a user without requiring receipt of an explicit trigger from the user, and initiating responding to the detected voice command. |
| US09940933B2 |
Method and apparatus for speech recognition
A speech recognition method includes receiving a sentence generated through speech recognition, calculating a degree of suitability for each word in the sentence based on a relationship of each word with other words in the sentence, detecting a target word to be corrected among the words in the sentence based on the degree of suitability for each word, and replacing the target word with any one of candidate words corresponding to the target word. |
| US09940926B2 |
Rapid speech recognition adaptation using acoustic input
A method includes the following steps. An acoustic input is obtained from a user, including issuing a verbal prompt to the user and receiving the acoustic input from the user in response to the verbal prompt. One or more acoustic representations are obtained, wherein the one or more acoustic representations are generated from a list of expected responses to the issued verbal prompt. The acoustic input from the user is compared to the one or more acoustic representations. One or more speech recognition parameters are adjusted based on the comparison. |
| US09940923B2 |
Voice and text communication system, method and apparatus
The disclosure relates to systems, methods and apparatus to convert speech to text and vice versa. One apparatus comprises a vocoder, a speech to text conversion engine, a text to speech conversion engine, and a user interface. The vocoder is operable to convert speech signals into packets and convert packets into speech signals. The speech to text conversion engine is operable to convert speech to text. The text to speech conversion engine is operable to convert text to speech. The user interface is operable to receive a user selection of a mode from among a plurality of modes, wherein a first mode enables the speech to text conversion engine, a second mode enables the text to speech conversion engine, and a third mode enables the speech to text conversion engine and the text to speech conversion engine. |
| US09940921B2 |
Vehicle, vehicle control method and vehicle driving sound control apparatus
A vehicle, a vehicle control method, and a vehicle driving sound control apparatus in which a user may freely generate a requested vehicle driving sound using a user terminal and generate an additional driving sound more similar to an actual vehicle driving sound by vibrating a structure of a vehicle using an exciter are provided. The vehicle includes a controller configured to receive vehicle driving sound parameters requested by a user from a user terminal and an exciter configured to vibrate a structure of a vehicle based on the vehicle driving sound parameters. |
| US09940918B2 |
Toot suite whistle pack
A set of two or more whistles. Each whistle of the set sounds differently from each other based on a different type of sound or a different value of a characteristic of sound common to whistles of the set. Sound characteristics may include but not limited to pitch, quality, loudness, and/or duration. Each whistle in the set may be different in appearance from each other in the set. Appearance characteristics may include but not limited to color, numbering, design, light up features, size, and/or shape. Alternatively, the whistles in a set may have a common appearance characteristic, but each whistle may have its own value of the common appearance characteristic. Additional element(s) such as lanyards or mouthpieces may be added to whistles of a set to distinguish them from each other. The set of whistles may be included in a kit having a box for removably storing the whistles. |
| US09940914B2 |
Score displaying method and storage medium
A controller of a score displaying apparatus operates in a view mode displaying a score on a screen of a user I/F 12, and a writing mode obtaining information indicating writing on the score via the user I/F 12. In response to one operation specifying one grand staff by a user in the view mode, the controller performs a process of enlarging an image of an image area to which the specified grand staff belongs and displaying the enlarged image on a foreground of a center of the screen, and performs a process of switching a control mode from the view mode to the writing mode. |
| US09940913B1 |
Rotational pivot structure within single reed woodwind ligature system
A single reed woodwind ligature system has an upper U-shaped structure for contacting the upper portion of a mouthpiece at one or more small areas of contact and for engaging a lower structure, preferably by threaded ends and nuts. A reed contactor plate contacts a reed at a portion of its bottom curved surface. At least one ball bearing sphere is located in aligned cavities of the lower structure and the reed contactor in a spaced-apart configuration and forms a pivot mechanism capable of roll, pitch and yaw rotations in three dimensions around the approximate center of the at least one sphere. Embodiments include multiple spheres and sphere-bearing pin contact combinations forming the three-dimensional adjustable pivot. A retainer holds the spherical pivot components together when the ligature system is not clamping the reed to the mouthpiece without hampering user adjustments in the three normal (roll, pitch and yaw) dimensional ranges. |
| US09940910B1 |
Apparatus and system for stretching a string of a musical instrument and corresponding method thereof
A string stretching apparatus, system and method are described. The string stretching apparatus may include lower and upper raised portions at an outer surface of a body of the stretching apparatus. A portion of the body of the string stretching apparatus may be placed in contact with a neck of a musical instrument. The lower and upper raised portions may be configured to extend outwardly to extend a distance between the neck of the musical instrument and at least one string of the musical instrument. The string stretching apparatus may be manipulable in a longitudinal direction of the neck of the musical instrument, and either or both of the lower and upper raised portions may be configured to rotate, in order to increase or decrease string tension. |
| US09940909B2 |
Display system with a virtual display
A system for generating a virtual display that is displayed on an existing monitor using a memory (e.g., graphics processing unit (GPU) memory, random access memory (RAM), etc.) of a connected device (e.g., a computer) as a frame buffer for the virtual display. For example, the virtual display may use the RAM or the memory of the GPU of the connected device as a second frame buffer to generate the frames displayed in the virtual display. The virtual display is not a physical display and, thus, does not require any additional hardware or physical space. Rather, the virtual display is displayed on a pre-existing display. The pre-existing display is also used to display the frames generated in a first frame buffer. |
| US09940907B2 |
Virtual surface gutters
Virtual surface techniques are described. These techniques support the use of initialization and batching of updates, use of updates and lookaside lists, use of gutters, blending and BLT operations, use of surface optimization techniques such as push down as well as enumeration and clumping, mesh usage, and use of occlusion management techniques. |
| US09940902B2 |
Automatic brightness control for displays
An automatic brightness adjustment for devices with displays includes the capability to assess ambient light. The assessment may be made using circuitry, such as a light meter circuit, by exploiting exposure control circuitry, or using other approaches. The ambient light value is sent to a brightness adjustment driver, which may employ a look-up table to keep track of brightness adjustments for particular ambient conditions. The look-up table may include distinct adjustment values. |
| US09940899B2 |
Image processing apparatus, color adjustment system, and non-transitory computer readable medium
An image processing apparatus includes an image information transmission unit, a color information acquisition unit, and a conversion relationship creation unit. The image information transmission unit transmits, to a display device, pieces of color-conversion image information representing images used for performing color conversion for the display device, in ascending order of lightness of the images in a predetermined color space. The color information acquisition unit acquires color information of each image that is displayed on the display device in accordance with a corresponding piece of color-conversion image information among the pieces of color-conversion image information that have been transmitted by the image information transmission unit. The conversion relationship creation unit creates, on the basis of the color information that has been acquired by the color information acquisition unit, a conversion relationship for a color of an image to be displayed on the display device. |
| US09940898B2 |
Variable refresh rate video capture and playback
A method for displaying video. The method includes executing an application at a processor. As instructed by the processor when executing the application, the method includes rendering a plurality of image frames at a plurality of graphics processing units (GPUs). The method includes determining information related to relative timing between renderings of the plurality of image frames. The method includes encoding the plurality of image frames into a video file. The method includes encoding the information into the video file. |
| US09940896B2 |
Telecine judder removal systems and methods
One embodiment of the present disclosure describes an electronic display. The electronic display includes a display driver that write image frames to pixels of the electronic display with a first refresh rate or a second refresh rate, in which the second refresh rate is less than the first refresh rate. Additionally, the electronic display includes a timing controller that receives image frames from an image source, in which one or more of the image frames are configured to be displayed on the display panel to play video content; determines a capture rate of the video content based at least in part on a cadence with which the image frames are received, in which the capture rate describes a rate at which each of the one or more image frames was captured by an image sensor; and instructs the display driver to write the one or more of the image frames at the second refresh when the second refresh rate is an integer multiple of the capture rate. |
| US09940895B1 |
Displays with safety segregation
Display systems and methods for configuring such display systems are disclosed. A display system may include a display and a monitoring processor in communication with the display. The monitoring processor may be configured to monitor a status of a device and present the status of the device on the display. The display system may also include a control processor in communication with the display. The control processor may be configured to operate independently with respect to the monitoring processor. The control processor may be further configured to process a user input and facilitate control of the device based on the user input received. |
| US09940890B2 |
Liquid crystal display device
Provided is a liquid crystal display device, including: a plurality of scanning connection lines formed on at least one side of edges of the image display region, the plurality of scanning connection lines connecting together a scanning signal drive circuit and a plurality of scanning signal lines; a selection circuit formed so as to be interposed between the plurality of scanning connection lines and the plurality of scanning signal lines, the selection circuit being configured to selectively short-circuit one of a plurality of the scanning signal lines to one of the plurality of scanning connection lines based on a selection signal; and a selection signal line connected to the selection circuit, the selection signal line transmitting the selection signal to the selection circuit. |
| US09940888B2 |
Display device with signal lines detouring around opening inside display area
A display device is disclosed. The display device includes a substrate having an active area including a plurality of pixels, a bezel area positioned outside the active area, and at least one opening area positioned inside the active area, at least one opening positioned in the opening area, first signal lines arranged in a first direction and making a detour around the opening in the opening area, and second signal lines arranged in a second direction and making a detour around the opening in the opening area. The opening area includes a first opening area in which the first signal lines are arranged and which is adjacent to the opening, and a second opening area in which the second signal lines intersecting the first signal lines are arranged and which is spaced from the opening. |
| US09940887B2 |
Liquid crystal display device, method of driving liquid crystal display device, and electronic apparatus
A liquid crystal display device is provided. The liquid crystal including an array of pixels each having a memory function; and a buffer to output a first voltage, wherein a second voltage is supplied to a counter electrode of a liquid crystal capacitor, and wherein each of the pixels supplies one of the first voltage and the second voltage to a pixel electrode of the liquid crystal capacitor according to a data value stored in the each of the pixels. |
| US09940886B2 |
Display device which prevents occurrence of flicker
A display device which prevents or minimizes the occurrence of flicker is provided. The display device includes a display panel having pixels, with data lines and gate lines that are respectively connected with the pixels. A display driving circuit is configured to vary a frame frequency of the display panel according to an operation mode, to select a gamma curve corresponding to the frame frequency. The selected gamma curve is one among gamma curves that are set so as to correspond to different frame frequencies. The display panel is driven based on the selected gamma curve. |
| US09940882B2 |
Source driver circuit and display device
In the technical field of display, a source driver circuit and a display device according to the present disclosure, which can effectively reduce the heat generating efficiency of a gamma driver circuit cooperating with the source driver circuit, lower the temperature of the gamma driver circuit, and facilitate the integration of the gamma driver circuit with other driver circuits, are provided. The source driver circuit is in connection with several pixel gray scale reference voltages from the gamma driver circuit, and comprises several operational amplifiers, the number of which equals to that of the pixel gray scale reference voltages outputted from the gamma driver circuit, and the operational amplifiers each are connected with a corresponding pixel gray scale reference voltage. |
| US09940874B2 |
Pixel compensating circuits, related display apparatus and method for driving the same
The present disclosure provides a pixel compensating circuit. The circuit includes a driving module and a resetting module connected to a reference voltage line for providing an initial potential and a reset-control potential, a scanning signal line, and the driving module. The circuit further includes a data-writing module connected to a data signal line, the scanning signal line, and the driving module. |
| US09940870B2 |
Display unit, image processing unit, and display method for improving image quality
An image processing unit includes: a gain calculating section obtaining, based on first luminance information for each pixel, a first gain, in which the first gain is configured to increase with an increase in pixel luminance value in a range where the pixel luminance value is equal to or larger than a predetermined luminance value, and in which the pixel luminance value is derived from the first luminance information; and a determination section determining, based on the first luminance information and the first gain, second luminance information for each of the pixels. |
| US09940867B2 |
Level shift circuit and display driver
A level shift circuit configured to generate an output signal having higher amplitude than that of an input signal. The level shift circuit includes serially-connected first and second level shift circuit for two-step amplitude increase of the input signal. The first level shift circuit includes first to fourth transistors, each of which has a control terminal and first and second current terminals, and first and second resistance elements respectively connected between the first and third transistors, and between the second and fourth transistors. A potential difference between two ends of each resistance element is respectively smaller than, or no smaller than, a respective predetermined potential difference when a current does not flow, or flows, therethrough. The second level shift circuit has fifth to tenth transistors, each of which has a control terminal and first and second current terminals. The output signal is outputted through a connection between the second current terminals of the fifth and ninth transistors. |
| US09940866B2 |
Electronic device having display with curved edges
A display may have an array of pixels. The array of pixels may have a shape such as a circular shape or other shape with a curved edge. Display driver circuitry may supply data signals to the pixels using folded vertical data lines and bisected horizontal gate lines. Each folded vertical lines may have a first segment in a left half of the array and a second segment in a right half of the display. Curved coupling segments in an inactive area of the display may be used in joining the first and second segments. Display driver circuits may be provided in top and bottom portions of the inactive area to supply data to respective top and bottom portions of the array. Gate driver output buffers may have different strengths in different rows of the array. |
| US09940864B2 |
Display device and method for driving same
There is provided a display device that is capable of suppressing occurrence of brightness drop which is caused by refresh of a display image during pause driving. In a normal driving mode, input image data (SsD0) according to a continuous tone method is supplied to a source driver (310) through a data selector (230) as an image signal (SsD) for driver. On the other hand, in a low-frequency driving mode in which pause driving is performed, the input image data (SsD0) is converted into dithered input image data (SsD1) by a dithering processing circuit (220), and is supplied to the source driver (310) through the data selector (230) as the image signal (SsD) for driver. A gradation of the dithered input image data (SsD1) is represented in a pseudo manner by an area coverage modulation method by using two values of a maximum value and a minimum value that can be taken as the gradation value of the input image data (SsD0). |
| US09940863B2 |
Display device and method for driving the same
A display device according to example embodiments includes: a display panel including a plurality of pixels configured to display an image; a gamma voltage generator configured to generate a plurality of gamma sets respectively corresponding to a plurality of luminance ranges, and configured to compare a target luminance level with the luminance ranges to select a target gamma set among the gamma sets, and to generate a plurality of gamma voltages using the target gamma set, the target luminance level being a luminance level of the image; a first dimming controller configured to scale input image data based on the target luminance level; a second dimming controller configured to determine an off duty ratio of an emission signal based on the target luminance level; and a display panel driver configured to drive the display panel based on the input image data and the gamma voltages. |
| US09940858B2 |
System and method for assymetric rendering to eyes in augmented reality and virtual reality devices
A head-mounted display device including first and second display surfaces associated with first and second eyes of the user, a graphics processing unit, one or more hardware processors, and an adaptive rendering module. The adaptive rendering module is configured to identify a threshold frame time, the threshold frame time representing an upper threshold of time to render frame data by the GPU, receiving a first frame time associated with rendering a first frame to the first eye and second eye of the user, the first frame being rendered at a target resolution, determining that the first frame time exceeds the threshold frame time, and lowering the resolution below the target resolution for parts of a second frame associated with the first eye of the user while maintaining the resolution for parts of the second frame at the target resolution for images associated with the second eye of the user. |
| US09940850B1 |
Interactive fire safety education kit and associated use thereof
An interactive fire safety education kit includes a frame having a first section, a second section conjoined to the first section, and a third section conjoined to the second section. A first fire-simulating mechanism is rotatably coupled to the first section, a second fire-simulating mechanism adjustably coupled to the second section, and a third fire-simulating mechanism rotatably coupled to the third section. A flag and an associated mechanism are provided wherein the mechanism is capable of reciprocating the flag along a vertical path located adjacent to the third section as the third fire-simulating mechanism rotates in opposing rotational directions. A user interface is provided wherein the user interface is capable of generating an output that causes selective rotational displacement of the first fire-simulating mechanism, selective linear displacement of the second fire-simulating mechanism, and selective rotational displacement of the third fire-simulating mechanism, respectively. |
| US09940849B2 |
Advanced surgical simulation constructions and methods
A surgical simulation system is provided. The system includes at least one simulated body organ placed upon the base of an organ tray and at least one covering layer placed over the simulated body organ. At least one of the simulated body organ and covering layer includes electro-conductive gel that is operably severable under application of electrical current to simulate electrosurgery in a training environment. The training environment comprises a top cover connected to and spaced apart from a base to define an internal cavity that is partially obstructed from direct observation by a practitioner. The tray, simulated body organs and covering layer are placed inside the internal cavity for the practice of laparoscopic surgical procedures. |
| US09940844B2 |
Enhancing cognition in the presence of distraction and/or interruption
The present disclosure relates to methods and tools for enhancing cognition and improving well being in an individual. The methods involve presenting to an individual a task to be performed, presenting to the individual an interference, and receiving inputs from the individual. Where the interference is a distraction, the individual is to ignore the interference. Where the interference is an interrupter, the individual is instructed to respond to the interrupter as a secondary task and is considered to be multi-tasking. Inputs are then also received from the individual pertaining to this secondary task. The methods encompass iterations of these presenting steps and receiving of the input, and generation of analysis and/or feedback to the individual. The analysis can include a comparison of the performances with or without each type of interference. |
| US09940842B2 |
Intelligent drone traffic management via radio access network
Concepts and technologies disclosed herein are directed to intelligent drone traffic management via a radio access network (“RAN”). As disclosed herein, a RAN node, such as an eNodeB, can receive, from a drone, a flight configuration. The flight configuration can include a drone ID and a drone route. The RAN node can determine whether capacity is available in an airspace associated with the RAN node. In response to determining that capacity is available in the airspace associated with the RAN node, the RAN node can add the drone ID to a queue of drones awaiting use of the airspace associated with the RAN node. When the drone ID is next in the queue of drones awaiting use of the airspace associated with the RAN node, the RAN node can instruct the drone to fly through at least a portion of the airspace in accordance with the drone route. |
| US09940836B2 |
Estimating transit queue volume using probe ratios
Transit through an area by a population of travelers may be evaluated by a number of techniques, and may be useful for routing, transit time estimation, and transit control. Some techniques involve the use of probes, such as individuals or vehicles that are tagged and trackable through the area. However, estimating properties such as transit queue volume through probe counts may be difficult, as the ratio of probes to the overall population may vary. Presented herein are techniques for estimating transit properties by evaluating transit queues to estimate the probe ratio for an area. Such techniques involve counting and tracking the probes in a transit queue to estimate a queue length change of the transit queue, and a probe rate change of probes entering and exiting the transit queue. This information may inform estimates of the probe ratio, and in turn regional transit estimates, such as transit queue volumes. |
| US09940833B2 |
Method and system for lane-accurate determination of the travel direction of a vehicle and outputting warning messages in the case of wrong-way travel
A method for detecting the direction of travel of and for determining travel in the wrong direction by a vehicle which is moving on a lane in a section of road. Identifiers are respectively emitted by an arrangement of radio beacons which are arranged along the lane. When the vehicle travels through the section of road, a radio receiver, in particular a cell phone device, which is arranged in the vehicle, successively receives the emitted identifiers of the radio beacons. The actual direction of travel of the vehicle is determined on the basis of the sequence of the successively received identifiers. |
| US09940831B2 |
Pointing device and controlling method thereof
A pointing device and a controlling method thereof are provided. The controlling method of the pointing device includes transmitting an identification signal to an external device that is targeted by the pointing device according to a user input, receiving a reflected signal that is generated by reflecting the identification signal from a reflective surface attached to a surface of the external device, and analyzing the reflected signal and identifying the external device. |
| US09940826B1 |
Sensor data processing system for various applications
A data analysis system and approach having sensors, a collective processing mechanism connected to the sensors, and a threshold logic panel connected to the collective processing mechanism. Raw data from the sensors may be subject to collective processing and collective threshold logic analysis. The collective processing mechanism and the threshold logic panel may be situated outside of or in the cloud. Big data analytics may be performed on the data. The sensors may be homogeneous or heterogeneous. Consequently, there may be data fusion for false alarm reduction and advanced alarm detection, and application of big data analysis. Raw data may be used for determining positional information. |
| US09940825B2 |
Barometric pressure to reduce security false alarms
A security monitoring system includes at least one sensor configured to sense an event condition. A security monitoring system controller communicates with the sensor and an indicator of alarm and trouble conditions. The central security system also detects barometric pressure within a monitored area. The security system controller is configured to receive an event signal indicative of an event from the at least one of the sensors and receive an indication of the barometric pressure from a barometer. When the barometric pressure from the barometer indicates a change in barometric pressure, the security monitoring system controller confirms that the event is present and outputs an indication signal to the indicator based on the confirmed event. When the barometric pressure from the barometer does not indicate a change in barometric pressure, the security monitoring system controller suppresses the output of the indication signal. |
| US09940820B2 |
Systems and methods for verified threat detection
Systems and methods for verified threat detection are provided. Some systems can include a sensor monitoring an ambient region and an image capturing device, wherein, upon the sensor detecting an alarm condition in the ambient region, the image capturing device is activated for capturing an image of the ambient region to determine whether the image is consistent with the alarm condition. |
| US09940816B2 |
Parking brake warning system for air brakes
A warning system for vehicles equipped with air brakes is provided. The present invention provides one or more warning modules in connection with a low pressure switch and a door jamb switch to provide an alert if the driver fails to apply the parking brake and opens the vehicle door. A low pressure switch is connected to an air line controlled by a cabin parking brake switch. When the parking brake switch is toggled on, air is evacuated from the air line and the parking brakes are applied; the low pressure switch is then open. When the air line is pressurized, the parking brake switch is not toggled on and the parking brakes are not applied, causing the low pressure switch to close. If the door jamb sensor registers the driver door is open, the low pressure switch and door jamb sensor complete a circuit, activating the warning modules. |
| US09940815B1 |
Fluid leak detection alarm system
A system having a user configurable and sizeable planar sensor pad having electrical circuits thereon, adjacent to a trough or groove formed in the sensor pad. These circuits are energized upon the application of a conductive fluid into the trough and once activated initiates a wireless communication device to transmit an alarm to a mobile device of the user, such as a smart phone, alerting the user of the detected fluid leak. The device may be self contained, operating on its own DC power source and may not require the use of a computer, a WI-Fi signal, or the internet. |
| US09940812B2 |
Circuit protective device fault diagnostic translator
An apparatus (100) and method are provided for translating diagnostic information provided by a circuit protective device, such as a circuit breaker, to a graphic display format. The apparatus and method monitor through a sensor (120) a trip sequence implemented by the circuit protective device as a function of time during a read out operation to indicate a type of fault condition from a plurality of fault conditions for a prior occurrence of a trip event or diagnostic information. The apparatus and method then determine a time period of the monitored trip sequence, and determine the type of fault condition based on the determined time period. Information concerning the determined type of fault condition is outputted. |
| US09940810B2 |
Person support apparatuses with patient mobility monitoring
A person support apparatus, such as a bed, stretcher, cot, or the like, includes a fall detector. The fall detector is adapted to detect when a person associated with the person support apparatus has fallen and to issue a fall alarm. In some embodiments, the person support apparatus also includes an exit detection system that issues an exit alarm when the person exits from the person support apparatus. The fall alarm is given a higher priority than the exit alarm. The fall detector may include a camera, a thermal image sensor, a device worn by the person, or another sensor. The person support apparatus may also, or alternatively, include a timer for measuring how long an occupant remains out of the person support apparatus. |
| US09940806B2 |
Fire detection
A particle detection system including a particle detector in fluid communication with at least two sample inlets for receiving a sample flow from a monitored region. The particle detector includes detection means for detecting the level of particles within the sample flow and outputting a first signal indicative of the level of particles within the sample flow. A flow sensor is located downstream of the sample inlets for measuring the flow rate of the sample flow and outputting a second signal indicative of the flow rate of the sample flow. At least a first sample inlet is normally open to the monitored region for receiving at least part of the sample flow. At least a second sample inlet is normally closed to the monitored region but is openable to the monitored region in response to a change in environmental conditions in the monitored region. The particle detection system further includes processing means adapted for receiving the first and second signals and comparing the first signal to a predetermined threshold level and comparing the second signal to a predetermined threshold flow rate, and generating an output signal based on the respective comparisons of the first and second signals. A method of particle detection is also described. |
| US09940798B2 |
Alarm arming with open entry point
A magnet and magnetometer may be integrated into a smart home environment and allow it to be placed into an away mode of operation despite an entry point being semi-open. The disclosed implementations can detect a magnetic field strength and determine, based on the detected field strength, an approximate distance that a moveable partition is open. In some configurations, the presence of a second magnetic source can be detected. A notice may be generated based on one or more signals received from the magnetometer. The notice may be sent to a controller, a remote system, a remote device, and/or a client device as disclosed herein. |
| US09940785B2 |
Dynamic placement of in-game ads, in-game product placement, and in-game promotions in wager-based game environments
Various aspects are described herein for implementing in-game advertising, in-game product placement, and in-game promotion techniques in wager-based games conducted at an electronic gaming device of a casino gaming network. These techniques provide the ability for traditional video-type wager-based gaming machines (such as those deployed at casino gaming establishments) to be quickly and easily converted to wager-based games which support in-game advertising while still satisfying the strict regulatory compliance rules and regulations governing wager-based gaming. |
| US09940783B2 |
Automated hand strength estimation for card games
In various embodiments, a method of estimating odds that a player will win a round of a card game is disclosed. Information is received pertaining to cards that have been dealt from a deck at a particular point during a round of a card game. The information identifies cards that have been revealed to the player and a number of cards that have not been revealed to the player. An estimation of odds that the player will win the round of the card game is generated. The generating includes repeatedly, for each of the number of cards that has not been revealed to the player and for each remaining card to be dealt in the round, randomly selecting a card from remaining cards in the deck. The estimation of the odds is communicated for integration into a presentation of information pertaining to the card game. |
| US09940780B2 |
Variable payback gaming
A system for interactive gaming among a plurality of players includes a host computer system and a plurality of player terminals communicably coupled to the host computer system or gaming platform via a network. The plurality of player terminals may be located at a plurality of licensed gaming locations. The plurality of player terminals may be configured to engage the plurality of players in a common interactive game operated by the host computer system. The plurality of player terminals can include means for dispensing player winnings from the player terminal. |
| US09940779B2 |
Method and system for a card game variant of a community-style poker game
A card game that is a variant of a community card poker game is disclosed. The card game involves presenting a plurality of sets of hole cards to one or more players. One of the sets of hole cards includes at least one card being presented face down and at least one card being presented face up. The card game further includes receiving a hand bet made by a player on at least one of the sets of hole cards. Further, the card game includes presenting a plurality of community cards to the one or more players, and subsequently determining a highest-ranked poker hand for the game based on each of the sets of hole cards in combination with the community cards. |
| US09940777B2 |
Betting terminal and system
A system in a casino for playing a game, the system comprising: a network of betting terminals linked to a plurality of game tables, first players playing a first game at each of the game tables, at least one first game being a live baccarat game, wherein each of the betting terminals comprises a mechanism to display a plurality of first games occurring at the game tables in the casino so as to allow a second player at each one of the betting terminals to switch to different game tables, place bets at different first games at a same time, place a separate jackpot wager bet on a jackpot game based on the first games being played live at the game tables and select betting options, wherein the system includes a display part having a screen for showing game number and respective amounts available for betting. |
| US09940774B2 |
Multi-touch gesture gaming system and method
Various embodiments disclosed herein are directed to a multi-touch game play system that includes a display subsystem, a sensor subsystem, and one or more computing subsystems. The display subsystem is configured to display images related to one or more games to be played on at least a first game playing surface. The images include a virtual game layout having a number of demarcations of at least one area associated with the play of the one or more games. The sensor subsystem is configured to detect multiple touch gestures, wherein gestures include simultaneous touches by multiple fingers, consecutive touches by a single finger, touching and sliding of a finger, touching and sliding of multiple fingers, and combinations thereof. |
| US09940770B1 |
Coin machine using proximity and ambient light sensing technology
A coin acceptor includes main body having coin dispenser mounted therein, coin tubes mounted in the main body and disposed at the bottom side of the coin dispenser, and sensing device including multiple optical sensor modules respectively aimed at the coin tubes. The distance between each optical sensor module and the coins in the respective coin tube is calculated by: measuring the time taken for the reflected light to travel from the coins in the respective coin tube to the proximity sensor of the respective optical sensor module and then multiplying the time thus measured by the speed of light. The number of coins in each coin tube is calculated by: deducting the distance between the respective optical sensor module and the coins in the respective coin tube from the pre-measured depth of the empty coin tube, and then dividing the reminder thus obtained by the thickness of single coin. |
| US09940764B2 |
Key fob challenge request masking base station
A base station may include a transceiver, an indicator, and a processor programmed to detect presence of a key fob using one or more inputs. When the key fob is detected, the processor may direct the transceiver to broadcast an interference signal using the transceiver to prevent the key fob from detecting and responding to challenge requests and set the indicator to indicate presence of the broadcast. When an access request is received from a modem, using the transceiver the base station may temporarily discontinue broadcast of an interference signal to send a challenge request to the key fob and receive a challenge response, and send a response to the access request including information based on the challenge response. |
| US09940761B2 |
Self-driving vehicle sensor fault remediation
Methods, systems, and computer program products for self-driving vehicle sensor fault remediation are provided herein. A computer-implemented method includes detecting a fault in one or more sensors of a self-driving vehicle; determining a remedial action in response to the detected fault, wherein said determining comprises (i) comparing the fault to a database comprising (a) historical sensor fault information and (b) sensor fault remedy information, and (ii) analyzing one or more items of contextual information pertaining to the location of the self-driving vehicle; generating a signal comprising one or more instructions pertaining to carrying out the determined remedial action; and outputting the generated signal to one or more remote-controlled pilotless airborne devices configured to remotely carry out the determined remedial action on the self-driving vehicle. |
| US09940760B2 |
System and method for facilitated collaboration between automotive mechanics
A method for facilitating communication for diagnosis of automotive repair issues includes retrieving diagnostic data from a first processor in a first vehicle using a first diagnostic tool, and transmitting the diagnostic data to a server with a request for assistance from a first user who operates the first diagnostic tool. The server identifies a second user who has received diagnostic data from a second processor in a second vehicle with a second diagnostic tool that corresponds to the diagnostic data retrieved by the first processor in the first vehicle, and the server transmits a communication notification to an electronic communication device that is associated with the second user to establish a communication channel between the first user and second user regarding the vehicle issue. |
| US09940757B2 |
Modifying a simulated character by direct manipulation
A portion of a simulated element of a graphical simulation available for modification is identified in view of a cursor location associated with a user input device. The identified portion of the simulated element is selected for modification. The selected portion of the simulated element is then modified according to a direct manipulation of a display of the selected portion of the simulated element by a user using the user input device. |
| US09940756B2 |
Silhouette-based object and texture alignment, systems and methods
An object-image alignment data generating method for use in an object recognition system is presented. The method obtains a 3D model and a set of 2D images of the object. Each 2D image from the set is captured based on a particular camera point of view. The method then uses the 3D model of the object to generate multiple silhouettes of the object according to different camera point of views. Each silhouette is then matched and aligned with a 2D image based on the corresponding camera point of view. The method also derives at least one descriptor from the 2D images and compiles feature points that correspond to the descriptors. Each feature point includes a 2D location and a 3D location. The method then generates an object-image alignment packet by packaging the 2D images, the descriptors, and the feature points. |
| US09940752B2 |
Hybrid reality based object interaction and control
The present disclosure discloses a system and method for real time interaction of a real world with a virtual world through an augmentation concept has been provided. The system includes a mobile electronic device compatible with all operating system. The mobile electronic device is having a virtual reality application, on running the application and mounting the mobile electronic device in a virtual reality platform, the display provides two scenes. First scene is a menu scene and the second scene provides stereoscopic image with wide field view in a virtual environment. The system captures a real time image and scans characteristics of IoT based devices. Based on movement of virtual reality platform, the system provides guidance to perform actions on the IoT based devices from the virtual environment. |
| US09940750B2 |
System and method for role negotiation in multi-reality environments
Provided herein are methods and systems for role negotiation with multiple sources. A method for role negotiation can comprise rendering a common field of interest that reflects a presence of a plurality of elements, wherein at least one of the elements is a remote element located remotely from another of the elements. A plurality of role designations can be received, each role designation associated with one of a plurality of devices, wherein at least one of the plurality of devices is a remote device located remotely from another of the plurality of devices. The common field of interest can be updated based upon the plurality of role designations, wherein each of the plurality of role designations defines an interactive functionality associated with the respective device of the plurality of devices. |
| US09940744B2 |
Remote font management
Remote font management techniques are described. In one or more implementations, one or more layout tables are obtained, located remotely via a network by a computing device, that correspond to a font associated with a request to output text using the font. A layout and glyph dependencies of the text is generated by the computing device using the obtained one or more layout tables to identify glyphs that are involved in an output of the text. The identified glyphs are obtained by the computing device from a font file located remotely from the computing device via the network and the text is rendered by the computing device using the obtained glyphs. |
| US09940741B2 |
Delay coordinate analysis of periodic data
Periodic data is analyzed by obtaining a vector of delay coordinates for each one of a plurality of samples of the periodic data in a time window, and transforming each of the vectors into a coordinate system comprising a plurality of predefined vectors, to obtain a projection of an attractor of the periodic data along one of the predefined vectors. The periodic data may be physiological data. Information representing one or more characteristics of the obtained attractor, which is of diagnostic value, is then displayed to enable a diagnosis. |
| US09940737B2 |
Analyzer, analysis method and analysis program of bone mineral density
To make a user easily obtain an objective and stable analysis result of bone mineral density. An analyzer 100 of bone mineral density using CT image data of a phantom having a known bone mineral density includes: a known data storage part 105 that stores known data of bone mineral density for a phantom; a histogram production part 102 that produces a histogram of region number relative to a CT value for three-dimensional CT image data of the phantom; a correspondence determination part 106 that determines correspondence between a CT value and a bone mineral density by correlating CT values showing respective peaks of the produced histogram with the known data of the phantom; and an analysis part 109 that decides a bone mineral density for three-dimensional CT image data of a subject using the determined correspondence. |
| US09940732B2 |
Implementing reduced video stream bandwidth requirements when remotely rendering complex computer graphics scene
A method and apparatus are provided for implementing reduced video stream bandwidth requirements when remotely rendering a complex computer graphics scene. Complexity of a scene is reduced at a server, prior to rendering a video stream that comprises the scene and transmitting the video stream to a client. Reducing the complexity of a scene at the server includes adjusting predefined scene configuration parameters. The order and degree to which predefined scene configuration parameters are adjusted is based upon a required stream bandwidth reduction to be made. |
| US09940731B2 |
Unsupervised asymmetry detection
Asymmetries are detected in one or more images by partitioning each image to create a set of patches. Salient patches are identified, and an independent displacement for each patch is identified. The techniques used to identify the salient patches and the displacement for each patch are combined in a function to generate a score for each patch. The scores can be used to identify possible asymmetries. |
| US09940730B2 |
Methods and systems for automatic fullness estimation of containers
A method and apparatus for (a) receiving a three-dimensional (3D) point cloud from a depth sensor that is oriented towards an open end of a shipping container, the point cloud comprising a plurality of points that each have a respective depth value, (b) segmenting the received 3D point cloud among a plurality of grid elements, (c) calculating a respective loaded-container-portion grid-element volume for each grid element, (d) calculating a loaded-container-portion volume of the shipping container by aggregating the calculated respective loaded-container-portion grid-element volumes, (e) calculating an estimated fullness of the shipping container based on the loaded-container-portion volume and a capacity of the shipping container; and (f) outputting the calculated estimated fullness of the shipping container. |
| US09940727B2 |
Three-dimensional modeling from wide baseline range scans
The present disclosure describes systems and techniques relating to generating three dimensional (3D) models from range sensor data. According to an aspect, frames of range scan data captured using one or more three dimensional (3D) sensors are obtained, where the frames correspond to different views of an object or scene; point clouds for the frames are registered with each other by maximizing coherence of projected occluding boundaries of the object or scene within the frames using an optimization algorithm with a cost function that computes pairwise or global contour correspondences; and the registered point clouds are provided for use in 3D modeling of the object or scene. Further, the cost function, which maximizing contour coherence, can be used with more than two point clouds for more than two frames at a time in a global optimization framework. |
| US09940721B2 |
Scene change detection in a dimensioner
A package dimensioner is disclosed. A change in the pose of the package dimensioner is detected by background modeling the area of a measurement platform and then determining if a number of points in a scene are different in distance from the background model. Change in the pose can also be detected by comparing a count of support points in a 3D container generated from images taken in a training process with a count of support points in a subsequent images and determining how many support points are different. |
| US09940720B2 |
Camera and sensor augmented reality techniques
Camera and sensor augmented reality techniques are described. In one or more implementations, sensor data is obtained from a sensor of a hardware device, the sensor data being associated with the hardware device that is located in an environment, such as in three-dimensional (3D) space. Images of the environment are captured with at least one camera of the hardware device. A position of the hardware device in the environment can then be determined based on at least one of the sensor data and the images of the environment. Further, an orientation of the hardware device in the environment can be determined based on at least one of the sensor data and the images of the environment. |
| US09940717B2 |
Method and system of geometric camera self-calibration quality assessment
Techniques related to geometric camera self-calibration quality assessment. |
| US09940708B2 |
Systems and methods for double pulsed diffusional kurtosis imaging
One aspect of the present disclosure relates to a system that can perform double pulsed diffusional kurtosis imaging (DP-DKI). Image data can be received. The image data can be acquired using a double pulsed field gradient (d-PFG) diffusion sequence. A six dimensional (6D) diffusional kurtosis for the image data can be determined. A magnitude of the image data can be determined in terms of the 6D diffusional kurtosis. DP-DKI can isolate the contributions to the d-PFG diffusion sequence, which can represent leading diffusion effects, that cannot be seen from single pulsed field gradient (s-PFG) diffusion sequences. |
| US09940707B2 |
Systems and methods for assessing images
Disclosed are systems and methods for assessing images in applications such as microscopic scanning of a slide having light emitting objects. In certain embodiments, such scanning can involve objects such as sequencing beads disposed on the slide to facilitate biological analysis such as nucleic acid sequencing. Also disclosed are certain embodiments where images of light emitting objects are assessed for image quality so as to facilitate a feedback response such as a corrective action. In certain embodiments, such assessment and correction can be performed in real-time during the scanning process, and can include re-acquisition of the assessed image. Also disclosed are certain embodiments where such assessment and correction can be triggered dynamically during the scan, or before start of the scan, so as to enhance the scanning performance, including scanning time and throughput. |
| US09940704B2 |
Pre-layer defect site review using design
A system and method to image a layer of a wafer based on a coordinate of a defect in a pre-layer of the wafer are disclosed. A design file for the current layer can be aligned to the wafer using an image of the current layer. A design file for a previous layer can be aligned to the design file for the current layer. |
| US09940703B2 |
Method of measuring a property of a target structure, inspection apparatus, lithographic system and device manufacturing method
A property of a target structure is measured based on intensity of an image of the target. The method includes (a) obtaining an image of the target structure; (b) defining a plurality of candidate regions of interest, each candidate region of interest comprising a plurality of pixels in the image; (c) defining an optimization metric value for the candidate regions of interest based at least partly on signal values of pixels within the region of interest; (d) defining a target signal function which defines a contribution of each pixel in the image to a target signal value. The contribution of each pixel depends on (i) which candidate regions of interest contain that pixel and (ii) optimization metric values of those candidate regions of interest. |
| US09940702B1 |
Delayed petroleum coking vessel inspection device and method
This invention comprises a system and a method for inspecting the inside of delayed petroleum coking vessels to identify deformations, detect and determine the severity of other defects, and visually observe the inside of the inspected vessel. |
| US09940699B2 |
Image processing apparatus capable of appropriate image conversion in all regions of an image in image transformation processing
A projection conversion coefficient acquirer of an image processing apparatus acquires the same number of projection conversion coefficients, which are coefficients for doing projection conversion of an image, as the number of a plurality of reference points at differing positions in the image. A post-projection-conversion image acquirer does projection conversion on the image through each of the projection conversion coefficients, of which there are the same number as the number of the plurality of reference points acquired by the projection conversion coefficient acquirer, and acquires a plurality of post-projection-conversion images from the image, the number of the post-projection-conversion images being the same as the number of reference points. A weighted averager finds a weighted average for each of the coordinates of pixels comprising the plurality of post-projection-conversion images, using a plurality of weightings determined in accordance with distance from the plurality of reference points in the image. A weighted average image acquirer acquires a weighted average image in which the plurality of post-projection-conversion images have undergone weighted averaging by the weighted averager. |
| US09940695B2 |
Method for ensuring perfect stitching of a subject's images in a real-site image stitching operation
The present invention is to provide a method for ensuring perfect stitching of a subject's images in a real-site image stitching operation, which enables an electronic device to read two real-site images which are taken respectively of different parts of the same site and each of which has an overlap area of a common subject; to determine and choose an optimal stitching path bypassing the subject; to construct a mask diagram such that, within a difference diagram of the overlap areas, the farther a pixel on one side of the optimal stitching path is from the optimal stitching path, the greater the pixel's value, and the farther a pixel on the other side of the optimal stitching path is from the optimal stitching path, the smaller the pixel's value; and to stitch and fuse the overlap areas together through a fusion algorithm, with the mask diagram serving as a weight. |
| US09940692B2 |
Augmented reality overlays based on an optically zoomed input
A method for managing a content overlay. The method included a processor identifying a first image and a second image from an augmented reality (AR) device. The method further includes identifying a first element of interest within the first image. The method further includes associating a corresponding first AR content overlay for the first element of interest. The method further includes determining one or more differences between the first image and the second image, wherein the second image includes at least the first element of interest. The method further includes modifying a position of at least the first AR content overlay based, at least in part, on the one or more differences between the first image and the second image. |
| US09940689B2 |
Latency-resistant sparse simulation technique, system and method
A Central Processing Unit (CPU), system and method of performing a Graphics Processing Unit (GPU) simulation of a fluid-like object in a grid-based simulation space are provided. In one embodiment, the method includes: (1) determining, by a CPU, a list of bricks in the simulation space that the fluid-like object would occupy in a future frame based on simulation data of a current frame and (2) updating, based on the list, a virtual table that maps portions of a GPU memory to tiled resources corresponding to the bricks before a simulation of said future frame. |
| US09940687B2 |
Dynamic graphics rendering scheduling
Aspects can be for ray tracing of 3-D scenes, and include dynamically controlling a population of rays being stored in a memory, to keep the population within a target, a memory footprint or other resource usage specification. An example includes controlling the population by examining indicia associated with rays returning from intersection testing, to be shaded, the indicia correlated with behavior of shaders to be run for those rays, such that population control selects, or reorders rays for shading, to prioritize shading of rays whose shaders are expected to produce fewer rays. |
| US09940686B2 |
Exploiting frame to frame coherency in a sort-middle architecture
Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame. |
| US09940683B2 |
Managing a risk of a liability that is incurred if a subject treated for a condition is retreated within a specified time period
An embodiment of a risk-management method includes determining a risk that a subject treated for a condition will be retreated within a time period, and calculating, in response to a determined risk, a fee for taking an action if the subject is retreated within the time period. For example, such an embodiment may aid in managing a risk of a liability that may be incurred if a subject treated for a condition is retreated for the condition, for a complication arising from the condition or from the treatment of the condition, or for another reason, within a specified retreatment time period. |
| US09940677B2 |
System and method for detecting potential property insurance fraud
A system and method for assessing a condition of property for insurance purposes includes a sensor for acquiring a spectral image. In a preferred embodiment, the spectral image is post-processed to generate at least one spectral radiance plot, the plot used as input to a radiative transfer computer model. The output of the model establishes a spectral signature for the property. Over a period of time, spectral signatures can be compared to generate a spectral difference, the spectral difference can be used to determine whether a change in the condition of the property was potentially fraudulently caused. |
| US09940672B2 |
System for generating data from social media messages for the real-time evaluation of publicly traded assets
A system for generating data from social media messages for the real-time evaluation of publicly traded assets includes an ingest component for ingesting the social media messages and a filter module eliminating expressions not considered useful language from social media messages and configuring input social media message into useful formats to form filtered social media messages. The system also includes a language processor processing the filtered social media messages based upon lexical databases to form filter and processed social media messages. The system further includes a sentiment calculator applying rules to the filtered and processed social media messages so as to compute a representation of sentiment values associated with the social media messages. A graphical user interface displaying the sentiment values is also provided. |
| US09940668B2 |
Switching between data aggregator servers
Switching between data aggregator servers. A method for switching between data aggregator servers may include tracking a first financial account using a PFM server, receiving, at the PFM server, first account identification data and first account transaction data for the first financial account from a first data aggregator server over a network, detecting, at the PFM server, that the first account transaction data of the first data aggregator server has become unavailable to the PFM server over the network and that a second data aggregator server is currently available to the PFM server over the network, and in response to the detecting, switching, at the PFM server, from the first data aggregator server to a second data aggregator server, the second data aggregator server configured to send data for the same financial accounts with different data fields and/or with different data formats than the first data aggregator server. |
| US09940667B2 |
Volume control for mass quote messages
Systems and methods are provided for processing mass quote messages and generating market data. A mass quote message is received and individual orders are parsed and processed. Individual market data messages are stored in a market data message buffer. After all orders are processed, the contents of the market data message buffer is distributed as a single market data message. |
| US09940665B1 |
System and method for providing virtual items to users of a virtual world
A shop interface is presented to users in conjunction with presentation of views of an online game, wherein the shop interface is configured to facilitate presentations to users of offers to sell virtual items usable within the game in exchange for consideration. In response to detecting that the online game is systematically unavailable to users, an alternative virtual shop interface is presented to users that is accessed over the Internet separately from the online game, and offers to sell the virtual times usable within the game are presented to users in exchange for less consideration than the offers to sell the virtual items through the shop interface presented in conjunction with the online game. |
| US09940664B2 |
Information input method, account information input method and terminal
An electronic device for receiving an account identifier is described. The device includes display; one or more processors; and memory storing one or more programs. The device displays a user interface that includes an area for receiving an account identifier and a first set of candidates for a first set of characters. The device detects a selection of a first candidate of the first set of candidates. In response, the device displays characters in the first candidate in the area. The device, subsequent to detecting the selection of the first candidate, receives a manual input of each character in one or more sets of characters; and displays, in the area, characters in the one or more sets of characters concurrently with at least the characters in the first candidate. A corresponding method and a computer readable storage medium storing one or more programs for execution by the electronic device are also described. |
| US09940663B2 |
Indoor location mapping and wayfinding system
An Indoor location mapping and wayfinding system for mapping waypoints on an interactive mapping system that can function both indoors and outdoors based on user selections and location. It can include a shopping system that allows users to pre-select items for purchase, maps the items on an indoor map of the store, and provides a route to the user for the collection of the selected items. |
| US09940659B1 |
Category preferred layout for items in an electronic marketplace
Techniques for determining and providing a preferred layout of a network page may be provided. For example, the system may receive a query with a keyword, access data regarding previous users' interactions associated with the results of the keyword, determine a category associated with the interactions, and provide a display (e.g., on the original network page) for that particular category. In some examples, the system may provide generic network pages and item- or category-specific network pages associated with a particular layout or presentation characteristics. The system can identify the presentation characteristics of the category-specific network page and incorporate them with the generic network page, without redirecting the user to the category-specific network page. |
| US09940654B1 |
Network system with scheduled breaks
A method and system for scheduled breaks are described. A network computer system receives provider data corresponding to a request to initiate a pause state with the network service and also receives a position of the service provider from a computing device equipped with a location-based resource. In response to receiving the request, the network computer system selects a facility, based on a selection objective, from facilities that are associated with the pause state and at least one of the position of the service provider and a destination of a service task that is to be completed. The network computer system transmits data corresponding to the selected facility to the computing device to be displayed on a user interface of the computing device. |
| US09940651B2 |
Selecting vehicle type for providing transport
A transport arrangement system operates to receive a transport request from a user, and to make a selection of a vehicle type for the user based at least in part on a set of criteria associated with the transport request or user information. For example, the determination of whether an autonomous vehicle is to be provided can be based at least in part on the destination specified with the transport request. |
| US09940649B2 |
System and method for integrating retail price optimization for revenue and profit with business rules
The disclosed technology improves the process of generating recommended prices for retail products by optimizing revenue and profit while complying with a set of business rules by assigning a monetary value to each business rule. Then for each decision price that violates a business rule constraint, a penalty value is added to the monetary value. If the monetary value including the penalty is better than an original monetary value, the decision price is included in the recommended prices. |
| US09940648B2 |
Managing ephemeral locations in a virtual universe
Systems and methods for advertising, and, more particularly, systems and methods for managing ephemeral locations in a virtual universe. A method for managing ephemeral locations in a virtual universe (VU) includes causing a computer infrastructure to: render an ephemeral location upon a triggering in the VU; teleport a VU user avatar to the ephemeral location; permit the user avatar to interact in the ephemeral location; teleport the user avatar out of the ephemeral location; and un-render the ephemeral location. |
| US09940645B1 |
Application installation using in-video programming
A method for delivering and installing applications on user devices includes providing a video and a video annotation for display on a first user device, the video annotation comprising an identifier of a mobile application. The method further includes receiving, by a processing device, an indication of a user selection of the video annotation, the indication of the user selection of the video annotation corresponding to a signal to install the application on the first user device; and causing the application to be remotely installed on the user first device. |
| US09940644B1 |
Multimedia product placement marketplace
A multimedia product placement marketplace is provided. A media player presents primary media content received over a first channel. A media component presents auxiliary media content received over a second channel, and selects a portion of an auxiliary media content related to the primary media content, which may have been presented by the media player during a previous time period. If the selected portion of the auxiliary media content is associated with at least one item of information, the media component receives the information over a second channel, and displays the received information via a user interface on the handset. The received information includes a link to a commerce server that provides a commercially available product and/or a commercially available service related to the selected portion of the auxiliary media content to enable a transaction. The link may be based on a highest value bid within a period of time. |
| US09940642B1 |
Electronic real estate access system
A system for providing physical access to a building that is for sale, lease, or rent is described. The system includes a server, a remote device located at the building that prohibits access to the building, and a handheld device. The handheld device transmits location information for the handheld device and identification information to the server. The server identifies the building based on the location information and transmits marketing information for the building to the handheld device. The device displays the marketing information and transmits a request for access to the building, the request transmitted to the server. The remote device is configured to provide access to the building when the remote device receives an access signal from the server or from the handheld device. The access signal is sent from the server based on confirmation of the location information for the handheld device and confirmation of the identification information. |
| US09940640B2 |
Automated event correlation to improve promotional testing
Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables on purposefully segmented subpopulations. The plurality of test promotions automatically account for covariates. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate general public promotion. |
| US09940639B2 |
Automated and optimal promotional experimental test designs incorporating constraints
Methods and apparatus for implementing forward looking optimizing promotions by administering, in large numbers and iteratively, test promotions formulated using highly granular test variables and automatically incorporating constraints on segmented subpopulations. The responses from individuals in the subpopulations are received and analyzed. The analysis result is employed to subsequently formulate a general public promotion. |
| US09940637B2 |
User interface for loyalty accounts and private label accounts
The present disclosure generally relates to the use of loyalty accounts, private label payment accounts, and general payment accounts using an electronic device with an electronic wallet. Various accounts are linked to the electronic device. In some examples, the electronic device is NFC-enabled. The electronic device may be used to provide loyalty account information and payment account information to a payment terminal, such as an NFC-enabled payment terminal. |
| US09940634B1 |
Content consumption monitor
A content consumption monitor (CCM) generates intent data that identifies topics of real-time interest to users. The CCM uses the intent data to direct information to more interested audiences and reduce the information noise/overload that may prevent users from viewing information. This targeted information may increase user conversion rates for seminars, advertising, documents downloads, or any other activity associated with published information. In one example, the CCM generates the intent data from third party content. Using a wide variety of third party content enables the CCM to better identify current user interests. The CCM may aggregate the intent data for different demographics, such as for companies, job positions, age, gender, or geographic locations. |
| US09940633B2 |
System and method for video-based detection of drive-arounds in a retail setting
A system and method for detection of drive-arounds in a retail setting. An embodiment includes acquiring images of a retail establishment, analyzing the images to detect entry of a customer onto the premises of the retail establishment, tracking a detected customer's location as the customer traverses the premises of the retail establishment, analyzing the images to detect exit of the detected customer from the premises of the retail establishment, and generating a drive-around notification if the customer does not enter a prescribed area or remain on the premises of the retail location for at least a prescribed minimum period of time. |
| US09940632B2 |
Real-time broadcast content synchronization database system
In response to a track playing on a broadcast radio station, the corresponding artist name is used as a key to access a database of artist messages, news and events information associated with that artist, that may be automatically distributed and geo-targeted while the track is playing. Distribution of the supplemental artist-related content extends to the radio broadcast—via RDS and HD, to the Internet, social media and various mobile devices. The supplement content may comprise messages pre-programmed by the artist, agents, or music labels. The supplemental content may be geo-targeted to include local tour dates, media appearances, related news, album releases and other data tied to the artist's song that is playing on the radio or on a streaming application. Further, the system may feed messages directly from the artist's existing social platforms, to provide further engagement of listeners while the track is playing. |
| US09940630B2 |
Systems and methods for delivering tailored content based upon a consumer profile
The present disclosure includes a system, method, and article of manufacture for aggregating a consumer profile, identifying tailored content (e.g., in response to a trigger event and/or based upon a consumer profile), and/or tailoring a digital destination. For example, the systems may receive direct data indicating an interest in receiving specific content, aggregate that data into a consumer profile, compare the consumer profile to content, and/or identify tailored content based upon the comparison. Further, the systems may communicate the tailored content to a web client associated with a consumer, receive a transaction request from a web client, and/or receive bids associated with tailored content. In addition, these systems may prioritize tailored content comprising a plurality of tailored offers and/or forecast a budget for an upcoming experience. |
| US09940629B2 |
Personalizing digital gifts
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for gifting and personalizing a digital media item, particularly an electronic book. A system is described that includes personalizing a digital media item that is to be gifted from a first person to one or more people. The digital media item can be personalized using a segment of the digital media item that the first person associated with the second person. Depending on the second person's response, the gift can be accepted, rejected, or re-gifted. News of the second person's response can be automatically transmitted to a plurality of social networking services. |
| US09940623B2 |
Method and system for facilitating payments on a payment card network
A computer implemented method of processing a payment request is provided, the method comprising operating a processor of a network node to: (i) determine that a current time is within a predefined period of a payment time associated with a payment profile; (ii) determine an account number, a payment amount and a payment provider associated with the payment profile; (iii) transmit to the payment provider a request for pre-authorization of payment of the payment amount from an account associated with the determined account number; and (iv) responsive to receiving a pre-authorization from the payment provider, associating an authorization indication with the payment profile. |
| US09940621B2 |
Method and system using candidate dynamic data elements
A method and computer readable medium for conducting a transaction, comprising receiving a verification value and a portion of a dynamic data element, determining candidate dynamic data elements using the portion of the dynamic data element, calculating candidate verification values using candidate dynamic data elements, and determining if the received verification value matches any of the candidate verification values, wherein the transaction is thereafter authenticated if a candidate verification value matches a candidate verification value. |
| US09940618B2 |
Method and apparatus for transmitting wallets between mobile devices
A method of and apparatus for transmitting data of a terminal which includes a wallet application used for a commercial transaction service is provided. The method includes determining wallet data which comprise payment information and non-payment information provided by the wallet application, which is able to be transmitted, and a scheme of transmitting the wallet data; notifying a receiving terminal of a transmission of the wallet data according to input transmission information; transmitting the wallet data to the receiving terminal based on the transmission method, after receiving an acceptance message from the receiving terminal; and updating information of the wallet data, which is transmitted to the receiving terminal, based on preset regulation information. The apparatus includes a wallet transmission and reception unit and a wallet management unit. |
| US09940615B2 |
Automated pairing of payment products and mobile to mobile devices
A computer receives card transaction data in response to a transaction using a financial services card. The card transaction data identifies at least a location, date, and time associated with the transaction. Upon receiving the card transaction data, the computer compares the card transaction data with telematics information associated with a vehicle equipped with a telematics device. The telematics information identifies at least a location of the vehicle, and a time and date associated with the location of the vehicle. On the basis of the comparison, the computer determines if the location of the transaction substantially matches the location of the vehicle at the time and date of transaction. Responsive to determining a substantial match, the computer associates the financial services card with the vehicle. |
| US09940613B2 |
Wireless service provider system and method for activating and selling a wireless service on a wireless device
A wireless service provider system and associated methods of using the system for the sale and/or activation of wireless services is disclosed. The system includes a communication interface for a wireless device having a unique identifier. A backend system computer of the wireless service provider system can receive a unique identifier corresponding to the wireless device; authorize the activation of the wireless service corresponding to the unique identifier of the wireless device; and record, in a database, the authorized unique identifier to improve a user's experience and ease of activation/provisioning of services for the wireless device. |
| US09940609B2 |
Systems and methods for point of sale deposits
The disclosed embodiments include systems and methods for executing a point of sale deposit. In one embodiment, a system may include one or more memory devices storing software instructions, and one or more processors configured to execute the software instructions to receive transaction information related to a point of sale deposit from a client device, and generate a pending deposit transaction based on the transaction information. The one or more processors may be further configured to execute the software instructions to receive a first transaction token from the client device, receive a second transaction token from a third-party device, match the first transaction token to the second transaction token, and complete the pending deposit transaction based on the match. |
| US09940606B2 |
Correlating jobs with personalized learning activities in online education platforms
Employers or recruiters populate an online database with job postings. The concepts that job applicants need to have learned to be successful applicants for a job are stated or inferred from the job posting and optionally resumes of others who have held that job. A student's own learning activities are logged by an online education platform. From a comparison between the student's completed learning units and a job posting's required learning units, a personalized learning unit gap can be identified for a student. The online education platform can then recommend how the student can fill the gap by undertaking the study of learning units on the education platform. |
| US09940602B1 |
Item purchase, redemption and delivery including user-defined parameters
Systems and methods including techniques for allowing users of an electronic marketplace to create “Giveaways” on the electronic marketplace are described. For example, a user (“host”) can purchase a certain number of items using the electronic marketplace, and set parameters for others to redeem or claim those items. The electronic marketplace charges the host for the items and other estimated costs, reserves the requested number of items, and sets up a redemption site through which other individuals can claim the items according to the parameter(s) set by the host. The electronic marketplace may validate winners of the giveaways by confirming user identities, addresses, etc., using their own user database. When items are claimed, actual costs, such as shipping, taxes, etc., may be calculated, and the electronic marketplace can send a refund to the host for any overcharges, as well as any unclaimed items. |
| US09940599B2 |
Systems and methods for generating solution recommendations for power plant operation
Systems and methods for generating solution recommendations for power plant operation can be provided by certain embodiments of the disclosure. In one embodiment, a system may include a processor configured to collect power plant operational data from power plant components. The power plant operational data may be analyzed to identify cost factors for the power plant components. Based at least in part on the power plant operational data and the cost factors, upgrade opportunities for the power plant components may be determined. Financial values may be calculated for the upgrade opportunities. Based at least in part on the financial values, recommendations may be generated using a product interaction database and provided as an electronic output to a user. |
| US09940597B2 |
Executing a business process by a standard business process engine
Executing a business process can include providing a context data object including a payload data structure for storing a payload data and automatically splitting an annotated context data object into one or more utility data objects. Responsive to creating a second utility data object, a pre-processing task can be injected into the business process, the pre-processing task using a copy of a first mapping to read data from the predefined data structure instance and to store the read data as payload data in the payload data structure of the first utility data object. Responsive to creating a third utility object, a post-processing task can be injected into the business process. The post-processing task can use a copy of the second mapping to write the payload data of the first utility data object to elements of a predefined data structure instance. |