最新美国发明专利第2018-02-20期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US09899669B2	Structures for interdigitated finger co-extrusion An electrode structure has an interdigitated layer of at least a first material and a second material, the second material having either higher or similar electrical conductivity of the first material and being more ionically conductivity than the first material, a cross-section of the two materials being non-rectangular.
US09899668B2	Method of preparing positive active material for rechargeable lithium battery, positive active material for rechargeable lithium battery prepared by method, and rechargeable lithium battery including same Disclosed is a method of preparing a positive active material for a rechargeable lithium battery that includes mixing an iron source including a carbon source, a lithium source, and a phosphoric acid source to form a positive active material precursor for a rechargeable lithium battery, the positive active material precursor including a lithium iron phosphate precursor and a carbon precursor; pulverizing the positive active material precursor for a rechargeable lithium battery; and heat-treating the pulverized positive active material precursor for a rechargeable lithium battery.
US09899662B2	Method for producing electrodes for all-solid battery and method for producing all-solid battery Disclosed herein is a method for producing an electrode includes a step of reducing lithium-vanadium oxide by heating in reducing gas, a step of causing the reduced lithium-vanadium oxide to deliquesce, a step of mixing the deliquesced lithium oxide with an active material so as to prepare an electrode mixture, and a step of making the electrode mixture into an electrode by virtue of molding after heat treatment to the electrode mixture. The method for producing an all-solid battery further includes a step of bonding the thus-made electrode to a solid electrode layer in such a way that the solid electrode layer is interposed between the electrode and either of cathode and anode to be paired with the electrode.
US09899658B2	High current battery pack fusing system A high current fuse with a short time constant is provided for use in an electric vehicle. The fuse is designed to exhibit thermal characteristics that are similar if not substantially identical to those of the wire bond interconnects used in the vehicle's battery pack. As a result, the system does not go into an overheat protection condition when the system is subjected to repetitive high current cycles, such as those common during aggressive and/or spirited driving.
US09899657B2	Current interruption device and electrical energy storage device using the same A current interruption device includes a first conductive member, a second conductive member, a first deformable member, and a second deformable member. The first conductive member is fixed to a casing. The second conductive member is disposed at a position opposed to the first conductive member. The first deformable member is in contact with the second conductive member when pressure in the casing is equal to or less than a predetermined value. Further, the first deformable member is brought out of contact with the second conductive member when the pressure in the casing exceeds the predetermined value. A plastic deformation portion deformed in a manner of projecting toward the second conductive member is provided on a center portion of the second deformable member.
US09899655B2	Electrochemical current collector screen designs utilizing ultrasonic welding An electrochemical cell comprising an electrode assembly having a plurality of cathodes in which the plurality of cathodes is electrically connected together at a connection tab junction is disclosed. The junction preferably comprises a plurality of cathode connection tabs that are folded over each other to construct a junction that is mechanically and electrically robust. The junction is comprised of a plurality of connection tabs that each extend from a cathode. Each of the respective tabs is folded over each other to form a compact electrode junction having redundant connections. An elongated lead extends from the junction to provide an electrical connection to the plurality of cathodes. The junction is welded together such as by a laser, resistance or ultrasonic weld joint. The cathode junction is suitable for either primary or secondary cells, particularly those powering implantable biomedical devices.
US09899654B2	Metal-air battery In a metal-air battery (1), an interconnector (24) formed of ceramic having alkali resistance is provided on the surface of a porous positive electrode layer (2) on the side opposite to the surface that is in contact with an electrolyte layer (4). A liquid repellent layer (29) having liquid repellency to an electrolyte solution is further provided on the surface of the positive electrode layer (2) on which the interconnector (24) is formed, and covers this surface along with the interconnector (24). The metal-air battery (1) using an alkaline electrolyte solution can thus easily prevent leakage of the electrolyte solution by the interconnector (24) and the liquid repellent layer (29) while suppressing degradation of the interconnector (24).
US09899648B2	Battery holder and isolation assembly A battery holder for securing a battery to a vehicle and for mechanically isolating the battery from the vehicle is provided. The battery holder includes a vehicle mounting plate, a lower battery containment plate, an upper battery containment plate, a number of spacer rods, and a number of shock absorbing elements. The lower battery containment plate and the upper battery containment plate secure the battery to the shock absorbing elements. The shock absorbing elements prevent vibrations and shocks from being transferred from the vehicle to the battery.
US09899647B2	Onboard power supply apparatus An onboard power supply apparatus includes: power storage modules each including power storage devices; a pair of brackets configured to come into contact with respective ends of the power storage modules vertically stacked so as to fix at least an upper power storage module to a vehicle; and an insertion portion that is disposed between at least one of the pair of brackets and an end of one of the power storage modules located between terminal portions of the vertically stacked power storage modules, a connecting member used for connecting the terminal portions of the vertically stacked power storage modules being inserted in the insertion portion.
US09899646B2	Battery module having battery guiding portions A battery module includes a battery group configured of a plurality of cylindrical batteries, a holder configured to retain the battery group so that the respective batteries are bundled in parallel to each other, and a casing being closed by the holder and including a storing space for housing the battery group. The casing includes an opposing wall portion facing the holder, and the opposing wall portion includes hole portions that retain the batteries by peripheries or inner circumferential surfaces of the hole portions. The battery module also includes guiding portions formed on the peripheries or the inner circumferential surfaces of the hole portions that are configured to guide the batteries into the storing space within the casing by causing the batteries to come closer to centers of the hole portions, such that central axis lines of the batteries pass through the centers of the hole portions.
US09899645B2	Battery pack A battery pack may include a drainage device provided at a bottom portion of the housing case. The drainage device may include a drain hole communicating between the inside and the outside of the housing case, so that water introduced into the housing case is discharged to the outside of the housing case. The drainage device may be disposed between two of the terminal members that are connected to electrodes of the battery cells.
US09899640B2	Flat-shaped battery A flat-shaped battery of the present invention includes an outer can that is open upward, a sealing can that is open downward, and a gasket that is placed between the outer can and the sealing can to seal the space between them. The outer can includes a base plate and a cylindrical surrounding wall. The surrounding wall of the outer can includes a straight portion that extends upward and perpendicular to the base plate. The sealing can includes a housing in the form of an inverted dish, a flange that projects outward from a lower end of the opening of the housing, and a single outer surrounding wall that extends downward from an outside edge of the flange so as to be perpendicular to the flange. The outer surrounding wall of the sealing can is arranged perpendicular to the base plate of the outer can. The gasket includes a base that receives a lower end of the outer surrounding wall of the sealing can, and an outer cylindrical wall that extends upward from the base and is disposed between the surrounding wall of the outer can and the outer surrounding wall of the sealing can. The surrounding wall of the outer can has a curved edge such that the surrounding wall at the opening of the outer can is bent toward an axis of the outer can and positioned laterally with respect to the outer surrounding wall of the sealing can. The curved edge presses an upper end of the outer cylindrical wall of the gasket against an upper end of the outer surrounding wall of the sealing can.
US09899639B2	Packaging material for cell A technique relates to a packaging material for a battery, including a laminate of film form including at least a base material layer, an adhesive layer, a metal layer, and a sealant layer, laminated in that order, the packaging material being resistant to cracks or pinholes occurring during molding, and having exceptional moldability. The packaging material for a battery is characterized by including a laminate of at least a base material layer, an adhesive layer, a metal layer, and a sealant layer, laminated in that order, the metal layer being aluminum foil having 0.2% proof stress of 55-140 N/mm2 when subjected to tensile testing in a parallel direction to the rolling direction, and the ratio of thickness of the base material layer and the metal layer (base material layer thickness:metal layer thickness) being within the range 1:1 to 1:3.
US09899638B2	Rechargeable battery A rechargeable battery includes a conductive case including a bottom part and a wall part extending from a periphery of the bottom part, an electrode assembly including a positive electrode and a negative electrode, and accommodated in the case, a cap plate opposite to the bottom part and electrically connected to the case, a positive terminal fixed to the cap plate and electrically connected to the cap plate, a negative terminal fixed to the cap plate and electrically insulated from the cap plate, a positive electrode tab extending from the positive electrode and electrically connected to the bottom part, and a negative electrode tab extending from the negative electrode, facing the positive electrode tab, and electrically connected to the negative terminal, wherein a length of the cap plate in a first direction is less than a height of the wall part in a second direction.
US09899636B2	Photolithographic patterning of organic electronic devices A method of making an OLED device includes providing a first undercut lift-off structure over the device substrate having a first array of bottom electrodes. Next, one or more first organic EL medium layers including at least a first light-emitting layer are deposited over the first undercut lift-off structure and over the first array of bottom electrodes. The first undercut lift-off structure and overlying first organic EL medium layer(s) are removed by treatment with a first lift-off agent comprising a fluorinated solvent to form a first intermediate structure. The process is repeated using a second undercut lift-off structure to deposit one or more second organic EL medium layers over a second array of bottom electrodes. After removal of the second undercut lift-off structure, a common top electrode is provided in electrical contact with the first and second organic EL medium layers.
US09899635B2	System for depositing one or more layers on a substrate supported by a carrier and method using the same A system for depositing one or more layers, particularly layers including organic materials therein, is described. The system includes a load lock chamber for loading a substrate to be processed, a transfer chamber for transporting the substrate, a vacuum swing module provided between the load lock chamber and the transfer chamber, at least one deposition apparatus for depositing material in a vacuum chamber of the at least one deposition chamber, wherein the at least one deposition apparatus is connected to the transfer chamber; a further load lock chamber for unloading the substrate that has been processed, a further transfer chamber for transporting the substrate, a further vacuum swing module provided between the further load lock chamber and the further transfer chamber, and a carrier return track from the further vacuum swing module to the vacuum swing module, wherein the carrier return track is configured to transport the carrier under vacuum conditions and/or under a controlled inert atmosphere.
US09899633B2	OLED display and display module having gradient change of reflectivities The present disclosure provides an OLED display and display module thereof. The OLED display module includes: a cathode plate, an anode plate and a luminance function layer sandwiched in between the cathode plate and the anode plate, and characterized in that multiple reflectivities among multiple layers of the luminance function layer are satisfied with a following relationship, which is a reflectivity of the material of the luminance function layer near to the cathode plate is greatly higher than a reflectivity of another material of the luminance function layer distant from the cathode plate. The display module solves the technical problem of decreasing the contrast and sharpness of the OLED display caused by the cathode plate with the high reflectivity.
US09899630B2	Organic EL display device A bank partitions a plurality of pixels and has an opening in each of the plurality of pixels. An organic layer includes a light emitting layer, and covers the bank opening. A first inorganic barrier layer is formed of an inorganic material, and covers the bank and the organic layer. A plurality of organic barrier portions are formed of organic materials, and are disposed on the first inorganic barrier layer. A second inorganic barrier layer is formed of the inorganic material, and covers the first inorganic barrier layer and the plurality of organic barrier portions. A recessed portion is formed on the bank and the first inorganic barrier layer (for example, the recessed portion is formed in an area which covers a contact hole), and a portion of the organic barrier portion is formed in the recessed portion.
US09899628B2	Ultraviolet LED light source and curing and packaging device and method for OLED device The present invention provides an ultraviolet LED light source and an device curing and packaging device and method. The ultraviolet LED light source (3) includes a PCB (31) and a plurality of ultraviolet LED lights (33) mounted on the PCB (31). The plurality of ultraviolet LED lights (33) is distributed in a longitudinal direction and a lateral direction of the PCB (31) to form an array. The PCB (31) includes a driving circuit corresponding to each of the ultraviolet LED lights (33) for controlling activation and deactivation of each of the ultraviolet LED lights (33) thereby achieving selective control of an illumination area of the ultraviolet LED light source (3). Using the ultraviolet LED light source to carry out curing and packaging of an OLED device may omit a masking plate and effectively protect an organic light emissive layer.
US09899626B2	Light-emitting device A flexible device with fewer defects caused by a crack is provided. A flexible device with high productivity is also provided. Furthermore, a flexible device with less display failure even in a high temperature and high humidity environment is provided. A light-emitting device includes a first flexible substrate, a second flexible substrate, a buffer layer, a first crack inhibiting layer, and a light-emitting element. A first surface of the first flexible substrate faces a second surface of the second flexible substrate. The buffer layer and the first crack inhibiting layer are provided over the first surface of the first flexible substrate. The buffer layer overlaps with the first crack inhibiting layer. The light-emitting element is provided over the second surface of the second flexible substrate.
US09899621B2	Organic light emitting diode and display device thereof The present application discloses an organic light emitting diode comprising a cathode; an anode; a plurality of light emitting layers connected in series between the cathode and the anode; and a charge generation layer between at least one pair of adjacent light emitting layers. At least one light emitting layer comprises a host layer having charge transport property.
US09899619B2	Electroluminescent diode having delayed florescence quantum dot The present invention relates to a delayed fluorescence-quantum dot (QD) electroluminescent diode, the delayed fluorescence-quantum dot electroluminescent diode includes an anode, a cathode, and a light emitting layer located between the anode and the cathode, and the light emitting layer includes a QD and a delayed fluorescence material which supplies energy to the QD.
US09899616B2	Organic field effect transistor and method for producing the same The disclosure relates to organic field effect transistors, and methods for producing organic field effect transistors. The organic field effect transistors may include a first electrode, and a second electrode, the electrodes providing a source electrode and a drain electrode, an intrinsic organic semiconducting layer in electrical contact with the first and second electrode, a gate electrode, a gate insulator provided between the gate electrode and the intrinsic organic semiconducting layer, and a doped organic semiconducting layer including an organic matrix material and an organic dopant.
US09899609B2	Organic electroluminescent compound and organic photoelectric apparatus thereof The present disclosure provides a nitrogen-containing heterocyclic compound having a general formula (I) and an organic photoelectric apparatus thereof. The general formula (I) is: wherein A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10 are independently selected from a hydrogen atom, a nitrile group and a function group having a general formula (II), and A1, A2, A3, A4, A5, A6, A7, A8, A9, and A10 include at least one nitrile group and at least one function group having the general formula (II),the general formula (II) being: wherein R1, R2, R3, R4, R5, R6, R7, and R8 are independently selected from hydrogen atoms, deuterium atoms, C6-30 aromatic group and C2-30 heterocyclic aromatic group.
US09899608B2	Heterocyclic compound, light-emitting element, light-emitting device, electronic device, and lighting device An object is to provide a novel heterocyclic compound which can be used for a light-emitting element, as a host material of a light-emitting layer in which a light-emitting substance is dispersed. Other objects are to provide a light-emitting element having low driving voltage, a light-emitting element having high current efficiency, and a light-emitting element having a long lifetime. Provided are a light-emitting element including a compound in which a dibenzo[f,h]quinoxaline ring and a hole-transport skeleton are bonded through an arylene group, and a light-emitting device, an electronic device, and a lighting device each using this light-emitting element. The heterocyclic compound represented by General Formula (G1) below is provided.
US09899604B2	Compound for organic optoelectronic device, organic light emitting diode including the same, and display including the organic light emitting diode A compound for an organic optoelectronic device represented by Chemical Formula 1 wherein groups R1-R4, Ar1, Ar2, L1, L2, X, n1, and n2 are described in the specification.
US09899603B2	Organic compound, light-emitting element, light-emitting device, electronic appliance, and lighting device An organic compound that emits blue light with high color purity and has a long lifetime is provided as a novel substance. The organic compound is a fluorescent organic compound having a structure in which benzonaphthofuranylamine is bonded to the 1-position and the 6-position of a pyrene skeleton.
US09899600B2	Multicyclic aromatic compound and organic light emitting device using the same The present specification describes a multicyclic aromatic ring compound having a novel structure and an organic light emitting device using the same.
US09899599B2	Manufacturing methods of flexible display panels and the substrate components thereof A manufacturing method of flexible display panels and the substrate components thereof are disclosed. The method includes: providing a rigid substrate and a flexible substrate; forming a sealed plastic frame on the rigid substrate and/or flexible substrate; within a vacuum environment, bonding the rigid substrate with the flexible substrate and curing the sealed plastic frame to fix the flexible substrate on the rigid substrate, after taken out from the vacuum environment, an area of the flexible substrate within the sealed plastic frame is adhered to the rigid substrate due to negative pressure; forming at least one display component on the flexible substrate; and cutting the rigid substrate and/or the flexible substrate to separate the flexible substrate and the rigid substrate. In this way, the components are prevented from being failed when the flexible substrate is stripped during the manufacturing process of the flexible substrate.
US09899597B2	Manufacturing methods of electroluminescent devices A manufacturing method of electroluminescent devices includes: providing a first electrode; electrically depositing a first carrier injection layer on the first electrode to form a first electrode component; adopting a multiple transfer-print method to form a plurality of functional layers on the first electrode component in turn, one functional layer is manufactured by executing the transfer-print method once; and arranging a second electrode on the farthest functional layer away from the first carrier injection layer. The manufacturing method is capable of manufacturing the electroluminescent devices having a plurality of functional layers. The material utilization rate is high and the cost is low.
US09899594B2	Magnetic memory devices A magnetic memory device includes a substrate, a circuit device on the substrate, a lower electrode electrically connected to the circuit device, a magnetic tunnel junction structure (MTJ structure) on the lower electrode, and an upper electrode on the MTJ structure. The MTJ structure includes a pinned layer structure including at least one crystalline ferromagnetic layer and at least one amorphous ferromagnetic layer, a free layer, and a tunnel barrier layer between the pinned layer structure and the free layer.
US09899589B2	Thermal power generation unit and thermoelectric power generation system A thermoelectric power generation system of the present disclosure includes first and second thermoelectric power generation units. Each of the thermoelectric power generation units includes a plurality of tubular thermoelectric generators. The first and second thermoelectric power generation units are electrically connected to each other such that a first impedance caused by the tubular thermoelectric generator included in the first thermoelectric power generation unit is matched with a second impedance caused by the tubular thermoelectric generator included in the second thermoelectric power generation unit.
US09899588B2	Thermoelectric element A thermoelectric element having high thermal resistance and requiring less semiconductor material than a conventional thermoelectric element with comparable performance comprises a substrate having a substrate front side and a substrate rear side opposite the substrate front side, a first contact, applied as a layer to the substrate front side, a second contact, applied as a layer to the substrate front side, a cut-off between the first and second contact which thermally and electrically separates the first and second contact from one another, and a thermoelectrically active layer having a top side and a bottom side, which are connected to one another by lateral delimiting surfaces, wherein the thermoelectrically active layer is arranged in the cut-off in such a way that the bottom side is on the substrate front side, and one of the lateral delimiting surfaces is against the first contact and one of the lateral delimiting surfaces is against the second contact. The invention further relates to a method for producing the thermoelectric element.
US09899585B2	Light emitting device A light emitting device includes a substrate, a conductive electrode connection layer, at least one epitaxial structure and an insulating layer. The substrate had an upper surface and a lower surface opposite to each other. The conductive electrode connection layer is disposed on the upper surface of the substrate and electrically connected with the substrate. The epitaxial structure is disposed on the conductive electrode connection layer and electrically connected with the conductive electrode connection layer, wherein the epitaxial structure has a first peripheral surface. The insulating layer is disposed between the conductive electrode connection layer and the least one epitaxial structure, wherein the insulating layer has a second peripheral surface, and the second peripheral surface is aligned with the first peripheral surface.
US09899581B2	Light emitting apparatus A light emitting device including a contact layer, a blocking layer over the contact layer, a protection layer adjacent the blocking layer, a light emitter over the blocking layer, and an electrode layer coupled to the light emitter. The electrode layer overlaps the blocking layer and protection layer, and the blocking layer has an electrical conductivity that substantially blocks flow of current from the light emitter in a direction towards the contact layer. In addition, the protection layer may be conductive to allow current to flow to the light emitter or non-conductive to block current from flowing from the light emitter towards the contact layer.
US09899576B2	Light emitting device and method for manufacturing the same A light emitting device includes a light emitting element having electrodes on a lower surface side thereof; a phosphor layer covering a surface of the light emitting element; a transparent covering member disposed on at least one side surface of the light emitting device; and a reflection member that covers the covering member.
US09899573B2	Slim LED package Disclosed herein is a slim LED package. The slim LED package includes first and second lead frames separated from each other, a chip mounting recess formed on one upper surface region of the first lead frame by reducing a thickness of the one upper surface region below other upper surface regions of the first lead frame, an LED chip mounted on a bottom surface of the chip mounting recess and connected with the second lead frame via a bonding wire, and a transparent encapsulation material protecting the LED chip while supporting the first and second lead frames.
US09899572B2	Semiconductor light-emitting device The present techniques provide a semiconductor light-emitting device in which current diffusion is ensured in a transparent electrode and light absorption by the transparent electrode is suppressed. The light-emitting device comprises an n-type semiconductor layer, a light-emitting layer, a p-type semiconductor layer, a transparent electrode, a transparent insulating film, and a reflection electrode. The transparent electrode contains In. The thickness of the transparent electrode is 10 nm to 150 nm. The reflection electrode is a p-type electrode. The reflection electrode P1 has a plurality of contact electrodes being in contact with the transparent electrode at a plurality of openings. The number density of the contact electrodes is 400/mm2 to 1,000/mm2.
US09899571B2	Semiconductor light emitting device Disclosed is a semiconductor light emitting device. The semiconductor light emitting device includes a plurality of compound semiconductor layers including a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer; a pad on the plurality of compound semiconductor layers; an electrode layer under the plurality of compound semiconductor layers; and a supporting member disposed under the plurality of compound semiconductor layers and corresponding to the pad.
US09899568B2	Method of producing periodic table group 13 metal nitride semiconductor crystal and periodic table group 13 metal nitride semiconductor crystal produced by this production method For a Periodic Table Group 13 metal nitride semiconductor crystal obtained by epitaxial growth on the main surface of a base substrate that has a nonpolar plane and/or a semipolar plane as its main surface, an object of the present invention is to provide a high-quality semiconductor crystal that has a low absorption coefficient, is favorable for a device, and is controlled dopant concentration in the crystal, and to provide a production method that can produce the semiconductor crystal. A high-quality Periodic Table Group 13 metal nitride semiconductor crystal that has a precisely controlled dopant concentration within the crystal and a low absorption coefficient and that is thus favorable for a device, can be provided by inhibiting oxygen doping caused by impurity oxygen and having the Si concentration higher than the O concentration.
US09899562B2	Method of fabricating a solar cell A method for fabricating a solar cell includes the steps of providing a substrate, forming a transparent conductive layer on a surface of the substrate, forming a plurality of photoresist patterns on the transparent conductive layer, forming a dielectric layer on the photoresist patterns and the transparent conductive layer, in which a part of a sidewall of the photoresist pattern is exposed from the dielectric layer, removing the photoresist patterns and a part of the dielectric layer covering the photoresist pattern so that a plurality of openings are defined in the remaining part of the dielectric layer, and forming plural electrodes in the openings respectively. A solar cell fabricated by the method is also disclosed.
US09899561B2	Method for producing a compound semiconductor, and thin-film solar cell The present invention relates to a method for producing a compound semiconductor (2), which comprises the following steps: Producing at least one precursor layer stack (11), consisting of a first precursor layer (5.1), a second precursor layer (6), and a third precursor layer (5.2), wherein, in a first stage, the first precursor layer (5.1) is produced by depositing the metals copper, indium, and gallium onto a body (12), and, in a second stage, the second precursor layer (6) is produced by depositing at least one chalcogen, selected from sulfur and selenium, onto the first precursor layer (5.1) and, in a third stage, the third precursor layer (5.2) is produced by depositing the metals copper, indium, and gallium onto the second precursor layer (6); Heat treating the at least one precursor layer stack (11) in a process chamber (13) such that the metals of the first precursor layer (5.1), the at least one chalcogen of the second precursor layer (6), and the metals of the third precursor layer (5.2) are reactively converted to form the compound semiconductor (2).
US09899556B2	Hybrid tandem solar cells with improved tunnel junction structures Tandem solar cells comprising two or more solar cells connected in a solar cell stack via pn diode tunnel junctions and methods for fabricating the tandem solar cells using epitaxial lift off and transfer printing are provided. The tandem solar cells have improved tunnel junction structures comprising a current tunneling layer integrated between the p and n layers of the pn diode tunnel junction that connects the solar cells.
US09899554B2	Method of installing a strain relief apparatus to a solar cell Methods are disclosed for assembling PV modules using connectors that have strain relief elements. Strings can be inspected individually and dimensional information can be obtained to layup the strings into a PV module in a specific manner. Portions of the strings can be soldered using elevators to lift connectors into place, and then applying heat to both sides of the connector.
US09899549B2	Infrared-ray sensing device An infrared-ray sensing device includes a support and a plurality of photodiodes disposed on the support. Each photodiode of the plurality includes a first mesa including a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type that is disposed between the first and second semiconductor layers, and a super-lattice region disposed on the support along a reference plane. The third semiconductor layer and the super-lattice region are provided in common for the photodiodes of the plurality. In the photodiodes, the first mesas and the second semiconductor layers are aligned along a first axis intersecting the reference plane so that each of the second semiconductor layers is provided in a position corresponding to the position of its first mesa. Each second semiconductor layer is disposed between the third semiconductor layer and the super-lattice region.
US09899546B2	Photovoltaic cells with electrodes adapted to house conductive paste One embodiment of the present invention provides an electrode grid positioned at least on a first surface of a photovoltaic structure. The electrode grid can include a number of finger lines and an edge busbar positioned at an edge of the photovoltaic structure. The edge busbar can include one or more paste-alignment structures configured to facilitate confinement of conductive paste used for bonding the edge busbar to an opposite edge busbar of an adjacent photovoltaic structure.
US09899544B1	Array of geiger-mode avalanche photodiodes for detecting infrared radiation An array of Geiger-mode avalanche photodiodes is formed in a die and includes: an internal dielectric structure, arranged on the die; and an external dielectric region arranged on the internal dielectric structure. The external dielectric region is formed by an external material that absorbs radiation having a wavelength that falls in a stop-band with low wavelength and transmits radiation having a wavelength that falls in a pass-band with high wavelength, at least part of the pass-band including wavelengths in the infrared. The internal dielectric structure is formed by one or more internal materials that substantially transmit radiation having a wavelength that falls in the stop-band and in the pass-band and have refractive indices that fall in an interval having an amplitude of 0.4. In the stop-band and in the pass-band the external dielectric region has a refractive index with the real part that falls in the above interval.
US09899543B2	Microelectronics package with integrated sensors The present disclosure relates to a microelectronics package with optical sensors and/or thermal sensors. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, and a first mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with sensor structure integrated at a top portion of the device layer. Herein, the sensor structure is below the first surface portion and not below the second surface portion. The first mold compound component is formed over the second surface portion to define a first cavity over the upper surface of the thinned flip-chip die. The first mold compound component is not over the first surface portion, and the first surface portion is exposed at the bottom of the first cavity.
US09899542B2	Solar cells with improved lifetime, passivation and/or efficiency A method of fabricating a solar cell can include forming a dielectric region on a silicon substrate. The method can also include forming an emitter region over the dielectric region and forming a dopant region on a surface of the silicon substrate. In an embodiment, the method can include heating the silicon substrate at a temperature above 900 degrees Celsius to getter impurities to the emitter region and drive dopants from the dopant region to a portion of the silicon substrate.
US09899540B2	Semiconductor device and method for manufacturing same A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin protruding from the element separation film and extending in the first direction in plan view. The semiconductor device further includes a control gate electrode extending in the second direction that is orthogonal to the first direction along the surface of the fin through a gate insulating film and overlaps with a first main surface of the element separation film, and a memory gate electrode extending in the second direction along the surface of the fin through an insulating film and overlaps with a second main surface of the element separation film, in which the second main surface is lower than the first main surface relative to the main surface.
US09899538B1	Non-volatile memory device and operation method thereof The present invention provides a non-volatile memory device, including a source region and a drain region, a channel region, a floating gate, an enhance hot carrier (hole or electron) injection gate and an erasing gate. The floating gate is disposed on the channel region and the source region and a first dielectric layer is disposed therebetween. The enhance hot carrier injection gate is disposed on the floating gate and the substrate wherein the enhance hot carrier injection gate has an L-shape cross-section. A second dielectric layer is disposed between the enhance hot carrier injection gate and the floating gate, and a fourth dielectric layer is disposed between the enhance hot carrier injection gate and the substrate. The erasing gate is disposed on the drain region. A third dielectric layer is disposed between the erasing gate and the substrate.
US09899533B2	Semiconductor device A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.
US09899531B2	Thin film transistor substrate, method of manufacturing the same, and display apparatus having the same A thin film transistor substrate includes a thin film transistor including a gate electrode, a semiconductor layer, a source electrode and a drain electrode. Each of the source electrode and the drain electrode includes a wire layer and a protective layer. The protective layer includes zinc oxide in an amount greater than about 70% by weight and less than about 85% by weight and indium oxide in an amount greater than about 15% by weight and less than about 30% by weight.
US09899527B2	Integrated circuits with gaps Integrated circuits and methods of producing such integrated circuits are provided. In one example, an integrated circuit has a working layer that includes a semiconductor substrate. A handle layer underlies the working layer, where a gap is defined in the handle layer such that an upper gap surface underlies the working layer. The gap has a gap area measured along a first plane at the gap upper surface. A switch directly overlies the gap, where the switch has a switch area measured along a second plane parallel with the first plane. The switch area is less than the gap area.
US09899524B2	Split fin field effect transistor enabling back bias on fin type field effect transistors A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may further include forming a split fin structure from the substrate. The metal nitride is positioned in the split portion of the fin structure. The method may continue with removing the metal nitride from a source region and drain region portion of the split fin structure, in which the metal nitride remains in a channel region portion of the split fin structure. A gate structure may then be formed on a channel region portion of the fin structure. A back bias is applied to the semiconductor device using the metal nitride in the split portion of the fin structure as an electrode.
US09899523B2	Semiconductor structure The present invention provides a semiconductor structure, comprising a substrate, a gate structure, a source/drain region and at least a dislocation. The gate structure is disposed on the substrate. The source/drain region is disposed in the substrate at two sides of the gate structure. The dislocation is located in the source/drain region, and is asymmetrical relating to a middle axis of the source/drain region.
US09899521B2	FinFET low resistivity contact formation method The invention relates to a contact structure of a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a trench below the major surface; a strained material filling the trench, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and wherein a surface of the strained material has received a passivation treatment; an inter-layer dielectric (ILD) layer having an opening over the strained material, wherein the opening comprises dielectric sidewalls and a strained material bottom; a dielectric layer coating the sidewalls and bottom of the opening, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; a metal barrier coating an opening of the dielectric layer; and a metal layer filling a coated opening of the dielectric layer.
US09899520B2	Method for fabricating semiconductor device A method for forming a semiconductor device includes steps as follows: Firstly, a semiconductor substrate having a circuit element with at least one spacer formed thereon is provided. Next, an acid treatment is performed on a surface of the spacer. A disposable layer is then formed on the circuit element and the spacer. Thereafter, an etching process is performed to form at least one recess in the semiconductor substrate adjacent to the circuit element. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer in the recess.
US09899513B1	Lateral diffused metal oxide semiconductor transistor and manufacturing method thereof A lateral diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof are provided. A deep well region is disposed in a substrate. An isolation structure is disposed in the substrate to define a first active area and a second active area. A well region is disposed in the deep well region in the first active area. A gate is disposed on the substrate in the first active area. A gate dielectric layer is disposed between the gate and the substrate. A first doped region is disposed in the well region in the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structure is disposed on the isolation structure, surrounds the second doped region and is connected to the gate.
US09899510B2	Semiconductor device The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.
US09899507B2	Nitride semiconductor transistor device A nitride semiconductor transistor device provides a normally-off nitride semiconductor transistor device which is excellent in switching properties with less dispersion of the properties. The nitride semiconductor transistor device has a buffer layer, a GaN layer, and an AlGaN layer in turn grown on a substrate. A first insulating film, a charge storage layer, a second insulating film, and a control electrode are in turn grown on the AlGaN layer. A source electrode and a drain electrode are formed to sandwich the charge storage layer over the AlGaN layer. A threshold voltage to shut off an electric current flowing between the source and drain electrodes through a conductive channel induced at an interface of the AlGaN layer and the GaN layer is made positive by adjusting the charge stored in the charge storage layer.
US09899506B2	Semiconductor device Provided is a semiconductor device in which electron mobility is improved by applying sufficiently large tensile stress in a predetermined direction without occurrence of cracks in a nitride semiconductor. The semiconductor device includes: substrate (101), electron transit layer (103) that is disposed on substrate (101) and is formed by GaN; and electron supply layer (104) that is disposed on electron transit layer (103) and is formed by AlGaN. A coefficient of thermal expansion of substrate (101) is different between a first direction in a main surface of substrate (101) and a second direction that is perpendicular to the first direction in the main surface, and tensile stress occurs in electron transit layer (103).
US09899502B2	Bipolar junction transistor layout structure A bipolar junction transistor layout structure includes a first emitter including a pair of first sides and a pair of second sides, a pair of collectors disposed at the first sides of the first emitter, and a pair of bases disposed at the second sides of the first emitter. The first sides are perpendicular to the second sides. The first emitter is disposed in between the pair of collectors and in between the pair of bases.
US09899489B2	Vertical gate all around (VGAA) devices and methods of manufacturing the same Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
US09899488B2	Semiconductor device having a trench with different electrode materials A semiconductor device includes a semiconductor body having a front side and a back side, and a trench included in the semiconductor body. The trench extends into the semiconductor body along an extension direction that points from the front side to the back side. The trench includes an electrode structure and an insulation structure, the insulation structure insulating the electrode structure from the semiconductor body and the electrode structure being arranged for receiving an electric signal from external of the semiconductor device. The electrode structure includes a first electrode and a second electrode in contact with the first electrode, the first electrode including a first electrode material and the second electrode including a second electrode material different from the first electrode material. The first electrode extends further along the extension direction as compared to the second electrode.
US09899486B2	Memory transistor with multiple charge storing layers and a high work function gate electrode An example memory device includes a channel positioned between and electrically connecting a first diffusion region and a second diffusion region, and a tunnel dielectric layer, a multi-layer charge trapping layer, and a blocking dielectric layer disposed between the gate structure and the channel. The multi-layer charge trapping layer includes a first dielectric layer disposed abutting a second dielectric layer and an anti-tunneling layer disposed between the first and second dielectric layers. The anti-tunneling layer includes an oxide layer. The first dielectric layer includes oxygen-rich nitride and the second dielectric layer includes oxygen-lean nitride.
US09899482B2	Tunnel barrier schottky A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.
US09899479B2	Semiconductor devices with superlattice layers providing halo implant peak confinement and related methods A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.
US09899477B2	Edge termination structure having a termination charge region below a recessed field oxide region An edge termination structure is disclosed. The edge termination structure includes an active cell in a semiconductor wafer, an edge termination region adjacent the active cell in the semiconductor wafer, where the edge termination region includes a recessed field oxide region and a termination charge region below the recessed field oxide region. The recessed field oxide region may be thermally grown in a recess in the semiconductor wafer. A top surface of the recessed field oxide region is substantially coplanar with a top surface of the semiconductor wafer. The active cell may include at least one insulated-gate bipolar transistor surrounded by the edge termination region in the semiconductor wafer. The termination charge region has a conductivity type opposite of that of the semiconductor wafer. The termination charge region is adjacent to at least one guard ring in the semiconductor wafer.
US09899476B2	Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stresses An integrated circuit includes a substrate and at least one component unfavorably sensitive to compressive stress which is arranged at least partially within an active region of the substrate limited by an insulating region. To address compressive stress in the active region, the circuit further includes at least one electrically inactive trench located at least in the insulating region and containing an internal area configured to reduce compressive stress in the active region. The internal area is filled with polysilicon. The polysilicon filled trench may further extend through the insulating region and into the substrate.
US09899475B2	Epitaxial channel with a counter-halo implant to improve analog gain The present disclosure relate to an integrated chip having long-channel and short-channel transistors having channel regions with different doping profiles. In some embodiments, the integrated chip includes a first gate electrode arranged over a first channel region having first length, and a second gate electrode arranged over a second channel region having a second length greater than the first length. The first channel region and the second channel region have a dopant profile, respectively along the first length and the second length, which has a dopant concentration that is higher by edges than in a middle of the first channel region and the second channel region. The dopant concentration is also higher by the edges of the first channel region than by the edges of the second channel region.
US09899473B2	Method of forming nanostructure, method of manufacturing semiconductor device using the same, and semiconductor device including nanostructure Provided are methods of forming nanostructures, methods of manufacturing semiconductor devices using the same, and semiconductor devices including nanostructures. A method of forming a nanostructure may include forming an insulating layer and forming a nanostructure on the insulating layer. The insulating layer may have a crystal structure. The insulating layer may include an insulating two-dimensional (2D) material. The insulating 2D material may include a hexagonal boron nitride (h-BN). The insulating layer may be formed on a catalyst metal layer. The nanostructure may include at least one of silicon (Si), germanium (Ge), and SiGe. The nanostructure may include at least one nanowire.
US09899469B2	Semiconductor device and manufacturing method thereof A semiconductor device includes a p-type semiconductor region in contact with a bottom face of a trench gate, wherein the p-type semiconductor region includes a first p-type semiconductor region containing a first type of p-type impurities and a second p-type semiconductor region containing a second type of p-type impurities. The first p-type semiconductor region is located between the trench gate and the second p-type semiconductor region. In a view along the depth direction, the second p-type semiconductor region is located within a part of the first p-type semiconductor region. A diffusion coefficient of the second type of p-type impurities is smaller than a diffusion coefficient of the first type of p-type impurities.
US09899466B2	Head resistance buffer An integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions wherein the resistor buffer regions are disposed between the resistor body and the resistor heads. The width of the first and second resistors is different. The length of the first and second resistor buffer regions is different. The total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for forming an integrated circuit with first and second resistors comprised of resistor bodies, resistor heads, and resistor buffer regions disposed between the resistor body and the resistor head wherein the width of the first and second resistors is different, wherein the length of the resistor buffer regions of the first and second resistors is different, and wherein the total head resistance which is equal to the resistor head resistance plus the resistor buffer region is equal for both the first and second resistors. A method is described for calculating the length of a resistor buffer region as a function of resistor width so that the resistance of the resistor head plus the resistor buffer region remains the same as resistor body width changes.
US09899462B2	Manufacturing method for OLED display panel The present disclosure provides an OLED display panel and a manufacturing method thereof. The OLED display panel includes a substrate and a bank layer and pixel units disposed on the substrate. The pixel units are partitioned by the bank layer. The bank layer is negative photoresist. Openings obtained by exposing and developing the bank layer are formed in the bank layer. The openings are used for placing light-emitting layers of the pixel units. A light-permeable light enhancement layer is disposed between the bank layer around the opening and the substrate, such that light intensity on one side of the bank layer around the opening close to the substrate is increased during the exposure and development process to obtain the opening having a top wider than a bottom. By using the present disclosure, a manufacturing efficiency of the light-emitting layers of the OLEDs increases.
US09899461B2	Organic light-emitting diode display An organic light-emitting diode display is disclosed. The display includes a semiconductor layer formed over a substrate, a scan line formed over the semiconductor layer and configured to provide a scan signal, and a light emission control line formed over the semiconductor layer and configured to provide a light emission control signal. The display includes a data line configured to provide a data voltage and a driving voltage line configured to provide a driving voltage, wherein the driving voltage line crosses the scan line and is electrically insulated from the scan line. A switching transistor is electrically connected to the scan line and the data line and includes a switching drain electrode. A driving transistor includes a driving source electrode electrically connected to the switching drain electrode. Any one of the semiconductor layer and the light emission control line includes an extension at least partially overlapping the data line.
US09899459B2	Organic light emitting device Disclosed is an organic light emitting device, (OLED) comprising a substrate on which a driving transistor is formed, a bank formed on the substrate providing a boundary for a pixel region, a first electrode formed on the substrate and electrically connected with the driving transistor, the first electrode comprising a first and second cross sectional area both oriented in a direction perpendicular to a vertical direction of the substrate, the first area adjacent to the bank, the second area surrounded by the first area, an organic layer formed on the first electrode within the boundary provided by the bank, and a second electrode formed on the organic layer, wherein during operation of the OLED a first electric field between the first area of the first electrode and the second electrode is greater than a second electric field between the second area of the first electrode and the second electrode.
US09899457B2	Flexible OLED display having increased lifetime Embodiments of the disclosed subject matter provide a device including an active-matrix driven flexible display including a plurality of Organic Light Emitting Diodes (OLEDs) formed on a plastic substrate, where each OLED includes a phosphorescent first emissive layer, where the display operates at a luminance value of at least 500 cd/m2 with a luminance decay of not more than about 3% after 10,000 hours of operation, and where the display is formed on the plastic substrate having a glass transition temperature of the less than 200° C.
US09899456B2	Large area OLED microdisplay and method of manufacturing same An organic light-emitting diode (OLED) display device is provided having a color emission layer including a plurality of organic light-emitting elements in a first arrangement and an electronics layer. The electronics layer includes a plurality of pixel drive circuits each including an electrode contact. The electronics layer includes a plurality of independently addressable sub-regions each sub-region including an identical pattern of electrode contacts created using a single reticle exposure. Each sub-region is orientated differently within a plane such that the first arrangement of light-emitting elements is electrically connected to the patterned electronics layer.
US09899455B2	Organic light emitting diode display An organic light emitting diode display includes: a first organic light emitting element configured to emit light having a first wavelength; and a second organic light emitting element configured to emit light having a second wavelength substantially shorter than the first wavelength. The first organic light emitting element includes a first electrode, and the second organic light emitting element includes a second electrode having substantially higher reflectance for the light having the second wavelength than the first electrode.
US09899451B2	Array of cross point memory cells and methods of forming an array of cross point memory cells An array of cross point memory cells comprises spaced elevationally inner first lines, spaced elevationally outer second lines which cross the first lines, and a multi-resistive state region elevationally between the first and second lines where such cross. Individual of the multi-resistive state regions comprise elevationally outer multi-resistive state material and elevationally inner multi-resistive state material that are electrically coupled to one another. The inner multi-resistive state material has opposing edges in a vertical cross-section. The outer multi-resistive state material has opposing edges in the vertical cross-section that are laterally offset relative to the opposing edges of the inner multi-resistive state material in the vertical cross-section. Methods are also disclosed.
US09899450B2	Memristors and method for fabricating memristors There are disclosed memristors and memristor fabrication methods. A memristor may include a stack of four functional elements including, in sequence, a first electrode, a barrier layer, an oxygen-deficient switching layer, and a second electrode.
US09899449B2	Solid-state imaging device and imaging system A solid-state imaging device includes: a first semiconductor substrate including a photoelectric conversion element; and a second semiconductor substrate including at least a part of a peripheral circuit arranged in a main face of the second semiconductor substrate, the peripheral circuit generating a signal based on the charge of the photoelectric conversion element, a main face of the first semiconductor substrate and the main face of the second semiconductor substrate being opposed to each other with sandwiching a wiring structure therebetween; a pad to be connected to an external terminal; and a protection circuit electrically connected to the pad and to the peripheral circuit, wherein the protection circuit is arranged in the main face of the second semiconductor substrate.
US09899448B2	Semiconductor device having SOI substrate There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.
US09899442B2	Image sensor device An image sensor device, as well as methods therefor, is disclosed. This image sensor device includes a substrate having bond pads. The substrate has a through substrate channel defined therein extending between a front side surface and a back side surface thereof. The front side surface is associated with an optically-activatable surface. The bond pads are located at or proximal to the front side surface aligned for access via the through substrate channel. Wire bond wires are bonded to the bond pads at first ends thereof extending away from the bond pads with second ends of the wire bond wires located outside of an opening of the channel at the back side surface. A molding layer is disposed along the back side surface and in the through substrate channel. A redistribution layer is in contact with the molding layer and interconnected to the second ends of the wire bond wires.
US09899435B2	Solid-state imaging device, production method of the same, and imaging apparatus A solid-state imaging device in which a pixel circuit formed on the first surface side of a semiconductor substrate is shared by a plurality of light reception regions and second surface side of the semiconductor substrate is the light incident side of the light reception regions. The second surface side regions of the light reception regions are arranged at approximately even intervals and the first surface side regions of the light reception regions e are arranged at uneven intervals. Respective second surface side regions and first surface side regions are joined in the semiconductor substrate so that the light reception regions extend from the second surface side to the first surface side of the semiconductor substrate.
US09899434B1	Light-receiving device having avalanche photodiodes of different types A light-receiving device includes a silicon semiconductor substrate, a plurality of first serial connections each of which includes a first avalanche photodiode (APD) and a first resistor connected in series, and a plurality of second serial connections each of which includes a second avalanche photodiode (APD) and a second resistor connected in series. The first APDs and the first resistors are formed on the silicon semiconductor substrate, and the first APDs is formed of silicon. The second APDs and the second resistors are formed on the silicon semiconductor substrate, and the second APDs is formed of a material having a smaller band gap than silicon. The plurality of first and second serial connections is connected in parallel between an anode terminal and a cathode terminal.
US09899433B2	Array substrate and method for preparing the same, and display device The invention relates to an array substrate and a method for preparing the same, and a display device. The method for preparing an array substrate comprises steps S1) forming a pattern, which includes a gate electrode, a gate electrode insulating layer, an active layer and a source-drain electrode, on a base substrate; and S2) forming a transparent conducting layer on the base substrate on which step S1 has been accomplished, and simultaneously forming a pattern including a pixel electrode and a data line via a one-time patterning process. In this method, the steps of the manufacture process can be reduced, the production cost can be saved, and the production efficiency can be improved. Moreover, since the pixel electrode and the data line may be both formed to have a low resistance value and a high light transmission rate, the performance of the array substrate can be improved.
US09899431B2	Array substrate, display panel and display device An array substrate, a display panel and a display device are provided. The array substrate comprises: an active area, a package area and a drive circuit area, wherein the drive circuit area is located between the active area and the package area. A package metal layer is provided at the package area, and at least one groove structure is provided on a side of the package metal layer in a proximity to the drive circuit area. At least one drive unit is provided at the drive circuit area and comprises at least one element, wherein the element is provided in the groove structure.
US09899423B2	Semiconductor device and display device including the semiconductor device A semiconductor device including a transistor and a connection portion is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, an oxide semiconductor film over the first insulating film and at a position overlapping with the gate electrode, and source and drain electrodes electrically connected to the oxide semiconductor film; and the connection portion includes a first wiring on the same surface as a surface on which the gate electrode is formed, a second wiring on the same surface as a surface on which the source and drain electrodes are formed, and a third wiring connecting the first wiring and the second wiring. The distance between an upper end portion and a lower end portion of the second wiring is longer than the distance between an upper end portion and a lower end portion of each of the source and drain electrodes.
US09899422B2	Thin film transistor substrate and display device including the same A thin film transistor substrate includes a base substrate, a first metallic layer including a gate electrode of a thin film transistor and an island electrode spaced apart from the gate electrode on the base substrate, a semiconductor layer of which a portion thereof overlaps the gate electrode of the first metallic layer, and a second metallic layer including a source electrode and a drain electrode of the thin film transistor which are spaced apart from each other on the portion of the semiconductor layer. The source electrode of the thin film transistor overlaps the island electrode.
US09899416B2	Semiconductor device and fabricating method thereof There is provided a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure. The semiconductor device includes a substrate including a first region and a second region, a first wire pattern provided on the first region of the substrate and spaced apart from the substrate, a second wire pattern provided on the second region of the substrate and spaced apart from the substrate, a first gate insulating film surrounding a perimeter of the first wire pattern, a second gate insulating film surrounding a perimeter of the second wire pattern, a first gate electrode provided on the first gate insulating film, intersecting with the first wire pattern, and including a first metal oxide film therein, a second gate electrode provided on the second gate insulating film and intersecting with the second wire pattern, a first gate spacer on a sidewall of the first gate electrode, and a second gate spacer on a sidewall of the second gate electrode.
US09899415B1	System on chip fully-depleted silicon on insulator with rf and mm-wave integrated functions A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 KΩ·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.
US09899410B1	Charge storage region in non-volatile memory Disclosed herein is a non-volatile storage system with memory cells having a charge storage region that may be configured to store a higher density of charges (e.g., electrons) in the middle than nearer to the control gate or channel. The charge storage region has a middle charge storage material that stores a higher density of charges than two outer charge storage materials that are nearer to the control gate or channel, in one aspect. The charge storage region of one aspect has oxide regions between the middle charge storage material and the two outer charge storage materials. The oxide regions of one embodiment are thin (e.g., less than one nanometer) such that during operation charges may easily pass through the oxide regions. The non-volatile memory cell programs quickly and has high data retention.
US09899404B2	Semiconductor device Provided is a semiconductor device. The semiconductor device includes a conductive pattern disposed on a semiconductor substrate. First and second conductive lines disposed on the conductive pattern and located at the same level as each other, are provided. An isolation pattern is disposed between the first and second conductive lines. A first vertical structure passing through the first conductive line and conductive pattern is provided. A second vertical structure passing through the second conductive line and conductive patterns is provided. An auxiliary pattern passing through the conductive pattern and in contact with the isolation pattern is provided.
US09899401B2	Non-volatile memory devices including vertical NAND channels and methods of forming the same A non-volatile memory device can include a plurality of immediately adjacent offset vertical NAND channels that are electrically coupled to a single upper select gate line or to a single lower select gate line of the non-volatile memory device.
US09899396B1	Semiconductor device, fabricating method thereof, and fabricating method of memory A method for fabricating a semiconductor device includes: forming a first trench and a wider second trench in a substrate and a material layer formed thereon, forming a flowable isolation material covering the material layer and filling in the first and second trenches, removing a portion of the flowable isolation material in the second trench so that the thickness of the remaining flowable isolation material on the sidewall of the second trench is 200 Å to 1000 Å, and forming a non-flowable isolation material on the flowable isolation material.
US09899393B2	Integrated circuit devices including fin shapes Integrated circuit devices are provided. An integrated circuit device includes a substrate having first and second fin-shaped Field Effect Transistor (FinFET) bodies protruding from the substrate. The first and second FinFET bodies have different respective first and second shapes in a first region and a second region, respectively, of the integrated circuit device.
US09899392B2	Silicon precursor, method of forming a layer using the same, and method of fabricating semiconductor device using the same The inventive concepts provide silicon precursors, methods of forming a layer using the same, and methods of fabricating a semiconductor device using the same. The silicon precursor includes a silane group including two or more silicon atoms. The silicon precursor has a high and uniform adsorption property on surfaces of layers (e.g., a silicon layer, an oxide layer, and a nitride layer) that are mainly used when semiconductor devices are fabricated.
US09899391B2	Metal trench capacitor and improved isolation and methods of manufacture A high-k dielectric metal trench capacitor and improved isolation and methods of manufacturing the same is provided. The method includes forming at least one deep trench in a substrate, and filling the deep trench with sacrificial fill material and a poly material. The method further includes continuing with CMOS processes, comprising forming at least one transistor and back end of line (BEOL) layer. The method further includes removing the sacrificial fill material from the deep trenches to expose sidewalls, and forming a capacitor plate on the exposed sidewalls of the deep trench. The method further includes lining the capacitor plate with a high-k dielectric material and filling remaining portions of the deep trench with a metal material, over the high-k dielectric material. The method further includes providing a passivation layer on the deep trench filled with the metal material and the high-k dielectric material.
US09899387B2	Multi-gate device and method of fabrication thereof A semiconductor includes a first transistor and a second transistor. The first transistor includes a first and a second epitaxial layer, formed of a first semiconductor material. The second epitaxial layer is disposed over the first epitaxial layer. The first transistor also includes a first gate dielectric layer surrounds the first and second epitaxial layers and extends from a top surface of the first epitaxial layer to a bottom surface of the second epitaxial layer and a first metal gate layer surrounding the first gate dielectric layer. The second transistor includes a third epitaxial layer formed of the first semiconductor material and a fourth epitaxial layer disposed directly on the third epitaxial layer and formed of a second semiconductor. The second transistor also includes a second gate dielectric layer disposed over the third and fourth epitaxial layers and a second metal gate layer disposed over the second gate dielectric layer.
US09899382B2	Fin field effect transistor (FinFET) device structure with different gate profile and method for forming the same A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width.
US09899381B2	Semiconductor integrated circuit device having a standard cell which includes a fin Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.
US09899379B2	Semiconductor devices having fins A semiconductor device includes a first fin on a substrate, a gate electrode on the substrate to intersect the first fin, an epitaxial layer on both sides of the gate electrode to contact side surfaces of the first fin, and a metal alloy layer which contacts an upper surface of the first fin and part of the epitaxial layer, wherein a first region of the first fin has a higher doping concentration than a second region of the first fin which is located under the first region.
US09899372B1	Forming on-chip metal-insulator-semiconductor capacitor A method is presented for forming a semiconductor structure. The method includes forming a plurality of fins on a first region of the semiconductor substrate, forming a bi-polymer structure, selectively removing the first polymer of the bi-polymer structure and forming deep trenches in the semiconductor substrate resulting in pillars in a second region of the semiconductor structure. The method further includes selectively removing the second polymer of the bi-polymer structure, doping the pillars, and depositing a high-k metal gate (HKMG) over the first and second regions to form the MIS capacitor in the second region of the semiconductor substrate.
US09899370B2	Auxiliary self-protecting transistor structure This document discusses, among other things, an auxiliary self-protecting transistor circuit, system, and method configured to protect a complementary metal-oxide semiconductor (CMOS) transistor. The auxiliary self-protecting transistor circuit can include an ESD device including a gate terminal, a drain terminal, and a source terminal. The ESD device is configured to be coupled to an isolation region of a complementary metal-oxide semiconductor (CMOS) transistor, and can provide a discharge path between the isolation region of the CMOS transistor and the source terminal of the ESD device. The isolation region of the CMOS transistor can include a blocking junction, such as an n-doped isolation well (niso), a p-type well (pwell), or one or more other blocking junctions.
US09899366B2	Electronic device, in particular for protection against overvoltages An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
US09899365B1	Layout of semiconductor device A layout of a semiconductor device includes a first active area, a second active area, plural gates, a first conductive layout and plural plugs. The first and the second active areas are disposed on a substrate and surrounded by a shallow trench isolation (STI). The plural gates are parallel with one another and cross the first and the second active areas. The first conductive layer covers the plural gates, and the plural gates are electrically connected to each other through the first conductive layer. The plural plugs are disposed on the first conductive layer to electrically connect the plural gates.
US09899364B2	Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.
US09899360B2	Semiconductor device A semiconductor device includes a semiconductor substrate, a conducting portion, and a sealing resin. The substrate has a main surface and is formed with a recessed portion in the main surface. The conducting portion is formed on the substrate. The sealing resin is disposed in the recessed portion. The conducting portion includes a first wiring layer and a second wiring layer both formed in the recessed portion. The second wiring layer is closer to the main surface than is the first wiring layer in the normal direction of the main surface.
US09899355B2	Three-dimensional integrated circuit structure Provided is a 3DIC structure including first and second IC chips and connectors. The first IC chip includes a first metallization structure, a first optical active component, and a first photonic interconnection layer. The second IC chip includes a second metallization structure, a second optical active component, and a second photonic interconnection layer. The first and second IC chips are bonded via the first and second photonic interconnection layers. The first optical active component is between the first photonic interconnection layer and the first metallization structure. The first optical active component and the first metallization structure are bonded to each other. The second optical active component is between the second photonic interconnection layer and the second metallization structure. The second optical active component and the second metallization structure are bonded to each other.
US09899354B2	Method for interconnecting stacked semiconductor devices A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
US09899349B2	Semiconductor packages and related methods Methods of forming a semiconductor package. Implementations include providing a leadframe, coupling a semiconductor die or an electronic component to the leadframe, and encapsulating at least a portion of the semiconductor die or the electronic component using a mold compound leaving two or more leads of the leadframe exposed. The method may also include coating the two or more leads of the leadframe with an electrically conductive layer. The method may include fully electrically and physically singulating one or more tie bars between two or more leads of the leadframe, a lead of the two or more leads and a leadframe flag or any combination thereof. The method may also include singulating the leadframe to form one or more semiconductor packages.
US09899347B1	Wire bonded wide I/O semiconductor device A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.
US09899346B2	Semiconductor device According to one embodiment, a semiconductor device includes lower layer wirings formed on a semiconductor chip, a protection film arranged on the lower layer wirings, an upper layer wiring arranged on the protection film and across a plurality of lower layer wirings, and connected to the lower layer wirings, wherein the upper layer wiring is larger than the lower layer wirings in terms of wiring line width and wiring line thickness, and a stress relaxing portion configured to reduce a stress at an in-corner portion of the upper layer wiring on the protection film, as compared with a case where the in-corner portion is set in 90°.
US09899344B2	Substrate structure, fabrication method thereof and conductive structure A substrate structure is provided, which includes: a substrate body having a plurality of conductive pads; an insulating layer formed on the substrate body and exposing the conductive pads; a plurality of conductive vias formed in the insulating layer and electrically connected to the conductive pads; a plurality of circuits formed on the conductive vias and in the insulating layer, wherein the circuits are greater in width than the conductive vias; and a plurality of conductive posts formed on the circuits and the insulating layer, wherein each of the conductive posts has a width greater than or equal to that of each of the circuits. The conductive vias, the circuits and the conductive posts are integrally formed. As such, micro-chips or fine-pitch conductive pads can be electrically connected to the substrate structure in a flip-chip manner.
US09899342B2	Integrated fan-out package, redistribution circuit structure, and method of fabricating the same A redistribution circuit structure electrically connected to at least one conductor underneath is provided. The redistribution circuit structure includes a dielectric layer, an alignment, and a redistribution conductive layer. The dielectric layer covers the conductor and includes at least one contact opening for exposing the conductor. The alignment mark is disposed on the dielectric layer. The alignment mark includes a base portion on the dielectric layer and a protruding portion on the base portion, wherein a ratio of a maximum thickness of the protruding portion to a thickness of the base portion is smaller than 25%. The redistribution conductive layer is disposed on the dielectric layer. The redistribution conductive layer includes a conductive via, and the conductive via is electrically connected to the conductor through the contact opening. A method of fabricating the redistribution circuit structure and an integrated fan-out package are also provided.
US09899336B2	Semiconductor device A scale-like portion wherein metal plating is changed into a scale-like form is provided by continuously carrying out laser spot irradiation on a lead frame, the front surface of which is coated with the metal plating. The scale-like portion is disposed in an optional portion of the lead frame, for example, in the vicinity of a gate break mark, in an outer peripheral portion in a region sealed with a molding resin, or around a semiconductor element. The adhesion between the lead frame and the molding resin improves owing to the anchor effect of the scale-like portion, and it is thus possible to suppress the molding resin separating from the lead frame.
US09899335B2	Method for fabricating package structure A package structure includes a carrier, an electronic component disposed on the carrier, an encapsulant formed on the carrier for encapsulating the electronic component, a first shielding layer formed on the encapsulant, and a second shielding layer formed on the first shielding layer. The first and second shielding layers are made of different materials. With the multiple shielding layers formed on the encapsulating layer, the electronic component is protected from electromagnetic interferences. The present invention also provides a method for fabricating the package structure.
US09899332B2	Visual identification of semiconductor dies Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer having a plurality of dies and printing a unique visual identification mark on each of the plurality of dies. In other embodiments, a method may include receiving an electronic device comprising a die and a package surrounding at least a portion of the die and reading, from the electronic device, a unique visual identification mark that encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.
US09899331B2	Fan-out semiconductor package and method of manufacturing same A fan-out semiconductor package includes a redistribution layer, the redistribution layer including a first insulating layer, a first wiring disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first wiring, a line via passing through the second insulating layer continuously and connected to the first wiring, and a second wiring disposed on the second insulating layer and connected to the line via; a semiconductor chip disposed on one side of the redistribution layer, and having an electrode pad electrically connected to the first wiring, the second wiring, and the line via; and an encapsulant disposed on the one side of the redistribution layer, and encapsulating the semiconductor chip.
US09899322B2	Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.
US09899321B1	Methods of forming a gate contact for a semiconductor device above the active region One illustrative method disclosed includes, among other things, completely forming a first conductive structure comprising one of a conductive gate contact structure (CB) or a conductive source/drain contact structure (CA), wherein the entire conductive gate contact structure (CB) is positioned vertically above a portion of an active region of a transistor device, and, after completely forming the first conductive structure, completely forming a second conductive structure comprising the other of the conductive gate contact structure (CB) or the conductive source/drain contact structure (CA).
US09899317B1	Nitridization for semiconductor structures A method for fabricating a semiconductor structure includes the following steps. A substrate including a dielectric material is formed. A surface of the substrate is molecularly modified to convert the surface of the substrate to a nitrogen-enriched surface. A metal layer is deposited on the molecularly modified surface of the substrate interacting with the molecularly modified surface to form a nitridized metal layer.
US09899312B2	Isolating electric paths in semiconductor device packages Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.
US09899311B2	Hybrid pitch package with ultra high density interconnect capability A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).
US09899307B2	Fan-out chip package with dummy pattern and its fabricating method A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a plurality of vertical connectors. The encapsulation encapsulates the sides of the chip. The thickness of the encapsulation is the same as the thickness of the chip. The first passivation layer covers the active surface of the chip and the peripheral surface of the encapsulation. The redistribution layer is formed on the first passivation layer to extend the electrical connection of the chip to the peripheral surface of the encapsulation. The second passivation layer is formed on the first passivation layer. The vertical connectors are embedded in the encapsulation and the redistribution layer. The vertical connectors are only penetrate through the encapsulation protect the redistribution layer from damages.
US09899303B2	Electronic package and fabrication method thereof A method for fabricating an electronic package is provided, which includes the steps of: providing an insulating layer having at least an electronic element embedded therein; forming at least a first via hole on one side of the insulating layer; forming a first conductor in the first via hole of the insulating layer; forming on the insulating layer a first circuit structure electrically connected to the electronic element and the first conductor; and forming a second via hole on the other side of the insulating layer, wherein the second via hole communicates with the first via hole. As such, the second via hole and the first via hole constitute a through hole. Since the through hole is fabricated through two steps, the aspect ratio (depth/width) of the through hole can be adjusted according to the practical need so as to improve the process yield.
US09899302B2	Semiconductor package having multi-phase power inverter with internal temperature sensor According to an exemplary implementation, a semiconductor package includes a multi-phase power inverter having power switches and situated on a leadframe of the semiconductor package. The semiconductor package further includes a temperature sensor situated on the leadframe, where the temperature sensor is configured to generate a sensed temperature of the power switches. The semiconductor package also includes a driver circuit configured to drive the power switches of the multi-phase power inverter responsive to the sensed temperature. The temperature sensor can be on a common IC with the driver circuit. Furthermore, the semiconductor package can include an over-temperature protection circuit configured to provide over-temperature protection to the multi-phase power inverter using the sensed temperature.
US09899291B2	Method for protecting layer by forming hydrocarbon-based extremely thin film A method for protecting a layer includes: providing a substrate having a target layer and forming a protective layer on the target layer, said protective layer contacting and covering the target layer and containing a hydrocarbon-based layer constituting at least an upper part of the protective layer, which hydrocarbon-based layer is formed by plasma-enhanced atomic layer deposition (PEALD) using an alkylaminosilane precursor and a noble gas without a reactant.
US09899289B2	Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.
US09899284B2	Chip package and method for fabricating the same A method for fabricating chip package includes providing a semiconductor chip with a metal bump, next adhering the semiconductor chip to a substrate using a glue material, next forming a polymer material on the substrate, on the semiconductor chip, and on the metal bump, next polishing the polymer material, next forming a patterned circuit layer over the polymer material and connected to the metal bump, and then forming a tin-containing ball over the patterned circuit layer and connected to the patterned circuit layer.
US09899279B2	Flat laminate, symmetrical test structures and method of use to gauge white bump sensitivity A symmetrical, flat laminate structure used to minimize variables in a test structure to experimentally gauge white bump sensitivity to CTE mismatch is disclosed. The test structure includes a flat laminate structure. The method of using the test structure includes isolating a cause of a multivariable chip join problem that is adversely impacted by warpage and quantifying a contribution of the warpage, itself, in a formation of the multivariable chip join problem.
US09899273B1	Semiconductor structure with dopants diffuse protection and method for forming the same Semiconductor structures and methods for forming the same are provided. The method for forming a semiconductor structure includes forming an N-well region in a substrate and forming a first protection layer over the N-well region. The method for forming a semiconductor structure further includes forming a P-well region in the substrate and forming a second protection layer over the P-well region. The method for forming a semiconductor structure further includes growing a first channel layer over the first protection layer and a second channel layer over the second protection layer and forming a first gate structure over the first channel layer and a second gate structure over the second channel layer.
US09899270B2	Methods for manufacturing semiconductor devices There is disclosed a method for manufacturing a semiconductor device comprising two opposite types of MOSFETs formed on one semiconductor substrate, the method comprising: forming a portion of the MOSFET on the semiconductor substrate, said portion of said MOSFET comprising source/drains regions located in the semiconductor substrate, a dummy gate stack located between the source/drain region and above the semiconductor substrate and a gate spacer surrounding the dummy gate stack; removing the dummy gate stack of said MOSFET to form a gate opening which exposes the surface of the semiconductor substrate; forming an interfacial oxide layer on the exposed surface of the semiconductor structure; forming a high-K gate dielectric on the interfacial oxide layer within the gate opening; forming a first metal gate layer on the high-K gate dielectric; implanting doping ions in the first metal gate layer; forming a second metal gate layer on the first metal gate layer to fill up the gate opening; and annealing to diffuse and accumulate the doping ions at an upper interface between the high-K gate dielectric and the first metal gate layer and at a lower interface between the high-K gate dielectric and the interfacial oxide, and generating an electric dipole at the lower interface between the high-K gate dielectric and the interfacial oxide by interfacial reaction.
US09899269B2	Multi-gate device and method of fabrication thereof A method of semiconductor device fabrication is described that includes forming a first fin extending from a substrate. The first fin has a source/drain region and a channel region and the first fin is formed of a first stack of epitaxial layers that includes first epitaxial layers having a first composition interposed by second epitaxial layers having a second composition. The method also includes removing the second epitaxial layers from the source/drain region of the first fin to form first gaps, covering a portion of the first epitaxial layers with a dielectric layer and filling the first gaps with the dielectric material and growing another epitaxial material on at least two surfaces of each of the first epitaxial layers to form a first source/drain feature while the dielectric material fills the first gaps.
US09899268B2	Cap layer for spacer-constrained epitaxially grown material on fins of a FinFET device A method includes forming at least one fin in a semiconductor substrate. A fin spacer is formed on at least a first portion of the at least one fin. The fin spacer has an upper surface. The at least one fin is recessed to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer. A first epitaxial material is formed on the recessed fin. A lateral extension of the first epitaxial material is constrained by the fin spacer. A cap layer is formed on the first epitaxial material. The fin spacer is removed. The cap layer protects the first epitaxial material during the removal of the fin spacer.
US09899267B1	Semiconductor device and manufacturing method thereof A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, a plurality of gate electrodes, and a gate isolation structure. The semiconductor substrate includes a plurality of fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure.
US09899266B2	FinFET structures and methods of forming the same An embodiment is a method including forming a first fin in a first region of a substrate and a second fin in a second region of the substrate, forming a first isolation region on the substrate, the first isolation region surrounding the first fin and the second fin, forming a first dummy gate over the first fin and a second dummy gate over the second fin, the first dummy gate and the second dummy gate having a same longitudinal axis, replacing the first dummy gate with a first replacement gate and the second dummy gate with a second replacement gate, forming a first recess between the first replacement gate and the second replacement gate, and a filling an insulating material in the first recess to form a second isolation region.
US09899264B2	Integrated metal gate CMOS devices A semiconductor device comprises a first semiconductor fin arranged on a substrate, the first semiconductor fin having a first channel region, and a second semiconductor fin arranged on the substrate, the second semiconductor fin having a second channel region. A first gate stack is arranged on the first channel region. The first gate stack comprises a first metal layer arranged on the first channel region, a work function metal layer arranged on the first metal layer, and a work function metal arranged on the work function metal layer. A second gate stack is arranged on the second channel region, the second gate stack comprising a work function metal arranged on the second channel region.
US09899258B1	Metal liner overhang reduction and manufacturing method thereof Overhang reduction methods are disclosed. In some embodiments, a method includes forming a recess in a dielectric layer, the recess defining first sidewalls of the dielectric layer. The method also includes depositing a first conductive layer over an upper surface of the dielectric layer and the sidewalls of the dielectric layer, the first conductive layer having a first overhang, removing the first overhang of the first conductive layer using an etchant selected from the group consisting of a halide of the first conductive layer, Cl2, BCl3, SPM, SC1, SC2, and combinations thereof, and filling the recess with a second conductive layer.
US09899254B2	Forming array contacts in semiconductor memories Array contacts for semiconductor memories may be formed using a first set of parallel stripe masks and subsequently a second set of parallel stripe masks transverse to the first set. For example, one set of masks may be utilized to etch a dielectric layer, to form parallel spaced trenches. Then the trenches may be filled with a sacrificial material. That sacrificial material may then be masked transversely to its length and etched, for example. The resulting openings may be filled with a metal to form array contacts.
US09899251B2	Use of vacuum chucks to hold a wafer or wafer sub-stack Techniques are described for holding a wafer or wafer sub-stack to facilitate further processing of the wafer of sub-stack. In some implementations, a wafer or wafer sub-stack is held by a vacuum chuck in a manner that can help reduce bending of the wafer or wafer sub-stack.
US09899247B2	Container transport facility A storage portion includes a first support portion and a second support portion that support a container. The storage portion is configured to change between a first state and a second state due to the second support portion being raised or lowered. An inert gas supply apparatus includes a connection portion at a height at which the connection portion is connected to the container in the first state and the connection portion is located away from and below the container in the second state. A transport moving body includes a third support portion supporting the container and a protrusion/retraction driving portion that causes the third support portion to protrude and retract. The third support portion is inserted into a transfer space when moved so as to protrude or retract by the protrusion/retraction driving portion. Movement path of the third support portion overlaps with the connection portion in a vertical direction view.
US09899245B2	Conveying method and substrate processing apparatus Provided is a method of conveying a storage container from a placing table to a conveyance place using a conveying mechanism in a substrate processing apparatus. The storage container hermetically stores a substrate and includes a flange portion formed on the top thereof. The conveying mechanism includes a hand portion provided with a flange insertion portion. The substrate processing apparatus is provided with at least two placing tables arranged side by side in a first horizontal direction. The method includes moving the placing table to the conveyance place in the second horizontal direction by a predetermined distance; sliding the hand portion from a side of a placing table neighboring to the placing table in the first horizontal direction such that the flange portion is inserted into the flange inserting portion; and conveying the storage container from the placing table to the conveyance place through the hand portion.
US09899244B2	Liquid processing apparatus, liquid processing method, and storage medium A liquid processing apparatus includes multiple substrate holding units each configured to horizontally hold a substrate and arranged in a left/right direction; a moving unit that is spaced from an arrangement of the substrate holding units in a forward/backward direction and is moved in the left/right direction; a nozzle standby unit, provided between a movement path of the moving unit and the arrangement of the substrate holding units, at which a nozzle that supplies a processing liquid to the substrate held by the substrate holding unit is on standby; and a rotatable arm having one end at which a nozzle holding unit that detachably holds the nozzle and the other end rotatably provided at the moving unit. The nozzle is transferred between the nozzle standby unit and a supply position where the processing liquid is supplied to the substrate together by the moving unit and the rotatable arm.
US09899243B2	Light irradiation apparatus A light irradiation apparatus includes: a rotary holding unit that rotates a substrate around a rotary axis while holding the substrate; a lighting unit positioned to face the rotary holding unit; a light shielding mask positioned between the rotary holding unit and the lighting unit, and widened along a direction orthogonal to the rotary axis; and a driving unit that linearly moves the lighting unit along the direction orthogonal to the rotary axis. The light shielding mask overlaps with the substrate when viewed in the direction of the rotary axis. The light shielding mask has an opening portion. An opening width of the opening portion at a side away from the rotary axis is larger than the opening with near the rotary axis. The lighting unit irradiates light through the opening portion toward the surface of the substrate while being moved above the opening portion by the driving unit.
US09899237B2	Carrier, semiconductor package and fabrication method thereof A fabrication method of a semiconductor package includes the steps of: providing a carrier having a concave portion and a releasing layer formed on a surface thereof; disposing a chip on the releasing layer in the concave portion; forming an encapsulant on the chip and the releasing layer; removing the releasing layer and the carrier; and forming a circuit structure on the encapsulant and the chip. The design of the concave portion facilitates alignment of the chip to prevent it from displacement, thereby improving the product reliability. A semiconductor package fabricated by the fabrication method is also provided.
US09899232B2	Etching method Disclosed is a method for etching an etching target layer which contains silicon and is provided with a metal-containing mask thereon. The method includes: generating plasma of a first processing gas containing a fluorocarbon gas in a processing container that accommodates the etching target layer and the mask to form a fluorocarbon-containing deposit on the mask and the etching target layer; and generating plasma of a second processing gas containing an inert gas in the processing container to etch the etching target layer by radicals of the fluorocarbon contained in the deposit. A plurality of sequences, each including the generating the plasma of the first processing gas and the generating the plasma of the second processing gas, are performed.
US09899229B2	Substrate processing apparatus A substrate processing apparatus includes a phosphoric acid supply device for supplying phosphoric acid aqueous solution onto the upper surface of a substrate held on a spin chuck, a heater for emitting heat toward a portion of the upper surface of the substrate with the phosphoric acid aqueous solution being held on the substrate, a heater moving device for moving the heater to move a position heated by the heater within the upper surface of the substrate, a water nozzle for discharging water therethrough toward a portion of the upper surface of the substrate with the phosphoric acid aqueous solution being held on the substrate and a water nozzle moving device for moving the water nozzle to move the water landing position within the upper surface of the substrate.
US09899221B2	Method for preparing electrode The present disclosure discloses a method for preparing electrode including: providing a substrate; forming a buffer layer on the substrate; forming a patterned photoresist on the surface of the buffer layer away from the substrate, the photoresist has a bottom surface and a top surface disposed opposite and a side connected between the bottom surface and the top surface, the bottom surface is bonded to the buffer layer; by dry etching, the portions of the photoresist not covered by the buffer layer is removed to form a receiving area; depositing a conductive film, the conductive film layer includes a waste material forming on the top surface and an electrode filling in the receiving area; and stripping the waste material and the photoresist. The yields of the method for preparing electrode of the present disclosure is high.
US09899219B2	Trimming inorganic resists with selected etchant gas mixture and modulation of operating variables Provided is a method of trimming an inorganic resist in an integration scheme, the method comprising: disposing a substrate in a process chamber, the substrate having an inorganic resist layer and an underlying layer comprising an oxide layer, a silicon nitride layer, and a base layer, the inorganic resist layer having an inorganic structure pattern; performing an inorganic resist trimming process to selectively remove a portion of the inorganic resist structure pattern on the substrate, the trimming process using a first etchant gas mixture and generating a first pattern; controlling selected two or more operating variables of the integration scheme in order to achieve target integration objectives; wherein the first etchant gas mixture comprises a fluorine-containing gas and a diluent gas; and wherein the target integration objectives include a target critical dimension (CD), a target line edge roughness (LER), a target line width roughness (LWR) and a target substrate throughput.
US09899213B2	Group III nitride semiconductor, and method for producing same On an RAMO4 substrate containing a single crystal represented by the general formula RAMO4 (wherein R represents one or a plurality of trivalent elements selected from a group of elements including: Sc, In, Y, and a lanthanoid element, A represents one or a plurality of trivalent elements selected from a group of elements including: Fe(III), Ga, and Al, and M represents one or a plurality of divalent elements selected from a group of elements including: Mg, Mn, Fe(II), Co, Cu, Zn, and Cd), a buffer layer containing a nitride of In and a Group III element except for In is formed, and a Group III nitride crystal is formed on the buffer layer.
US09899212B2	Methods for depositing a monolayer on a substrate Methods and compositions for depositing a monolayer onto a surface of a substrate are described. The method can include contacting the surface with a vapor phase comprising a carbene source, and reacting a carbene group from the carbene source with a functional group on the surface, to obtain a covalently bound monolayer on the surface of the substrate. The carbene source can be a diazirine compound. The functional group on the surface can be a C—H containing group, a Si—H containing group, among others, or combinations thereof. The method can further involve removing physisorbed molecules from the surface of the substrate.
US09899208B2	Molded leadframe substrate semiconductor package A process for forming land grid array semiconductor packages includes a leadframe that is supported by a substrate comprising mold compound. In some embodiments, at least one die is electrically coupled to the leadframe by bondwires. The package comprises a second mold compound to act as an encapsulant. An apparatus for forming a land grid array semiconductor package includes means for molding a leadframe, assembling thereon at least one semiconductor device, applying a second mold, and singulating to form individual devices. A land grid array package comprises a leadframe, a substrate for supporting the leadframe, at least one semiconductor device and a mold compound.
US09899203B2	Mass spectrometry method and mass spectrometer The present invention is a mass spectrometer (1) for sequentially performing a measurement for a plurality of target ions, characterized by a storage section (41) for holding ion time-of-flight information concerning the time required for each of target ions to fly through each of the sections constituting the mass spectrometer, and a voltage controller (42) for changing, based on the ion time-of-flight information, the voltage applied to each of those sections to a voltage suited for each target ion, with a time lag corresponding to the difference in the timing of the arrival of the target ion at the section concerned.
US09899201B1	High dynamic range ion detector for mass spectrometers The invention relates to the linear dynamic range of ion abundance measurement devices in mass spectrometers, such as time-of-flight mass spectrometers. The invention solves the problem of ion current peak saturation by producing a second ion measurement signal at an intermediate stage of amplification in a secondary electron multiplier, e.g. a signal generated between the two multichannel plates in chevron arrangement. Because saturation effects are observed only in later stages of amplification, the signal from the intermediate stage of amplification will remain linear even at high ion intensities and will remain outside saturation. In the case of a discrete dynode detector this could encompass, for example, placement of a detection grid between two dynodes near the middle of the amplification chain. The invention uses detection of the image current generated by the passing electrons.
US09899197B2	Hybrid extreme ultraviolet imaging spectrometer A hybrid extreme ultraviolet (EUV) imaging spectrometer includes: a radiation source to: produce EUV radiation; subject a sample to the EUV radiation; photoionize a plurality of atoms of the sample; and form photoions from the atoms subject to photoionization by the EUV radiation, the photoions being desorbed from the sample in response to the sample being subjected to the EUV radiation; an ion detector to detect the photoions: as a function of a time-of-arrival of the photoions at the ion detector after the sample is subjected to the EUV radiation; or as a function of a position of the photoions at the ion detector; an electron source to: produce a plurality of primary electrons; subject the sample to the primary electrons; and form scattered electrons from the sample in response to the sample being subjected to the primary electrons; and an electron detector to detect the scattered electrons: as a function of a time-of-arrival of the scattered electrons at the electron detector after the sample is subjected to the EUV radiation or the primary electrons; or as a function of a position of the scattered electrons at the electron detector.
US09899194B2	Apparatus for plasma treatment and method of operating the apparatus Some embodiments of the present disclosure provide a semiconductor manufacturing apparatus. The semiconductor manufacturing apparatus includes a chamber, a support and a liner. The chamber is configured for plasma processes and includes a chamber wall. The support is configured to hold a wafer in the chamber. The liner is configured to surround the support and includes a top side and a bottom side. The top side is detachably hung on the chamber wait. The bottom side includes gas passages for plasma particles to pass through the liner.
US09899193B1	RF ion source with dynamic volume control Provided herein are approaches for dynamically modifying plasma volume in an ion source chamber by positioning an end plate and radio frequency (RF) antenna at a selected axial location. In one approach, an ion source includes a plasma chamber having a longitudinal axis extending between a first end wall and a second end wall, and an RF antenna adjacent a plasma within the plasma chamber, wherein the RF antenna is configured to provide RF energy to the plasma. The ion source may further include an end plate disposed within the plasma chamber, adjacent the first end wall, the end plate actuated along the longitudinal axis between a first position and a second position to adjust a volume of the plasma. By providing an actuable end plate and RF antenna, plasma characteristics may be dynamically controlled to affect ion source characteristics, such as composition of ion species, including metastable neutrals.
US09899191B2	Plasma processing apparatus A plasma processing apparatus includes a processing chamber including a dielectric window; a coil-shaped RF antenna, provided outside the dielectric window; a substrate supporting unit provided in the processing chamber; a processing gas supply unit; an RF power supply unit for supplying an RF power to the RF antenna to generate a plasma of the processing gas by an inductive coupling in the processing chamber, the RF power having an appropriate frequency for RF discharge of the processing gas; a correction coil, provided at a position outside the processing chamber where the correction coil is to be coupled with the RF antenna by an electromagnetic induction, for controlling a plasma density distribution on the substrate in the processing chamber; a switching device provided in a loop of the correction coil; and a switching control unit for on-off controlling the switching device at a desired duty ratio by pulse width modulation.
US09899184B2	Optical vacuum cryo-stage for correlative light and electron microscopy An optical vacuum cryostage for correlative light and electron microscopy comprises a vacuum chamber, an anti-contamination system adapter interface, an electron microscope specimen holder adapter interface, an upper optical window, a lower optical window, a vacuum pumping system adapter interface and a vacuum valve, wherein the anti-contamination system adapter interface is arranged in one end of the vacuum chamber, the electron microscope specimen holder adapter interface is arranged in the other end of the vacuum chamber, the upper optical window is arranged on the upper wall of the vacuum chamber, the lower optical window is arranged on the lower wall of the vacuum chamber and opposite to the upper optical window.
US09899181B1	Collision ionization ion source A collision ionization ion source comprising: A pair of stacked plates, sandwiched about an intervening gap; An input zone (aperture), provided in a first of said plates, to admit an input beam of charged particles to said gap; An output zone (aperture), located opposite said input zone and provided in the second of said plates, to allow emission of a flux of ions from said gap; A gas space, between said input and output zones, in which gas can be ionized by said input beam so as to produce said ions; A supply duct in said gap, for supplying a flow of said gas to said gas space, and comprising: An emergence orifice, opening into said gas space; An entrance orifice, connectable to a gas supply, wherein said duct comprises at least one transition region between said entrance orifice and said emergence orifice in which an inner height of said duct, measured normal to the plates, decreases from a first height value to a second height value.
US09899172B2	Circuit breaker and circuit breaker operating method The invention is intended to provide a circuit breaker or a circuit breaker operating method enabling a current interruption action to be performed efficiently. A circuit breaker is characterized in that includes a fixed contact and a movable contact that comes in and goes out of contact with the fixed contact; a main circuit conductor that is electrically connected to the fixed contact and the movable contact; an operating mechanism including a mover configured by concatenating permanent magnets or magnetic materials alternately having opposite N and S magnetic polarities along the direction of motion axis of the movable contact and magnetic poles disposed to face the N and S magnetic polarities of the mover and wound with windings; a current detector that detects a current flowing through the main circuit conductor; and a control device that varies the amount of a current to be supplied to the windings of the magnetic poles, depending on a current value detected by the current detector.
US09899170B2	Protective circuit for an apparatus A protective circuit for an apparatus includes an accelerometer having an output and a microcontroller coupled to the output of the accelerometer. The protective circuit also includes a switch for controlling the apparatus coupled to an output of the microcontroller and a load coupled to the switch. A power source is coupled to the load and the switch. In operation the microcontroller is cable of sending a signal to the switch to turn of power to the load when a dangerous condition as detected from the accelerometer data has occurred.
US09899169B2	Electric current switching apparatus An exemplary movable contact for an electric switch having a first contact blade and a second contact blade. Each of the first contact blade and the second contact blade includes an assembly hole. The movable contact having an assembly pin wherein the assembly pin includes a separation portion having a diameter greater than the assembly holes of the first and second contact blades thereby keeping the first and second contact blades separated from each other. The assembly pin includes a contact blade portion on each side of the separation portion for insertion to the assembly holes of the contact blades.
US09899168B2	Arc eliminator with earth contact The present invention relates to an arc eliminator, and more particularly, to an arc eliminator with an earth contact. An arc eliminator comprises: a housing; an extinguisher installed on the housing; and an earth contact that is installed on the housing and protrudes out from the housing in such a way as to be connected to the ground bus bar provided inside a distribution board when the extinguisher is moved to a first position where the extinguisher is connected to a fixed bus bar provided inside the distribution board, and to be disconnected from the ground bus bar when the extinguisher is moved to a second position where the extinguisher is disconnected from the fixed bus bar.
US09899167B2	Electrical switching device An electrical switching device is filled with a dielectric insulating medium comprising an organofluorine compound, in particular a fluoroether, a fluoroarnine, a fluoroketone or a fluoroolefin, and comprises at least an arcing contact arrangement with a first arcing contact and a mating second arcing contact. At least a first intermediate volume is provided downstream from the first arcing contact, and/or at least a second intermediate volume is provided downstream from the second arcing contact. The intermediate volumes are for intermediate pressure enhancement and exhaust gas jet formation for turbulent convective heat transfer to metal walls of the exhaust system. In embodiments, the first and/or second intermediate volume is delimited by at least one moveable wall arranged transversally to the longitudinal axis and shiftable parallel to it by an actuation device.
US09899162B2	Keyboard A keyboard includes a base plate, a pressure sensing layer, a first key structure and a second key structure. The pressure sensing layer includes plural pressure sensing regions. Each of the first key structure and the second key structure corresponds to a pressure sensing region. Moreover, the first key structure and the second key structure are located over the corresponding pressure sensing regions. In response to different magnitudes of the depressing force, the corresponding pressure sensing regions are pushed by the first key structure and the second key structure. Consequently, the corresponding pressure sensing regions generate different pressure sensing signals. The pressure sensing layer can replace plural pressure sensing element. Consequently, the assembling process is simplified, and the assembling cost is reduced.
US09899161B2	Method and control system for controlling a switching device A method controls a switching device having at least one phase comprising at least one couple of contacts which can be actuated for switching between a closed condition and an open condition. The method provides control means for controlling the actuation of the at least one couple of contacts, such control means being adapted to operate using time cycles; set the time cycles with a predetermined time duration; detects a difference of a value of a parameter associated to the phase with respect a preset value.
US09899153B2	Barium strontium-titanium (BST) capacitor configuration method A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.
US09899152B2	Electronic component An electronic component capable of suppressing variations in dimension of plating growth of a plating film serving as an external electrode. The external electrodes include plating films formed so as to extend from each of end surfaces to side surfaces of an electronic component body by electrolytic plating. Underlying main electrodes in which the degree of plating growth is relatively high, and underlying sub-electrodes in which the degree of plating growth is relatively low, are formed as a seed electrode serving as a starting point of plating growth for forming a plating film.
US09899151B2	Tensile stress resistant multilayer ceramic capacitor A multilayer ceramic capacitor is configured such that “a” is a distance in a height direction between an effective portion and a first principal surface; “b” is a distance in a length direction between a first end surface and the effective portion in the length direction; “c” is a thickness of the thickest portion of a first base layer provided over the first principal surface; “d” is a distance in the length direction between the thickest portion of the first base layer provided over the first end surface and a portion of the first base layer located over the first principal surface and closest to a second end surface; and “e” is a maximum thickness of a portion of the first base layer provided over the first end surface; and f: the height of the ceramic body, and 2≦(c·d+e·f/2)/(a·b)≦6 is satisfied.
US09899145B2	Winding arrangements in wireless power transfer systems Systems, methods and apparatus for wireless power transfer and particularly wireless power transfer to remote systems such as electric vehicles are disclosed. In one aspect an induction coil is provided comprising a plurality of substantially co-planar coils formed from one or more lengths of conducting material, each length of conducting material being electrically connectable at each end to a power source or battery, and wherein at least one of the lengths of conducting material is continuously wound around two or more of the coils. In another aspect, a method is provided for forming such an induction coil. In yet another aspect, a switching device is operable to alter the configuration of the coils, for example in response to a detected characteristic of another induction coil or device coupled thereto.
US09899138B1	Coil structure for generating a uniform magnetic field and coil apparatus having the same A coil structure for generating a uniform magnetic field and a coil apparatus having the same are disclosed. The coil apparatus has a plurality of coil units, and each of the coil units includes a sub-coil and a plurality of wire sections. The sub-coil has an eccentric-coil portion and two circuit connecting portions. The two circuit connecting portions are respectively connected to two segments of the eccentric-coil portion. The wire sections are arranged in parallel at intervals, are opposite the sub-coil, overlap the sub-coil, and are relatively inclined to the sub-coil. The circuit connecting portions of the segments of the coil units are connected to each other to form an auxiliary coil. A center position of the sub-coils is corresponding to a center position of the auxiliary coil so that a current flows through the sub-coils and the auxiliary coil to generate a uniform magnetic field.
US09899137B2	Method for producing a coil integrated in a substrate or applied to a substrate, and electronic device The subject matter of the invention relates to a method of producing a coil integrated in a substrate, using the following steps: creating the cavity in a substrate, said cavity having an open end which interrupts a surface of the substrate, introducing a paste containing ferromagnetic particles into the cavity so as to produce a coil core, closing the cavity by applying a cover layer so as to bridge the interruption in the surface of the substrate, introducing first winding portions of the coil which are vertical with respect to the surface, with a plurality or all of the first winding portions passing through the coil core contained inside the cavity, and applying second winding portions of the coil onto the surfaces of the substrate, with the second winding portions contacting the first winding portions so as to create the windings of the coil.
US09899136B2	Coil component and method of manufacturing the same A coil component includes a body portion, a coil portion, and an electrode portion. The body portion includes a magnetic material, the coil portion is disposed in the body portion, and the electrode portion is disposed on the body portion and electrically connected to the coil portion. The coil portion includes a first coil layer in which a plurality of conductors having a planar spiral shape are stacked, a second coil layer in which a plurality of conductors having a planar spiral shape are stacked, and a first bump disposed between the first and second coil layers to electrically connect the first and second coil layers to each other. The first coil layer and the second coil layer are electrically connected to each other through the first bump to form a single coil having coil turns adjacent to each other in horizontal and vertical directions.
US09899135B2	Reactor device Provided is a device that reduces loss by means of a large-capacity, three-phase reactor device that eliminates high-frequency components arising in a power controller system used in solar power generation and the like. The present invention is provided with: a yoke core that uses an amorphous ribbon; magnetic leg cores formed into a fan shape using an amorphous ribbon; and a coil wound around the magnetic leg cores. The yoke core is disposed in an approximately hexagonal bottom fastening fixture, the magnetic leg cores are disposed stacked at three equally spaced locations on the inner peripheral surface of the yoke core, the coil is inserted and disposed at the stacked magnetic leg cores, the yoke core is disposed above the magnetic leg cores, the yoke core is covered by an approximately hexagonal top fastening fixture, studs are disposed at the center of the outer periphery of three respectively corresponding sides of the bottom fastening fixture and the top fastening fixture, studs are further disposed at the center of the bottom fastening fixture and the top fastening fixture, the bottom fastening fixture and the top fastening fixture are clamped and affixed by the studs, and furthermore the coil is affixed by a coil affixing fixture disposed at the studs of the three sides.
US09899130B2	Anchoring clamp for an insulated electrical cable An anchoring clamp for an insulated electrical cable, includes a body defining a housing for receiving the cable, a securing loop fastened to the body and configured to be attached to a support, and a cam rotatable relative to the body between a first position in which the cam is at a distance from the housing, and a second position in which the cam is in immediate proximity to the housing and is configured to clamp the cable in the housing, the anchoring clamp being configured to prevent the cam from passing freely from its second position to its first position and including a holding member which is distinct from the body, from the cam and from the securing loop, which is connected both to the body and to the cam and which is configured to prevent the cam from passing freely from its second position to its first position.
US09899125B2	Medium- or high-voltage electrical appliance having a low environmental impact and hybrid insulation The present invention relates to medium- or high-voltage equipment having low environmental impact, including a leaktight enclosure in which there are located electrical components covered with a solid dielectric layer of varying thickness and a gaseous medium for providing electrical insulation and/or for extinguishing electric arcs that are likely to occur in said enclosure, and that comprises heptafluoroisobutyronitrile in a mixture with a dilution gas.
US09899123B2	Nanowires-based transparent conductors A method for forming a transparent conductor including a conductive layer coated on a substrate is described. The method comprises depositing a plurality of metal nanowires on a surface of a substrate, the metal nanowires being dispersed in a liquid; and forming a metal nanowire network layer on the substrate by allowing the liquid to dry.
US09899122B2	Display device connected by anisotropic conductive film A display device connected by an anisotropic conductive film, wherein the anisotropic conductive film has a first z-axis length variation rate of 10% to 90%, as measured using a thermo-mechanical analyzer and calculated according to Equation 1: first z-axis length variation rate=[(L1−L0)/L0]×100(%) (1), wherein, L0 is a z-axis length of the anisotropic conductive film at a heating start temperature, and L1 is a maximum z-axis length of the anisotropic conductive film at 130° C. to 170° C. after being heated, as measured using the thermo-mechanical analyzer.
US09899121B2	Systems and methods for providing overcharge protection in capacitive coupled biomedical electrodes An alternating electric field responsive biomedical composite is disclosed that provides capacitive coupling through the composite. The biomedical composite includes a binder material, a polar material that is substantially dispersed within the binder material, and electrically conductive particles within the binder material. The polar material is responsive to the presence of an alternating electric field, and the electrically conductive particles are not of sufficient concentration to form a conductive network through the composite unless and until the composite becomes overcharged.
US09899114B2	Lead-loaded structured solid organic scintillator A scintillator for imaging using X-rays or gamma rays or charged particles, includes a network of glass capillaries with an inner diameter no greater than 500 micrometers. The capillaries are filled with a polymer material made up of at least: (i) a monomer selected from the group including vinyltoluene, styrene and vinylxylene and the isomers thereof, (ii) a cross-linking agent made up of a dimethacrylate having a central chain which includes 1 to 12 carbon atoms, and (iii) lead dimethacrylate. The cross-linking agent is provided to make up 17 wt % to 60 wt % of the mixture thereof with the monomer, and the lead dimethacrylate makes up at least 5 wt %. The cross-linking agent is provided in a ratio of 1.75 to 2.25 times the weight content of the lead dimethacrylate.
US09899109B2	Treatment apparatus and method for waste steam generator, and installation method of treatment apparatus for waste steam generator Disclosed herein are a treatment apparatus and method for a waste steam generator, and an installation method of a treatment apparatus for a waste steam generator. The treatment apparatus includes a cutting part for cutting a body of a waste steam generator, a driving part for driving the cutting part, and a support frame for supporting the cutting part and the driving part, wherein the support frame is coupled to an outer peripheral surface of the body of the waste steam generator in a divided state, and the cutting part is driven and cuts the body in a state in which the support frame is coupled to the outer peripheral surface of the body. Consequently, since the treatment apparatus is easily moved and installed, an installation time of the treatment apparatus may be shortened and an exposure time of a worker can be reduced.
US09899108B2	Capillary connection through wall penetration A remote seal connection includes an outer sleeve, configured to be inserted through a penetration in a wall and having an outer surface. A capillary is within the outer sleeve and carries a fluid configured to communicate a pressure from a remote seal to a pressure transmitter. A space is provided about the capillary and is positioned between the capillary and the outer sleeve.
US09899106B2	Method and system for providing fuel in a nuclear reactor Exemplary embodiments provide automated nuclear fission reactors and methods for their operation. Exemplary embodiments and aspects include, without limitation, re-use of nuclear fission fuel, alternate fuels and fuel geometries, modular fuel cores, fast fluid cooling, variable burn-up, programmable nuclear thermostats, fast flux irradiation, temperature-driven surface area/volume ratio neutron absorption, low coolant temperature cores, refueling, and the like.
US09899102B2	Semiconductor device and operating method thereof A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.
US09899099B2	Electronic device including fuse element having three or more junctions for reduced area and improved degree of integration A fuse element includes a gate; first to Nth junction regions disposed in an active region, where N is a natural number of 3 or more; and a dielectric layer interposed between the gate and the first to Nth junction regions, wherein a dielectric breakdown between the gate and each of the first to Nth junction regions is independently performed.
US09899096B2	NAND flash memory having multiple cell substrates A NAND flash memory bank having a plurality of bitlines of a memory array connected to a page buffer, where NAND cell strings connected to the same bitline are formed in at least two well sectors. At least one well sector can be selectively coupled to an erase voltage during an erase operation, such that unselected well sectors are inhibited from receiving the erase voltage. When the area of the well sectors decrease, a corresponding decrease in the capacitance of each well sector results. Accordingly, higher speed erasing of the NAND flash memory cells relative to a single well memory bank is obtained when the charge pump circuit drive capacity remains unchanged. Alternately, a constant erase speed corresponding to a single well memory bank is obtained by matching a well segment having a specific area to a charge pump with reduced drive capacity. A reduced drive capacity charge pump will occupy less semiconductor chip area, thereby reducing cost.
US09899095B2	Nonvolatile semiconductor memory device and control method thereof A nonvolatile semiconductor memory device includes a memory cell array having first and second groups of memory strings, each memory string including first and second memory cells connected between select transistors. The nonvolatile semiconductor memory device further includes a first word line connected to the first memory cells of the memory strings, a second word line connected to the second memory cells of the memory strings, and a control unit configured to control application of control voltages to the select transistors and the word lines, such that a select line voltage is applied to the first word line and a non-select line voltage is applied to the second word line and not discharged while select transistors of the first group of memory strings are turned off and select transistors of the second group of memory strings are turned on.
US09899093B2	Semiconductor memory device having memory strings coupled to bit lines and operating method thereof There are provided a semiconductor memory device and an operating method thereof. A semiconductor memory device includes a memory cell array including a plurality of memory blocks, a peripheral circuit for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuit to perform the program operation. The control logic controls the peripheral circuit to perform a verify operation during the program operation and then apply a pre-drain select line voltage to drain select lines of the selected memory block and unselected memory blocks.
US09899092B2	Nonvolatile memory system with program step manager and method for program step management A Solid State Drive (SSD) that includes a host connector receptacle for connecting to a host computer, a plurality of NAND devices and a nonvolatile memory controller. The nonvolatile memory controller is configured to perform program operations and read operations on memory cells of each of the NAND devices. The nonvolatile memory controller includes a program step circuit configured to initially program memory cells of each of the NAND devices using an initial program step voltage and is configured to change the program step voltage used to program the memory cells of each of the NAND devices during the lifetime of each of the NAND devices.
US09899087B1	Content addressable dynamic random-access memory with parallel search functionality An extremely dense, high speed, and low power content addressable DRAM is presented. To enable a parallel searching, a data word to be searched may be driven onto column select lines (CSLs) of a DRAM array. Although two or more primary sense amplifiers typically are not connected at the same time to the same local data line during operation of a DRAM, in various embodiments presented herein, some or all sense amplifiers in a DRAM can be activated simultaneously to enable maximum parallelism with local data line sharing being explicitly allowed. Using this architecture, a data word can be simultaneously searched in all banks and with multiple wordlines. Since no input/output transactions are required and no data needs to be driven from the bank during execution of a search, overall current, and thus power usage, can be reduced.
US09899080B2	Electronic device with semiconductor memory having increased read margin An electronic device including a semiconductor memory. The semiconductor memory may include a cell array including a plurality of resistive storage cells; a current code generation block suitable for generating a current code which has a value corresponding to an average value of current amounts of test currents respectively flowing through at least two first resistive storage cells among the plurality of resistive storage cells, in a test operation; and a sensing block suitable for comparing a read current flowing through a second resistive storage cell selected among the plurality of resistive storage cells with a reference current, and thereby sensing data of the second resistive storage cell, wherein the semiconductor memory is operable to adjust a current amount of at least one current flowing through the sensing block based on the value of the current code.
US09899075B2	Multi channel semiconductor device having multi dies and operation method thereof A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.
US09899074B2	Fine granularity refresh A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.
US09899072B2	Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.
US09899070B2	Modified decode for corner turn Examples of the present disclosure provide apparatuses and methods for performing a corner turn using a modified decode. An example apparatus can comprise an array of memory cell and decode circuitry coupled to the array and including logic configured to modify an address corresponding to at least one data element in association with performing a corner turn operation on the at least one data element. The logic can be configured to modify the address corresponding to the at least one data element on a per column select basis.
US09899066B2	Priority based backup in nonvolatile logic arrays A processing device selectively backups only certain data based on a priority or binning structure. In one approach, a non-volatile logic controller stores the machine state by storing in non-volatile logic element arrays a portion of data representing the machine state less than all the data of the machine state. Accordingly, the non-volatile logic controller stores the machine state in the plurality of non-volatile logic element arrays by storing a first set of program data of the machine state according to a first category for backup and restoration and storing a second set of program data of the machine state according to a second category for backup and restoration.
US09899065B1	Power-on reset circuit and semiconductor memory device having the same Provided herein is a power-on reset circuit and a semiconductor memory device having the power-on reset circuit. The power-on reset circuit may include a reference voltage generation circuit configured to generate a reference voltage using an external supply voltage that is externally input, and a power-on reset signal generation circuit configured to generate a power-on reset signal by sensing a potential level of the reference voltage when the external supply voltage increases to a set level or more. The power-on reset signal generation circuit may be configured to, when the reference voltage changes depending on the temperature variation, control a sensing level to compensate for the change in the reference voltage.
US09899064B2	Apparatuses and methods for shifting data The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage.
US09899060B2	Recording medium, reproducing apparatus, and reproducing method In a recording medium on which is recorded a multiplexed stream including a plurality of first packets (V_main) constituting a first I-picture in a first video stream and a plurality of second packets (V_sub) constituting a second I-picture in a second video stream, information for identifying the first I-picture and information for identifying the second I-picture are recorded on the medium. A recording medium can thereby be obtained that enables the rapid detection, from a small amount of information, of a particular picture included in a stream such as a TS in which multiple content streams are multiplexed.
US09899059B2	Method of management of a multimedia program, server, terminals, signal and corresponding computer programs The invention relates to a method for managing a multimedia program, played back by a terminal of a user.According to the invention, such a method comprises the following steps: playback (201) of said multimedia program, by a terminal; obtaining (205) of a marking cue relating to an instant of playback of said multimedia program, associated with a marking request generated by order of a user of said terminal; use (209) of said marking cue to play back said multimedia program later starting from said instant of playback.
US09899058B2	Method for the reproduction of a film The present invention relates to a method for the reproduction, through an audio/visual means, of a film and an apparatus for the reproduction of the same. More particularly, the method according to the present invention allows more viewings of the same film such that the film itself is automatically composed as to be different at each viewing. The method for the reproduction of a film is finalized to the creation of a “multifilm”, i.e. a film that changes its plot in every reproduction.
US09899057B2	Control method for synchronized video, control system for synchronized video and electronic apparatus thereof A control method for synchronized video, a control system for synchronized video and an electronic apparatus thereof are provided. The control method for synchronized video includes the following steps. A video file corresponding to an operating instrument is obtained and displayed. Whether a control instruction corresponding to a current video frame of the displayed video file exists is determined. When the control instruction corresponding to the current video frame exists, the control instruction is obtained. Further, the control instruction is output to the operating instrument to control the operating instrument.
US09899056B1	In-circuit calibration of anti-aliasing filter A computer-implemented method, according to one embodiment, includes, performing anti-aliasing filtering on each of a plurality of symmetrical square wave signals, each symmetrical square wave signal having a frequency that is a different fraction of a frequency of a data read clock. The filtered symmetrical square wave signals are passed through a band pass filter. An amplitude of each of the symmetrical square wave signals is measured after the band pass filtering. In response to the amplitudes of the symmetrical square wave signals being within a predefined range, anti-aliasing settings used during the anti-aliasing filtering are stored. In response to the amplitudes of the symmetrical square wave signals being outside the predefined range, the anti-aliasing settings are changed.
US09899055B1	Optical storage system divider based draw verification An optical storage system includes an optical head and controller arrangement. The arrangement is configured to write data to an optical medium via a higher power main beam, to read, directly after writing, feedback from the medium containing the written data and noise resulting from the higher power main beam, to remove the noise from the feedback by dividing the feedback with data indicative of the higher power main beam, and to generate output indicative of the written data.
US09899044B2	Magnetoresistive element, magnetic head using magnetoresistive element, and magnetic reproducing device The present invention addresses the problem of providing an element which uses the current-perpendicular-to-plane giant magnetoresistance (CPPGMR) effect of a thin film having the three-layer structure of ferromagnetic metal/non-magnetic metal/ferromagnetic metal. The problem is solved by a magnetoresistive element provided with a lower ferromagnetic layer and an upper ferromagnetic layer which contain a Heusler alloy, and a spacer layer sandwiched between the lower ferromagnetic layer and the upper ferromagnetic layer, the magnetoresistive element being characterized in that the spacer layer contains an alloy having a bcc structure. Furthermore, it is preferable for the alloy to have a disordered bcc structure.
US09899043B2	Methods of forming near field transducers and near field transducers formed thereby A method of forming a near field transducer (NFT), the method including the steps of depositing a plasmonic material; depositing an encapsulant material on at least a portion of the plasmonic material; and implanting ions into at least a portion of the plasmonic material through the encapsulant material.
US09899038B2	Electronic notebook system An electronic notebook system is described that comprises a housing, a computing device, wireless interfaces, antennas, sensors, a touch display configured to receive input via a stylus and/or human digit input, the stylus comprising a pressure and/or an inclination sensor, a microphone, camera, the notebook system configured to provide a user condition interface, receive a user selection of a first user condition, provide an interface configured to receive user details, receive audible user details via the microphone, convert the audible user details received via the microphone to text, perform natural language processing to identify text keywords utilizing sentence segmentation, part-of-speech tagging, paraphrase recognition, and/or co-reference resolution, identify a condition based at least in part on the identified one or more keywords, dynamically generate an alert based at least in part on the identified condition, wirelessly transmit the generated alert to one or more destinations via at least a first wireless interface and antenna.
US09899036B2	Generating a reference audio fingerprint for an audio signal associated with an event An audio identification system generates a reference audio fingerprint associated with an event. The reference audio fingerprint is generated from samples of an audio signal associated with the event captured by multiple devices. To generate the reference audio fingerprint, fingerprints are generated from each sample, and the generated fingerprints are temporally aligned. Fingerprints associated a temporally overlapping portion of the audio signal are averaged, and the average value is associated with the temporally overlapping portion of the audio signal and included in the reference audio fingerprint. The reference audio fingerprint is stored along with identifying information, such as an event name, an event time, an event date, or other information describing the event associated with the audio signal from which the samples were captured.
US09899034B2	Technologies for robust crying detection using temporal characteristics of acoustic features Technologies for identifying sounds are disclosed. A sound identification device may capture sound data, and split the sound data into frames. The sound identification device may then determine an acoustic feature vector for each frame, and determine parameters based on how each acoustic feature varies over the duration of time corresponding to the frames. The sound identification device may then determine if the sound matches a pre-defined sound based on the parameters. In one embodiment, the sound identification device may be a baby monitor, and the pre-defined sound may be a baby crying.
US09899032B2	Systems and methods of performing gain adjustment A method of performing gain adjustment in an electronic device includes determining a first set of spectral frequency values and determining a second set of spectral frequency values. The first set of spectral frequency values corresponds to a high-band portion of an audio signal received at the electronic device. The second set of spectral frequency values approximates the first set of spectral frequency values in the high band portion of the audio signal. The method includes estimating a spectral distortion corresponding to a difference between the first set of spectral frequency values and the second set of spectral frequency values and adjusting, based on the spectral distortion, a gain value corresponding to at least a portion of the audio signal. The method also includes transmitting an encoded bitstream that includes information corresponding to the adjusted gain value and the second set of spectral frequency values.
US09899028B2	Information processing device, information processing system, information processing method, and information processing program An information processing device includes a first information processing unit, a communication unit, and a control unit. The first information processing unit performs predetermined information processing on input data to generate first processing result data. The communication unit is capable of receiving second processing result data generated by a second information processing unit capable of executing the same kind of information processing as the information processing on the input data under a condition with higher versatility. The control unit selects either the first processing result data or the second processing result data according to the use environment of the device.
US09899013B1	Forward and reverse delay effects pedal The invention pertains generally to an effects pedal employing multiple sub-buffers implementing a switching mechanism between forward and reverse delay effects, particularly useful in the music industry.
US09899012B2	Thumb-mountable support for enhancing support and control of an instrument of the violin-family A thumb-mountable support is disclosed for use on a support hand of a musician while playing an instrument of the violin-family. The thumb-mountable support includes a thumb ring and a saddle. The thumb ring is configured to at least partially surround the thumb of the support hand to facilitate securement of the thumb-mountable support to the thumb of the support hand. The saddle extends from the thumb ring and includes a lower surface configured to engage a generally V-shaped region formed between a thumb and body of the support hand, and also includes an upper surface configured to support a rear portion of a neck of the instrument.
US09899010B2	Aid for playing a stringed musical instrument This invention relates generally to an aid for playing a stringed instrument in the form of a glove comprising a plectrum protruding from the glove thumb tip and/or from one or more of the glove finger tips. The field of use in hand devices for playing stringed instruments. The aid for playing a stringed musical instrument, comprises: a glove with a glove thumb comprising a thumb plectrum rigidly connected to a rigid thumb portion of the glove thumb, wherein the rigid thumb portion encircles or partially encircles the glove thumb to hold the thumb plectrum snug on a thumb of the glove wearer.
US09899007B2	Adaptive lossy framebuffer compression with controllable error rate The device and method described in this application relate generally to graphics processing systems utilizing the tile based rendering technique and more specifically relate to the processing of the framebuffer data in graphics processing applications. The present invention discloses techniques to reduce the bandwidth needed to access the color data stored in the framebuffer. A method for adaptive lossy delta based compression of color data is disclosed. The error rate, that is the amount of color data lost during the lossy compression process, is controlled by various parameters of the rendered tiles produced by the graphics processing system. The compression process is driven by a dedicated unit which enables informed compression decisions with controllable error rate so as the output color data can be reliably decompressed to produce the original color data with minimal or no errors.
US09899006B2	Eye mounted displays and systems, with scaler using pseudo cone pixels A display device is mounted on and/or inside the eye. The eye mounted display contains multiple sub-displays, each of which projects light to different retinal positions within a portion of the retina corresponding to the sub-display. The projected light propagates through the pupil but does not fill the entire pupil. In this way, multiple sub-displays can project their light onto the relevant portion of the retina. Moving from the pupil to the cornea, the projection of the pupil onto the cornea will be referred to as the corneal aperture. The projected light propagates through less than the full corneal aperture. The sub-displays use spatial multiplexing at the corneal surface. Various electronic devices interface to the eye mounted display.
US09899002B2	Information processing methods for displaying parts of an object on multiple electronic devices The present disclosure discloses an information processing method and an electronic device, solving the technical problem that it needs to write additional special codes to enable executing an application program in two or more electronic devices simultaneously and enable displaying output content collectively on two or more display units. The method includes: acquiring data of a first part of a first object needed to be displayed on the first display unit, wherein, data of a second part in the first object different from the data of the first part is determined to be displayed on a second display unit; synchronizing, by the first electronic device, with the second electronic device; and displaying the data of the first part on the first display unit by the first electronic device synchronously executing a first application program corresponding to the first object while displaying the data of the second part on the second display unit by the second electronic device executing the first application program.
US09899001B2	Display panel, display device having the same, and controlling method thereof The present application discloses a display panel comprising a first substrate; a second substrate opposite to the first substrate; a liquid crystal layer between the first substrate and the second substrate; and an organic light emitting structure on a side of the second substrate distal to the liquid crystal layer. The organic light emitting structure comprises a light reflective layer for reflecting ambient light.
US09899000B2	Display, display control method, display control device, and electronic apparatus A display device configured to display at least one image. The display device includes at least one light emitter configured to emit a plurality of colored light beams, each of the plurality of colored light beams being a respective color different than the others; and a light emission controller configured to determine, based on at least one characteristic of the at least one image, one or more light beams of the plurality of colored light beams to emit in a frame period corresponding to the at least one image.
US09898992B2	Area-saving driving circuit for display panel The present invention relates to an area-saving driving circuit for a display panel, which comprises a plurality of digital-to-analog converting circuits convert input data, respectively, and produce a pixel signal. A plurality of driving units are coupled to the plurality of digital-to-analog converting circuits, respectively. They produce a driving signal according to the pixel signal and transmit the driving signal to the display panel for displaying. A plurality of voltage booster units are coupled to the plurality of driving units, respectively, and produce a supply voltage according to a control signal. Then the supply voltage is provided to the plurality of driving units. Thereby, by providing the supply voltage to the plurality of driving units of the display panel by means of the plurality of voltage booster units, the area of the external storage capacitor is reduced. Alternative, the external storage capacitor can be even not required.
US09898991B2	Shift register, gate driver and display device Provided are a shift register, a gate driver and a display device capable of eliminating voltage coupled noise at an output terminal. The shift register comprises a pulling-up unit, a clock control unit, a resetting unit, an inverting unit and a pulling-down unit; the pulling-up unit is connected with a shift trigging signal terminal, a high level signal terminal and the resetting unit; the clock control unit is connected with the pulling-up node, a clock signal terminal and the pulling-down unit; the resetting unit is connected with a reset signal terminal, a low level signal terminal, the pulling-up node and the output terminal; the inverting unit is connected with the high and low level signal terminals, the pulling-up node and the pulling-down unit; the pulling-down unit is connected with the pulling-up node, the pulling-down node, the low level signal terminal, the shift trigging signal terminal and the output terminal.
US09898989B2	Gate driver on array (GOA) circuit and liquid crystal display apparatus having the GOA circuit The disclosure discloses a GOA circuit and a liquid crystal display apparatus. The GOA circuit includes a number of GOA unit in cascade connection, wherein the Nth level GOA unit includes a common signal point control module, a gate signal point control module, and a GAS signal operation module; wherein the common signal point control module is used to pull up the electrical level of the common signal point after the period of all gate on; a gate signal point control module is used to pull down the electrical level of a gate signal point after the period of all gate on; the GAS signal operation module is used to achieve the all gate on function by a first GAS signal and a second GAS signal to control the output of the Nth level gate driving signal in the touch panel scanning period.
US09898987B2	Gate driving circuit A gate driving circuit is provided, where includes a plurality of gate driving units connected in cascade, each of the gate driving units is used to drive two scan lines arranged continuously, a gate driving signal of a first scan line and a first cascading signal are respectively transmitted by a first pull up module and a first down transmitting module, and a gate driving signal of a second scan line and a second cascading signal are respectively transmitted by a second pull up module and a second down transmitting module. By the above manner, the disclosure is capable of decreasing a component quantity of GOA circuit, thus achieving the ultra-narrow frame design.
US09898983B1	Source driving device with 3 types of gate oxide layer A source driving device for a display system includes a receiving module, for receiving display data; a register module, for sorting pixel data included in the display data to generate sorted pixel data; a latch module, for outputting sequenced display data to the level shifting module; a level shifting module, for adjusting the sequenced display data from a low voltage range to a medium voltage range; a converting module; for converting the sequenced display data to analog display voltages; a buffer module, for generating a plurality source driving signals according to the analog display voltages; and an output switching module, for outputting the plurality source driving signals to a display device of the display system operating in a high voltage range; wherein circuit components in the source driving device operating in different voltage ranges have different gate oxide thicknesses.
US09898982B2	Display method, device and computer-readable medium A display method, device and computer-readable medium are provided. The method includes: detecting whether there is any change in a displayed content for the display; and controlling the display to alternately update display data corresponding to a first portion and a second portion of display units in each row if it is detected that the displayed content does not change, wherein the display unit comprises n rows of pixels, and wherein n is a positive integer. The first portion of the display units comprises i first cells, the second portion of the display units comprises j second cells, and the first cells are alternate with the second cells, wherein i and j are positive integers. Moreover, the first cell comprises p successive pixels, and the second cell comprises q successive pixels, wherein p and q are greater than 1.
US09898980B2	Display apparatus A display apparatus includes a plurality of pixels arranged in columns and rows in a display area, a data line extending in a first direction and connected with pixels of a k-th column (‘k’ is a natural number) and a (k+1)-th column, a gate line extending in a second direction crossing the first direction and connected with ones of the pixels, a gate signal line extending in the first direction and connected with the gate line, and a gate driver in a first peripheral area adjacent to a first longer side of the display area and having a first width, and configured to apply a gate signal to the gate line.
US09898978B2	Liquid crystal panels and the driving circuits thereof The present disclosure relates to a liquid crystal panel and the driving circuit. The liquid crystal panel includes a plurality of source driving circuits and a plurality of sub-pixel rows extending along a row direction. Each of the sub-pixel rows includes a plurality of sub-pixels of different colors and the sub-pixels are arranged periodically along the row direction. Within one scanning frame, polarity of driving voltage of at least one sub-pixel within the arranging period is opposite to that of other sub-pixels. Each of the source driving circuit includes at least two output ends respectively connecting to at least two sub-pixels having the same polarity of driving voltage within the same scanning frame to provide the driving voltage of the same polarity to the at least two sub-pixels. In this way, the power consumption of the source driving circuit may be reduced.
US09898976B2	Color shift compensation method and device The color shift compensation method comprises: receiving target input gray scale data of a target sub pixel dot in a present line, and acquiring previous output gray scale data of a sub pixel dot of the previous line in the same display data line of the target sub pixel dot, and then, implementing digital to analog conversion to the target output gray scale data of the target sub pixel dot simultaneously corresponding to the target input gray scale data and the previous output gray scale data with combination of the target relationship table to acquire the target voltage of the target sub pixel dot, and ultimately, adjusting a color displayed by a target pixel where the target sub pixel dot is. With the present invention, the color shift issue due to the resistance difference of the fan section can be solved to promote the display effect.
US09898974B2	Display drive scheme without reset This disclosure provides systems, methods and apparatus for a display drive scheme without a reset. In one aspect, a first voltage can be applied to an electrode of a display unit to position a movable element from a first position towards a second position, and a second voltage can be applied to the electrode of the display unit to position the movable element to the second position.
US09898972B2	Field-sequential display panel, field-sequential display apparatus and driving method A field-sequential display panel, a field-sequential display apparatus and a driving method are provided. The field-sequential display apparatus includes a liquid crystal display panel and an OLED light source arranged at one side of the liquid crystal display panel where light is incident to provide trichromatic light for pixel cells of the liquid crystal display panel. The OLED light source includes multiple groups of trichromatic light sources, each of the groups of trichromatic light sources includes a first color sub-light source, a second color sub-light source and a third color sub-light source, and each sub-light source includes an anode, a cathode and a light emitting layer between the anode and the cathode.
US09898971B1	System, method, and apparatus to selectively control brightness of liquid crystal display The disclosure relates to a system, a method, and an apparatus to selectively control brightness of information displayed on a Liquid Crystal Display (LCD). A graphics layer can be provided in a display area of the LCD, and a semi-transparent mask layer can be provided above the graphics layer. An information graphics layer can be provided above the semi-transparent mask layer. The information graphics layer can be controlled to selectively display predetermined information on the LCD at an intended brightness, while remaining information from the underlying graphics layer can be dimmed relative to the brightness of the display predetermined information by activation of the semi-transparent mask layer.
US09898970B2	Voltage providing circuit with power sequence controller and display device including the same A display device includes a data driver configured to generate a data signal based on a data voltage; a display panel configured to be driven based on a first power supply voltage and the data signal; a timing controller configured to control operations of the data driver and the display panel and configured to generate a ready signal indicating a power supply timing; a first voltage regulator configured to generate the first power supply voltage based on a first input voltage and a first enable signal; a second voltage regulator configured to generate the data voltage based on the first input voltage and a second enable signal; and a power sequence controller configured to generate the first enable signal based on the ready signal and the data voltage and configured to generate the second enable signal based on the ready signal and the first power supply voltage.
US09898969B2	Drive control device, display device including the same, and drive control method Low frequency drive is performed that provides, after a charging period for refreshing a screen, a pause period for pausing the refresh. The length of the charging period is, for example, one frame and the length of the pause period is, for example, 59 frames. When new image data IMD is transmitted from a host to an LCD driver IC during the pause period, an interrupt process where the pause period is allowed to transition to the charging period is performed immediately thereafter. By performing the interrupt process, without waiting for the pause period with the predetermined length to end, the next charging period where refresh based on the new image data IMD is to be performed starts.
US09898967B2	Driving voltage control method and apparatus,array substrate, and display device A driving voltage control method and apparatus, an array substrate, and a display device, wherein a plurality of predetermined areas (11a) are preset within a display area (11), and corresponding to any of the predetermined areas, the apparatus comprises an acquisition module (21) configured to acquire a luminance value of a pixel cell with the maximum luminance within the predetermined area (11a) in any frame, a search module (22) configured to search a preset table for a corresponding driving voltage value according to the luminance value acquired by the acquisition module and a control module (23) configured to control a driving voltage outputted to all the pixel cells within the predetermined area (11a) in a next frame according to the driving voltage value obtained by the search module. The driving voltage for the display device in any image can be reduced without affecting the display effect of the image.
US09898965B2	Pixel driving circuit, pixel driving method and display apparatus The present disclosure provides a pixel driving circuit, a pixel driving method and a display apparatus. The pixel driving circuit includes a pre-charging control unit, a storage capacitor, a driving transistor and a threshold compensation unit. The pre-charging control unit charges the storage capacitor by a supply voltage during a pre-charging period; the threshold compensation unit during the threshold compensation period, together with the driving transistor and under the control of the control signal, controls the storage capacitor to be discharged until a voltage of the second electrode of the driving transistor becomes Vdata+Vth; and during a light-emitting period, control a gate-source voltage of the driving transistor to compensate for Vth, where Vth is a threshold voltage of the driving transistor, and Vdata is a voltage of the data signal.
US09898964B2	Array substrate and display apparatus There are provided an array substrate and a display apparatus. The array substrate comprises a voltage driving circuit (1) for driving display pixels to display images, a current sensing circuit (2), and further comprises test pixels (3), a current comparison circuit (4), and a voltage compensation circuit (5), wherein the current sensing circuit (2) is connected to the test pixels (3) and the current comparison circuit (4), and the current comparison circuit (4) is connected to the voltage compensation circuit (5); the current comparison circuit (4) compares the current value of the current sensed by the current sensing circuit and flowing through the test pixels (3) with a set threshold, and outputs the comparison result to the voltage compensation circuit (5); and the voltage compensation circuit (5) compensates for the driving voltage of the voltage driving circuit (1) when the current value is smaller than the set threshold. The array substrate can compensate for the current of the display pixels to avoid occurrence of the pixel degradation.
US09898950B2	Display panel device A display panel and an electronic device are provided. The display panel includes: multiple pixel units arranged in an array; multiple data lines for providing data signals for the pixel units; multiple gate lines for providing gate scanning signals for the pixel units; and at least one enhancing region, where at least one gate signal enhancing transistor and at least one of the pixel units are disposed in the enhancing region, the gate signal enhancing transistor is configured to pre-charge a gate line for a pixel row where the gate signal enhancing transistor is located. An electronic device including the display panel has a quick response speed and a narrow border region.
US09898946B2	Magnetic scanning device and method for image generation A magnetic scanning method includes acquiring an image from a storage device of a magnetic scanning device, controlling a magnetic read-write head of the magnetic scanning device to touch a reference point on a plane, generating an electric signal which reflects relevant information of the acquired image, inputting the electric signal reflecting the relevant information of the acquired image to the magnetic read-write head, when the electric signal reflecting the relevant information of the acquired image flows through the magnetic read-write head, controlling the magnetic read-write head to generate a magnetic field corresponding to the electric signal, controlling the magnetic read-write head to move and scan the plane from the reference point, to magnetize the magnetic powder on the plane by the magnetic field, and driving the magnetic powder to move relatively to generate an image similar to the acquired image.
US09898944B2	Detecting circuit, detecting method and display device The present invention provides a detecting circuit, a detecting method and a display device, and the detecting circuit includes data signal input buses, switching units and control units, wherein the data signal input buses are used to provide data signals to the data lines and a predetermined number of data lines corresponding to a central region of the display panel constitute a first data line group; the switching units are arranged between the data lines and corresponding data signal input buses, all of which are divided into two switching unit groups, and all switching units in correspondence with the data lines in the first data line group constitute a first switching unit group; and the control units are used to control all switching units of corresponding switching unit groups to be turned on or turned off simultaneously.
US09898941B2	Modular flush-mount sign channel track system and method A system and method for magnetically mounting a sign flush at a ceiling, window, or wall location that includes modular panels that are removably connected to one another to form a sign board stack. The sign board stack is mounted or unmounted from a prominent display location using a pole end gripper without the need for a ladder. The sign stack extends from a mounting strip having a holder at which the sign stack is fastened, and the gripper engages the mounting strip at an offset grasping portion disposed laterally of the holder. The panels have flanges at the top edge to fit into the holder of the mounting strip and clips at the bottom edge to hold a flange of a panel connected below it. Channel tracks are formed on the panels to hold strip sign elements, some of which may include accordion or spiral bound numbers or messages.
US09898940B2	Ladderless cleat and track banner hanger for vertical surface A track and cleat system includes a track attached by suction cups or other means to a window or other vertical surface. The track has a projection onto which a cleat is attached. The cleat includes a track receiving opening that fits onto the track. A banner holder is provided adjacent to the track receiving opening. The banner holder may use friction grips or magnets to hold a banner, sign or display. The cleat has an offset grip portion in a T-shape that is spaced from the banner holder and gripped by a gripper on a pole to move the banner and cleat to a display position on the track and to remove the banner and cleat from the display position by removing the cleat from the track. Various banner holding devices are provided, as well as various track and cleat shapes and various means of attachment.
US09898925B2	Method for operating a field device A method for operating a field device, wherein at least one command that is in line with a communication protocol for operating a field device is sent from a higher-order unit to a field device by sending the command to an operating unit by means of a first bearer protocol and by transmitting the command from the operating unit to the field device by means of a second bearer protocol.
US09898916B2	Alarm system A system including a working environment and a control center separated from the working environment and configured to monitor systems in the working environment, the control center having an odor alarm system configured to deliver at least a first odor to the control center and alert an operator to an alert condition. In an embodiment, the odor alarm system is configured to deliver a second odor associated with a second alarm condition, wherein the first alarm condition is different than the second alarm condition. In an embodiment, the odor alarm system is configured to be used in conjunction with the one or more visual or audio alarm systems.
US09898915B2	Tracking and monitoring apparatus and system A programmable mobile unit for a portable host, such as a person, comprising a microcontroller in communication with each of a detachable freespace communication module for communication with a control center, a GPS unit for communication with at least a GPS satellite system and a biometric sensor for monitoring and identifying the host.
US09898912B1	Systems and methods for automatically generating an escape route Methods and systems for generating escape routes are provided. With a home owner's or insured's permission, a smart home controller or insurance provider remote processor may analyze data received from a plurality of smart devices disposed on, within, or proximate to a home, as well as data received from an insurance provider. If it is determined that an emergency situation necessitating an evacuation exists, the smart home controller or insurance provider remote processor may automatically generate escape routes to guide occupants to safety. The smart home controller may then transmit the generated escape routes to inform occupants of emergency situation and how to reach safety. The smart home controller and/or insurance provider may also issue commands to smart devices to ensure the safety of the generated escape routes. Insurance policies, premiums, or discounts may be adjusted based upon the escape route determination functionality.
US09898911B2	Fire detecting device including metal-insulator transition (MIT) device molded by clear compound epoxy The inventive concept provides MIT devices molded by clear compound epoxy and fire detecting devices including the MIT device. The fire detecting device is supplied with a power source from a power control device. The fire detecting device includes a MIT device including a MIT chip molded by a clear compound epoxy, a diode bridge circuit supplied with the power source from the power control device for providing a non-polar power source, a notice circuit supplied with the non-polar power source from the diode bridge circuit for warning of a fire alarm in response to a detecting signal from the MIT device, and a stabilization circuit for maintaining the detecting signal for a certain period.
US09898909B2	Method and apparatus for tamper detection An apparatus secured to a device includes a fastener, an adhesive secured to the fastener, an electric circuit configured to measure a property, a memory configured to store the property, and at least one Key to access the stored property, wherein the apparatus is configured to detect an unauthorized opening of the device.
US09898907B1	Theft-prevention exhibition device and method A theft-prevention exhibition device includes a first unit, which comprises a microprocessor, a radiofrequency (RF) transceiver, a first alarm, a first switch, a power source, wherein the microprocessor is electrically connected with the RF transceiver, the first alarm, and the first switch; a second unit, which comprises a memory, a magnetic induction coil, and a wire retractor; a connecting plate adapted to be connected to a display item, wherein the connecting plate comprises a second switch; a wire rope spooled on the wire retractor and connected to the connecting plate, wherein the wire rope connects with the second switch, the memory, and the magnetic induction coil to form a circuit.
US09898905B1	Apparatus and method for a balcony access status alert system A barrier that is releasably secured across an ingress/egress to a balcony or other elevated platform. The barrier is a fence-style assembly that has a pair of vertical posts that are releasably secured within respective boots secured to the floor. One of the boots includes a switch-activated transmitter that is inactive when the respective post is seated in the boot. If the post is pulled out of the boot, the switch-activated transmitter transmits a wireless signal to a transceiver located on the barrier which then transmits a signal to an on-site controller that transmits respective text messages to authorized personnel informing them of the barrier removal and restoration and will continue to do so until the barrier status changes. The transceiver may be housed within a housing that also contains a visual and/or audible warning at the barrier vicinity to warn those in the vicinity of the barrier removal.
US09898894B2	Method of managing a lottery A method is provided of managing awards to players in a lottery where players purchase lottery access tickets, each of which is assigned a predetermined prize in the lottery and each of which provides access to a selected one of a series of accessible video games on a computer medium. Each game has a plurality of game images in which the player can enter a selected action from a number of options based on different skill levels where the selected action can have a token value different from other options. The system displays a table to the player of an accumulation of the tokens and controls the accumulation of the tokens in order that the final prize matches the predetermined prize but may allow other awards to more skilled players. The prize must be validated using a code from the ticket and from an image in the displayed game.
US09898892B2	System and method of modifying attribute values of game entities based on physical token detection Users may participate in instances of a virtual space through computing platforms associated with the users. User participation may include controlling game entities within the instances of the virtual spaces. Individual game entities may be defined by attribute values of one or more game entity attributes. One or more attribute values may be modified from their currently defined values based on detection of physical tokens communicatively coupled to token readers. By way of non-limiting example, tokens may store attribute modification information that may specify discrete amounts by which one or more attribute values may be changed.
US09898891B2	Gaming system with linked gaming machines that are configurable to have a same probability of winning a designated award A gaming system that is controlled by a central controller and includes a plurality of gaming machines. Each of the gaming machines includes a game operable upon a wager by a player, a plurality of winning symbol combinations including a designated winning symbol combination and a probability of achieving the designated winning symbol combination. At least two of the gaming machines have different probabilities of achieving the designated winning symbol combination. The gaming system includes a designated award and a triggering event. After an occurrence of the triggering event, the central controller is programmed to change the probability of achieving the designated winning symbol combination for at least one of the gaming machines such that each gaming machine has an equal probability of generating the designated winning symbol combination.
US09898890B2	Methods and systems for determining a batch run of sessions In accordance with some embodiments, a batch run of sessions is executed. The batch run comprises a plurality of sessions characterized by at least one common parameter and value thereof. A session comprises a plurality of outcomes of a wagering game. A video presentation may be created based on each such session of a batch run. The video presentation may be recorded onto a game disc (e.g., a DVD or CD-ROM) and sold to a player for viewing at a location remote from a casino.
US09898889B2	Remote game play in a wireless gaming environment A system employs a server computing system with an integrated database and wireless communications devices. The wireless communications devices permits players to take a position on a potential outcome of a game and includes remote game play and remote backline playing (taking a position on a potential outcome of a position on game outcome taken by a primary player occupying a player position at a gaming table) and other types of positions not involving money. In response to the electronic indication that the primary player is no longer occupying the player position at the gaming table the system automatically initiates a period locking out players taking positions on the potential outcome of the game such as a position on game outcome lock out period for such proposed backline positions on game outcome and modifies the user interface on a wireless device of the dealer accordingly.
US09898888B1	Slot machine with isometric symbols A method, apparatus, and computer readable storage to implement slot machine game that uses isometric symbols. The isometric symbols scroll on the screen in three-dimensions which also accommodate for hidden line removal. The game can be displayed on a traditional two-dimensional output device or an autostereoscopic display.
US09898886B2	Methods and apparatus for providing communications services at a gaming machine In a first aspect, a method is provided that includes the steps of (1) providing an auxiliary unit adapted to allow a gaming machine to be retrofitted to provide communications services; and (2) retrofitting a non-communications-enabled gaming machine with the auxiliary unit so that the non-communications enabled gaming machine is adapted to provide communications services based on game play at the non-communications-enabled gaming machine. Numerous other aspects are provided.
US09898882B1	System and method for customized message playback Various aspects of a system and method for customized message playback are disclosed herein. The system includes a first electronic device, which is configured to detect one or more physiological and/or behavioral characteristics of a first user. Thereafter, one or more attributes associated with the detected one or more physiological and/or behavioral characteristics of the first user are determined. One or more media items are retrieved from a plurality of media items in accordance with the determined one or more attributes. The retrieved one or more media items are played back at the first electronic device for the first user and/or a pre-registered second electronic device for a second user.
US09898877B2	Apparatus and method for operating same An apparatus and a method for using an apparatus are provided, which apparatus can be used in particular in an industrial automation process. The apparatus comprises a machine part for performing a process to be performed by an automation system or for processing a workpiece, and an authentication and access part for authenticating a user of the apparatus and for permitting the user access to at least some of the functions of the machine part if the user has been authenticated, and for blocking the user access to the functions of the machine part if the user has not been authenticated.
US09898876B2	Method and apparatus for vehicle usage recording A computer-implemented method of providing suggested entries for a candidate journey in a vehicle logbook, comprising selecting one or more neighbour journeys based on a location of one or more end-points of the candidate journey and the one or more neighbour journeys, determining an accuracy value indicative of a match between each neighbour journey and the candidate journey based on one or more attributes of each neighbour journey and the candidate journey, and providing at least one suggested entry for the candidate journey in the vehicle logbook based on the accuracy value associated
US09898873B2	Methods and systems for processing 3D graphic objects at a content processor Method and systems for processing at least one three-dimensional (3D) graphic object include: identifying a change of 3D graphic objects, creating a message, assigning a unique identifier; and forwarding the message and the unique identifier to a scene engine. The change is made by an authoring tool. The message is embedded with change information corresponding to the change. The scene engine functions can be performed by the same or a different computing device as the computing device performing the authoring tool.
US09898872B2	Mobile tele-immersive gameplay Techniques for displaying an augmented reality environment. Embodiments capture a visual scene for display. An embedded symbol associated with a garment worn by the first user within the visual scene is identified. Embodiments generate a virtual augmentation corresponding to the first user that is animated based on the captured visual scene. The virtual augmentation alters an appearance of the first user, such that the first user is depicted as wearing a virtual costume, the virtual costume determined to have a predefined relationship with the identified embedded symbol. A sequence of frames is rendered that depicts the first user augmented with the virtual augmentation in the augmented reality environment and depict at least a portion of the first user as wearing the virtual costume.
US09898870B2	Techniques to present location information for social networks using augmented reality Techniques to present location information using augmented reality are described. An apparatus may comprise an augmentation system operative to augment an image with information for an individual, the image having a virtual object representing a real object. The augmentation system may comprise a location component operative to determine location information for the real object, a virtual information component operative to retrieve location information for an individual, and a proximity component operative to determine whether location information for the real object substantially matches location information for the individual. The augmentation system may further comprise an augmentation component operative to augment the virtual object with information for the individual to form an augmented object when the location information for the real object substantially matches the location information for the individual. Other embodiments are described and claimed.
US09898869B2	Tactile interaction in virtual environments Tactile virtual reality (VR) and/or mixed reality (MR) experiences are described. Techniques described herein include receiving data from a sensor and accessing a position and an orientation of a real object that is physically present in a real scene. Furthermore, techniques described herein include identifying the real object based at least in part on the position and the orientation of the real object and causing a graphical element corresponding to the real object to be rendered on a display of a VR and/or MR display device. The graphical element can be determined based at least in part on a VR and/or MR application. The techniques described herein include determining an interaction with the real object and causing a functionality associated with the graphical element to be performed in the VR or MR environment rendered via the VR and/or MR display device, respectively.
US09898868B2	Display device, method of controlling the same, and program A head mounted display device includes an image display portion that transmits external scenery and displays an image so as to be capable of being visually recognized together with the external scenery. In addition, the head mounted display device includes a control unit that acquires an external scenery image including the external scenery which is visually recognized through the image display portion, recognizes an object which is visually recognized through the image display portion on the basis of the acquired external scenery image, and displays information regarding the object on the image display portion.
US09898864B2	Shared tactile interaction and user safety in shared space multi-person immersive virtual reality A “Shared Tactile Immersive Virtual Environment Generator” (STIVE Generator) constructs fully immersive shared virtual reality (VR) environments wherein multiple users share tactile interactions via virtual elements that are mapped and rendered to real objects that can be touched and manipulated by multiple users. Generation of real-time environmental models of shared real-world spaces enables mapping of virtual interactive elements to real objects combined with multi-viewpoint presentation of the immersive VR environment to multiple users. Real-time environmental models classify geometry, positions, and motions of real-world surfaces and objects. Further, a unified real-time tracking model comprising position, orientation, skeleton models and hand models is generated for each user. The STIVE Generator then renders frames of the shared immersive virtual reality corresponding to a real-time field of view of each particular user. Each of these frames is jointly constrained by both the real-time environmental model and the unified real-time tracking model.
US09898863B2	Information processing device, information processing method, and program Provided is an information processing apparatus including a sound output control unit configured to generate localization information of a sound marker based on a virtual position, and a sound output unit configured to output a sound associated with the sound marker, based on the localization information, wherein the virtual position is determined based on a position of a real object present in a space.
US09898859B2	Apparatus and method for managing structure data A storage unit stores structure data that includes coordinates of vertices of a plurality of polygons representing a three-dimensional structure. A computation unit calculates coordinates of a certain point with reference to the structure data. This point is used, together with the vertices of the polygons, to produce a graph from the structure data according to spatial arrangement of the polygons and further to calculate characteristic quantities based on the produced graph. The computation unit stores the calculated coordinates of the point in a memory device, as a piece of information relating to the structure data.
US09898857B2	Blending between street view and earth view In one aspect, computing device(s) may determine a plurality of fragments for a three-dimensional (3D) model of a geographical location. Each fragment of the plurality of fragments may correspond to a pixel of a blended image and each fragment has a fragment color from the 3D model. The one or more computing devices may determine geospatial location data for each fragment based at least in part on latitude information, longitude information, and altitude information associated with the 3D model. For each fragment of the plurality of fragments, the one or more computing devices may identify a pixel color and an image based at least in part on the geospatial location data, determine a blending ratio based on at least one of a position and an orientation of a virtual camera, and generate the blended image based on at least the blending ratio, the pixel color, and the fragment color.
US09898856B2	Systems and methods for depth-assisted perspective distortion correction Systems and methods for automatically correcting apparent distortions in close range photographs that are captured using an imaging system capable of capturing images and depth maps are disclosed. In many embodiments, faces are automatically detected and segmented from images using a depth-assisted alpha matting. The detected faces can then be re-rendered from a more distant viewpoint and composited with the background to create a new image in which apparent perspective distortion is reduced.
US09898855B2	Method and system for rule based display of sets of images The invention provides, in some aspects, a system for implementing a rule derived basis to display image sets. In various embodiments of the invention, the selection of the images to be displayed, the layout of the images, as well as the rendering parameters and styles can be determined using a rule derived basis. In an embodiment of the present invention, the user is presented with images displayed based on their preferences without having to first manually adjust parameters.
US09898853B2	Rendering apparatus and method A rendering method includes receiving resolution information including an optimal resolution for rendering images constituting a frame, a number of multi-samples, and resolution factors of the respective images, rendering the images at the optimal resolution, and adjusting a resolution of each of the rendered images based on the resolution factors and the number of multi-samples.
US09898852B2	Providing a real-time shared viewing experience in a three-dimensional modeling environment When multiple users simultaneously view and/or collaboratively develop a three-dimensional (3D) model using respective independent computing devices, one of the participating users may locally modify a viewpoint of the 3D model, and the viewpoint changes are automatically propagated in real-time to the other users. A viewpoint may correspond to a positioning, an orientation, a zoom degree, an angle, etc. of the 3D model as would be provided by a virtual camera trained on the 3D model. The multiple users may share a common viewpoint of the 3D model in real-time in addition to viewing and/or participating in the generation and modification of the 3D model in real-time. In an embodiment, only one user at a time may be allowed to control the viewpoint modification of the 3D model.
US09898849B2	Facial expression based avatar rendering in video animation and method Apparatuses, methods and storage medium associated with creating an avatar video are disclosed herein. In embodiments, the apparatus may one or more facial expression engines, an animation-rendering engine, and a video generator. The one or more facial expression engines may be configured to receive video, voice and/or text inputs, and, in response, generate a plurality of animation messages having facial expression parameters that depict facial expressions for a plurality of avatars based at least in part on the video, voice and/or text inputs received. The animation-rendering engine may be configured to receive the one or more animation messages, and drive a plurality of avatar models, to animate and render the plurality of avatars with the facial expression depicted. The video generator may be configured to capture the animation and rendering of the plurality of avatars, to generate a video. Other embodiments may be described and/or claimed.
US09898848B2	Co-registration—simultaneous alignment and modeling of articulated 3D shapes Present application refers to a method, a model generation unit and a computer program (product) for generating trained models (M) of moving persons, based on physically measured person scan data (S). The approach is based on a common template (T) for the respective person and on the measured person scan data (S) in different shapes and different poses. Scan data are measured with a 3D laser scanner. A generic personal model is used for co-registering a set of person scan data (S) aligning the template (T) to the set of person scans (S) while simultaneously training the generic personal model to become a trained person model (M) by constraining the generic person model to be scan-specific, person-specific and pose-specific and providing the trained model (M), based on the co registering of the measured object scan data (S).
US09898841B2	Synchronizing digital ink stroke rendering A method for operating a computing system is provided. The method includes at a local computing device and while an ink input is occurring, rendering a local uncommitted ink stroke on a local display based on the ink input and sending uncommitted ink data corresponding to the uncommitted ink stroke to a remote computing device, the uncommitted ink data including an uncommitted ink stroke path and a global unique identifier differentiating the uncommitted ink data from other uncommitted ink data corresponding to different computing devices and ink inputs. The method further includes responsive to receiving an ink stroke commitment input, rendering a local committed ink stroke on the local display and sending committed ink data including an ink commitment command and the global unique identifier associated with the uncommitted ink stroke path to the remote computing device.
US09898840B2	Systems and methods for continuous motion breast tomosynthesis A method of continuous motion digital tomosynthesis includes exposing an object to a programed intensity x-ray beam as an x-ray source travels a pre-determined path, accumulating a signal charge from the x-ray beam, recording the accumulated signal charge into a digital frame image representing raw baseline data, acquiring information on the source's and the detector's position when the recording occurs, compressing the raw baseline data into compressed views, where each respective compressed view is formed by combining the raw data readouts of the respective compressed view, and reconstructing a volumetric breast image by processing each respective compressed view with a reconstruction process function that incorporates the acquired position information and a spatial sampling corresponding to the compressed views. A system configured to implement the method and a computer-readable medium are also disclosed.
US09898839B2	Medical image diagnosis apparatus and mammography apparatus A medical image diagnosis apparatus emits radiation to a breast as a subject, detects radiation that has passed through the subject, and generates three-dimensional image data including a plurality of tomographic images of the subject. The medical image diagnosis apparatus includes an image generator, a setting unit, an image detector, and a display controller. The image generator projects the three-dimensional image data in a predetermined direction to generate a two-dimensional image. The setting unit sets a region of interest in the two-dimensional image. Based on the region of interest and a corresponding region that corresponds to the region of interest in each of the tomographic images, the image detector detects a tomographic image including the corresponding region that is similar in pixel value to the region of interest from the three-dimensional image data. The display controller displays the tomographic image detected by the image detector on a display unit.
US09898837B2	Image processing system An image processing device, an image processing system, and an image processing method according to the present invention include a mask determining unit that determines a vertical relation in an overlapping area when a video window and a still image window overlap. As a result of a determination, if it is decided that the still image window overlaps as an upper window, the mask process is performed, and if it is decided that the still image window overlaps as a lower window, the mask process is not performed, thereby allowing an appropriate composite image to be obtained regardless of the vertical relation in the overlapping area of the video window and the still image window.
US09898836B2	Method for automatic video face replacement by using a 2D face image to estimate a 3D vector angle of the face image A method for automatic video face replacement includes steps of capturing a face image, detecting a rotation angle of the face image, defining a region to be replaced in the face image, and pasting a region to be replaced of one of the replaced images having the corresponding rotation angle of the face image into a target replacing region. Therefore, the region to be replaced of a static or dynamic face image can be replaced by a replaced image quickly by a single camera without requiring a manual setting of the feature points of a target image. These methods support face replacement at different angles and compensate the color difference to provide a natural look of the replaced image.
US09898833B1	Apparatus and method for determining the dimensions of a package while in motion An exemplary apparatus determines the dimensions of a package while being moved by a transport through a scanning zone. Sensors with different respective fields of view are disposed about a scanning zone and generate corresponding frames of 3-D images where some of the points represent the transport and package. A computing apparatus translates the points in the images into a transport coordinate system with a common point of origin on the transport so that the package does not appear to be in motion from frame to frame. The computing apparatus merges the translated points in different frames into a combined point cloud image and deletes points representing the transport resulting in a final point cloud image of the package. The computing apparatus determines the dimensions of the package based on the location of points representing the package in the final point cloud image.
US09898832B1	Surface metallographic method for characterizing the degree of sensitization of aluminum-magnesium alloys A non-destructive method for assessing the “degree of sensitization” of ship structures formed from aluminum-magnesium marine service alloys. Features of the method include (1) selective etching of beta phase in a sensitized aluminum-magnesium alloy (2) metallographic recording of the etched surface; (3) image enhancement to produce high-contrast binary images of etched and unetched areas; (4) image analysis of the enhanced images using line segments along grain boundaries to provide statistical information about the grain boundary beta phase percentage and (5) calibration, whereby the grain boundary beta phase percentage is converted to an expression of the degree of sensitization in the sample.
US09898830B2	Oil leakage detector and oil leakage detection method An oil leakage detector of the present invention includes an image processing unit wherein the image processing unit calculates the values of saturation and intensity of each pixel in the color image of the object after an ultra-violet light is irradiated thereon, draws an intensity-saturation characteristic line of the saturation expressed in an X-axis and the intensity expressed in a Y-axis, sets an upper limit and a lower limit of intensity of each saturation as a threshold value based on an area without oil adhesion on the surface of the object, and determines, in the intensity-saturation characteristic line, an area corresponding to a pixel group where the intensity exceeds the threshold value of the upper limit and a pixel group where the intensity falls below the threshold value of the lower limit, to be an oil leakage adhered area.
US09898825B2	Segmentation of magnetic resonance imaging data There is described herein an image segmentation technique using an iterative process. A contour, which begins with a single point that expands into a hollow shape, is iteratively deformed into a defined structure. As the contour is deformed, various constraints are applied to points along the contour to dictate its rate of change and direction of change are modified dynamically. The constraints may be modified after one or more iterations, at each point along the contour, in accordance with newly measured or determined data.
US09898824B2	Method for volume evaluation of penumbra mismatch in acute ischemic stroke and system therefor A method and a system automatically evaluate the volume of penumbra mismatch during an exam. The method includes performing a magnetic resonance (MR) diffusion-weighted imaging of the brain for acquiring native diffusion images of brain slices. A MR perfusion-weighted imaging of the brain is performed for acquiring native perfusion images of the brain slices. For each brain slice, b0 native diffusion image of the brain slice are segmented to create a contour mask. For each brain slice, a necrosis and cerebrospinal fluid mask (hereafter NC mask) is created from an ADC map of the brain slice. The contour mask and the NC mask of a same slice are fused. For each brain slice, all native perfusion images acquired for the slice are aligned with the NC mask obtained for the slice and the NC mask is fused with each native perfusion image for obtaining a perfusion image.
US09898823B2	Disparity deriving apparatus, movable apparatus, robot, method of deriving disparity, method of producing disparity, and storage medium A disparity deriving apparatus for deriving disparity of an object includes a calculator to calculate costs between a first reference area in a reference image and each one of corresponding areas corresponding to the first reference area in the comparison image, and costs between a second reference area, surrounding the first reference area in the reference image, and each one of corresponding areas corresponding to the second reference area in a comparison image; a synthesizer to synthesize the costs of the first reference area and the second reference area as synthesis costs; a deriving unit to derive a disparity value of the object captured in the first reference area based on the synthesized synthesis costs; and a correction unit to apply a spatial filter to a local region, composed of a plurality of areas, in the first reference image to correct a disparity value of the local region.
US09898821B2	Determination of object data by template-based UAV control A Method for providing information about an object using an unmanned aerial vehicle with a data acquisition unit is disclosed according to some embodiments of the invention. The method may include determining positional data with reference to the object, the positional data being referenced to a measuring coordinate system, providing a digital template regarding the object, the template at least partly representing the object in coarse manner, and referencing the template with the positional data so that the template corresponds as to its spatial parameters to the object in the measuring coordinate system.
US09898820B2	Methods and systems for analyzing biological reaction systems A method for analyzing biological reaction systems is provided. The method includes receiving an image of a substrate including a plurality of reaction sites after a biological reaction has taken place. Next, the method includes removing a noise background from the first image. The method includes determining an initial position of each reaction site based on an intensity threshold to generate a initial position set, then refining the initial position set of each reaction site based on an expected pattern of locations of the plurality of reaction sites to generate a first refined position set. The method further includes determining a presence or absence of a fluorescent emission from each reaction site based on the first refined position set and the first image.
US09898819B2	System and method for detecting region of interest Disclosed is region of interest (ROI) detection apparatus and method. The ROI detection apparatus includes: a selecting criterion acquirer configured to acquire a selecting criterion; an image receiver configured to receive a current image; a suspicious area selector configured to select a part of the current image as a suspicious area according to the selecting criterion; and an ROI detector configured to detect an ROI from the suspicious area.
US09898818B2	Automated measurement of changes in retinal, retinal pigment epithelial, or choroidal disease A method for automatically measuring changes in retinal, retinal pigment epithelial, or choroidal disease includes retrieving a set of images of a fundus and selecting a plurality of images from the set of images. The plurality of images are co-registered and pre-processed such that the quality, contrast, and gain of each of the plurality of images is made similar. Then, a comparison is made between the plurality of images to determine a change in retinal, retinal pigment epithelial, or choroidal disease, wherein the change in retinal, retinal pigment epithelial, or choroidal disease is determined based on various disease metrics. Finally, an indication of the change in retinal, retinal pigment epithelial, or choroidal disease is generated for display to a user on a computing device.
US09898816B2	Diagnosis assisting apparatus and method for assisting diagnosis A diagnosis assisting apparatus includes a display, an imaging unit configured to image a subject, a line of sight detecting unit configured to detect a line of sight direction of the subject from a picked-up image imaged by the imaging unit, a point of view detecting unit configured to detect a point of view of the subject in a display region of the display based on the line of sight direction, and an output controller configured to display a diagnostic image including a natural image and a geometrical image, and the point of view detecting unit detects the point of view of the subject in a case where the diagnostic image is displayed.
US09898812B1	Composite image quality assurance Features are disclosed for processing composite images. Composite images may be received that include a common item such as a t-shirt with different graphics overlaid on the item. Features for determining the quality of composite images based on processing the image data are provided. Detection of a region that the overlaid graphic covers provides a targeted location for analyzing the underlying image. A quality metric may be determined based on whether, which, and how many features of the item shown in the underlying image are obscured or otherwise modified by the overlaid image.
US09898811B2	Method and system for defect classification Defect classification includes acquiring one or more images of a specimen, receiving a manual classification of one or more training defects based on one or more attributes of the one or more training defects, generating an ensemble learning classifier based on the received manual classification and the attributes of the one or more training defects, generating a confidence threshold for each defect type of the one or more training defects based on a received classification purity requirement, acquiring one or more images including one or more test defects, classifying the one or more test defects with the generated ensemble learning classifier, calculating a confidence level for each of the one or more test defects with the generated ensemble learning classifier and reporting one or more test defects having a confidence level below the generated confidence threshold via the user interface device for manual classification.
US09898810B2	Digital media enhancement system, method, and apparatus Aspects are disclosed for enhancing digital media. In an aspect, a target object in a primary image is identified, and reference images that include the target object are located. The target object is then modified within the primary image according to data derived from analyzing the reference image. In another aspect, a primary file is received, and at least one reference file is referenced to generate enhancement data that facilitates enhancing the primary file from an extrapolation of the reference file. In yet another aspect, media files corresponding to a common event are aggregated, and a desired enhancement of a primary file is identified. Here, the desired enhancement corresponds to a modification of an obstruction included in the primary file. A reference file which includes data associated with the desired enhancement is then referenced, and the obstructed data is modified based on replacement data extrapolated from the reference file.
US09898807B2	Image processing device, imaging device, image processing method, and program The image processing device includes a gradation correction unit (gamma correction processing unit 33) which performs gradation correction, a restoration processing unit, a sharpening processing unit, a sharpening and recovery control unit 37 which is able to adjust a restoration rate of restoration processing and a sharpening rate of sharpening processing by controlling the restoration processing unit and the sharpening processing unit, a sharpening and recovery control unit 37 which acquires a total sharpening and restoration rate based on the restoration rate and the sharpening rate and one rate of the restoration rate and the sharpening rate and calculates the other rate of the restoration rate and the sharpening rate based on the total sharpening and restoration rate, and a brightness information acquisition unit. The sharpening and recovery control unit adjusts the restoration rate and the sharpening rate according to acquired brightness information.
US09898806B2	Correction image creation device, radiographic imaging device, imaging device, computer readable medium and correction image creation method A correction image creation device includes: an acquisition unit that acquires at least one original image, which is a basis when creating a correction image used in offset correction with respect to an image that has been obtained by imaging; a determination unit that determines whether or not noise from the exterior is superimposed on the original image; and a cancellation unit that cancels creation of the correction image in a case in which it has been determined by the determination unit that noise from the exterior is superimposed on the original image.
US09898804B2	Display driver apparatus and method of driving display Provided is a method of driving a display. The method includes receiving a plurality of pieces of layer data and classifying the received plurality of pieces of layer data into at least one of two-dimensional (2D) layer data, three-dimensional (3D) layer data, and direct mixed layer data, processing the 2D layer data, mixing the 3D layer data, and mixing the direct mixed layer data, the processed 2D layer data, the processed 3D layer data to generate a display interface.
US09898800B2	Image processing apparatus and image processing method An image processing apparatus that morphs at least part of an input image has an image acquiring unit that acquires an input image, an object specifying unit that specifies an object that is included in the input image and is to be morphed, a map storage unit in which a shift amount map, which is a map in which shift amounts of pixels in a two-dimensional plane are defined, is stored, a map morphing unit that morphs the shift amount map according to a shape of the object to be morphed, and an image morphing unit that morphs the image by determining a shift amount of a pixel that corresponds to the object based on the morphed shift amount map and shifting the pixel.
US09898799B2	Method for image processing and electronic device supporting thereof An image processing method and an electronic device supporting the method are provided. The electronic device includes a processor having an image processing module processing an input image, and a memory, wherein the processor obtains image data that is processed for the input image, wherein the memory stores volatile information which is temporarily obtained from the image during an image processing process of the image processing module.
US09898798B2	Electronic apparatus, external apparatus and method of controlling the same An electronic apparatus includes a locking unit to selectively lock a physical connection with an external apparatus and a control unit to control an operation mode of the electronic apparatus, according to a connection state with the external apparatus, in which the control unit controls the locking unit to lock the connection with the external apparatus, when the electronic apparatus is in an operation mode of using a graphic processing unit of the external apparatus.
US09898797B2	Thermal management for smooth variation in display frame rate Techniques pertaining to thermal management for smooth variation in display frame rate are described. A method may involve performing either or both of: (1) determining whether a temperature of at least one portion of an electronic apparatus exceeds a temperature threshold; and (2) determining whether a variation in a frame rate of images displayed on a display device associated with the electronic apparatus exceeds a variation threshold. The method may also involve controlling the frame rate in response to either or both of a first determination that the monitored temperature exceeds the temperature threshold and a second determination that the variation in the frame rate exceeds the variation threshold.
US09898794B2	Host-based GPU resource scheduling Examples allocate and schedule use of graphics processing unit (GPU) resources among a plurality of users executing virtual machines (VMs) or processes. During initialization, shares representing proportional access to the GPU resources are assigned and then adjusted based on graphics command characteristics. Quantum is allocated among the VMs based on the shares. At runtime, graphics commands from the VMs are queued and iteratively sent to the GPU based on a comparison between allocated quantum and a threshold quantum. In this manner, the GPU resources are fairly shared among the VMs.
US09898792B2	Hierarchical watermark detector The present invention relates generally to digital watermarking. One aspect of the disclosure includes a method comprising: obtaining data representing imagery; using one or more configured processors, analyzing a plurality of portions of the data to detect a watermark orientation component, said analyzing employing a match filter, in which the match filter yields a correlation value for each of the plurality of portions; determining a first portion from the plurality of portions that comprises a correlation value meeting a predetermined value; and directing a watermark decoder at the first portion to decode a plural-bit watermark payload, in which the watermark decoder produces a watermark signature for the first portion, and in which the watermark decoder searches a plurality of areas at or around the first portion to decode the plural-bit watermark payload. Of course, many other aspects and disclosure are provided in this patent document.
US09898791B1	Network system to filter requests by destination and deadline A method and system for filtering service requests by destination and deadline are described. A network computer system receives provider data corresponding to a specified destination and a deadline from a service provider. The network computer system tracks a current location of the service provider through a device equipped with one or more location-based resources and receives request data corresponding to requests for service from users. The network computer system analyzes the request data for each of the requests for service to identify a subset of the requests that are assignable to the service provider based on whether the service provider is able to fulfill the request and travel to the desired destination before the deadline. The network computer system transmits a message to the service provider's device requesting that the service provider fulfill one of the requests for service from the identified subset.
US09898790B2	System and method of identity verification A system and method of verifying the identity of a user or registrant. The user or registrant provides identification information and registration information. The identification information may be a visual representation of an identifying item associated with location information. In some embodiments, the identification information may be a visual representation of a government issued identity. An identification module verifies the identification information and compares the verified identification information to the registration information.
US09898787B2	Allocation of energy production changes to meet demand changes A computer implemented method optimizes a utility plant having multiple devices to convert input energy into output energy for a building. The method includes dividing a utility plant scheduling interval into several control intervals and for each control interval, obtaining a difference between a desired and a measured in-building condition controlled by output power from the utility plant, obtaining current values of multiple factors that influence operation of the utility plant, determining a new power demand of the building expected to decrease the difference, and finding set points for the multiple devices that satisfy the new power demand, take into account response times of the devices and their capacities, and optimize utility plant operation costs.
US09898786B2	Semi-tractor trailer for distribution of natural gas and system and method for use of same A semi-tractor trailer for distribution of natural gas and a system and method for use of the same are disclosed. In one embodiment, a semi-tractor trailer supported fuel receptacle has a plurality of metered fuel dispensers along the sides thereof to permit customers to park along side the semi-tractor trailer and fuel their vehicles with clean natural gas, which may be compressed natural gas or liquid natural gas, for example. The semi-tractor trailer is filled at a central filling location and transported by a tractor to a convenient retail location. A volume monitor monitors the volume of clean natural gas in the semi-tractor trailer and transmits this information to the central filling location, which may dispense a replacement semi-tractor trailer upon the volume of clean natural gas reaching a pre-determined threshold and retrieve the spent semi-tractor trailer in one trip.
US09898784B1	Method and system for categorizing vehicle treatment facilities into treatment complexity levels To generate a repair code when repairing a damaged vehicle, impact characteristics are received for the damaged vehicle and damaged vehicle parts are identified based on the impact characteristics. An extent of the damage is identified for each vehicle part and a repair code is assigned to the vehicle part based on the type of vehicle part, the type of vehicle, the extent of the damage to the vehicle part, etc. The repair code may be from a set of repair codes, where each repair code is generated for a particular type of vehicle part, type of vehicle, extent of damage to the vehicle part, etc., and each repair code corresponds to a cost estimate for repairing or replacing the damaged vehicle part. Each of the repair codes assigned to the damaged vehicle parts are provided to a treatment facility for treating the damaged vehicle.
US09898783B2	Directed order A directed order process and related market center are disclosed, wherein a market center grants permission to order sending firms to send directed order flow to participating designated market makers. Such designated market makers create a virtual guarantee order book for each permissioned order sending firm. If an order sending firm sends a directed order to the market center that is marketable against a virtual guarantee order, then the market center automatically pairs the orders in a two-sided directed cross order instruction, which executes against any superior trading interest in the marketplace first before crossing.
US09898778B1	Systems and methods for obtaining an image of a check to be deposited An image of a check may be presented for payment in a banking system in place of the physical paper check. The check to be deposited can be collected from a depositor using a scanner. A web site, accessed through a depositor's web browser, can be used to drive the process of collecting the check, but in some contexts (e.g., in less popular computing environments, such as those that do not run the most popular operating systems), it is economically infeasible to obtain the certificates that would be used to allow a program executing in the web browser to control the scanner. Thus, a depositor can be instructed to capture and upload images of the check in the form of files, where the image files are then presented for payment through a banking system.
US09898776B2	Providing services related to item delivery via 3D manufacturing on demand Methods and systems can be provided for providing items manufactured on demand to users. A user request for an item can be received. The item can have 3D manufacturing instructions associated therewith. A delivery method for the item can be determined. A manufacturing apparatus can be selected to manufacture the item based on the 3D manufacturing instructions. Instructions can be sent to the manufacturing apparatus to manufacture the item based on the 3D manufacturing instructions. Delivery instructions can be provided for delivering the item according to the delivery method.
US09898775B2	Method and system for providing information by using store terminal Provided are a method and system for providing information by using a store terminal. A method performed by a mobile terminal to receive information about goods, the method may include storing a first list of goods from a store; receiving, from the store terminal, a second list of goods confirmed by a store terminal; and displaying goods included in the stored first list and goods included in the second list. The goods listed on the second list may be confirmed by the store terminal to be contained in a shopping cart of a user.
US09898772B1	Item recommendation Techniques for providing a recommendation for an item may be provided. In particular, a system can provide a recommendation for one or more items based at least in part on how easily a system can fulfill the recommended item. The ease of fulfillment may be affected by one or more items selected or selected by the user, so that when two potential items can be recommended for the user, the item that is easier to provide to the user with the selected item can receive a better recommendation by the system (e.g., through a ranked or scored recommendation list, by limiting the recommended items provided to a user).
US09898771B2	System and method for facilitating the purchase of products determined to be useful in the performance of a task A retailer computer system facilitates the purchase of products that are determined to be useful in the performance of a task by presenting to a consumer a first user interface by which the consumer may select a task from a repository of tasks, each task stored in the repository of tasks having documented instructions, such as a recipe, for performing the task, by presenting in a web page the documented instructions of the selected task, by using one or more keywords within the documented instructions of the selected task to select at least one product from an electronic product catalog, the selected at least one product being one or more of a part, such as a recipe ingredient, and a tool, such as an appliance, usable in performing the task, and by presenting to the consumer a second user interface for allowing the consumer to purchase via use of an online retail channel the selected at least one product.
US09898770B2	Method and apparatus to visualize locations of radio frequency identification (RFID) tagged items Methods and apparatus to visualize locations of radio frequency identification (RFID) tagged items are described. One example method includes receiving a request from a portable electronic device to access product information associated with an individual radio frequency identification (RFID) tagged item, determining a location of the product information in a database, transmitting the located product information to the portable electronic device for display thereon, receiving modified product information associated with the individual RFID tagged item from the portable electronic device, and storing the modified product information to the location of the product information in the database.
US09898765B1	Pricing usage of software products Functionality is disclosed herein for charging for the use of software products based upon billable units defined by a software provider. The software product identifies the occurrences of the billable units as the software product is executing. The software product also sends billing data to a billing service identifying an occurrence of a billable unit, or billable units, such that an invoice may be created that charges for use of the software product based, at least in part, on the occurrence of the billable units.
US09898763B1	Delivering personalized content based on geolocation information in a social graph with sharing activity of users of the open web A system receives geographic information from devices to determine and deliver relevant advertisements or personalized content for consumers. This ties a user's real-world location, with virtual leads (e.g., advertisements). The system uses geographical information gathered by mobile devices and saves the geographical information to consumer profiles. For example, the system can use different wireless radios present on mobile devices to gather different types of geographical information. Some radios include cellular, Bluetooth, global positioning system (or GPS), Wi-Fi, near field communications (or NFC), and other radios.
US09898758B2	Providing a modified content item to a user Methods and systems for generating a content item associated with search results and, based on a subsequent return to the search results, providing the content item in a modified manner.
US09898757B2	Purchase support server, purchase support method, purchase support program, and computer-readable recording medium for recording said program A mediation server (30) includes a second request receiving unit (35) that receives first store information for identifying a store visited by a user as a visited store and second store information for identifying a designated store designated as a place to purchase an item recognized by the user at the visited store from a mobile terminal (10) of the user, a response information generating unit (36) that compares the first and second store information and determines whether the visited store and the designated store match, and generates bargaining information indicating a specified service offered for the item by the visited store when the two stores do not match, and a response information transmission unit (37) that transmits the generated bargaining information to the mobile terminal (10).
US09898754B2	Measuring display effectiveness with interactive asynchronous applications A system to measure effectiveness of displayed content includes a video processing service configured to receive and process a stream of video images captured by one or more video cameras, a display application service configured to produce display content to be displayed on one or more display monitors and to capture user interactions with the displayed content, and a display effectiveness service configured to correlate data received from the video processing service and the display application service and generate a display effectiveness measurement that is a measure of an effectiveness of the displayed content for specific periods of time.
US09898753B2	Methods for cross-market brand advertising, content metric analysis, and placement recommendations In another embodiment, a computer-implemented method for processing and optimizing selection of placement, of advertising content related to a brand, in websites of a network is provided. The computer-implemented method is processed by a server in response to communication from a user that is connected to the server over the Internet. The method includes receiving from the user, attributes of an advertisement to be placed on a brand-centric website that relates to the brand, and also receiving selections for types of websites to place the advertisement. The types of websites do not have to be brand-centric websites, but should include content related to the brand. Then, the method includes obtaining metrics from selected websites and historical performance for similar advertisements when placed on the selected websites. The method includes processing the obtained metrics and historical performance to preliminarily define an advertising model. The advertising model defines a score correlated to effectiveness of the advertisement. Optimizing the advertising model is then performed to define a recommended advertising model, where the recommended advertising model defines optimal selections of websites for placement of the advertisement. The optimizing uses multivariable optimization to correlate the obtained metrics to a desired optimization criteria.
US09898752B2	Point system, method for controlling point system, point management device, program, and information storage medium A point storage unit stores points, which are imparted to the user in an electronic commerce, in association with user identification information. A link request receiving unit receives a link request for linking user identification information and membership card identification information for identifying a membership card for receiving points imparted at an actual shop. In a case where the link request is received, a link information storage unit stores link information indicating a link between the user identification information and the membership card identification information. In a case where a point use request with a designation of the membership card identification information is received, a use permission unit permits use of the points stored in association with the user identification information linked to the membership card identification information.
US09898749B2	Method and system for determining consumer positions in retailers using location markers A computer-implemented method is disclosed herein. The method includes the step of positioning at least one location marker at a position in a retail store. The method also includes the step of receiving, with a processing device of a position detection server, a video signal from an electronic device possessed by a consumer as the consumer shops in the retail store. At least one image frame of the video signal contains the at least one location marker. The method also includes the step of determining, with the processing device, a location of the consumer within the retail store in response to the receiving step.
US09898745B2	Methods and systems for conducting research on an airplane This invention relates to methods and systems for conducting market research, product research, or advertising research. More particularly, travelers are presented with a product and asked to provide feedback regarding the product by completing a survey. Answers to the survey are entered via an input device. Survey answer data is stored in a storage device along with demographic information relating to the traveler and the data is stored. In exchange for completing product research travelers may receive carrier specific rewards or a discount on the cost of travel. Data collected from travelers is collected and sold to corporate sponsors.
US09898743B2	Systems and methods for automatic generation of a relationship management system A method and apparatus for the automatic creation of a relationship management system is described. The method may include receiving a request from a user to create a relationship management system, and receiving specification of one or more electronic communication systems and user access credentials that provide access to each of the corresponding accounts. Furthermore, the method may include obtaining past electronic communications using the received user access credentials and analyzing the past electronic communications to extract contact data. The method may also include creating the relationship management system for the user and adding the contact data as contacts associated with the user in the created relationship management system.
US09898741B2	Real time analytics system Improved real-time analytics systems are provided. An analytics system may be used to generate transaction scores for transactions. A method may comprise receiving a scoring request associated with a transaction, sending the scoring request to a plurality of scoring models including a production model, wherein each scoring model is operable to generate a transaction score in response to the scoring request, and wherein each scoring model may be implemented using a virtual machine, receiving a transaction score generated by the production model, and sending the transaction score to a server for approval or denial the transaction.
US09898740B2	Online challenge-response Embodiments of the invention enable cardholders conducting an online transaction to be authenticated in real-time using a challenge-response application. The challenge-response application can be administered by an issuer or by a third party on-behalf-of an issuer. A challenge question can be presented to the cardholder, and the cardholder's response can be verified. The challenge question presented can be selected based on an analysis of the risk of the transaction and potentially other factors. A variety of dynamic challenge questions can be used without the need for the cardholder to enroll into the program. Additionally, there are many flexible implementation options of the challenge-response application that can be adjusted based on factors such as the location of the merchant or the location of the consumer.
US09898731B2	Donation device and method An electronic, hand-held, and portable donation device and method are disclosed for collecting financial donations. The donation device may include a plurality of electronic payment processors, each payment processor corresponding to a different monetary amount.
US09898729B2	Mutual mobile authentication using a key management center A system, method, and server computer configured to authenticate a consumer device. The consumer device is authenticated via a mobile gateway using challenge-response authentication. If the consumer device is successfully authenticated, a secure channel is established between the consumer device and a first entity. The secure channel allows for secure communication between the consumer device and the first entity.
US09898722B2	System and method for interacting with a self-service terminal Systems and methods for processing custom structured tags at a self-service terminal are disclosed. Custom structured tags received by a self-service terminal can include information to identify one or more devices attached to the terminal and identify one or more types of data to be obtained from a user by use of the attached devices. In some embodiments, a browser can natively interpret the custom structured tags. The self-service terminal can also be configured to receive and decode structured tags identifying or more actions to be performed by the device, such as printing a transaction record or dispensing currency.
US09898720B2	Credit instrument and system providing multiple services including access to credit services and access to a service provider club An apparatus and methods for a card that allows a cardholder to set up auto-charge payment of dues and fees to a series of clubs, merchants or service providers. The card also may be used for other transactions that accept credit cards. The apparatus includes a database containing information of the associated clubs, merchants and service providers, so that applicants and cardholders can easily configure auto-charging for multiple business concerns in one sitting. The apparatus may process auto-charge transactions in an automated fashion without requiring a cardholder to submit payment authorization or the business concern to submit a charge for each payment. Inconvenience and administrative costs to the cardholder and the business concern are reduced. The system and method provide a competitive advantage to the associated business concerns to secure the initial account and then to maintain it. The system and method encourages card loyalty of both the card members and the business concerns to the card provider.
US09898719B2	Systems, methods, and computer program products providing push payments In electronic financial transactions a receiver, or targeted recipient of funds, provides account information to a transmitter, or sender of funds. The transmitter initiates a push of funds from a transmitter funding source to the receiver's funding source processor. In some embodiments the receiver provides a payment card, similar to a credit card, which is read by an electronic device of the transmitter, such as a smart phone. In some embodiments, the receiver provides the account information by way of a bar code, such as a QR code, which is scanned and read by the transmitter's electronic device.
US09898716B2	Social network construction Technologies are generally described for constructing an ad-hoc social network. In some examples, a method performed under control of an end device may include calculating a social relevance on a social graph between the end device and another end device, based on a social graph bit array of the end device and a social graph bit array of the other end device; determining that the calculated social relevance is greater than a predetermined threshold value; and constructing an ad-hoc social network that connects the end device with the other end device.
US09898715B2	Systems and methods for creating, manipulating and processing rights and contract expressions using tokenized templates System and methods for manipulating rights expressions for use in connection with a rights management system include one or more tokenized templates. Each tokenized template includes one or more rights expression language statements and one or more tokens associated with at least one of the rights expression language statements. Further, the tokens can be place holders for data items or rights expression elements. The system further includes a license template module that creates the tokenized templates, and a license instance creation module that replaces at least one of the tokens in one or more selected license templates with one or more of the data items or rights expression elements to generate a license instance. Additionally, the system includes a license instance analysis module having sub-modules for validating and interpreting license instances, and a data parsing module for extracting data from created license instances.
US09898714B2	System and method for a direct social network A system for a direct social network comprises a first device and a second device. The first device of the social network includes a first contact list. The first contact list includes a first plurality of users. The second device of the social network includes a second contact list. The second list includes a second plurality of users. The first device directly requests data from the second device when a user of the second device is one of the first plurality of users. The second device transmits the requested data when the user of the first device is one of the second plurality of users.
US09898712B2	Continuous display shelf edge label device A method and apparatus for providing information along a shelf edge of a retailer is described. On a display configured to be oriented along an edge of a shelf of a retailer, a first user interface including first information about a first product on the shelf is provided. At least one second user interface including at least one second information about at least one second product on the shelf is provided on the display. An individual is permitted to edit a parameter of the first user interface and/or the at least one second user interface. The parameter may include at least one of: a size of the user interface on the display, a shape of the user interface on the display, and a location of the user interface on the display. The first information and the at least one second information may be outputted concurrently to the display.
US09898708B2	Uplifting of computer resources The present disclosure improves upon existing systems and methods by providing a tool for managing processing resources. For instance, the presently described tool may be used to time replacement, plan for uplifts, budget for uplifts/decommissioning of hardware, and/or maintain a plurality of servers. This tool may lead to increased satisfaction, uptime, and a reduction of unexpected costs. The system may include initiating collection of variables to compile a prioritized list of servers, executing, a calculation application for determining a prioritized list of servers' end of life targets based on both technical and business parameters based on the entered variables, and prioritizing uplifts of the servers based on the technical and the business parameters.
US09898706B1	Autonomic discrete business activity management method An autonomic method of applying stochastic modeling techniques within a group of commercially interrelated businesses to utilize a universal business activity mosaic to derive an entity's near or real time asset conversion risk profile from the interpretation of concatenated entity asset conversions and other specified risk determinants within time indexed asset mosaics for the purpose of deriving and providing of risk management services.
US09898705B2	Automated handtool task verification A method of automated handheld tool task verification is disclosed. In one embodiment, at least one operating parameter for performing a task is received at a handheld tool. It is then verified at the handheld tool that it is configured with the at least one operating parameter. The handheld tool then generates data verifying that the task was performed in accordance with the at least one operating parameter.
US09898702B2	Method, computer program product, and apparatus for managing decision support related event information An apparatus for managing decision support related events and solutions includes a plurality of case management elements. Each of the case management elements is in communication with at least an associated one of a corresponding plurality of portal access controllers associated with a corresponding unit within an organization. Each of the case management elements includes at least a corresponding one of a plurality of solution elements. Each of the solution elements is configured to receive solution information from the at least one corresponding portal access controller and to communicate the solution information only with each other one of the solution elements. The solution information comprises data regarding a decision support related event associated with a case associated with the corresponding unit.
US09898699B2	Smart metal card with radio frequency (RF) transmission capability Ferrite material utilized in a smart metal card as a shield between a metal layer and an antenna does not occupy a complete layer. Instead, only sufficient ferrite material is utilized to track and conform to the antenna.
US09898698B2	Production tool having RFID device mounted within a dielectric inclusion A production tool has a dielectric inclusion, and an RFID device mounted within the dielectric inclusion.
US09898696B2	IC card issuance apparatus, IC card issuance system and IC card issuance method An IC card issuance apparatus includes an issuance processing unit and a data supply unit. The issuance processing unit performs processing for issuing an IC card based on issuance data. The data supply unit monitors whether or not an issuance data file containing the issuance data is stored in a storage apparatus designated in advance, and supplies the issuance data contained in the issuance data file stored in the storage apparatus to the issuance processing unit such that the issuance processing unit executes issuance of the IC card based on the issuance data if the issuance data file is stored in the storage apparatus.
US09898692B2	Printing apparatus, printing control apparatus, printing system, control method of printing apparatus, and storage medium A printing apparatus includes a first receiving unit, an obtaining unit, a sending unit, a second receiving unit, and a setting unit. The first receiving unit receives, from a printing control apparatus, an instruction to obtain first attribute information of a sheet held in a sheet holding unit. The obtaining unit obtains the first attribute information in accordance with the instruction received by the first receiving unit. The sending unit sends the first attribute information obtained by the obtaining unit to the printing control apparatus. The second receiving unit receives, from the printing control apparatus, second attribute information based on the first attribute information sent from the sending unit. The setting unit sets the second attribute information, received by the second receiving unit, as attribute information of a sheet held in the sheet holding unit.
US09898691B2	Control device, control system, and control method of a control device Concentrating the processing load on a specific device can be suppressed when producing coupons by effectively using information printed on a receipt. A host computer 12 has a print control unit 20a that generates and outputs a control command to produce a receipt to a receipt printer 10; and a command interpreting unit 20b that interprets a receipt control command generated by the print control unit 20a, extracts specific information contained in the control command for each server, generates transmission data for each server based on the extracted information, and sends the transmission data to the respective servers.
US09898686B2	Object re-identification using self-dissimilarity A method of identifying an object in an image is disclosed. At least one feature map for each of a plurality of cells in the image is determined. A self-dissimilarity between a first feature map associated with a first one of said cells and a second feature map associated with a second cell, is determined. The self-dissimilarity is determined by determining a sum over thresholds of a difference in area between the first feature map and the second feature map. An appearance signature for the object is formed based on the determined self-dissimilarity. A distance between the appearance signature of the object in the image and appearance signatures of each of a plurality of further objects is determined. The object in the image is identified based on the determined distances.
US09898683B2	Robust method for tracing lines of table A method for image processing includes obtaining a mask of a stroke from an image and identifying a plurality of cross edges for the stroke based on the mask and a reference line. The plurality of cross edges includes a group of adjacent cross edges that intersect the reference line. The method further includes (a) calculating a first vector based on positions of at least two of the cross edges in the group, (b) expanding the group, based on the first vector, to include cross edges adjacent to the group that do not intersect the reference line, (c) calculating a second vector based on positions of at least two of the cross edges in the expanded group, and (d) expanding the expanded group, based on the second vector, to include a second group of adjacent cross edges nearby the expanded group that do not intersect the reference line.
US09898682B1	System and method for tracking coherently structured feature dynamically defined within migratory medium A system and method are provided for discriminating and tracking a coherently structured feature dynamically defined in evolving manner within a migratory medium. A data set is captured for a plurality of physical points defined within a multi-dimensional physical space, in terms of a plurality of scalar parameter values. At least one pre-selected target feature type is established, as is a scalar field predefined by at least one of the scalar parameters. A sparse set of key points is selectively generated a within the scalar field. Each key point is associated with one of the physical points and descriptive information adaptively determined therefor from the data content within a neighborhood of the physical point coinciding therewith. At least one predetermined feature-based operation is executed responsive to the descriptive information of the key points as a surrogate for execution generally on the data set.
US09898680B2	Feature image generation apparatus, classification apparatus and non-transitory computer-readable memory, and feature image generation method and classification method A feature image generation apparatus includes circuitry. The circuitry generates, on the basis of a processing target image in which an object appears, a first image showing the object, and generates, as a feature image showing a feature of the object, at least a part of a rotational composite image obtained by composition of a plurality of rotated images obtained by rotating the first image.
US09898677B1	Object-level grouping and identification for tracking objects in a video In one embodiment, a method of determine and track moving objects in a video, including detecting and extracting regions from accepted frames of a video, matching parts including using the extracted parts of a current frame and matching each part from a previous frame to a region in the current frame, tracking the matched parts to form part tracks, and determining a set of path features for each tracked part path. The determined path features are used to classify each path as that of mover or a static. The method includes clustering the paths of movers, including grouping parts of movers that likely belong to a single object, in order to generate one or more single moving objects and track moving objects. Also a system to carry out the method and a non-transitory computer-readable medium that when executed in a processing system causes carrying out the method.
US09898674B2	Spoof detection for facial recognition An embodiment of the invention provides a method of analyzing an image of a user to determine whether the image is authentic, where a first image of a user's face is received with a camera. Four or more two-dimensional feature points can be located that do not lie on the same two-dimensional plane. Additional images of the user's face can be received; and, the at least four two-dimensional feature points can be located on each additional image with the image processor. The image processor can identify displacements between the two-dimensional feature points on the additional image and the two-dimensional feature points on the first image for each additional image. A processor can determine whether the displacements conform to a three-dimensional surface model. The processor can determine whether to authenticate the user based on the determination of whether the displacements conform to the three-dimensional surface model.
US09898671B2	Vehicle vision system with structure and motion estimation A vision system of a vehicle includes a camera disposed at the vehicle and having a field of view exterior of the vehicle. A control has an image processor that is operable, via image processing of frames of image data captured by the camera, to detect an object present in the field of view of the camera. When the vehicle is moving, the control, responsive at least in part to vehicle motion information and image processing of frames of captured image data, determines motion of the detected object relative to the moving vehicle. The control determines the relative motion of the detected object by (i) determining corresponding object points in at least two frames of captured image data, (ii) estimating object motion trajectory of the detected object responsive to the determination of corresponding object points and (iii) determining the structure of the detected object along the estimated object motion trajectory.
US09898666B2	Apparatus and method for providing primitive visual knowledge An apparatus and method for providing primitive visual knowledge are disclosed. The method of providing primitive visual knowledge includes receiving an image in a form of a digital image sequence, dividing the received image into scenes, extracting a representative shot from each of the scenes, extracting objects from frames which compose the representative shot, extracting action verbs based on a mutual relationship between the extracted objects, selecting a frame best expressing the mutual relationship with the objects, which are the basis for the extracting of the action verbs, as a key frame, generating the primitive visual knowledge based on the selected key frame, storing the generated primitive visual knowledge in a database, and visualizing the primitive visual knowledge stored in the database to provide the primitive visual knowledge to a manager.
US09898658B2	Pupil detection light source device, pupil detection device and pupil detection method A pupil detection light source device includes an aperture disposed to face a subject to allow light from a pupil of the subject to pass therethrough, an illumination light for obtaining a light pupil image toward the subject from the inside or the vicinity of the aperture when seen from the subject, and an illumination light for forming a reflection image with glasses obtained by canceling a reflection image with glasses of the light pupil image using an image difference toward the subject from the inside or the vicinity of the aperture when seen from the subject.
US09898657B2	Four-dimensional code, image identification system and image identification method based on the four-dimensional code, and retrieval system and retrieval method The invention discloses a four-dimensional code, an image identification system and an image identification method based on the four-dimensional code, a retrieval system and a retrieval method. All the conceives of the invention are mainly based on the four-dimensional code which includes an identification image and a group of recognition data corresponding to the identification image, wherein the identification image includes a true color image, a two-dimensional code, a color overlaid on the two-dimensional code, and an ID No., and the true color image, the two-dimensional code, the color overlaid on the two-dimensional code and the ID No. have same or corresponding indexes. Data corresponding to the four-dimensional code is stored through a server, and the four-dimensional code or the identification image is scanned during identification or retrieval, so that corresponding data can be retrieved through image identification processing, and returned to a mobile terminal. The invention has high identification precision and broad application range, and can be applied to various commercial purposes.
US09898655B2	System and method for identification and extraction of data A system and method of for describing target data as a sequence of pattern elements and pattern element groups that comprise an overall target pattern is described. Pattern elements may utilize regular expression syntax along with other metadata that describe the behavior of the element. A pattern element group may be a collection of fully defined pattern elements where at least one pattern element from the group must have a match for the overall pattern to match. Patterns contain both pattern elements and pattern element groups. The general process involves first performing optical character recognition (OCR) on the document, which in turn produces a sequence of text tokens representing the lines of text on each page of the document. The search algorithm may then apply each defined pattern to the entire document capturing and/or extracting data that match each pattern's required elements and element groups.
US09898654B2	Translating procedural documentation into contextual visual and auditory guidance A method and system are provided for assisting a user performing a procedure. The method includes capturing, by a camera, images of user activity while the user is performing the procedure. The method further includes converting, by computer processing system, the images of user activity into a text representation of user activity. The method also includes comparing, by the computer processing system, the textual representation of user activity to procedure documentation. The method additionally includes at least one of visually and audibly indicating, by a display and a speaker, a corrective action to the user responsive to a mismatch result from said comparing step.
US09898653B2	Method for determining width of lines in hand drawn table A method for image processing includes obtaining a mask of a stroke from an image; determining a plurality of cross edges for the stroke based on the mask; generating a histogram comprising a plurality of widths of the cross edges and a plurality of frequencies of the plurality of widths from the cross edges; estimating a lower bound of a width range for the stroke based on a mode width of the plurality of widths, a first subset of the plurality of widths below the mode width, and a first plurality of weights assigned to the first subset of the plurality of widths; and estimating an upper bound of the width range for the stroke based on the mode width, a second subset of the plurality of widths above the mode width, and a second plurality of weights assigned to the second subset of the widths.
US09898651B2	Upper-body skeleton extraction from depth maps A method for processing data includes receiving a depth map of a scene containing at least an upper body of a humanoid form. The depth map is processed so as to identify a head and at least one arm of the humanoid form in the depth map. Based on the identified head and at least one arm, and without reference to a lower body of the humanoid form, an upper-body pose, including at least three-dimensional (3D) coordinates of shoulder joints of the humanoid form, is extracted from the depth map.
US09898646B2	Method of validation intended to validate that an element is covered by a true skin Disclosed is a method intended to validate that an element is covered with a true skin and implemented by a validation device including a light source at at least one wavelength, a sensor, an analysis module and a decision-taking module. The method may include: placing a surface of the element in front of the light source and the sensor; illuminating, by the light source, the surface of the element; capturing, by the sensor, for each wavelength, an image of the positioned element that encompasses an illuminated zone of the element directly illuminated by the light beam and a peripheral zone (“the diffusion zone of the element,” which is peripheral to the illuminated zone); analyzing the illuminated zone and the diffusion zone of the captured image; and deciding, by the decision-taking module, whether the element is covered with a true skin according to the results of the analysis.
US09898642B2	Device, method, and graphical user interface for manipulating user interfaces based on fingerprint sensor inputs An electronic device with a display and a fingerprint sensor displays a fingerprint enrollment interface and detects, on the fingerprint sensor, a plurality of finger gestures performed with a finger. The device collects fingerprint information from the plurality of finger gestures performed with the finger. After collecting the fingerprint information, the device determines whether the collected fingerprint information is sufficient to enroll a fingerprint of the finger. When the collected fingerprint information for the finger is sufficient to enroll the fingerprint of the finger, the device enrolls the fingerprint of the finger with the device. When the collected fingerprint information for the finger is not sufficient to enroll the fingerprint of the finger, the device displays a message in the fingerprint enrollment interface prompting a user to perform one or more additional finger gestures on the fingerprint sensor with the finger.
US09898640B2	Capacitive fingerprint sensing device and method for capturing a fingerprint using the sensing device There is provided a capacitive fingerprint sensing device for sensing a fingerprint pattern of a finger, the capacitive fingerprint sensing device comprising: a protective dielectric top layer having an outer surface forming a sensing surface to be touched by the finger; at least one electrically conductive sensing structure arranged underneath the top layer; readout circuitry coupled to the at least one electrically conductive sensing structure to receive a sensing signal indicative of a distance between the finger and the sensing structure; and a plurality of individually controllable electroacoustic transducers arranged underneath the top layer and configured to generate a focused ultrasonic beam, and to transmit the ultrasonic beam through the protective dielectric top layer towards the sensing surface to induce an ultrasonic vibration potential in a ridge of finger placed in contact with the sensing surface at the location of the ultrasonic beam.
US09898638B2	Optical marker for delivery drone cargo delivery At least one image captured by an image capture device of a delivery drone can be processed to identify at least one optical marker contained in the image. The optical marker can display at least one machine readable optical label, or alphanumeric characters, indicating a cargo recipient. Responsive to identifying the optical marker, image processing on the image can be performed to generate data corresponding to the machine readable optical label or alphanumeric characters. Whether the data corresponds to an intended cargo recipient of a cargo being carried by the delivery drone can be determined. Responsive to determining that the data corresponding to the machine readable optical label or alphanumeric characters corresponds to the intended cargo recipient of the cargo being carried by the delivery drone, the delivery drone can be initiated to deliver the cargo at a specific location indicated by the optical marker.
US09898637B2	Two-dimensional code Disclosed is a two-dimensional code which is not likely to be affected by contamination or out-of-focus photographing thereof and can thus be accurately recognized even when it is photographed under various photographing conditions. The disclosed two-dimensional code comprises: cells representing binary-coded data that are arranged as a pattern in the form of a two-dimensional matrix, the two-dimensional code comprising: a position detection pattern; plural data blocks created by dividing a region of the two-dimensional matrix that excludes the part of the position detection pattern; and a separation space arranged between the plural data blocks that are adjacent.
US09898636B2	Wrapper for terahertz, detection sensor, detection apparatus using terahertz wave, optical identification device for terahertz, apparatus for recognizing optical identification device for terahertz wave, and writing apparatus for identification unit A wrapper for a terahertz wave according to an embodiment of the present invention includes: a terahertz wave transmission layer that is made of a material that transmits a terahertz wave; and an electric field enhancement structure that enhances an electric field by reacting with a predetermined frequency band of terahertz waves passing through the terahertz wave transmission layer. An optical identification device for a terahertz wave according to an embodiment of the present invention includes m identification units composed of: a terahertz wave transmission layer that is made of a material that transmits a terahertz wave; and a waveguide grating that resonates at a natural resonant frequency when receiving the transmitted terahertz wave, in which the natural resonant frequency is any one of a first natural resonant frequency to an n-th natural resonant frequency.
US09898634B2	Auto-diagnostic NFC reader A self-diagnosing validation device includes an NFC reader having an RF signal range, an active diagnostic chip positioned within the RF signal range of the NFC reader, a memory, and a processing unit. The active diagnostic chip is configured to be selectively powered during a diagnostic procedure. The processing unit is configured to determine that the diagnostic procedure needs to be performed on the NFC reader and perform the diagnostic procedure. The diagnostic procedure includes activating the active diagnostic chip by supplying power to the active diagnostic chip, reading, using the NFC reader, any data being transmitted by the active diagnostic chip, determining whether any data was read by the NFC reader, and determining whether the NFC reader is functioning properly based at least in part of the determination whether any data was read by the NFC reader.
US09898632B2	Article management system, article management method, and non-transitory computer readable medium storing article management program An article management system includes RFID tags (102) fixed above a reader waveguide (101), a tag position table storage unit (106) that stores tag information and fixed positions of the RFID tags (102) in association with each other, an article position table storage unit (105) that stores identification information and an assigned position of an article (108) in association with each other, an article management table storage unit (107) that stores the identification information of the article (108) and the tag information of the RFID tags (102) in association with each other, a tag reading unit (103) that reads the RFID tags (102) by electromagnetic coupling through the reader waveguide (101), and an article presence/absence determination unit that determines presence or absence of placement of the article (108) corresponding to the RFID tags (102) based on results of reading the RFID tags (102).
US09898631B2	Intelligent energy management system and energy management method for passive radio frequency tag The present invention relates to an intelligent energy management system and an energy management method for a passive radio frequency tag. Digital conversion is performed on the amplitude of a DC signal absorbed and rectified by an inductance coil antenna of the tag, by providing an intelligent energy management module. The input terminal of the intelligent energy management module is respectively connected to a power supply voltage detection and judgment circuit and a demodulator circuit, and configured to judge the level of charge and enabling state of the tag; and the output terminal thereof is respectively connected to a discharge path, a bias current source and an analog circuit module, and configured to bring the analog circuit module into the optimal operating state according to the enabling state of the tag, or to turn-off/get dormant each analog circuit module thus to reduce power consumption of the tag and improve the sensitivity of the tag. Meanwhile, the intelligent energy management module may further control the discharge path to conduct control on discharge of charge at both ends of the antennas, so that the voltage withstanding performance of devices connected to an inductance coil antenna is reliably ensured.
US09898628B1	Dynamic quick response code branding In an approach to managing a quick response code branding device and management of a quick response code branding device, one or more computer processors receive one or more quick response code configuration parameters. The one or more computer processors determine one or more program instructions corresponding to the one or more quick response code configuration parameters based on one or more task-specific factors. The one or more computer processors send the one or more program instructions to a quick response code branding device. The one or more computer processors receive quick response code branding device status data. The one or more computer processors determine whether the quick response code branding device status data meets the one or more quick response code configuration parameters.
US09898625B2	Method and apparatus for limiting access to an integrated circuit (IC) A method and apparatus for limiting access to an integrated circuit (IC) upon detection of abnormal conditions is provided. At least one of abnormal voltage detection, abnormal temperature detection, and abnormal clock detection are provided with low power consumption. Both abnormally low and abnormally high parameter values (e.g. abnormally low or high voltage, temperature, or clock frequency) may be detected. Abnormal clock detection may also detect a stopped clock signal, including a clock signal stopped at a low logic level or at a high logic level. Furthermore, abnormal clock detection may detect an abnormal duty cycle of a clock signal. A sampled bandgap reference may be used to provide accurate voltage and current references while consuming a minimal amount of power. Upon detection of an abnormal parameter value, one or more tamper indications may be provided to initiate tampering countermeasures, such as limiting access to the IC.
US09898623B2	Method for performing an encryption with look-up tables, and corresponding encryption apparatus and computer program product An encryption method includes accessing a look-up table (LUT) to implement countermeasures against side-channel attacks, such as embedding masks. The LUT is initialized by writing initialization values in the LUT by applying an address-mask to input data that identify a location of said LUT and a data-mask to data to be stored at a location of the LUT. The method includes carrying out an initialization of the LUT that includes providing at least one second address-mask and one second data-mask; and computing corresponding initialization values as a function of a logic combination of the aforesaid first address-mask and second address-mask and of a logic combination of the aforesaid first data-mask and second data-mask. In the resulting table the address data are masked only by the second address-mask and the data are masked only by the second data-mask. The structure of the LUT may allow convenient implementation by initializing all the values of the LUT in parallel in one cycle.
US09898616B2	Providing logical partitions with hardware-thread specific information reflective of exclusive use of a processor core Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
US09898611B2	Method and apparatus for scrambling a high speed data transmission A method of transmitting high speed serial data with reduced levels of radiated emissions is disclosed. A transmitting device scrambles data utilizing a pseudo-random number sequence generator. Scrambling the data eliminates transmission of repeated data sequences. The transmitting device similarly scrambles idle pairs of data between data transmissions to eliminate an additional source of repeated data sequences. The scrambled and encoded data is transmitted to a receiving device. The receiving device also includes a pseudo-random number sequence generator. Synchronization of the two pseudo-random number sequence generators occurs by utilizing control characters of the data frame being transmitted. Each of the pseudo-random number sequence generators is configured to generate the same sequence of numbers and is initialized to start with a first number in the sequence of numbers corresponding to the first byte of data being transmitted or received.
US09898605B2	Monitoring executed script for zero-day attack of malware Embodiments are directed to hooking a call for a malware monitoring logic into a JavaScript API engine interpreter. Upon JavaScript being placed into heap memory, the malware monitoring logic can initiate an evaluation or analysis of the heap spray to determine whether the JavaScript includes malware or other malicious agents prior to execution of the JavaScript shell code. Upon execution of the JavaScript within the sandbox, the malware monitoring logic can initiate monitoring of the JavaScript using malware analysis and/or execution profiling techniques. Inferences can be made of the presence of malware based on a start and end time of the JavaScript execution.
US09898598B2	Authentication system having a non-volatile memory including memory cells in initial or variable states and a host computer for performing authentication therebetween An authentication system comprises a host computer; and a non-volatile memory that includes a memory cell array including a plurality of memory cells are arranged in array, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied; and a memory cell in an initial state which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including first authentication data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state, wherein at least one of the host computer and the non-volatile memory stores second authentication data, and wherein at least one of the host computer and the non-volatile memory is operative to perform authentication on the basis of the first authentication data and the second authentication data.
US09898596B2	System and method for eye tracking during authentication A system, apparatus, method, and machine readable medium are described for performing eye tracking during authentication. For example, one embodiment of a method comprises: receiving a request to authenticate a user; presenting one or more screen layouts to the user; capturing a sequence of images which include the user's eyes as the one or more screen layouts are displayed; and (a) performing eye movement detection across the sequence of images to identify a correlation between motion of the user's eyes as the one or more screen layouts are presented and an expected motion of the user's eyes as the one or more screen layouts are presented and/or (b) measuring the eye's pupil size to identify a correlation between the effective light intensity of the screen and its effect on the user's eye pupil size.
US09898588B2	Method and apparatus for providing cloud-based digital rights management service and system thereof A method for providing a Digital Rights Management (DRM) service in a network is provided. The method includes receiving a request message for device registration, which includes DRM-related identification information, from a user device; and registering registration information of the user device, which is distinguished according to a corresponding user account and according to a corresponding DRM solution, based on the DRM-related identification information.
US09898580B2	Methods and apparatus for analyzing specificity in clinical documentation A set of one or more clinical facts may be collected from a clinician's encounter with a patient. From the set of facts, it may be determined that an additional fact that provides additional specificity to the set of facts may possibly be ascertained from the patient encounter. A user may be alerted that the additional fact may possibly be ascertained from the patient encounter.
US09898579B2	Relational DNA operations A database implemented by storing information encoded in DNA molecules provides high information density but the information is more difficult to access than in conventional electronic storage media. A relational database is a way of organizing information by using multiple related tables. Relational algebra operations are performed on relational databases to locate and manipulate information. This disclosure provides techniques for implementing relational algebra operations on a relational database that uses DNA molecules to store information. The techniques of this disclosure relate to the structure of DNA molecules used to store the information and to correlations between relational algebra operations and manipulations of DNA molecules.
US09898574B2	Method for determining the presence of disease The invention provides a method for determining presence of a disease, comprising steps of; measuring the levels of expression of transcription products of genes in a biological sample obtained from a subject suspected of having a target disease, wherein the genes comprise at least one gene belonging to each of at least two disease-determining gene families related to the target disease; obtaining values representing deviations by standardizing the levels of the expression based on the levels of expression of transcription products of the corresponding genes in a plurality of healthy subjects; obtaining the average of values representing deviations with respect to the gene belonging to each of the disease-determining gene families; and determining whether or not the subject has the target disease by using the average; as well as a computer program product for determining presence of a disease.
US09898573B2	Rule and process assumption co-optimization using feature-specific layout-based statistical analyses Disclosed are methods, systems and computer program products that, during new technology node development, perform design rule and process assumption co-optimization using feature-specific layout-based statistical analyses. Specifically, the layout of a given feature can be analyzed to determine whether it complies with all of the currently established design rules in the new technology node. When the layout fails to comply with a current design rule, statistical analyses (e.g., Monte-Carlo simulations) of images, which are generated based on the layout and which illustrate different tolerances for and between the various shapes in the layout given current process assumption(s), can be performed. Based on the results of the analyses, the current process assumption(s) and/or the design rule itself can be adjusted using a co-optimization process in order to ensure the manufacturability of the feature within the technology.
US09898570B2	Transparent editing of physical data in hierarchical integrated circuit design Systems and techniques are described for transparently editing physical data in hierarchical IC designs. Some embodiments allow a user to access objects at any level of the physical hierarchy and to specify a particular editing operation (move, rotate, delete, cut, split, etc.) relative to the top-level block. The embodiments can automatically transform and apply the editing operations in the context of the block where the edited object resides. Systems and techniques for automatic context selection, logical connection analysis, cross hierarchical routing, transparent hierarchical routing, and maintaining physical connectivity across hierarchy boundaries are also described.
US09898569B2	Semiconductor layout structure and designing method thereof A method for designing a semiconductor layout structure includes following steps. A first active feature group including at least a first active feature is received, and the first active feature includes a first channel length. A pair of first dummy features is introduced to form a first cell pattern. The first dummy features include a first dummy width. A first spacing width is defined between the first active feature group and one of the first dummy features and a third spacing width is defined between the first active feature group and the other first dummy feature. The first cell pattern includes a first cell width and a first poly pitch, and the first cell width is a multiple of the first pitch. The receiving of the first active feature group and the introducing of the first dummy features are performed in by at least a computer-aided design tool.
US09898568B2	Reducing the load on the bitlines of a ROM bitcell array Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.
US09898567B2	Automatic layout modification tool with non-uniform grids A method (and system) of automatically legalizing a circuit layout with layout objects in a presence of a plurality of non-uniform grids is disclosed. The method comprises generating a set of layout constraints comprising design rule constraints and gridding requirements based on the plurality of non-uniform grids. In addition, the method comprises processing the set of layout constraints to a feasible form using Boolean variables by determining infeasibility of the set of layout constraints, identifying infeasible layout constraints from the set of layout constraints, and resolving the infeasibility by a constraint relaxation process. Additionally, the method comprises generating an output circuit layout, for display to a user, by solving the set of layout constraints in the feasible form with standard linear program solvers.
US09898562B2	Distributed state and data functional coverage This application discloses a computing system to implement a design verification tool and simulate a circuit design with a test bench. The computing system can identify multiple components in the circuit design to combine for distributed state coverage analysis based, at least in part, on data transactions generated during the simulation of the circuit design. The computing system can correlate information captured during simulation that corresponds to the identified components. The correlated information can identify at least one distributed state coverage event for the test bench. The computing system can generate a distributed state coverage metric based on the correlated information corresponding to the identified components. The computing system can prompt presentation of the correlated information a display window, which can graphically show how a test bench exercised the identified components during simulation.
US09898561B2	Behavioral simulation model for clock-data recovery phase-locked loop Method and non-transitory computer-readable medium storing instructions for simulating a phase-locked loop measures a first phase of a data signal and a second phase of a reference clock signal in a phase-locked loop to be simulated, filters the first phase of the data signal by a threshold function of a lock detection module of the phase-locked loop to be simulated, and adjusts the second phase of the reference clock signal to align with the filtered first phase of the data signal.
US09898559B2	Method for predicting changes in properties of a formation in a near-wellbore area exposed to a drilling mud In order to predict properties of a formation in a near-wellbore area exposed to a drilling mud rheological properties of the drilling mud, of a filtrate of the drilling mud and of a reservoir fluid are determined. Properties of an external mudcake, porosity and permeability of the core sample are determined. A mathematical model of the external mudcake is created. The drilling mud is injected through a core sample and dynamics of pressure drop across the sample and dynamics of a flow rate of a liquid leaving the sample are determined. Using an X-ray micro Computed Tomography a profile of concentration of particles of the drilling mud penetrated into the sample is determined. A mathematical model is developed for the internal mudcake to describe dynamics of changes in concentration of the particles of the drilling mud in a pore space of the core sample. A coupled mathematical model of the internal and the external mudcakes is created and parameters of the mathematical model of the internal mudcake are determined providing matching of simulation results to the experimental data on injection the drilling mud through the core sample and to the concentration profile of the particles of the drilling mud.
US09898557B2	Method and system for generating building plans using slices A non-transitory computer-readable storage medium is disclosed. In an embodiment, the non-transitory computer-readable storage medium includes instructions that, when executed by a computer, cause the computer to perform steps involving receiving parameters, selecting pre-configured slices from a library of slices that satisfy the parameters, and placing the selected slices to generate a configuration variant in accordance with slice placement logic.
US09898556B2	Immersive dimensional variation A computing device is used for creating a dimensional model of at least a portion of a product, the dimensional model including a range of possible conditions with respect to at least one component in the product. The dimensional model is used to create a set of geometries for the product, a geometry being a representation of at least a portion of the product, wherein each of the geometries corresponds to one or more of the conditions. A display is provided of a first one of the geometries, and then, upon receiving an input requesting a second one of the geometries, a display is provided of the requested second one of the geometries.
US09898553B2	Capturing run-time metadata A processor captures, during the run-time of a first event, run-time metadata associated with the first event, the run-time metadata comprising a data lineage and a data provenance. The data lineage identifies input data existing before the first event and resulting data of the first event. The data provenance identifies an agent executing the first event. The processor then generates a property graph with the property graph comprising a plurality of nodes. The plurality of nodes comprises a first node, a second node, and a third node. The first node comprises an identification of the input data existing before the first event. The second node comprises an identification of the agent executing the first event, and the second node is coupled to the first node. The third node comprises an identification of the resulting data of the first event, and the third node is coupled to the second node.
US09898543B2	Browser interaction for lazy loading operations A system and method for enhancing a lazy loading operation is disclosed. The system and method, in general, retrieves a plurality of subsets of a dataset via the lazy loading operation and increments a counter for each of the plurality of subsets retrieved by the processor. Then, the system and method detects a first event that navigates away from the retrieving of the plurality of subsets and also detects a second event that navigates back to the retrieving of the plurality of subsets. Next, the system and method returns to the retrieving of the plurality of subsets in accordance with the counter in response to the detecting of the second event.
US09898540B1	Method for automated categorization of keyword data A method for categorizing text strings assigns text strings to topical categories. A search engines retrieves and ranks a list of Uniform Resource Locators (URLs) for each test string. The most highly-ranked URLs for a set of text strings form a whitelist of pre-approved text strings that are assumed to correlate closely with category meaning. Incorrectly categorized text strings are identified by scoring a list of URLs retrieved by a search engine for each text string, comparing each score to the whitelist position of the text string, flagging text strings with scores that deviate from whitelist position by at least a threshold amount, and reassigning flagged text strings to categories with the most similar sets of retrieved URLs.
US09898538B2	Role-relative social networking A role-based social network follow request that identifies a specified user role to follow within a social network is received from a social network user. A social network role-based query, derived from the specified user role identified within the role-based social network follow request, is executed. In response to executing the social network role-based query, role-based information of social network users within the social network is retrieved. Another social network user that matches the specified user role is identified based upon the retrieved role-based information of the social network users. Role-based social network following of the matching other social network user is configured for the requesting social network user.
US09898535B2	Avatar-based search tool A method of performing a digital search, wherein the result set returned is additionally narrowed via a virtual personality, represented by an animated avatar selected by the user prior to enacting the search. The avatar consists of a virtual identity, which, when reduced to keyword characteristics and then applied to a search algorithm, enables the filtering of result sets according to the inferred desires of the hypothetical individual instantiated by the virtual identity itself, expressed as an avatar.
US09898532B2	Resolving inconsistent queues Embodiments described herein may involve inconsistent queues. An example implementation may involve a computing device receiving a message indicating a playback queue corresponding to a playback zone of a media playback system. The playback queue may include first media items queued in a first order for playback by the playback zone. The computing device determines that a playlist at the computing device is to be queued for playback in the playback queue corresponding to the playback zone, the playlist including second media items in a second order. The computing device determines that the first media items in the first order is different from the second media items in the second order, and based on the determination, causes the first media items in the playback queue to be replaced with the second media items in the playlist.
US09898531B2	System and method for mathematics ontology extraction and research An extensive computer based online math research system (the “Research System”) having as its foundation an Ontology of mathematics, and utilizing unique and intensive computer support, coordination, data structuring, data storage, computer processing, retrieval capabilities, and data-mining capabilities, and an Ontology editing system that runs on computer software with computer processors and data storage capabilities (the “Ontology Editor System”). The Research System also includes a methodology to enable online reference and data manipulation of the Ontology, and an Internet based search of the concepts of mathematics and applications of mathematics to the sciences on the basis of the Ontology.
US09898528B2	Concept indexing among database of documents using machine learning techniques Systems and techniques for indexing and/or querying a database are described herein. Discrete sections and/or segments from documents may be determined by a concept indexing system. The segments may be indexed by concept and/or higher-level category of interest to a user. A user may query the segments by one or more concepts. The segments may be analyzed to rank the segments by statistical accuracy and/or relatedness to one or more particular concepts. The rankings may be used for presentation of search results in a user interface. Furthermore, segments and/or documents may be ranked based on recency decay functions that distinguish between segments that maintain their relevance over time in contrast with temporal segments whose relevance decays quicker over time, for example.
US09898524B2	Managing a classification system and associated selection mechanism Generating a wizard includes receiving a scheme as an input source to form a received scheme, wherein the received scheme is a taxonomy, receiving a defined set of content files to form received content files, and loading the received content files and the received scheme. The received content files can be tagged using the received scheme. A wizard can be generated using the received scheme. The generated wizard is capable of use with an application utilizing the scheme, wherein a change in the received scheme is directly represented in the generated wizard.
US09898520B2	Systems and methods for seamless access to remotely managed documents using synchronization of locally stored documents A system and method for seamless access to remotely manage documents using synchronization of locally stored documents is provided. In some embodiments, a content management server stores documents in a cache on the user's computer. Documents can thus be accessed and edited using the document in the local file system of the user and synchronized with the content management server asynchronously to access the documents on the local files system. Advantageously, the teachings of embodiments as described can be used in conjunction with content management systems for providing faster access to documents in conjunction with editing and for enabling offline work on such documents.
US09898515B1	Data extraction and transformation method and system A system and method for processing raw transaction records received from multiple data sources. The system and method receive multiple raw transaction records from multiple data sources. Transaction pair records are generated from the raw transaction records. Location and entity fields including raw information are identified from the transaction pair records. The raw location and entity information is resolved to generate resolved location and entity information capable of aggregation and further processing, such as the deriving of analytics.
US09898513B2	System, method and computer program for multi-dimensional temporal and relative data mining framework, analysis and sub-grouping The present invention relates to a system, method and computer program product that is a multi-dimensional data mining environment and that operable to apply a series of temporal and relative rules (i.e., STDMn0) and is further operable in at least one of the following ways: to incorporate a framework to support temporal abstractions and relative alignments to data (i.e., STDMn0); and to derive characteristics within the data (STDMn0). The present invention may incorporate data from multiple sources, and potentially multiple centers. The analysis and alignment of the data may involve both temporal dimensions and other dimensions (or relative aspects) of the data. The present invention may further be a data mining environment that is flexible enough to permit relatively open ended queries thereby enabling, for example, the detection of trends, including trends with new dimensions, or trends based on relatively small data sets.
US09898511B2	Method of manipulating vocabulary depending on the audience A system for recommending content based on the audience, implemented by a computing processor, detects content that is to be transmitted to an audience. The system receives a user profile associated with the audience, and scores the content against the user profile to produce a rating. The content is weighted based on at least one attribute associated with the user profile. The system invokes an action in response to the rating.
US09898508B2	Method and device for processing information The embodiments of the present invention provide a method for processing information, comprising: obtaining attribute information about a target field; obtaining, according to the attribute information about the target field, attribute information about the target field described in a first language; and sending the attribute information about the target field described in the first language to a query engine using the first language, so that the query engine obtains, according to the attribute information about the target field described in the first language, data corresponding to the target field; and the embodiments of the present invention also provide an apparatus for processing information. According to the technical solutions provided in the embodiments of the present invention, attribute information about a target field being automatically described in a language can be realized, so as to improve the query efficiency of data.
US09898506B2	Runtime optimization for multi-index access Optimization of a multi-index database access at runtime. A processor receives a query. A processor determines a plan and a record identifier (RID) results threshold for the plan, wherein the plan includes an access to the index. A processor determines a static risk threshold, a static risk for the access, and whether the static risk exceeds the static risk threshold. Responsive to the static risk exceeding the static risk threshold, a processor determines a risk bound for the access, and links the access to the risk bound. A processor accesses the index with the key. Responsive to the access being linked to a risk bound, a processor determines a dynamic risk for the access. A processor receives one or more RID results during the execution of the plan. A processor aborts the execution of the plan if a quantity of the RID results is less than the RID results threshold.
US09898503B2	Finding services in a service registry system of a service-oriented architecture Searching a service registry system including a plurality of services identified by respective service names, wherein at least some of said service names being associated with a set of client identifiers, includes receiving a search request, said request including a service name and a further set of client identifiers, searching, using a processor, the service registry system for a match between the requested service name and a service name of one of said services in the service registry system, and, in the absence of such a match, searching, using the processor, the service registry system for services that have an association with at least some of the client identifiers in said further set. A search result can be returned.
US09898499B2	Multimedia scheduling for airplay with alternate category support A device and method for resolving a conflict in a chronological scheduling order for airplay while with constant order of the multimedia. A scheduling order can be designated for the delivery and playback of multimedia content (e.g., music, news, other audio, advertising, etc) with respect to particular slots within the scheduling order. Conflict resolution between multimedia content is based upon exchanging a slot position of either of one of a first set and one of a second set of a category of multimedia content identifiers with another corresponding one of either of the first set and the second set of the multimedia content identifiers based upon a predetermined number of slot value to resolve the conflict and to modify at least the portion of the chronological scheduling order while adhering to constant order for the multimedia content. Modified portions of the chronological scheduling order are produced for eventual airplay of multimedia content corresponding to the multimedia content identifiers.
US09898494B2	Zero downtime upgrade for database applications using tables with sequences An upgrade of a first version of a database application to a second version of a database application that both have a same data schema is initiated. The first database application has a first access schema such that at least one table in the data schema is linked to the first access schema. The second version of the database application has a second access schema such that at least one database table in the data schema is linked to the second access schema. The first access schema differs from the second access schema. Concurrent access is provided for each access schema to at least one sequence in the data schema to both the first version of the database application and the second version of the database application. Related apparatus, systems, techniques and articles are also described.
US09898489B2	Preserving high value entries in an event log A first entry is received at an event log interface. The event log interface is configured to store received entries in an event log. It is determined that there is not enough storage space to store the first entry in the event log. A second entry is identified. The second entry is the oldest entry in the event log based on when the second entry was written to the event log. It is determined that the second entry contains an indicator to preserve. A copy of the second entry is sent to the event log interface to be written to the event log. One or more entries are deleted from the event log. The one or more entries includes the second entry. The first entry is written to the event log. The copy of the second entry is written to the event log.
US09898485B2	Dynamic context-based data protection and distribution Systems and methods for storing data in a data storage system that allows dynamic context-based data protection and distribution are disclosed. The method includes receiving a storage request and evaluating whether a storage policy is specified in the storage request. When the storage request specifies a storage policy, the data is stored according to the specified policy. When the storage request does not specify a storage policy, meta data and/or the data item itself may be evaluated to identify a storage policy. When a storage policy has been identified, store the data is stored according to the identified policy. When a storage policy has not been specified and cannot be identified, an error is returned.
US09898478B2	Distributed deduplicated storage system A distributed, deduplicated storage system according to certain embodiments is arranged in a parallel configuration including multiple deduplication nodes. Deduplicated data is distributed across the deduplication nodes. The deduplication nodes can be networked together and communicate with one another according using a light-weight, customized communication scheme (e.g., a scheme based on FTP or HTTP). In some cases, deduplication management information including deduplication signatures and/or other metadata is stored separately from the deduplicated data in deduplication management nodes, improving performance and scalability.
US09898473B2	Security via data concealment Methods, apparatuses, and embodiments related to improving security of data that is stored at a data store distributed over a computer network. In an example, source data to be protected is partitioned into multiple files, and each file is obfuscated, such as by being encrypted, to created multiple obfuscated data files. Information as to how each obfuscated data file was obfuscated is stored in an associated trace file. The multiple obfuscated data files are moved around a computer network via a data movement process that includes sending each of the multiple obfuscated data files to a different randomly selected computer, where the computer further obfuscates the obfuscated data the trace file, and sends the further obfuscated data and trace file to a next randomly selected computer.
US09898469B1	Parallel streaming of external data Methods, systems, and apparatus, including computer programs encoded on computer storage media, for streaming external data in parallel from a second distributed system to a first distributed system. One of the methods includes receiving a query that requests a join of first rows of a first table in a first distributed system with second rows of an external table, the external table representing data in a second distributed system. Each of the segment nodes communicates with a respective extension service that obtains fragments from one or more data nodes of the second distributed system according to location information for the respective fragments, and provides to the segment node a stream of data corresponding to second rows of the external table. Each of the segment nodes computes joined rows between the first rows of the first table and the stream of data corresponding to second rows of the external table.
US09898468B2	Single pass file system repair with copy on write Example apparatus and methods concern identifying an error in a file system. The error is identified during one or more b-tree traversals through the file system. A fix for the error is produced upon detecting the error. Data or metadata associated with the fix is not initially written to the file system, but instead is stored somewhere other than the file system using a copy on write approach. After the traversals are complete, the file system may be fixed using the data or metadata stored using the copy on write approach.
US09898466B2	Media preference affinity recommendation systems and methods The present systems and methods relate to a concept for providing media recommendations targeted to particular, “subject” user. The present systems and methods involve obtaining historical usage data associated with the subject user; identifying candidate users; calculating media preference overlap scores with respect to the subject user and each candidate user; ranking the candidate user according to their media preference overlap scores, and generating recommendations for the subject user from the historical usage data associated with the candidate users.
US09898456B2	User interface for a handheld device A user interface and method for composing a message to be sent over a wireless network environment using a handheld device is disclosed. According to the method, upon receipt of a user request to compose a message, a screen is displayed with a recipient field for a recipient address, an associated label to indicate that the recipient field is for a recipient address, and a message body field for holding message content. The method further includes, upon each keystroke entry of text to the recipient field, looking up entries from an address book which match the text, and displaying a selection menu representing addresses from at least a portion of the entries as well as cached entries previously looked up from a global address book.
US09898450B2	System and method for repagination of display content A method and system for repaginating content displayed on a display screen of a computing device when upon receiving indication of an object superposed on the content. The content comprises display of one page in a series of digitally constructed pages. The repaginated content is re-flowed or line-wrapped around an identified keep out boundary to counteract any obscuration of displayed content. The repagination forces reconstruction of a next one of the series of pages for display.
US09898449B1	System and method for automatically replacing information in a plurality electronic documents In a method for processing electronic documents, an indication of a plurality of electronic source documents is received with one or more computing devices that each have a processor executing at least a portion of an electronic document processing application and a memory coupled to the processor to store associated data. An indication of an electronic destination location is received. An indication of particular source document content is received. An indication of one or more processing actions to be performed with respect to the particular source document content is received. One or more occurrences of the particular source document content within the plurality of electronic source documents are detected. The one or more processing actions are performed so as to generate the electronic output content, without presenting contents of the plurality of electronic source documents to a user. The electronic output content is written to the electronic destination location.
US09898446B2	Processing a webpage by predicting the usage of document resources Browser systems and methods of loading/rendering a webpage include preprocessing the web document (HTML page) using speculation/prediction techniques to identify the resources that are likely to be required from an incomplete set of information, and requesting/pre-fetching the resources that are determined to have a high probability of being required for proper rending of the web document. The speculation/prediction techniques may include the use of heuristics to improve the efficiency and speed of document loads and network communications.
US09898445B2	Resource prefetching via sandboxed execution The aspects include browser systems and methods of loading/rendering a webpage by preprocessing scripts within the web document (HTML page) in a sandboxed script engine to discover resources not explicitly requested in the web document so such resources can be pre-fetched and downloaded speculatively. The sandboxed execution of scripts and downloading of discovered resources may proceed in parallel with the performance of other browser operations (e.g., HTML parsing) and other resource requests. The sandboxed script engine may be isolated or separated from the other browser components. The sandboxed script engine may operate to speedup the process of identifying resources inconsistent with standard script execution processes.
US09898438B2	Symbol lock method and a memory system using the same A memory system includes a transmitter and a receiver. The transmitter is configured to transmit a data signal corresponding to a first symbol lock pattern and a data burst via an interface. The data burst includes a first data and a subsequent data. The receiver is configured to receive the data signal, to detect the first symbol lock pattern based on the received data signal, and to find the first data of the data burst according to the detected first symbol lock pattern.
US09898435B2	Aggregate baseboard management controller (BMC) controller Apparatuses, methods and storage media associated with the exchange of messages between a hybrid switch and one or more baseboard management controllers (BMCs) are described herein. Specifically, an aggregate BMC controller (ABC) may be communicatively coupled with both the hybrid switch and the BMCs and configured to facilitate the exchange of messages between the hybrid switch and the one or more BMCs. Other embodiments may be described and/or claimed.
US09898434B2	System, process control method and medium A system includes: a first processor; a second processor; and a communication bus configured to couple the first processor and the second processor; wherein the first processor is configured to obtain a bus usage rate by monitoring a delay time period of data transfer in the communication bus, determine whether to offload a processing on received data based on the monitored bus usage rate, and offload the processing to the second processor when the processing is determined to be offloaded.
US09898431B1	Method and apparatus for memory access Aspects of the disclosure provide a circuit that includes a plurality of memory access circuits configured to access a memory to read or write data of a first width. The memory includes a plurality of memory banks that are organized in hierarchy. Further, the circuit includes a plurality of interface circuits respectively associated with the plurality of memory access circuits. Each interface circuit is configured to receive memory access requests to first level memory banks from an associated memory access circuit, segment the memory access requests into sub-requests to corresponding second level memory banks, buffer the sub-requests into buffers associated with the second level memory banks. In addition, the circuit includes arbitration circuitry configured to control multiplexing paths from the buffers to the second level memory banks to enable, in a same memory access clock, memory accesses by the memory access circuits.
US09898427B2	Method and apparatus for accessing multiple storage devices from multiple hosts without use of remote direct memory access (RDMA) A method and apparatus for accessing multiple storage devices from multiple hosts without use of remote direct memory access (RDMA) as disclosed herein include: providing a data store switch fabric enabling data communications between a data storage access system and a plurality of compute nodes, each compute node having integrated compute capabilities, data storage, and a network interface controller (Host NIC); providing a plurality of physical data storage devices; providing a host bus adapter (HBA) in data communication with the plurality of physical data storage devices and the plurality of compute nodes via the data store switch fabric, the HBA including at least one submission queue and a corresponding shadow queue; receiving an input/output (I/O) request from the plurality of compute nodes; including an element of the I/O request to the at least one submission queue; and including additional information related to the element of the at least one submission queue to the corresponding shadow queue.
US09898416B2	Translation entry invalidation in a multithreaded data processing system In a multithreaded data processing system including a plurality of processor cores and a system fabric, translation entries can be invalidated without deadlock. A processing unit forwards translation invalidation request(s) received on the system fabric to a processor core via a non-blocking channel. Each of the translation invalidation requests specifies a respective target address and requests invalidation of any translation entry in the processor core that translates its respective target address. Responsive to a translation snoop machine of the processing unit snooping broadcast of a synchronization request on the system fabric of the data processing system, the translation synchronization request is presented to the processor core, and the translation snoop machine remains in an active state until a signal confirming completion of processing of the one or more translation invalidation requests and the synchronization request at the processor core is received and thereafter returns to an inactive state.
US09898415B2	Slot/sub-slot prefetch architecture for multiple memory requestors A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.
US09898414B2	Memory corruption detection support for distributed shared memory applications Nodes in a distributed node system are configured to support memory corruption detection when memory is shared between the nodes. Nodes in the distributed node system share data in units of memory referred to herein as “shared cache lines.” A node associates a version value with data in a shared cache line. The version value and data may be stored in a shared cache line in the node's main memory. When the node performs a memory operation, it can use the version value to determine whether memory corruption has occurred. For example, a pointer may be associated with a version value. When the pointer is used to access memory, the version value of the pointer may indicate the expected version value at the memory location. If the version values do not match, then memory corruption has occurred.
US09898413B2	Auto-adaptive system to implement partial write buffering for storage systems dynamic caching method and system for data storage system An auto-adaptive system to implement partial write buffering for storage systems comprises: dynamically determining a wiring method for a data queue which needs to be written, and on the basis of a determination result, directly writing to a storage medium data suited to being written directly, and as for data suited for being written after being cached, caching the data by a caching device and then writing the data to the storage medium. A dynamic caching system uses the above method. The method and system significantly reduce the space requirements for caching, enable fault tolerance integration, and improve system performance.
US09898412B2	Methods, systems and apparatus for predicting the way of a set associative cache A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.
US09898409B2	Issue control for multithreaded processing A multithreaded data processing system performs processing using resource circuitry which is a finite resource. A saturation signal is generated to indicate when the resource circuitry is no longer able to perform processing operations issued to it. This saturations signal may be used to select a scheduling algorithm to be used for further scheduling, such as switching to scheduling from a single thread as opposed to round-robin scheduling from all of the threads. Re-execution queue circuitry is used to queue processing operations which have been enabled to be issued so as to permit other processing operations which may not be blocked by the lack of use of circuitry to attempt issue.
US09898406B2	Caching of data in data storage systems by managing the size of read and write cache based on a measurement of cache reliability A disk drive is disclosed that varies its caching policy for caching data in non-volatile solid-state memory as the memory degrades. As the non-volatile memory degrades, the caching policy can be varied such that the non-volatile memory is used more as a read cache and less as a write cache. Performance improvements and slower degradation of the non-volatile memory can thereby be attained.
US09898403B2	Voltage control circuit for providing two voltages generated based on a parameter corresponding to an input signal Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories.
US09898399B2	Memory management apparatus and method A memory management apparatus and method are provided herein. The memory management apparatus includes a memory management list generation unit, a memory allocation unit, and a memory release unit. The memory management list generation unit generates a memory management list adapted to have all memory blocks divided into a plurality of memory blocks and to indicate whether each of the memory blocks has been allocated. The memory allocation unit allocates a memory region that belongs to the memory management list and that corresponds to an amount of memory requested for allocation in response to a memory allocation request. The memory release unit releases a memory region that belongs to the memory management list and that corresponds to a memory region to be released in response to a memory release request.
US09898398B2	Re-use of invalidated data in buffers Reusing data in a memory buffer. A method includes reading data into a first portion of memory of a buffer implemented in the memory. The method further includes invalidating the data and marking the first portion of memory as free such that the first portion of memory is marked as being usable for storing other data, but where the data is not yet overwritten. The method further includes reusing the data in the first portion of memory after the data has been invalidated and the first portion of the memory is marked as free.
US09898395B2	Unit-level formal verification for vehicular software systems According to one exemplary embodiment, a method for preparing a software component for verification is provided. The method may include receiving the software component and a design model. The method may also include generating a wrapper program based on the received software component and the received design model. The method may then include associating the received software component with the generated wrapper program. The method may further include determining a plurality of inputs for the received software component based on the received design model. The method may also include sending the determined plurality of inputs and the received software component with associated wrapper program to a verification tool.
US09898389B2	Debugging a transaction in a replica execution environment A computer-implemented method for debugging a transaction includes receiving a transaction in a transaction management system, where the transaction management system includes one or more message-processing regions (MPRs). A request to debug the transaction is identified. A debug session for the transaction is isolated from the one or more MPRs, by a computer processor, and this isolation is responsive to identifying the request to debug the transaction. Performing the isolation includes identifying a first MPR of the one or more MPRs, and deploying a replica MPR having an execution environment copied from the first MPR. Performing the isolation further includes invoking, inside the replica MPR, a debug-specific application program configured to perform the transaction.
US09898386B2	Detecting byte ordering type errors in software code An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.
US09898385B1	Systems, methods, and devices for vertically integrated instrumentation and trace reconstruction In an embodiment, a system is configured to replay and/or reconstruct execution events and system states in real time or substantially in real time starting from the point when execution of a target program has stopped to the point when the user desires to step through the target program's execution in order to debug the software. In an embodiment, a system is configured to efficiently collect trace data that is sufficient to reconstruct the state of a computer system at any point of time from the start of execution to the time execution was stopped. Efficient and effective debugging of the software can be performed using embodiments of the disclosed methods, systems, and devices.
US09898383B2	Techniques and mechanisms for managing and analyzing database query activities Techniques and mechanisms for analyzing a plurality of database queries within a database environment. A first statistical evaluation of a first query plan is determined for a first database query with at least one computing device within the database environment. A second statistical evaluation for a second query plan is determined for a second database query. The first statistical evaluation and the second statistical evaluation are compared to determine whether the first query plan matches the second query plan with at least one computing device within the database environment. An indication is stored in a repository of the database environment that the first query matches the second query if the first hash value matches the second hash value. A function that provides the first query plan is determined. If the second query plan is provided by the function that provides the first query plan, data objects referenced by the first query plan and the second query plan if the function provides both the first query plan and the second query plan to determine if the first query plan and the second query plan are syntactically different versions of equivalent database queries. Query statistics are stored in the statistical repository if the first query plan and the second query plan are syntactically different versions of equivalent database queries.
US09898382B2	Hyperlink-induced topic search algorithm lock analysis A system is described for identifying key lock contention issues in computing devices. A computing device is executed and lock contention information relating to operations during execution of the computing device is recorded. The data is parsed and analyzed to determine blocking relationships between operations due to lock contention. Algorithms are implemented to analyze dependencies between operations based on the data and to identify key areas of optimization for performance improvement. Algorithms can be based on the Hyperlink-Induced Topic Search algorithm or the PageRank algorithm.
US09898378B2	Smart selection of a storage module to be excluded Provided are a computer program product, computer system, and method for smart selection of a storage module to be excluded when a connection between two storage modules is broken. An indication is received from a first storage module that a connection between the first storage module and a second storage module is broken. In response to determining that the second storage module is accessible, values of exclusion criteria for the first storage module are determined and summed to identify a first exclusion total. Then, values of exclusion criteria for the second storage module are determined and summed to identify a second exclusion total. In response to determining that the first exclusion total exceeds the second exclusion total, the second storage node is excluded from the cluster. In response to determining that the second exclusion total exceeds the first exclusion total, the first storage node is excluded from the cluster.
US09898375B1	Asymmetric memory transceiver A system for transmission of memory entries. The system includes a computing device that includes a memory module, a memory controller interfacing with the memory module via a memory bus, a snooping module interfacing with the memory bus, functionally in parallel to the memory module, and a high-speed interconnect, functionally connecting the snooping module to a receiving device. The memory controller is configured to write a memory entry to the memory module via the memory bus. The snooping module is configured to capture a copy of the memory entry being written to the memory module and to send the copy of the memory entry to the receiving device, via the high-speed interconnect.
US09898370B2	Flash copy for disaster recovery (DR) testing In one embodiment, a system includes a processor and logic configured to create a backup copy of data stored to one or more production clusters and store the backup copy to one or more disaster recovery (DR) clusters. Moreover, the logic is configured to establish a time-zero in the DR family and create a snapshot of each backup copy stored to the one or more DR clusters. Each snapshot represents data stored to the one or more DR clusters at the time-zero, and each snapshot is a point-in-time flash copy of at least a user data portion of all virtual tapes of the one or more DR clusters with the proviso that the snapshot does not include a metadata portion of the virtual tapes. The logic is further configured to share a point-in-time data consistency at the time-zero among all clusters within the DR family.
US09898359B2	Predictive disaster recovery system Environmental data, associated with a first computer, is received. Social media data, associated with the first computer, is also received. A first severity value, based on the environmental data, is determined. A second severity value, based on the social media data, is determined. A first weighted severity score is determined. The first weighted severity score is a combination of the first and second severity values. One or more actions is determined. The determined action is one of a recovery point objective action or a recovery time objective action. Each action has a threshold. Whether the first weighted severity score is equal to or greater than any threshold associated with any action is determined. In response to determining that the first weighted severity score is equal to or greater than one or more thresholds, each action associated with each threshold is implemented.
US09898356B2	Packet processing on a multi-core processor A method for packet processing on a multi-core processor. According to one embodiment of the invention, a first set of one or more processing cores are configured to include the capability to process packets belonging to a first set of one or more packet types, and a second set of one or more processing cores are configured to include the capability to process packets belonging to a second set of one or more packet types, where the second set of packet types is a subset of the first set of packet types. Packets belonging to the first set of packet types are processed at a processing core of either the first or second set of processing cores. Packets belonging to the second set of packet types are processed at a processing core of the first set of processing cores.
US09898353B2	Type agnostic data engine Systems and methods for processing and/or presenting data are disclosed. In an aspect, one method can comprise receiving a request for information and detecting a type of data representing the information requested. The data can be processed via a type-dependent agent and the processed data can be provided via an agnostic data engine.
US09898348B2	Resource mapping in multi-threaded central processor units A processor determines that processing of a thread is suspended due to limited availability of a processing resource. The processor supports execution of the plurality of threads in parallel. The processor obtains a lock on a second processing resource that is substitutable as a resource during processing of the first thread. The second processing resource is included as part of a component that is external to the processor. The component supports a number of threads that is less than the plurality of threads. The processing of the thread is suspended until the lock is available. The processor processes the first thread using the second processing resource. The processor includes a shared register to support mapping a portion of the plurality of threads to the component. The portion of the plurality of threads is equal to, at most, the number of threads supported by component.
US09898346B2	Resource substitution and reallocation in a virtual computing environment A host system reallocates resources in a virtual computing environment by first receiving a request to reallocate a first quantity of a first resource type. Next, potential trade-off groups are evaluated and a trade-off group is selected based on the evaluation. The selected trade-off group includes a set of applications running in the virtual computing environment that can use one or more alternate resource types as a substitute for the first quantity of the first resource type. After the selection, the host system reallocates the first quantity of the first resource type from the trade-off group. This reallocation may be made from the trade-off group to either a first application running in the virtual computing environment or the host system itself. If the reallocation is to the host system, then the total quantity of the first resource type allocated to applications running in the virtual computing environment is thereby reduced.
US09898344B2	System and method for providing configuration modularity in an application server, cloud platform, or other environment In accordance with an embodiment, described herein is a system and method for providing configuration modularity in an application server, cloud platform, or other environment. For example, in a cloud computing environment, application server modules, e.g., WebLogic Server or GlassFish modules, can be embedded within the environment to provide various cloud platform functionalities. In accordance with an embodiment, the system comprises a configuration modularity logic for use in determining, for a particular application or service deployment, a configuration of application, module or service components, including determining if a configuration is provided by a global or domain configuration, determining if annotations are provided by the particular application or service deployment for use in configuring the application, module or service components, and/or determining if a default configuration is provided for use with the particular application or service deployment.
US09898339B2	Meter reading data validation A meter data management (MDM) system processes imported blocks of utility data collected from a plurality of utility meters, sensors, and/or control devices by using independent parallel pipelines associated with differing processing requirements of the data blocks. The MDM system determines processing requirements for each of the imported data blocks, selects one of the pipelines that matches the determined processing requirements for each of the imported data blocks, and directs the data blocks to the selected one of the pipelines for processing. The pipelines may include a validation pipeline for validation processing, an estimation pipeline for estimation processing and a work item pipeline for work item processing.
US09898338B2	Network computer system and method for dynamically changing execution sequence of application programs A computer system and operating method thereof are provided. The computer system comprises a central processing unit (21) and a random access memory (22). The random access memory (22) is provided with a resource allocating management storage region (32) for storing execution sequence of the central processing unit executing an application program, and a resource allocating management unit (31) for dynamically changing the execution sequence according to request amount of resource occupied by a plurality of application programs, wherein the execution sequence is such that the execution priority level of an application program with a small request amount of resource is higher than the execution priority level of an application program with a large request amount of resource. The method comprises the following steps: the resource allocating management unit (31) receives information on request amount of resource sent from a plurality of application programs; writes an execution sequence of the plurality of application programs into the resource allocating management storage region (32); the resource allocating management unit (31) dynamically changes the execution sequence according to request amount of resource occupied by the application programs; and the central processing unit (21) executes the application programs according to the execution sequence.
US09898336B2	Resource allocation for software development Software development data indicative of a development activity is accessed. A component parameter of a component of a software development platform is set, in which the component parameter is based upon, at least in part, an anticipated component workload associated with the development actively. At least one system resource is allocated for the component of the software development platform based upon, at least in part, the component parameter.
US09898335B1	System and method for batch evaluation programs A batching module that prepares a plurality of blocked expressions for batch evaluation. The plurality of blocked expressions comprises a current expression in a particular stack in a blocked state. The batching module divides the plurality of blocked expressions into one or more partitions. For each particular partition of the one or more partitions, a single batch processing call is dispatched to an application server to perform a batch evaluation.
US09898334B1	Method and apparatus for scheduling processing tasks in a pipelined engine The present disclosure provides a method of scheduling data processing at a pipelined data processing engine, and a command scheduler for scheduling data processing at the pipelined data processing engine. The command scheduler determines whether a first data stream is locked to the pipelined data processing engine based on a status of a current data frame of the first data stream in the pipelined data processing engine. The command scheduler will schedule a next data frame of the first data stream to the data processing engine if the first data stream is not locked to the pipelined data processing engine, or it will postpone the scheduling of the next data frame of the first data stream if the first data stream is locked to the pipelined data processing engine.
US09898331B2	Dynamic releasing of cache lines A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.
US09898329B1	Flexible processor association for virtual machines The present disclosure relates to flexible processor association for virtual machine instances. One example method includes initializing a virtual machine instance on a particular computing device, the particular computing device including a plurality of physical processors, determining a maximum number of the physical processors available to be associated with the virtual machine instance; initializing a number of virtual processors for use by the virtual machine instance, the same as the maximum number of the physical processors; associating the virtual machine instance with a number of the physical processors less than the maximum number of the physical processors; during execution of the virtual machine instance: identifying a change in a demand metric associated with the virtual machine instance; and adjusting the number of the physical processors associated with the virtual machine instance based on the identified change in the demand metric while maintaining the number of virtual processors.
US09898326B2	Securing code loading in a virtual environment Methods, systems, and computer program products are included for loading a code module. A method includes providing, by a hypervisor, a virtual machine that includes a guest operating system. The code module and a signature corresponding to the code module are sent by the guest operating system to the hypervisor. One or more relocations are applied to the code module. The hypervisor verifies the signature corresponding to the code module. After verifying the signature, the hypervisor allows the guest operating system to execute the code module.
US09898322B2	Steganographic message passing between a virtual machine and a hypervisor A computer-implemented method may include identifying a plurality of selected bits of usage data of a virtual machine. A desired message may be encoded, by a computer processor, as a steganographic message stored in the plurality of selected bits in the usage data. Encoding the desired message may include manipulating one or more resources of the virtual machine to cause a change in the plurality of selected bits in the usage data. The usage data may be provided to the hypervisor, and the steganographic message may be observable in the usage data.
US09898321B2	Data-driven feedback control system for real-time application support in virtualized networks Concepts and technologies disclosed herein are directed to data-driven feedback control systems for an acceptable level of real-time application transaction completion rate in virtualized networks, while maximizing virtualized server utilization. According to one aspect disclosed herein, a network virtualization platform (“NVP”) includes a plurality of hardware resources, a virtual machine (“VM”), and a virtual machine monitor (“VMM”). The VMM can track an execution state of each of a plurality of applications associated with the VM. The VMM can measure a real-time application transaction completion rate of the VM. The VMM can determine whether a trigger condition exists for priority scheduling of real-time applications based upon the real-time application transaction completion rate and a pre-set threshold value. The VMM can, in response to determining that the trigger condition exists, apply a priority control schedule to instruct the VM to perform priority processing of a real-time application over a non-real-time application.
US09898320B2	Using a delta query to seed live migration Examples perform live migration of objects such as VMs from a source host to a destination host. The disclosure exposes the contents of the storage disk at the destination host, compares the storage disk of the destination host to the source host, and during migration, migrates only data which is not already stored at the destination host. The source and destination VMs have concurrent access to storage disks during migration. After migration, the destination VM executes, with exclusive access to the storage disks.
US09898316B1	Extended fractional symmetric multi-processing capabilities to guest operating systems Operating at least one hypervisor includes running a first hypervisor as a first thread of an underlying operating system, running a second hypervisor as a second thread of the underlying operating system, loading a first guest operating system using the first hypervisor based on the first thread of the underlying operating system, loading a second guest operating system using the second hypervisor based on the second thread of the underlying operating system, and scheduling sharing of resources of the underlying system between the first hypervisor and the second hypervisor according to a scheduler of the underlying operating system, where the first hypervisor and the second hypervisor run independently of each other. The scheduler of the underlying operating system may schedule fractional time shares for the first hypervisor and the second hypervisor to access the same resource.
US09898314B2	Javascript extension tool A method, system, and apparatus for extending JavaScript to operate more fully as an object oriented language. A multiple inheritance module may be configured to enable JavaScript to implement multiple inheritance. A messaging module may be configured to enable JavaScript to implement messaging. A polymorphism module may be configured to enable JavaScript to implement polymorphism.
US09898311B1	Software installation through bootloader management A bootloader detects that an operating system of a computing device has finished booting. In response to detecting with the bootloader that the operating system of the computing device has finished booting, installation of software on the computing device except for particular educational software is disabled. The particular educational software is determined not to be installed on the computing device. In response to determining that educational software is not installed on the computing device, the particular educational software is installed. After installing the particular educational software, a boot sequence of the computing device is modified so that the particular educational software is executed after the operating system has finished booting. The bootloader is disabled.
US09898310B2	Symmetrical dimensions in context-oriented programming to optimize software object execution A method, system, and/or computer program product optimizes execution of a computation. Multiple slots, each of which is a container for information, are defined. A coordinate tuple is defined for each of the multiple slots. The coordinate tuple describes a position of a slot along multiple dimensions in a slot space. The multiple dimensions describe roles for executing a software object, and each of the multiple dimensions has a same level of primacy such that no dimension has primacy over another dimension in the slot space. Multiple method slots are populated with software method objects that address different contexts and purposes as defined by coordinate tuples of the multiple method slots. Software method objects are retrieved from coordinate tuples in the slot space that match a defined context and purpose of a particular computation, which is propagated to a processor that is executing a particular software method object.
US09898306B2	Computing performance and power management with firmware performance data structure In some embodiments, a PPM interface for a computing platform may be provided with functionality to facilitate, to an OS through the PPM interface, firmware performance data.
US09898300B2	Instruction for fast ZUC algorithm processing Vector instructions for performing ZUC stream cipher operations are received and executed by the execution circuitry of a processor. The execution circuitry receives a first vector instruction to perform an update to a liner feedback shift register (LFSR), and receives a second vector instruction to perform an update to a state of a finite state machine (FSM), where the FSM receives inputs from re-ordered bits of the LFSR. The execution circuitry executes the first vector instruction and the second vector instruction in a single-instruction multiple data (SIMD) pipeline.
US09898299B2	Dynamic thread sharing in branch prediction structures Embodiments relate to multithreaded branch prediction. An aspect includes a system for dynamically evaluating how to share entries of a multithreaded branch prediction structure. The system includes a first-level branch target buffer coupled to a processor circuit. The processor circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with the search request, and searching for an entry corresponding to the search request in the first-level branch prediction structure. The entry is not allowed based on a thread state of the entry indicating that the entry has caused a problem on a thread associated with the thread state.
US09898298B2	Context save and restore Processor context save latency is reduced by only restoring context registers with saved state that differs from the reset value of registers. A system agent monitors access to the design blocks and sets a dirty bit to indicate which design block has registers that have changed since the last context save. During a context save operation, the system agent bypasses design blocks that have not had context changes since the latest context save operation. During a context restore operation the system agent does not restore the context registers with saved context values that are equal to the reset value of the context register.
US09898297B2	Issuing instructions to multiple execution units A single chip sequential processor comprising at least one ALU-Block, where said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
US09898296B2	Selective suppression of instruction translation lookaside buffer (ITLB) access Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is from a same address page as a last instruction fetch from the instruction cache; and based, at least in part, on determining that the next instruction fetch is from the same address page, suppressing for the next instruction fetch an instruction address translation table access, and comparing for an address match results of an instruction directory access for the next instruction fetch with buffered results of a most-recent, instruction address translation table access for a prior instruction fetch from the instruction cache.
US09898292B2	Hardware instruction generation unit for specialized processors Methods, devices and systems are disclosed that interface a host computer to a specialized processor. In an embodiment, an instruction generation unit comprises attribute, decode, and instruction buffer stages. The attribute stage is configured to receive a host-program operation code and a virtual host-program operand from the host computer and to expand the virtual host-program operand into an operand descriptor. The decode stage is configured to receive the first operand descriptor and the host-program operation code, convert the host-program operation code to one or more decoded instructions for execution by the specialized processor, and allocate storage locations for use by the specialized processor. The instruction buffer stage is configured to receive the decoded instruction, place the one or more decoded instructions into one or more instruction queues, and issue decoded instructions from at least one of the one or more instruction queues for execution by the specialized processor.
US09898291B2	Microprocessor with arm and X86 instruction length decoders A microprocessor natively translates and executes instructions of both the x86 instruction set architecture (ISA) and the Advanced RISC Machines (ARM) ISA. An instruction formatter extracts distinct ARM instruction bytes from a stream of instruction bytes received from an instruction cache and formats them. ARM and x86 instruction length decoders decode ARM and x86 instruction bytes, respectively, and determine instruction lengths of ARM and x86 instructions. An instruction translator translates the formatted x86 ISA and ARM ISA instructions into microinstructions of a unified microinstruction set architecture of the microprocessor. An execution pipeline executes the microinstructions to generate results defined by the x86 ISA and ARM ISA instructions.
US09898290B2	Efficiency for coordinated start interpretive execution exit for a multithreaded processor A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.
US09898285B2	Method and apparatus for performing logical compare operations A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.
US09898279B2	Optimizing ABAP development as a service A development account is provisioned, the provisioning including a request for a backing service. The backing service includes: generating a developer schema in a database, generating a table link in the developer schema to shared tables required for the new development environment, generating a delta table, and generating a union view with a defined instead-of-trigger used to write, update, or delete from the delta table upon a write, update, or delete operation on the union view. A runtime application server is obtained and a repository is configured in a version control system. The runtime application server is configured to connect to the generated developer schema of the provisioned development account, and an identifier is provided to the provisioned development account.
US09898278B2	Release and management of composite applications on PaaS A solution descriptor comprises a set of component workload units, a workload unit describing a deployable application component with application binary, configuration parameters and dependency declarations. An environment descriptor specifies a set of target platforms and plugins in an execution environment. A deployer interprets the solution descriptor and the environment descriptor, and generates a list of tuples comprising compatible workload-plugin-platform combinations. The deployer determines an execution order for the list of tuples, and invokes the plugins in the list of tuples in the execution order, wherein each of the plugins executes a corresponding compatible workload on a corresponding compatible target platform specified in the list of tuples.
US09898277B2	Replacing an accelerator firmware image without operating system reboot The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.
US09898276B2	Entity wide software tracking and maintenance reporting tool Embodiments of the invention are directed to a system, method, or computer program product for providing an entity wide software tracking and maintenance tool for monitoring maintenance and software updates across an entity. As such, the invention provides a uniform and stable method of monitoring software updates and software installation across an entity's information technology infrastructure. The invention receives software updates or new programs for installation across the entity. The invention then creates a tracking module to link to the maintenance update. The tracking module is a self-contained, self-describing module that contains static information related to the maintenance. Subsequently, the tracking module allows users to monitor the progress of maintenance levels. In some embodiments, the user may query the system to determine the progress of a specific maintenance. In some embodiments, the system may automatically notify a user of the success or failure of maintenance at one or more stages.
US09898273B1	Dynamically updating APIS based on updated configuration file of a computing system Aspects of the present disclosure involve systems and methods for providing extensibility of one or more APIs of a computing system management interface to allow a user of the management interface to dynamically generate new interfaces for data attributes from one or more underlying hardware components of the computing system. In one particular embodiment, a management interface is configured to receive a configuration file from a user of the system through a user interface. The configuration file may define or otherwise indicate a type of API utilized by the management interface to communicate with components of the computing system and receive information concerning those components. The configuration file may also cause the management interface to update the identified API according to the update. By dynamically updating the number and type of APIs utilized by the management interface, the user may obtain information concerning the components of the computing system otherwise not previously available.
US09898271B2	Multiple virtual machines in a mobile virtualization platform Systems and methods are described for embodiments of a mobile virtualization platform (MVP) that may be embedded in an end user mobile device or comprise part of the firmware loaded on the device. The MVP may implement a thin layer of software embedded on the device to decouple applications and data from the underlying hardware, thus enabling the device to concurrently run multiple operating systems. Furthermore, the MVP may enable applications to run concurrently per each base band.
US09898263B2	System and method for resource-definition-oriented software generation and development A system and method for productively developing web services and associated client software to access web services across entire development lifecycle is disclosed. In various aspects, collections of resource definitions stored and managed in a repository and configured and published as network addressable/accessible resources, serve as a platform with application programming interfaces and/or user-interfaces to enable software professionals to continuously define, design, construct, test, publish and access web services.
US09898262B2	User interface event orchestration Methods, systems and computer program products for user interface event orchestration are provided. A computer-implemented method may include defining a business domain object, associating the business domain object with a user interface component type, defining a rule for an event of the user interface component type, generating an event handling routine providing the defined rule in a programming language, and associating the generated event handling routine with a user interface component of an application interface.
US09898261B1	Method and system for configuring processes of software applications using activity fragments A method for creating processes in a software application. The method includes obtaining an activity fragment. The activity fragment includes an activity fragment name and an activity fragment configuration. The method further includes obtaining a process specification specifying an activity, and obtaining activity configuration instructions. The activity configuration instructions specify inclusion of the activity fragment in the activity. The method also includes building, based on the process specification, a process. Building the process includes associating the activity fragment with the activity. In addition, the method includes deploying the software application, including the process.
US09898260B2	Adaptive function-based dynamic application extension framework A mobile device includes a processor and a non-transitory computer-readable medium storing instructions. The instructions include, in response to a state of a first application being instantiated from a first state template of the first application, selecting a first function module identifier from a plurality of predetermined function module identifiers. Each predetermined function module identifier corresponds to a first function offered by the first state template. The instructions include transmitting a function module request to a developer exchange system using a wireless transceiver. The function module request includes the first function module identifier, which uniquely identifies a first function module. The instructions include receiving the first function module from the developer exchange system, storing and executing the first function module, and presenting display data generated by execution of the first function module. The display data is presented in an area reserved for the first function by the first state template.
US09898258B2	Versioning of build environment information A method includes collecting information corresponding to a build environment in which a build result of a source code is generated, the collected information including one or more predefined build environment factors, and storing, in a repository, the collected information as a version of the build environment.
US09898256B2	Translation of gesture to gesture code description using depth camera A system of injecting a code section to a code edited by a graphical user interface (GUI) of an integrated development environment (IDE), comprising: a memory storing a dataset associating each code segment with one hand pose feature or hand motion feature; an imager adapted to capture images of a hand while an IDE being executed on a client terminal; and processor for executing code of an application, comprising: code instructions to identify at least one of the features and at least one discrete value of the identified features from an analysis of the images; code instructions to select at least one of the code segments associated with the identified features; and code instructions to add automatically a code section generated based on the code segments and the discrete value to a code presented by a code editor of the IDE.
US09898253B2	Division operations on variable length elements in memory Examples of the present disclosure provide apparatuses and methods for performing variable bit-length division operations in a memory. An example method comprises performing a variable length division operation on a first vector comprising variable length elements representing a number of dividends and stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second vector comprising variable length elements representing a number of divisors stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include dividing the first vector by the second vector by performing a number of operations. The method can include performing at least one of the number of operations without transferring data via an input/output (I/O) line.
US09898251B2	Bit-matrix multiplication using explicit register The invention relates to a processor comprising, in its instruction set, a bit matrix multiplication instruction (sbmm) having a first double precision operand (A) representing a first matrix to multiply, a second operand (B) explicitly designating any two single precision registers whose joint contents represent a second matrix to multiply, and a destination parameter (C) explicitly designating any two single precision registers for jointly containing a matrix representing the result of the multiplication.
US09898248B2	Method and device for playing modified audio signals A method and a device are provided for modifying audio signals in accordance with hearing capabilities of an individual who is listening to audio signals played by a music player. The method comprises the steps of: providing a music player operative to play audio signals, wherein the music player comprises a processor configured to modify audio signals that are about to be played, by taking into account the hearing capabilities of the individual; providing information that relates to the hearing capabilities of the individual; forwarding the information that relates to the hearing capabilities of the individual, from an electronic device to the music player; and using the music player processor to modify audio signals when the individual is listening to audio signals being played by the music player, wherein the audio signals are modified before they are played by taking into account the individual's hearing capabilities.
US09898244B2	Portable playback device state variable Systems, methods, apparatus, and articles of manufacture to facilitate playback of multimedia content are disclosed. An example apparatus includes a network interface configured to receive audio content over a playback network. A processor comprising instructions which when executed, cause the processor to detect that a portable playback device has joined the playback network. The processor is to update a state variable to indicate that the portable playback device has joined the playback network. The processor is to play audio content received over the playback network based on the state variable. The processor is to detect that the portable playback device is not joined to the playback network. The processor is to, after detecting that the portable playback device is not joined to the playback network, update the state variable to indicate that the portable playback device is not joined to the playback network.
US09898238B2	Printing control terminal device connectable to an image forming apparatus having a resource saving mode and method for printing control thereof A printing control terminal device including an input unit to receive a printing order to request a printing operation for a printing work, a communication interface unit to receive information regarding a resource saving mode from an image forming apparatus, a display unit to display information regarding the received resource saving mode, a printer driver unit to generate printing data for the printing work, and a controller to control the communication interface unit to transmit the generated printing data to the image forming apparatus.
US09898237B1	System and method of printing using mixed paper sizes A system and method of printing involves the use of mixed paper sizes in which the orientation of printing media can be selected to avoid a mixture of paper sheet orientations in the output document when auto tray selection has been selected by a user.
US09898235B2	Marking agent credit adjustments In one example of the disclosure, account data that is indicative of marking agent credits attributed to a printer is stored. The printer is a printer connected to a supply of marking agent. A marking agent credit is to authorize consumption of a credit amount of marking agent from the supply according to a subscription. A print job is received from a sponsor computing device. The account data is adjusted to add credits in an adjustment amount that is a function of marking agent consumption to print the job. The job is sent to the printer for printing.
US09898234B2	Printer, operation terminal, and recording medium The disclosure discloses a printer including a communication device, a processor, and a memory. The memory stores computer-executable instructions that cause the printer to perform a connection control process, an operation control process, and a mode control process. In the connection control process, an exclusive connection with a first operation terminal is established while excluding at least one second operation terminal. In the operation control process, printing is performed by controlling plurality of operation mechanisms after establishment of the exclusive connection. In the mode control process, a first switching mode or a second switching mode is selectively executed. The exclusive connection established with the first operation terminal is disconnected at a predetermined timing after completion of the printing in the first switching mode. The exclusive connection established with the first operation terminal is maintained without being disconnected at the predetermined timing in the second switching mode.
US09898232B2	Method and device for sequencing print jobs In a method to administer, via a print job administrator, print jobs to be printed at a printing system, a plurality of print jobs are determined. A print job can indicate a specification of one or more print features. Different specifications of a print feature may require different configurations of the printing system. Change-over expenditures for the printing of at least two print jobs of the plurality of print jobs by the printing system can be determined based on the specification of the one or more print features of the plurality of print jobs. An order for the printing of the plurality of print jobs can be determined based on the change-over expenditures. The order of the plurality of print jobs can be indicated.
US09898231B2	System and method of mobile printing using near field communication A method of mobile printing using near field communication (NFC) includes executing a mobile printing application installed in a mobile device; setting a wireless connection for data transmission between the mobile device and an image forming apparatus by performing NFC tagging on the image forming apparatus with the mobile device; and automatically performing a function corresponding to a status of the mobile printing application when NFC tagging is performed.

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