最新美国发明专利第2018-02-20期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09899567B2	Light emitting device A light emitting device includes a metal layer, a light emitting structure, an electrode disposed on a first upper portion of a second conductive type semiconductor layer, a current spreading portion disposed on a second upper portion of the second conductive type semiconductor layer, an adhesive layer disposed under a first conductive type semiconductor layer, an insulating layer disposed between the electrode and the adhesive layer, a passivation layer disposed on a side surface of the light emitting structure and on a at least one upper surface of the light emitting structure, and a reflective layer disposed between the metal layer and the first conductive type semiconductor layer.
US09899566B2	Optoelectronic device comprising microwires or nanowires The invention relates to an optoelectronic device comprising microwires or nanowires, each having at least one active portion (34, 39) between two insulated portions (32, 36, 40), the active portion having inclined flanks or having a diameter different from the diameter of at least one of the two insulated portions.
US09899563B2	Method of fabricating light-emitting diode with a micro-structure lens A light emitting diode (LED) with a micro-structure lens includes a LED die and a micro-structure lens. The micro-structure lens includes a convex lens portion, at least one concentric ridge structure surrounding the convex lens portion, and a lower portion below the convex lens portion and the at least one concentric ridge structure. The lower portion is arranged to be disposed over the LED die. A first optical path length from an edge of the LED die to a top center of the microstructure lens is substantially the same as a second optical path length from the edge of the LED die to a side of the micro-structure lens.
US09899558B2	Photosensor and display device including the same A disclosed photosensor includes: a first electrode layer including a reflection part having an inclination surface; a first semiconductor layer positioned on the first electrode layer; a second electrode layer positioned on the first semiconductor layer; and a first dielectric layer and a second dielectric layer sequentially positioned on the second electrode layer, wherein the first dielectric layer and the second dielectric layer have different dielectric constant values. Further, the disclosed display device includes a plurality of pixel areas positioned on a substrate, and a sensor unit formed in at least some pixel areas among the plurality of pixel areas.
US09899557B2	Avalanche photodiode operating in geiger mode including a structure for electro-optical confinement for crosstalk reduction, and array of photodiodes An avalanche photodiode includes a cathode region and an anode region. A lateral insulating region including a barrier region and an insulating region surrounds the anode region. The cathode region forms a planar optical guide within a core of the cathode region, the guide being configured to guide photons generated during avalanche. The barrier region has a thickness extending through the planar optical guide to surround the core and prevent propagation of the photons beyond the barrier region. The core forms an electrical-confinement region for minority carriers generated within the core.
US09899553B2	Adhesive sheet and protective sheet for solar cell A readily adhesive sheet including a base material film and an olefin-based polymer layer which is disposed on at least one surface of the base material film and contains at least one binder, which is an olefin-based binder having an elastic modulus of 320 MPa or less, at least one coloring pigment selected from titanium oxide, carbon black, titanium black, black combined metal oxides, cyanine-based colors and quinacridone-based colors, and a crosslinking agent has a favorable adhesion to the sealing material even after aged in a hot and humid environment.
US09899552B2	Edge-protection tape A self-adhesive edge-protection tape is intended to improve the protective effect for glass edges. This is achieved by providing an adhesive tape which comprises, in sequence directed towards the substrate to be covered, a backing layer (hard phase) and a soft phase comprising a polymer foam, a viscoelastic composition and/or an elastomeric composition, where the thickness of the hard phase is ≦150 μm, the thickness of the soft phase is ≧200 μm and the ratio of the thickness of the soft phase to the thickness of the hard phase is ≧4. The invention also relates to a solar module which comprises an adhesive tape according to the invention adhesive-bonded around at least one portion of the edges thereof, and the use of the claimed adhesive tape for the protection of edges of a solar module.
US09899550B2	Electric power transfer system using optical power transfer An apparatus and method for optical-power-transfer (OPT). A light source converts electrical energy into light, and the light is transmitted from the active layer of the light source directly to the active layers of a series of photovoltaic (PV) devices without first passing through a conduction layer of the PV device. Thus, absorption in the conduction layer is avoided, and the efficiency of the OPT system is improved. The PV devices are configured to each generate equal current, and the PV devices are electrically connected in series. PV devices are arranged in series with light first propagating through PV devices closer to the light source, and farther PV devices having a longer propagation length, such that the light absorbed and current generated by each PV device is equal to the other PV devices. In one implementation, the PV devices are configured in a laser cavity with the light source.
US09899548B2	Solar cell unit A solar cell unit having a semiconductor body formed as a solar cell, whereby the semiconductor body has a front side with a first electrical connection and a back side with a second electrical connection and a side surface formed between the front side and the back side, and having a substrate with a top side and a bottom side, whereby the substrate on the top side has a first conductive trace region, configured as part of the substrate, and the first electrical connection is electrically connected to the first conductive trace region, and the substrate on the top side has a second conductive trace region, configured as part of the substrate, and the second electrical connection is electrically connected to the second conductive trace region, and having a secondary optical element, which has a bottom side and guides light to the front side of the semiconductor body.
US09899547B2	Multi-wavelength detector array incorporating two dimensional and one dimensional materials A method of forming a wavelength detector that includes forming a first transparent material layer having a uniform thickness on a first mirror structure, and forming an active element layer including a plurality of nanomaterial sections and electrodes in an alternating sequence atop the first transparent material layer. A second transparent material layer is formed having a plurality of different thickness portions atop the active element layer, wherein each thickness portion correlates to at least one of the plurality of nanomaterials. A second mirror structure is formed on the second transparent material layer.
US09899537B2	Semiconductor device with transition metal dichalocogenide hetero-structure The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal dichalcogenide film on a substrate; a second transition metal dichalcogenide film on the first transition metal dichalcogenide film; source and drain features formed over the second transition metal dichalcogenide film; and a first gate stack formed over the second transition metal dichalcogenide film and interposed between the source and drain feature.
US09899536B2	Method of forming semiconductor device with different energy gap oxide semiconductor stacked layers A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor device which includes a first oxide semiconductor layer which is in contact with a source electrode layer and a drain electrode layer and a second oxide semiconductor layer which serves as a main current path (channel) of a transistor is provided. The first oxide semiconductor layer serves as a buffer layer for preventing a constituent element of the source and drain electrode layers from diffusing into the channel. By providing the first oxide semiconductor layer, it is possible to prevent diffusion of the constituent element into an interface between the first oxide semiconductor layer and the second oxide semiconductor layer and into the second oxide semiconductor layer.
US09899535B2	Semiconductor device To provide a transistor with stable electrical characteristics, a transistor with a low off-state current, a transistor with a high on-state current, a semiconductor device including the transistor, or a durable semiconductor device. The semiconductor device includes a first transistor using silicon, an aluminum oxide film over the first transistor, and a second transistor using an oxide semiconductor over the aluminum oxide film. The oxide semiconductor has a lower hydrogen concentration than silicon.
US09899534B2	Thin-film transistor and method for forming the same A TFT includes a substrate, a gate, a gate insulating layer, a semiconductor oxide layer, a source/drain layer, a passivation layer, and a transparent conducting layer arranged from bottom to top. An etching block layer is formed after the source/drain layer arranged on the semiconductor oxide layer is etched. A method for forming for the TFT includes: depositing and photo-etching a gate on a substrate; depositing a gate insulating layer on the gate; depositing and photo-etching a semiconductor oxide layer on the gate insulating layer; depositing and photo-etching a source/drain layer on the semiconductor oxide layer; etching the source/drain layer on the semiconductor oxide layer for forming an etching block layer; depositing a passivation layer on the source/drain layer and the semiconductor oxide layer; depositing a transparent conducting layer on the passivation layer.
US09899529B2	Method to make self-aligned vertical field effect transistor A method for making a self-aligned vertical nanosheet field effect transistor. A vertical trench is etched in a layered structure including a plurality of layers, using reactive ion etching, and filled, using an epitaxial process, with a vertical semiconductor nanosheet. A sacrificial layer from among the plurality of layers is etched out and replaced with a conductive (e.g., metal) gate layer coated with a high-dielectric-constant dielectric material. Two other layers from among the plurality of layers, one above and one below the gate layer, are doped, and act as dopant donors for a diffusion process that forms two PN junctions in the vertical semiconductor nanosheet.
US09899528B2	Manufacturing method for TFT array substrate, TFT array substrate and display device The disclosure provides a manufacturing method for TFT array substrate, a TFT array substrate and a display device. The manufacturing method includes following steps: in sequence, forming a gate pattern layer, a gate insulating layer, a patterned poly-silicon layer, a separation layer on s substrate, and adopting a mask to form a source pattern layer and a drain pattern layer on the separation layer by photolithography processes. The source pattern layer and the drain pattern layer are connected to the patterned poly-silicon layer. The mask blocks one side of the channel area, and the same mask is adopted to form a lightly doped area on the other side of the channel area not blocked by the mask. The disclosure may reduce production costs and has great design flexibility.
US09899522B1	Semiconductor device and method for fabricating the same A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a first recess adjacent to two sides of the gate structure; forming an epitaxial layer in the first recess; removing part of the epitaxial layer to forma second recess; and forming an interlayer dielectric (ILD) layer on the gate structure and into the second recess.
US09899519B2	Defect-Free SiGe source/drain formation by epitaxy-free process MOSFET transistors having localized stressors for improving carrier mobility are provided. Embodiments of the invention comprise a gate electrode formed over a substrate, a carrier channel region in the substrate under the gate electrode, and source/drain regions on either side of the carrier channel region. The source/drain regions include an embedded stressor having a lattice constant different from the substrate. In a preferred embodiment, the substrate is silicon and the embedded stressor is SiGe. Implanting a portion of the source/drain regions with Ge forms the embedded stressor. Implanting carbon into the source/drain regions and annealing the substrate after implanting the carbon suppresses dislocation formation, thereby improving device performance.
US09899517B2	Dislocation stress memorization technique (DSMT) on epitaxial channel devices The present disclosure relates to a transistor device having epitaxial source and drain regions with dislocation stress memorization (DSM) regions that provide stress to a channel region. In some embodiments, the transistor device has an epitaxial source region arranged within a substrate. An epitaxial drain region is arranged within the substrate and is separated from the epitaxial source region by a channel region. A first DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial source region to a location within the epitaxial source region. A second DSM region, which has a stressed lattice configured to generate stress within the channel region, extends from below the epitaxial drain region to a location within the epitaxial drain region.
US09899516B2	Engineered ferroelectric gate devices Coupling of switchable ferroelectric polarization with the carrier transport in an adjacent semiconductor enables a robust, non-volatile manipulation of the conductance in a host of low-dimensional systems, including the two-dimensional electron liquid that forms at the LaAlO3—SrTiO3 interface. However, the strength of the gate-channel coupling is relatively weak, limited in part by the electrostatic potential difference across a ferroelectric gate. Compositionally grading of PbZr1-xTixO3 ferroelectric gates enables a more than twenty-five-fold increase in the LAO/STO channel conductance on/off ratios. Incorporation of polarization gradients in ferroelectric gates can enable significantly enhanced performance of ferroelectric non-volatile memories.
US09899515B1	Fabrication of a pair of vertical fin field effect transistors having a merged top source/drain A method of fabricating a vertical fin field effect transistor with a merged top source/drain, including, forming a source/drain layer at the surface of a substrate, forming a plurality of vertical fins on the source/drain layer; forming protective spacers on each of the plurality of vertical fins, forming a sacrificial plug between two protective spacers, forming a filler layer on the protective spacers not in contact with the sacrificial plug, and selectively removing the sacrificial plug to form an isolation region trench between the two protective spacers.
US09899508B1	Super junction semiconductor device for RF applications, linear region operation and related manufacturing process Embodiments are directed to super-junction semiconductor devices having an inactive region positioned between active cells. In one embodiment, a semiconductor device is provided that includes a substrate and a drain region on the substrate. The drain region has a first conductivity type. A plurality of first columns is disposed on the drain region, with the first columns having the first conductivity type. A plurality of second columns is disposed on the drain region, with the second columns having a second conductivity type. The first and second columns are alternately arranged such that each of the second columns is positioned between respective first columns. First and second gate structures are included that overlie respective first columns, and a body region is included that has the second conductivity type. The body region abuts at least two second columns and at least one first column positioned between the at least two second columns.
US09899505B2	Conductivity improvements for III-V semiconductor devices Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
US09899504B2	Power semiconductor transistor having increased bipolar amplification A transistor includes first and second load terminals and a semiconductor body coupled to both terminals. The semiconductor body includes: a drift region having dopants of a first conductivity type; a transistor section for conducting a forward load current and having a control head coupling the first load terminal to a first side of the drift region; and a diode section for conducting a reverse load current. A diode port couples the second load terminal to a second side of the drift region and includes: a first emitter electrically connected to the second load terminal and having dopants of the first conductivity type for injecting majority charge carriers into the drift region; and a second emitter having dopants of a second conductivity type for injecting minority charge carriers into the drift region. A pn-junction transition between the first and second emitters has a breakdown voltage of less than 10 V.
US09899497B2	Method of fabricating semiconductor device A method of fabricating a semiconductor device is disclosed. The method includes forming an active pattern protruding orthogonally from a substrate; forming a preliminary gate structure on the active pattern to cross the active pattern; etching the active pattern to form preliminary recess regions at both sides of the preliminary gate structure, wherein each of the preliminary recess regions is formed to define a delta region in an upper portion of the active pattern; forming a sacrificial layer on inner side surfaces and a bottom surface of the active pattern exposed by each of the preliminary recess regions; etching the delta regions and the sacrificial layer to form recess regions having a ‘U’-shaped section; and forming source/drain regions in the recess regions.
US09899496B2	Method of making a finFET device The present disclosure provides a device having a doped active region disposed in a substrate. The doped active region having an elongate shape and extends in a first direction. The device also includes a plurality of first metal gates disposed over the active region such that the first metal gates each extend in a second direction different from the first direction. The plurality of first metal gates includes an outer-most first metal gate having a greater dimension measured in the second direction than the rest of the first metal gates. The device further includes a plurality of second metal gates disposed over the substrate but not over the doped active region. The second metal gates contain different materials than the first metal gates. The second metal gates each extend in the second direction and form a plurality of respective N/P boundaries with the first metal gates.
US09899494B2	Methods of forming silicide regions and resulting MOS devices A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.
US09899493B2	High electron mobility transistor and method of forming the same A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.
US09899491B2	Semiconductor device and method of forming the same A semiconductor device and a method of forming the same, the semiconductor device include a substrate, and a first gate structure and a second gate structure disposed on the substrate. The first gate structure includes a barrier layer, a first work function layer, a second work function layer and a conductive layer stacked one over another on the substrate. The second gate structure includes the barrier layer, a portion of the first work function layer and the conductive layer stacked one over another on the substrate, wherein the portion of the first work function layer has a smaller thickness than a thickness of the first work function layer.
US09899490B2	Semiconductor structure with changeable gate length and method for forming the same A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a nanowire structure formed over the substrate. In addition, the nanowire structure includes a first portion, a second portion, and a third portion. The semiconductor structure further includes a gate structure formed around the third portion of the nanowire structure and a source region formed in the first portion of the nanowire structure. In addition, a depletion region in the nanowire structure has a length longer than a length of the gate structure and is not in contact with the source region.
US09899487B2	Semiconductor devices and methods of manufacturing the same A semiconductor device may include a linear gate trench that crosses an active region of a substrate of the semiconductor device. The active region may include a plurality of gate areas at a bottom of the gate trench and junction areas at a surface of the substrate in a central portion and opposite end portions of the active region. A conductive line may be in a lower portion of the gate trench. The conductive line may include a gate line and a capping layer that at least partially isolates the gate line from an upper surface of the conductive line. A sealing line may be in an upper portion of the gate trench. The sealing line may cover the conductive line and a surface of the sealing line may be coplanar with the junction areas.
US09899481B2	Electronic component and switch circuit In an embodiment, an electronic component includes a compound semiconductor transistor device having a first current electrode, a second current electrode and a control electrode, a die pad, a first lead, a second lead and a third lead. The first lead, the second lead and the third lead are spaced at a distance from the die pad. The control electrode is coupled to the first lead, the first current electrode is coupled to the die pad and the second current electrode is coupled to the second lead. The third lead is coupled to the compound semiconductor transistor device and provides a source sensing functionality.
US09899480B2	Single transistor random access memory using ion storage in two-dimensional crystals A single-transistor random access memory (RAM) cell may be used as universal memory. The single-transistor RAM cell generally includes a first gate, a 2D-crystal channel, a source, a drain, an ion conductor, and a second (back) gate. The single-transistor RAM cell is capable of drifting ions towards the graphene channel. The ions in turn induce charge carriers from the source into the graphene channel. The closer the ions are to the graphene channel, the higher the conductivity of the graphene channel. As the ions are spaced from the graphene channel, the conductivity of the graphene channel is reduced. Thus the presence of the charged ions adjacent to the channel is used to modify the channel's conductivity, which is sensed to indicate the state of the memory.
US09899478B2	Desaturable semiconductor device with transistor cells and auxiliary cells A semiconductor device includes transistor cells that connect a first load electrode with a drift structure forming first pn junctions with body zones when a gate voltage applied to a gate electrode exceeds a first threshold voltage. First auxiliary cells in a vertical projection of and electrically connected with the first load electrode are configured to inject charge carriers into the drift structure at least in a forward biased mode of the first pn junctions. Second auxiliary cells are configured to inject charge carriers into the drift structure at high emitter efficiency when in the forward biased mode of the first pn junctions the gate voltage is below a second threshold voltage lower than the first threshold voltage and at low emitter efficiency when the gate voltage exceeds the second threshold voltage.
US09899468B2	Adaptive capacitors with reduced variation in value and in-line methods for making same A method of making a capacitor with reduced variance comprises providing a bottom plate in a first metal layer, a first dielectric material over the bottom plate, and a middle plate in a second metal layer to form a first capacitor. The method also comprises measuring the capacitance of the first capacitor, and determining whether to couple none, one, or both of a second capacitor and a third capacitor in parallel with the first capacitor. The method may further comprise the steps of providing a second dielectric material over the middle plate, and providing a first top plate and a second top plate in a third metal layer to form the second capacitor, and a third capacitor. Electrical connections may be formed to couple one or both of the second capacitor and the third capacitor in parallel with the first capacitor based on the measured value of the first capacitor.
US09899464B2	Organic light emitting diode display An organic light emitting diode display includes a substrate, a scan line on the substrate for transferring a scan signal, a data line crossing the scan line and for transferring a data signal, a driving voltage line crossing the scan line and for transferring a driving voltage, a switching thin film transistor coupled to the scan line and the data line, a driving thin film transistor coupled to a switching drain electrode of the switching thin film transistor, and an organic light emitting diode (OLED) coupled to a driving drain electrode of the driving thin film transistor, wherein a driving semiconductor layer of the driving thin film transistor is bent and in a plane substantially parallel to the substrate.
US09899460B2	Organic light emitting display device Discussed is an organic light emitting display device that can include a bank that defines the periphery of an emission area; a structure disposed on the bank; a first electrode disposed in the emission area; an organic layer disposed on the bank, the structure, and the first electrode, an organic layer disposed on the structure being separated from other organic layers; and a second electrode disposed on the organic layer.
US09899458B2	Organic light-emitting display device and method of manufacturing the same An organic light-emitting display device comprises: a substrate; a thin film transistor (TFT) disposed on the substrate; a protection film disposed on the substrate so as to cover the TFT and including a hole; a pixel electrode disposed on the protection film so as to cover an inner surface of the hole, and electrically connected to the TFT; a pixel-defining film disposed on the pixel electrode and the protection film and including an opening that exposes a part of the pixel electrode; and first and second spacers disposed on the pixel-defining film. The first spacer is disposed so as to correspond to the hole, and a height of the second spacer is higher than a height of the first spacer.
US09899453B2	Pixel of a multi-stacked CMOS image sensor and method of manufacturing the same Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC.
US09899447B2	Solid-state imaging device, method for driving the same, and imaging device a CMOS image sensor including a pixel array unit having pixels arranged in even-numbered pixel rows and odd-numbered pixel rows. A reading operation performed such that a first signal of a first pixel group is read in a first accumulation time, and a second signal of a second pixel group is read in a second accumulation time shorter than said first accumulation time.
US09899445B2	Method for manufacturing solid-state image pickup apparatus, solid-state image pickup apparatus, and image pickup system including the same A method for manufacturing a solid-state image pickup apparatus includes forming a first insulating film over a substrate after forming a gate electrode of a first transfer transistor and a gate electrode of a second transfer transistor, forming a second insulating film on the first insulating film, forming a first structure and a second structure on side surfaces of the gate electrodes of the first and second transfer transistors, respectively, via the first insulating film by etching the second insulating film in such a manner that the first insulating film remains on a semiconductor region of a photoelectric conversion unit and a semiconductor region of a charge holding unit, and forming a light shielding film that covers the gate electrode of the first transfer transistor, the semiconductor region of the charge holding unit, and the gate electrode of the second transfer transistor.
US09899443B2	Complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package with an image buffer A complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) package is provided. The image sensor package comprises a first integrated circuit (IC) die, a second IC die, and a fan-out structure. The first IC die comprises a pixel sensor array, and the second IC die is under and bonded to the first IC die. Further, the fan-out structure is under and bonded to the second IC die. The fan-out structure comprises a third IC die, a fan-out dielectric layer laterally adjacent to the third IC die, a through insulator via (TIV) extending through the fan-out dielectric layer, and one or more redistribution layers (RDLs) under the third IC die and the TIV. The one or more RDLs electrically couple to the third IC die and the TIV. A method for manufacturing the CIS package is also provided.
US09899441B1	Deep trench isolation (DTI) structure with a tri-layer passivation layer A method for manufacturing a deep trench isolation (DTI) structure with a tri-layer passivation layer is provided. An etch is performed into a semiconductor substrate to form a trench. A first undoped semiconductor layer is formed by epitaxy lining surfaces of the semiconductor substrate that define the trench. A doped semiconductor layer is formed by epitaxy over and lining the first undoped semiconductor layer in the trench. A second undoped semiconductor layer is formed by epitaxy over and lining the doped semiconductor layer in the trench. A structure resulting from the method is also provided.
US09899440B2	Solid state imaging device and electronic apparatus A solid state imaging device including: a pixel region that is formed on a light incidence side of a substrate and to which a plurality of pixels that include photoelectric conversion units is arranged; a peripheral circuit unit that is formed in a lower portion in the substrate depth direction of the pixel region and that includes an active element; and a light shielding member that is formed between the pixel region and the peripheral circuit unit and that shields the incidence of light, emitted from an active element, to the photoelectric conversion unit.
US09899427B2	Self-emission type display A self-emission type display including a carrier substrate, a light-emitting element, a first electrode, and a second electrode is provided. The light-emitting element is disposed on the carrier substrate and has a first pad and a second pad. The first electrode has a plurality of first stripe portions electrically connected to a first electric potential. The first pad of the light-emitting element is electrically connected to the carrier substrate through at least one first strip portion. The second electrode has a plurality of second stripe portions electrically connected to a second electric potential. The first electrode and the second electrode are separated from each other. The second pad of the light-emitting element is electrically connected to the carrier substrate through at least one second strip portion. The first electric potential is different from the second electric potential.
US09899424B2	Semiconductor device and electronic device Decrease of the output voltage of the logic circuit is inhibited by raising the gate voltage using a capacitor. In a first transistor, a drain and a gate are electrically connected to a first wiring, and a source is electrically connected to a first node. In a second transistor, a drain is electrically connected to the first node, a source is electrically connected to a second wiring, and a gate is electrically connected to a second node. In a third transistor, a drain is electrically connected to a third wiring, and a source is electrically connected to a third node, and a gate is electrically connected to the first node. In a fourth transistor, a drain is electrically connected to the third node, a source is electrically connected to a fourth wiring, and a gate is electrically connected to the second node. In a capacitor, one electrode is electrically connected to the first node, and the other electrode is electrically connected to the third node. OS transistors are preferably used as the transistors above.
US09899417B2	Semiconductor structure including a first transistor and a second transistor A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.
US09899413B2	Integrated structures and methods of forming vertically-stacked memory cells Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.
US09899412B2	Vertical semiconductor device A vertical semiconductor device includes a channel structure extending from a substrate in a first direction perpendicular to an upper surface of the substrate, and a ground selection line, word lines, and a string selection line sequentially formed on a side surface of the channel structure in the first direction to be separated from one another. The channel structure includes a protruding region formed in a side wall portion of the channel structure between the ground selection line and the upper surface of the substrate, the protruding region protruding in a horizontal direction perpendicular to the first direction.
US09899411B2	Three-dimensional semiconductor memory device and method for fabricating the same A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures.
US09899409B2	Nonvolatile memory device having pad structure for high speed operation A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a first metal layer, a peripheral circuit configured to control the memory cell array, a second metal layer, and a pad. The first metal layer is disposed on the memory cell array and includes a plurality of cell region interconnections connected to the memory cell array. The second metal layer is disposed on the peripheral circuit and includes a plurality of peripheral region interconnections connecting the peripheral circuit and the plurality of cell region interconnections. The pad is disposed on the second metal layer and exchanges data, an address, or a command with the peripheral circuit during operation of the device. The second metal layer is lower than the first metal layer relative to a substrate of the device.
US09899406B2	Vertical NAND flash memory device Provided is a vertical NAND flash memory device. The vertical NAND flash memory device may include word lines formed on a substrate, a plurality of pads horizontally extending from the word lines, and contact plugs connected to respective pads. The contact plugs may include a first contact plug connected to a lowermost pad that is closest to the substrate, and a set of second contact plugs each second contact plug connected to a corresponding pad of the plurality of pads. A first distance between the first contact plug and a second contact plug of the set of second contact plugs that is adjacent to the first contact plug may be different from second distances between adjacent contact plugs of the set of second contact plugs. The second distances may be substantially the same as each other.
US09899403B2	Semiconductor device and method of manufacturing the same Resistance of a FINFET is reduced while performance of an element is prevented from being deteriorated due to an increase in stress, thereby performance of a semiconductor device is improved. When a memory cell formed on an upper side of a first fin and an n transistor formed on an upper side of a second fin are mounted on the same semiconductor substrate, the surface of the first fin having a source/drain region of the memory cell is covered with a silicide layer, and part of a source/drain region of the n transistor is formed of an epitaxial layer covering the surface of the second fin.
US09899400B2	Semiconductor device and method of manufacturing the same A semiconductor device and a method of manufacturing a semiconductor device may be provided. The semiconductor device may include first channel layers arranged in a first direction. The semiconductor device may include second channel layers adjacent to the first channel layers in a second direction crossing the first direction and arranged in the first direction. The semiconductor device may include insulating layers stacked while surrounding side walls of the first and second channel layers. The semiconductor device may include conductive layers interposed between the insulating layers, and including first metal patterns extended in the first direction and second metal patterns extended in the first direction while surrounding the side walls of the first channel layers.
US09899399B2	3D NAND device with five-folded memory stack structure configuration A three-dimensional semiconductor device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack and arranged in at least five rows that extend along a first horizontal direction, contact via structures arranged in a same number of rows as the memory stack structures and overlying the memory stack structures, each of the contact via structures being electrically connected to a semiconductor channel of a respective memory stack structure, bit lines contacting a respective contact via structure and extending along a second horizontal direction that is different from the first horizontal direction, and a pair of wall-shaped via structures extending through the alternating stack and laterally extending along the first horizontal direction.
US09899397B1	Integration of floating gate memory and logic device in replacement gate flow After forming a first sacrificial gate stack over a portion of a first semiconductor fin located in a logic device region of a substrate, and a second sacrificial gate stack over a portion of a second semiconductor fin located in a memory device region of the substrate, in which each of the first sacrificial gate stack and the second sacrificial gate stack includes, from bottom to top, a tunneling oxide portion, a floating gate electrode, a control oxide portion, a gate conductor and a gate cap, an entirety of the first sacrificial gate stack is removed to provide a first gate cavity, and only the gate cap and the gate conductor are removed from the second sacrificial gate stack to provide a second gate cavity. Next, a high-k gate dielectric and a gate electrode are formed within each of the first gate cavity and the second gate cavity.
US09899395B1	Semiconductor device and method for manufacturing the same A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.
US09899394B2	Vertical memory devices having contact plugs contacting stacked gate electrodes A vertical memory device includes a plurality of gate electrodes at a plurality of levels, respectively, spaced apart from each other in a vertical direction substantially perpendicular to a top surface of a substrate, a channel extending in the vertical direction on the substrate and penetrating through the gate electrodes, and a plurality of contact plugs extending in the vertical direction and contacting the gate electrodes, respectively. At least one second contact plug is formed on a first gate electrode among the plurality of gate electrodes, and extends in the vertical direction.
US09899390B2	Methods and systems for reducing electrical disturb effects between thyristor memory cells using heterostructured cathodes Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.
US09899389B2	Two-transistor SRAM semiconductor structure and methods of fabrication A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM.
US09899385B2	Semiconductor integrated circuit and manufacturing method thereof A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.
US09899384B2	Self aligned structure and method for high-K metal gate work function tuning A semiconductor device and a method for fabricating the device. The method includes: forming a STI in a substrate having a nFET and a pFET region; depositing a high-k layer and a TiN layer; depositing a polycrystalline silicon layer; forming a block level litho layer; removing a portion of the polycrystalline silicon layer; removing the block level litho layer; forming a first protective layer; depositing a fill layer above the pFET region; removing the first protective layer; cutting the TiN layer and the high-k layer to expose a portion of the STI; depositing a second protective layer on the STI; removing the fill layer; removing the TiN layer above the pFET region; treating the high-k layer with a work function tuning process; removing the polycrystalline silicon layer and TiN layer; and depositing a metal layer on the high-k layer and the second protective layer.
US09899376B2	MOSFET transistors with robust subthreshold operations An integrated circuit with transistor regions formed on a substrate. Each transistor region includes a channel region and a terminal region. The channel region is positioned along a traverse dimension, and it includes a channel edge region along a longitudinal dimension. The terminal region is positioned adjacent to the channel region, and it is doped with a first dopant of a first conductivity type. Each transistor region may include an edge block region, which is positioned along the longitudinal dimension and adjacent to the channel edge region. The edge block region is doped with a second dopant of a second conductivity type opposite to the first conductivity type. The channel region doped with a dopant and having a first doping concentration. Each transistor region may include an edge recovery region overlapping with the channel edge region and having a second doping concentration higher than the first doping concentration.
US09899375B1	Co-integration of self-aligned and non-self aligned heterojunction bipolar transistors The present disclosure relates to semiconductor structures and, more particularly, to co-integration of self-aligned and non-self aligned heterojunction bipolar transistors and methods of manufacture. The structure includes at least two heterojunction bipolar transistor (HBT) devices integrated onto a same wafer with different epitaxial base profiles. An intrinsic base epitaxy for a second device of the at least two HBT devices acts as an extrinsic base for a first device of the at least two HBT devices.
US09899367B2	Integrated circuit including lateral insulated gate field effect transistor An embodiment of an integrated circuit includes a minimum lateral dimension of a semiconductor well at a first surface of a semiconductor body. The integrated circuit further includes a first lateral DMOSFET having a load path electrically coupled to a load pin. The first lateral DMOSFET is configured to control a load current through a load element electrically coupled to the load pin. A minimum lateral dimension of a drain region of the first lateral DMOSFET at the first surface of the semiconductor body is more than 50% greater than the minimum lateral dimension.
US09899363B1	Fin-FET resonant body transistor Circuit structures including a FinFET resonant body transistor are disclosed. One circuit structure includes: a plurality of fins over a substrate and a plurality of gate structures over the plurality of fins, the plurality of gate structures comprising at least one voltage sensing gate, and at least two of the plurality of fins comprising multiple pn-junctions disposed on opposing sides of the at least one voltage sensing gate, the multiple pn-junctions being fabricated to operate as driving units; at least one phononic crystal, wherein the at least one phononic crystal is arranged to confine vibrational energy arising from electrically induced mechanical stresses in the fins comprising driving units; and, wherein the electrically induced mechanical stresses modulate carrier mobility in the at least one voltage sensing gate to produce a current extractable by the circuit structure.
US09899359B1	Light emitting diode package structure, method for making the same, and flat panel light source having the same A vertically shallow LED package structure includes at least one LED chip, a package layer, and a first cover layer. Each LED chip includes a first bottom surface. The package layer covers and wraps around each LED chip, and can absorb light emitted by each LED chip and emit light with a different preset wavelength. The package layer includes a second bottom surface facing the first bottom surface, a first side surface perpendicular to the second bottom surface, and a convex surface interconnecting the second bottom surface and the first side surface. The convex surface protrudes away from the LED chip. The convex surface can reflect the light with the preset wavelength towards the first side surface. The first cover layer covers the package layer and exposes the first side surface.
US09899356B2	Semiconductor light-emitting device A semiconductor light emitting device (A) includes an elongated substrate (1) formed with a through-hole (11), a first, a second and a third semiconductor light emitting elements (3R, 3G, 3B) mounted on the main surface of the substrate (1), and an electrode (2R) electrically connected to the first semiconductor light emitting element (3R) and extending to the reverse surface of the substrate (1) via the through-hole (11). The first semiconductor light emitting element (3R) and the through-hole (11) are positioned between the second semiconductor light emitting element (3G) and the third semiconductor light emitting element (3B) in the longitudinal direction of the substrate (1). The second semiconductor light emitting element (3G) is arranged closer to one end of the substrate (1), whereas the third semiconductor light emitting element (3B) is arranged closer to the other end of the substrate (1).
US09899353B2	Off-chip vias in stacked chips A microelectronic assembly includes first and second stacked microelectronic elements, each having spaced apart traces extending along a front face and beyond at least a first edge thereof. An insulating region can contact the edges of each microelectronic element and at least portions of the traces of each microelectronic element extending beyond the respective first edges. The insulating region can define first and second side surfaces adjacent the first and second edges of the microelectronic elements. A plurality of spaced apart openings can extend along a side surface of the microelectronic assembly. Electrical conductors connected with respective traces can have portions disposed in respective openings and extending along the respective openings. The electrical conductors may extend to pads or solder balls overlying a face of one of the microelectronic elements.
US09899352B2	Data storage device and an electronic device including the same A data storage device may include a package substrate, and an upper semiconductor chip disposed above a top surface of the package substrate. At least one lower bump is disposed on a bottom surface of the package substrate. A lower semiconductor chip is disposed on the bottom surface of the package substrate and spaced apart from the at least one lower bump. The lower semiconductor chip is thinner than the at least one lower bump.
US09899350B2	Flip chip module with enhanced properties A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound residing on the top surface. A first mold compound is disposed on the top surface of the carrier. A first thinned flip chip die resides over a first portion of the first mold compound with interconnects extending through the first portion to the top surface wherein the first portion of the mold compound fills a region between the first flip chip die and the top surface. A second mold compound resides over the substrate and provides a first recess over the first flip chip die wherein the first recess extends to a first die surface of the first flip chip die. A third mold compound resides in the first recess and covers an exposed surface of the flip chip die.
US09899345B2	Electrode terminal, semiconductor device for electrical power, and method for manufacturing semiconductor device for electrical power An electrode terminal includes: a first drawn-out part to be bonded to a main electrode; and a second drawn-out part that is formed of a plate member in a continuous fashion from one end portion to be positioned opposite to the main electrode with a gap therebetween until another end portion to be connected to an external circuit, so that a portion in the first drawn-out part that is adjacent to a portion therein to be bonded to the main electrode, is bonded to an opposing surface to the main electrode in said one end portion; wherein the first drawn-out part is formed so that the portion to be bonded to the main electrode is away from the opposing surface; and wherein an opening portion corresponding to the main electrode is formed in the second drawn-out part.
US09899341B2	Antenna on integrated circuit package An antenna on integrated circuit (IC) package is disclosed. In an embodiment, an IC package comprises: a substrate; a radio frequency (RF) transceiver attached to the substrate; mold compound encapsulating the substrate; a shield layer formed on the mold compound; and one or more vias extending vertically through the shield layer and the mold compound, providing a conductive path to the RF transceiver. In another embodiment, a method comprises: attaching a radio frequency (RF) transceiver to a substrate; encapsulating the substrate with mold compound; forming a shield layer on the mold compound; and forming one or more vias through the shield layer and mold compound, providing a conductive path to the RF transceiver.
US09899340B2	Microelectronics package with inductive element and magnetically enhanced mold compound component The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for making the same. The disclosed microelectronics package includes a module substrate, a thinned flip-chip die with an upper surface that includes a first surface portion and a second surface portion surrounding the first surface portion, the magnetically enhanced mold compound component, and a mold compound component. The thinned flip-chip die is attached to the module substrate and includes a device layer with an inductive element embedded therein. Herein, the inductive element is underlying the first surface portion and not underlying the second surface portion. The magnetically enhanced mold compound component is formed over the first surface portion. The mold compound component is formed over the second surface portion, not over the first surface portion, and surrounding the magnetically enhanced mold compound component.
US09899339B2	Discrete device mounted on substrate A method of making an electronic device having a discrete device mounted on a surface of an electronic die with both the discrete device and the die connected by heat cured conductive ink and covered with cured encapsulant including placing the discrete device on the die; and keeping the temperature of each of the discrete device and the die below about 200° C. Also disclosed is a method of electrically attaching a discrete device to a substrate that includes placing the device on the substrate, applying conductive ink that connects at least one terminal on the device to at least one contact on the substrate and curing the conductive ink. Also disclosed is an IC package with a discrete electrical device having electrical terminals; an electrical substrate having contact pads on a surface thereof; and cured conductive ink connecting at least one of the electrical terminals with at least one of the contact pads.
US09899338B1	Structure and fabrication method for enhanced mechanical strength crack stop Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.
US09899337B2	Semiconductor package and manufacturing method thereof A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip. The encapsulation layer encapsulates the at least one chip. The stress controlling layer is disposed on a surface of the package member. The stress controlling layer has an internal stress to the extent that the stress controlling layer prevents the package member from having warpage.
US09899333B2	Method for forming crack-stopping structures A crack-stopping structure includes a semiconductor wafer comprising a plurality of dies defined by a plurality of scribe line regions, a plurality of metal patterns formed in the scribe line regions, and a plurality of groups of through silicon holes (TSHs) formed in the scribe line regions. The wafer further includes a front side and a back side, and the TSHs respectively include at least a bottom opening formed in the bottom side of the wafer. The groups of TSHs are formed between the metal patterns and the dies.
US09899329B2	Interconnection structures and methods for transfer-printed integrated circuit elements with improved interconnection alignment tolerance An electronic component array includes a backplane substrate, and a plurality of integrated circuit elements on the backplane substrate. Each of the integrated circuit elements includes a chiplet substrate having a connection pad and a conductor element on a surface thereof. The connection pad and the conductor element are electrically separated by an insulating layer that exposes at least a portion of the connection pad. At least one of the integrated circuit elements is misaligned on the backplane substrate relative to a desired position thereon. A plurality of conductive wires are provided on the backplane substrate including the integrated circuit elements thereon, and the connection pad of each of the integrated circuit elements is electrically connected to a respective one of the conductive wires notwithstanding the misalignment of the at least one of the integrated circuit elements. Related fabrication methods are also discussed.
US09899328B2	Power semiconductor module A power semiconductor module includes: a positive arm and a negative arm that are formed by series connection of self-arc-extinguishing type semiconductor elements, the positive arm and the negative arm being connected at a series connection point between the self-arc-extinguishing type semiconductor elements; a positive-side electrode, a negative-side electrode, and an AC electrode connected to the positive arm and the negative arm; and a substrate on which a plurality of wiring patterns are formed, the wiring patterns connecting the self-arc-extinguishing type semiconductor elements of the positive arm and the negative arm to the positive-side electrode, the negative-side electrode, and the AC electrode. Respective directions of current flowing in adjacent wiring patterns are identical to each other, and one of the adjacent wiring patterns is arranged in mirror symmetry with the other of the adjacent wiring patterns.
US09899324B1	Structure and method of conductive bus bar for resistive seed substrate plating A method includes providing a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, and forming a metallic structure on the semiconductor substrate to serve as a bus bar for the printed circuits and/or semiconductor devices. A semiconductor structure is realized with the method, the semiconductor structure including a semiconductor substrate having horizontal and vertical scribe lines thereon defining semiconductor areas for printed circuits and/or semiconductor devices, a metallic structure on the semiconductor substrate serving as a bus bar for the printed circuits and/or semiconductor devices, and printed circuits and/or semiconductor devices in the semiconductor areas.
US09899323B2	Integrated circuit device and method of manufacturing the same An integrated circuit device includes a first conductive line and a second conductive line that are spaced apart from each other and extend in a first direction to be parallel to each other; and a contact pad including a pad body including a first branch portion from which the first conductive line branches and a second branch portion from which the second conductive line branches and a loop branch portion that is located between the first branch portion and the second branch portion and protrudes from the pad body. Related devices and fabrication methods are also discussed.
US09899318B2	Method for providing electrical antifuse including phase change material An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further includes an antifuse material layer comprising a phase change material alloy of tantalum and nitrogen. A first surface of the antifuse material layer is present in direct contact with the first electrode. A second electrode is present in direct contact with a second surface of the antifuse material layer that is opposite the first surface of the antifuse material layer.
US09899316B2	Semiconductor device and a method of manufacturing the same For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.
US09899315B2	Wiring for semiconductor device and method of forming same A method for forming a wiring for a semiconductor device according to an aspect of the present invention includes: forming a predetermined pattern on a first surface of a silicon substrate by selectively etching the first surface; coating, with a metal layer, a selected area of the first surface, including an area whereat the predetermined pattern is formed; forming organic material in the first surface to fill an etched portion and cover the coated metal layer; forming a plurality of via holes in the organic material and connecting the metal wiring to the coated metal layer through the via holes; and grinding a second surface corresponding to the first surface to remove a part of the metal layer formed in the etched portion.
US09899310B2	Wiring substrate and method of manufacturing the same A wiring substrate includes an insulating layer, at least one via hole formed in the insulating layer, a first wiring layer formed on one surface of the insulating layer and having a droop portion at an end-side of the via hole, a second wiring layer formed on the other surface of the insulating layer, and a metal-plated layer formed in the via hole and configured to connect the second wiring layer and the droop portion of the first wiring layer. One surface of the insulating layer around the via hole is formed as a convex curved surface and the droop portion of the first wiring layer is arranged on the convex curved surface.
US09899309B2	Electronic package and semiconductor substrate A semiconductor substrate is provided, including a substrate body having a lateral surface, and a protruding structure extending outward from the lateral surface. The semiconductor substrate distributes stresses generated during a manufacturing process through the protruding structure, and is thus prevented from delamination or being cracked. An electronic package having the semiconductor substrate is also provided.
US09899308B2	Semiconductor package and method of fabricating the same A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor substrate, a plurality of conductive pads formed on end surfaces of the conductive vias and covering the buffer layer. During a reflow process, the buffer layer greatly reduces the thermal stress, thereby eliminating the occurrence of cracking at the interface of conductive pads. A method of fabricating such a semiconductor package is also provided.
US09899304B2	Wiring substrate and semiconductor device A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.
US09899301B2	Semiconductor device manufacturing method A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is connected with a semiconductor chip while jigs are pressed against a die pad. The jigs each have a first support portion with a first projection and a second support portion with a second projection. Using the jigs thus structured, the first projection is made to contact with a first point on the front surface of the die pad and then the second projection is made to contact with a second point on the front surface of the die pad located closer to a suspension lead than the first point.
US09899299B2	Semiconductor device A semiconductor part includes a resin package and an exposed portion exposed from a bottom surface of the resin package. The exposed portion has a first diagonal line perpendicular to both first and third sides of the package as viewed from the bottom surface. The exposed portion also has a second diagonal line perpendicular to both the second fourth side in the bottom view. A first lead terminal portion opposes the exposed portion and has a first shape in the bottom view. A second lead terminal portion, also opposing the exposed portion, has a second shape in the bottom view. A third lead terminal portion opposing the exposed portion, also has the second shape in the bottom view. A fourth lead terminal portion, similarly opposed to the exposed portion, likewise has the second shape in the bottom view.
US09899298B2	Microelectronic packages having mold-embedded traces and methods for the production thereof Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.
US09899296B2	Method of forming conductive bumps for cooling device connection A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate includes depositing a first-side UBM layer on a first surface of the substrate, and forming a plurality of first-side metal bumps on the first surface of the substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the substrate, and the first surface and the second surface are opposite of each other. The method includes forming a plurality of second-side metal bumps on the second surface of the substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.
US09899295B2	Method of manufacture for a semiconductor device A method of manufacture for a semiconductor device is disclosed. The method includes providing a semiconductor stack structure that includes a device terminal of a semiconductor device, and having a first surface and a buried oxide (BOX) layer attached to a wafer handle. Another step includes disposing a polymeric layer that includes a polymer and an admixture that increases thermal conductivity of the polymer onto the first surface of the semiconductor stack structure. Another step involves removing the wafer handle from the BOX layer to expose a second surface of the semiconductor stack structure, and yet another step involves removing a portion of the semiconductor stack structure to expose the device terminal.
US09899294B2	Thermal interface material layer and package-on-package device including the same Provided are a thermal interface material layer and a package-on-package device including the same. The package-on-package device may include a thermal interface material layer interposed between lower and upper semiconductor packages and configured to have a specific physical property. Accordingly, it is possible to prevent a crack from occurring in a lower semiconductor chip, when a solder ball joint process is performed to mount the upper semiconductor package on the lower semiconductor package.
US09899293B2	Semiconductor device packages with improved thermal management and related methods Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate. A heat sink may be located on a side of the uppermost semiconductor die opposite the substrate. A passivation material may be located between the uppermost semiconductor die and the heat sink.
US09899288B2	Interconnect structures for wafer level package and methods of forming same A device package is provided. The device package includes a first die and a second die. A top surface of the first die is offset from a top surface of the second die in a direction that is parallel to a sidewall of the first die. A molding compound extends along sidewalls of the first die and the second die, where at least a portion of a top surface of the molding compound includes an inclined surface. A polymer layer contacts the top surface of the molding compound, the top surface of the first die, and the top surface of the second die. A top surface of the polymer layer is substantially level. A first conductive feature is in the polymer layer, where the first conductive feature is electrically connected to the first die.
US09899287B2	Fan-out wafer level package structure A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding compound encapsulates the chip. The at least one circuit layer is disposed on a surface of the chip and a surface of the molding compound coplanar to the surface of the chip. The at least one circuit layer includes a plurality of traces. Each of the traces includes a first portion and a second portion. The first portion is located at an edge region of a projection of the chip onto the dielectric layer. A width of the first portion is larger than a width of the second portion. The at least one dielectric layer is disposed at a side of the at least one circuit layer.
US09899286B2	Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask A semiconductor device has a semiconductor die with a die bump pad. A substrate has a conductive trace with an interconnect site. A conductive bump material is deposited on the interconnect site or die bump pad. The semiconductor die is mounted over the substrate so that the bump material is disposed between the die bump pad and interconnect site. The bump material is reflowed without a solder mask around the die bump pad or interconnect site to form an interconnect structure between the die and substrate. The bump material is self-confined within the die bump pad or interconnect site. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material substantially within a footprint of the die bump pad and interconnect site. The interconnect structure can have a fusible portion and non-fusible portion.
US09899283B2	Power module with low stray inductance A power module providing a half bridge comprises at least one substrate and an inner metallization area, two intermediate metallization areas and two outer metallization areas, each of which extends in a longitudinal direction of the at least one substrate; wherein the two intermediate metallization areas are arranged besides the inner metallization area with respect to a cross direction of the at least one substrate and each outer metallization area is arranged beside one of the two intermediate metallization areas with respect to the cross direction; wherein the power module comprises two inner sets of semiconductor switches, each inner set of semiconductor switches bonded to an intermediate metallization area and electrically connected to the inner metallization area, such that the inner sets of semiconductor switches form a first arm of the half bridge; wherein the power module comprises two outer sets of semiconductor switches, each outer set of semiconductor switches bonded to an outer metallization area and electrically connected to an intermediate metallization area, such that the outer sets of semiconductor switches form a second arm of the half bridge.
US09899280B2	Method of forming a temporary test structure for device fabrication A method of forming a temporary test structure for device fabrication is provided. The method allows for electrically testing conductive interconnects during controlled collapse chip connections (C4) fabrication and/or through-silicon vias (TSVs) during interposer fabrication. The method includes providing a substrate containing a plurality of electrically conductive interconnects extending vertically to top surface of the substrate. A temporary test structure is formed to connect the plurality of interconnects for electrical testing. Electrical testing is performed on the substrate by probing at different test locations on the temporary test structure. All or part of the temporary test structure is removed so as not to affect product performance. The temporary test structure can contain electrical test pads which provide a way to make temporary connections to small interconnect landings or features at extreme tight pitch to fan them out to testable pads sizes and pitches.
US09899278B2	Semiconductor manufacturing apparatus and semiconductor manufacturing method In one embodiment, a semiconductor manufacturing apparatus includes an extraction module configured to extract, in cycle etching that repeats first processes of etching a workpiece layer and second processes of performing different processing from the first processes for plural cycles, light emission intensities in the first processes for individual cycles. The apparatus further includes a detection module configured to detect an etching end point of the workpiece layer in the cycle etching, based on the light emission intensities of the plural cycles.
US09899271B2	Structure and formation method of semiconductor device structure Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element
US09899262B2	Wafer processing method A wafer formed from an SiC substrate having a first surface and a second surface is divided into individual device chips. A division start point formed by a laser has a depth corresponding to the finished thickness of each device chip along each division line formed on the first surface. The focal point of the laser beam is set inside the SiC substrate at a predetermined depth from the second surface, and the laser beam is applied to the second surface while relatively moving the focal point and the SiC substrate to thereby form a modified layer parallel to the first surface and cracks extending from the modified layer along a c-plane, thus forming a separation start point. An external force is applied to the wafer, thereby separating the wafer into a first wafer having the first surface and a second wafer having the second surface.
US09899261B2	Semiconductor package structure and method for forming the same A semiconductor package structure having a substrate, wherein the substrate has a front side and a back side, a through silicon via (TSV) interconnect structure formed in the substrate, and a first guard ring doped region and a second guard ring doped region formed in the substrate. The second guard ring doped region is disposed between the first guard ring doped region and the TSV interconnect structure.
US09899259B2	Gate tie-down enablement with inner spacer A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.
US09899256B2	Self-aligned airgaps with conductive lines and vias A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.
US09899255B2	Via blocking layer Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.
US09899253B2	Fabrication of silicon germanium-on-insulator finFET A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.
US09899249B2	Fabrication method of coreless packaging substrate A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.
US09899248B2	Method of forming semiconductor packages having through package vias A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer and protrude from the patterned layer to expose tapered sidewalls.
US09899246B2	Gas distributor used in wafer carriers The present invention relates to gas distributors used in wafer carriers. The gas distributors comprise a body having an interior space, a separator configured at the front side of the body in the interior space, and an air inlet connected with the body. One edge of the separator and the front side of the body together form a passage. The configuration of the passage in the gas distributors enables the gas distributors to evenly distribute gases.
US09899241B2	Plasma processing method A plasma processing method which performs plasma processing on a sample by a plurality of steps includes a first step of stopping supply of gas of one step while supplying an inert gas and a second step stopping the supply of the inert gas of the first step while as supplying a gas of the other step after the first step. An amount of the gas of the one step remaining inside a process chamber in which the sample is plasma-processed is detected in the first step. An amount of the gas of the other step reached inside the process chamber is detected in the second step. The one step is switched to the other step based on the amount of the gas of the one step detected in the first step and the amount of the gas of the other step detected in the second step.
US09899240B2	Substrate treatment apparatus A substrate treatment apparatus is provided, which includes: a seal chamber including a chamber body having an opening, a lid member provided rotatably with respect to the chamber body and configured to close the opening, and a first liquid seal structure which liquid-seals between the lid member and the chamber body, the seal chamber having an internal space sealed from outside; a lid member rotating unit which rotates the lid member; a substrate holding/rotating unit which holds and rotates a substrate in the internal space of the seal chamber; and a treatment liquid supplying unit which supplies a treatment liquid to the substrate rotated by the substrate holding/rotating unit.
US09899235B2	Fabrication method of packaging substrate A packaging substrate is disclosed, which includes: a dielectric layer; a circuit layer embedded in and exposed from a surface of the dielectric layer, wherein the circuit layer has a plurality of conductive pads; and a plurality of conductive bumps formed on the conductive pads and protruding above the surface of the dielectric layer. As such, when an electronic element is disposed on the conductive pads through a plurality of conductive elements, the conductive elements can come into contact with both top and side surfaces of the conductive bumps so as to increase the contact area between the conductive elements and the conductive pads, thereby strengthening the bonding between the conductive elements and the conductive pads and preventing delamination of the conductive elements from the conductive pads.
US09899230B2	Apparatus for advanced packaging applications The embodiments disclosed herein pertain to novel methods and apparatus for removing material from a substrate. In certain embodiments, the method and apparatus are used to remove negative photoresist, though the disclosed techniques may be implemented to remove a variety of materials. In practicing the disclosed embodiments, a stripping solution may be introduced from an inlet to an internal manifold, sometimes referred to as a cross flow manifold. The solution flows laterally through a relatively narrow cavity between the substrate and the base plate. Fluid exits the narrow cavity at an outlet, which is positioned on the other side of the substrate, opposite the inlet and internal manifold. The substrate spins while in contact with the stripping solution to achieve a more uniform flow over the face of the substrate. In some embodiments, the base plate includes protuberances which operate to increase the flow rate (and thereby increase the local Re) near the face of the substrate.
US09899228B2	Showerhead electrode assemblies for plasma processing apparatuses Showerhead electrode assemblies are disclosed, which include a showerhead electrode adapted to be mounted in an interior of a vacuum chamber; an optional backing plate attached to the showerhead electrode; a thermal control plate attached to the backing plate or to the showerhead electrode at multiple contact regions across the backing plate; and at least one interface member separating the backing plate and the thermal control plate, or the thermal control plate and showerhead electrode, at the contact regions, the interface member having a thermally and electrically conductive gasket portion and a particle mitigating seal portion. Methods of processing semiconductor substrates using the showerhead electrode assemblies are also disclosed.
US09899227B2	System, method and apparatus for ion milling in a plasma etch chamber A system and method of ion milling performed in a plasma etch system including a plasma etch chamber, multiple process gas sources coupled to the plasma etch chamber, a radio frequency bias source and a controller. The plasma etch chamber including a substrate support. The substrate support being a non-pivoting and non-rotating substrate support. The substrate support capable of supporting a substrate to be processed on a top surface of the substrate support without use of a mechanical clamp device. The plasma etch chamber also including an upper electrode disposed opposite from the top surface of the substrate support. The radio frequency bias source is coupled to the substrate support. The controller is coupled to the plasma etch chamber, the multiple process gas sources and the radio frequency bias source. The controller including logic stored on computer readable media for performing an ion milling process in the plasma etch chamber.
US09899226B2	Semiconductor device and fabrication method thereof Provided herein is a semiconductor device including a substrate; an active layer formed on top of the substrate; a protective layer formed on top of the active layer and having a first aperture; a source electrode, driving gate electrode and drain electrode formed on top of the protective layer; and a first additional gate electrode formed on top of the first aperture, wherein an electric field is applied to the active layer, protective layer and driving gate electrode due to a voltage applied to each of the source electrode, drain electrode and driving gate electrode, and the first additional gate electrode is configured to attenuate a size of the electric field applied to at least a portion of the active layer, protective layer and driving gate electrode.
US09899220B2	Method for patterning a substrate involving directed self-assembly A method for patterning a substrate is disclosed. The method includes applying a first directed self-assembly (DSA) patterning process that defines a first patterned layer on top of the substrate. The pattern of the first patterned layer is to be transferred into the substrate. The method also includes applying a planarizing layer on top of the first patterned layer. The method further includes applying a second DSA patterning process that defines a second patterned layer on top of the planarizing layer, thereby not patterning the planarizing layer. A pattern of the second patterned layer is to be transferred into the substrate. Projections of the pattern of the second patterned layer and the pattern of the first patterned layer on the substrate have no overlap. Additionally, the method includes transferring the patterns defined by the first patterned layer and the second patterned layer into the substrate.
US09899216B2	Semiconductor device manufacturing method The present invention provides a semiconductor device manufacturing method for lowering the technical difficulties of a process forming a horizontal single crystal nanowire and a manufacturing cost, the semiconductor device manufacturing method comprising the steps of: preparing a substrate including a first area and a second area; determining a position at which a nanowire is to be formed on the substrate of the first area and arranging an empty space in which the nanowire is to be filled; exposing a substrate surface of a part adjacent to the first area; causing selective single crystal growth from the exposed substrate surface; and forming a nanowire by a self-aligned method through an etching process within the first area, and removing, from outside the first area, a single crystal growth layer of the remaining areas excluding a part necessary for the wiring of the second area.
US09899214B1	Method for fabricating a vertical heterojunction of metal chalcogenides The present disclosure provides a method for fabricating a vertical heterojunction of metal chalcogenides. The method includes steps of providing a multi-layer material, performing an ion implantation and performing an annealing. The multi-layer material has a carrier and a metal layer, in which the metal layer covers the carrier to form an interface. The carrier includes an oxide of a first metal element, and the metal layer includes a second metal element. The step of performing the ion implantation is to inject a chalcogen ion source into the multi-layer material to allow a plurality of chalcogen ions to be implanted in a depth area of the multi-layer material, and the depth area includes the interface. The step of performing the annealing is to form a first metal chalcogenide and a second metal chalcogenide at two sides of the interface, respectively.
US09899210B2	Chemical vapor deposition apparatus and method for manufacturing semiconductor device using the same A method for manufacturing a semiconductor device includes forming a transistor on a substrate. Precursor gases are provided from a showerhead of a chemical vapor deposition (CVD) apparatus to form a contact etch stop layer (CESL) to cover the transistor and the substrate. A temperature of the showerhead is controlled in a range of about 70° C. to about 100° C. to control a temperature of the precursor gases.
US09899209B2	Electrically conductive thin films An electrically conductive thin film including a plurality of nanosheets including a doped titanium oxide represented by Chemical Formula 1 and having a layered crystal structure: (AαTi1−α)O2+δ Chemical Formula 1 wherein, in Chemical Formula 1, δ is greater than 0, A is at least one dopant metal selected from Nb, Ta, V, W, Cr, and Mo, and α is greater than 0 and less than 1. Also, an electronic device including the electrically conductive thin film.
US09899206B2	Method of producing a halogen lamp and halogen lamp The present invention relates to a method for producing a halogen lamp, including the following steps: providing a glass tube blanket; dip-coating of the glass tube blanket using a sol gel process having an inorganic coating; forming a lamp bulb from the coated glass tube blanket. The present invention relates further to a halogen lamp produced accordingly.
US09899205B2	System and method for inhibiting VUV radiative emission of a laser-sustained plasma source A system for forming a laser-sustained plasma includes a gas containment element, an illumination source configured to generate pump illumination, and a collector element configured to focus the pump illumination from the pumping source into the volume of the gas mixture in order to generate a plasma within the volume of the gas mixture that emits broadband radiation. The gas containment element may be configured to contain a volume of a gas mixture including a first gas component and a second gas component. The second gas component suppresses at least one of a portion of the broadband radiation associated with the first gas component or radiation by one or more excimers associated with the first gas component from a spectrum of radiation exiting the gas mixture.
US09899204B2	Mass spectrometry analysis of biomolecules by multiple charge state selection using a concurrent precursor isolation technique A method is described for the analysis of biological polymers, for example, intact proteins or oligonucleotides, by mass spectrometry. This method produces sample ions from a sample containing biological polymers, and ion species are selected that correspond to different charge states of a biological polymer molecule. The ion species are concurrently isolated from the sample ions to generate precursor ions in an ion trap mass spectrometer or in a quadrupole mass filter mass spectrometer. Precursor ions or product ions derived from the precursor ions may then be mass analyzed. The mass analysis step may include fragmenting the precursor ions to form product ions.
US09899199B2	Mass spectrometer comprising a radio frequency ion guide having continuous electrodes The invention relates to a mass spectrometer, comprising an ion guide having a plurality of electrodes that are supplied with a radio frequency voltage to facilitate radial confinement of ions in an internal volume defined by inward facing surfaces of the electrodes, the internal volume including a first section having a variable radial diameter along a longitudinal axis of the ion guide, in which the electrodes are helically wound, and an adjacent second section having a substantially constant radial diameter along the longitudinal axis, wherein the electrodes extend from the first section to the second section continuously. The continuous nature of the ion guide electrodes facilitates in particular unhindered axial propagation of ions through the assembly and prevents ion losses during their transmission through different compartments of the mass spectrometer.
US09899195B2	Systems and methods for removing particles from a substrate processing chamber using RF plasma cycling and purging Systems and methods for operating a substrate processing system include processing a substrate arranged on a substrate support in a processing chamber. At least one of precursor gas and/or reactive gas is supplied during the processing. The substrate is removed from the processing chamber. Carrier gas and purge gas are selectively supplied to the processing chamber. RF plasma is generated in the processing chamber during N cycles, where N is an integer greater than one. The RF plasma is on for a first period and off for a second period during each of the N cycles. The purge gas is supplied during at least part of each of the N cycles.
US09899189B2	Ion implanter A technique disclosed in the present specification relates to an ion implanter capable of preventing a semiconductor substrate from being damaged by an abnormal electric discharge through a simple method. The ion implanter of this technique includes an ion irradiation unit configured to irradiate a surface of a semiconductor substrate with ions. The ion implanter also includes at least one electrode (needle electrode, annular electrode) disposed in a position in the vicinity of at least one of back and side surfaces of an end of the semiconductor substrate. The position is dischargeable to and from the semiconductor substrate. The at least one electrode (needle electrode, annular electrode) is spaced apart from the semiconductor substrate.
US09899188B2	Selective processing of a workpiece using ion beam implantation and workpiece rotation Systems and methods for the selective processing of a particular portion of a workpiece are disclosed. For example, the outer portion may be processed by directing an ion beam toward a first position on the workpiece, where the ion beam extends beyond the outer edge of the workpiece at two first locations. The workpiece is then rotated relative to the ion beam about its center so that certain regions of the outer portion are exposed to the ion beam. The workpiece is then moved relative to the ion beam to a second position and rotated in the opposite direction so that all regions of the outer portion are exposed to the ion beam. This process may be repeated a plurality of times. The ion beam may perform any process, such as ion implantation, etching or deposition.
US09899187B2	Charged particle beam writing apparatus and charged particle beam writing method A charged particle beam writing apparatus includes a processing circuitry configured to calculate a third proximity effect correction irradiation coefficient where at least one correction irradiation coefficient term up to k-th order term, in correction irradiation coefficient terms of from a first order term to a n-th order term for a first proximity effect correction irradiation coefficient which does not take account of a predetermined effect, are replaced by at least one correction irradiation coefficient term up to the k-th order term, for a second proximity effect correction irradiation coefficient which takes account of the predetermined effect; and a processing circuitry configured to calculate a dose by using the third proximity effect correction irradiation coefficient.
US09899186B1	Charged-particle beam microscope with an evaporator A charged-particle beam microscope is provided for imaging a sample. The microscope has a vacuum chamber to maintain a low-pressure environment. A stage is provided to hold a sample in the vacuum chamber. The microscope has a compact evaporator in the vacuum chamber to evaporate and deposit a coating onto a surface of the sample. The microscope also has a charged-particle beam column is provided to direct a charged-particle beam onto the coating on the surface of the sample. The charged-particle beam column includes a charged-particle beam source to generate a charged-particle beam and charged-particle beam optics to converge the charged-particle beam onto the sample. A detector is provided to detect charged-particle radiation emanating from the coating on the surface of the sample to generate an image. A controller analyzes the detected charged-particle radiation to generate an image of the sample.
US09899183B1	Structure and method to measure focus-dependent pattern shift in integrated circuit imaging Various embodiments include measurement structures and methods for measuring integrated circuit (IC) images. In some cases, a measurement structure for use in measuring an image of an IC, includes: a first section having a positive shift spacing pattern; a second section, on an opposite side of the measurement structure, having a negative shift spacing pattern; and a third section having a reference spacing pattern for calibrating a measurement from at least one of the first section or the second section.
US09899178B2	Electronic control device including interrupt wire An electronic control device includes one or more substrates, a casing, a plurality of circuit blocks, a common wire, a plurality of branch wires and two interrupt wires. The circuit blocks are disposed on the substrates and the substrates are disposed in the casing. The common wire is shared by the circuit blocks. The branch wires are respectively coupled between the circuit blocks and the common wire. The two interrupt wires are respectively coupled with two of the common wire and the branch wires for overcurrent protection of the circuit blocks.
US09899177B2	Delay time generation apparatus for air circuit breaker A delay time generation apparatus for an air circuit breaker according to the present invention can provide an effect of ensuring a delay time as long as possible even in a narrow space upon outputting a signal related to a conductive state, by virtue of interaction of a main shaft, a pin portion, a first rotating unit, a second rotating unit and a spring member.
US09899173B2	Swtiching phase offset for contactor optimization A system and methods providing for minimizing the arc energy delivered to the pads of a plurality of contactors using a single control coil based on monitoring the electrical sine waves of the three alternating current electrical poles and calculating the instant to energize or deenergize a single control coil. The remainder of the contactors will make or break based on an offset in time from the making or breaking of the control contactor.
US09899165B2	Safety test switch An interface test device for testing a circuit, the interface test device including a module configured to open and close a medium to high voltage monitoring circuit, the module having at least one pair of contacts biased towards each other that are electrically connected and in line with the medium to high voltage monitoring circuit; at least one pair of insulated jacks, wherein the at least one pair of insulated jacks is connected to the medium to high voltage monitoring circuit before or substantially simultaneously with the medium to high voltage monitoring circuit being opened; at least one disconnect plug that is insertable into the module through at least one parking opening into at least one parking position and insertable into the module through at least one disconnect opening into at least one disconnect position.
US09899163B2	Switch unit and game machine A switch unit has a display part configured to display an image, and an operation part provided on the display part in a stacked manner. The operation part includes a button made of a transparent material except for an edge, a transparent button case having an opening formed in a position corresponding to a display region of the display part and configured to position the button, and a transparent substrate provided below the button case and having an electronic component disposed in a position corresponding to the edge of the button. The button is disposed on the transparent substrate via the opening in the button case. A discharge gap in parallel with the electronic component is provided on a wire in a position corresponding to the edge of the button on the transparent substrate.
US09899154B2	Dense energy ultra-capacitor preform, thin film, module and fabrication methods therefor A Dense Energy Ultracapacitor DEUC preform, thin film, and module and methods of fabrication therefor, are provided. The DEUC thin film includes: a multilayer polymer thin film (2210) including a plurality of matched polymer layers (2215) having DEUC structural features resulting from drawing, by a draw process, and/or stretching, of a multilayer polymer DEUC preform (2201) having size, shape, and an arrangement of matched polymer layers (2205), where the multilayer polymer thin film (2210) having DEUC structural features in at least one dimension proportionally reduced in comparison to the same features in the Preform (2201). The multilayer polymer thin film includes negative and positive electrodes (903) made from conducting polymer and spaced apart by suspended particle high dielectric energy storage media (904) including high dielectric nano and/or micro sized particles (901, 902) suspended in a binder (904) including at least one of a polymer, a copolymer, and a terpolymer. All the layers (903, 904) are bound and unified together.
US09899149B2	Electronic component and method of manufacturing the same An electronic component includes a magnetic body having first and second end surfaces opposing each other and first and second side surfaces connected to the first and second end surfaces, and first and second internal coil patterns disposed in the magnetic body and including coil pattern portions having a spiral shape and lead portions connected to ends of the coil pattern portions and exposed to one surfaces of the magnetic body, respectively. The coil pattern portions are exposed to the first and second side surfaces, and first and second side parts are disposed on the first and second side surfaces. A manufacturing method therefore is presented.
US09899148B2	Manufacturing device for field pole magnet body and manufacturing method for same A device for manufacturing a field pole magnet body includes a reference jig having reference surfaces in a lengthwise direction, a width direction, and a thickness direction for positioning the plurality of cleaved and divided magnet fragments; a lengthwise direction pressing means that presses the magnet fragments from the lengthwise direction to the lengthwise direction reference surface; a width direction pressing means that presses them from the width direction to the width direction reference surface; and a thickness pressing means that presses them from the thickness direction to the thickness direction reference surface. The lengthwise direction pressing means is operated to press the magnet fragments in a state in which a pressing force of at least one of the width direction pressing means and the thickness direction pressing means is suppressed to be weaker than a pressing force generated by the lengthwise direction pressing means or is released.
US09899147B2	Transmission coil module for wireless power transmitter Embodiments provide a wireless power transfer technology, and more particularly, provide a method of mounting a transmission coil, which wirelessly transmits power, in a wireless power transmitter. The transmission coil module includes a transmission coil for wirelessly transmitting power, a coil frame including a receptacle for insertion of the transmission coil, a support unit for surrounding the receptacle, and a central fixing plate formed inside the receptacle and corresponding to an inner shape of the transmission coil, and a connector for electrically connecting the transmission coil to a control circuit board, and the support unit and the central fixing plate are integrally formed with each other.
US09899144B2	Resonant high current density transformer A resonant high current density transformer including two cores that are abut against each other with their first and second side posts on two sides thereof. A first bobbin envelops the first side posts on the same side of the two cores. A side plate is provided on either end of the first bobbin. The space between the two side plates is divided into two coil slots with a spacer, and at least a wire is wound in each coil slot to form a primary winding. A further second bobbin envelops the second side posts on the same side of the two cores. The outer periphery of the second bobbin is divided into two winding regions by another spacer, and a metal plate envelops each of the winding regions to form a secondary winding. A bobbin mount is disposed at the external flank of the second bobbin with a barrier plate at a side thereof for separating the first and the second bobbins. An insulating separating cover is provided on a side of the first bobbin closer to the bobbin mount, and the two ends of the separating cover cover the top and bottom sides of the first bobbin, respectively.
US09899143B2	Chip electronic component and manufacturing method thereof The present application provides a chip electronic component and a manufacturing method thereof. More particularly, there is provided a chip electronic component including a thin insulating film having a reduced width and extended up to a lower portion of a coil pattern without exposing the coil pattern such that the coil pattern has no direct contact with a magnetic material, thereby preventing a poor waveform at high frequency and increasing inductance.
US09899142B2	Method and device for insulation of high-voltage generator tank The present disclosure relates to a tank of a high-voltage generator including a tank body and a tank lid. There is an opening in the tank lid. The opening is connected to the bellows so as to counteract the volume change of the transformer oil and avoid generation of bubbles. The tank includes a positive transformer, a negative transformer, a bellows, and other components. The high-voltage winding is embedded in the PCBs. The outer insulating bushing is covered by the PCBs so as to improve the insulativity between the turns of the high-voltage winding. In addition, oil barriers may be placed between the positive and the negative transformers, or between the transformers and the ground so as to eliminate the bridge breakdown effect and make the electric field uniform. By means of said measures, the present disclosure improves the stability of the high-voltage generator.
US09899139B2	Magnetic component The present invention discloses a magnetic component and which includes a bobbin, a magnetic core assembly, a first winding, and a second winding. The bobbin has a main body, a channel, and a pin holder. The main body has a primary winding section and a secondary winding section. The channel penetrates the main body. The pin holder is extended from a side of the main body. The magnetic core assembly is partially disposed in the channel of the bobbin. The first winding and the second winding respectively have two outlet terminals. The first winding is wound around the primary winding section. The second winding is wound around the secondary winding section. Two outlet terminals of the first winding and two outlet terminals of the second winding are configured in the pin holder.
US09899129B2	Tubular electric cable fittings with strain relief A tubular cable fitting which is capable of providing strain relief for Tubular Electric Cables (“TEC”) and is designed to protect end fittings from loss of circuit continuity. The TEC end fittings may be of fiber optic or electric type service.
US09899128B1	Signal transmission cable assembly with ungrounded sheath containing electrically conductive particles A data transmission cable assembly includes an elongate first conductor, an elongate second conductor, and a sheath at least partially axially surrounding the first and second conductors. The sheath contains a plurality of electrically conductive particles interspersed within a matrix formed of an electrically insulative polymeric material. The conductive particles may be formed of a metallic material or and inherently conductive polymer material. The plurality conductive particles may be filaments that form a plurality of electrically interconnected networks. Each network is electrically isolated from every other network. Each network contains less than 125 filaments and/or has a length less than 13 millimeters. The bulk conductivity of the sheath is substantially equal to the conductivity of the electrically insulative polymeric material. The data transmission cable assembly does not include a terminal that is configured to connect the sheath to an electrical ground.
US09899120B2	Graphene oxide-coated graphitic foil and processes for producing same A graphene oxide-coated graphitic foil, composed of a graphitic substrate or core layer having two opposed primary surfaces and at least a graphene oxide coating layer deposited on at least one of the two primary surfaces, wherein the graphitic substrate layer has a thickness preferably from 0.34 nm to 1 mm, and the graphene oxide coating layer has a thickness preferably from 0.5 nm to 1 mm and an oxygen content of 0.01%-40% by weight based on the total graphene oxide weight. The graphitic substrate layer may be preferably selected from flexible graphite foil, graphene film, graphene paper, graphite particle paper, carbon-carbon composite film, carbon nano-fiber paper, or carbon nano-tube paper. This graphene oxide-coated laminate exhibits a combination of exceptional thermal conductivity, electrical conductivity, mechanical strength, surface smoothness, surface hardness, and scratch resistance unmatched by any thin-film material of comparable thickness range.
US09899119B2	Electric wire apparatus An electric wire apparatus includes an electric wire including an aluminum alloy wire rod having an outer periphery portion coated, and a crimp terminal crimped to an end portion of the electric wire, the crimp terminal having a barrel portion crimped with the aluminum alloy wire rod, the barrel portion having a one-end closed tubular shape. The aluminum alloy wire rod has a composition including 0.10 mass % to 1.00 mass % of magnesium (Mg), 0.10 mass % to 1.00 mass % of silicon (Si), 0.01 mass % to 2.50 mass % of iron (Fe), 0.000 mass % to 0.100 mass % of titanium (Ti), 0.000 mass % to 0.030 mass % of boron (B), 0.00 mass % to 1.00 mass % of copper (Cu), 0.00 mass % to 0.50 mass % of silver (Ag), 0.00 mass % to 0.50 mass % of gold (Au), 0.00 mass % to 1.00 mass % of manganese (Mn), 0.00 mass % to 1.00 mass % of chromium (Cr), 0.00 mass % to 0.50 mass % of zirconium (Zr), 0.00 mass % to 0.50 mass % of hafnium (Hf), 0.00 mass % to 0.50 mass % of vanadium (V), 0.00 mass % to 0.50 mass % of scandium (Sc), 0.00 mass % to 0.50 mass % of cobalt (Co), 0.00 mass % to 0.50 mass % of nickel (Ni), and the balance including aluminum and inevitable impurities.
US09899118B2	Aluminum alloy wire rod, alluminum alloy stranded wire, coated wire, wire harness, method of manufacturing aluminum alloy wire rod, and method of measuring aluminum alloy wire rod An aluminum alloy wire rod has a composition including Mg: 0.10-1.0 mass %, Si: 0.10-1.20 mass %, Fe: 0.01-1.40 mass %, Ti: 0.000-0.100 mass %, B: 0.000-0.030 mass %, Cu: 0.00-1.00 mass %, Ag: 0.00-0.50 mass %, Au: 0.00-0.50 mass %, Mn: 0.00-1.00 mass %, Cr: 0.00-1.00 mass %, Zr: 0.00-0.50 mass %, Hf: 0.00-0.50 mass %, V: 0.00-0.50 mass %, Sc: 0.00-0.50 mass %, Co: 0.00-0.50 mass %, Ni: 0.00-0.50 mass %, and the balance: Al and incidental impurities, Mg/Si mass ratio being 0.4 to 0.8. The aluminum alloy wire rod has a tensile strength of greater than or equal to 200 MPa, an elongation of greater than or equal to 13%, a conductivity of 47% IACS, and a ratio (YS/TS) of 0.2% yield strength (YS) to the tensile strength (TS) of less than or equal to 0.7.
US09899117B2	Metallic nanomesh A transparent flexible nanomesh having at least one conductive element and sheet resistance less than 300Ω/□ when stretched to a strain of 200% in at least one direction. The nanomesh is formed by depositing a sacrificial film, depositing, etching, and oxidizing a first metal layer on the film, etching the sacrificial film, depositing a second metal layer, and removing the first metal layer to form a nanomesh on the substrate.
US09899116B2	Silver nanowire conductive film and method of fabricating the same Provided are a silver nanowire conductive film coated with an oxidation protection layer and a method for fabricating the same. A silver nanowire conductive film coated with an oxidation protection layer includes: a substrate; silver nanowires disposed on the substrate; and an oxidation protection layer coated on the silver nanowires, wherein the oxidation protection layer comprises an oxide.
US09899113B2	Production method of scintillator dual array A method for producing a scintillator dual array comprising the steps of bonding first and second scintillator bar arrays having different sensitivity distributions of X-ray energy detection and pluralities of parallel grooves with equal gaps, via an intermediate resin layer, such that both scintillator bars are aligned in a lamination direction, cutting the integrally bonded bar array in a direction crossing the scintillator bars, and coating one cut surface of each bonded bar array piece with a resin.
US09899112B2	Particle beam therapy system, ridge filter, and method of making ridge filter A structure configuring a ridge filter has line symmetry about a line vertical to a depth direction passing the center of the structure. A small structure obtained in such a way that the structure is divided by this line has a bilaterally asymmetric shape about a center line in an iterative direction, and has a point symmetric shape about an intersection between the center line in the iterative direction and the center line in the depth direction. Thicknesses in the iterative direction of an uppermost stream surface and a lowermost stream surface in the depth direction are equal to each other. The structure is configured so that a thick portion in the iterative direction of the uppermost stream surface and the lowermost stream surface is not present in the depth direction.
US09899107B2	Rod assembly for nuclear reactors One embodiment provides a multi-segment rod that includes a plurality of rod segments. The rod segments are removably mated to each other via mating structures in an axial direction. An irradiation target is disposed within at least one of the rod segments, and at least a portion of at least one mating structure includes one and/or more combinations of neutron absorbing materials.
US09899103B2	Area efficient parallel test data path for embedded memories A built-in self-test (BIST) parallel memory test architecture for an integrated circuit, such as a system-on-a-chip (SoC), is disclosed. A BIST controller generates a test data pattern for memories of a common memory type, with this test data pattern forwarded to the memories, with pipeline delay stages inserted in the data path according to the operational speed of the memory in its normal operation. The expected data response of these memories, when read, and corresponding to this test data pattern is delayed for a group of memories by a local delay response generator shared by those memories. For example, the memories in the group of memories may be physically near one another. The local delay response generator delays the expected data response by a delay corresponding to the memory latency of those memories in the group, before applying the expected data response to local comparators associated with the memories in the group.
US09899100B2	One time programmable (OTP) cell and an OTP memory array using the same An anti-fuse device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and a salicide layer formed on a first portion of the gate electrode such that a second portion of the gate electrode omits the salicide layer, wherein a hard breakdown of at least a portion of the gate insulating film at a time of programming the anti-fuse device.
US09899098B1	Semiconductor memory device and memory system A semiconductor memory device includes a first word line and a second word line that are adjacent to each other, a first voltage boosting circuit configured to generate a first voltage based on a clock signal, a second voltage boosting circuit configured to generate a second voltage lower than the first voltage based on the clock signal, a counter, and a determination circuit. The counter counts a first number of clock cycles of the clock signal during a first period in which the first voltage boosting circuit generates the first voltage and applies the first voltage to the first word line while the second voltage boosting circuit generates the second voltage and applies the second voltage to the second word line, and a second number of clock cycles of the clock signal during a second period in which the first voltage boosting circuit generates the first voltage while the first word line is electrically disconnected from the first voltage boosting circuit. The determination circuit compares the first number of clock cycles and the second number of clock cycles to determine whether or not a leakage exists in the word lines.
US09899094B2	Nonvolatile memory device for supporting fast checking function and operating method of data storage device including the same A nonvolatile memory device includes a memory block including a plurality of memory cells which are coupled to a plurality of word lines; and a control unit configured to perform a read operation in response to a read command for target memory cells which are coupled to a target word line, wherein the control unit performs the read operation by applying a read bias voltage to the target word line, applying a first pass bias to a monitoring word line, applying a second pass bias to one or more adjacent word lines adjacent to the target word line, and applying a third pass bias to remaining word lines.
US09899091B2	Semiconductor memory device for switching high voltage without potential drop There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.
US09899089B1	Memory architecture having two independently controlled voltage pumps A system including a memory architecture is described. In one embodiment, the memory architecture includes an array of non-volatile memory cells, a first independently controlled voltage generation circuit, a plurality of register bits to store programmable values used by the independently controlled voltage generation circuit and a control circuit coupled to the first independently controlled voltage generation circuit. The first independently controlled voltage generation circuit is coupled to supply a positive voltage to the array during program and erase operations so that a magnitude of the positive voltage is applied across a storage node of an accessed memory cell of the array. The plurality of register bits to store programmable values used by the independently controlled voltage generation circuit to control the magnitude of the positive voltage. The control circuit controls a duration of the positive voltage. Other embodiments are also described.
US09899088B1	Content addressable memory decomposition Circuits and methods are disclosed for decomposition of a content addressable memory into a plurality of CAMs having a lower cost. In an example implementation, a set of CAM rules are grouped into a plurality of subsets. For each of the subsets, CAM rules in the subset are reformatted for storage in a respective CAM configured to store fewer ternary bits or configured for prefix match. Each reformatted subset of CAM rules are stored in the respective CAM. A search key formatting circuit is configured to reformat an input search key for each of the respective CAMs is used to store the reformatted subsets to produce a respective reformatted search key and input the respective reformatted search key to the respective CAM.
US09899085B1	Non-volatile FeSRAM cell capable of non-destructive read operations A FeSRAM cell includes (a) first and second inverters between a power supply voltage and a ground reference cross-coupled to each other, the first and second cross-coupled inverters providing first and second data terminals; (b) first and second select transistors respectively coupled to the first and second data terminals to control access to the first second data terminals; and (c) first and second ferroelectric capacitors coupled between a first plate line and respectively the first and second data terminals, the first plate line receiving a negative programming voltage having a magnitude greater than the power supply voltage to allow programming one of the first and second ferroelectric capacitors into a first non-volatile programmed state.
US09899082B2	Semiconductor memory device According to one embodiment, a semiconductor memory device includes: a first memory cell including a first variable resistance element; a first buffer coupled to the first memory cell; a second memory cell including a second variable resistance element; and a second buffer coupled to the second memory cell. In data write, first data is stored in the first buffer and is transferred to the first memory cell, and second data is stored in the second buffer and is transferred to the second memory cell, and a start of the transferring the first data and the second data is based on a first data transfer signal.
US09899079B2	Memory devices A device is disclosed that includes memory cells, bit lines and a source line. The bit lines and the source line are electrically connected to the memory cells. In the I/O memory block, the source line and the bit lines are configured to provide logical data to the memory cells.
US09899073B2	Multi-level storage in ferroelectric memory Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. In some examples, multi-level accessing, sensing, and other operations for ferroelectric memory may be based on sensing multiple charges, including a first charge associated with a dielectric of the memory cell and a second charge associated with a polarization of the memory cell. In some cases, multi-level accessing, sensing, and other operations may be based on transferring a first charge associated with a dielectric of the memory cell to a sense amplifier, isolating the sense amplifier, activating the sense amplifier, transferring a second charge associated with a polarization of the memory cell to the sense amplifier, and activating the sense amplifier a second time.
US09899069B1	Adaptable sense circuitry and method for read-only memory Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.
US09899062B2	Interface apparatus for designating link destination, interface apparatus for viewer, and computer program An interface apparatus for designating a link destination, is provided with: a range designating device (110) for designating a desired range in a screen on which motion picture content is reproduced; a range mark setting device (107b) for superimposing and displaying a range mark indicating the designated range on the motion picture content; a movement operating device (110, 105, 107b) for moving the range mark in a desired direction, along with a lapse of reproduction time of the motion picture content in the screen; a link destination inputting device (110) for inputting link destination identification information as what corresponds to the range mark; and a holding device (106) for holding position information indicating a position of the range mark, in association with the link destination identification information and each time point in the reproduction time.
US09899054B2	Apparatus and system to secure and maintain integrity of a physical disc Apparatus, systems, and methods disclosed herein include apparatus, systems, and methods for securing the information contained on information discs, such as CD's, DVD's, Blu-Ray discs, or any optical media used for carrying information. The apparatus includes a security device that prevents unauthorized users from accessing the protected disc, discs, or spindle. The apparatus is such that any unauthorized attempts to unlock the locking device will result in damage to the disc, making it unreadable and/or unrenderable. The security device may be part of a system that also includes a network and a remote authentication server. Authentication data is transmitted over the network between the security device and the remote authentication server. The authentication data is then used to determine whether or not to unlock the security device.
US09899053B1	Protecting against unauthorized firmware updates using induced servo errors Method and apparatus for data security in a data storage device. In some embodiments, a first version of firmware is installed in a memory of the device. The firmware is used by a programmable processor to control accesses to a rotatable data recording medium on which is written pre-recorded servo positioning data used to position a data transducer. A newer, second version of the firmwave is subsequently installed in the memory to replace the first version of firmware. The second version of the firmware includes an instruction to corrupt a selected portion of the servo positioning data on the medium in order to authenticate the second version of the firmware. During a subsequent initialization of the device, host access is granted based on detection of the corruption of the selected portion of the servo positioning data.
US09899050B2	Multiple layer FePt structure One embodiment described herein is directed to a method involving depositing a seed layer on a substrate, the seed layer comprising A1 phase FePt with a ratio of Pt of Fe greater than 1:1. A main layer is deposited on the seed layer, the main layer comprising A1 phase FePt with a ratio of Pt to Fe of approximately 1:1. A cap layer is deposited on the main layer, the cap layer comprising A1 phase FePt with a ratio of Pt to Fe of less than 1:1. The seed, main and cap layers are annealed to convert the A1 phase FePt to L10 phase FePt having a graded FePt structure of varying stoichimetry from approximately Fe50Pt50 adjacent a lower portion of the structure proximate the substrate to Fe>50Pt<50 adjacent an upper portion of the structure opposite the lower portion.
US09899047B2	Bond pad sharing for powering a multiplicity of electrical components A bond pad set includes at least one ground pad and at least one electrical bond pad configured to bias and send/receive signals. The bond pad set is electrically connected to a multiplicity of electrical components. At least one electrical bond pad of the bond pad set is shared between two or more of the electrical components.
US09899046B2	Method of testing anti-high temperature performance of a magnetic head and apparatus thereof A method of testing anti-high temperature performance of a magnetic head comprises applying a plurality of second magnetic fields with different intensities in a second direction to the magnetic head, and measuring a second output parameter curve, and judging whether a variation that is beyond an allowable value is presented on the second output parameter curve, therein the second direction passes through the ABS and at an angle whose absolute value is an acute angle to the ABS. The present invention can screen out defective magnetic heads that possess poor anti-high temperature performance without heating the magnetic head.
US09899042B1	Data writer with laminated front shield A data storage device data writer may arrange a write pole to be positioned uptrack from a front shield on an air bearing surface. The front shield can consist of a lamination of a first magnetic alloy material and a second magnetic alloy material. The second magnetic alloy material may be NiFe that has 80% iron by weight.
US09899040B2	Methods and systems for managing adaptation data Computationally implemented methods and systems include managing adaptation data, wherein the adaptation data is correlated to at least one aspect of speech of a particular party, facilitating transmission of the adaptation data to a target device, in response to an indicator related to a speech-facilitated transaction of a particular party, wherein the adaptation data is correlated to at least one aspect of speech of the particular party, and determining whether to update the adaptation data, said determination at least partly based on a result of at least a portion of the speech-facilitated transaction In addition to the foregoing, other aspects are described in the claims, drawings, and text.
US09899035B2	Systems for and methods of intelligent acoustic monitoring A system for intelligent acoustic monitoring. The system includes a microphone to capture environmental acoustic data and a processor coupled to the microphone. The processor is configured to receive and perform acoustic analysis on the captured acoustic data to generate an acoustic signature, based on a result of the acoustic analysis, identify an event indicated by the acoustic signature, and perform a remedial action based on the identified event.
US09899033B2	Signal coding and decoding methods and devices In a signal coding method, bits for coding allocated to different bands of a frequency domain signal obtained from an input signal are adjusted to improve the coding quality. The total available bits for coding are first allocated to the bands of the frequency domain signal according to a predetermined allocation rule. The numbers of bits allocated to the respective bands of the frequency domain signal are then adjusted when a highest frequency of the frequency domain signal to which bits are allocated is greater than a predetermined value. The frequency domain signal is coded according to the adjusted bit allocation for the bands of the frequency domain signal.
US09899031B1	Method and apparatus for inserting tag into stereo audio signal, and method and apparatus for extracting tag from stereo audio signal Provided is a tag insertion method performed by an apparatus for inserting a tag into a stereo audio signal, the method including receiving an original stereo audio signal, analyzing an energy distribution of the original stereo audio signal based on an azimuth, determining valid azimuths for control information and for a plurality of pieces of tag information based on the energy distribution, wherein the control information is used to control tag information, modulating the plurality of pieces of tag information and the control information generated based on the valid azimuths, generating a left signal and a right signal based on the modulated control information and the plurality of pieces of modulated tag information, and generating a multi-tagged stereo audio signal by mixing the generated left signal and the generated right signal with the original stereo audio signal.
US09899023B2	Audio video navigation device, vehicle and method for controlling the audio video navigation device An Audio Video Navigation (AVN) device includes a voice receiver for receiving a command from a user in a voice recognition mode; a storage for storing Help; and a controller for providing the Help for the user if the number of times a same pattern has occurred is equal to or greater than a threshold in the voice recognition mode.
US09899021B1	Stochastic modeling of user interactions with a detection system Features are disclosed for modeling user interaction with a detection system using a stochastic dynamical model in order to determine or adjust detection thresholds. The model may incorporate numerous features, such as the probability of false rejection and false acceptance of a user utterance and the cost associated with each potential action. The model may determine or adjust detection thresholds so as to minimize the occurrence of false acceptances and false rejections while preserving other desirable characteristics. The model may further incorporate background and speaker statistics. Adjustments to the model or other operation parameters can be implemented based on the model, user statistics, and/or additional data.
US09899016B2	Musical sound signal generation apparatus that generates sound emulating sound emitting from a rotary speaker An electronic musical instrument includes a storage unit storing waveform data WD constituted by a plurality of sample values, the waveform data expressing an acoustic waveform of a musical sound emitted from a speaker while a rotor rotates about a rotation axis by a predetermined angle, and a reproduction unit configured to sequentially read out the sample values from the storage unit and generate a musical sound signal based on the read-out sample values, the reproduction unit being configured to change a reproduction speed of the musical sound expressed by the plurality of sample values, without changing a pitch and formant of the musical sound.
US09899015B2	Systems and methods for creating digital note information for a metal-stringed musical instrument Systems and methods for a digital instrument are described, for example to simulate or be used in conjunction with a stringed instrument. A sensor system detects the deflection of one or more strings of the digital instrument, produces a measurement of the detected deflection, correlates the measurement to a musical note, and produces at least a portion of digital output based upon the musical note.
US09899011B2	Guitar support assembly A guitar support assembly engages a handle of an amplifier and receives a neck of a guitar. The guitar support assembly includes a body that has an upper surface and a lower surface. The body is bound by a perimeter edge that has a front side, a rear side, a first lateral side and a second lateral side. The front side has a notch that receives the neck of the guitar or another string instrument. A tab is attached to the rear side and extends away from the body. The tab is spaced from the first lateral side and the second lateral side. The body is situated on the amplifier such that the notch receives the neck of the guitar and retains the guitar in a vertical position.
US09899009B2	Guitar capo with universal device mount Described herein is a combination guitar capo with universal electronic device mount for placement onto a guitar. The mount allows a user to view the attached device while playing the guitar.
US09899003B2	Display system A display system and a method for displaying items and/or performances is provided. At least a display panel is used to play multimedia content. In an embodiment, at least a portion of the display panel turns transparent for displaying items or performances in a display space. In an embodiment, the display item is moved in accordance with the multimedia played on the display panel. In an embodiment, light effects are adjusted during the display. In an embodiment, audio media is played and adjusted during the display.
US09898997B2	Display driving circuit The display driving circuit including a type detector for receiving a data packet including a 2-bit embedded signal, in which a clock signal embedded in a data signal, and outputting a first reference clock or a second reference clock different from the first reference clock according to a type of the data packet, a window generator for receiving multi-phase clocks and providing to the type detector a first window reference and a second window reference different from the first window reference to be used in determining the type of the data packet, a buffer for delaying the first reference clock by a first interval and delaying the second reference clock by a second interval different from the first interval, and a multiplexer for multiplexing the delayed first and second reference clocks and outputting a multiplexed reference clock may be provided.
US09898996B2	Display apparatus and display control method A display apparatus includes a display section configured to display, on a display surface, a screen of an application program running on an information processing apparatus, a detecting section configured to detect the position of a pointer, a drawing section configured to draw, when an operation mode of the display apparatus is a first mode, a line corresponding to a track of the position, a transmitting section configured to transmit, when the operation mode is a second mode, information indicating the position to the information processing apparatus, and an erasing section configured to erase the line when a first position of the pointer when the operation mode is the first mode is within a predetermined range including a first image object for performing an input to the application program on the screen and an instruction from a user for switching the operation mode to the second mode is received.
US09898995B2	Head-mounted display device and method of changing light transmittance of the same A method of changing a light transmittance of a head-mounted display device and the head-mounted device. The method of changing a light transmittance of a head-mounted display device includes detecting an illuminance; determining an application displayed on a display unit of the head-mounted display device; determining a first light transmittance corresponding to the illuminance and the application; and changing a second light transmittance of a light transmission unit of the head-mounted display device to the determined first light transmittance.
US09898994B1	Voltage generation circuit and liquid crystal television The present invention provides a voltage generation circuit, comprising a control unit, a controlled unit and an output unit, and the control unit receives a trigger signal to generate a control signal having a preset delay, and the control unit is further coupled to the controlled unit to control the controlled unit to be in a first state in a duration of the preset delay and to be in a second state in a duration of a non-preset delay, and the output unit outputs a first drive voltage to the drive unit as the controlled unit is in the first state and to output a second drive voltage to the drive unit as the controlled unit is in the second state, and the first drive voltage is smaller than the second drive voltage to achieve decreasing the drive voltage to lower power consumption of the data drive chip.
US09898993B2	Method for controlling message signal within timing controller integrated circuit, timing controller integrated circuit and display panel The present disclosure provides method for controlling a message signal within a timing controller integrated circuit, the timing controller integrated circuit and a display panel. The method includes: receiving a low voltage differential signaling signal; decoding the low voltage differential signaling signal to obtain a transistor-transistor logic RGB data signal and a control signal, wherein the control signal comprises: a start signal, a horizontal synchronization and a vertical synchronization; processing the transistor-transistor logic RGB data signal to obtain an input RGB data; controlling a timing of the start signal before a timing of the input RGB data; and processing the input RGB data to obtain a mini-low voltage differential signaling data. Therefore, the technical scheme provided by the present disclosure has an advantage of the low cost.
US09898986B2	Display device capable of performing black frame insertion The present invention discloses a display device capable of performing black frame insertion. The gamma circuit comprises an either-or multiplex selector. The input data of one input end of the selector is a VCOM voltage outputted by the gamma circuit, and the input data of the other input end of the selector is a voltage converted from a predetermined value after digital to analog conversion stored in a multi time programmable memory of the gamma circuit. As the selector selects the VCOM voltage outputted by the gamma circuit under control of the control port, the outputted VCOM voltage is amplified by an operational amplifier in the gamma circuit and then outputted to the source driving circuit to be a first gamma reference voltage which is required as the source driving circuit performs digital to analog conversion.
US09898985B2	Gate on array drive system of raising yield and liquid crystal panel having the same The present invention provides a GOA drive system and a liquid crystal panel. Two GOA modules (2) are respectively provided at two sides of the liquid crystal display area (1), and each GOA module (2) is electrically coupled to one automatic detection interrupting function module (3) correspondingly, and each automatic detection interrupting function module (3) receives a feedback signal (FB) transmitted from the GOA unit circuit of the last stage of the GOA module (2), and by detecting whether the feedback signal (FB) is normal or abnormal, the scan start signal (STV) is transmitted or not transmitted to the corresponding GOA module (2) to normally drive the corresponding GOA module (2) or terminate driving so that as the GOA module (2) at one side of the liquid crystal panel display area (1) appears to be abnormal, the corresponding automatic detection interrupting function module (3) terminates driving the abnormal GOA module (2), and the GOA module (2) at the other side of the liquid crystal panel display area (1) continues normal driving, which contributes to raise the yield of the liquid crystal panel.
US09898962B2	Organic light emitting display device An organic light emitting display device is disclosed, which may increase sensing accuracy by solving a problem that a difference between sensing data output from sensing units is generated due to a difference in sensing capability between the sensing units. The organic light emitting display device includes a display panel including data lines, scan lines, sensing lines, and pixels connected to the data lines, the scan lines and the sensing lines; a sensing data output unit outputting first sensing data by sensing currents flowing to the sensing lines; a scan driver supplying scan signals to the scan lines; and a source drive integrated circuit (IC) including a data voltage supply unit supplying data voltages to the data lines and a switching unit connecting the sensing lines to the sensing data output unit in a predetermined order.
US09898961B2	Data processing method and apparatus for organic light emitting diode display device A data processing method and an apparatus for an organic light emitting diode (OLED) display device are provided. The method includes modulating input data using a maximum degradation compensation gain, compensating degradation of the modulated data using a degradation compensation gain, accumulating the degradation-compensated data, determining a degree of degradation of each of sub-pixels, based on the accumulated data, detecting a degradation compensation gain in accordance with the determined degradation degree, storing the detected degradation compensation gain, and outputting the stored degradation compensation gain, detecting a maximum one of degradation compensation gains of respective sub-pixels, and outputting the detected maximum degradation compensation gain, analyzing the input data, thereby setting a peak luminance control (PLC) gain, and modulating the PLC gain, using the output maximum degradation compensation gain, and analyzing the degradation-compensated data, thereby detecting a peak luminance, and adjusting the detected peak luminance, using the modulated PLC gain.
US09898958B2	Shift register unit, shift register, gate driver circuit and display apparatus The present disclosure provides a shift register unit and a shift register, a gate driver circuit and a display apparatus where the shift register unit can be applied. A signal amplification module including two transistors each having a small channel width is added at an output node of the shift register unit. In this way, the output capability can be improved significantly with the same design parameters in case of a high load.
US09898957B2	Display device with switchable viewing angle and operation method thereof A display device with switchable viewing angle includes a first pixel and a second pixel. The first pixel has a first sub-pixel and a second sub-pixel. The second pixel has a third sub-pixel, a fourth sub-pixel and a fifth sub-pixel. The fifth sub-pixel is configured to be enabled when operating in a narrow viewing angle mode and to be disabled when operating in a wide viewing angle mode. When the fifth sub-pixel is enabled, each viewing angle of the first sub-pixel, the second sub-pixel, the third sub-pixel and the fourth sub-pixel is narrower than that when the fifth sub-pixel is disabled.
US09898956B2	Method of driving active-matrix organic light-emitting diode (AMOLED) panels A method of driving active-matrix organic light-emitting diode (AMOLED) panels includes: (A) dividing a current frame of a current image corresponding to an i-th color component into a plurality of sub-frames, wherein iε[1,N], and N is a total number of the color component; (B) obtaining a sequence of the sub-frames of a previous frame of a previous image corresponding to the i-th color component, wherein the previous frame has been divided into a plurality of sub-frames by the same way with the current frame; (C) determining the sequence of the sub-frames of the current frame in accordance with the sequence of the sub-frames of the previous frame, wherein the sequence of the sub-frames (SF) of the current image is same with or is different from that of the previous frame; and (D) controlling the panel to display in accordance with the sequence of the sub-frames of the current frame determined by corresponding color components.
US09898955B2	Active-matrix display with power supply voltages controlled depending on the temperature In a liquid crystal or OLED active-matrix screen, the power supply voltages VGON and VGOFF of the display control circuit driving the control transistors of the pixels are optimized, as a function of a measurement of the operating temperature, to conserve the display qualities of the screen at high and low temperatures and reduce the power consumed on average to produce screens for applications in a severe environment, with transistors of standard size. Circuits are provided for supplying these analog voltages from numeric values supplied by a code associated with the temperature measurement, stored or computed by a programmable circuit. Provision is made to adapt these voltages as a function of a measurement of lighting level received by the transistors of the display control circuit. The optimization extends to the power supply and reference voltages necessary to the control of the pixels, notably to the gamma reference voltages.
US09898954B2	Liquid crystal panel common electrode voltage adjustment device and liquid crystal panel common electrode voltage adjustment method The present invention provides a liquid crystal panel common electrode voltage adjustment device and a liquid crystal panel common electrode voltage adjustment method. The liquid crystal panel common electrode voltage adjustment device includes a detection unit, a data collection unit, a process unit and an adjustment unit, and the detection unit detects a flicker condition of the liquid crystal panel in an activation state, and the data collection unit collects a common voltage value as the flicker exceeds a predetermined range to obtain a first common voltage, and the process unit obtains a control signal according to the first common voltage, and the adjustment unit sends a corresponding adjustment signal, and the adjustment signal adjusts the common voltage to be a second common voltage, and as the second common voltage is applied to the liquid crystal panel, the flicker of the liquid crystal panel is controlled in the predetermined range.
US09898952B2	Data compensation device compensating data based on average current, bus voltage drop information, and array voltage drop information and display device including the same A data compensation device includes a current calculator which calculates an average current of each of blocks included in a pixel array based on an input data, a data enable signal, a horizontal synchronization signal and a vertical synchronization signal, a voltage drop info provider which provides a bus voltage drop information of predetermined bus points and an array voltage drop information of predetermined array points, the bus points being included in a power supply bus wiring which is connected to the pixel array, the array points being included in the pixel array, a data compensation circuit configured to provide a compensation data corresponding to the input data based on the average current, the bus voltage drop information and the array voltage drop information, and an adder configured to provide a compensation result data by adding the input data and the compensation data.
US09898951B2	Display screen and method for secure representation of information A display screen for secure representation of information comprising a background grid with light-emitting background grid elements of a first type and light-emitting or light-blocking background grid elements of a second type. A foreground grid (4) having completely light-transmissive foreground grid elements and light-attenuating foreground grid elements is arranged in front of the background grid. The lateral dimensions of the foreground grid elements, the distance and the lateral position of the foreground grid are matched in relation to the background grid in such a manner that a viewer looking at the foreground grid perceives coded information in a decoded form, on the basis of a contrast difference and/or color difference in relation to those fields of the background grid that are base-coded, only from one direction of view or one view angle range of up to ±50° about the view direction. Further, a method for secure representation of information on such a display screen.
US09898949B2	Electronic device for adjusting brightness of display screen of the electronic device and method using the same In a method for adjusting brightness of a display screen of an electronic device, a current brightness value of the display screen and a current illumination value of ambient lights are acquired, and then are processed by denoising and normalizing. The current brightness value is adjusted to meet user preferences by self-learning according to the current illumination value and a brightness/illumination relationship table which stores a relationship between brightness values of the display screen and illumination values of ambient lights determined according to the user preferences.
US09898945B2	Display panel and method for verifying data lines thereon A display panel includes a substrate, a display area, N data lines, first switches, second switches, third switches, and fourth switches. A first peripheral circuit zone, a second peripheral circuit zone, and a display area are defined on a first surface of the substrate, and located between the first peripheral circuit zone and the second peripheral circuit zone. A display area circuit is located in the display area. Each of the N data lines crosses the display area circuit from the first peripheral circuit zone to the second peripheral circuit zone, and N is a positive integer greater than 1. The first switches are located in the first peripheral circuit zone. The second switches are located in the first peripheral circuit zone. The third switches are located on the first surface. The fourth switches are located in the second peripheral circuit zone.
US09898943B2	Liquid crystal display module The present disclosure provides a liquid crystal display module, which includes a liquid crystal display panel and a driver integrated circuit, wherein the liquid crystal display panel includes a testing pad, a first pad and a second pad, the first pad includes a first sub pad and a second sub pad which are separately disposed, the second sub pad is electrically connected to the testing pad, the driver integrated circuit includes at least two third pads, the third pads are respectively bonded to the first pad and the second pad; the first sub pad and the second sub pad are commonly bonded to one of the third pads, so as to achieve a short circuit between the first sub pad and the second sub pad. In the liquid crystal display module of the present disclosure, the space occupied by the bonding area is small.
US09898938B1	Trifold letter card display Various embodiments provide a trifold letter card comprising a first riser portion, a second riser portion, a base portion, and an engaging portion. The engaging portion comprises at least three segments and at least two slits. Such structures allow the first riser portion to be inserted through the at least two slits and secured relative to the engaging portion.
US09898937B2	Surgical training model for laparoscopic procedures A model for practicing laparoscopic surgical skills is provided. The model includes a base having a plurality of practice stations at the upper surface. The practice stations include a cover having a first closed position in which a cavity is concealed beneath the cover and a second open position in which the cover is moved to uncover the cavity. The covers are connected to the surface in a number of ways to provide a variety of haptic responses useful in fine-tuning laparoscopic surgical skills. The cover is configured as a door hinged with or without a bias, a flexible flap, a sliding cover, a lid, and a penetrable sheet. An object for removal is hidden inside the cavity underneath the cover for practicing hand-to-hand transfer of instruments, use of both hands, switching instruments and determining and visualizing tissue planes in a laparoscopic environment.
US09898936B2	Recording, monitoring, and analyzing driver behavior A system that monitors, records and analyzes driver performance includes a server having: a map data access module that retrieves map data elements indicating various features associated with at least one path of at least one vehicle including a set of previously-defined segments having a set of associated points including a set of associated attributes having a set of fixed attributes; a communication module that receives information from the at least one vehicle, the received information including data from an in-vehicle system including sensors associated with the at least one vehicle; a driver behavior engine that monitors and evaluates driver performance based on the received information by: generating evaluation curves based on the retrieved set of map data elements; and calculating mathematical differences between each evaluation curve and corresponding performance curves generated based on the set of measured driving characteristics for a particular driver and a particular trip.
US09898935B2	Language system A language system having an image library and a text and/or audio library for enabling a user with a user device to form words, phrases and sentences by selecting by selecting images and to provide the user with text and/or audio representations thereof in a chosen language.
US09898929B2	Vehicle driving assistance apparatus A vehicle driving assistance apparatus has a sensor that detects an object around an own vehicle; and a processing apparatus that determines whether the object detected by the sensor is a static vehicle or a roadside static object, carries out driving assistance if a first driving assistance carrying-out condition is satisfied when determining as a static vehicle and carries out the driving assistance if a second driving assistance carrying-out condition is satisfied when determining as a roadside static object. A threshold concerning the first driving assistance carrying-out condition is lower than a threshold concerning the second driving assistance carrying-out condition.
US09898927B2	Wi-Fi/radio frequency converting device A Wi-Fi/radio frequency (RF) converting device includes a Wi-Fi transceiver, a multiplexing converting module, an RF transceiver, and an RF extension device. The Wi-Fi transceiver receives a Wi-Fi control signal from a control signal generator, wherein the Wi-Fi control signal contains at least one command. The multiplexing converting module receives the Wi-Fi control signal from the Wi-Fi transceiver, and converts the Wi-Fi control signal into a first wireless control signal or a second wireless control signal. The RF transceiver is electrically connected to the multiplexing converting module, and is connected to at least one electric appliance through RF signals. The RF transceiver receives the first wireless control signal from the multiplexing converting module, and transmits the RF control signal to the electric appliance. The RF extension device transmits the second wireless control signal, which corresponds to at least one another electric appliance, to the at least one another electric appliance.
US09898924B2	Method for the reliable transport of alarm messages in a distributed computer system The invention relates to a method for the reliable transport of alarm messages in a distributed computer system, said computer system comprising components, in particular a plurality of components, the components being node computers, distributor units, sensors—preferably intelligent sensors—and actuators—preferably intelligent actuators—and all components having access to a global time of known precision, and the node computers, intelligent sensors and intelligent actuators exchanging messages via the distributor units. It is provided that the computer system includes intelligent alarm sensors or intelligent alarm sensors are assigned to the computer system, and an intelligent alarm sensor transmits two types of time-triggered messages, alarm messages having an alarm transport period prescribed a priori, and error detection messages having an error detection period prescribed a priori, and the time stamps for the occurrence of alarm events are included in an alarm monitoring interval, the alarm monitoring interval ending directly before the transmission of the alarm message and being at least twice as long as the alarm transport period, and an alarm message only being transmitted if at least one time stamp of an alarm event is included in the alarm message, and the current states of all alarms that are active immediately before the transmission of the error detection message are included in the periodic error detection messages.
US09898922B2	Systems and methods for coordinating and administering self tests of smart home devices having audible outputs Systems and methods for self-administering a sound test to verify operation of a speaker and/or alarm within a hazard detection system are described herein. The sound test can verify that the audible sources such as the alarm and speaker operate at the requisite loudness and frequencies. In addition, the sound test can be self-administered in that it does not require the presence of a person to initiate or verify that the audible sources are functioning properly.
US09898920B2	System and method for preventing loss of electronic cigarette case The invention is related to a system and method for preventing a loss of an electronic cigarette case. The system comprises a first receiving and transmitting module, a first alarm module, a first control module, a second receiving and transmitting module and a second control module. The second receiving and transmitting module and the second control module are connected and are arranged together on an electronic cigarette. The first receiving and transmitting module and the first alarm module are respectively connected to the first control module, and are arranged together on the electronic cigarette case used for accommodating an electronic cigarette. The first receiving and transmitting module and the second receiving and transmitting module are in a wireless communication connection within a preset range. The system and method for preventing the loss of the electronic cigarette case has a beneficial effect of preventing the loss of the electronic cigarette case.
US09898919B2	Keypad projection A method for security and/or automation systems is described. In one embodiment, the method may include detecting a proximity of a user at a home automation device. The method may further include projecting an external display of home automation system information from the home automation device onto a surface. In some embodiments, the external display may be projected based, at least in part, on the detected proximity of the user at the home automation device.
US09898918B2	Treadmill belt wear notification system Belt wear of a treadmill is monitored. In one implementation, samples of electric current draw of a treadmill at different speeds of the treadmill belt of the treadmill are received. A value of each sample is differently weighted based on a speed of the treadmill belt at which the value of each sample was obtained. A belt wear notification is output based on the different weighted values of the samples.
US09898917B2	Method and apparatus for providing environmental management using smart alarms The present invention is directed to methods and apparatuses for environmental management using a smart alarm comprising, receiving one or more readings from one or more sensors, wherein the sensors are of at least one or more distinct logical types, generating one or more derived points representing the one or more readings from the sensors and alerting one or more alarm units when the derived points satisfy an alarm condition.
US09898914B2	Technology for detecting a fall of a person A technology for detecting a fall of a person is provided. A corresponding device (100) comprises an interface (102) which is designed for capturing a time-dependent air pressure signal (600) that is determined by means of at least one air pressure sensor (104, 106) worn on the body of the person. The device (100) also comprises an evaluation unit (108) which is designed for determining a fall height (λ) with respect to an evaluation time (te) by means of a window-based signal analysis of the time-dependent air-pressure signal. The window-based signal analysis includes a first time window (702) before the evaluation time and a second time window (704), which does not overlap with the first time window, after the evaluation time. The fall height is determined from a difference between a first filter value that is computed based on the time-dependent air pressure signal in the first time window, and a second filter value that is computed based on the time-dependent air pressure signal in the second time window.
US09898913B2	Medical alert message pre-configuration and mission handling method A medical alert message handling method for a medical communication device is disclosed. The medical alert message handling method includes receiving a shift, a medical alert message classification configuration and a medical alert message priority configuration, receiving at least one medical alert message, filtering the medical alert message according to the shift to generate a personal alert message, displaying the personal alert message, filtering the medical alert message according to the medical alert message classification configuration and the medical alert message priority configuration, receiving a selection command to select one of the medical alert message, and noting a handling status and a handling problem of the selected medical alert message.
US09898910B2	System and method for remote monitoring based on LED lighting device A system for remote monitoring based on an LED lighting device is provided. The system includes a smart terminal configured to check regularly data and status of the LED lighting device stored in a cloud server and a wireless router configured to provide a wireless network. The LED lighting device includes a Wi-Fi module and a microwave sensor module, where the Wi-Fi module is configured to connect the LED lighting device to the wireless network, perform real-time data acquisition on the microwave sensor module, and upload the acquired data to the cloud server in real time; and the microwave sensor module is configured to detect object movement within an effective range. Further, the system includes the cloud server configured to receive information about an abnormal object moving within the effective range sent from the Wi-Fi module, and send the received information to the smart terminal.
US09898908B2	Method and system for site-based power management of radio frequency identification implementations A method and system for site based RFID power management is provided. The systems comprise one or more gateways, configured to create chatter in one or more gateway transmission ranges, a tag, located on an asset and operable in a plurality of states, configured to identify the presence of chatter in a tag reception range, and if chatter is identified by the tag, created by a chatter creating gateway that is one of the one or more gateways, then the tag enters a chatter present state.
US09898901B1	Physical security system for computer terminals A computer terminal located in an environment may include an actuator, retractable privacy barrier attached to the computer terminal by the actuator, a display, a memory, a processor, and a terminal application stored in the memory. The actuator is typically configured to extend the retractable privacy barrier to thereby reduce viewability of the computer terminal. The terminal application is typically configured for initiating an interactive session with a user, determining that a trigger event has occurred, and in response to determining that the trigger event has occurred, transmitting a control signal to the actuator, the control signal causing the actuator to extend the retractable privacy barrier. The present invention is further configured for monitoring one or more parameters of the environment, and displaying, via the display, data associated with the one or more parameters of the environment.
US09898900B2	Automated banking system controlled responsive to data bearing records An automated banking machine operative to cause financial transfers responsive to data read from data bearing records. The automated banking machine includes a card reader that is operative to read card data from user cards corresponding to financial accounts. The automated banking machine is operative responsive to the card data to carry out transactions that transfer and/or allocate funds between accounts. The automated banking machine is further operative to provide users with a receipt for transactions conducted. The automated banking machine includes a cash dispenser operative to dispense cash to machine users and to cause the value of cash to be assessed to financial accounts corresponding to card data. The automated banking machine is further operative to receive currency bills or other sheets from a user and to process and store such sheets through operation of a currency accepting device. The account corresponding to card data may be credited for the value of bills or other sheets received.
US09898896B2	Methods of playing wagering games and related systems A card game is played against a pay table, wherein a player receives a partial hand that is preferably completed by community cards, but may be completed by cards dealt directly to a hand or a combination of cards dealt directly to a hand and at least one community card or wild card. After placement of an ante wager, each player will have an opportunity to place a game wager before receiving another card for the player's hand (whether dealt directly to the player or as a community card revealed to all players). At least some or all game wagers may be an amount within a range of multiples of the player's ante wager, such as one times, two times, three times, four times, or five times the amount of the ante wager. The range of wagers may remain the same or vary with the number of dealt cards or community cards revealed to the players.
US09898895B2	Methods, systems, and apparatus for playing poker, blackjack and baccarat A method, system, gaming apparatus for playing blackjack, poker and baccarat allowing players the option of pre-determining the starting variables from a plurality of starting wagering positions with payouts that substantially correspond with a starting selection or selections.
US09898893B2	Gaming system with spawning wild symbols A gaming system includes an input mechanism for initiating a game and one or more displays providing a plurality of reels. The gaming system also includes a controller coupled to the one or more displays and the input mechanism. The controller is configured to: detect a win involving a combination of the symbol instances across two or more of the reels; determine that at least one of the symbol instances involved in the win is a wild symbol, the wild symbol able to assume the identity of at least one other symbol when detecting the win; and in response to determining that at least one of the symbol instances involved in the win is a wild symbol, updating at least one of the other of the symbol instances involved in the win to include a wild symbol for at least the next iteration of the game.
US09898885B1	Prize-dispensing apparatus A prize-dispensing apparatus includes a casing unit, a preloading unit, a pulling unit, a feed-measuring unit and a grabbing unit. The preloading unit is partially inserted in and movably connected to the casing unit. The pulling unit is inserted in and connected to the casing unit. The grabbing unit includes claws and links. Each claw incudes an upper end pivotally connected to the preloading unit and a lower end for contact with a prize. Each link includes an upper end pivotally connected to the casing unit and a lower end pivotally connected to a portion of a corresponding claw. The claws are closed to grab the prize when the pulling unit is actuated. The claws are opened by the preloading unit when the pulling unit is not actuated. The feed-measuring unit is inserted in the casing unit and used to measure feed of the pulling unit.
US09898884B1	Method and system of personal vending A system and method for vending products to a customer that encompasses a group of vending machines managed by a vending company, a database of the inventory of products in the vending machines and information about customer purchase history from the vending machines; and the use of a personal electronic device by the customer. Embodiments include the customer selecting either products or vending machines from a list of options provided via the user interface of the personal electronic device, wherein the list of options depends on the actual available inventory on vending machines co-located with customer, and the customer purchase history. Methods are described to permit advance purchases with deferred dispensing, and methods of payment that are both fast and automatic. Also described are methods of identifying vending machines and ordering a group of products as single request.
US09898881B2	Short-range device communications for secured resource access Communications over short-range connections are used to facilitate whether access to resources is to be granted. For example, upon device discovery of one of an electronic user device and an electronic client device by the other device over a Bluetooth Low Energy connection, an access-enabling code associated with a user device or account can be evaluated for validity and applicability with respect to one or more particular resource specifications. User identity can be verified by comparing the user against previously obtained biometric information.
US09898880B2	Authentication system using wearable device A wearable device (“WD”) stores a token after its wearer completes a successful strong authentication on a primary protected device (“primary PD”). Other protected devices (“secondary PDs”) recognize the stored token as representing a strong authentication and grant the user access while the user continues to wear the WD within a “digital leash-length” proximity. The WD constantly monitors whether the user continues to wear the device. Upon sensing that the user has removed the WD, the WD deletes, disables, or invalidates the token, The user must then repeat the strong authentication to gain further access to the protected devices.
US09898878B2	Entry control system An integrated security system which seamlessly assimilates with current generation logical security systems. The integrated security system incorporates a security controller having standard network interface capabilities including IEEE 802.x and takes advantage of the convenience and security offered by smart cards and related devices for both physical and logical security purposes. The invention is based on standard remote authentication dial-in service (RADIUS) protocols or TCP/IP using SSL, TLS, PCT or IPsec and stores a shared secret required by the secure communication protocols in a secure access module coupled to the security controller. The security controller is intended to be a networked client or embedded intelligent device controlled remotely by to an authentication server. In another embodiment of the invention one or more life cycle management transactions are performed with the secure access module. These transactions allow for the updating, replacement, deletion and creation of critical security parameters, cryptographic keys, user data and applications used by the secure access module and/or security token. In another embodiment of the invention a security access module associated with the security controller locally performs local authentication transactions which are recorded in a local access list used to update a master access list maintained by the authentication server.
US09898875B2	Maintenance systems and methods for ECS elements A maintenance system is provided for an environment conditioning element of an environmental control system (ECS) of a vehicle. The system includes a data collection module configured to receive geographical areas of travel for the vehicle over respective periods of time. The data collection module is configured to determine a pollution value and a time value for each of the geographic areas of travel. The system further includes a pollution count module coupled to the data collection module and receiving the pollution values and the time values. The pollution count module is configured to determine a pollution count for the environment conditioning element based on the pollution values and the time values. The system further includes a reporting module coupled to the pollution count module and receiving the pollution count. The reporting module is configured to generate a report for a user that includes the pollution count.
US09898867B2	System and method for augmented reality display of hoisting and rigging information A method for providing information associated with a lift process to a mobile device user is presented. The method comprises receiving a request for lift environment information from a mobile device, determining a pose of the mobile interface device relative to a lift process target area, and obtaining lift environment information for at least a portion of the lift process target area. The lift environment information is used to assemble AR lift information for transmission to and display on the mobile interface device. The AR lift information is configured for viewing in conjunction with a real-time view of the lift process target area captured by the mobile interface device. The AR lift information is then transmitted to the mobile interface device for display.
US09898866B2	Low latency stabilization for head-worn displays Methods, systems, and computer readable media for low latency stabilization for head-worn displays are disclosed. According to one aspect, the subject matter described herein includes a system for low latency stabilization of a head-worn display. The system includes a low latency pose tracker having one or more rolling-shutter cameras that capture a 2D image by exposing each row of a frame at a later point in time than the previous row and that output image data row by row, and a tracking module for receiving image data row by row and using that data to generate a local appearance manifold. The generated manifold is used to track camera movements, which are used to produce a pose estimate.
US09898861B2	Systems and methods for projecting planar and 3D images through water or liquid onto a surface Systems and methods for projecting planar and 3D images through water or liquid onto a surface include creating a 3D model of the body of liquid and surface and 3D models of creative elements to be used in scenes. Animating the 3D models of the creative elements, placing them inside the 3D model of the body of liquid. Lighting the animated creative elements, rendering planar animations of the modeled creative elements and, using projection and texturing software, virtually projecting the planar animations back onto the surface of the 3D model of the body of liquid from the same camera position in order to “bake in” a warped transformation of the digitally rendered planar animations. Digitally rendering a 3D animation of the warped, transformed planar animations, and playing or looping the digitally rendered 3D animation through the body of liquid on a digital video player or digital server.
US09898860B2	Method, apparatus and terminal for reconstructing three-dimensional object A method, an apparatus and a terminal for reconstructing a three-dimensional object, where the method includes acquiring two-dimensional line drawing information, segmenting, according to the two-dimensional line drawing information and according to a degree of freedom, the two-dimensional line drawing to obtain at least one line sub-drawing, where the degree of freedom is a smallest quantity of vertices that need to be known for determining a spatial location of the three-dimensional object that includes planes, reconstructing a three-dimensional sub-object according to the line sub-drawing, and combining all three-dimensional sub-objects to obtain the three-dimensional object, and hence, the three-dimensional object can be automatically reconstructed according to two-dimensional line drawing information.
US09898850B2	Support and complement device, support and complement method, and recording medium for specifying character motion or animation A support and complement device etc., are provided, which appropriately generates the character's motion for content introduction in a simple manner. The user inputs a command to an input device, which specifies the character's motion used for content introduction. The support and complement device complements the command input operation. The content includes material data and language data. The language data includes voice data to be emitted by the character. A unit for recognizing emotions analyzes the material data and the language data, and deduces the emotion pattern to be expressed by the character. A unit for choosing commands determines the character's motion using the deduced emotion pattern, command, and voice data, and generates a motion command. A unit for reading out animation movies for user's check instructs a readout device to display a proposed animation movie generated by the unit for choosing commands, thereby allowing the user to review it.
US09898845B2	Information processing apparatus, information processing method, and storage medium In a case where a position of a recognized cell is shifted from a position of a ruled line of an actual cell, if the recognized cell is deleted, a part of the ruled line of the actual cell is deleted. According to an aspect of the present invention, straight lines are detected from regions around four sides constituting the recognized cell, and an inside of a region surrounded by the detected straight lines is deleted.
US09898843B2	Graph display apparatus, its operation method and non-transitory computer-readable recording medium having stored therein graph display program When line graphs are displayed on coordinates having a horizontal axis as a time axis and a vertical axis as an axis representing examination values, a line graph is generated in such a manner that data points representing examination data are connected to each other by a line in a case where a time interval between examinations temporally next to each other is less than a maximum line-connection interval for an examination item, and in such a manner that data points representing examination data are not connected to each other in a case where the time interval between examinations temporally next to each other exceeds the maximum line-connection interval for the examination item. Plural line graphs overlapping with each other are displayed on the coordinates.
US09898842B2	Method and system for generating data-efficient 2D plots In one aspect, a method can include a computing system receiving data for rendering as a plurality of objects in a chart, and rendering the plurality of objects in a first order in a first graph in a virtual display. The method can include swapping a first object and a second object in the first order of the plurality of objects creating a second order of the plurality of objects, rendering the objects in a second graph in the virtual display based on the second order, determining that a number of visible objects in the first graph is less than a number of visible objects in the second graph, and outputting the second order of the plurality of objects for rendering on a display device based on determining that a number of visible objects in the first graph is less than a number of visible objects in the second graph.
US09898838B2	Graphics processing apparatus and method for determining level of detail (LOD) for texturing in graphics pipeline A method of determining a level of detail (LOD) for a texturing includes: acquiring texture coordinate data on pixels included in an upper block; determining a reference quad among quads included in the upper block; determining a similarity between the determined reference quad and the upper block using texture coordinates of the determined reference quad and the upper block; and determining LODs of remaining quads among the quads included in the upper block to be the same as an LOD of the determined reference quad in response to the determining of the similarity including determining that the determined reference quad and the upper block are similar.
US09898834B2	Method and apparatus for generating a bitstream of repetitive structure discovery based 3D model compression A method and apparatus for generating a bitstream representative of a 3D model, and a method and an apparatus for processing the same. A 3D model is modeled by using a using a ‘pattern-instance’ representation, wherein a pattern is a representative geometry of a repetitive structure, and the connected components belonging to the repetitive structure is call an instance of the corresponding pattern. After discovery of the repetitive structures and their transformations and properties, the present embodiments provide for generating a bitstream in either a first format or a second format. In the first format, the pattern ID and its associated transformation and property information are grouped together in the bitstream, and in the second format the pattern ID, transformation property and property information are grouped together according to information type.
US09898831B2	Macropixel processing system, method and article Digital image processing circuitry converts a macro-pixel of an image in a color filter array (CFA) color space to a macro-pixel in a luminance-chrominance (YUV) color space. Chrominance filtering is applied to chrominance components of the converted macro-pixel in the YUV color space, generating a filtered macro-pixel in the YUV color space. The filtered macro-pixel in the YUV color space is converted into a filtered macro-pixel in the CFA color space.
US09898829B2	Monitoring apparatus and system using 3D information of images and monitoring method using the same A monitoring apparatus using three-dimensional (3D) information of images includes: an image acquisition unit to acquire a two-dimensional (2D) image from a pan/tilt/zoom (PTZ) camera; an information extraction unit to extract 2D coordinate information of an object based on a pan/tilt angle of the PTZ camera and extract distance information between the PTZ camera and the object; an operation unit to calculate at least one of variation of the 2D coordinate information and the distance information by comparing a current frame and a previous frame of the 2D image, and variation of the 2D coordinate information and height information of the object by comparing a current frame and a previous frame of a 3D image of the object; and a position tracking unit to track a position of the object by controlling the PTZ camera based on the at least one of the two variations.
US09898828B2	Methods and systems for determining frames and photo composition within multiple frames Methods and systems for determining frames and photo composition within multiple frames are provided. First, a plurality of frames, which are respectively captured with a predefined time interval are obtained. At least one object within at least two of the frames is detected. In some embodiments, a moving speed of the object is calculated according to the positions of the object in the respective frames and the predefined time interval, and candidate frames are selected from the frames according to the moving speed of the object. In some embodiments, an overlapped area corresponding to the object within a first frame and a second frame is calculated, and at least one candidate frame is selected according to the overlapped area corresponding to the object. The at least one candidate frame is composed to generate a composed photo.
US09898827B2	High-speed automatic multi-object tracking method and system with kernelized correlation filters A high-speed automatic multi-object tracking method with kernelized correlation filters is provided. The method includes obtaining an image frame from a plurality of image frames in a video, extracting a foreground object sequence from the obtained image frame, and determining similarity between each foreground object of the extracted foreground object sequence and a tracked object. The method also includes calculating HOG features of the foreground objects with a lower similarity, obtaining training samples for each of the foreground objects with the lower similarity using a circular matrix, obtaining a classifier via a kernel method accelerated by FFTW, and obtaining tracking points using a sparse optical flow. Further, the method includes detecting object matching responses using a detection response function, performing multi-scale analysis for the object based on an optical flow method, and processing a next image frame of the plurality of image frames in the video until the video ends.
US09898826B2	Information processing apparatus, information processing method, and program An information processing apparatus inputs shape data indicating shapes and positional relationships of a plurality of objects; based on the shape data, in a space formed by a plurality of blocks each having a predetermined size, generates block data in which a corresponding attribute of an object or a space is allocated to each of the plurality of blocks; determines a part of blocks adjacent to a block having the attribute of the object in the block data as a block used for detection processing of a difference of contacted states of the objects between the shape data and the block data; and performs the detection processing by using the determined block as being used for the detection processing among the blocks adjacent to the block having the attribute of the object.
US09898822B2	Method and system for reconstructing scenes as 3D models from sequences of images using constraint satisfaction A method reconstructs a scene as a three-dimensional (3D) model by first acquiring a sequence of images of the scene with a camera. Then, feature point matches or line matches are extracted from the sequence of images, variables for camera optical centers and 3D points are initialized using random values, and n copies of the variables are made depending on an availability of n constraints. The n copies are projected to satisfy each of the n constraints. Then, the n copies are replaced with averages of the copies and the projecting and the replacing are repeated until convergence to provide the 3D model.
US09898813B2	Method for detecting flaws in the walls of hollow glass items The invention relates to a method for detecting defects in the walls of hollow glass items that rotate about their longitudinal axis during inspection, which method, in one form, is characterized by the production of an image series (4) that is binarised using a grey-scale value threshold image (5), wherein the threshold values of the threshold image (5) are measured differently according to the fixed positions of radiation-receiving elements used to display images. The images of the image series (10) formed by binarising the original image series (4) are combined in a histogram (6) that locally adds up the frequency of an occurrence of, inter alia, defect pixels representing static reflections within the sensor regions of the image series (10). Based on this histogram (6), a two-dimensional fade-out mask (12) is formed on which the regions of static reflections are combined, and by means of which the sensor regions (18) of the original image series (4) are masked, such that a masked image series (16) is produced, said series having images, in particular sensor regions characterized in that static reflections are faded out on same, whereby a subsequent flaw-detecting evaluation (17) of the images can be carried out, independent of their sequence.
US09898805B2	Method for efficient median filtering A method is disclosed for efficiently calculating a median value of a high-order array in a Single Instruction Multiple Data (SIMD) processor. Values of the high-order array are sorted vertically in each column followed by sorts on each individual row. After the sort, selective diagonal values of the sorted high-order array are used to form a low-order array to calculate the median of the high-order array. The median calculation using selective diagonal values of the high-order array in a low-order array significantly improves SIMD processor efficiency and throughput.
US09898803B2	Image processing apparatus, image processing method, and recording medium storing image processing program An image processing apparatus including: an image obtaining unit that obtains low-resolution (LR) images acquired in time series; a position alignment unit that aligns the LR images on the basis of a movement between the LR images to generate a high-resolution (HR) image; a correlation calculating unit that calculates correlation information between areas of the LR images, the areas corresponding to partial area in the HR image; a compositing-ratio calculating unit that calculates, for each partial area, a ratio between the HR image and an image to be composited which is generated from the LR or HR images and has a lower resolution than the HR image, such that the proportion of the HR image becomes smaller as the correlation of the area decreases; and an image compositing unit that composites the HR image and the image to be composited according to the ratio.
US09898801B1	Computing device independent and transferable game level design and other objects A system which employs a method of creating transferable map schemas, storing the map schemas to storage devices, receiving target device settings, re-sampling the map schemas to fit the target devices using the target device settings, delivering the re-sampled map schemas to the target devices is described. Thereby providing the innovation that map schemas may be accessed by more than one type of device, the method by which maps are scaled from a created map dimension with given details to either a larger map having the ability to be utilized on a more capable playing device or to a map or a smaller map having the ability to be utilized on a less capable device without losing the important game-specific required data is also described.
US09898795B2	Host-based heterogeneous multi-GPU assignment Examples of the disclosure assign a plurality of graphics processing units (GPUs) to a plurality of virtual machines (VMs) or processes. A composite score is generated for each GPU. The composite score represents the normalized processing capabilities of the multiple GPUs. Based on a comparison between the composite scores and allocated quantum corresponding to a proportional amount of GPU resources to which each VM is entitled, each VM is assigned to at least one of the GPUs. Graphics commands from the VMs are scheduled for execution by the assigned GPUs.
US09898793B2	Methods and arrangements involving substrate marking First and second patterns are formed on a substrate. A spatial offset between the patterns is determined, and stored for later use in authenticating the substrate. (One or both of the patterns may convey steganographic information. One pattern may be printed, while the other may be embossed.) A smartphone can sense these patterns, determine the spatial offset, and check whether the determined offset matches the earlier-stored offset, to judge whether the substrate is authentic. Another arrangement effects serialization of product packaging by use of paired patterns (at least one of which is typically a watermark pattern) applied in a manner causing a spatial offset between the patterns to progressively vary along a length of a printed web. Still other arrangements involve substrates conveying patterns that degrade over time, e.g., indicating freshness or pressurization condition. A great variety of other features and arrangements are also detailed.
US09898789B2	Method and a system for providing hosted services based on a generalized model of a health/wellness program One embodiment of the present invention provides a system for creating a health/wellness program on a generic health/wellness platform. During operation, the system receives, at the generic health/wellness platform, a set of definitions for the health/wellness program, constructs a program model for the health/wellness program, generates a program instance to be executed on the generic health/wellness platform, and associates the program instance to a number of health/wellness modules provided by the health/wellness platform.
US09898781B1	System and method for issuing, circulating and trading financial instruments with smart features A system and method for issuing, circulating and trading financial instruments with smart features is disclosed. In one particular exemplary embodiment, a financial instrument having smart features may comprise a document portion and a token device attached to or embedded in the document portion. The token device may comprise a storage device and a communication interface, wherein the token device is configured to provide a unique address for the financial instrument, the unique address including a device identifier that matches at least in part the document portion and a network address that changes based on a network location of the financial instrument and to communicate securely with an external entity at least to report an identity or a status of the financial instrument.
US09898769B2	Data processing systems and methods for operationalizing privacy compliance via integrated mobile applications Data processing systems and methods for receiving data regarding a plurality of data privacy campaigns and for using that data to modify stored data associated with the data privacy campaign. In various embodiments, the system may be adapted to: (1) display one or more visual summaries of one or more data flow diagrams that visually depicts key features of the data flow, such as whether data is confidential and/or encrypted; (2) automatically assess and display a relative risk associated with each campaign; and (3) automatically set, monitor, and facilitate the timely completion of an audit schedule for each campaign. In some embodiments, the system is configured to provide a mobile application via which a user may view information related to the privacy campaign, modify that data, etc.
US09898768B2	System and method for preventing, responding to, or discouraging predatory and uncompetitive sales practices A method and system for identifying and discouraging predatory and uncompetitive sales practices includes identifying at least one base cost for at least one product, determining at least one current cost for the at least one product from at least one retailer displaying or selling products and services through online or mobile channels, and determining if the at least one product sold by the at least one retailer displaying or selling products and services through online or mobile channels is a loss-leader based at least partially on the at least one base cost and the at least one current cost. At least one of the at least one product may be automatically purchased from the at least one retailer displaying or selling products and services through online or mobile channels if the at least one product sold by the at least one retailer is determined to be a loss-leader. A system for implementing the aforementioned method includes appropriately communicatively connected hardware components.
US09898767B2	Transaction facilitating marketplace platform A platform facilitates buyers, sellers, and third parties in obtaining information related to each other's transaction histories, such as a supplier's shipment history, the types of materials typically shipped, a supplier's customers, a supplier's expertise, what materials and how much a buyer purchases, buyer and shipper reliability, similarity between buyers, similarity between suppliers, and the like. The platform aggregates data from a variety of sources, including, without limitation, customs data associated with actual import/export transactions, non-public shipper records, and facilitates the generation of reports as to the quality of buyers and suppliers, the reports relating to a variety of parameters that are associated with buyer and supplier quality.
US09898762B2	Managing bids in a real-time auction for advertisements A method and system conduct an auction for advertising across multiple markets. A first market conducts a first auction for a first advertising impression. A first bid is selected as the auction winner and a ratio is computed as the first bid plus a spread to the second highest bid. The price to be paid is the lower of the first bid or the first bid multiplied by the ratio. The first bid, second bid, and spread are transmitted to a second market for a second advertising impression auction. The second market respects the rules of the first market's auction where such that if the first bid is selected as the winner, a ratio is computed as the first bid plus the spread to the next highest bid. The price to be paid for the second impression is the first bid multiplied by the new ratio.
US09898759B2	Methods and systems for collecting driving information and classifying drivers and self-driving systems Systems and methods for efficiently addressing technical and privacy/authorization obstacles associated with tracking of individuals in a vehicle, and enabling route-based analysis to determine driving behavior, socio-demographics, future profitability, and interests of individuals or self-driving systems. Driving information is collected using a device associated with a driver and a vehicle or using data collected by systems of self-driving vehicles. The frequency and methods used for the collection of driving information can be modified based on location and movement of the device and based on previous classification of the driver or self-driving system, thereby enabling efficient use of bandwidth and battery and increasing accuracy of the classification. The driving information is encoded and transmitted to a server, where future typical route segments that the driver is likely to travel are predicted, and the driver, or the self-driving system, is classified into one or more groups based on the encoded driving information.
US09898756B2	Method and apparatus for displaying ads directed to personas having associated characteristics A system and method for directing self-targeted advertising to users who are interested in receiving it. A user creates or adopts one or more personas that define a number of characteristics that the user has or wants to be associated with. The characteristics of the personas can be used by advertisers to define members of a target audience. Each persona included in a target audience has an address or identifier to which ads are sent. In one embodiment, users are shown a user interface screen with icons representing a number of brands. The user provides input that indicates whether they have different opinions of the brands. Based on the input received, an estimate is made of the likelihood that the user has a number of characteristics. The user can arrange the icons representing the brands on the user interface screen to indicate if the user likes or dislikes the brand.
US09898751B1	Direct purchase of merchandise This disclosure describes systems and methods related to providing direct purchase of merchandise from an electronic communication and subsequent delivery of the purchased merchandise. A direct merchandise purchase system may generate an electronic communication associated with an offer for merchandise for a user. The user may be able to directly purchase merchandise from the electronic communication which may then be delivered accordingly.
US09898750B2	Platform for distribution of content to user application programs and analysis of corresponding user response data A processing platform is configured for distribution of content to user application programs over a network and analysis of corresponding user response data received over the network. The user application programs are provided by respective ones of a plurality of application developers. The processing platform comprises at least one content repository configured to store the content, at least one content distribution and analysis application programming interface exposed to the network, one or more user web portals associated with said at least one content distribution and analysis application programming interface, one or more developer web portals associated with said at least one content distribution and analysis application programming interface, a plurality of user services accessible via the one or more user web portals, and a plurality of developer services accessible via the one or more developer web portals.
US09898748B1	Determining popular and trending content characteristics Features are disclosed for analyzing requests for network accessible content, including but not limited to web pages, to determine which topics and other characteristics are popular or are gaining in popularity (“trending”). Content items or sources may be profiled to determine characteristics that two or more content items or sources may have in common. Content requests from multiple client devices may be tracked and analyzed to determine the trending or popular characteristics. Data feeds or reports regarding the summarized content requests may be generated and distributed to content servers, advertisers, and other entities. The data feeds may be used to tailor content, such as by highlighting or featuring content associated with the most-requested content characteristics, or utilizing demographic data to tailor content for different users.
US09898744B2	Three-dimensional authentication and identification methods, devices, and systems In some embodiments, an apparatus includes a tag that may include an encapsulant and a plurality of three-dimensional objects randomly oriented within the encapsulant. Each three-dimensional object may include a plurality of characteristics defining at least one statistically unique signature. At least one of the characteristics may be dependent on the orientation of the object. In some instances, the plurality of three-dimensional objects may also be randomly distributed within the encapsulant, and at least one of the characteristics defining at least one statistically unique signature may be dependent on the distribution of the objects.
US09898739B2	System and method for ensuring safety of online transactions Online transaction security is improved by detecting a start of an online financial transaction between a user-controlled online transaction application and a remote payment service. A protected data input module, a protected environment module, and a safe data transfer module each provides a corresponding set of protection operations. A risk level of conducting the financial transaction is assessed based on a vulnerability assessment and on present condition of the local computing system. An initial degree of protection for each of the modules is set, and subsequently adjusted based on the risk level.
US09898735B2	Dynamic checkout button apparatuses, methods and systems The DYNAMIC CHECKOUT BUTTON APPARATUSES, METHODS AND SYSTEMS (“DCB”) transforms product page checkout request input and user identification input via DCB components such as offer/discount determination component and checkout button embedding component, into dynamic checkout button outputs.
US09898734B2	Method and system for terminal device-based communication between third-party applications and an electronic wallet A method for terminal device-based communications between a third-party application and an electronic wallet includes: the third-party application setting up a connection to an Internet service; the third-party application receiving a request and setting up a communication channel between the third party application and the electronic wallet within the terminal device via the On-Device API; verifying, by the electronic wallet, an access right of the request of the third party application; the third-party application forwarding the request to the electronic wallet if the access right is approved; the electronic wallet generating a corresponding response; forwarding the response via the On-Device API to the third party application, wherein the third party application forwards the response to the Internet service.
US09898732B2	Securely generating time and location bounded virtual transaction cards using mobile wallets without involving third parties or point of sale terminals Methods and systems may provide for generating a virtual transaction card based on a card value and one or more mobile usage constraints including a time bounded policy, wherein the virtual transaction card is invalid if the time bounded policy is not satisfied. Additionally, the virtual transaction card may be transmitted to a delegate mobile device. Other mobile usage constraints, such as location bounded policies and type of transaction policies may also be used.
US09898730B2	Credit card system and method A credit card system is provided which has the added feature of providing additional limited use credit card numbers and/or cards. These numbers and/or cards can be used for a single or limited use transaction, thereby reducing the potential for fraudulent reuse of these numbers and/or cards. The credit card system finds application to “card remote” transactions such as by phone or Internet. Additionally, when a single use or limited use credit card is used for “card present” transactions, so called “skimming” fraud is eliminated. Various other features enhance the credit card system which will allow secure trade without the use of elaborate encryption techniques. Methods for limiting, distributing and using a limited use card number, controlling the validity of a limited use credit card number, conducting a limited use credit card number transaction and providing remote access devices for accessing a limited use credit card number are also provided.
US09898726B2	Security system A terminal for use in a retail banking system comprises an interface for receiving multiple types of personal authentication elements. An authentication request for a user is associated with one or more of these types of element. The terminal also comprises a security module for providing access to a plurality of different access spaces of the system, each space comprises a different respective function or combination of functions of the system. For each access space, the security module provides a mapping between that access space and a respective one or more of the types of personal authentication element. Based on this mapping, the security module is thus configured to grant the user with access to one of the access spaces on condition of being mapped to the one or more types of personal authentication element associated with the authentication request for the user, and on condition those elements are verified.
US09898725B2	Passenger information module A method and system utilizes an interface for the blind and low vision passengers in a touch screen passenger information module (PIM). The PIM is enabled to operate in at least two modes. A low vision mode provides different user input framework on the touch screen as well as appropriate audio prompting. The interface enables a blind or low vision person to interact with the PIM easily, including using the PIM to pay for the fare. The low vision mode can be initiated by the passenger.
US09898724B2	Method and apparatus for determining item based on interaction environment A method and an apparatus for using a device to determine an item, such as, for example, a card based on an interaction environment, such as, for example, a settlement environment, are provided. The method by which a device determines a card to be used in a settlement includes: acquiring a card use history of a card, which is stored in the device; acquiring information which relates to a settlement environment of the device; determining a card to be used in the settlement, based on the acquired information relating to the settlement environment and the acquired card use history; and providing settlement information which relates to the determined card to a point of sale (POS) terminal.
US09898718B2	Providing a requisite level of service for an electronic meeting Providing a requisite level of service for an electronic meeting. An embodiment can include receiving a request to schedule a first electronic meeting in a time slot, identifying an electronic meeting system to host the first electronic meeting, identifying a second electronic meeting scheduled to be hosted by the electronic meeting system in the time slot, determining an estimate of resource usage within the electronic meeting system during the time slot at least based on the second electronic meeting being scheduled to be hosted by the electronic meeting system in the time slot, comparing the estimate of resource usage with a threshold value, responsive to determining that the estimate of resource usage exceeds the threshold value, providing the requisite level of service to the first electronic meeting in the time slot by reducing anticipated resource usage of the electronic meeting system by the second electronic meeting.
US09898713B1	Methods systems and computer program products for monitoring inventory and prices Methods, systems, and computer program products for an inventory monitor are disclosed. In one or more embodiments, the disclosed method involves predicting a number of inventory items on a future date based at least in part upon a number of the inventory items on the current date and a rate of consumption of the inventory items, which is determined based on prior sales of the inventory items. The method also involves determining a price trend of the inventory items. In addition, the method involves determining whether to purchase the inventory items on the current date based at least in part upon the predicted number of inventory items, a rate of consumption of the inventory items, and a price trend of the inventory items. Further, the method involves displaying to the user an indicator of whether to purchase the inventory items on the current date or on a later date.
US09898709B2	Methods and apparatus for analysis of structured and unstructured data for governance, risk, and compliance Methods and apparatuses for organizations to monitor, analyze and respond to unstructured and structured data that is related to their Governance, Risk, and Compliance (GRC) programs. Embodiments of the invention generated mapped Risk Control Matrices (RCMs) and/or insights for improving the GRC process from unstructured and structured data. Natural language processing is employed to process the aggregated data from various data sources to create attributes and contributors. The attributes and weighted contributors are processed to form mapped RCMs and/or GRC-related insights.
US09898704B2	Forecast monitor to track transport supply in development environments Systems and method for forecasting release times in a multisystem software development environment are disclosed. A forecast engine may analyze the system specific data for multiple systems in a particular transport chain of systems in the development environment to determine when object code should be released from a source system to reach a target system in time to be included in an event, such as a software build or quality assurance test. The system specific data may include event schedules for each system in the transport chain. By analyzing the system specific data and the transport chain, the forecast engine can generate a time by which object code needs to be released to traverse the transport chain so that it is available to the target system for a particular scheduled event.
US09898701B2	Systems and methods for the determining annotator performance in the distributed annotation of source data Systems and methods for determining annotator performance in the distributed annotation of source data in accordance embodiments of the invention are disclosed. In one embodiment of the invention, a method for clustering annotators includes obtaining a set of source data, determining a training data set representative of the set of source data, obtaining sets of annotations from a set of annotators for a portion of the training data set, for each annotator determining annotator recall metadata based on the set of annotations provided by the annotator for the training data set and determining annotator precision metadata based on the set of annotations provided by the annotator for the training data set, and grouping the annotators into annotator groups based on the annotator recall metadata and the annotator precision metadata.
US09898697B2	Support device for band-shaped sheet, and method for managing band-shaped sheet A support device, which supports a belt-shaped sheet wound around a hollow cylindrical shaft core so as to feed the belt-shaped sheet, includes a support shaft that is insertable into a hollow part of the shaft core, a frame that supports the support shaft, an antenna surface perpendicular to an axis line of the support shaft, and a loop antenna provided to the antenna surface. The shaft core includes a non-contact data carrier capable of at least one of storing and transmitting predetermined data. The loop antenna includes a loop unit coiled to define a loop surrounding the axis line. When the shaft core is seen through the loop antenna along the axis line, the loop unit is disposed in the vicinity of the shaft core.
US09898695B2	Security token and authentication system Techniques are provided for entering a secret into a security token using an embedded tactile sensing user interface with the purpose of verifying the secret against a stored representation of the same secret. In particular, an embodiment of the security token according to the invention comprises a tactile sensing user interface being arranged to receive a user-encoded secret, a decoding unit being arranged to generate a decoded secret by decoding the user-encoded secret, a comparison unit being arranged to compare the decoded secret with a copy of the secret stored in the token in order to verify the authenticity of a user. Thereby, the security token provides on-card matching functionality.
US09898694B2	Tri-layer transaction cards and associated methods A transaction card having three layers, wherein the first layer is metal, the second layer is a polymer, and the third layer is a carbon-containing layer.
US09898690B2	Gesture control for printing presses A device controls at least one of a machine, a color measurement device or an inspection system of the graphic arts industry. The device contains a control console that has at least one screen for displaying at least one of machine information, color information or image information. The control console includes a plurality of sensors for detecting gestures of an operator who operates the machine, the color measurement device or the inspection system via the control console.
US09898688B2	Vision enhanced drones for precision farming Methods, apparatuses and systems may provide for a neural network that analyzes and classifies agricultural conditions based on depth data and color data recorded by one or more drones, and generates an annotated three dimensional (3D) map with the agricultural conditions. Additionally, an object recognition model may be trained for use by a drone controller to trigger drones to conduct a collection of depth data at an increased proximity to crop-related objects based on agricultural conditions.
US09898687B2	Technique for identifying association variables An apparatus determines patterns of occurrence of compound variables based on a set of mathematical interactions and patterns of occurrence of a set of biological variables. Then, the apparatus calculates statistical relationships corresponding to a pattern of occurrence of a trait in a group of life forms and the patterns of occurrence of the compound variables. Moreover, the apparatus determines numbers of occurrences of biological variables that were used to determine compound variables in at least a statistically significant subset of the compound variables, and determines numbers of different mathematical interactions that were used to determine the compound variables in the subset of the compound variables for the biological variables that are associated with the corresponding numbers of occurrences. Next, the apparatus identifies one or more of the biological variables as one or more association variables based on the numbers of occurrences and the numbers of different mathematical interactions.
US09898685B2	Method and apparatus for analyzing media content Aspects of the subject disclosure may include, for example, a method for determining a first set of features in first images of first media content, generating a similarity score by processing the first set of features with a favorability model derived by identifying generative features and discriminative features of second media content that is favored by a viewer, and providing the similarity score to a network for predicting a response by the viewer to the first media content. Other embodiments are disclosed.
US09898681B2	Apparatus and method for detecting object using multi-directional integral image An apparatus and method for detecting an object using a multi-directional integral image are disclosed. The apparatus includes an area segmentation unit, an integral image calculation unit, and an object detection unit. The area segmentation unit places windows having a size of xy on a full image having wh pixels so that they overlap each other at their edges, thereby segmenting the full image into a single area, a double area and a quadruple area. The integral image calculation unit calculates a single directional integral image for the single area, and calculates multi-directional integral images for the double and quadruple areas. The object detection unit detects an object for the full image using the single directional integral image and the multi-directional integral images.
US09898678B2	Compound object separation Representations of an object in an image generated by an imaging apparatus can comprise two or more separate sub-objects, producing a compound object. Compound objects can negatively affect the quality of object visualization and threat identification performance. As provided herein, a compound object can be separated into sub-objects. Three-dimensional image data of a potential compound object is projected into a two-dimensional manifold projection, and segmentation is performed on the two-dimensional manifold projection of the compound object to identify sub-objects. Once sub-objects are identified, the two-dimensional, segmented manifold projection is projected into three-dimensional space. A three-dimensional segmentation may then be performed to identify additional sub-objects of the compound object that were not identified by the two-dimensional segmentation.
US09898675B2	User movement tracking feedback to improve tracking Technology is presented for providing feedback to a user on an ability of an executing application to track user action for control of the executing application on a computer system. A capture system detects a user in a capture area. Factors in the capture area and the user's actions can adversely affect the ability of the application to determine if a user movement is a gesture which is a control or instruction to the application. One example of such factors is a user being out of the field of view of the capture system. Some other factor examples include lighting conditions and obstructions in the capture area. Responsive to a user tracking criteria not being satisfied, feedback is output to the user. In some embodiments, the feedback is provided within the context of an executing application.
US09898672B2	System and method of detection, tracking and identification of evolutionary adaptation of vehicle lamp A system of detection, tracking and identification of an evolutionary adaptation of a vehicle lamp includes an image capture device and a processor. The image capture device captures an image of a vehicle. The processor processes the image of the vehicle to generate a detection result of the vehicle lamp, analyzes and integrates vehicle lamp dynamic motion information and vehicle lamp multiple scale variation information based on the detection result, and then tracks the position of the vehicle lamp by applying a multiple scale vehicle lamp measurement model.
US09898669B2	Traveling road surface detection device and traveling road surface detection method A traveling road surface detection device is provided. The traveling road surface device determines a road surface area, a stereoscopic object existence area where a stereoscopic object exists, and an indeterminate area other than the road surface area and the stereoscopic object existence area based on a parallax image of the surroundings of the vehicle, detects a traveling road surface that sequentially extends in a direction away from the vehicle based on the captured image, estimates a height position of a road surface within the road surface area based on the parallax information, and specifies an area including a parallax point with a height equal to or greater than a predetermined threshold value from the height position of the road surface in the indeterminate area as a parallax height existence area based on the estimated height position of the road surface and the parallax information.
US09898668B2	System and method of object detection A system and method of object detection are disclosed. In a particular implementation, a method of processing an image includes receiving, at a processor, image data associated with an image of a scene. The scene includes a road region. The method further includes detecting the road region based on the image data and determining a subset of the image data. The subset excludes at least a portion of the image data corresponding to the road region. The method further includes performing an object detection operation on the subset of the image data to detect an object. The object detection operation performed on the subset of the image data is exclusive of the at least a portion of the image data corresponding to the road region.
US09898667B2	Accident information management appratus, vehicle including the same, and accident information management method An accident information management apparatus for acquiring accident associated information such as images stored in a black box (i.e., black box images) from a peripheral vehicle through direct communication between vehicles when an accident such as a traffic accident occurs, a vehicle including the accident information management apparatus, and a method for managing accident information are disclosed. The vehicle includes an antenna array having a plurality of antenna elements configured to transmit and receive a signal; and a beamformer configured to adjust a phase of the signal transmitted from the antenna elements so as to form a beam pattern focused in a specific direction; and a controller configured to focus the beam pattern onto a peripheral vehicle so as to control a communication unit to transmit a request signal of accident associated information. The antenna array and the beamformer are contained in the communication unit.
US09898663B2	Collaboration facilitator for wearable devices A wearable apparatus is provided for capturing and processing images from an environment of a user. In one implementation, a system for facilitating collaboration between individuals includes a transceiver and at least one processing device. The at least one processing device is programmed to obtain and analyze one or more images captured by an image sensor included in a wearable apparatus. The at least one processing device is further programmed to detect, by the analysis, a visual trigger in an environment of a wearer of the wearable apparatus. The visual trigger may be associated with a collaborative action to be taken. The at least one processing device may be further programmed to use the transceiver to transmit an indicator relating to the visual trigger associated with the collaborative action to be taken.
US09898662B2	Information processing apparatus, information processing method, and information processing system An information processing apparatus includes an acquiring unit that acquires a plurality of kinds of medical apparatus information, which are information acquired from a plurality of medical apparatuses, a generating unit that generates information for presentation including at least a part of the plurality of kinds of medical apparatus information acquired by the acquiring unit, and a presenting unit that outputs the generated information for presentation to an image display apparatus that displays an image. The generating unit generates the information for presentation including at least the medical apparatus information acquired by the medical apparatus, visual recognition of a display unit of which by a user of the image display apparatus is difficult.
US09898660B2	Object detection system An airborne mine countermeasure system includes a processor coupled to a memory having stored therein software instructions that, when executed by the processor, cause the processor to perform a series of image processing operations. The operations include obtaining input image data from an external image sensor, and extracting a sequence of 2-D slices from the input image data. The operations also include performing a 3-D connected region analysis on the sequence of 2-D slices, and extracting 3-D invariant features in the image data. The operations further include performing coarse filtering, performing fine recognition and outputting an image processing result having an indication of the presence of any mines within the input image data.
US09898659B2	System and method for remote medical diagnosis A system for use in remote medical diagnosis of a biological subject, the system including one or more electronic processing devices that receive image data indicative of at least one image of part of the subject's eye from a client device via a communications network, review subject data indicative of at least one subject attribute, select at least one analysis process using results of the review of the subject data, use the analysis process to quantify at least one feature in the image data and generate an indicator value indicative of the quantified at least one feature, the indicator value being used in the assessment of a condition status of at least one condition.
US09898649B2	Face authentication method and device The disclosure discloses a face authentication method and device. The face authentication method includes: acquiring multiple face training images; extracting Gabor features of the multiple face training images; extracting Pattern of Oriented Edge Magnitude (POEM) features of the multiple face training images; fusing the Gabor features of the multiple face training image and the POEM features of the multiple face training image to acquire positive samples and negative samples of the multiple face training images; training the positive samples and negative samples of the multiple face training images to obtain training results by an AdaBoost algorithm; and performing face authentication by the training results. By the disclosure, the problem of difficulty of a face authentication method in the related technology in combination of efficiency and recognition rate is solved, and the effects of improving feature extraction efficiency of face recognition and increasing the face recognition rate are further achieved.
US09898648B2	Face recognition method A face recognition method of the present disclosure includes configuring aggregations of feature data that include a plurality of feature data of faces and match to a plurality of personnel data; extracting from an input image a plurality of input feature data that correspond to the feature data and that is equal to or more than a critical value; comparing an aggregation of input feature data that includes the input feature data with each of the pre-stored aggregations of feature data, and selecting from the aggregations of feature data an aggregation of feature data having the greatest similarity with the aggregation of the input feature data; and identifying a person on the image based on personnel data that matches the aggregation of feature data having the greatest similarity.
US09898647B2	Systems and methods for detecting, identifying and tracking objects and events over time A system for detecting, identifying and tracking objects of interest over time is configured to derive object identification data from images captured from one or more image capture devices. In some embodiments of the system, the one or more image capture devices perform a first object detection and identification analysis on images captured by the one or more image capture devices. The system may then transmit the captured images to a server that performs a second object detection and identification analysis on the captures images. In various embodiments, the second analysis is more detailed than the first analysis. The system may also be configured to compile data from the one or more image capture devices and server into a timeline of object of interest detection and identification data over time.
US09898644B2	Touch panel with fingerprint identification function A touch panel with fingerprint identification function includes a glass substrate, a fingerprint identification device, a packaging layer, an optical adhesive layer and a sealing layer. The glass substrate has a visible section, a non-visible section and a first plane face. The non-visible section is formed with a recess having a bottom side. The fingerprint identification device is disposed in the recess, having a substrate having a first side. A silicon substrate is disposed on the first side and electrically connected to the substrate via a wire. Multiple fingerprint identification chips are disposed on one side of the silicon substrate. The packaging layer encloses the wire, the substrate and an exposed section of the silicon substrate. The optical adhesive layer is disposed between the fingerprint identification device and the bottom side of the recess. The sealing layer seals the fingerprint identification device in the recess of the glass substrate.
US09898641B2	Finger biometric sensor including drive signal level updating and related methods A finger biometric sensor may include an array of finger biometric sensing pixels and processing circuitry coupled thereto. The processing circuitry may be capable of acquiring initial data from the array based upon an initial drive signal level and with a finger positioned adjacent the array, and determining an updated drive signal level based upon the initial data. The processing circuitry may also be capable of acquiring finger biometric data from the array of finger biometric sensing pixels based upon the updated drive signal level and with the finger positioned adjacent the array.
US09898630B2	Interrogation device, system including interrogation device, and program A controller in an interrogation device performs, for each RF tag passing through an interrogation zone that is defined near an interrogation unit, an integration process of integrating a strength of a reception signal from the RF tag received by the interrogation unit. The integration process includes weighting of an integral value of the strength of the reception signal in a manner to cause an integrate value calculated for each reception signal to be larger than an integral value calculated for a preceding reception signal. When an RF tag moves to a predetermined position in the interrogation zone, the controller transmits, to a host device, an identifier of an RF tag having a maximum integral value selected from the integrated value calculated for each RF tag.
US09898629B1	Dynamic quick response code branding In an approach to managing a quick response code branding device and management of a quick response code branding device, one or more computer processors receive one or more quick response code configuration parameters. The one or more computer processors determine one or more program instructions corresponding to the one or more quick response code configuration parameters based on one or more task-specific factors. The one or more computer processors send the one or more program instructions to a quick response code branding device. The one or more computer processors receive quick response code branding device status data. The one or more computer processors determine whether the quick response code branding device status data meets the one or more quick response code configuration parameters.
US09898624B2	Multi-core processor based key protection method and system A multi-core processor based key protection method and system is described. An Operating System (OS) supporting Symmetric Multi-Processing (SMP) is set up on a multi-core processor. One core of the multi-core processor is configured as a cryptographic operation core, which is prohibited from running other processes of the OS and dedicated to perform a public-key cryptographic operation. The private key and an intermediate variable in a process of the public-key cryptographic operation are stored in a cache exclusively occupied by the cryptographic operation core.
US09898621B2	Automatic application dependent anonymization Disclosed are various embodiments for facilitating the anonymization of unique entity information. A service may send anonymized responses to requests for data from multiple requestors, the data being associated with entity identifiers. The anonymized responses may comprise the data requested in association with anonymous entity identifiers as opposed to the entity identifiers.
US09898614B1	Implicit prioritization to rate-limit secondary index creation for an online table A data storage system may implement implicit prioritization to rate-limit secondary index creation for an online table. A secondary index may be generated for a table stored in a data store. The table may be incrementally indexed, performing multiple indexing operations to populate the secondary index. Prior to performing an indexing operation, an evaluation of a capacity limitation for performing indexing operations may be made with respect to capacity to process access requests at the data store. If a determination is made that performance of the indexing operation exceeds the capacity limitation, then the indexing operation may be throttled. If a determination is made that performance of the indexing operation does not exceed the capacity limitation, then the indexing operation may be performed.
US09898613B1	Crowdsourcing privacy settings The disclosed subject matter relates to a computer-implemented method including steps for aggregating privacy setting information for one or more networking associates, generating data based on the aggregated privacy setting information and providing a privacy setting recommendation for display to a user based on the data. Systems and computer-readable media are also provided.
US09898612B2	Multi-party encryption cube processing apparatuses, methods and systems Computer-implemented systems and methods are disclosed herein for use within secure multi-party computation. A system and method are used for storing an operation preference and a cryptographic preference. A data set is stored based on the operation preference and the cryptographic preference. A determination is made that processing the query involves performing an allowable operation on the data set based on the operation preference.
US09898610B1	System and method for concealing sensitive data on a computing device A computer-implemented method may conceal sensitive data displayed within a viewport of a display of a client computing device, such as sensitive data relating to auto, home, life, or renters insurance, banking, and/or vehicle loans. In one aspect, the method may receive a user credential authenticating a user of the computing device and determine that a sensitive data flag has been triggered. The sensitive data flag may indicate that sensitive user data is displayed within a viewport of the computing device. The method may also initiate a biometric detection service, application, and/or functionality in response to determining that the sensitive data flag has been triggered and detect a first biometric identifier belonging to the user of the computing device. The method may further detect a second biometric identifier belonging to someone other than the user, and obscure the sensitive user data displayed within the viewport of the computing device.
US09898609B2	Trusted boot of a virtual machine A method, system and program product for performing a trusted boot of a virtual machine comprises the steps of executing, in turn, a series of components of the trusted boot, performing a function on each component prior to the execution of the respective component, storing the output of the functions in a virtual trusted platform module, detecting that the virtual trusted platform module has not responded to the storing of the output of a function in the virtual trusted platform module, and generating a request that the virtual trusted platform module be disabled.
US09898601B2	Allocation of shared system resources Techniques are described for allocating resources to a task from a shared hardware structure. A plurality of tasks may execute on a processor, wherein the processor may include one or more processing cores and each task may include a plurality of computer executable instructions. In accordance with one technique for allocating resources to a task from a shared hardware structure amongst multiple tasks, aspects of the disclosure describe assigning a first identifier to a first task from the plurality of tasks, associating a portion of the shared hardware resource with the first identifier, and restricting access and/or observability for computer executable instructions executed from any other task than the first task to the portion of the hardware resource associated with the first identifier.
US09898600B2	Method and apparatus for managing application data of portable terminal A method for managing application data of a portable terminal according to the present invention comprises the steps of: allocating a plurality of data areas required for a data management policy for an application program; when the application program is executed, permitting connection to a specific data area of the plurality of data areas allocated for the application program on the basis of the data management policy; and executing the application program while performing the permitted connection to the specific data area.
US09898599B2	Implementing extent granularity authorization and deauthorization processing in CAPI adapters A method, system and computer program product are provided for implementing block extent granularity authorization and deauthorization processing for a Coherent Accelerator Processor Interface (CAPI) adapter. The Application Client, such as an Application Child Client sends a Delete Authorizations command to the CAPI Adapter via the Client CAPI Server Registers assigned to the specific Application Client. The CAPI Adapter deletes the Authorizations in all Lists in the Delete Authorizations command.
US09898595B2	Monetized online content systems and methods and computer-readable media for processing requests for the same One aspect of the invention provides a computer system having processing and memory means operable to provide a monetized online content system. The computer system is coupled to one or more resource modules each having data in the memory means and includes: an interceptor module configured to receive a request from a client for one or more resources available from one or more resource modules, refer the request to one or more of the resource modules configured to fulfill the request, receive one or more responses from one or more of the resource modules, at least one of said one or more responses having one or more events associated therewith, and transform the one or more responses by removing the one or more events associated with the one or more responses prior to presentation of the one or more responses to the client.
US09898592B2	Application marketplace administrative controls The subject matter of this specification can be embodied in, among other things, a method that includes receiving, by one or more servers associated with an application marketplace, a policy that includes data that identifies one or more users, and a restricted permission. A request is received, by the servers associated with the application marketplace, to access one or more applications that are distributed through the application marketplace, wherein the request includes data that identifies a particular one of the users. One or more of the applications that are associated with the restricted permission are identified by the servers associated with the application marketplace, and access by the particular user to the applications that are associated with the restricted permission is restricted by the servers associated with the application marketplace.
US09898591B2	Authentication method for authenticating a first party to a second party An authentication method authenticates a first party to a second party, where an operation is performed on condition that the authentication succeeds. If the first party is not authenticated, then if the first party qualifies for a sub-authorization, the operation is still performed. Further, a device that includes a first memory area holding a comparison measure, which is associated with time, and which is also used in said authentication procedure, a second memory area holding a limited list of other parties which have been involved in an authentication procedure with the device, and a third memory area, holding compliance certificates concerning parties of said list.
US09898589B2	Content sharing and storage of a plurality of remotely connected computing devices in physical or virtualized space An information handling system includes a processor that executes instructions for a content sharing system having mixed operating system capabilities. The processor detects prepaired wireless connectivity remotely connected computing devices, and auto-initiates navigation accessibility within authorized remotely connected computing devices via the content sharing system. The information handling system also includes a display for a content sharing system desktop that includes representation of file structures corresponding to a plurality of remotely connected computing devices.
US09898586B2	Medical reporting system and method Systems and methods for use in providing input relating to medical data are provided. A method includes receiving a partial textual input relating to medical data. The method further includes determining one or more suggested input strings associated with the partial textual input. Determining the suggested input string(s) includes: (1) for each of a plurality of reference input strings contained within one or more of a plurality of reference files within a database, identifying a frequency with which the reference input string appears in the plurality of reference files, and (2) determining the suggested input string(s) further includes determining the suggested input string(s) from among the plurality of reference input strings based on the frequencies with which the reference input strings appear in the plurality of reference files. The method further includes providing the suggested input string(s) to the user as suggestions for completing the partial textual input.
US09898585B2	Method and system for insulin management A method of administering insulin includes receiving blood glucose measurements of a patient at a data processing device from a glucometer. Each blood glucose measurement is separated by a time interval and includes a blood glucose time associated with a time of measuring the blood glucose measurement. The method also includes receiving patient information at the data processing device and selecting a subcutaneous insulin treatment for tube-fed patients from a collection of subcutaneous insulin treatments. The selection is based on the blood glucose measurements and the patient information. The subcutaneous insulin treatment program for tube-fed patients determines recommended insulin doses based on the blood glucose times. The method also includes executing, using the data processing device, the selected subcutaneous insulin treatment.
US09898584B2	System and method for providing a common medical device architecture Systems, methods, and computer readable storage medium for providing a genericized medical device architecture common to a plurality of medical devices are disclosed. The architecture may comprise at least one diagnostics module associated with at least one of the plurality of medical devices, wherein the at least one diagnostics module is configured to monitor an operational status of the at least one medical device. At least one hardware abstraction layer may be associated with at least one of the plurality of medical devices, and may be configured to provide abstracted access to hardware of the at least one medical device.
US09898581B2	Health care eligibility verification and settlement systems and methods Devices, systems, and methods for processing healthcare and financial transactions are provided. A point-of-care terminal for processing a healthcare transaction by a healthcare provider includes a reader configured to read information from a healthcare eligibility and settlement presentation instrument associated with a patient, and a processor configured to process a healthcare transaction based on the information, wherein the healthcare transaction includes at least one of a healthcare eligibility verification transaction and a healthcare settlement transaction.
US09898566B2	Method for automated assistance to design nonlinear analog circuit with transient solver A method is provided for providing an automated assistance to design an analog non linear circuit under transient conditions, and to a corresponding system. The method enables the circuit designer to consider with simulation the time reactive effects of generally nonlinear components, while keeping the significant and intuitive qualities of an analysis view design tool like the CAIRO+/CHAMS environment. The method includes at least a transient instant solving procedure producing a numerical simulation that uses a given set of sizes and biases to provide a set of local behavior parameters in at least one node at current time. This transient instant solving procedure includes an incremental iteration under transient conditions of an evaluation in an analysis view of a dependency graph of the functional structure of the circuit. An optional transient analysis performs a numerical simulation to provide a time dependent behavior simulation of the circuit, and a performance evaluation.
US09898564B2	SSTA with non-gaussian variation to second order for multi-phase sequential circuit with interconnect effect In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.
US09898560B2	System and method for flexible and efficient simulation of varying fracture density in a reservoir simulator Simulation system and method for a reservoir represented by a model having a plurality of matrix nodes, a plurality of fracture nodes, a fracture zone and a fracture-free zone are described. One embodiment includes computer-implemented steps of, for each of a plurality of matrix nodes in interconnected zones, characterizing the matrix nodes as dual matrix nodes or non-dual matrix nodes. Dual matrix nodes may be treated as a block and eliminated, after which the coefficient matrix and RHS vector for the model are updated. In-fill patterns between and among fracture nodes and non-dual matrix nodes resulting from the elimination are determined. For non-dual matrix nodes, the nodes are merged to a fracture grid, after which the coefficient matrix and RHS vector for the model are updated accordingly. The resultant linear system is linearly solved, and backsolving is performed for any eliminated dual matrix nodes.
US09898555B2	Systems and methods to automatically suggest elements for a content aggregation system According to some embodiments, a suggestion platform associated with a content aggregation system may access a plurality of data context trigger criteria associated with potential business information content elements. Each data context trigger criteria may include, for example: (i) a data locator associated with a business information data structure, (ii) an operator, and (iii) a threshold. For each data context trigger criteria, it may be automatically determined if a value in the business information data structure satisfies the data context trigger criteria based on the operator and the threshold. When a data context trigger criteria is satisfied, it may be automatically suggested to a user that the potential business information content element associated with that data context trigger criteria be added to a user display of the content aggregation system.
US09898554B2	Implicit question query identification Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for identifying implicit question queries. In one aspect, a method includes receiving a query in unstructured form, comparing terms of the query to query templates, determining, based on the comparison, a match of the query terms to a first query template, wherein the first query template is not determined to be indicative of a question query, determining, based on the first query template, a second query template, and determining that the query is an implicit question query in response to the second query template being indicative of a question queries.
US09898551B2	Fast row to page lookup of data table using capacity index The subject matter disclosed herein provides methods for determining the page on which a desired row position value is located. A table having a plurality of rows can be accessed. The rows can be distributed across one or more pages in an in-memory database. Each row can be associated with a unique row position value. Each page can be associated with a capacity that is representative of an amount of data stored on the page. A capacity index having a plurality of entries can be created to record changes in capacity between pages. Neighboring entries in the capacity index can have a different capacity. Each entry in the capacity index can correspond to a page. A page directory can be created based on the capacity index. The page directory can indicate all possible row position values associated with each page. Related apparatus, systems, techniques, and articles are also described.
US09898548B1	Image conversion of text-based images Conversion of text-based images to vector graphics (VG) is disclosed. The text-based images may include images of equations, custom typefaces, or other types of text that may not be included in a font selection of an optical character recognition (OCR) device or an application stored on a viewing device. A textual image may be converted from a raster graphics (RG) image to a VG image, which may enable resizing and alignment of the VG image with body text. In some aspects, the server may determine a body size of a reference character in the VG image. The server may determine a baseline of the VG image that may be used to align the image with the body text.
US09898547B1	Online information system with backward continuous scrolling A web page may be rendered for display on a client device. The rendered web page may be based on a first document. It may be determined that a first scroll position of the rendered web page is above a first threshold scroll position. Possibly responsive to determining that the first scroll position of the rendered web page is above the first threshold scroll position, a second document may be requested and received from a server device. The web page may be re-rendered for display on the client device. The re-rendered web page may include content from the second document followed by content from the first document.
US09898544B2	Guided web navigation tool Using a processor, a first N×N matrix is determined based on a plurality of N webpages. Each cell of the first matrix corresponds to a pair of webpages. The first matrix is transformed into a second N×N matrix with each cell being in one of N partitions, the values of the cells within each partition being substantially equal. A sequence of M webpages is determined based on the second matrix and keyword(s) inputted by a user. The sequence is arranged in order from a first webpage to an Mth webpage (M
US09898542B2	Narration of network content A process is directed to the generation, maintenance, and provision of narrations for requested network content. A client computing device transmits a narration of a network resource, such as a web page, to a network computing provider. The narration can be separated into portions, each portion corresponding to a portion of the network resource. A second client computing device can request the network resource and the narration. The network computing provider can determine whether there has been any change in the requested network resource since the narration was received, and can modify the narration provided to the second client computing device accordingly. The second client computing device can playback appropriate portions of the narration while still being capable of regular interaction with the requested network resource.
US09898537B2	Systems, methods and computer program products for information management across disparate information systems An information integration system may include a set of integration services embodied on one or more server machines in a computing environment. The set of integration services may include connectors communicatively connected to disparate information systems. The connectors are configured for integrating data utilizing a common model comprising a content management interoperability services data model, common property definitions, and a common security model particularly defined for use by the set of integration services. Responsive to a user query to search disparate information systems or a subset thereof, an application may communicate metadata of interest contained in the user query to a search engine which locates, via a unified index, requested data from the disparate information systems or a subset thereof. The search engine returns search results referencing the requested data to the application which interprets the search results and displays a visualization thereof on a client device.
US09898534B2	Automatically adapting a user interface A portal server comprises memory, a profile manager, a profile selector, and a profile initiator. The profile manager is configured to manage a plurality of profile records in a profile database. The profile selector is configured to select at least one of the plurality of profile records based on context data collected at a client and context data collected at the portal server. The collected context data corresponds to particular user interaction activity with the portal server. The profile initiator is configured to adapt a user interface based on the profile selected by the profile selector.
US09898533B2	Augmenting search results Results of a search on one body of data are enhanced by performing the same search, or a related search, on another body of data. A first body of data is pages (or other content) on a web site, and a second body of data is pages (or other content) on another web site. When a user enters a query to perform a site-specific search on the first web site, that web site performs a related search on the second web site. When results are obtained from the second web site, it is determined whether the first web site has any pages that correspond to the received results. The first web site then uses the corresponding pages in the results that it provides to the user.
US09898529B2	Augmenting semantic models based on morphological rules A computer processor determines a root of a first element of a semantic model, in which a first relationship of the first element to a second element of the semantic model, is unknown. The computer processor generates a search token, based on applying morphological rules to the root of the first element and appending a preposition. The computer processor determines one or more regular expressions by applying the search token to search a source of unstructured data. The one or more regular expressions are in a form of a triple, having a subject, a predicate, and an object, and the computer processor applies the predicate of the triple as the first relationship of the first element of the semantic model to a second element of the semantic model.
US09898527B2	Methods for retrieving information and devices thereof A method for retrieving information includes determining, by the information retrieval management computing device, when an identified subject of interest in a received query maps to one of one or more ontology entities. An identification is made, by the information retrieval management computing device, when the identified subject of interest is one of one or more existing subjects of interest when the identified subject of interest is determined to map to one of the ontology entities. One or more filters associated with the identified subject of interest are stored by the information retrieval management computing device. The one or more filters include: one or more new property conditions in the received query, one or more ontology property conditions associated with the mapped one of the ontology entities, and one or more existing property conditions associated with the one of the one or more existing subjects of interest when the identified subject of interest is identified as one of the existing subjects of interest; or the one or more new property conditions and the one or more ontology property conditions when the identified subject of interest is not identified as one of the existing subjects of interest. An updated query is automatically built based on the stored one or more filters by the information retrieval management computing device. One or more results are retrieved and provided, by the information retrieval management computing device, based on the automatically built updated query.
US09898526B2	Computer-implemented system and method for inclusion-based electronically stored information item cluster visual representation A computer-implemented system and method for inclusion-based electronically stored information item cluster visual representation is provided. A set of reference electronically stored information items is maintained. A subset of the electronically stored information items is selected from the set, each associated with a classification code, each of the classification codes associated with a visual representation different from the visual representations of the remaining classification codes. The subset is combined with a set of uncoded electronically stored information items, each associated with a visual representation different from the visual representations of the classification codes. The combined electronically stored information items are grouped into clusters. Each of the clusters is visually represented, including displaying the visual representation associated with the code of each of the reference electronically stored information items in that cluster and the visual representation associated with each of the uncoded electronically stored information item in that cluster.
US09898525B2	Information processing device which carries out risk analysis and risk analysis method An information processing device includes: a unit configured to compute a service influence degree for each risk factor with respect to each service, on the basis of information which indicates a relation between components which have the risk factors and other components which are influenced by the state of the components, information which denotes characteristics of the respective risk factors, and information which denotes a correspondence between the services and these components; and a unit configured to compute, on the basis of the computed service influence degrees, similarities between specific risk factors and other risk factors, and for generating and outputting a set of component identification information on the basis of the computed similarities.
US09898523B2	Tabular data parsing in document(s) One or more techniques and/or systems are provided for parsing tabular data of a document. That is, a document may comprise arbitrarily formatted content (e.g., an equipment inspection report generated by an engineer). Respective rows of the document may be clustered into one or more row clusters based upon row proximity and/or numeric content (e.g., rows having similar numeric content may comprise logically related information). One or more vertical clusters may be generated within respective row clusters based upon vertical overlap. In this way, row clusters and/or vertical clusters may be searched for one or more values that may be assigned to a search term. For example, a row cluster may comprise a search term “Average temp”. One or more vertical clusters within the row cluster may be searched for a word that matches a pattern criteria (e.g., a two digit number), which may be assigned to the search term.
US09898522B2	Distributed storage of aggregated data Techniques are described for managing aggregation of data in a distributed manner, such as for a particular client based on specified configuration information. The described techniques may include storing aggregated data values for an OLAP cube or other data structure in a distributed manner, such as in some situations in a distributed hash table. The aggregated data values to be stored may be generated in various manners, such as by performing multi-stage data manipulation operations—for example, a map-reduce architecture may be used, with a first stage involving the use of one or more specified map functions to be performed, and with at least a second stage involving the use of one or more specified reduce functions to be performed.
US09898521B2	Massively scalable object storage system Several different embodiments of a massively scalable object storage system are described. The object storage system is particularly useful for storage in a cloud computing installation whereby shared servers provide resources, software, and data to computers and other devices on demand. In several embodiments, the object storage system includes a ring implementation used to associate object storage commands with particular physical servers such that certain guarantees of consistency, availability, and performance can be met. In other embodiments, the object storage system includes a synchronization protocol used to order operations across a distributed system. In a third set of embodiments, the object storage system includes a metadata management system. In a fourth set of embodiments, the object storage system uses a structured information synchronization system. Features from each set of embodiments can be used to improve the performance and scalability of a cloud computing object storage system.
US09898514B2	System and method for aggregating query results in a fault-tolerant database management system A redundant array of independent nodes are networked together. Each node executes an instance of an application that provides object-based storage. Metadata objects are stored in a set of regions distributed among the nodes across the array. A given region is identified by hashing a metadata object attribute and extracting a given set of bits of a resulting hash value. A method of managing query results comprises: receiving, by a first node of the plurality of independent nodes from a client application, a request for a list of objects with a criterion; issuing by the first node a query to all the nodes based on the received request; processing the query by each node over the regions in the node using the metadata objects stored in the regions; aggregating and filtering by the first node results of the query from all the nodes; and returning by the first node the aggregated and filtered results to the client application.
US09898512B1	Factual query pattern learning Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for providing a statement that references a particular attribute of a particular topic, in response to providing the statement, obtaining one or more query patterns that each include one or more query terms that are used in queries submitted to a search system in obtaining a value for the particular attribute of the particular topic, generalizing one or more of the query patterns, and associating the one or more generalized query patterns with one or more other topics that include the particular attribute.
US09898510B2	Semantic data generation In some examples, a computing device may be configured to simulate the deduction process of human mind by generating new data based on existing data and newly received data that is semantically relevant to the existing data.
US09898507B2	Pre-fetching information in anticipation of a user request A system may pre-fetch search result information in anticipation of a user request for the search result information. The system may receive a user search query and request initial search results from a server based on the search query. The system may receive the initial search results from the server and render the initial search results for display to the user. In anticipation of a user request for additional search results, the system may request additional search results from the server. The additional search results may then be pre-fetched for potential display to the user in response to a user request to render the additional search results.
US09898504B1	System, method, and computer program for accessing data on a big data platform A system, method, and computer program product are provided for accessing data on a big data platform. In use, a request associated with a data processing job to process data stored in a big data store is identified, the data being stored in a plurality of rows with each row being associated with a unique key. Additionally, a data processing job input associated with the request is received, the data processing job input including a set of keys required to be read for processing. Further, the set of keys is translated into one or more queries, the one or more queries including at least one of a request to read an individual key or a request to read a range of keys. Moreover, the data is loaded from the big data store based on the one or more queries.
US09898502B2	System and method for executing a SPARQL query The present disclosure provides system and method for executing SPARQL query on a SPARQL engine. For executing the SPARQL query, a function may be instantly integrated with the SPARQL query which leads to extension of the SPARQL query. The extension may be achieved through a user friendly interface which may allow transparent integration of code (i.e., the function) in any language such as JAVA, C, C++ and the like, supporting a particular functionality. The system may integrate the code by addition of newly added code to the SPARQL library after validation. Further, the system may analyze the functionality associated with the code to optimize decision making of a user. The system may further support auto compilation and rating of the functions based on the user feedback and re-usability of the code working in a collaborative environment. Further the system may enable also enable to integrate external tools and web services.
US09898501B2	Method and system for performing transactional updates in a key-value store A method and system for performing a transactional update of a plurality of values in a key-value store that includes a first writer starting a transaction, a second writer joining the transaction, the first writer and the second writer writing changes to the plurality of values in a temporary transaction area in a storage area, and after the first writer and the second writer complete writing the changes, moving the plurality of values from the temporary transaction area to a global area in the key-value store.
US09898500B2	Management of downloads from a network-based digital data repository based on network performance Improved techniques and systems for storage, delivery and acquisition of digital assets stored in cloud data storage. Cloud data storage can be provided by a cloud data repository that is capable of storing digital data for various users. A given user can access cloud data storage from any of his/her authorized client devices via a network. A given client device can access not only locally stored digital assets but also remotely stored digital assets from cloud data storage. In one embodiment, downloads of digital assets resident in cloud data storage to client devices can be managed in view of available network performance. As one example, digital assets of differing quality levels can be downloaded in a manner dependent on network performance. As another example, locally stored digital assets of reduced quality can be upgraded (e.g., replaced) by higher quality versions in a manner dependent on network performance.
US09898491B2	Method and system for providing business intelligence data A machine implemented method for accelerating access to business intelligence data including providing a master database table on a computer readable medium and accessible by an analytics server, accessing rows in the master database table by the analytics server, with each row in the master database table containing at least a partial set of measures for a plurality of dimensions, identifying by the analytics server a set of one or more dimensions from the plurality of dimensions subject to a query by one or more computing devices in communication with the analytics server, extracting the set of one or more dimensions and associated measures for each of the one or more dimensions from the master database table, and forming a baby fact table such that each row in the baby fact table contains the set of one or more dimensions subject to the query and the associated measures derived from the extracting step.
US09898488B2	Preserving deprecated database columns A method of preserving deprecated database columns across application upgrades may include maintaining a database communicatively coupled to an application. The application may include a first schema. The first schema may indicate a first column for the database. The method may also include receiving an update for the application. The update may include a second schema that removes the first column from the database. The method may additionally include renaming the first column by appending a prefix to a name of the first column. The prefix may indicate that the first column is deprecated. The method may further include maintaining the first column in the database.
US09898487B2	Determining color names from keyword searches of color palettes Systems and methods are described herein to determine data, including color names, associated with color palettes identified from keyword searches. Color palettes may be searched by name or other data associated with the color palettes. Images and/or items may be retrieved based at least in part on the colors of the color palettes. Individual colors may be associated with color names based at least in part on human surveys and/or color names may be retrieved. Furthermore, the color names of individual colors may be retrieved based at least in part on a fast color search and/or associated with human votes. Various user interfaces may provide color palettes, images, and/or color names to users based at least in part on keyword searching of color palettes.
US09898486B2	Method, a system, an apparatus and a computer program product for image-based retrieval The invention relates to a method and a system for image-based retrieval. The method comprises receiving a query image; processing the query image to obtain visual features; determining a feature from the obtained visual features; determining a viewing direction for the query image from a pre-determined set of viewing directions; generating a direction-based hash based on the determined feature in the query image and the viewing direction; identifying sub-volumes of a point cloud database that match the direction-based hash; and matching the identified sub-volumes against all the query image features to find a match.
US09898483B2	Systems, methods, and apparatuses for creating a shared file system between a mainframe and distributed systems The disclosed system may comprise a mainframe computing resource, a data library, a data processing appliance, and a distributed system. The data library may be securely connected to the mainframe computing resource. The data library may be configured to receive data from the mainframe computing resource via a first interface. The data processing appliance may be configured to read and write data to the data library via a second user interface. The distributed system may be configured to receive data from the data processing appliance. The distributed system may be further configured to process the data based on a workflow from the mainframe computing system.
US09898482B1	Managing stream connections in storage systems A method is used in managing stream connections in storage systems. A set of criteria is evaluated for managing flow control characteristics of a stream connection in a storage system. The flow control characteristics indicates the rate at which requests are processed by the stream connection. Based on the evaluation, management of the flow control characteristics is affected.
US09898481B2	Data synchronization management In general, a data synchronization management system is disclosed in which files (and/or other data) are synchronized among two or more client computing devices in connection with a backup of those files. Synchronization polices specify files to be synchronized based on selected criteria including file data, metadata, and location information. In general, files are initially copied from a primary client computing device to secondary storage. Thereafter, files to be synchronized are identified from the secondary storage, and copied to other client computing devices. Additionally, synchronized files may be viewed and accessed through a cloud and/or remote file access interface.
US09898480B2	Application recommendation using stored files The disclosed technology can enable files to be stored with a networked environment. The files can be associated with information (e.g., properties) such as a file name, a file type, a date/time at which a respective file was last accessed, a number of times a respective file was accessed, data representing the contents of a respective file, and other information. Based at least in part on analyzing the information, the disclosed technology can select or identify a file and/or a file property (e.g., a file type) that the disclosed technology predicts to be most relevant to the user. The disclosed technology can then recommend applications based at least in part on the selected or identified file and/or file property (e.g., file type).
US09898474B1	Object sharding in a host-side processing device for distributed storage A host-side network processing device coupled between a storage system and a host machine may encode a data object according to a sharding technique. Encoding the data object may include receiving, from the host machine, a data object and a request to store the data object. The network processing device may send a request for a plurality of storage locations to the storage system. The network processing device may receive a location list including a plurality of location identifiers from the storage system, where each location identifier corresponds to a respective storage location. The network processing device may determine an encoding matrix and encode the data object into a plurality of shards based on the encoding matrix according to a sharding technique. The network processing device may generate a plurality of storage requests that each specify a different location identifier and that each includes a respective shard.
US09898471B1	Computer implemented system and method, and computer program product, for generic source control for orchestration workflows A system, method and computer program product for generic source control for orchestration workflows. An example method may include receiving orchestration workflow information from an orchestration workflow engine. The received orchestration workflow information may be in a native file format. The received orchestration workflow information may be converted from a native file format to a predefined format. A request to check in the converted orchestration workflow information may be received, and responsive to receiving the request, the converted orchestration workflow information is stored in a source control system. A request to check out the converted orchestration workflow information may be received from a client computer, and, responsive to receiving the request, orchestration workflow change information may be generated, which indicate changes that have been made to the orchestration workflow information. The orchestration workflow change information may be sent to the client computer.
US09898467B1	System for data normalization Described are techniques and systems to process input data into normalized data using regular expression (“regex”) tokens to build rules. The regex tokens refer to a predefined regex phrase. A developer or an automated system may create the regex tokens. A user or automated system may combine and reuse the regex tokens in various ways to express different normalization rules. These rules may be automatically processed to generate regexs. The regexs are used in processing the input data to generate the normalized data.
US09898465B2	System and method for providing audio-visual content A system and method for providing access to audio-visual (AV) content, such as music or video clips, is described that includes providing an openly accessible code on an item or packaging associated with the item, and a second (limited-access) code associated with the same item or packaging. The first code and the second code can be a quick-response code or other scannable code, or a string of alphanumeric characters. Access to a sample and a full version of the AV content can be provided when the first code or second code, respectively, is scanned, or entered on a particular website or other location, using a device such as a computer, smartphone, or tablet computer. The sample can be a portion or a reduced-quality version of the full AV content. The AV content can be related to images and/or words provided on or associated with the item.
US09898464B2	Information extraction supporting apparatus and method According to one embodiment, an information extraction supporting apparatus includes a first acquirer, a determiner, a selector and an extractor. The first acquirer acquires a document from which at least one attribute indicating a type of desired information is extracted as an analysis target. The determiner determines whether or not the at least one attribute is valid, and obtains at least one of the valid attributes as one or more attribute candidates. The selector selects an attribute to be used for an analysis from the one or more attribute candidates as a selected attribute. The extractor extracts an expression belonging to the selected attribute from the document as an attribute expression.
US09898458B2	Generating distributed word embeddings using structured information A computer program that uses structured information, such as syntactic and semantic information, as context for representing words and/or phrases as vectors, by performing the following steps: (i) receiving a first set of natural language text and a set of information pertaining to the first set of natural language text, where the information includes metadata and corresponding contextual information indicating a relationship between the metadata and the first set of natural language text; and (ii) generating a first vector representation for the first set of natural language text utilizing the metadata and its corresponding contextual information.
US09898457B1	Identifying non-natural language for content analysis Examples for detecting and removing non-natural language within natural language to enhance performing content analysis on the natural language are provided herein. A plurality of terms is identified in a phrase, and a sliding window having a defined length is placed over a first sequence of terms from the plurality of terms. The first sequence of terms includes a first term, a second term, and a third term, the first term and the third term being adjacent to the second term. Based on the first term, the second term, and the third term, a determination is made as to whether the second term represents non-natural language. Upon determining that the second term is non-natural language, the second term is labeled as non-natural language and is removed from the plurality of terms based on determining the second term as non-natural language.
US09898455B2	Natural language understanding cache Disclosed methods and systems are directed to natural language understanding cache usage. The methods and systems may include receiving a first natural language input comprising a set of one or more terms, and parsing the first natural language input to determine a first pretag result comprising a first string comprising at least one term from the set of one or more terms. The methods and systems may also determine that if the first pretag result corresponds to a key stored in a cache, then retrieve one or more cached NLU results corresponding to the at least one key. The methods and systems may also determine that if the first pretag result does not correspond to a key stored in the cache, then determine, based on the set of one or more terms, a first NLU result corresponding to the first natural language input.
US09898454B2	Using text messages to interact with spreadsheets Text messages are used to interact with objects in a spreadsheet. For example, text messages may be used to enter/receive data in the spreadsheet. One or more text messages may be associated with a spreadsheet. Text messages may be associated with cells, tables, charts and other objects of the spreadsheet. When the spreadsheet receives a text message, the text message is parsed and information that is contained within the text message is used to interact with one or more objects within the spreadsheet. The spreadsheet may also generate and send text messages that provide information about the spreadsheet and/or request information to be entered within the spreadsheet. For example, the spreadsheet may send out an update of one or more values/objects within a spreadsheet and/or send a request within a text message requesting information to update a table.
US09898452B2	Annotation data generation and overlay for enhancing readability on electronic book image stream service Provided are techniques for receiving a scanned image corresponding to a page; analyzing the scanned image to identify a set of characters (Ci) and corresponding positions (Pi) of each character of Ci on the page; applying natural language processing (NPL) and an analytic analysis algorithm to determine a semantic analysis relationship of phrases formed by Ci to determine meanings for the phrases; generating a plurality of annotations (Ai) indicating the determined meanings of the phrases, wherein each annotation is assigned a corresponding position (Qi) on the page based upon the Pi of the corresponding characters on the page; and storing, in a non-transitory computer-readable medium, the scanned image in conjunction with the plurality of annotations and the corresponding Qi.
US09898444B1	Image comparison for user interface testing Disclosed are various embodiments for comparing images of network pages using computer vision to identify changes that have occurred between two versions of a network page. A first plurality of segments in a first image representing a first version of a network page are identified and a second plurality of segments in a second image representing a second version of the network page are identified. It is then determined whether each segment in the first plurality of segments matches a respective segment in the second plurality of segments or vice versa.
US09898442B2	Data processing device, data processing method, and program A data processing device includes: a data obtaining section obtaining time series data on a total value of current consumed by a plurality of electric apparatuses; and a parameter estimating section obtaining a model parameter when states of operation of the plurality of electric apparatuses are modeled by a factorial HMM on a basis of the obtained time series data.
US09898440B2	Calculation framework utilizing fragmentation of expressions A calculation engine computes equation(s) based upon dependencies between variables, both initially input and as calculated from various fragmented sub expressions. The calculation engine accommodates relationships between equations, with output variable(s) of one equation possibly serving as input to another equation in a chain. Initially, the calculation engine sorts equations based upon their relationship to each other and to the input variables. The calculation engine next fragments the equations' expressions into various sub expressions. This fragmenting may be according to an order of operations (e.g., brackets/parentheses, then exponents/powers, then multiplication/division). Sub expressions ultimately resulting from fragmentation process, may comprise unary expressions, binary expressions, or expressions involving three or more operations at a same level of priority. Upon rationalizing an order of the fragments, the engine may evaluate units (e.g., SI and others) thereof, allowing assignment of units to output variables of the larger and more complex equations.
US09898439B2	Optimizing remote direct memory access (RDMA) with cache aligned operations A system for optimizing remote direct memory accesses (RDMA) is provided. The system includes a first computing device and a second computing device disposed in signal communication with the first computing device. The first and second computing devices are respectively configured to exchange RDMA credentials during a setup of a communication link between the first and second computing devices. The exchanged RDMA credentials include cache line size information of the first computing device by which a cache aligned RDMA write operation is executable on a cache of the first computing device in accordance with the cache line size information by the second computing device.
US09898437B2	Host for use with dual interface card with backward and forward compatibility A host device includes a slot configured to receive a first type of memory card having an indentation and a mechanical structure. The mechanical structure includes a pivot structure and a lever arm. The lever arm is configured to pivot on the pivot structure and a portion of the lever arm is configured to at least partially fit into the indentation to distinguish the first type of memory card from a second type of memory card.
US09898436B2	Data transmission system and transmission method thereof including connection and orientation detection A data transmission system and a transmission method thereof are provided. The data transmission system includes a first electronic apparatus and a second electronic apparatus. The first electronic apparatus includes a first clock pin and a first data pin. The second electronic apparatus includes a second clock pin and a second data pin. In a connecting detection mode, the first electronic apparatus transmits a first detection signal to the first clock pin and drives the first data pin to a reference logic level. The second electronic apparatus transmits a second detection signal to the second clock pin and drives the second data pin to the reference logic level. The first electronic apparatus determines whether the first and the second electronic apparatuses are connected to each other according to whether at least one of signals on the first clock pin and on the first data pin is varied or not.
US09898432B2	Data transfer control apparatus According to an embodiment, a data transfer control apparatus has a band measurement unit and a request mask unit. The band measurement unit measures a band level to transfer data, and compares this measurement band level with a target band level. The request mask unit outputs a correction request signal which is obtained by correcting a timing of a request signal sent from each of a plurality of processing units, based on a request mask control signal which the band measurement unit outputs.
US09898430B2	Tracking virtual machine memory modified by a single root I/O virtualization (SR-IOV) device Techniques for tracking, by a host system, virtual machine (VM) memory modified by a physical input/output (I/O) device that supports I/O virtualization are provided. In one embodiment, a hypervisor of the host system can receive a hardware interrupt from the physical I/O device, where the hardware interrupt indicates that a virtual function (VF) of the physical I/O device has completed a direct memory access (DMA) write to a guest memory space of a VM running on the host system. In response to the hardware interrupt, the hypervisor can invoke a function implemented by a physical function (PF) driver of the physical I/O device, where the function is configured to inspect the VF's state in order to identify memory portions modified by the DMA write. The hypervisor can then mark, in a hypervisor-level page table, one or more memory pages corresponding to the identified memory portions as dirty pages.
US09898428B2	Column bus driving method for micro display device A method of generating column signals for use by a pixel array includes connecting two or more controllable bus buffers in series. The output of each of the two or more controllable bus buffers drives an associated node. The method further includes providing a column data signal to an input of the series-connected string of two or more controllable bus buffers. The method also includes sequentially enabling each controllable bus buffer in the series-connected string of two or more controllable bus buffers, such that each node is sequentially driven. Each node is electrically coupled to an input of an associated controllable local output buffer. The method further includes sequentially enabling each of the controllable local output buffers in an order associated with the sequentially enabling of the controllable bus buffers.
US09898426B2	Electronic device An electronic device may include a semiconductor memory, and the semiconductor memory may include a free layer having a variable magnetization direction; a pinned layer having a pinned magnetization direction; and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein the free layer may include a first magnetic layer; a second magnetic layer formed over the first magnetic layer; and a Zirconium (Zr)-containing material layer interposed between the first magnetic layer and the second magnetic layer.
US09898424B2	Bioinformatics, systems, apparatus, and methods executed on an integrated circuit processing platform A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes an integrated circuit formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the integrated circuit connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.
US09898421B2	Memory access processing method, memory chip, and system based on memory chip interconnection A memory access processing method is based on memory chip interconnection, a memory chip, and a system, which relate to the field of electronic devices, and can shorten a time delay in processing a memory access request and improve a utilization rate of system bandwidth. The method of the present disclosure includes receiving, by a first memory chip, a memory access request; and if the first memory chip is not a target memory chip corresponding to the memory access request, sending, according to a preconfigured routing rule, the memory access request to a next memory chip connected with the first memory chip, until the target memory chip corresponding to the memory access request is determined. Embodiments of the present disclosure are mainly used in a process of processing a memory access request.
US09898407B2	Configuration based cache coherency protocol selection Topology of clusters of processors of a computer configuration, configured to support any of a plurality of cache coherency protocols, is discovered at initialization time to determine which one of the plurality of cache coherency protocols is to be used to handle coherency requests of the configuration.
US09898397B2	Deployment pattern monitoring A computer system can detect a request for status information relating to a particular deployment pattern; query, in response to the request, a deployment pattern registry for deployment configuration information about the particular deployment pattern; test deployment capabilities for the particular deployment pattern by: verifying installation files for the particular deployment pattern are accessible; identifying one or more candidate deployment components for a hypothetical deployment of the particular deployment pattern; installing, on the one or more candidate deployment components, a virtual machine that is configured to test computing resources of the one or more candidate deployment components; and receiving test results regarding the resources of the one or more candidate deployment components. The system can generate a notification in response to detecting a failure in the testing.
US09898394B2	Test design assistance device, test design assistance method, program and computer-readable medium A test design assistance device 10 acquires information about the number of levels indicating the number of values which can be obtained for each factor in a plurality of factors of a test target, selects a matrix capable of allocating all of factors in a maximum number of levels information in the matrix capable of allocating factors in multilevel generated based on an orthogonal table, sets the maximum number of the number of levels in the levels of factors which are not allocated as a focused number of levels, and allocates factors in the focused number of levels to the matrix when the number of columns capable of allocating the factors in the focused number of levels is equal to greater than the number of factors in the focused number of levels, in the selected matrix.
US09898390B2	Virtual service localization A virtual service is instantiated from a service model that is operable to receive requests intended for a particular software component in a system and generate simulated responses of the particular software component based on a service model modeling responses of the particular software component. A particular request intended for the particular software component is identified that has been redirected to the virtual service and content of a simulated response to the particular request is generated using the virtual service in a first language. A second language to be applied to the simulated response is determined based on the request, and a translation of the content from the first language into the second language is determined. A modified version of the simulated response is sent to the other software component in response to the particular request that includes the content in the second language.
US09898388B2	Non-intrusive software verification This application discloses a computing system configured to simulate an embedded system including a processor capable of executing embedded software, compile the embedded software into a format capable of execution by the computing system, insert instrumentation code into the compiled embedded software, and execute the compiled embedded software and the instrumentation code. The execution of the compiled embedded software can simulate execution of the embedded software by the processor in the simulated embedded system, while the execution of the instrumentation code can configure the computing system to gather information corresponding to the execution of the compiled embedded software.
US09898376B2	Recovery of a transaction after XA end Embodiments of the present invention disclose a method for recovery of a two-phase commit transaction. A computer receives an end command prior to completing execution of a prepare command for a transaction identifier. The computer determines if a failure and restart occurred within a distributed data processing environment after a resource manager receives an end command. The computer responds to a determination that the failure and restart did occur within the distributed data processing environment by retrieving the first transaction identifier from a data store. The computer transmits a rollback command for the retrieved first transaction identifier to the resource manager.
US09898374B2	Recovery of an infected and quarantined file in a primary storage controller from a secondary storage controller A primary storage controller determines that a quarantined area of the primary storage controller cannot be repaired, wherein the quarantined area is infected with a virus. A query is sent to a secondary storage controller to determine whether the secondary storage controller has data that is free of virus in an area of the secondary storage controller corresponding to the quarantined area of the primary storage controller. In response to receiving a notification that the secondary storage controller has data that is free of virus, the primary storage controller is repaired to remove the virus.
US09898372B2	Backing up a computer application A method and associated systems for backing up a target computer application that comprises identifying and backing up databases and other information repositories upon which the target application depends. The target application is identified and related to a backup requirement that specifies a minimum application-backup frequency. The application's “dependencies” are automatically identified from sources that include configuration files, where each dependency identifies one or more databases or other information repositories that store information upon which the application directly or indirectly depends. If any of these databases or repositories is associated with a backup frequency less than the application's minimum backup frequency, the database or repository is flagged. Each flagged entity's backup schedule is then revised so that the flagged entity's backup frequency is equal to or greater than the application's minimum backup frequency.
US09898367B2	Automatic scanning and recovering method for electronic device An automatic scanning and recovering method for an electronic device is provided herein and executed by the electronic device. The method comprises following steps: a step of receiving a booting command; a step of determining whether a crash flag is in an activating status when the electronic device is turned on; a step of performing a system diagnostics utility to scan and recover the electronic device when the crash flag is in the activating status; and a step of setting the crash flag to be in an inactivating status and performing a rebooting procedure.
US09898365B2	Global error correction A method that includes evaluating, with a controller, local error detection (LED) information in response to a first memory access operation is disclosed. The LED information is evaluated per cache line segment of data associated with a rank of a memory. The method further includes determining an error in at least one of the cache line segments based on an error detection code and determining whether global error correction (GEC) data for a first cache line associated with the at least one cache line segment is stored in a GEC cache in the controller. The method also includes correcting the first cache line associated with the at least one cache line segment based on the GEC data retrieved from the GEC cache in the controller without accessing GEC data from a memory.
US09898361B2	Multi-tier detection and decoding in flash memories Methods and apparatus are provided for multi-tier detection and decoding in flash memory devices. Data from a flash memory device is processed by obtaining one or more read values for at least one bit in a given page of the flash memory device; converting the one or more read values for the at least one bit to a reliability value; performing an initial decoding of the at least one bit in a given page using the reliability value; and performing an additional decoding of the at least one bit in the given page if the initial decoding is not successful, wherein the additional decoding uses one or more of additional information for the given page and at least one value for at least one bit from at least one additional page.
US09898360B1	Preventing unnecessary data recovery A method that prevents unnecessary data recovery includes receiving, at a data processing device, a status of a resource of a distributed system. When the status of the resource indicates a resource failure, the method includes executing instructions on the data processing device to determine whether the resource failure is correlated to any other resource failures within the distributed system. When the resource failure is correlated to other resource failures within the distributed system, the method includes delaying execution on the data processing device of a remedial action associated with the resource. However, when the resource failure is uncorrelated to other resource failures within the distributed system, the method includes initiating execution on the data processing device of the remedial action associated with the resource.
US09898358B2	Error response circuit, semiconductor integrated circuit, and data transfer control method In an error response circuit an analysis circuit unit analyzes a command transmitted from a first circuit section to a second circuit section, and detects a status of data transfer between the first circuit section and the second circuit section. A response circuit unit generates an error signal in accordance with the detected status of the data transfer in response to the second circuit section changing from a first power consumption state to a second power consumption state in which power consumption is lower than power consumption in the first power consumption state. A switching circuit unit transmits the error signal to the first circuit section in place of a response signal that is responsive to the command and transmitted from the second circuit section to the first circuit section.
US09898350B2	Techniques for synchronizing operations performed on objects Described are techniques for synchronizing operations performed on objects. Locking tables may be received where each of the locking tables corresponds to different object class. First processing may be performed by a first thread to acquire a set of one or more locks. Each lock in the set may be a lock for one of the objects. The first processing may include traversing the locking tables in accordance with a predefined ordering and acquiring the set of one or more locks, wherein, for each lock in the set, a first entry is updated in a first of the locking tables to indicate that the first thread has acquired the lock on one of the objects included in an associated object class corresponding to the first locking table.
US09898343B2	Application-level dispatcher control of application-level pseudo threads and operating system threads An application-level thread dispatcher that operates in a main full-weight thread allocated to an application is established. The application-level thread dispatcher initializes a group of application-level pseudo threads that operate as application-controlled threads within the main full-weight thread allocated to the application. The application-level thread dispatcher evaluates run-time performance of the application.
US09898337B2	Dynamic workload deployment for data integration services An approach for deploying workload in a multi-tenancy computing environment is provided. The approach generates, by one or more computer processors, a tenant ID and a plan ID for a tenant based, at least in part, on a tenant registration request. The approach stores, by one or more computer processors, the tenant ID and the plan ID into a shared system record. The approach receives, by one or more computer processors, a request to update a first tenant service plan. The approach determines, by one or more computer processors, one or more resource pools supporting a second tenant service plan based at least in part, on an association between the tenant ID and the plan ID. The approach deploys, by one or more computer processors, one or more resources from the one or more resource pools supporting the second tenant service plan.
US09898330B2	Compacted context state management Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.
US09898328B2	Auto-adaptive virtual desktop persistence An adaptive virtual desktop architecture is provided. Application install or assignment is evaluated, such as by using heuristics to identify applications that may present compatibility problems. Upon determining that a newly installed application may have compatibility problems when associated with a non-persistent virtual desktop, a promotion to a persistent virtual desktop occurs.
US09898313B2	Parallel processing of data for an untrusted application An untrusted application is received at a data center including one or more processing modules and providing a native processing environment. The untrusted application includes a data parallel pipeline. Secured processing environments are used to execute the untrusted application.
US09898312B2	Intelligent data storage and processing using FPGA devices Methods and systems are disclosed where a plurality of precompiled hardware templates are stored in memory, each of the hardware templates being configured for loading onto a re-configurable logic device such as a FPGA to define a data processing operation to be performed by the re-configurable logic device, each of the data processing operations defined by the precompiled hardware templates having an associated performance characteristic. A processor selects a precompiled hardware template from a plurality of the precompiled hardware templates in the memory for loading onto the re-configurable logic device based at least in part on the associated performance characteristics of the data processing operations defined by the precompiled hardware templates.
US09898309B2	Wake-up trigger using MEMS wind turbines A portable device includes micro-electro-mechanical systems (“MEMS”) wind turbines integrated in the portable device. A gesture detection module receives signals generated by the MEMS wind turbines based on movement of the portable device that causes a wind force to be applied to the MEMS wind turbines. The gesture module then recognizes a gesture based on the signals generated from the wind force and initiates an action of the portable device that corresponds to the gesture (e.g., the device is awakened).
US09898308B2	Computing apparatus and method for initiating automatic booting process when cover is opened Disclosed is a method for controlling a computing apparatus including a cover having a display on one surface facing into a keyboard when the cover is in a closed state. The method comprises, in response to receiving a command to turn on an automatic booting mode of the computing apparatus, storing a configuration value corresponding to an ON state of the automatic booting mode in a memory; when the cover is in the closed state, detecting an opening of the cover via a sensor of the computing apparatus; and, in response to detecting the opening of the cover when a system status of the computing apparatus is an S5 state defined by the Advanced Configuration and Power Interface (ACPI) standard, performing, via a controller of the computing apparatus, an operation of entering from the S5 state to an S0 state defined by the APCI standard based on the configuration value stored in the memory.
US09898305B2	Display method for logo graphics displayed on screen and smart device A display method for logo graphics displayed on a screen is provided, implemented by a smart device. The display method includes the following steps: powering on the smart device, to enter a Basic Input Output System (BIOS) stage; accessing, from a first non-volatile memory of the smart device, exclusive logo graphics data private-key encrypted for decryption, and using a public key pre-stored in a second non-volatile memory of the smart device for verification; and displaying, when the public key matches a private key corresponding to the exclusive logo graphics data, an exclusive logo graphic on a screen according to the decrypted and decompressed exclusive logo graphics data. The present invention further includes a smart device, a readable record medium, and a computer program product.
US09898304B2	Fast booting a computing device to a specialized experience Described is a technology by which independent computing functions such as corresponding to separate operating systems may be partitioned into coexisting partitions. A virtual machine manager, or hypervisor, manages the input and output of each partition to operate computer system hardware. One partition may correspond to a special purpose operating system that quickly boots, such as to provide appliance-like behavior, while another partition may correspond to a general purpose operating system that may load while the special purpose operating system is already running. The computer system that contains the partitions may transition functionality and devices from one operating system to the other. The virtual machine manager controls which computer hardware devices are capable of being utilized by which partition at any given time, and may also facilitate inter-partition communication.
US09898303B2	Multi-core hardware semaphore in non-architectural address space A microprocessor includes a plurality of processing cores, a resource shared by the plurality of processing cores, and a hardware semaphore readable and writeable by each of the plurality of processing cores within a non-architectural address space. Each of the plurality of processing cores is configured to write to the hardware semaphore to request ownership of the shared resource and to read from the hardware semaphore to determine whether or not the ownership was obtained. Each of the plurality of processing cores is configured to write to the hardware semaphore to relinquish ownership of the shared resource.
US09898302B2	Control device and access system utilizing the same A control device coupled between a first memory and a second memory and including an execution unit, a first storage unit, a second storage unit, a selection unit and a processing unit is disclosed. The execution unit executes a specific instruction set to access the first and the second memories. The first storage unit is configured to store a first instruction set. The second storage unit is configured to store a second instruction set. The selection unit outputs one of the first and the second instruction sets to serve as the specific instruction set according to a control signal. The processing unit generates the control signal according to an execution state of the execution unit.
US09898293B2	Decoding instructions that are modified by one or more other instructions Methods and apparatus are provided for decoding instructions in a computer program wherein the instructions include one or more base instructions that are subject to modification by one or more other instructions. A decoder determines whether a first received instruction was arrived at by a non-incremental change to a program counter (i.e. a jump in the program). If the first instruction was arrived at by a non-incremental change to the program counter the decoder decodes the immediately preceding instruction to determine if the original instruction is a base instruction subject to modification by one or more other instructions. If the preceding instruction indicates that the original instruction is a base instruction an error has occurred and exception handling code is invoked.
US09898289B2	Coordinated start interpretive execution exit for a multithreaded processor A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.
US09898288B2	Methods and systems for managing an instruction sequence with a divergent control flow in a SIMT architecture A computer-implemented method of executing an instruction sequence with a recursive function call of a plurality of threads within a thread group in a Single-Instruction-Multiple-Threads (SIMT) system is provided. Each thread is provided with a function call counter (FCC), an active mask, an execution mask and a per-thread program counter (PTPC). The instruction sequence with the recursive function call is executed by the threads in the thread group according to a program counter (PC) indicating a target. Upon executing the recursive function call, for each thread, the active mask is set according to the PTPC and the target indicated by the PC, the FCC is determined when entering or returning from the recursive function call, the execution mask is determined according to the FCC and the active mask. It is determined whether an execution result of the recursive function call takes effects according to the execution mask.
US09898287B2	Dynamic wavefront creation for processing units using a hybrid compactor A method, a non-transitory computer readable medium, and a processor for repacking dynamic wavefronts during program code execution on a processing unit, each dynamic wavefront including multiple threads are presented. If a branch instruction is detected, a determination is made whether all wavefronts following a same control path in the program code have reached a compaction point, which is the branch instruction. If no branch instruction is detected in executing the program code, a determination is made whether all wavefronts following the same control path have reached a reconvergence point, which is a beginning of a program code segment to be executed by both a taken branch and a not taken branch from a previous branch instruction. The dynamic wavefronts are repacked with all threads that follow the same control path, if all wavefronts following the same control path have reached the branch instruction or the reconvergence point.
US09898284B2	Apparatus and method for an instruction that determines whether a value is within a range A method is described that includes performing the following with a single instruction: receiving a first input operand V; receiving a second input operand S; calculating V−S; determining if V−S is positive or negative; and, providing as a resultant: V if V−S is negative; V−S if V−S is positive.
US09898283B2	Processors, methods, systems, and instructions to generate sequences of integers in which integers in consecutive positions differ by a constant integer stride and where a smallest integer is offset from zero by an integer offset A method of an aspect includes receiving an instruction. The instruction indicates an integer stride, indicates an integer offset, and indicates a destination storage location. A result is stored in the destination storage location in response to the instruction. The result includes a sequence of at least four integers in numerical order with a smallest one of the at least four integers differing from zero by the integer offset and with all integers of the sequence in consecutive positions differing by the integer stride. Other methods, apparatus, systems, and instructions are disclosed.
US09898281B2	Verifying source code in disparate source control systems A computer program product for verifying source code in disparate source control systems. A processor configured to: obtain a first source code from a target repository; access a second source code from a source repository; and verify each file in the first source code matches each corresponding file in the second source code. Verifying causes the processor to: read contents of a file in the first source code in the target repository; access a corresponding file in the second source code in the source repository; replace contents of the corresponding file in the second source code in the source repository with the contents of the file in the first source code in the target repository; execute an editor in the source repository to display differences in the corresponding file that have been modified as a result of replacing contents; and log each file that does not match.
US09898270B2	Multi-environment configuration of data integration projects A system and method for facilitating execution of one or more data integration projects in multiple environments or an environment that undergoes changes. Each project has a set of project parameters, which are bound to environment variables. Each environment has a corresponding environment representation with environment variables and corresponding values. Each project is mapped to an environment representation. Values of environment variables are provided to projects with corresponding parameters. When one or more projects are changed to a different environment with a different corresponding environment representation, the environment variable values of the new environment representation are provided to the projects. When an environment change is reflected in the environment representation, the changed variable values are provided to mapped projects.
US09898266B2	Loop vectorization methods and apparatus Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.
US09898264B2	Automatic componentization engine Disclosed herein are technologies for automatically updating object model and associated code for software applications, such as web pages, by invoking an automatic componentization engine client to determine changes in the component code of web pages, receiving the changes in the component code, and compiling and verifying the code. Generated or revised and updated code may then be provided to a user.
US09898252B2	Multiplication operations in memory Examples of the present disclosure provide apparatuses and methods for performing multiplication operations in a memory. An example method comprises performing a multiplication operation on a first element stored in a group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include a number operations performed without transferring data via an input/output (I/O) line.
US09898245B1	System limits based on known triggers In an example implementation, a method may involve, while a first zone and a second zone of a media playback system are playing back respective media, receiving data indicating the occurrence of a first trigger condition. The method may also involve, based on the received data, modifying respective volume limits of the first zone and the second zone, wherein modifying the volume limit causes first volume levels that exceed the second limit to be reduced to respective second volume levels that are at or below the second limit. The method may also involve receiving data indicating the occurrence of a second trigger condition. The method may further involve, based on the received data, modifying the respective volume limits of the first zone and the second zone from the second limit to the first limit.
US09898243B2	Information processing apparatus, program, information processing system, and information processing method An information processing apparatus for displaying a specified display area of target data in a display unit, the target data being shared with another information processing apparatus. The information processing apparatus includes: a reception unit that receives information indicative of the specified display area specified in the another information processing apparatus; and a display controlling unit that scales the specified display area and an image in a peripheral portion of the specified display area and displays the specified display area and the image in the display unit such that the specified display area is included in a display field of the display unit based on the received information indicative of the specified display area and information about the display field of the display unit.
US09898240B2	Systems, devices, and methods relating to an electronic display Systems, devices, and methods relating to an electronic display are disclosed. A method of operating a display system may include conveying visual content representing a contiguous image to a display system including a plurality of display panels, wherein each display panel is adjacent at least one mounting member. The method may further include selectively retrieving with each display panel of the plurality an associated subset of the visual content belonging thereto. In addition, the method may include displaying on a display device of each display panel the associated subset of the visual content.
US09898239B2	Print control device and control method for print control device for communicating with host devices by multiple communication standards A print control device includes: a first communication unit which communicates with a host device via a first communication standard; a second communication unit which communicates with a host device via a second communication standard that is different from the first communication standard; and a control unit which carries out communication control with the host device and print control, wherein the control unit turns a connection with the host device through the first communication unit into a disconnected state when data is received via the first communication standard during print control based on a print job received via the second communication standard.
US09898230B2	Information processing apparatus, system, and information processing method The apparatus comprises a register, a transferring unit that transfers data stored in a first memory to a second memory, and a calculator that applies a checksum operation to the data being transferred by the transferring unit. When a first mode is set, the calculator transmits the result of the checksum operation to the transferring unit, and the transferring unit transfers the result to the second memory. When a second mode is set, the calculator applies the checksum operation to partial data that is included in the data and has been specified as a target of the checksum operation, and transmits the result of the checksum operation applied to the partial data to the register.
US09898226B2	Reducing page invalidation broadcasts in virtual storage management Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.
US09898221B2	Control device for storage system capable of acting as a constituent element of virtualization storage system A management target constituting the target of processing executed by a first storage system in accordance with a request transmitted from a higher-level device is managed by first and second management identifiers. A request designating the first management identifier is received from the higher-level device, and a first management identifier designated by the request is converted into a corresponding second management identifier.
US09898220B2	Resource sharing in a telecommunications environment A transceiver is designed to share memory and processing power amongst a plurality of transmitter and/or receiver latency paths, in a communications transceiver that carries or supports multiple applications. For example, the transmitter and/or receiver latency paths of the transceiver can share an interleaver/deinterleaver memory. This allocation can be done based on the data rate, latency, BER, impulse noise protection requirements of the application, data or information being transported over each latency path, or in general any parameter associated with the communications system.
US09898219B1	Allocating a device to a container In one aspect, a method includes associating disk devices with containers based on a policy, allocating a disk device to a container based on the policy and allowing access to the disk device from the container. In another aspect, an apparatus includes electronic hardware circuitry configured to associate disk devices with containers based on a policy, allocate a disk device to a container based on the policy and allow access to the disk device from the container. In a further aspect, an article includes a non-transitory computer-readable medium that stores computer-executable instructions. The instructions cause a machine to associate disk devices with containers based on a policy, allocate a disk device to a container based on the policy and allow access to the disk device from the container.
US09898216B2	Data storage system and specific command execution method thereof The present invention relates to a data storage system and specific command execution method thereof, which is applied to a memory storage system. When a memory manager receives an command from a host system, it can judge whether the command is a normal command or a specific command. If the command is the specific command, read a first logic sector address, an accessible data length and a second logic sector address in the specific command, and duplicate the first logic sector address pointing to the physical storage address of the stored data reading to a memory buffer; and move physical storage address pointing to that from the first logic sector address to the second logic sector address. It can achieve both data reading and data moving by one specific command.
US09898213B2	Scalable auxiliary copy processing using media agent resources A scalable approach is disclosed for processing auxiliary-copy jobs in a storage management system by using distributed media agent resources instead of a centralized storage manager. Enhanced media agents coordinate and control auxiliary-copy jobs and tap the storage manager to reserve data streams and provide job-specific metadata on demand. An enhanced storage manager may initially select a media agent as “coordinator” to coordinate auxiliary-copy jobs with any number of other media agents, which act as “controllers.” A coordinator media agent is generally responsible for obtaining data stream reservation information from the storage manager and assigning auxiliary-copy jobs to respective controller media agents, based on the components involved in the respective reserved data streams.
US09898211B2	Nonvolatile memory control device, nonvolatile memory control method and computer readable storage medium A nonvolatile memory control device performs data reading/writing control on partitions of a rewritable nonvolatile semiconductor memory. The device includes an erase cycle counting unit, a read cycle counting unit, a data reading/writing unit and a control unit. The erase cycle counting unit counts the number of erase cycles in total per partition. The read cycle counting unit counts the number of read cycles that same data is read per partition. When the number of erase cycles of a first partition is equal to or larger than a predetermined number of erase cycles, and a second partition having a smaller number of erase cycles and a larger number of read cycles than the first partition is present, the control unit controls the data reading/writing unit to exchange data in the first partition and data in the second partition.
US09898207B2	Storage device A storage device is provided. The storage device includes storage clusters, and a controller. The controller receives a command and an address from an external host device, selects a storage cluster according to the received address, and transmits the received command and the received address to the selected storage cluster. The controller controls the storage clusters as normal storage clusters and slow storage clusters according to a temperature of a zone to which the storage clusters belong.
US09898203B2	Replacing data structures for process control A method of replacing information governing transactions between computer systems may include storing a first data structure comprising first information that governs an active process of transactions between the computer systems, and cloning the first data structure to generate a second data structure. The method may also include receiving changes to the second information. The method may additionally include processing the first and second data structures using a simulation process to generate a first and second result set including simulation results of transactions between the computer systems over a future time interval as governed by the first and second information. The method may also include causing the first result set and the second result set to be comparatively displayed together, receiving a selection associated with the second result set, and replacing the first data structure with the second data structure to govern the active process.
US09898197B1	Lock-free memory management Described are techniques for memory management. An N-level bitmap is received, N>2. A memory pool is partitioned into slots each slot having a corresponding bit in level-1 of the N-level bitmap that indicates whether the slot is used or free. The slots are grouped into a hierarchy including N levels. A first thread receives a first request to allocate a first slot of the memory pool. Responsive to receiving the first request, the first thread performs first processing to allocate the first slot using the N-level bitmap. Allocation requests each to allocate slots from the memory pool are only processed by the first thread. A second thread receives a second request to free a second slot of the memory pool. Responsive to receiving the second request, the second thread performs second processing using the N-level bitmap to free the second slot. Requests to free slots are processed by multiple threads.
US09898196B1	Small block write operations in non-volatile memory systems A first portion of an asymmetric memory is configured as temporary storage for application data units with sizes corresponding to a small memory block that is smaller than the size of a logical write unit associated with the asymmetric memory. A portion of the remaining asymmetric memory is configured as a reconciled storage for application data units with varying sizes. A first application data unit is received for writing to the asymmetric memory. Based on computing the size of the first application data unit as corresponding to the small memory block, the first application data unit is written to the temporary storage. Upon determining that a threshold is reached, a memory write operation is performed for writing the application data units from the temporary storage to the reconciled storage. The application data units written to the reconciled storage are removed from the temporary storage.
US09898193B2	Application-specific integrated circuit and measurement transmitter having such a circuit An application-specific integrated circuit comprises: analog inputs having analog-digital converters; at least one digital signal processor, which has input registers and output registers. The analog-digital converters sample and digitize input signals Si with sampling frequencies fSi and forward the digitized signals SDi with output frequencies fSD-out-i to the input registers of the digital signal processor. The digital signal processor processes the digitized signals SDi to m processed signals SPj and forwards such to the output registers of the digital signal processor. The digital signal processor has a clock frequency, wherein, furthermore, the signals of the output registers can be output, respectively read-out, with an output frequency. One or more of the frequencies is, respectively, variable, wherein especially one or more of the frequencies, respectively, variable independently of the others of the frequencies.
US09898188B2	Information processing method and electronic device An information processing method and an electronic device are described. The method is applied to an electronic device and includes obtaining first track data of a motion of an operating body with respect to the electronic apparatus, and obtaining first identification data of the operating body; deriving first input data corresponding to the first identification data and the first track data; and the electronic apparatus responding to the first input data.
US09898187B2	Managing real-time handwriting recognition Methods, systems, and computer-readable media related to a technique for providing handwriting input functionality on a user device. A handwriting recognition module is trained to have a repertoire comprising multiple non-overlapping scripts and capable of recognizing tens of thousands of characters using a single handwriting recognition model. The handwriting input module provides real-time, stroke-order and stroke-direction independent handwriting recognition for multi-character handwriting input. In particular, real-time, stroke-order and stroke-direction independent handwriting recognition is provided for multi-character, or sentence level Chinese handwriting recognition. User interfaces for providing the handwriting input functionality are also disclosed.
US09898180B2	Flexible touch-based scrolling A computer-implemented method includes receiving user input comprising a gesture on a touchscreen, the gesture having a gesture velocity. The gesture velocity is compared with an inertia movement threshold. Based on the comparing, the gesture is determined to be an inertia gesture. When the gesture velocity is greater than or equal to the inertia movement threshold, simulated inertia is applied to visual information displayed on the touchscreen.
US09898177B2	Display processing method and portable mobile terminal A display processing method that is applied in a portable mobile terminal, to display multiple objects on a touch screen of the portable mobile terminal. The method includes obtaining a touch point that is a point created when an operating object contacts/almost touches the touch screen; determining a preset area with the touch point being the center; determining a first object and a second object, among multiple objects, each intersecting with the preset area on at least one point; determining a first information of the movement of the first object, the first information indicating moving the first object from a first position to a second position, the first position being the original position of the first object displayed on the touch screen; and moving the first object from the first position to the second position according to the first information.
US09898175B2	Home network manager for home automation A method and/or system of managing a plurality of elements of a premise having a plurality of areas via an electronic management interface. The method and/or system includes grouping via the electronic management interface a number of said elements consuming one or more commodity within said areas, and displaying via the electronic management interface a list of said areas. The method and/or system also includes selecting via the electronic management interface one or more of said areas from said displayed list, monitoring via the electronic management interface commodity data indicative of commodity consumed by said number of elements within said selected one or more areas, displaying via the electronic management interface a plurality of visualization modes of said monitored data, and displaying via the electronic management interface said monitored data based on one or more of said visualization modes.
US09898171B2	Information processing apparatus, method of controlling a lock screen displayed while the information processing apparatus is locked, and recording medium An information processing apparatus includes: a touch-enabled display; a lock portion that locks the information processing apparatus; a display controller that displays a lock screen on the display, the lock screen having a first icon for unlock and one or more second icons each representing a function, and that refreshes the lock screen, when a user moves the first icon, such that the first icon is present at a different position; an unlock portion that unlocks the information processing apparatus; a recognition portion that recognizes a function as being selected, the function being represented by the one second icon or one of the second icons being present at the position where the user releases the first icon; a user information obtaining portion that obtains user information; and an authentication portion that conducts user authentication with the obtained user information while the user is moving the first icon.
US09898167B2	Systems and methods for providing a tagging interface for external content Computer-implemented systems and methods are disclosed for providing a tagging interface for tagging external content. In accordance with some embodiments, a method is provided for tagging content external to a database system. The method comprises accessing the external content via a web browser of an electronic device. The method also comprises enhancing the web browser by providing a tagging interface for tagging at least a portion of the external content. The method further comprises receiving created tag associated with a tagged portion of the external document content, and exporting the external content and the received tag to the database system. The tagging interface can also provide an option to export the created tag to an internal database system.
US09898165B1	Taxi route recording methods on an aircraft display unit Present novel and non-trivial methods for electronically recording a taxi route on a display unit are disclosed. In one method, a tax route entry window (“TREW”) such as a taxi clearance entry window is used to present in smaller windows surfaces and next intersecting surfaces from which a pilot sequentially selects surfaces based upon surfaces stated in a taxi clearance. In another method, the TREW is comprised of an airport-specific keyboard or a traditional keyboard with visually-variable, interactive buttons, where an activation or deactivation of each button is dependent upon surfaces specified in the taxi clearance and potential intersecting surface. In another method, selections are made on the TREW and surfaces corresponding to the selections are highlighted in an image presenting a map of surfaces. Additionally, the image presenting a map of surfaces may be panned and zoom to the size of the highlighted surface.
US09898162B2	Swiping functions for messaging applications This application relates to performing organizational tasks using a variety of physical operations in a message application. The physical operations can include swiping actions performed by the user of the message application. By performing certain types of swipes on a user interface of the message application, the user can more readily organize messages stored by the message application. The types of swipes can include full swipes, which can execute one or more functions on a message, and partial swipes, which can open up a menu that includes multiple buttons for executing various operations on the message being swiped. Additionally, the direction of the swipe can also determine the functions and operations to be performed on the message being swiped.
US09898159B2	Arrangement and display of graphical elements based on designation of a point Provided is an information processing apparatus including a detection unit configured to detect a position of a first point that has been designated, and a control unit configured to display an icon at a position designated by indicating a direction from the first point.
US09898157B2	Generation of a filter that separates elements to be displayed from elements constituting data A technique to improve the efficiency for generating a filter for separating elements to be displayed from elements constituting data. At a client, a content acquisition unit acquires content from a server. A content division unit divides the content into elements. An element display unit randomly displays the elements at positions different from positions at which the elements of the content in an original form are displayed. A selected-element identification unit identifies an element selected by a user from the elements. A filter generation unit generates a filter based on the identified element and saves the filter in a filter saving unit. A filtering unit applies the filter saved in the filter saving unit to the content. A content display unit displays the filtered content.
US09898146B2	Touch panel and display device including the same A display device includes: a plurality of first electrode patterns; a plurality of second electrode patterns; a plurality of first touch signal lines; and a plurality of second touch signal lines. The plurality of first electrode patterns respectively include a plurality of first electrode cells physically separated from each other and arranged in a first direction. The plurality of second electrode patterns include a plurality of second electrode cells physically separated from each other and arranged in a second direction crossing the first direction. The plurality of first touch signal lines are connected to the first electrode cells. The plurality of second touch signal lines are connected to the second electrode cells. The first and second electrode patterns and the first and second touch signal lines are all positioned at the same layer on a substrate. The first touch signal lines are independently connected to each first electrode cell.
US09898137B2	Object positioning method for a touch panel An object positioning method for touch panel is disclosed. In the method, an amount of sensing of a sensing signal can be detected and a sensing coordinate of an object can be obtained based on the detection. A positioning coordinate of the object can be locked in a point-locked mode when the amount of sensing of the sensing signal decreases continuously to be larger than a first threshold time and the amount of sensing of the sensing signal is smaller than a first sensing threshold value. Otherwise, the point-locked mode of the positioning coordinate of the object can be unlocked when the amount of sensing of the sensing signal is larger than a first sensing threshold value.
US09898133B2	Touchscreen Malfunction of a large-sized touchscreen is prevented. In particular, malfunction of a large-sized touchscreen is prevented by reduction of wiring delay between a detection region and a controller. In a touchscreen, in which a detection area is divided, including a plurality of detection regions and a plurality of sensors, controllers are provided for the respective divided detection regions, and all the controllers are electrically connected to one central control device. It is preferable that a wiring between each of the divided detection regions and the corresponding controller be shorter than a wiring between the controller and the central control device.
US09898131B2	Display apparatus and control method of display apparatus A display apparatus including a flexible display device includes a touch detection unit that detects a touch operation to the display device, a bending detection unit that detects a bending state of the display device, and a control unit that controls an operation according to a touch operation depending on the detected bending state, where the control unit differentiates the operation according to the touch operation between a case where a portion of the display device, which is less than a predetermined bending amount, is a greater than a predetermined threshold area and a case where the portion that is less than the predetermined bending amount is less than the predetermined area.
US09898130B2	Grip management Grip management includes determining, using first changes of capacitance of a sensing region of an input device, a first signal level corresponding to a first input object satisfying a size threshold and being proximate to a first side of the input device at a first time, and determining a first signal level threshold based on the first signal level. The grip management further includes determining, using second changes of capacitance of the sensing region, a second signal level corresponding to the first input object being proximate to the first side of the input device at a second time, and detecting a squeeze of the input device based at least in part on the second signal level satisfying the first signal level threshold.
US09898129B1	Displays with functional bezels Displays with functional bezels and methods for providing functional bezels to displays are disclosed. A display may include a touch screen, a bezel surrounding the touch screen, and a touch-sensitive zone extending along the bezel. The touch-sensitive zone may be configured to define a secondary touch location. The secondary touch location may be configured to operate jointly with the touch screen to support multi-touch operations.
US09898128B2	Sensor signal processing circuit and sensor signal processing method A sensor signal processing circuit is connected to a sensor including first and second conductors arranged in different directions. The sensor signal processing circuit includes: a signal supply circuit configured to supply a first signal to the first conductor; a first signal detecting circuit connected to the second conductor; and a control circuit configured to perform control of detecting a proximity of an indicator to the sensor based on a change in a capacitance between the second conductor and a ground, and detecting a position indicated by the indicator based on a change in a capacitance at an intersection point of the first and second conductors by controlling the signal supply circuit and the first signal detecting circuit based on a comparison between a predetermined value and a detection result based on the change in the capacitance between the second conductor and the ground.
US09898120B2	Watch type mobile terminal and control method for the mobile terminal Disclosed is a watch type mobile terminal wearable on a wrist. The watch type mobile terminal includes a main body, a band unit, a sensing unit and a controller. The main body has a display unit. The band unit is connected to the main body so that the mobile terminal is worn on the wrist, and surrounds the wrist. The sensing unit senses at least one tap applied to at least one of the main body and the band unit. The controller configured performs a function corresponding to a pattern to which the tap is applied.
US09898116B2	Touch panel having multiple electrodes with reduced number of pins A touch panel including a substrate and a touch element is provided. The substrate has a first predetermined number of touch areas. Each of the touch areas has a second predetermined number of sub touch areas. The touch element includes a plurality of first electrodes, a plurality of second electrodes, a plurality of third electrodes and the first predetermined number of fourth electrodes. Multiple of the first electrodes arranged along a first direction and corresponding to different sub touch areas are electrically connected, multiple of the second electrodes arranged along a second direction and corresponding to different sub touch areas are electrically connected, and multiple of the third electrodes corresponding to different touch areas are electrically connected.
US09898111B2	Touch sensitive device and method of touch-based manipulation for contents A touch sensitive device allows a touch-based manipulation for contents displayed thereon. In a method, the device receives a predefined input event when a content screen is displayed on a display unit, determines whether a closed curve is formed on the display unit by the input event, and crops a specific content region defined by the closed curve.
US09898110B1	Mouse pad, input system and pairing method thereof An embodiment of the present disclosure provides a mouse pad. The mouse pad includes a substrate and storage module. The substrate includes a first surface. A mouse device can move on the first surface. The storage module is located in the substrate for surface parameters of the first surface of the mouse pad, operation parameters or calibration parameters of the mouse device. When the mouse device moves on the first surface, the mouse device executes an optimization process to generate the calibration parameters according to the surface parameters, and the mouse device transmits the calibration parameters to the mouse pad.
US09898107B1	Tactile input contol data modifying system, device, and method A tactile control device and method for generating a modifier through the use of fuzzy logic for modifying control data responsive to a user's tactile input with the device are disclosed. The system may include one or more measurements corresponding to one or more interfering factors, a source of control data representative of a command generated in response to the user's tactile interaction, and a processing unit (PU). The PU may be configured to receive input data representative of at least one measurement corresponding to a measurement(s) of an interfering factor, determine a plurality of values based upon the measurement(s) and a plurality of first functions, determine a control data modifier based upon the plurality of values, and generate data representative of the modifier, where the modifier may be applied to the control data or data correspond to the control data.
US09898102B2	Broadcast packet based stylus pairing Examples are disclosed herein that relate to pairing styluses to an interactive display. One example provides a stylus comprising a processor and memory holding instructions executable by the processor. The instructions are executable by the processor to, before sending a pairing request to a display, receive a broadcast packet indicating an occupancy of a set of stylus communication slots of the display, determine that at least one stylus communication slot is available based on the broadcast packet, and responsive to determining that the at least one stylus communication slot is available, selectively send the pairing request to occupy a stylus communication slot based on a pairing request history.
US09898101B2	Input device and electronic information board system with a movable object movable in a slant direction An input device includes a casing having a concave compartment having an inner bottom end, the concave compartment formed at one end of an axis direction of the casing, a moveable object supported in the concave compartment and reciprocally moveable along the axis direction of the casing, and a transmitter to transmit a contact-detection signal of the input device contacting on a display face when the moveable object is pressed and moved into the inner bottom end of the concave compartment for a given distance. When the moveable object is pressed along the axis direction of the casing, the moveable object is moved into the inner bottom end along the axis direction of the casing, and when the moveable object is pressed along a direction slanted from the axis direction of the casing, the moveable object is moved into the inner bottom end along the slanted direction.
US09898100B2	Authenticating stylus device Various methods and systems for authenticating and identifying stylus devices are described herein. In one example, a method includes receiving a value generated by the stylus device during an initialization stage. The method includes receiving a code generated from the stylus device during an authentication stage. The method also includes cryptographically authenticating an author of digital ink corresponding to the stylus device on a computer device based in part on the value and the received code.
US09898095B2	Low-profile capacitive pointing stick In an example, an isometric input device configured to control a user interface indicator of an electronic device includes a plurality of sensor electrodes disposed on a sensor substrate. The input device further includes a control member mechanically coupled to the sensor substrate over at least a portion of the plurality of sensor electrodes. The input device further includes a conductive support substrate and a compliant member disposed between the sensor substrate and the conductive support substrate. The input device further includes a securing component extending through the conductive support substrate and the compliant member and engaging with the control member, the securing component defining a gap between the sensor substrate and the conductive support substrate.
US09898086B2	Systems and methods for visual processing of spectrograms to generate haptic effects Systems and methods for visual processing of spectrograms to generate haptic effects are disclosed. In one embodiment, a signal comprising at least an audio signal is received. One or more spectrograms may be generated based at least in part on the received signal. One or more haptic effects may be determined based at least in part on the spectrogram. For example, a generated spectrogram may be a two-dimensional image and this image can be analyzed to determine one or more haptic effects. Once a haptic effect has been determined, one or more haptic output signals can be generated. A generated haptic output signal may be output to one or more haptic output devices.
US09898085B2	Haptic conversion system using segmenting and combining A system is provided that converts an input into one or more haptic effects using segmenting and combining. The system receives an input. The system further segments the input into a plurality of input sub-signals. The system further converts the plurality of input sub-signals into a haptic signal. The system further generates the one or more haptic effects based on the haptic signal.
US09898084B2	Enhanced dynamic haptic effects A system is provided that generates a dynamic haptic effect that includes one or more key frames, where each key frame includes a first interpolant value and a first haptic effect. The system further receives an interpolant value, where the interpolant value is between at least two interpolant values of at least two key frames. The system further determines the dynamic haptic effect from the interpolant value. The system further distributes the dynamic haptic effect among a plurality of actuators.
US09898080B2	Method and apparatus for eye tracking A method and apparatus for eye tracking are disclosed. The method may include obtaining feature points corresponding to at least one portion of a face area of the user in an image, determining an inner area of an eye area of a first eye of the user based on the feature points, determining a pupil area of the user based on a pixel value of at least one pixel of the inner area, and determining an eye position of the user based on a position value of each pixel of the pupil area.
US09898079B2	Graphical user interface for non-foveal vision A device may be configured to provide a graphical user interface that is specifically designed for use in a person's non-foveal vision. Via a graphical user interface for non-foveal vision, a user may interact with the device without focusing his or her foveal vision on a touchscreen of the device. Thus, the user may operate the device and its applications entirely and exclusively without using his or her foveal vision. For example, the user may operate the device exclusively using his or her peripheral vision or using no vision whatsoever.
US09898073B2	Updating firmware and configuration of a computer system by a system management controller during power on reset state For system management applied to a computer system, a power supply of the computer system starts to power a motherboard and a CPU thereon. A reset holding module in a system management controller holds the CPU in a Power-on Reset (PoR) state. The system management controller executes an operation requested by a user. The reset holding module releases the CPU from the PoR state in response to the system management controller completing the operation.
US09898072B2	Semiconductor integrated circuit and circuit operation method The power consumption of a data sampling unit that selects a phase of a clock signal appropriate for sampling payload data is reduced at an input interface. A semiconductor integrated circuit includes an input interface and internal core circuits. The input interface includes a hysteresis circuit and a data sampling unit. The hysteresis circuit detects an input signal between first and second input thresholds as a sleep command. The data sampling unit selects an appropriate phase of a sampling clock signal in accordance with a synchronizing signal and samples payload data. When a sleep command is detected, a sleep signal is also supplied to the internal core circuits and the data sampling unit and they are controlled into a low-power consumption state.
US09898071B2	Processor including multiple dissimilar processor cores In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.
US09898068B2	Semiconductor device, electronic device, and method for controlling semiconductor device A semiconductor device includes a CPU core, a frequency regulating circuit, and a frequency control circuit. The frequency regulating circuit includes a table. The frequency control circuit provides a clock to the CPU core. The CPU core outputs an operating state signal indicating an operating state of the CPU core. The frequency regulating circuit controls a frequency of the clock based on the table and the operating state signal. Thus it is possible to provide a semiconductor device that allows performance to follow a dynamically changing load.
US09898066B2	Method and apparatus to configure thermal design power in a microprocessor A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.
US09898065B2	Wake-up circuit for a security device An exemplary security device includes a reader configured to read information stored on a credential device. The reader enters a sleep mode when not reading a credential device. A wake-up module includes an inductively coupled resonant circuit. The wake-up module is configured to detect a credential device near the reader if the credential device has a resonant frequency corresponding to a frequency of an electromagnetic field of the inductively coupled resonant circuit that is controlled by a stable oscillator. The wake-up module is configured to provide an indication to wake-up the reader from the sleep mode responsive to detecting a change in power of the electromagnetic field caused by the credential device.
US09898063B2	Touch input determining method which can determine if the touch input is valid or not valid and electronic apparatus applying the method An electronic apparatus comprising an environment sensing device, a display, a touch sensing device, and a processing module comprising a main controller and a sub-controller is disclosed. The main controller performs a predetermined function based a touch input. The sub-controller computes a tilt angle of the electronic apparatus, and activates the touch sensing device without turning on the display if the tilt angle falls in a predetermined angle range, while the main controller is in the sleep mode. The processing module performs following steps when the display is off: determining the touch input is valid or invalid; keeping the display off if the touch input is invalid. The sub-controller wakes and activates the main controller to turn on the display and to control the electronic apparatus to perform the predetermined function according to a gesture formed by the touch input if the touch input is valid.
US09898062B2	Systems and methods for protection of components in electrical power delivery systems Various embodiments disclosed herein provide protection to monitored equipment at both a local level and a system level, in order to offer more comprehensive protection. In one particular embodiment, the protected equipment may include one or more generators. The protection system may utilize time-synchronized data in order to analyze data provided by systems having disparate sampling rates, that are monitored by different equipment, and/or equipment that is geographically separated. Various embodiments may be configured to utilize a variety of sampling rates.
US09898061B2	Resource capacity management in a cluster of host computers using power management analysis A resource management system and method for performing resource capacity management in a cluster of host computers uses a snapshot of the cluster with one or more ghost host computers added to the cluster to execute a power management analysis. A ghost host computer is a fictitious construct based on a physical host computer. The results of the power management analysis may then be used as a cluster capacity recommendation to increase resource capacity of the cluster of host computers.
US09898060B2	System and method for wireless power transfer using automatic power supply selection A system and method of wireless power transfer using automatic power supply selection includes an electronic system. The electronic system includes an electronics module, a primary power supply that receives power from a primary external power source, a secondary power supply that receives power from a secondary external power source, and a selection module. When the primary power supply is operative, the selection module selects the primary power supply to supply power to the electronics module and disables the secondary power supply. When the primary power supply is not operative and the secondary power supply is operative, the selection module selects the secondary power supply to supply power to the electronics module. When the secondary power supply is disabled, the secondary power supply disables the secondary external power source.
US09898059B2	Dynamic control of power consumption based on memory device activity A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.
US09898057B2	Fan fixing device A device for fixing a heat dissipation fan in a computer includes a cage, a handle, and a movable portion. The handle is rotatably fixed on the cage, the handle has a pushing pole and holes are defined at each distal end. The movable portion is movably and elastically connected to the cage. The movable portion includes a plate with opposite ends, a sloping sheet connected with the plate at one end, and a protrusion extending from the plate at the same end as the sheet.
US09898055B1	Securing mechanism for data storage device A data storage device securing mechanism includes a rack and a securing module. The rack includes a shell and two side plates connected to the ends of the shell. The securing module includes a slidable bracket on the rack and a magnetic latching member. The bracket includes two magnets of opposing poles against two magnetic blocks, and the latching member is rotatably installed on the side plate. When the bracket is slid in the rack, the two magnetic blocks are displaced adjacent to the latching member, to attract or to repel the latching member. The latching member is thereby rotated to approach or to move away from the side plate.
US09898054B2	Near zero force grounding feature An electronic device can include first and second housing components and an electrical grounding feature located therebetween to provide a grounding path. The grounding feature can include an outer portion formed from an electrically conductive material and an internal region containing a removable expansion element. The grounding feature can exert an expansion force against the housing components when the device is assembled and the expansion element remains, and exert no expansion force against the housing components when the expansion element is removed. The device can also include an adhesive coupling the electrical grounding feature to the housing components, which adhesive can be electrically conductive. The expansion element can be deformable and removable from an open end of the grounding feature outer portion, which outer portion can be elastic and can deform to contact more of the housing components when the grounding feature is compressed therebetween.
US09898053B2	Electrode member and touch panel including the same Disclosed is a touch panel. The touch panel includes a substrate, and an electrode part formed in a mesh shape on the substrate. The electrode part includes a resin layer comprising first and second sub-patterns, and a transparent electrode on the first sub-pattern. A ratio of a width of the first sub-pattern to a width of the second sub-pattern is in a range of 1:0.01 to 1:0.5.
US09898051B2	Hinge device According to the hinge device of the present invention, a hinge part connecting a first body part and a second body part forming a multimedia apparatus for the hinge device is provided, where the hinge part includes a plurally-arranged hinge blocks.
US09898049B2	Handheld device enclosure having outer periphery members and a front cover assembly This is directed to an electronic device enclosure. The enclosure includes an outer periphery member forming an outer surface of a device, and to which an internal platform is connected. Electronic device components can be assembled to one or both surfaces of the internal platform. The enclosure can include front and back cover assemblies assembled to the opposite surfaces of the outer periphery member to retain electronic device components. One or both of the cover assemblies can include a window through which display circuitry can provide content to a user of the device.
US09898048B2	Interconnectable electronic device with magnetic rail An electronic device includes a plurality of magnetic guide rails proximate its surface. The electronic device may be interconnected to a second electronic device in a configuration in which the second electronic device is located at a pre-defined position relative to the electronic device. The plurality of magnetic guide rails in the electronic device interact with at least one magnetic element on the second electronic device to magnetically guide relative movement of the two electronic devices. As one electronic device is urged along a surface of the other toward the pre-defined position, the electronic devices are positioned in the configuration of the pre-defined position.
US09898046B2	Bendable glass stack assemblies, articles and methods of making the same A glass element having a thickness from 25 μm to 125 μm, a first primary surface, a second primary surface, and a compressive stress region extending from the first primary surface to a first depth, the region defined by a compressive stress σI of at least about 100 MPa at the first primary surface. Further, the glass element has a stress profile such that it does not fail when it is subject to 200,000 cycles of bending to a target bend radius of from 1 mm to 20 mm, by the parallel plate method. Still further, the glass element has a puncture resistance of greater than about 1.5 kgf when the first primary surface of the glass element is loaded with a tungsten carbide ball having a diameter of 1.5 mm.
US09898044B2	Docking station and mobile terminal with the same The disclosure provides a docking station and a mobile terminal with the docking station. The docking station includes a docking main body, a shelter, a first link mechanism, a second link mechanism and a moveable locking bar. The shelter shields the connector and the moveable locking bar is stayed in an unlocked position when the docking station is free. When the mobile terminal is coupled with the docking station, the first link mechanism is driven by the mobile terminal, the shelter is forced to rotate to a predetermined storage position, and the second link mechanism drives the moveable locking bar to a locked position to lock the mobile terminal. The docking station is easy to use with simple process of assembly and adjustment.
US09898042B2	Smart device docking apparatus A docking apparatus is provided. The docking apparatus includes a host mount and a smart device mount. The host mount includes a base plate. At least one hinge clip is pivotally secured to the base plate by a binder post. The hinge clip is resiliently biased towards the base plate by a spring. A turn table is secured to an upper surface of the base plate and rotatable about a first axis. A hinge arm includes a first end pivotally attached to an upper surface of the turn table. The first end is rotatable about a second axis, such as a horizontal axis, substantially perpendicular to the first axis. The smart device mount is secured to a second end of the hinge arm and is operable to releasably retain a smart device.
US09898040B2	Configurable dock storage A docking scheme enables storage systems to adapt different storage configurations to different clients. Dock configurations identify reconfigurable sets of storage extensions for executing storage operations in a resource node. The resource node receives storage requests from clients and identifies the dock configurations associated with the clients. The resource node then generates a set of storage operations that implement the storage extensions for the identified dock configuration and uses the storage operations to execute the storage requests. Different clients may thus access the same stored data through different docks resulting on different operations within the resource node with the aim of optimizing performance for all clients.
US09898036B2	Apparatus and method for automatically aligning data signals and strobe signals on a source synchronous bus An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a Joint Test Action Group (JTAG) interface, and a bit lag control element. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network includes replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to adjust a propagation time. The bit lag control element is configured to measure the propagation time beginning with assertion of the first signal and ending with assertion of the second signal, and is configured to generate a first value on a lag bus that indicates an adjusted propagation time. The bit lag control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control is configured to select one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and is configured to generate a second value on a lag select bus that indicates the propagation time, where the delay lock control selects the one of a plurality of successively delayed versions of the first signal by incrementing and decrementing bus states of select inputs on a mux, and where the plurality of successively delayed versions includes inputs to the mux, and where the plurality of successively delayed versions includes outputs a first plurality of series-coupled matched inverter pairs. The adjust logic is coupled to the JTAG interface and to the lag select bus, and is configured adjust the second value by the amount prescribed by the JTAG interface to yield a third value that is output to an adjusted lag bus. The gray encoder is configured to gray encode the third value to generate the first value on the lag bus.
US09898035B2	Clock synchronization method The first synchronous FF is disposed at the starting point of the clock tree of the frequency-divided clock of each lower hierarchical block, and the first maximum delay time of the reference clock from the branch point of the reference clock and the frequency-divided clock to the first synchronous FF is acquired. The second maximum delay time of the reference clock between adjacent two of second synchronous FFs is determined so as to be less than half the period of the reference clock. The number of stages of the second synchronous FFs is determined according to the first and second maximum delay times. The target delay time from the branch point is determined so as to be not more than the second maximum delay time, and the second synchronous FF and a latch are disposed so as to achieve the target delay time.
US09898033B1	Magnetic spring inceptor A magnetic spring input device is disclosed. In various embodiments, an input device as disclosed includes a manual input structure movably coupled to a base assembly; and a non-stationary magnet fixedly coupled to the manual input structure; a stationary magnet coupled to the base assembly in a manner that is fixed with respect to at least a first input axis of the input device, the stationary magnet being coupled to the base assembly with a first magnetic pole having a first magnetic polarity is oriented opposite a corresponding magnetic pole of the non-stationary magnet having the first magnetic polarity, in a position that is adjacent to but offset from the non-stationary magnet when the manual input structure is in a neutral position. The non-stationary magnet is coupled to the manual input structure in a position such that movement of the manual input structure about or along the first input axis of the input device brings said poles have said first magnetic polarity within sufficient proximity to generate a repulsive magnetic force.
US09898031B1	Clutch pedal extender A clutch extender which is positioned between the free end of a clutch pedal arm and a clutch pedal.
US09898027B2	Station building power supply device A station building power supply device according to the present invention includes: a station building power generation unit including an inverter main circuit and an inverter control circuit to control the inverter main circuit, in which the inverter main circuit converts a voltage supplied from an overhead wire into a voltage required by loads in a station building; a control-circuit power generation unit that converts a voltage supplied to the loads in the station building and generates an input voltage for the inverter control circuit; and a start-up power generation unit that converts a voltage supplied from the overhead wire and generates an input voltage for the inverter control circuit, in a state where the inverter main circuit has stopped the operation and the control-circuit power generation unit has stopped an operation of generating the input voltage for the inverter control circuit.
US09898026B2	Power distribution apparatus with input and output power sensing and method of use Power distribution apparatus with input and output power sensing and a method of use. A power distribution unit includes a sensor that senses power parameters of power outputs and a power input, a processor, and a communication circuit. A power management system includes a power manager, a user interface, and a plurality of power distribution units that may be located in one or more equipment cabinets and data centers. The system may compute apparent power, RMS power, power factor, energy usage over time, power usage history, or environmental history for any or all of the power distribution units. The system may identify an under-utilized server connected to one of the power distribution units and initiate a shut-down of that server.
US09898025B2	Balancing power supply and demand A method and apparatus to balance adapter power supply and computing device power demand. In one embodiment, power to/from battery pack(s) maybe controlled by adjusting the output voltage of the power adapter via the current input to the power adapter through a feedback pin to meet power demand of electrical loads. Another embodiment provides a way to adjust the activities of the electrical loads such that neither adapter power rating nor the electrical load power limit is exceeded while avoiding system shutdown.
US09898024B2	Energy consumption modeling Methods, devices, and systems for energy consumption modeling are described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to assign energy consumption data to an on state and an off state of a device, generate a model configured to predict a future state of the device and a duration of the future state based on a duration of a current state of the device, a duration of a previous state of the device, and operating conditions of the device, and predict a future energy consumption of the device using the assigned energy consumption data and the generated model.
US09898022B2	Power sharing device and method thereof A power sharing device and method thereof are disclosed herein. The power sharing device includes a control unit, multiple regulators and multiple feedback circuits. Each regulator includes a first input terminal, a second input terminal and an output terminal. The control unit generates multiple pulse-width modulation signals. The first input terminal receives one of multiple input voltages. The second input terminal receives one of the pulse width modulation signals. The output terminal selectively outputs an output power. Each feedback circuit is coupled between the second input terminal and the output terminal of one of the regulators. The output terminals of the regulators are coupled to a load, and the regulators selectively output the output power one at a time and in rotation according to the input voltages and duty cycles of the pulse-width modulation signals.
US09898020B2	Power supply voltage priority based auto de-rating for power concurrency management Particular embodiments include logic that can reduce an voltage output of a regulator to multiple subsystems in response to detecting high power conditions in an electronic device. When the power being monitored goes up, the logic detects the increase in power. Then, the logic can compare the power to a plurality of thresholds. The plurality of thresholds may be set below an absolute limit threshold in which the electronic device may not operate properly if the absolute limit is met. When a first threshold is met, the output voltage of the regulator may be decreased until a minimum voltage level is reached. When a second threshold is met, the output voltage may be increased until a maximum voltage level is reached. The minimum and maximum voltage levels may be based on voltage levels requested from a set of subsystems and also priority levels associated with those subsystems.
US09898017B2	Thermostatic mixing valve Embodiment thermostatic valves are protected against damage to the wax motor from the leakage of hot water into the valve when the hot water inlet is closed. Embodiments include an improved temperature motive means with fewer parts than conventional valves and with an improved sealing relation between the wax motor/shuttle and the water ports.

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