| Document | Document Title |
|---|---|
| US09749313B2 |
Protection from unfamiliar login locations
In one embodiment, a user authentication server may use geo-location tracking to determine whether to present an enhanced identity challenge. A communication interface 180 may receive a user login attempt by a user and a current location of the user login attempt. A data storage 150 may store a user location profile of the user. A processor 120 may execute a comparison of the current location to the user location profile. The communication interface 180 may present the user with an enhanced identity challenge before allowing user access based on the comparison. |
| US09749311B2 |
Policy based compliance management and remediation of devices in an enterprise system
The present disclosure relates generally to managing compliance of remote devices that access an enterprise system. More particularly, techniques are disclosed for using a compliance policy to manage remediation of non-compliances of remote devices that access an enterprise system. A device access management system may be implemented to automate remediation of non-compliances of remote devices accessing an enterprise system. Remediation may be controlled based on different levels of non-compliance, each defined by one or more different non-compliances. In some embodiments, a level of non-compliance may be conditionally defined by one or more user roles for which non-compliance is assessed. Access to computing resources of an enterprise system may be controlled for a remote device based on compliance of the remote device. Access may be inhibited for those resources not permitted during a time period of a non-compliance. |
| US09749309B2 |
Identity management system
A system comprising an IMS network (104), an adapter module (106), an identity provider (108) and an application (110) is described. The adapter module (106) is within an IMS trust domain. The application (110) is within the trust domain of the identity provider. A user of the system can access the application (110) via the IMS network (104), regardless of whether the application is within the IMS trust domain, by making use of the adapter module (106) to obtain the user's user credentials for the application from the identity provider. |
| US09749306B2 |
Method, device and communications system for network convergence
Embodiments of the present invention provide a method, a device and a communications system for network convergence, which can support a charging manner of a network to which an access user belongs. The method for network convergence includes: after authentication of an access user is successful, receiving, by a second gateway, a PDN connection establishment message corresponding to the access user, where the message carries an access user identifier and is sent by a first gateway, the first gateway is a gateway of a first network in which the access user is currently located, and a service borne by the PDN connection corresponding to the access user includes a network side service of the access user in the first network; and initiating, by the second gateway, according to the access user identifier, a charging procedure corresponding to the access user. |
| US09749305B1 |
Malicious client detection based on usage of negotiable protocols
A destination server receives an application layer request, including a user-agent and one or more cipher suites, from a user client to initiate a secure communications channel. In response to the request, the destination server obtains from a user-agent database a set of one or more cipher suites that are supported by a user agent corresponding to the user-agent provided by the user client. The destination server uses this set of one or more cipher suites to determine if the user client fails to support any of these cipher suites. If the destination server determines, based on the set of one or more cipher suites, that the user client fails to support any of these cipher suites, the destination server initiates one or more security measures. |
| US09749300B1 |
Method and system for immediate recovery of virtual machines encrypted in the cloud
Example embodiments of the present invention relate to a method and a system for immediate recovery of virtual machines encrypted in the cloud. The method includes retrieving at least a portion of data from an off-premise replica site configured to store an encrypted first data part of an I/O as data at the off-premise replica site according to a second metadata part of the I/O. The first data part of the at least the portion of the data then may be decrypted at the on-premise recovery site according to a private key not available to the replica site and stored at the on-premise recovery site in a cache at the recovery site. |
| US09749297B2 |
Manicoding for communication verification
Verifiable, secure communications between a sender and a receiver on at least one shared communication channel is provided. A manicoded key encoder produces an argument of knowledge for a secret key to the at least one shared communication channel, and a manicoded message encoder provides an implication argument indicating that knowledge of the secret key enables access to message content of the manicoded message. The argument of knowledge is included in a key manifest for the secret key within a manicoded key, and the implication argument is included in a message manifest of a manicoded message. In this way, the sender may provide message content within the manicoded message, and the receiver may operate a decoder to access the message content. A verifier may use the manicoded key and the manicoded message to verify that the receiver has access to the message content. |
| US09749295B2 |
Systems and methods for internet traffic analysis
Generally discussed herein are systems, apparatuses, and methods for internet traffic analysis. In one or more embodiments, a system can include a web proxy server to receive, from a client, a request to download content from an internet, produce a request to the internet for the content, receive the content from the internet, and produce a malware analysis request in response to receiving the requested content and a malware server communicatively connected to the web proxy server, the malware server to receive the malware analysis request and the content from the web proxy server, and issue a response to the malware analysis request indicating whether to allow the content to be downloaded to the client. |
| US09749289B2 |
Infrastructure coordinated media access control address assignment
Described herein are systems, devices, techniques and products for managing the dynamic assignment of media access control (MAC) addresses to wireless network devices, such as by identifying a dynamically assigned MAC address before, after, or during a wireless association process and communicating the dynamically assigned MAC address to a wireless network device. Also disclosed are systems, devices, techniques and products for preventing a denial of service attack on a wireless access point's association table, such as by requiring devices that associate with a wireless access point to respond to a query from the wireless access point shortly after association. |
| US09749286B2 |
Method and system for optimized load balancing across distributed data plane processing entities for mobile core network
A system and an algorithm in a mobile core network to distribute the data load across multiple data processing entities. The system is seen as having one data plane entity to the external entities like routers; hence the system can scale without needing to update the external nodes. In general when a data plane processing entity is added or removed, a new distribution rule is provided to the remaining data plane processing entities. Only after some number of sessions have been migrated does the new distribution get provided to the data distribution entities. This delay allows sufficient sessions to be migrated to minimize the overall number of packets that have to be forwarded for processing. This benefit can be maximized by taking advantage of cellular network's idle mode behavior and by migrating the sessions while they are in idle mode. |
| US09749285B2 |
Connected home control system with auto router port configuration and DDNS registration
A network based product enables browser based computers, smart phones or tablets to connect to and access the product. A local router can be automatically configured by the product. The product can be automatically registered with a DDNS server and a user account opened. Authentication can be carried out between the product and the server. |
| US09749282B2 |
Electronic device and methods of updating and managing application status information in the electronic device
Provided are an electronic device and methods of updating and managing application status information of an application in the electronic device. The method of updating application status information in an electronic device may include detecting a change from first device status information to second device status information from among a plurality of device status information settings stored in the electronic device; and updating application status information of at least one application mapped to the second status information. |
| US09749281B2 |
Dynamic adaption of electronic routing slips for financial messaging
Embodiments of the present invention disclose a method, computer program product, and system for generating a routing slip for a message. A computer system determines an appropriate sub-flow for the message. The sub-flow dictates a sequence of processing steps for the message. The computer system generates a routing slip for the message based on the appropriate sub-flow. The routing slip provides an order for executing one or more processing steps of the sub-flow. The computer system associates the routing slip to the message. The processing steps of the sub-flow are executed by the computer system according to the routing slip. In an embodiment, the message is a financial message describing at least one financial transaction. |
| US09749280B2 |
Techniques for reliable messaging for an intermediary in a network communication environment
The present disclosure relates generally to techniques for improving reliability of message communications. In certain embodiments, techniques are described for facilitating reliable communication of messages between a source (e.g., a client system) and a destination (e.g., a target system) via an intermediary communication handler system. In certain embodiments, a message can include a request to be communicated to a destination for a target service. An intermediary communication handler system can store information indicative of the delivery status for a message to ensure reliable communication. The information indicative of the delivery status for a message can be managed in association with a unique identifier corresponding to the message. The information indicative of the delivery status for a message may also be used to determine whether to retry communication of a message in satisfaction of reliability parameters (e.g., QoS criteria) specified for a communication protocol used for communication of the message. |
| US09749269B2 |
User terminal and method of displaying lock screen thereof
An example user terminal device includes a display unit, including a display, configured to display a lock screen. The lock screen includes content representative information representing content included in a message that is provided by an acquaintance of a user of the user terminal device, and a first user interface element. A control unit, including a processor, is configured to, when a user input signal is received via the first user interface element, execute an application capable of reproducing the content and to reproduce the content. |
| US09749261B2 |
Arrangements and methods for minimizing delay in high-speed taps
Methods and arrangements are provided for minimizing delay in a high-speed tap arrangement are disclosed and include hardware and software arrangements and methods for quickly switching the transmission path for data between a primary data path and a bypass data path. The switching is accomplished rapidly using set of powered analog switches and a relay to minimize packets loss in the event of power loss. Further, when power is restored, software and hardware methods and arrangements disclosed herein permit the data path to be promptly restored resulting in the restoration of tapping ability quickly after power is restored. |
| US09749248B2 |
System and method for feedback based traffic management
A communication system that may include a traffic management module and a communication interface module. The communication interface module is arranged to: estimate a status of multiple channels by utilizing hardware channel status estimators, generate filler packets in response to the status of the multiple channels; wherein the filler packets are associated with the multiple channels; send the filler packets to the traffic management module. The traffic management module is arranged to receive multiple input packets that are associated with multiple channels, receive the filler packets; apply a traffic management scheme on the multiple input packets and the filler packets to provide multiple intermediate packets that comprise (a) multiple filler traffic managed packets and (b) multiple non-filler traffic managed packets. |
| US09749243B2 |
Systems and methods for optimizing network traffic
Systems and methods for optimizing network traffic are disclosed. In one embodiment, a system for optimizing the performance of a plurality of networks includes a first terminal device, a traffic steering controller, and a terminal traffic steering agent. The traffic steering controller may be configured to receive user profiles and network performance metrics and create traffic steering rules based on the user profiles and network metrics. The terminal traffic steering agent may be configured to receive traffic steering rules from the traffic steering controller and direct a virtual network switch based on the traffic steering rules. The virtual network switch may be configured to receive network traffic at a virtual network interface and, based on directions received from the traffic steering controller, forward the network traffic to a physical interface of at least one of the plurality of networks. |
| US09749242B2 |
Network platform as a service layer for open systems interconnection communication model layer 4 through layer 7 services
According to one aspect of the concepts and technologies disclosed herein, a cloud computing system can include a hardware resource and a Network Platform as a Service (“NPaaS”) layer. The NPaaS layer can expose a cloud service for use by a service that operates within at least one of layer 4 through layer 7 of the Open Systems Interconnection (“OSI”) communication model. The cloud service can include a database service, an application container service, a resource broker service, a load balancer service, a domain name system (“DNS”) service, a state persistence service, a probe service, or a combination thereof. The NPaaS also can receive a request for the cloud service, and in response to the request, can provide the cloud service. |
| US09749236B2 |
Increased network scalability by router aware switches
Handling of ELS REQ and RSP packets that contain addresses in the payload is shifted to the edge fabric switches connected to the node devices issuing and receiving the ELS REQ packet, the ingress and egress switches. This allows the ELS REQ and RSP packet payload address modification operations to be removed from the tasks handled by the router processor. As this removes a processing burden from the router processors, those router processors are free to handle other normal operations, thus allowing more processor bandwidth to be provided to those other operations, which allows further growth of the network as one limitation has been removed. The need to replicate or provide commands between switches or routers is avoided as there are no redundant paths at that point. |
| US09749235B2 |
Packet retransmission
Through the identification of different packet-types, packets can be handled based on an assigned packet handling identifier. This identifier can, for example, enable forwarding of latency-sensitive packets without delay and allow error-sensitive packets to be stored for possible retransmission. In another embodiment, and optionally in conjunction with retransmission protocols including a packet handling identifier, a memory used for retransmission of packets can be shared with other transceiver functionality such as, coding, decoding, interleaving, deinterleaving, error correction, and the like. |
| US09749228B2 |
Tunnel provisioning with link aggregation
A method for processing data packets in a communication network includes establishing a path for a flow of the data packets through the communication network. At a node along the path having a plurality of aggregated ports, a port is selected from among the plurality to serve as part of the path. A label is chosen responsively to the selected port. The label is attached to the data packets in the flow at a point on the path upstream from the node. Upon receiving the data packets at the node, the data packets are switched through the selected port responsively to the label. |
| US09749224B2 |
Method and apparatus for cloud provisioning of communication services
An approach for cloud provisioning of consumer services based on requested services. The approach uses customer request for services and current network utilization patterns to most efficiently and effectively provision network resources. For example, a network manager establishes one or more terms for a cloud provider based on one or more provider network provisions. The network manager further determines a customer profile subscription based on customer credentials, cloud provider credentials, and a combination thereof. Then, the network manager delivers one or more credentials based on the cloud provider, and generates a routing path to the cloud provider based on the subscription and/or service request. |
| US09749211B2 |
Detecting network-application service failures
A computer-implemented process for detecting service failures of a network application under test involves collecting raw network-application availability monitoring (NAAM) data. The NAAM data can include datapoints, each which specifies the network application under test, a respective test site; a time corresponding to a respective probe, and an indication whether the respective probe resulted in a success or a failure. The raw NAAM data is filtered to remove datapoints indicating failures associated with causes other than a service failure of the NAUT. The filtered NAAM data is analyzed to detect a service failure of the NAUT. |
| US09749209B2 |
Methods and apparatus to credit background applications
Methods, apparatus, systems and articles of manufacture are disclosed which credit background applications. Examples disclosed herein set a threshold for bandwidth activity based on the bandwidth pattern. Examples disclosed herein compare a bandwidth usage of the application executing in the background to the threshold for bandwidth activity. Examples disclosed herein determine a state of the application executing in the background as one of active or inactive based on the comparing, and generate a log file comprising an identification of the application, a timestamp, and the state of the application. |
| US09749204B2 |
Method of data delivery across a network
The present invention provides a method of preserving packet ordering in a multipath network having a plurality of network elements interconnected by network links wherein for each data packet arriving at an egress port of the multi-path network, a delivery acknowledgement is issued by the egress port and is transmitted across the network following in reverse the path taken by the data packet being acknowledged. The state of each link in the path taken by the data packet being acknowledged is updated by the acknowledgement. The present invention further provides a multi-path network for use in a bridge, switch, router, hub or the like, the multi-path network comprising a plurality of network ports; a plurality of network elements; and a plurality of network links interconnecting the network elements and the network ports for transporting data packets, each network egress port including an acknowledgement mechanism for issuing a delivery acknowledgement in response to receipt of a data packet and each network element being adapted to transmitted a delivery acknowledgment in the opposite direction along the path taken by the data packet being acknowledged and being further adapted to update the state of at least one of the network links to which it is connected in response to receipt of an acknowledgement. The invention further provides an Ethernet bridge or router incorporating such a multi-path network. |
| US09749200B2 |
Method and apparatus for detecting application
Provided is a method for detecting an application in a wireless communication system. The method includes receiving and inspecting a packet; detecting flows from the packet using a predefined signature; granting a score to each of the detected flows, and summing the granted scores by integrating the detected flows for each application; comparing the summed score of the flows integrated for each application with a preset value; and determining that an application is detected, if the summed score is greater than the preset value. |
| US09749199B2 |
Dynamically determining packet sampling rates
For dynamically determining packet sampling rates, a method including setting a packet sampling rate for one or more switch ports, collecting for an interval of time a plurality of statistics for the one or more switch ports, and adjusting the packet sampling rate in response to one or more of the plurality of statistics. |
| US09749198B2 |
Methods and systems for monitoring computer systems using wireless devices
Methods and systems for providing information regarding monitored computer systems to wireless devices are provided. Information may be requested by a wireless device and displayed on the wireless device in a browser. The web server application may detect the wireless device, and may also then specially format the response, including the requested information formatted for optimized delivery and/or display on a wireless device. The web server application may also send a message to a wireless device about events associated with the monitored computer systems. |
| US09749197B2 |
Mobile user data collection
A device receives, from multiple user devices, event information associated with the multiple user devices, where the event information includes one or more actions, user information, content information, and one or more attributes. The device stores the event information in a database, and analyzes one or more portions of the event information stored in the database. The device also recommends, based on the analyzed event information, one or more adjustments to a network that delivers content to the multiple user devices. |
| US09749190B2 |
Maintaining invalidation information
A computer-implemented method is operable on a device having hardware including memory and at least one processor. The method includes maintaining invalidation information in a list at a service on the device, where the invalidation information includes a plurality of invalidation commands. At least some of the invalidation commands in the list are selectively combined to form at least one other invalidation command in the list. |
| US09749188B2 |
Predictive networking architecture for next-generation multiservice, multicarrier WANs
In one embodiment, network traffic data is received regarding traffic flowing through one or more routers in a network. A future traffic profile through the one or more routers is predicted by modeling the network traffic data. Network condition data for the network is received and future network performance is predicted by modeling the network condition data. A behavior of the network is adjusted based on the predicted future traffic profile and on the predicted network performance. |
| US09749184B2 |
Cloud device and method for network device discovering
A network device discovery method receives registration information from the network devices which are registered to the cloud device, and generates a management list for recording the registration information and a management status of each of the registered network devices. When a request of searching for specified network devices of a specified network manager from a specified client device is received, the discovery method retrieves specified network devices managed by the specified network manager from the management list. The discovery method further searches for target network devices which have the same public Internet Protocol (IP) addresses with the specified network devices, and presents one or more target network devices which have not been managed by any network manager to the specified client device for the specified network manager. |
| US09749183B2 |
System and method for determining optimal combinations of computer servers
A computer-implemented method, apparatus, and non-transitory computer-readable medium for determining optimal combinations of elements having multiple dimensions, including removing all multi-dimensional elements from a combination matrix which have a dimension corresponding to a highest classification in a plurality of classifications, iteratively combining one or more multi-dimensional elements from a first end of the combination matrix and one or more multi-dimensional elements from a second end of the combination matrix to generate one or more combined multi-dimensional elements, incrementing a count of packed combinations when a combined multi-dimensional element in the one or more combined multi-dimensional elements has a dimension corresponding to the highest classification in the plurality of classifications, and removing a combined multi-dimensional element in the one or more combined multi-dimensional elements from the combination matrix when the combined multi-dimensional element has a dimension corresponding to the highest classification in the plurality of classifications. |
| US09749181B2 |
Managing communications for modified computer networks
Techniques are described for managing communications between multiple computing nodes, such as computing nodes that are part of a virtual computer network. In some situations, various types of modifications may be made to one or more computing nodes of an existing virtual computer network, and the described techniques include managing ongoing communications for those computing nodes so as to accommodate the modifications. Such modifications may include, for example, migrating or otherwise moving a particular computing node that is part of a virtual network to a new physical network location, or modifying other aspects of how the computing node participates in the virtual network (e.g., changing one or more virtual network addresses used by the computing node). In some situations, the computing nodes may include virtual machine nodes hosted on one or more physical computing machines or systems, such as by or on behalf of one or more users. |
| US09749176B2 |
Systems, methods, and apparatuses for providing adaptive user notifications
Methods and apparatuses are provided for providing adaptive user notifications. A method may include detecting an event. The method may further include determining usage of one or more connected apparatuses. The method may also include determining, based on the determined usage, a notification method for notifying of the event. The method may additionally include generating an event notification message based on the determined notification method. The method may further include causing the event notification message to be sent to a connected apparatus to trigger the connected apparatus to provide an alert indicative of the event in accordance with the determined notification method. Corresponding apparatuses are also provided. |
| US09749174B1 |
System and method for dynamic allocation of cloud resources
A system and method for dynamically allocating cloud resources includes receiving an application data request from a user and routing the request to a specific cluster of servers. Each application has a record in a database that contains a unique token along with subscriber information. Application requests to the service provider backend, are routed by DNS using an API endpoint name and originating geographic location to appropriate server clusters. When the request reaches the cluster, the load balancer extracts the application token from the URL, looks up the record in the database, and finds the subscriber plan and identity the application is associated with. A load balancer routes the data request to a specific cluster based upon the subscriber plan and identity. The clusters can have different processing speeds and features based upon the subscriber plan with premium plans having better performance than lower end plans. |
| US09749173B2 |
Systems and methods for synchronizing forwarding databases across multiple interconnected layer-2 switches
A method and a multi-switch architecture include learning a media access control (MAC) address at a first switch in a multi-switch architecture; storing the MAC address in a forwarding database of the first switch; transmitting a data frame to one or more switches in the multi-switch architecture via inter-switch connectivity between the first switch and the one or more switches, wherein the data frame is created to enable the one or more switches to learn the MAC address therefrom; learning the MAC address from the data frame at the one or more switches; and storing the MAC address in a forwarding database for each of the one or more switches. This further includes transmitting the data frame via ports and queues in the inter-switch connectivity that are separate from ports and queues in a data path between the first switch and the one or more switches to avoid data path interference. |
| US09749172B2 |
Calibration method and calibration apparatus for calibrating mismatch between first signal path and second signal path of transmitter/receiver
A method for calibrating mismatches of an in-phase signal path and a quadrature signal path of a receiver is proposed in the present invention, including: utilizing the receiver to receive at least one test signal with a specific frequency via the first signal path and the second signal path, to generate a first signal path received signal and a second signal path received signal; performing frequency analysis upon the first signal path received signal and the second signal path received signal respectively, to generate a first frequency analysis result and a second frequency analysis result; and calculating at least one calibration coefficient according to the first frequency analysis result and the second frequency analysis result. A method for calibrating mismatches of an in-phase signal path and a quadrature signal path of a transmitter is also proposed in the present invention. |
| US09749159B2 |
Methods and apparatus for scrambling symbols over multi-lane serial interfaces
Methods and apparatus for scrambling symbols over multi-lane serial interfaces in order to improve undesired electromagnetic emissions. In one embodiment the scrambling is based on a seed value associated with each lane. In a second embodiment, the scrambling values are selected from various taps of a scrambling component, where the selection is based on the associated lane. In still a third embodiment, each lane is associated with a distinct scrambling component. |
| US09749156B2 |
Receiving device and method of mobile communication system
An apparatus and a method for generating statistical signals having a characteristic similar to an input signal of a receiving apparatus to determine an optimized filter coefficient through an adaptive equalization algorithm are provided. The apparatus includes a channel estimator, a statistical signal generator, and an adaptive algorithm processor. The channel estimator estimates a channel of a reception signal. The statistical signal generator generates a plurality of signals having the same characteristic as that of a reception signal using a channel determined through a channel estimation process. The adaptive algorithm processor performs an adaptive equalization algorithm using the plurality of generated signals to determine an optimized filter coefficient. |
| US09749155B1 |
Method of blindly estimating WCDMA OVSF code for signal analyzer
Provided is a method of blindly estimating WCDMA OVSF of a signal analyzer, which includes: (a) setting SF to 512 and an index thereof to 0; (b) calculating a power average value of a symbol obtained by despreading descrambled data with an OVSF code set by increasing the index from ‘0’ by ‘1’; (c) determining an OVSF code by which the power average value is equal to or greater than a power reference value as a used OVSF code candidate and determining an OVSF code by which the power average value is less than the power reference value as an unused OVSF code; (d) comparing a zero crossing rate of a symbol with a reference value to determine whether the OVSF code candidate is the used OVSF code; and (e) repeating (b) to (d) while reducing the SF half by half until the SF is equal to 4. |
| US09749154B2 |
Method of channel estimation by phase rotation in an orthogonal frequency division multiplexing (OFDM) system
The method includes receiving communication signals in a time domain and to aa frequency domain, providing resource blocks in the frequency domain including a first and second resource block, selecting first pilot signals from first resource block and second pilot signals from second resource block, calculating a first average value based on the first pilot signals, calculating a second average value, determining a phase difference between the first and second pilot signals using the first and second average values, adjusting a first phase of first resource block using the phase difference, providing a first waveform using the first resource block with adjusted the first phase and the second resource block, applying a smoothing filter against the first waveform to generate a second waveform, generating a third waveform using at least the first and third set of phase and amplitude differences, and converting third waveform from frequency domain to time domain. |
| US09749147B2 |
Ethernet AVB for time-sensitive networks
Embodiments are disclosed for a device for handling communications from AVB and non-AVB networks. In some embodiments, a device includes a gateway interface communicatively connectable to one or more devices and configured to transmit and receive data from an AVB network and at least one other, non-AVB network, a processor, and a storage device that stores instructions executable by the processor to receive first data from a first device in the at least one other network, and receive second data from a second device in the AVB network. The instructions are further executable to process one or more of the first data and the second data according to one or more of an AVB protocol and a protocol associated with the at least one other network, and transmit one or more commands to one or more of the first device and the second device. |
| US09749146B2 |
Apparatus and methods for providing home network service
An apparatus and method for providing a home network service are provided. The method may include creating a user account in a server, receiving first initial setting information from an electronic device, transmitting second initial setting information to the electronic device, and receiving a message regarding registration of the electronic device from the server. |
| US09749145B2 |
Interoperability for distributed overlay virtual environment
A method includes receiving tunnel information and end point information in response to a request to a distributed cluster. A common tunnel type supported by a source switch and a destination switch is selected. A packet is encapsulated with the common tunnel type supported by the source switch and the destination switch for a destination virtual machine (VM). |
| US09749142B2 |
Notification of resource restrictions in a multimedia communications network
The invention relates to a method of notifying an Application Function, AF, in a communications network of resource restrictions relating to a communications session. The network includes a Policy and Charging Rules Function, PCRF, for authorising and controlling flows of data in the session. In the method the AF sends an authorisation request to the PCRF for establishing the communication session. The authorisation request includes an indication that the AF is to be notified of resource restrictions for the data flows in the session. The PCRF notifies the AF of the resource restrictions. |
| US09749139B2 |
Digital certificate issuer-correlated digital signature verification
A message including a digital signature of a message originator is received at a processor. In response to determining that the message originator is authorized by a data protection policy to originate the message, a determination is made as to whether a specific authorized certificate issuer is configured for the message originator within a data protection policy. In response to determining that the specific authorized certificate issuer is configured for the message originator within the data protection policy, a determination is made as to whether a message originator certificate used to generate the digital signature of the message originator is issued by the specific authorized certificate issuer configured for the message originator within the data protection policy. |
| US09749137B2 |
Method and system for securing the entry of data to a device
Crypto-glasses include systems that implement a method of authentication of users by blinking, the crypto-glasses including a frame configured so as to be worn by a user, a processor, a display device communicating with the processor so as to dynamically display data, and a communication unit, as executed by the processor, to execute the method of authentication by transmitting data to the display device for performing the authentication of the user to interact with the display device. The communication unit is configured to display in an optical unit of the crypto-glasses a key map which correlates data input into the display device with keys of the display device, the key map indicating data different from that of the keys of the display device. |
| US09749136B2 |
Method for watermarking content
The disclosure relates to processing content with watermarks to generate watermarked versions. In some aspects, each version may be different. Groups of fragments may be combined to generate a unique stream by pulling fragments from two or more of the groups of fragments. Further, fragmenting may be performed before watermarking, and fragments may be pulled and watermarked upon request. |
| US09749135B2 |
Encrypting device, encrypting method, and recording medium
From the least significant bit of the current secret key, k bits are retrieved, obtaining a binary window sequence. A binary bit string of concatenation of the random number to the more significant bits of the window sequence is obtained if the most significant bit of the window sequence is 0, subtracting a bit string from the current secret key to obtain a new secret key, or the bit string of a complement of the base number for the window sequence in binary system is calculated if the most significant bit of the window sequence is 1, obtaining a bit string by adding a minus sign to a bit string obtained by concatenating the random number to the more significant bits of the bit string, subtracting the bit string from the current secret key to obtain a new secret key. |
| US09749134B2 |
Wireless configuration using passive near field communication
A system comprises an access point and a client device. The access point receives, using near field communication (NFC) technology, a public key associated with the client device and sends, using NFC technology, a public key associated with the access point. The access point further encrypts configuration data associated with a network and sends the encrypted configuration data to the client device. The client device receives, using NFC technology, a command indicating that a public key associated with the client device is to be sent to the access point and sends, using NFC technology, the public key to the access point. The client device further receives, using NFC technology, a public key associated with the access point and configures the client device to wirelessly connect to a network associated with the access point. |
| US09749133B2 |
Method and apparatus for secure communication and determining secret information
A method of secure communication in a transmitter, includes determining a method of generating a training sequence that is shared with a receiver. The method further includes generating the training sequence based on the method of generating the training sequence, and secret information. The method further includes communicating with the receiver based on channel information derived from the training sequence. |
| US09749131B2 |
System and method for implementing a one-time-password using asymmetric cryptography
A system, apparatus, method, and machine readable medium are described for authentication with asymmetric cryptography. For example, a method in accordance with one embodiment comprises: generating a challenge at a server; encrypting the challenge at the server using a public encryption key; transmitting the encrypted challenge to a connected device having a first connection over a network with the server; providing the encrypted challenge from the connected device to a user device; decrypting the encrypted challenge using a private encryption key corresponding to the public encryption key to determine the challenge; converting the challenge to a converted challenge, the converted challenge having a different format than the original challenge; receiving the converted challenge at the connected device and providing the converted challenge from the connected device to the server; and validating the converted challenge at the server to authenticate the user. |
| US09749130B2 |
Distributing keys for decrypting client data
In some embodiments, a server can establish a session with a remote client. The server can generate a session key portion for the session and a client key portion for the remote client. The server can use a combined encryption key to encrypt client data received from the remote client during the session. The combined encryption key can be generated from a static key portion accessible by the server, the session key portion, and the client key portion. The server can associate the session key portion with the session. The session key portion is accessible by the server during the session. The server can delete the client key portion after providing the client key portion to the remote client. The server can obtain the client key portion from the remote client in response to determining that subsequent transactions during the session involve decrypting the encrypted client data. |
| US09749128B2 |
Compact fuzzy private matching using a fully-homomorphic encryption scheme
A method for data matching includes providing two sets of encrypted data elements by converting data elements to respective sets of vectors and encrypting each vector with a public key of a homomorphic encryption scheme. Each data element includes a sequence of characters drawn from an alphabet. For pairs of encrypted data elements, a comparison measure is computed between the sets of encrypted vectors. An obfuscated vector is generated for each encrypted data element in the first set, which renders the first encrypted data element indecipherable when the comparison measure does not meet a threshold for at least one of the pairs of data encrypted elements comprising that encrypted data element. The obfuscated vectors can be decrypted with a private key, allowing data elements in the first set to be deciphered if the comparison measure meets the threshold for at least one of the data elements in the second set. |
| US09749126B2 |
Data transmitter, data receiver and smart device using the same
Provided is a data transmitter including a signal interval determination unit configured to receive a data input signal corresponding to data to be transmitted, determine time intervals between a synchronization signal and a plurality of data signals according to the data input signal, and output interval signals corresponding to the intervals; a trigger generation unit configured to trigger according to an output signal from the signal interval determination unit; and a signal generation unit configured to receive the trigger to generate the synchronization signal and the data signals. |
| US09749121B2 |
Enabling half-duplex operation
Half-duplex (HD) operations enable low cost implementations of LTE terminals. Traditionally, HD operations may be linked to a particular frequency band which may not allow a mix of full-duplex (FD) and HD terminals in the same frequency band. Therefore, certain aspects of the present disclosure provide techniques for enabling coexistence, in a given frequency band, of HD and FD terminals, by introducing frequency bands designated for HD operation and overlapping existing frequency bands designated for FD operation. |
| US09749120B2 |
Uplink/downlink switching in half-duplex frequency division duplex communication
A method controls uplink/downlink (UL/DL) switching for half-duplex operation of user equipment (UE) in which UL and DL transmissions occur on different frequencies. The method comprises determining a duration of time required for the UE to switch between UL operation and DL operation, determining a time interval required by the UE to perform a measurement operation, determining a minimum number of subframes required for the measurement operation in the time interval, and controlling a switching configuration of the UE based on the determined duration of time, the determined time interval, and the minimum number of subframes. |
| US09749114B2 |
Method and apparatus for signal interference processing
A system that incorporates the subject disclosure may include, for example, a device comprising a memory to store instructions and a processor coupled to the memory, wherein responsive to executing the instructions, the processor performs operations. The operations comprise receiving signals over a spectrum of frequencies, providing location data of the device to a base station, receiving a request from a base station to perform a spectral analysis of the signals, detecting an interference among the signals, and providing, in response to the request, data to the base station regarding a source of the interference, wherein the data comprises a location of the source relative to the device, spectral data for identifying the source, and a time a frequency of occurrence of the interference. Other embodiments are disclosed. |
| US09749113B1 |
Control channel indication based on power level
An example embodiment may involve defining a time-division multiplexed, orthogonal frequency-division multiplexed wireless air interface containing a primary signaling channel. The primary signaling channel may be formed by a first set of modulation symbols that are allocated to a fixed time position of each time-division multiplexed subframe across a plurality of contiguous subcarrier frequencies. A first set of the subcarrier frequencies may be powered at a first level and a second set of subcarrier frequencies may be powered at a second level. The example embodiment may also involve defining a secondary signaling channel. The secondary signaling channel may be formed in the air interface by a second set of modulation symbols that are allocated to dynamic time positions on the first set of the subcarrier frequencies. The example embodiment may further involve transmitting signaling messages to one or more WCDs via the secondary signaling channel. |
| US09749110B2 |
MAC protocol for wide-bandwidth transmission utilizing echo cancellation for Wi-Fi
Techniques for presenting communication by two or more stations in a WLAN environment are provided. Specifically, methods are presented, that when taken alone or together, provide a device or group of devices with an efficient way for bandwidth adaptation using echo cancellation. Even more specifically, a narrow-bandwidth transmission can be interrupted in favor of a higher-bandwidth transmission upon one or more secondary channels becoming available or going quiet. |
| US09749108B2 |
Terminal, base station, transmission method, and reception method
Provided is a terminal whereby the accuracy of CSI measurement results in the terminal can be assured, and declines in throughput prevented. In this terminal, a reception processor (203) receives reference signals respectively transmitted from a plurality of transmission points. A CSI generator (206) identifies a second subframe on the basis of a first subframe respectively established for each of the plurality of transmission points, and using the reference signals from the plurality of transmission points, generates channel information in a subframe other than the second subframe, without generating channel information in the second subframe. A transmission signal former (208) transmits the generated channel information. |
| US09749105B2 |
Methods and apparatus in a wireless communication system
The present invention relates to methods and apparatus in a RBS and a UE for reference signal (RS) measurements in an OFDM system, that enable having a configurable RS transmission bandwidth which is smaller than the system bandwidth. This allows for better interference coordination of RS, which in turn improves the UE RS measurements used for different services such as positioning. The RBS retrieves the RS transmission bandwidth, determines a RS measurement bandwidth based on this RS transmission bandwidth, and transmits the determined bandwidth to the UE. The UE receives the RS measurement bandwidth and measures the RS in a bandwidth determined based on the received measurement bandwidth and the UE capability. |
| US09749100B2 |
Multiband Ethernet over Coax system
Described herein are apparatuses and methods for providing communication in multiple frequencies in a multiband Ethernet over Coax (EoC) system. An exemplary apparatus comprises a transceiver for transmitting or receiving a first data packet on a first channel associated with a first frequency, and a transmitter for transmitting a second data packet on at least one second channel associated with at least one second frequency. |
| US09749098B2 |
Method and apparatus for transmitting and receiving system information in mobile communication system
A method and apparatus of receiving system information of an SeNB, including configuring connection to an MeNB and receiving a RRC Connection Reconfiguration message including the system information of a cell included in a SCG controlled by the SeNB, and a method of sharing frame offset between a MCG controlled by an MeNB and an SCG controlled by an SeNB connected to the MeNB through non-ideal backhaul, including measuring system frame number (SFN) and subframe number (SN) of a cell included in the SCG and sharing the frame offset, which is determined based on the SFN and the SN, with the MeNB or the SeNB are provided. |
| US09749097B2 |
Method for wireless communications testing using downlink and uplink transmissions between an access point and mobile terminals
A method for wireless communications testing using downlink (DL) signal transmissions from an access point to a mobile terminal and uplink (UL) signal transmissions from said mobile terminal to said access point. Accurate block error rate (BLER) testing of LTE mobile devices in a wireless signal environment is enabled by preventing repeated transmissions of the same downlink (DL) data block that would normally follow reception of uplink (UL) transmissions of negative UL acknowledgments (NACKs) caused by failures to decode prior DL data transmissions, thereby producing cumulative NACK counts accurately reflecting data reception errors. |
| US09749090B2 |
System and method for transmitting a low density parity check signal
A system and method for transmitting LDPC parameters is provided. In the method, an initial number of OFDM symbols (Nsym_init) is determined for a packet that is based on the number of information bits to be delivered in the packet. An STBC value is also determined. A number of extra symbols (Nsym_ext) value is generated based on the Nsym_init value, wherein a Nsym value is based on said Nsym_init value and said Nsym_ext value. An Nldpc_ext value is determined based on the STBC value and the Nsym_ext value for purposes of determining LDPC parameters associated with the packet. |
| US09749089B2 |
Fast log-likelihood ratio (LLR) computation for decoding high-order and high-dimensional modulation schemes
A method receives the symbol transmitted over a channel, selects, from a constellation of codewords, a first codeword neighboring the received symbol and a set of second codewords neighboring the first codeword, and determines a relative likelihood of each second codeword being the transmitted symbol with respect to a likelihood of the first codeword being the transmitted symbol. Next, the method determines an approximation of a log-likelihood ratio (LLR) of each data bit in the received symbol as a log of a ratio of a sum of the relative likelihoods of at least some of the second codewords having the same value of the data bit to a sum of the relative likelihoods of at least some of the second codewords having different value of the data bit and decodes the received symbol using the LLR of each data bit. |
| US09749088B2 |
Method and apparatus for LDPC transmission over a channel bonded link
A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel. |
| US09749084B2 |
Method for temporarily blocking incoming and outgoing wireless communication for a mobile phone
A method for temporarily blocking incoming and outgoing wireless communication is provided with a mobile-phone disrupting unit and a motion sensor in a vehicle. A current speed of the vehicle is monitored with the motion sensor and then a plurality of communication disrupting signals is emitted by the mobile-phone disrupting unit if the current speed of the vehicle exceeds a minimum-speed threshold. When the current speed drops to the minimum-speed threshold or a lower speed, the process of emitting the plurality of disrupting signals is disabled so that the user can utilize the mobile phone. The mobile-phone disrupting unit and the motion sensor is either operatively integrated into the vehicle or housed within a self-containing enclosure. |
| US09749083B2 |
Transmission device with mode division multiplexing and methods for use therewith
Aspects of the subject disclosure may include, for example, a transmission device that includes at least one transceiver configured to modulate data to generate a plurality of first electromagnetic waves. A plurality of couplers are configured to couple at least a portion of the plurality of first electromagnetic waves to a transmission medium, wherein the plurality of couplers generate a plurality of mode division multiplexed second electromagnetic waves that propagate along the outer surface of the transmission medium. Other embodiments are disclosed. |
| US09749081B2 |
Wavelength/bandwidth tunable optical filter and driving method thereof
Provided herein is a wavelength/bandwidth tunable optical filter capable of flexibly tuning a wavelength and bandwidth, the wavelength/bandwidth tunable optical filter including an optical circulator configured to receive a WDM (Wavelength-Division-Multiplexing) optical signal from an optical cable; and a plurality of wavelength-tunable optical filters configured to receive the WDM optical signal via the optical circulator, wherein the plurality of wavelength-tunable optical filters reflect wavelengths of different bandwidths from one another. |
| US09749077B2 |
Controlling optical signal power levelling in an optical communication network
A method (10) of controlling optical signal power levelling in an optical communication network node configured to apply an optical attenuation, α, to a pass-through optical signal. The method comprises: a. performing the following steps i. to iii. until an attenuation variation value, Δα, is greater than a preselected attenuation variation threshold value (18), ΔαTH: i. measuring (12) an optical signal power of an optical signal; ii. calculating (14) a difference, ΔP, between the measured optical signal power and a target optical signal power; iii. calculating (16) a value for the attenuation variation, Δα, to be applied to the optical attenuation taking account of ΔP; b. obtaining (20) a current value of the optical attenuation, αn, and obtaining (22) a new optical attenuation value, αn+1, in dependence on the current value of the optical attenuation, a current value of the attenuation variation, Δαn, and at least an earlier value of the attenuation variation, Δαn−1; and c. generating (24) a control signal arranged to configure the node to apply the new optical attenuation value, αn+1. |
| US09749074B2 |
Resource mapping method and apparatus of OFDM system
A method and apparatus for allocating resource between uplink ACK/NACK channel and downlink control channel supporting spatial multiplexing in an OFDM-based wireless communication system which configures uplink ACK/NAK channel implicitly using reference signals for discriminating among resource allocation spaces and physical channel resource. The method is capable of multiplexing the uplink ACK/NACK channel associated with the control channel extended by spatial multiplexing into the uplink ACK/NACK channel resource which does not support spatial multiplexing. |
| US09749071B2 |
Radio broadcast apparatus and method for simultaneous playback and radio channel scanning
A radio broadcast playback method and apparatus is provided. The radio broadcast playback method includes playing a radio broadcast received by a tuner, receiving a channel search request, through an input unit, searching for radio channels by a communication module, while playing the radio broadcast received by the tuner, and outputting the found radio channels. |
| US09749064B2 |
Automated radio frequency testing management system
The disclosed embodiments include an automated RF testing management system that is configured to control a plurality of RF testing units, each having multiple test ports for performing RF testing of various electronic devices. Advantages of the disclosed embodiments include cost savings, increase productivity, and ease of configuration and maintenance. |
| US09749061B2 |
Digital signal processing device
A digital signal processor which performs digital signal processing of a digital signal includes a statistical analysis method which calculates a moving average and a standard deviation from the digital signal, performs statistical decision deciding whether or not the digital signal is within a predetermined range obtained from the moving average and the standard deviation, and corrects the digital signal outside the range within the range. Statistical analysis of the digital signal is performed, thereby suppressing transient changes without increasing the number of times of averaging during the digital signal processing. |
| US09749060B1 |
Front end characterization of coherent receiver
Techniques are described for characterizing a receiver front end of a pluggable optical module. The pluggable optical module receives an optical signal that includes a first portion having a first polarization and a second portion having a second polarization. The first portion and second portion are not coherent with one another and the power of the first portion and second portion is equal. |
| US09749058B2 |
Nonlinear tolerant optical modulation formats at high spectral efficiency
Techniques for transmitting a data signal through an optical communications system. An encoder is configured to encode the data signal to generate symbols to be modulated onto an optical carrier. Each symbol encodes multiple bits of data and includes a first portion selected from a first constellation and a second portion selected from a second constellation. The first and second constellations have respective different average amplitudes. Each of the first and second constellations have a cardinality of at least two and the cardinality of the first constellation is greater than the cardinality of the second constellation. A modulator is configured to modulate a first frame of the optical signal using the first portion and modulate a second frame of the optical signal using the second portion. A selection of one frame of the optical signal to be used as the first frame encodes at least 1 bit of data. |
| US09749057B2 |
Detection and alignment of XY skew
An optical device may include a modulator. The modulator may receive an optical signal. The modulator may modulate the optical signal to include a first channel and a second channel. The modulator may modulate the optical signal based on a training pattern associated with detecting a skew. The modulator may cause the first channel to interfere with the second channel. The modulator may perform a power measurement on the first channel and the second channel. The modulator may determine the skew based on the power measurement and the training pattern. The modulator may time delay the first channel or the second channel to align the skew based on the skew. |
| US09749055B2 |
Optical transmitter and optical transmission method
An optical transmitter converts a plurality of transmission signals transmitted via a plurality of lanes into a multi-carrier signal and transmits the multi-carrier signal. The optical transmitter includes: a controller configured to generate allocation information that indicates an allocation of sub-carriers to the plurality of lanes according to a bit rate of the transmission signal of each of the lanes and a possible transmission capacity of each of the sub-carriers; and a signal processor configured to convert the plurality of transmission signals into the multi-carrier signal in accordance with the allocation information generated by the controller. |
| US09749053B2 |
Node device, repeater and methods for use therewith
Aspects of the subject disclosure may include, for example, a node device includes an interface configured to receive first signals. A plurality of coupling devices are configured to launch the first signals on a transmission medium as a plurality of first guided electromagnetic waves at corresponding plurality of non-optical carrier frequencies, wherein the plurality of first guided electromagnetic waves are bound to a physical structure of the transmission medium. Other embodiments are disclosed. |
| US09749047B2 |
Optical network unit capable of reducing optical beat interference and method for controlling the same
Disclosed are an optical network unit included in an OFDMA-PON system that is capable of reducing OBI (optical beat interference), and a method of controlling the optical network unit. The disclosed optical network unit includes: a signal generator part configured to generate an electrical signal carrying transmission data; an RF tone generator part configured to generate an RF tone; a combiner part configured to combine the electrical signal and the RF tone; and a photoelectric converter part configured to convert the combined signal of the electrical signal and RF tone into an optical signal. |
| US09749045B2 |
Visible ray communication system, transmission apparatus, and signal transmission method
Disclosed is a visible ray communication system including a transmission apparatus and a reception apparatus, wherein the transmission apparatus includes: a plurality of light emitting devices; an S/P converter for serial-to-parallel converting transmission data, thereby generating N data streams; a modulator for modulating the generated N data streams for respective carriers with a predetermined number of dimensions, thereby generating N modulated signals; a carrier signal multiplier for multiplying the generated N modulated signals by orthogonal N carrier signals, respectively, thereby generating N transmission signals; and a light emitting control unit for illuminating the plurality of light emitting devices according to the generated N transmission signals. |
| US09749042B2 |
Channel validation in optical networks using multi-channel impairment evaluation
In an optical communication network that includes a plurality of interconnected network nodes, a method includes storing in each network node, and for each communication channel that traverses the node, one or more impairment margins of respective impairments that affect the communication channel. A potential communication channel that traverses a subset of the nodes in the network is identified. A quality of the potential communication channel is evaluated by processing the impairment margins stored in the nodes in the subset. |
| US09749032B2 |
Transmitter diversity technique for wireless communications
A simple block coding arrangement is created with symbols transmitted over a plurality of transmit channels, in connection with coding that comprises only simple arithmetic operations, such as negation and conjugation. The diversity created by the transmitter utilizes space diversity and either time or frequency diversity. Space diversity is effected by redundantly transmitting over a plurality of antennas, time diversity is effected by redundantly transmitting at different times, and frequency diversity is effected by redundantly transmitting at different frequencies: Illustratively, using two transmit antennas and a single receive antenna, one of the disclosed embodiments provides the same diversity gain as the maximal-ratio receiver combining (MRRC) scheme with one transmit antenna and two receive antennas. The principles of this invention are applicable to arrangements with more than two antennas, and an illustrative embodiment is disclosed using the same space block code with two transmit and two receive antennas. |
| US09749030B2 |
Method and apparatus for transmitting and receiving feedback information in a mobile communication system
A method and user equipment for transmitting channel state information (CSI) are provided. The method includes identifying a plurality of CSI configurations, each CSI configuration including channel measurement information, interference measurement information, an index for the each CSI configuration, and information for a period and an offset; and reporting a CSI for a CSI configuration among the plurality of CSI configurations based on a CSI report type and an index for the CSI configuration, in case of collision between CSI reports for the plurality of CSI configurations. |
| US09749027B2 |
Reference signal design for LTE A
Systems and methods are disclosed that facilitate creating antenna ports to correspond to two or more groups of user equipment. The systems and methods can organize two or more groups of user equipment and signal to each of the two or more groups a respective antenna port. The systems and methods can further communicate mapping information, a reference signal, or delay related to a linear combination in order to identify antenna ports. Based on such communicated information, the reference signal can be decoded in order to identify each antenna port. |
| US09749024B2 |
Wireless devices, methods, and computer readable media for multi-user request-to-send and clear-to-send in a high efficiency wireless local-area network
Apparatuses, methods and computer readable media for multi-user request-to-send and clear-to-send are disclosed. An apparatus of a high-efficiency wireless local area network (HEW) master station comprising circuitry is disclosed. The circuitry may be configured to: select a first group of stations to transmit a multi-user request-to-send (MU-RTS) transmission to and generate a MU-RTS packet for the first group of stations. The circuitry may be configured to transmit the MU-RTS packet to the first group of stations. The MU-RTS may include a resource map that indicates a subchannel for each of the first group of stations to receive data on and/or a power control indication for at least one of the stations of the one or more stations. The MU-RTS may indicate that some of the first group of stations should transmit a multi-user clear-to-send (MU-CTS) and others of the first group of stations should not transmit a MU-CTS. |
| US09749023B2 |
Apparatus and methods for transmission and reception of data in multi-antenna systems
Methods and apparatus adapted to address asymmetric conditions in a multi-antenna system. In one embodiment, the multi-antenna system comprises a wireless (e.g., 3G cellular) multiple-input, multiple-output (MIMO) system, and the methods and apparatus efficiently utilize transmitter and receiver resources based at least in part on a detected asymmetric condition. If an asymmetric condition is detected by the transmitter on any given data stream, the transmitter can decide to utilize only a subset of the available resources for that stream. Accordingly, the signal processing resources for that data stream are adapted to mirror the reduction in resources that are necessary for transmission. The transmitter signals the receiver that it will only be using a subset of the resources available, and the receiver adapts its operation according to the signaling data it receives. The multi-antenna system can therefore reduce power consumption as well as increasing spectral efficiency on the network. |
| US09749017B2 |
Wireless charging system
A master unit for wirelessly charging a slave device includes a plurality of radio frequency integrated circuit (RFIC) modules, each of the plurality of RFIC modules having an antenna array. The master unit is configured to select one of a single beam mode by using all or substantially all antenna arrays in the plurality of RFIC modules, a multi-beam mode by using each respective antenna array in each of the RFIC modules to form a separate beam from each RFIC module, and a customized beam pattern mode by using a customized combination of antennas in selected ones of the plurality of RFIC modules. The master unit is configured to dynamically select from one of the single beam mode, the multi-beam mode, and the customized beam pattern mode based on a location of the slave device relative to the master unit. |
| US09749015B2 |
Method and system for transmitting video data over a powerline communications transmission channel
For transmitting video data over a powerline communications transmission channel, a first communication device: obtains video data in the form of a succession of uncompressed images; determines the capacity of the transmission channel; performs a wavelet-decomposition of each uncompressed image, thereby obtaining data having different resolutions; compresses each wavelet-decomposed image, on the basis of the determined capacity of the powerline communications transmission channel; and performs transmission in pulse form with spreading of each compressed image to a second communication device, to introduce data redundancy, the rate of which, for each data item of said compressed image, is defined on the basis of the resolution of said video data item, the redundancy of the data having the lowest resolution being higher than the one of the data having any other resolution. The first communication device also transmits speed maps enabling the second communication device to thereby apply an image enhancement operation. |
| US09749012B2 |
Synchronized slotted power line communication
A method and a device are disclosed including a PLC node having a synchronizer, a modem with a transceiver, and a computing device coupled with a power line for power line data communications. In various embodiments, a coordinator or Data Concentrator Unit (DCU) coordinates the communication of PLC nodes. The PLC nodes are configured to detect a zero crossing of the power line wave form and transmit or receive data within time slots defined with respect to the detected zero crossing. In other embodiments, the time slots may be synchronized using a frame sync signal, an external signal, or polling. In various embodiments, the time slots may be random access or assigned. In some embodiments, the modem and/or node may be placed in a sleep mode when not communicating to reduce power consumption and be awaken when an allocated time slot is approaching. |
| US09749002B1 |
Clamping apparatus for portable electronic device
A clamping apparatus includes: a base defining a holding plate; two clamping units installed on the machine base and movable relative to each other; a unidirectional restriction unit restricting the clamping units from moving toward a center of the holding plate, having a portion exposed to an exterior of the holding plate such that an applied pressure results in withdrawal of the portion into the base and releases the clamping units from moving, thereby permitting the clamping units to move toward each other to clamp an electronic device tightly; and a manipulating unit is disposed in the base and has an manipulating part exposed to an exterior of the base such that activation of the manipulating part results in causing simultaneous movement of the clamping units away from each other and releasing the electronic device from the clamping units. |
| US09749001B2 |
Enhanced shell geometry for a flexible case for a portable electronic device
An accessory device is described. The accessory device may include a base region and sidewalls that combine with the base region to secure an electronic device with the accessory device. The accessory device may include a rigid layer having openings in at least some corners of the rigid layer. In order to facilitate insertion and extraction of the electronic device, an elastic material disposed in the openings may join with two sidewalls at the corners, allowing the sidewalls to move or bend with respect to other sidewalls. The accessory device may include a protective layer embedded in a sidewall to provide support to an opening formed in the sidewall. The sidewall may include a protrusion supported by features embedded in sidewall to facilitate pressing the protruding feature, which corresponds to pressing a button of the electronic device. |
| US09748999B2 |
Case for a tablet shaped device
A case for a tablet shaped device. The case comprises a body comprising a first face and a second face. The first face has a tablet shaped device receiving area. The body comprises a stylus holder for holding a stylus at the second face. The body comprises a collapsible stand attached to the body. The collapsible stand defines a space in which the stylus, when so held, is disposed when the collapsible stand is collapsed. |
| US09748997B2 |
Electronic device and method for making same
An electronic device includes a housing and a base plate. The housing includes a frame. The frame includes a first end portion having a first inner surface and a second end portion connected to the first end portion to form the closed frame. The second end portion has a second inner surface. The base plate is fixedly connected to the frame. One of the first inner surface and the base plate includes a first protrusion, and the other of the first protrusion and the base plate defines a first latching slot; the first protrusion receives in the first latching slot. One of the second inner surface and the base plate includes a second protrusion, and the other of the second inner surface and the base plate defines a second latching slot, the second protrusion receives in the second latching slot. |
| US09748996B2 |
Protective cover for electronic device
A protective cover for an electronic device includes a bottom plate, an integral side wall extending from the edges of the bottom plate. The bottom plate and the integral side wall cooperate to define a concave portion for receiving an electronic device. At least one connecting structure is arranged across the bottom plate and the integral side wall. Each connecting structure divides the protective cover into a first cover and a second cover. One of the first cover or the second cover is able to rotate relative to the other cover via the connecting portion, forming an angle between the first cover and the second cover, whereby the protective cover forms a standing base to support the electronic device at an angle. |
| US09748993B2 |
Radio frequency receiver front-end with gain control capability as well as improved impedance matching control capability
A radio frequency receiver is provided. The receiver can be employed in a low power (or ultra-low power) receiver architecture to generate a baseband signal or an intermediate frequency signal. In addition, the receiver includes capabilities of gain control to provide different gain settings as well as providing better/improved impedance matching control. |
| US09748988B2 |
Interference wave signal removing device, GNSS reception apparatus, mobile terminal, interference wave signal removing program and interference wave removing method
An interference wave signal frequency is highly accurate and the interference wave signal is surely removed. A controller of an interference wave signal remover detects the interference wave signal based on a frequency scanning result by an entire-range frequency scanner, and sets a notch filter to attenuate the interference wave signal frequency. A local scan frequency band BWfL of a local frequency scanner is set by having the interference wave signal frequency as its central frequency, and local scan frequencies BINL are set so that frequency bands overlap with each other between adjacent frequency BINA. The local frequency scanner frequency-scans input signals to the notch filter. The controller calculates a frequency error δf of the interference wave signal frequency from the local frequency scanner, corrects the interference wave signal frequency which is from the entire-range frequency scanner by the frequency error δf, and updates the setting of the notch filter. |
| US09748987B2 |
Interference cancellation system for cancelling interference in the optical domain
Systems and methods for cancelling interference from a received signal in order to properly detect a signal of interest are disclosed. A combined signal of interest plus interference signal may be received. A copy or sample of the interference signal may be determined. The interference signal and the combined signal of interest plus interference signal may be converted to the optical domain. The interference signal may be optically phase shifted by −180 degrees, which may result in an optically inverted interference signal. The optically inverted interference signal may be variably optically attenuated and/or variably optically time delayed, for example based on a detected output power of an optical subsystem of the interference cancellation system. As a result, interference cancellation of the interference signal from the combined signal of interest plus interference signal may be achieved, resulting in 50 dB or more of cancellation of the interference signal. |
| US09748985B2 |
Multiple band multiple mode transceiver front end flip-chip architecture and circuitry with integrated power amplifiers
An integrated circuit architecture and circuitry is defined by a die structure with a plurality of exposed conductive pads arranged in a grid of rows and columns. The die structure has a first operating frequency region with a first transmit and receive chain, and a second operating frequency region with a second transmit chain and a second receive chain. There is a shared region of the die structure defined by an overlapping segment of the first operating frequency region and the second operating frequency region with a shared power supply input conductive pad connected to the first transmit chain, the second transmit chain, the first receive chain, and the second receive chain, and a shared power detection output conductive pad connected to the first transmit chain and the second transmit chain. |
| US09748981B2 |
Receiving a plurality of radio frequency bands
A radio frequency receiver comprises a plurality of parallel receiving paths, wherein each path can receive a radio frequency signal in one of a plurality of radio frequency bands and amplify the received signal in a low noise amplifier. The amplified signals from the plurality of parallel paths are combined to one combined radio frequency signal in a common summation node and down-converted to a lower frequency signal in a mixer circuit. Each low noise amplifier comprises a low noise transconductance circuit providing a current signal to drive the common summation node, and an automatic gain control circuit in each path compensates for variations in signal strength independently of signal strengths of signals received by the other receiving paths. The receiver is suitable for simultaneous multiple band reception, where received signal strength can vary between the frequency bands. |
| US09748979B2 |
System for providing software defined radio on a device
A system for providing software defined radio on a mobile device includes a hardware portion including an antenna and an interface configured to connect to the mobile device; a software portion configured for execution on the mobile device, the software portion configured to receive and process RF signals received at the antenna. |
| US09748978B2 |
CRC code calculation circuit and method thereof, and semiconductor device
A CRC code calculation circuit including: an extraction circuit that extracts a calculation target packet that is a target of CRC calculation from a signal frame inputted as a parallel signal of a first bit length; a shift circuit that generates, when a bit length of the calculation target packet does not match an integral multiple of the first bit length, data A of a bit length that is the integral multiple of the first bit length by shifting the calculation target packet such that a last bit of the calculation target packet is positioned at a least significant bit, and adding “0” to a most significant bit side of a head bit of the shifted calculation target packet; and a calculation circuit that generates a CRC code by performing a CRC calculation on the data A based on an initial value “0” stored in a register. |
| US09748976B2 |
Fault tolerant syndrome extraction and decoding in Bacon-Shor quantum error correction
Systems and methods are provided for quantum error correction. A quantum system includes an array of qubits configured to store an item of quantum information. The array of qubits includes a plurality of data qubits and a plurality of measurement qubits configured to extract a syndrome representing agreement among the plurality of data qubits. The quantum system further includes an integrated circuit comprising validation logic configured to determine if the syndrome is valid, decoding logic configured to determine evaluate the syndrome to determine location of errors within the plurality of data qubits, and an error register configured to store locations of the determined errors. |
| US09748975B2 |
Transmitting apparatus and interleaving method thereof
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. |
| US09748973B2 |
Interleaved layered decoder for low-density parity check codes
A controller is configured to access information to generate data blocks. The controller includes a data block interleaver and a low-density parity check (LDPC) decoder. The data block interleaver is configured to interleave the data blocks to generate interleaved data blocks. The LDPC decoder is configured to decode the interleaved data blocks. |
| US09748963B2 |
Reducing distortion in an analog-to-digital converter
In one embodiment, an apparatus includes: a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential analog signal and convert the first portion of the differential analog signal into a first digital value; a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the differential analog signal into a second digital value; a combiner to form a combined digital signal from the first and second digital values; a decimation circuit to receive the combined digital signal and filter the combined digital signal into a filtered combined digital signal; and a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal, based at least in part on a coefficient value. |
| US09748961B2 |
Single cycle asynchronous domain crossing circuit for bus data
Techniques are disclosed for managing the timing between two asynchronous clocks. The techniques are particularly well-suited for synchronizing the reference clock with the divided clock in a phase coherent DSM PLL application, but can be more broadly applied to any application that includes a need for synchronizing a data bus across a clock boundary. In one example embodiment, the techniques are implemented in a retime word circuit operatively coupled between a DSM and the divide-by-N integer divider of a PLL application. The retime word circuit receives the divide word from the DSM and generates a retimed divide word that can be applied to the divider. The retime word circuit maintains the reference clock frequency throughput, and forces the divide word seen by the divider to change only at end of a given divide cycle. |
| US09748960B2 |
Method and apparatus for source-synchronous signaling
A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals. |
| US09748957B2 |
Voltage level shifter circuit, system, and method for wide supply voltage applications
A level shifter circuit is configured to receive first and second complementary input signals. Each of the first and second complementary input signals have a value of either a first supply voltage or a first reference voltage. The level shifter further includes a strong latch circuit operable in response to the first and second complementary input signals to drive one of first and second output signals to a second supply voltage and includes a weak latch circuit operable to drive the other of the first and second output signals to a second reference voltage. |
| US09748956B2 |
Integrated circuit and storage device including the same
An integrated circuit includes an input/output pad, a driver circuit connected to the input/output pad, and a receiver circuit connected to the input/output pad, and a code generator. The driver circuit is configured to output an output signal to an external device through the input/output pad. The receiver circuit is configured to receive an input signal from the external device through the input/output pad. The code generator is configured to generate a termination code of the external device in response to a signal output from the receiver circuit. |
| US09748953B2 |
Memory modules including plural memory devices arranged in rows and module resistor units
A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit. |
| US09748950B2 |
Gate energy recovery
Embodiment of the inventive subject matter include an apparatus comprising a first switch, a second switch, a third switch, and a transistor. The first switch is coupled to a first voltage device and the transistor to selectively electrically connect the first voltage device to the transistor to provide a first charge to the transistor. The second switch is coupled to a second voltage device and the transistor to selectively electrically connect the second voltage device to the transistor to remove charge from the transistor. The third switch is coupled to the third voltage device and the transistor to selectively couple the third voltage device to the transistor to provide a second charge to the transistor. |
| US09748947B1 |
IGBT gate drive circuit and method
There are provided methods and systems for operating insulated gate bipolar transistors (IGBTs). For example, there is provided a method that can include detecting a desaturation condition in an IGBT and initiating a turn off procedure when desaturation is detected. The turn off procedure can include holding a gate of the IGBT at at least one voltage level intermediate between a positive rail voltage and a negative rail voltage of an operational range of the IGBT. |
| US09748942B2 |
Switching element driving circuit
A switching element driving circuit includes a current detection unit that outputs a driving stop signal based on a level of current flowing through the switching element, and first and second control elements each connected to a control terminal of the switching element. A comparator controls the first control element based on a result of comparison of an output voltage of the driving circuit main unit with a first reference voltage. A differential amplifier drives the second control element in accordance with a voltage difference between the output voltage of the driving circuit main unit and a second reference so as to maintain the output voltage equal to the second reference voltage. An operation stopping unit stops the comparator and the differential amplifier to drive the first and second control elements, respectively, in response to the driving stop signal. |
| US09748939B2 |
Output circuit and integrated circuit
An output circuit has: a first driver circuit configured to receive a voltage of an input terminal and output a first voltage to an output terminal; a first comparison circuit configured to compare a first reference voltage with a voltage of the output terminal; a second driver circuit configured to receive the voltage of the input terminal and output a second voltage to the output terminal and become an off state according to a comparison result of the first comparison circuit; a second comparison circuit configured to compare a second reference voltage different from the first reference voltage with the voltage of the output terminal; and a third driver circuit configured to receive the voltage of the input terminal and output a third voltage to the output terminal and become an off state according to a comparison result of the second comparison circuit. |
| US09748936B2 |
Frequency generator, method and computer program
Embodiments relate to a frequency generator. The frequency generator comprises a quantization device configured to synthesize a carrier signal with a desired frequency characterized by a series of phase transitions at desired time instants, by approximating a phase transition at a desired time instant with a phase transition at a quantized effective time instant. The frequency generator further comprises a noise shaper configured to provide a noise-shaped feedback signal using the desired time instant and the effective time instant. Moreover, the frequency generator comprises an error generator configured to cause an error component within the effective time instant, the error component being at least 50 percent of a temporal quantization unit. |
| US09748935B2 |
Signal calculator
Examples of a signal calculator include a voltage multiplier and a time divider. The voltage multiplier copies time information corresponding to a first voltage and generates a third voltage using a second current corresponding to a second voltage during a first period corresponding to the copied time information. The time divider generates an output according to a result of comparing a voltage generated by a first current on the basis of a voltage corresponding to a first time with a second voltage corresponding to a second time. |
| US09748934B1 |
Systems and methods for reducing power supply noise or jitter
Systems and methods for reducing jitter due to power supply noise in an integrated circuit by drawing additional current. The additional current causes the total current to generally have a frequency higher than a resonant frequency of the integrated circuit and/or a power distribution network of the integrated circuit. A power distribution network may supply power to components of an integrated circuit, and data driver circuitry may draw first current to drive a serial data signal generated from a parallel data signal. Compensation circuitry may receive the parallel data signal and draw second current at times when the compensation circuitry determines data driver circuitry is not drawing the first current based on the parallel data signal, thereby causing a net of the first and second current to be higher than a resonant frequency range of the integrated circuit device and/or a component of the integrated circuit device. |
| US09748932B2 |
Phase locked loop using received signal
A phase locked loop includes a signal receiver configured to generate a mixed signal based on the received signal and an oscillator signal, and a frequency control circuit configured to compare the mixed signal to a reference signal, and adjust the oscillator signal based on a result of the comparing. |
| US09748930B2 |
Fast filter calibration apparatus
A method includes generating a calibration signal by a clock generator, feeding the calibration signal to a first filter through a first switch unit, comparing an output of the first filter with the calibration signal through a frequency detector and a phase comparator and generating a first updated bandwidth code to adjust a bandwidth frequency of the first filter. |
| US09748926B2 |
Antenna LNA filter for GNSS device
Low-noise amplifier (LNA) filters and processes for filtering global navigation satellite system (GNSS) signals are disclosed. The LNA filters can be used to down-convert a received GNSS signal to a lower frequency, filter the GNSS signal at the lower frequency, and up-convert the GNSS signal to the original frequency of the GNSS signal. The down-converted frequency can be selected based on a temperature of the GNSS signal to compensate for shifts in the frequency response of the filter due to temperature changes. |
| US09748920B2 |
Resonator element, resonator, electronic device, electronic apparatus, and moving object
A resonator element includes a vibrating portion that vibrates in a thickness shear vibration and includes a first main surface and a second main surface which are in a front and back relationship to each other, a first excitation electrode that is provided on the first main surface, and a second excitation electrode that is provided on the second main surface, and an energy trapping coefficient M satisfies a relationship of 33.6≦M≦65.1. |
| US09748919B2 |
Elastic wave device
An elastic wave device includes a piezoelectric substrate, an IDT electrode, and a cover member. The IDT electrode is provided on the piezoelectric substrate. The cover member is provided above the piezoelectric substrate and separate from the IDT electrode. The cover member includes a first cover member and a second cover member. The second cover member is laminated on a side of the first cover member opposite to the piezoelectric substrate. The glass transition point of the first cover member is higher than that of the second cover member. |
| US09748913B2 |
Apparatus and method for transmitting/receiving voice signal through headset
An apparatus and method are disclosed, which separates ambient noise from a voice signal in a Bluetooth headset with dual microphones, switches the connection path between the dual microphones and automatically controls output audio gain, based on the ambient noise. The method for outputting the voice signal includes receiving/comparing the first and second input signals from the first and second microphones, extracting the voice signal of substantially identical intensity from the first and second input signals, and transmitting the voice signal from the portable terminal communicating with the Bluetooth headset. |
| US09748911B2 |
Variable gain amplifying circuit
A variable gain amplifying circuit incorporates an operational amplifier, an input device, a feedback device, a transconductance circuit, and a dynamic biasing circuit. The operational amplifier has an output terminal providing an amplified difference output signal. The input device has a first terminal receiving a first input signal, and a second terminal coupled to a first input terminal of the operational amplifier. The feedback device is coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier. The dynamic biasing circuit generates a bias current according to a set value. The transconductance circuit converts the difference between the first input signal and a second input signal into an analog output current flowing through the feedback device. The analog output current of the transconductance circuit is varied according to the bias current. |
| US09748905B2 |
RF replicator for accurate modulated amplitude and phase measurement
The disclosure provides a communication circuit including an amplification circuit, a replicator circuit, and a correction circuit. Specifically, the amplification circuit generates an amplified signal. The replicator circuit emulates the amplification circuit and generates a replicated signal that approximates the amplified signal. The replicated signal is used by the correction circuit to generate control signals for controlling the amplification circuit. |
| US09748904B2 |
High frequency signal amplifying circuitry
A high frequency signal amplifying circuitry of an embodiment includes a first splitter, a first amplifier, a second amplifier, a loop oscillation suppressor, and a combiner. The first amplifier includes a second splitter, a first carrier amplifier, a first peak amplifier, and a first combiner. The second amplifier includes a third splitter, a second carrier amplifier, a second peak amplifier, and a second combiner. The second carrier amplifier being adjacent to an associated the first carrier amplifier or the second peak amplifier being adjacent to an associated the first peak amplifier. The loop oscillation suppressor located between the second carrier amplifier and the associated first carrier amplifier or the second peak amplifier and the associated first peak amplifier. |
| US09748903B2 |
Power amplifiers with signal conditioning
A device includes an amplifier having a first path and a second path and a first variable attenuator connected to the first path. The device includes a controller coupled to the first variable attenuator. The controller is configured to determine a magnitude of an input signal to the amplifier. When the magnitude of the input signal is below a threshold, the controller is configured to set an attenuation of the first variable attenuator to a first attenuation value. When the magnitude of the input signal is above the threshold, the controller is configured to set the attenuation of the first variable attenuator to a second attenuation value. The second attenuation value is less than the first attenuation value. |
| US09748900B2 |
Low noise amplifier
A device is disclosed that includes a first gain stage and a first amplifier. The first gain stage is configured to generate a first signal according to a first input signal, and to multiply the first signal and the first input signal, to generate a second signal at a first output terminal, in which the first signal is associated with the even order signal components of the first input signal. The first amplifier is configured to amplify the first input signal to generate a third signal at the first output terminal, in order to output a first output signal with the first gain stage, in which the first output signal is the sum of the second signal and the third signal. |
| US09748899B2 |
MEMS amplitude modulator and MEMS magnetic field sensor including same
The present invention provides an amplitude modulator, which is disposed in an area through which a magnetic field flows so as to modulate amplitudes, comprising: a substrate; a first driving electrode which receives a first frequency signal and a second frequency signal supplied from the substrate and carries out resonant motion by the magnetic field; and a second driving electrode for receiving the second frequency signal and carries out resonant motion by the first driving electrode and the magnetic field, wherein a modulated signal is generated by modulating the amplitudes of the first and second frequency signals through the resonant motions of the first and second driving electrodes. Therefore, since the signal generated by modulating a carrier signal through mechanical resonance according to the magnetic field is outputted, amplitude modulation can be carried out without a complicated circuit configuration. In addition, since an MEMS device is a single structure that does not include an insulating layer, a single signal is applied to one structure, thereby simplifying driving, and all the driving electrodes of both ends thereof are driven so as to double a change in variable capacitance, thereby improving sensing ability. |
| US09748898B2 |
Current driven crystal oscillator
An oscillator circuit with an oscillator stage and a first current source arranged to drive the oscillator stage is presented. The oscillator stage has an oscillator stage input terminal, an oscillator stage output terminal, an oscillator arranged to provide an oscillating signal between the oscillator stage input terminal and the oscillator stage output terminal. The oscillator circuit has an operational amplifier with an inverting input, a non-inverting input and an operational amplifier output. The oscillator stage input terminal and the oscillator stage output terminal are coupled to the inverting input and non-inverting input. The operational amplifier output is coupled to the oscillator stage input terminal such that the oscillator stage input terminal and the oscillator stage output terminal are controlled to have a same DC voltage level. |
| US09748897B2 |
Electrically isolated heat dissipating junction box
A junction box used for making electrical connections to a photovoltaic panel. The junction box has two chambers including a first chamber and a second chamber and a wall common to and separating both chambers. The wall may be adapted to have an electrical connection therethrough. The two lids are adapted to seal respectively the two chambers. The two lids are on opposite sides of the junction box relative to the photovoltaic panel. The two lids may be attachable using different sealing processes to a different level of hermeticity. The first chamber may be adapted to receive a circuit board for electrical power conversion. The junction box may include supports for mounting a printed circuit board in the first chamber. The second chamber is configured for electrical connection to the photovoltaic panel. A metal heat sink may be bonded inside the first chamber. |
| US09748896B2 |
Electrically isolated heat dissipating junction box
A junction box used for making electrical connections to a photovoltaic panel. The junction box has two chambers including a first chamber and a second chamber and a wall common to and separating both chambers. The wall may be adapted to have an electrical connection therethrough. The two lids are adapted to seal respectively the two chambers. The two lids are on opposite sides of the junction box relative to the photovoltaic panel. The two lids may be attachable using different sealing processes to a different level of hermeticity. The first chamber may be adapted to receive a circuit board for electrical power conversion. The junction box may include supports for mounting a printed circuit board in the first chamber. The second chamber is configured for electrical connection to the photovoltaic panel. A metal heat sink may be bonded inside the first chamber. |
| US09748895B2 |
Solar module with simplified humidity level regulation
A solar module in a concentrating solar system including: a box including a top wall, formed from an optical system, and walls; at least one photovoltaic cell placed in the box; and at least one humidity management device. At least one first wall among the walls includes a principal part contained in a plane. The humidity management device includes a housing defined between the first wall and a cover fixed to the first wall including an occultation part and an inner part forming an air film at the occultation part. A moisture-absorbing material is placed in the housing, at least part of the moisture-absorbing material is located on one side of the plane containing the occultation part. |
| US09748893B2 |
Photovoltaic array mounting system
A system for mounting a photovoltaic array onto short sections of mounting rails such that a section of mounting rail is only installed fewer than all the photovoltaic modules in the array. A single section of mounting rail may support one, two or three photovoltaic modules depending on it's length and position respect to the edge of each module frame. |
| US09748890B2 |
Hybrid flow solar thermal collector
A hybrid solar thermal collector is provided. The hybrid solar collector comprises a photovoltaic element to convert sunlight into electricity; and a solar thermal collector device comprising an absorber element to convert sunlight into heat; wherein the absorber element is immersed in a heat transfer fluid in use. |
| US09748887B2 |
Permanent magnet synchronous motor and winding-switching motor driving device, and refrigeration air conditioner and electric vehicle using same
A permanent magnet synchronous motor includes at least two series-connected windings for each phase, and is configured to be driven by selecting the windings using a multi-inverter driving device configured to switch between an inverter for low-speed drive and an inverter for high-speed drive. A ratio of an induced voltage constant of at least one group of windings constituting the windings for the high-speed drive and a d-axis inductance is larger than a ratio of an induced voltage constant of all the series-connected windings to the d-axis inductance. |
| US09748882B1 |
Integrated motor driver/controller with sensorless or sensored commutation
A motor controller configured to control different types of electronically commutated motors (ECMs) includes a range of different rotor orientation signal inputs to accommodate differences between ECM motor types. The motor controller includes a control unit that receives motor operation commands and controls operation of the ECM in accordance with the motor operation commands. The control unit receives and stores data designating ECM type and estimates rotor position based on the designated ECM type. |
| US09748881B2 |
Voltage regulator, operation method thereof, voltage regulating system, and mobile vehicle
A voltage regulator, an operation method thereof, and a voltage regulating system, and a mobile vehicle are provided. The voltage regulator coupled to an alternator and a battery includes a voltage detection unit which is coupled to the alternator and a startup assisting unit. The voltage detection unit operatively generates an enable signal responsive to an output voltage of the alternator. The startup assisting unit is coupled to the alternator, the battery, and the voltage detection unit. The startup assisting unit operatively generates a first exciting current to excite a rotor coil according to the enable signal. When the voltage detection unit detects that the output voltage is greater than a predetermined voltage threshold, the voltage detection unit outputs the enable signal causing the startup assisting unit to generate the first exciting current to the rotor coil, thereby facilitating the alternator to establish voltage under low rotational speed. |
| US09748879B2 |
Motor drive controller and control method of motor drive controller
A motor drive controller is provided with: a motor drive circuit that drives a motor and having a position detector that detects a position of a rotor of the motor and outputs a position detection signal; a motor control circuit that generates a rotation pulse signal based on the position detection signal output by the motor drive circuit; and a microcomputer that is provided with at least one timer and outputs a conversion signal that is obtained by multiplying the rotation pulse signal by n, where n is a natural number equal to or greater than two. |
| US09748877B2 |
Motor drive circuit and method
In accordance with an embodiment, a method for driving a motor includes determining a position of a first pole of a rotor of the motor relative to a position of a Hall sensor. A drive signal is generated in response to the position of the first pole of the rotor of the motor, the drive signal having a duty in accordance with the duty control signal or a second duty control signal. In accordance with another embodiment, a drive circuit for a motor includes a state controller connected to a rotational state generation unit, a pulse width modulation detection circuit, and a duty control controller. An align duty set circuit is connected to the duty control controller. |
| US09748875B2 |
Method and device for operating a brushless DC motor
A method for operating a three-phase brushless DC motor with a pulse-width modulation controlled electronic commutation in the event of a malfunction. A maximum number (n) of commutation steps, a direction of motor rotation and at least two possible operating end states are specified, and one of the operating end states is chosen. Following indication of a malfunction, the rotor of the brushless DC motor is rotated at the specified maximum number (n) of commutation steps in the specified direction of motor rotation and the brushless DC motor is then set to the operating end state selected. |
| US09748873B2 |
5-pole based wye-delta motor starting system and method
One embodiment describes a motor starter, which includes a first single pole switching device that opens to disconnect power from a first winding of a motor; a second single pole switching device that closes after the first switching device opens to connect power to the first winding; a third single pole switching device closes after the second single pole switching device closes to increase power supplied to a second winding of the motor; a fourth single pole switching device that opens after the third single pole switching device closes to disconnect power supplied to a third winding of the motor and to reduce power supplied to the second winding; and a fifth single pole switching device that closes after the fourth switching device opens to connect power to the third winding. |
| US09748872B2 |
Vibrational energy harvesting system
A vibrational energy harvesting system is disclosed. Included is a first energy harvesting unit and a second energy harvesting unit that convert mechanical vibrations into first and second AC signals, respectively. A first AC-DC converter coupled to the first energy harvesting unit and a second AC-DC converter coupled to the second energy harvesting unit are configured to convert the first AC signal and the second AC signal into a first DC signal and a second DC signal, respectively. A DC-DC converter is coupled between the second AC-DC converter and a controller, and is configured to receive the second DC signal and provide a regulated DC signal by using energy from the second DC signal in response to a periodic signal generated by the controller. Typically, an energy storage unit is coupled to the DC-DC converter and is configured to receive and store energy from the regulated DC signal. |
| US09748870B2 |
Acoustic mechanical feed-throughs for producing work across a structure
An apparatus that passes vibrational energy across a mechanical structure lacking a perforation. The disclosed apparatus and method provide the ability to transfer work (rotary or linear motion) across pressure or thermal barriers or in a sterile environment without generating contaminants; the presence of reflectors in the solid barrier to enhance the efficiency of the energy/power transmission, and the ability to produce a bi-directional driving mechanism using a plurality of different mode resonances, such as a fundamental frequency resonance and a higher frequency resonance. In some instances, a plane within the mechanical structure lacking a perforation is a nodal plane of the vibrational energy field. |
| US09748868B2 |
Triboelectric composite for mechanical energy harvesting and sensing
Composite material comprising a matrix of elastic and electrically insulating material, and a filler of electrically conducting material embedded within the matrix. The filler forms a conductive path defining an active electrode adapted to be associated with a reference electrode for forming an electrical signal output. A deformable gap is formed between an outer surface of the conductive path and an inner surface of the matrix, in such a way that the application of a mechanical load to the composite material causes the surface of the conductive path and the surface of the matrix to be brought closer together, and the removal of the mechanical load causes the surface of the conductive path and the surface of the matrix to be moved away from one another as a result of the elastic force of the material of the matrix. |
| US09748864B2 |
Power supply circuits incorporating transformers for combining of power amplifier outputs and isolation of load voltage clamping circuits
A power supply circuit includes a power amplifier that receives a direct current (DC) voltage from a first power source. A control signal applied to the power amplifier causes the power amplifier to convert the DC voltage to an alternating current (AC) output signal. The AC output signal is applied to a transformer that includes a first winding, a second winding, and a third winding. The first winding receives the AC output signal and the second winding receives an output current that varies in accordance with the AC output signal to apply current to a load. A rectifier includes a plurality of diodes configured to rectify a voltage across the third winding and clamp the voltage at the load. Return power from the third winding may be returned to the first power source. |
| US09748863B1 |
System and method for leakage current suppression in a low switching frequency photovoltaic cascaded multilevel inverter
The cascaded multilevel inverter is considered to be a promising topology alternative for low-cost and high-efficiency photovoltaic (PV) systems. However, the leakage current issue, resulting from the stray capacitances between the PV panels and the earth, remains a challenge in the photovoltaic cascaded multilevel inverter application. The present invention presents leakage current suppression solutions for the PV cascaded multilevel inverter by introducing properly arranged and designed passive filters. The embodiments of the invention do not include an active semiconductor device, and as such, the leakage current suppression techniques of the present invention retain the simple structure of the cascaded inverter and do not complicate the associated control system. |
| US09748862B2 |
Sparse matrix multilevel actively clamped power converter
Power converters are presented with one or more sparse multilevel actively clamped (SMAC) power converter stages, where the individual stages include an integer number N capacitors or DC voltage sources coupled between stage DC inputs to provide L=N+1 converter stage DC voltage nodes, with a switching circuit having no more than L*(L−1) switching devices and no flying or floating DC storage capacitors, where N is greater than 2. |
| US09748861B2 |
Method and device for operating an electrical power converter
A method for operating an N-level K-phase electrical power converter, wherein N is greater than or equal to 3 and K is greater than or equal to 1. The method includes: providing a plurality of N connection points that each correspond to a definable potential, wherein a first connection point corresponds to a first potential, a second connection point corresponds to a second potential, and at least one further connection point corresponds to a further potential which is lower than the first and greater than the second potential; providing a plurality of K output connections that are each selectively connected to a respective one of the connection points via at least one switching device; and having at least one current flowing into the at least one further connection point. |
| US09748860B2 |
Input filter pre-charge fed by a medium-voltage grid supply
A device includes a transformer configured to supply a pre-charge voltage to a capacitor and a converter configured for coupling to the transformer and responsive to an increasing modulation index. The modulation index increases for a time quanta after the capacitor becomes substantially fully charged and the pre-charge voltage is substantially constant during the time quanta. |
| US09748855B2 |
Bidirectional DC-DC converter
A bidirectional DC-DC converter is disclosed. According to the bidirectional DC-DC converter, switching loss is reduced by implementing zero voltage switching of switching devices in a boost mode of the bidirectional DC-DC converter. Accordingly, it is possible to realize the high efficiency of power conversion. Further, switching devices of the bidirectional DC-DC converter are controlled using simple logic devices, thereby controlling a plurality of directional DC-DC converters coupled in parallel to each other. |
| US09748854B2 |
Alternating current (AC)-direct current (DC) conversion circuit and control method thereof
An AC-DC conversion circuit includes an input rectifier circuit, a primary side input filtering capacitor, a primary side inverter circuit, a drive circuit, an isolation transformer, a secondary side rectifier circuit, a secondary side capacitors, and a control circuit connected between the secondary side output filtering capacitor and the drive circuit, where the drive circuit is connected to the primary side inverter circuit. The primary side inverter circuit and the primary side input filtering capacitor form a loop, so as to form a clamping resonant circuit. Inverter switching transistors operate in a zero voltage switching (ZVS) state. The secondary side rectifier circuit has two operation modes including a forward operation mode and a flyback operation mode. Each of the first and the second inverter switching transistors in the primary side inverter circuit is used as an inverter switching transistor or a clamping switching transistor according to an operation period. |
| US09748848B2 |
Modular multilevel DC/DC converter for HVDC applications
A DC converter is suitable for continuous operation for connecting high-voltage DC networks having different voltages. The DC converter has a first partial converter and a second partial converter, which are connected in series with each other, forming a converter series circuit. The converter series circuit extends between the DC terminals of a DC connection. The second partial converter extends between the DC terminals of a second DC connection. The first partial converter and the second partial converter are connected to each other via a power exchange device, such that the exchange of electrical power between the first partial converter and the second partial converter is made possible via the power exchange device. |
| US09748847B2 |
Circuits and methods providing high efficiency over a wide range of load values
An apparatus and method are disclosed for providing efficient operation in a feedback loop having a synchronous buck converter. The synchronous buck converter includes a plurality of individually selectable phases, where each of the phases has a plurality of individually selectable and parallel switching legs. The circuit stores information that associates multiple different load values with respective configuration settings that each define a number of phases and a number of switching legs. As the load changes, the circuit measures the load and selects an appropriate configuration setting. The circuit applies the selected configuration setting to operate the number of phases and a number of parallel switching legs in the buck converter. |
| US09748845B1 |
Method and apparatus for wide bandwidth, efficient power supply
An efficient power supply with fast, wideband response has been disclosed. In one implementation, two switching regulators with different frequency responses are combined to provide wideband, efficient power. |
| US09748839B2 |
Digital voltage regulator controller with multiple configurations
A digital voltage regulator controller includes control logic, an interface and configuration logic. The control logic is operable to control power stages of a voltage regulator so that groups of one or more of the power stages individually regulate one or more output voltages of the voltage regulator. An external electrical parameter that indicates a location of the controller on a board or a version of the board is measured via the interface. The configuration logic is operable to determine a set of configuration parameters for the voltage regulator based on the location of the controller on the board or the version of the board as indicated by the external electrical parameter, and configure the control logic in accordance with the set of configuration parameters so that each output voltage is regulated based on the location of the controller on the board or the version of the board. |
| US09748836B2 |
Power stabilization circuit and method
A power stabilization circuit including a first reference power supply, a second reference power supply, and a combiner circuit coupled to the first reference power supply and the second reference power supply. The first reference power supply is configured to receive a first control signal, generate a first reference signal based on the first control signal, and provide the first reference signal to a first output power supply. The second reference power supply is configured to receive a second control signal, generate a second reference signal based on the second control signal, and provide the second reference signal to a second output power supply. The combiner circuit is configured to generate a combined reference signal based on the first reference signal and the second reference signal and drive a reference load based on the combined reference signal. |
| US09748835B2 |
Digital power factor correction
A circuitry for providing a power factor correction is suggested. The circuitry includes a digital pulse width modulator, a switching element, a control unit, and a combiner. An output of the digital pulse width modulator is connected to the switching element. The combiner determines a combined signal based on an output of the control unit and an input signal. The combined signal is conveyed towards the digital pulse width modulator. An output of the switching element provides a feedback signal for the digital pulse width modulator and for the control unit such that an error in the feedback signal is reduced. |
| US09748833B2 |
Power conversion apparatus and method for starting up the same
A power conversion apparatus includes a transformer; a primary side full bridge circuit provided on a primary side of the transformer; a first port connected to the primary side full bridge circuit; a second port connected to a center tap of the primary side of the transformer; a secondary side full bridge circuit provided on a secondary side of the transformer; a third port connected to the secondary side full bridge circuit; and a control unit configured to cause an upper arm of the secondary side full bridge circuit to operate in an active region in a case where a capacitor connected to the third port is charged with a transmitted power transmitted to the secondary side full bridge circuit via the transformer from the primary side full bridge circuit when power of the second port is stepped up and the stepped up power is output to the first port. |
| US09748828B2 |
Overmolded flux ring
An overmolded steel flux ring member for an eddy-current fan drive assembly. The flux ring member includes a base member having a hub member, an annular outer ring member, and a plurality of connecting arm members. An overmolding material, such as aluminum, is overmolded on the annular outer ring member preferably in separate sections. Ventilation openings in said base member allow air to flow past a magnet ring for cooling. |
| US09748827B2 |
Linear vibration motor
A linear vibration motor is disclosed in the present disclosure. The linear vibration motor includes a housing including a cover and a base associated with the cover to form an internal space; a pair of elastic members received in the internal space, each of the elastic member including a first connecting portion and an elastic arm extending from the first connecting portion and connected with the cover; an vibrator unit suspended in the internal space by the elastic members; a stator unit mounted on the base; a pair of dampers, each damper located on one side of the first connecting portion, and been in contact with the first connecting portion for absorbing vibrations of the vibrator unit; and a pair of clamping members, each clamping member clamping the first connecting portion and the damper to the vibrator unit. |
| US09748825B2 |
Tool for installing a wedge in a slot of a stator core
A tool (110) is presented for installing a wedge (104) in a slot (101) of a stator core (100). The tool (110) includes a housing (112) and a shaft (128) extending axially from the housing. An end of the shaft (128) is positioned in the slot (101) on a first side of the wedge (104) to engage a wedge surface (118). The tool (110) further includes a pump (120) operatively coupled to the shaft (128) to actuate the shaft in an axial direction (122) external to the housing (112) to install the wedge in the slot. The tool (110) further includes a tongue (124) inserted in a vent gap (126) of the slot (101) on the first side of the wedge to brace the tool against the slot during the installation of the wedge. A system (200) and method (300) are also presented for installing the wedge. |
| US09748821B2 |
Modular cooling arrangement for electric machine
A cooling arrangement for electric machines where cooling plates are maintained against the inner surface of the stator and are interconnected by a cooling tube that carries the stator generated heat outside of the machine. |
| US09748818B2 |
Method and device for supplying a measurement electronics system with electrical energy
A method and a device for supplying a measurement electronics system in a fitting, through which a fluid flows, with electrical energy, which is generated in a turbine by the fluid flowing through the filling, wherein the flow quantities and pressures vary within wide boundaries, typically 1:1000. A pressure control device associated with the turbine controls the pressure of the fluid striking the turbine in such a manner that the electrical energy required for operating the measurement electronics system is generated with a small flow quantity, the pressure loss incurred by the fluid while flowing through the fitting being limited to a maximum value. |
| US09748817B2 |
Gear motor assembly
A gear motor assembly includes a motor and a gearbox connected together. The motor includes a stator and a rotor. The stator has a housing, magnets attached to the housing, and brushes. The rotor includes a shaft with a rotor core, a commutator, a sleeve, a bushing and a worm mounted thereon. The bushing is slidably located between the commutator and worm. The sleeve is located between the commutator and the bushing. The rotor is balanced with the worm fix to the shaft. The gearbox includes a casing having an opening, and a worm gear received in the casing. The brushes of the motor are mounted in the casing. The shaft has a first end that extends into the gearbox. The bushing is fixed in the casing via a bushing seat. |
| US09748813B2 |
Bobbin and rotary electric machine
A bobbin for electrically insulating the stator core from a coil wire to be wound around the bobbin includes: a coil winding portion around which the coil wire is to be wound; and a terminal fixing portion to which a winding starting end portion and a winding finishing end portion of the coil wire are to be fixed. The terminal fixing portion includes a first groove configured to guide a winding starting section extending from the winding starting end portion of the coil wire to a winding starting position of the coil winding portion and a second groove configured to guide a winding finishing section extending from a winding finishing position of the coil winding portion to the winding finishing end portion of the coil wire to intersect the winding starting section when seen in an axial direction. |
| US09748812B2 |
Stator of motor having insulation structure for separation of stator winding groups
Disclosed is a stator of an EPS motor, the stator including a stator core including a plurality of teeth protrusively formed toward a center of an inner circumferential surface, a plurality of coils wound on the teeth at a predetermined counts, an insulator coupled to an upper surface and a bottom surface of the stator core to insulate the coil from the stator core, and an insulation tube situated nearest to a coil wound on an adjacent stator core and inserted into a coil wound on an outmost side of the teeth. |
| US09748810B2 |
Motor and method for manufacturing stator therefor
A stator core is formed by deforming a core assembly having core pieces coupled in a strip form into an annular shape, and by joining both ends of the core assembly together to make a core-fastening portion. Individual phase windings are routed from one end of the core assembly toward another end. Lead portion (43v) of phase winding (40v) and lead portion (43w) of phase winding (40w) make up respective wire terminals. Lead portion (43u) of another phase winding (40u) is extended through a plural number of the core pieces in a direction of the lead portions (43v and 43w), and a wire terminal of the extended lead portion (43u) and the wire terminals of the other lead portions (43v and 43w) are electrically connected to provide a neutral point of three-phase Y-connection circuit. |
| US09748809B2 |
Stator winding heat sink configuration
In one possible implementation, a motor is provided including a rotor and a stator. Front cooling fins are thermally coupled to a front of the stator, and rear cooling fins are thermally coupled to a rear portion of the stator. The winding is between the front and rear cooling fins. |
| US09748799B2 |
Adaptable external battery modules and related systems
Embodiments of the present inventive concept provide an external battery module (EBM) including a communication server board (CSB) slot configured to receive a CSB, wherein the EBM operates regardless of whether the CSB is positioned in the CSB slot; and a battery charger slot configured to receive a battery charger, wherein the EBM operates regardless of whether the battery charger is positioned in the battery charger slot. |
| US09748798B2 |
Control module for an electrical energy accumulator, energy accumulator unit having such a control module, uninterruptible power supply unit and method for operating a control module
The invention relates to a control module for an electric energy store for operation on a supply line, which is configured for the parallel connection of a plurality of consumers, comprising a supply terminal for connection to the supply line, and comprising a control unit for the controlled charging and/or discharging of an electric energy store via the supply terminal, wherein the control module is connected or can be connected to the electric energy store, the control module can be connected to a delimiting device, and the control unit is configured, when the control module is connected to the delimiting device, to perform a rapid charging and/or a rapid discharging of the energy store. |
| US09748795B2 |
System for charging a rechargeable battery of an electric vehicle
An electric vehicle includes an electric machine, a generator generating a first AC output current, an internal combustion engine driving the generator, and a first electric plug-in charging device. When the engine is started, the generator supplies the battery with charging power. The first plug-in charging device is geometrically configured to be connectable with single phase AC power mains to supply the battery with charging power in a vehicle deactivated state. The first plug-in charging device is configured for a maximum electric power voltage load of 240 volts and a maximum current strength of 32 amperes. A second electric plug-in charging device is integrated into the vehicle. A DC charging station is connectable to the second charging device in the deactivated state so the DC charging station is usable either exclusively or simultaneously with the single phase AC power mains for charging the battery. |
| US09748792B2 |
Wireless charging system
A wireless charging system includes a wireless charger includes a power transmission part and a controller, the power transmission part being configured to transmit power to a portable terminal having a power-receiving part in a non-contact manner, the controller being configured to control power transmission performed by the power transmission part and to control a stop of the power transmission; and an in-vehicle wireless communication device having an antenna configured to perform wireless communication with an electronic key of an occupant of the vehicle, wherein the wireless charger is communicably connected to predetermined equipment which is provided to the vehicle, and when wireless communication between the in-vehicle wireless communication device and the electronic key is performed, the controller stops power transmission performed by the power transmission part in a case where a predetermined signal which is transmitted from the predetermined equipment is received before the antenna is driven. |
| US09748789B2 |
Charging/discharging control circuit, charging/discharging control device, and battery device
There is provided a battery device in which the accuracy of an over-current detection current value is high to have high safety. In a charging/discharging control circuit, a reference voltage circuit of an over-current detection circuit is configured to include a constant current circuit, a resistor, and a transistor having a resistance value that varies with a voltage of a secondary cell, that are connected to both ends of the secondary cell, and outputs, as a reference voltage, a voltage that is generated due to the flowing of a current of the constant current circuit to the resistor and the transistor. |
| US09748786B2 |
Battery stack with leapfrogging protocol
Embodiments of the present invention are directed to a battery stack with a leapfrogging communication network. Each cell stage may include a controller, a transmitter, and a pair of receivers. The cell stage in the battery stack may be coupled to the closest two preceding battery cell stages in the stack. In this manner, each cell stage may be able to determine if a fault is present in an immediately preceding cell stage in the stack by monitoring the first preceding cell stage and the second preceding cell stage. If discharge/charge commands transmitted by the second preceding cell stage are not reaching the battery cell stage at issue, the controller may determine that there is a fault in the first preceding cell stage and discharge/charge the cell stage based on the commands transmitted by the second preceding cell stage. |
| US09748783B2 |
Smart voltage dedicated charger system
A voltage dedicated charger apparatus includes an AC-to-DC converter circuit, a pair of switches, and a controller block. The AC-to-DC converter circuit converts an AC input voltage to a DC output voltage. The pair of switches is operable to isolate a pair of data ports from the AC-to-DC converter circuit. The pair of data ports includes a DP port and a DN port. The controller block includes a monitor circuit, a transceiver, and a control circuit. The monitor circuit monitors the DP and DN ports of the apparatus. The transceiver receives one or more messages form a charge-receiving device and communicate data to the charge-receiving device. The control circuit controls operation of the pair of switches based on a signal from the monitor circuit. |
| US09748779B1 |
Conditionally delayed charging of a barcode reader's rechargeable battery
A barcode reader may include a barcode reading system, a rechargeable battery, and a battery charging system. The battery charging system may be configured so that, in response to detecting placement of the barcode reader in a charging cradle, the battery charging system delays charging the battery if a charge level of the battery is above a first threshold level. |
| US09748778B2 |
Power supply apparatus
A power supply apparatus includes: a connection unit to which a battery pack is connected; a power conversion unit which converts direct current power output from the battery pack via the connection unit into a first power; a power plug which is connected to an external power source; a power supplying unit to which a power receiving unit of the external apparatus is connected to supply the first power output from the power conversion unit or a second power which is the power supplied from the external power source via the power plug; and a switching unit which switches between outputting the first power to the power supplying unit and outputting the second power to the power supplying unit. |
| US09748776B2 |
Apparatus for storing and releasing electrical energy using a flywheel and a plurality of electrochemical accumulators
An apparatus for transferring energy from cell to cell of a battery, wherein each cell is connected to its individual electrical motor/alternator through an electronic module, and wherein each motor/alternator is mechanically connected to a common flywheel. The electrical motor/alternator preferably is an electrical motor that provides rotational work and generates power when being driven by an external source of rotational kinetic energy or by an external source of rotational power. The common flywheel stores rotational kinetic energy. Cells of the battery provide various torque on the flywheel or on the shaft driving the flywheel. Cells with higher than average output current will provide higher than average torque, thus providing higher than average kinetic energy input to the flywheel, while cells with lower than average output current will provide lower than average torque, or will provide negative torque, the motor/alternator acting then as an alternator recharging the cell. |
| US09748774B2 |
System and method for bidirectional wireless power transfer
The present invention relates to a wireless power supply system including a remote device capable of both transmitting and receiving power wirelessly. The remote device includes a self-driven synchronous rectifier. The wireless power supply system may also include a wireless power supply configured to enter an OFF state in which no power, or substantially no power, is drawn, and to wake from the OFF state in response to receiving power from a remote device. |
| US09748772B2 |
Method of controlling a solar power plant, a power conversion system, a DC/AC inverter and a solar power plant
A solar power plant including a power conversion system and a method of controlling the power conversion system. Implemented in a DC/AC inverter, the plant includes photovoltaic modules (PV modules) arranged in arrays connected to a respective DC/DC converters. A power collecting grid interfaces between the DC/DC converters and the DC/AC inverter. The method includes monitoring the performance of each PV array by adjusting the voltage level of each interface between a PV array and the corresponding DC/DC converter, and includes monitoring the output power of each DC/DC converter as a feedback for the regulating. |
| US09748770B2 |
Using demand side resources to provide frequency regulation
In a direct load control system supporting frequency control of an electrical grid, at each electrical load of an aggregation of loads, a load status report is generated comprising an urgency value and a power level. At an aggregation dispatch controller, a dispatch signal is generated based on the generated load status reports and information indicative of electrical frequency. At each electrical load of the aggregation, the load is operated at the reported power level if the reported urgency value satisfies the dispatch signal and is not operated at the reported power level if the reported urgency value does not satisfy the dispatch signal. |
| US09748768B2 |
Pre-charging and voltage supply system for a DC-AC inverter
A pre-charging and voltage supply system for a DC-AC inverter is provided. The system includes a first battery having a first anode and a first cathode, and a second battery having a second anode and a second cathode. The first cathode is electrically isolated from the second cathode. The system includes a contactor coupled in series between the first anode and an electrical node. The system includes a microprocessor that generates a first control signal to induce a DC-DC voltage converter to increase a voltage level applied to the DC-AC inverter. The microprocessor generates a second control signal to induce the contactor transition to a closed position such that a first voltage level is applied to the DC-AC inverter, if the voltage level between the electrical node and the first cathode is greater than a threshold voltage level. |
| US09748765B2 |
Load allocation for multi-battery devices
This document describes techniques and apparatuses of load allocation for multi-battery devices. In some embodiments, these techniques and apparatuses determine an amount of load power that a multi-battery device consumes to operate. Respective efficiencies at which the device's multiple batteries are capable of providing power are also determined. A respective portion of load power is then drawn from each of the batteries based on their respective efficiencies. |
| US09748763B2 |
Circuit protection devices and methods of monitoring protection devices in a power distribution system
Circuit protection devices, power distribution systems, and methods of monitoring circuit protection devices are described. In one example, a method of monitoring a circuit protection device in a zone selective interlocking (ZSI) system includes monitoring a variable associated with operation of the circuit protection device, determining, based at least in part on the monitored variable, when a likelihood of a malfunction of the circuit protection device exceeds a predetermined threshold, and preventing the circuit protection device from outputting a ZSI blocking signal when the likelihood of the malfunction of the circuit protection device exceeds the threshold. |
| US09748756B2 |
Cable combination device
A cable combination device includes joint terminals configured to be mounted at a joint part formed by jointing a main cable and a branch cable to each other to fix the main cable and the branch cable; a housing configured to have the joint part inserted and mounted therein; and a clip configured to be provided on the housing and fixed to a vehicle body, such that moisture introduction may be prevented by improving water proof performance of the cable, and the cable may be stably mounted in a vehicle by the clip. Therefore, a wiring of the vehicle may be lightened, and at the same time, a cost may be decreased, thereby making it possible to improve marketability. |
| US09748755B1 |
Clip-based non-metallic fittings for attachment of flexible metallic conduit
Systems and methods are provided for attaching flexible conduit to a fitting. Prongs of a conduit retention clip contact opposite sides of the flexible conduit in an aperture of the fitting. By aligning the prongs in grooves of the flexible conduit, the flexible conduit is held in place in the aperture of the fitting without sufficient compression to surpass the structural limits of the fitting. |
| US09748750B2 |
Electrical connection box
The present invention suppresses an increase in the number of components and simplifies an attachment task. An electrical connection box is configured such that multiple wire harnesses are connected thereto side-by-side vertically. The electrical connection box includes: a lower case having a lower placement portion on which a lower wire harness is to be placed; a harness support member having a lower holding portion that is latched to the lower placement portion and holds the lower wire harness, and having an upper placement portion on which an upper wire harness is to be placed; and an upper case that is mated to the lower case and has an upper holding portion that is latched to the upper placement portion and holds the upper wire harness. |
| US09748747B2 |
Disposable optical fiber coating removal tool
A device to strip the external coating layer off of a coated optical fiber is provided. The optical fiber coating removal device includes a one piece molded body having a first body portion connected to a second body portion by a flexible region and a blade secured in one of the first body portion and the second body portion wherein the blade includes a U-shaped slot having cutting edges on the inside of the slot, wherein the flexible portion allows the first and second body portions to move between an open state and a closed state for stripping an optical fiber. |
| US09748744B2 |
Electrical enclosure with interchangeable pedestal mounting system
A electrical enclosure with interchangeable pedestal mounting system for an electrical enclosure that may be attached to different types of pedestals. The electrical enclosure with interchangeable pedestal mounting system generally includes a base having a mounting structure that allows for attachment of the base to at least two different pedestals. The mounting structure includes one or more support members that allow for attachment to a rectangular pedestal or a circular pedestal thereby allowing an installer to utilize their preferred pedestal type. |
| US09748737B2 |
Laser element and laser device
A laser element includes a photonic crystal layer on which laser light is incident. The photonic crystal layer includes a base layer formed of a first refractive index medium; and a plurality of different refractive index regions formed of a second refractive index medium having a refractive index different from that of the first refractive index medium and disposed in the base layer. The plurality of different refractive index regions includes a first different refractive index region of which a planar shape is an approximate circle, an approximate square, or an approximate polygon having a rotational symmetry of 90° and a first area perpendicular to a thickness direction; and a second different refractive index region having a second area perpendicular to a thickness direction. |
| US09748736B1 |
Waveguide embedded plasmon laser with multiplexing and electrical modulation
This disclosure provides systems, methods, and apparatus related to nanometer scale lasers. In one aspect, a device includes a substrate, a line of metal disposed on the substrate, an insulating material disposed on the line of metal, and a line of semiconductor material disposed on the substrate and the insulating material. The line of semiconductor material overlaying the line of metal, disposed on the insulating material, forms a plasmonic cavity. |
| US09748735B2 |
Light-effect transistor (LET)
Example photoconductive devices and example methods for using photoconductive devices are described. An example method may include providing a photoconductive device having a metal-semiconductor-metal structure. The method may also include controlling, based on a first input state, illumination of the photoconductive device by a first optical beam during a time period, and controlling, based on a second input state, illumination of the photoconductive device by a second optical beam during the time period. Further, the method may include detecting an amount of current produced by the photoconductive device during the time period, and based on the detected amount of current, providing an output indicative of the first input state and the second input state. The example devices can be used individually as discrete components or in integrated circuits for memory or logic applications. |
| US09748734B1 |
Apparatus and method for driving laser diode arrays with high-power pulsed currents using low-side linear drive with laser diode array protection and power efficiency monitoring and adjustment
A multi-stage laser drive circuit includes a variable common potential source, a PA light-emitting array between a storage capacitor and a current node, first and second low-side linear current sinks in electrical communication with the current node, and a second master oscillator (MO) light-emitting array in electrical communication between the current node and the first low side linear current sink. A trickle current circuit drives a low-value trickle current through the arrays, and a sense circuit senses the trickle current. Also, the headroom voltage across a pass element in the first low-side linear constant current sink is monitored and adjusted for maximum efficiency. |
| US09748727B2 |
Preliminary ionization discharge device and laser apparatus
A preliminary ionization discharge device used in a laser chamber of a laser apparatus using preliminary ionization includes a dielectric pipe; a preliminary ionization inner electrode provided inside the dielectric pipe; and a preliminary ionization outer electrode provided outside the dielectric pipe. The preliminary ionization outer electrode includes: a contact plate part configured to contact the dielectric pipe; and an elastic part configured to exert a force in a direction in which the contact plate part pushes the dielectric pipe. |
| US09748726B1 |
Multiple-microresonator based laser
This invention describes algorithmic and computational approaches to optimize the design and performance of microresonator based ultra-low noise lasers including a reflector or filter comprised of multiple (≧3) microresonator rings with different ring radii coupled together through bus waveguides. The enhanced reflector/filter design optimization provides more control over the key parameters, including the suppression ratio of unwanted modes over both a wide wavelength range (supporting wide wavelength tunability) and over the narrow range around the laser wavelength (improving laser singlemode and noise performance), while also enabling the design of specific reflector/filter bandwidth and effective length (delay), supporting the design of an ultra-low noise laser with specific operating performance parameters. |
| US09748724B2 |
Method of connecting electric cable to connector terminal and compression-molding die
A method of connecting an electric cable to a connector terminal includes arranging a connector terminal in a lower die so that an end portion of the electric cable in which a core wire is exposed from an outer cover is arranged in a barrel portion of the connector terminal, pressing a crimper to the barrel portion to crimp the barrel portion, overlapping the lower die with an upper die to form an injection space around the barrel portion and the end portion of the electric cable, and injecting a resin in an injection space, thereby forming a resin mold that covers and waterproofs the barrel portion and the end portion of the electric cable. |
| US09748715B2 |
Modular socket panel and layer module for modular socket panel
The present invention discloses a modular socket panel which includes a bottom layer adapted to be fixed to an embedded case in a wall and adapted to be electrically connected to a power supply provided by the embedded case, and a surface layer adapted to be directly or indirectly connected to the bottom layer in a non-fastening manner. The surface layer provides a power socket, which is electrically connected to the bottom layer. The modular socket panel disclosed in the present invention enables a user to mount a middle layer and the surface layer onto the bottom layer or remove the middle layer and surface layer from the bottom layer without any tool, and also enables the user to mount different middle layers in the modular socket panel when needed to implement different functions, for example adding more intelligent functions. |
| US09748713B2 |
Horizontally configured connector
A connector includes at least a pair of mating portions and each mating portion includes a at least one mating blade. The connector body has a height that is greater than twice a height of the mating portion. Flanges can be provided on both sides of the mating blade. |
| US09748712B2 |
Electrical connector having inserted insulator and method of making the same
An electrical connector includes an insulative housing, a number of first contacts and second contacts, an insulator inset-molded with the first contacts, a metallic shielding plate retained in the insulative housing, and a shielding shell attached to the insulative housing. The housing has a base portion defining a receiving cavity located at a back-end thereof and extending forwardly and a tongue portion extending forwardly from the base portion. The tongue portion defines a first surface carrying the first contacts and a second surface located oppositely and a number of terminal-receiving slots located at the first surface and the second surface and communicated with receiving cavity. The second contacts are inserted into terminal-receiving slots located at the second surface. The insulator is received in the receiving cavity to insert the first contacts into the terminal-receiving slots located at the first surface. |
| US09748710B2 |
RF connector with push-on connection
An RF connector is provided. The connector includes a first socket member. The first socket member includes a conductive sleeve comprising a top portion, a bottom portion, and a plurality of springs connecting the top portion and the bottom portion. The first socket member also includes a base inside the conductive sleeve comprising a first matching hole configured to match to a first conductive pin of a first plug member. The connector also includes a second socket member. The second socket member includes a second matching hole configured to match to a second conductive pin of a second plug member, and a conductive body having outer threads configured to match to inner threads of the second plug member. The connector further includes a middle portion connected between the first socket member and the second socket member, the middle portion extending radically outwardly from a periphery of the middle portion. |
| US09748707B2 |
Signal transmission cable
A signal transmission cable has a cable including a dielectric layer and a metallic layer. The signal transmission cable further includes a connector having a chip with a terminal. The connector includes a substrate having an organic layer, and a portion of the organic layer extends from the substrate so as to form the dielectric layer of the cable. The metallic layer is located on the dielectric layer and is directly connected to the terminal. |
| US09748706B2 |
Electrical connector having improved detective member
An electrical connector connecting with a cable electrically includes a mating member, a printed circuit board connected with the mating member and the cable electrically, a light source positioned on the printed circuit board, a detector controlling the light source, a light transmissive member permitting transmission of a light emitted from the light source therethrough, a metal shell enclosing the light transmissive member and the printed circuit board, and a detective member connecting the detector and the metal shell electrically. |
| US09748705B2 |
Contact structure
A contact structure is provided. The contact structure suppresses arcing that can occur between contacts that establish a live connection, without increasing the size of the contact structure, and without making longer the length of the inserting/drawing stroke of a correspondingly formed contact. A live contact portion of a first contact, and an auxiliary contact portion of an auxiliary contact body configured with a high resistance resistor having a base end connected portion that establishes an electrical connection with the first contact front on a movement path of a second contact at positions that are shifted in front and rear directions while being distanced by a width that allows simultaneously contact with the second contact. If the second contact separates from the first contact, the auxiliary contact body configured with the high resistance resistor intervenes between the first contact and the second contact, and inhibits arcing. |
| US09748699B1 |
Screw boss assemblies and methods
Systems and methods for providing screw bosses on a substrate. The substrate can be dimpled. The dimples can then be threaded to accept screw bosses. The dimples can be threaded using a threading die or can have threads cut by self-tapping screw bosses. An adhesive can be applied to the substrate, the bottom of the screw boss, or both. The screw bosses can include standoffs to determine the distance between the bottom of the screw boss and the substrate. The screw bosses can be threaded onto the dimples and can provide threads for attaching items to the substrate. A filler material can be applied to the reverse side of the substrate to fill-in the dimples and present a smooth surface. A decorative or protective layer can be applied over the filler material. |
| US09748698B1 |
Electrical connector having commoned ground shields
An electrical connector includes a housing, signal pods, and ground shields. The housing has a base that is electrically conductive. The base has chambers and ground slots extending therethrough. The chambers are defined by chamber walls that separate the chambers from the ground slots. The signal pods, which each include a dielectric body holding a pair of signal contacts, are received in the chambers. The dielectric body engages the chamber walls and electrically insulates the signal contacts from the base. The ground shields are received in the ground slots. Each ground shield surrounds an associated signal pod on at least two sides to provide electrical shielding for the signal contacts in the signal pod from other signal contacts. |
| US09748694B2 |
Connector and connectorized cable
A connector for being fitted to an other member so as to be prevented from disengaging by a locking piece on the other member includes a connector housing including a recessed portion engaged with the locking piece, and a sliding member that slidably moves relative to the connector housing. The connector housing is formed by coupling a first housing member and a second housing member, a tip portion of the locking piece coming into sliding contact with a side surface having the recessed portion when removing the connector housing from the other member. At least a portion of a seam between the first and second housing members on the side surface is inclined relative to a direction of attaching/detaching to/from the other member, the portion being firstly crossed by the tip portion of the locking piece when removing the connector housing from the other member. |
| US09748691B2 |
Latch assembly for low-profile right-angle electrical connector
A low-profile, right angle connector assembly comprises six cable connectors and six board-mount connectors housed within a PCIe bracket and EMI shell. The PCIe bracket and EMI shell are braced to a low profile PCIe card. Each board-mount connector is designed to receive a cable connector and allows for the transmission and processing of high-speed data with lower latency. A removable latch mounted on the cable connectors helps ensure the cable connectors remain physically connected to the board-mount connectors. The removable latch may be replaced as needed for breakage and wear and tear. |
| US09748690B2 |
Connector
A connector is provided with a connector housing including an elastic engagement arm as a part to be engaged with a mate connector serving as a mate to which the connector is fitted and a terminal accommodation chamber which accommodates therein a terminal of an electric wire having a terminal, and a rear holder including a holder side engagement part engaged with a housing side engagement part provided in the connector housing so as to be connected to the connector housing at a position of a rear end side in a fitting direction to the mate connector. |
| US09748689B1 |
Module assembly and connector and electronic device
Provided are a module assembly, a connector, and an electronic device, the module assembly including a first module that includes a pin configured to selectively protrude from a side thereof, a pin installation portion in which the pin is installed to be movable, and a first magnet configured to attract the pin into the pin installation portion, a second module to be coupled to the first module, the second module including a pin receiver configured to receive the pin when the pin protrudes from the first module, and a second magnet configured to attract the pin into the pin receiver, wherein the second magnet is configured to apply, to the pin, a greater magnitude of magnetic force than the first magnet in a case in which a distance between the first module and the second module is less than a preset distance. |
| US09748687B2 |
Shielding connector
A connector has a front shell and a back shell. The front shell is provided with a first contact portion and a fixed portion. The first contact portion surrounds a periphery of the fixed portion in a plane orthogonal to a predetermined direction. The back shell is provided with an opening portion and a second contact portion. The second contact portion surrounds a periphery of the opening portion in a plane orthogonal to the predetermined direction. The second contact portion is in contact with the first contact portion in the predetermined direction so that the fixed portion is visible within the opening portion in the predetermined direction and that the back shell is positioned with respect to the front shell. The fixed portion and the second contact portion are fixable to each other using a conductive fixing agent through the opening portion. |
| US09748686B1 |
BGA spring probe pin design
An improved BGA spring probe pin with a spring actuated solder ball receptacle that grips the sides of the solder ball during probing. A method of operating a BGA prober with improved BGA spring probe pins. |
| US09748683B2 |
Electroconductive material superior in resistance to fretting corrosion for connection component
An electroconductive material includes a Cu or Cu alloy base member, a Cu—Sn alloy coating layer, and a Sn coating layer. The Cu—Sn alloy coating layer has a Cu content of 20 to 70 atomic %, and an average thickness of 0.2 to 3.0 μm. The Sn coating layer has an average thickness of 0.2 to 5.0 μm. A surface of the electroconductive material has an arithmetic average roughness Ra of at least 0.15 μm in at least one direction along the surface and 3.0 μm or less in all directions along the surface. The Cu—Sn alloy coating layer is partially exposed at the surface of the electroconductive material. An area ratio of the Cu—Sn alloy coating layer exposed at the surface of the electroconductive material is 3 to 75%. An average crystal grain size on a surface of the Cu—Sn alloy coating layer is less than 2 μm. |
| US09748673B1 |
Terminal block and electronic appliance
A terminal block includes: a terminal body with a screw hole for a screw used to connect a wire; and a terminal holder that holds the terminal body and has a substrate facing portion placed facing a first surface of a substrate. The terminal block is attached to the substrate by soldering the terminal body to a conductive pattern of the substrate with the substrate facing portion facing the first surface. The terminal holder has the substrate facing portion at one end in a first direction that becomes parallel to the thickness of the substrate when the terminal block is attached to the substrate. A casing fixing portion equipped with an insertion portion, into which a fastener for fixing the terminal holder to a casing that houses the substrate is inserted, is provided at another end in the first direction of the terminal holder. |
| US09748667B2 |
Terminal device and antenna switching method
A terminal device includes a first memory that stores a position of each of antennas included in a main body of a terminal device for each of holding manners for the main body of the terminal device, a second memory, a processor coupled to the second memory, configured to detect a holding manner for the main body of the terminal device including the antennas, detect a shape indicating a shadow of an object pointing to a surface of the terminal device, identify a holding hand that holds the main body of the terminal device, based on the detected shape, and switch an antenna which overlaps with the holding hand to another antenna based on the identified holding hand and the position of each antenna stored in the first memory, the antenna corresponding to the detected holding manner. |
| US09748661B2 |
Antenna for achieving effects of MIMO antenna
An antenna disposed on a substrate includes a radiating portion, a first coupling and feeding portion, and a second coupling and feeding portion. A length of the radiating portion is substantially equal to a half wavelength of electromagnetic signals radiated by the radiating portion. Each coupling and feeding portion includes a feeding part and a coupling part. The feeding part feeds the electromagnetic signals to the radiating portion via the coupling part so as to achieve effects of a multiple-input multiple-output (MIMO) antenna. |
| US09748659B2 |
High gain antenna structure
An antenna structure includes a dipole antenna element, a meandering connection line, and a cascade radiation element. The dipole antenna element includes a feeding radiation element and a grounding radiation element. The feeding radiation element has at least one open slot. The cascade radiation element is coupled through the meandering connection line to the feeding radiation element. |
| US09748656B2 |
Broadband patch antenna and associated methods
The patch antenna includes an electrically conductive patch carried by a dielectric substrate and having a planar shape and a feed point defined therein. A feed conductor is coupled to the feed point of the electrically conductive patch, and a plurality of electrically conductive wings extend upwardly from a periphery of the electrically conductive patch. A method aspect may include adjusting at least one property (e.g. frequency) of the antenna by angling at least one of the plurality of electrically conductive wings outwardly from the electrically conductive patch. |
| US09748650B2 |
Antenna structure and wireless communication device using same
An antenna structure includes a feed unit, a grounding unit, a first radiating unit, a second radiating unit, third radiating unit, fourth radiating unit, and a fifth radiating unit. The grounding unit is spaced apart from the feed unit. The first radiating unit is electrically connected to the feed unit. The second radiating unit is electrically connected to the grounding unit. The third radiating unit is electrically connected to the first radiating unit, the second radiating unit, and the fourth radiating unit. The fifth radiating unit is electrically connected to the feed unit and couples with the fourth radiating unit. |
| US09748649B2 |
Antenna module and electronic apparatus including the same
An antenna module and an electronic apparatus include: an antenna element, and a clip which includes an antenna pattern, is formed of a metallic material, and electrically connects the antenna element to a circuit board to process an antenna signal through the antenna pattern. |
| US09748648B2 |
Distributed feeding device for antenna beamforming
A distributed feeding device for antenna beamforming comprises a first distributed feeding circuit comprising P inputs and N outputs, for producing a signal on each of its outputs with a phase shift which is substantially constant between two adjacent outputs, at least one frequency multiplexer connected to at least one input of the said first circuit, a number N of frequency demultiplexers each connected, by their input, to an output of the first circuit and a second distributed feeding means comprising a plurality of inputs, each connected to an output of one of the frequency demultiplexers, and a plurality of outputs, the second distributed feeding means comprising at least one second distributed feeding circuit comprising Q inputs and M outputs, for producing a signal on each output with a phase shift which is substantially constant between two adjacent outputs, the integers P, N, Q and M being equal or distinct. |
| US09748647B2 |
Frequency routing based on orientation
Systems, methods, and apparatus for frequency routing based on orientation are disclosed. An example method includes receiving, by a playback device, an audio data stream. The example method includes determining, by the playback device, an orientation of the playback device. The example method includes routing, by the playback device, a first set of frequencies in the audio data stream to at least one of a plurality of speaker drivers based on the first orientation. The example method includes routing, by the playback device, a second set of frequencies in the audio data stream to the at least one of the plurality of speaker drivers based on the second orientation, wherein the first set of frequencies is different than the second set of frequencies. |
| US09748646B2 |
Configuration based on speaker orientation
Systems, methods, and apparatus to shape sound based on a speaker orientation. An example playback device includes a network interface; a processor; and a memory including instructions stored therein. The instructions are executable by the processor to perform functions including: receiving, via the network interface from a network device, an indication that an orientation of the playback device is one of a first orientation or a second orientation; when the received indication is the first orientation, then configuring the playback device to reproduce sound according to a first equalization setting; and when the received indication is the second orientation, then configuring the playback device to reproduce sound according to a second equalization setting. |
| US09748643B2 |
Identification or messaging systems and related methods
An identification or messaging system is provided that has embodiments including a embodiment with a structure with different faces and a base with reflective or resonance panels which are positioned at different receiving angles to detect direct signals and amplify them including in a sequence to be detected by an active emitter that emits electromagnetic radiation that is reflected and steered or resonated off or with the panels. An emitter can be an aerial platform with the emitter and a library of reflected or resonated signals that are associated with a particular sequence of panels on the structure which are associated with a particular entity identification or message. Thermal patterned and/or magnetic patterned panels (e.g., for backplane beamforming) and return signal steering can also be provided. Embodiments with secondary signaling systems can also be provided. A variety of various embodiments and methods are also provided. |
| US09748637B2 |
Antenna and method for steering antenna beam direction for wifi applications
An antenna comprising an IMD element and one or more parasitic and active tuning elements is disclosed. The IMD element, when used in combination with the active tuning and parasitic elements, allows antenna operation at multiple resonant frequencies. In addition, the direction of antenna radiation pattern may be arbitrarily rotated in accordance with the parasitic and active tuning elements. Unique antenna architectures for beam steering in Wi-Fi band applications is further described. |
| US09748633B2 |
Antenna structure
An antenna structure includes a feed end, a ground end, a first radiator, a second radiator, and a third radiator. Both of the first radiator and the second radiator are connected to the feed end. The second radiator includes a first connection section and a second connection section. The third radiator is connected to the ground end, and includes a first coupling section separated from the first connection section and a second coupling section separated from the second connection section. A first gap is defined between the first coupling section and the first connection section; and a second gap is defined between the second coupling section and the second connection section. |
| US09748625B2 |
High-frequency transmission line and electronic device
A transmission line portion of a flat cable includes first regions and second regions connected alternately. In the first region, the transmission line portion is a flexible tri-plate transmission line including a dielectric element including a signal conductor, a first ground conductor including opening portions, and a second ground conductor which is a solidly filled conductor. In the second region, the transmission line portion is a hard tri-plate transmission line including a wide dielectric element including a meandering conductor, and a first ground conductor and a second ground conductor which are solidly filled conductors. A variation width of the characteristic impedance in the second region is larger than a variation width of the characteristic impedance in the first region. |
| US09748624B2 |
Non-reciprocal circuit element
A non-reciprocal circuit element includes a ferrite, a first central electrode and a second central electrode that are arranged on the ferrite so as to cross each other in an insulated state, and a permanent magnet configured to apply a DC magnetic field to a portion where the first and second central electrodes cross each other. One end of the first central electrode defines an input port and the other end thereof defines an output port. One end of the second central electrode defines the input port and the other end thereof defines a ground port. A resistance element and a capacitance element which are connected in parallel with each other are connected in series between the input port and the output port. A switching capacitance unit configured to switch a capacitance is connected in parallel with the resistance element between the input port and the output port. |
| US09748618B2 |
Battery assembly having a heat-dissipating and heat-emitting functions
According to one embodiment of the present invention, a battery assembly comprises: a battery module comprising a plurality of unit batteries; an exterior case for housing the battery module in an internal space; and a heat-dissipating film which is inserted between the plurality of unit batteries and fitted tightly against each of the plurality of unit batteries, and is attached to the inside surface of the exterior case; and the heat-dissipating film comprises: first and second heat-dissipating layers which are formed of a thermally conductive material and discharge the heat of the unit batteries; and an adhesive layer which is formed between the first and second heat-dissipating layers and adheres the first and second heat-dissipating layers. |
| US09748615B2 |
Rechargeable lithium batteries comprising means for the sorption of harmful substances in the form of a multilayer polymeric sheet
Rechargeable lithium batteries are described comprising an airtight container, electrodes immersed in an electrolytic solution and spaced apart by means of one or more separators, electrical contacts connected to the electrodes and a means for sorbing harmful substances formed of a multilayer polymeric sheet comprised of an inner layer of a polymeric material containing particles of one or more getter materials for the sorption of the harmful substances, and at least one external protective layer of a polymeric material impermeable to the electrolyte, wherein all the polymeric materials are permeable to the harmful substances. |
| US09748610B2 |
Spirally-wound lithium battery
A spirally-wound lithium battery includes: a bottomed cylindrical cell can doubling as an anode current collector; and a strip-shaped electrode body including an anode and a cathode arranged faced each other via a separator, the anode including an anode active material of lithium metal or alloy, the cell can being sealed, with a non-aqueous organic electrolyte, containing the electrode body wound in a longitudinal direction, the electrode body being wound from a winding axis side around the axis in a vertical direction, an extending direction of a cell can cylindrical axis, such that the anode is arranged at an outermost circumference, the electrode body is attached with a conductor, continuously extending in the longitudinal direction thereof, on an outer circumferential surface of the anode, from a winding end of the anode to an area thereof opposed to an inner surface of the cathode on its winding end side. |
| US09748601B2 |
Method of manufacturing lithium ion conductive solid electrolyte and lithium-ion secondary battery
A method of manufacturing a lithium ion conductive solid electrolyte includes (a) a step of preparing an object to be processed including a crystalline material, that includes alkali metal other than lithium and whose ionic conductivity at room temperature is greater than or equal to 1×10−13 S/cm; and (b) a step of performing an ion-exchange process on the object to be processed in molten salt including lithium ions. |
| US09748600B2 |
Phosphate based composite anode material, preparation method and use thereof
The present invention relates to a novel phosphate based composite anode material, preparation method and uses thereof. Specifically disclosed is a phosphate based composite cell anode material, the material having monoclinic and orthorhombic crystal lattice structures with the chemical formula of A3−xV2−yMY(PO4)3, wherein A is Li+, Na+ or the mixture thereof, M is Mg, Al, Sc, Ti, Cr, Mn, Fe, Co, Ni, Cu, Zn or Nb, 0≦x≦3.0, 0≦y≦2.0, and C is the carbon layer. Also disclosed are a preparation method and uses of the composite material. Unlike simple physical mixing, the composite material of the present invention has the advantages of an adjustable electric potential plateau, high reversible capacity, good cycle stability, power consumption early warning and the like. |
| US09748599B2 |
Phased introduction of lithium into the pre-lithiated anode of a lithium ion electrochemical cell
The present invention relates to a method for combining anode pre-lithiation, limited-voltage formation cycles, and accelerating aging via heated storage to maximize specific capacity, volumetric capacity density and capacity retention of a lithium-ion electrochemical cell. |
| US09748597B2 |
Flexible electrode assembly and electrochemical device including the electrode assembly
An electrode assembly including an electrode structure including a first electrode plate and a second electrode plate which are alternately disposed, and a separator film that is disposed between the first electrode plate and the second electrode plate, wherein a surface of the separator film is bonded to the first electrode plate, and a binding member, which rigidly connects at least one selected from the first electrode plate, the second electrode plate, and the separator film. |
| US09748595B2 |
High-energy-density, aqueous, metal-polyiodide redox flow batteries
Improved metal-based redox flow batteries (RFBs) can utilize a metal and a divalent cation of the metal (M2+) as an active redox couple for a first electrode and electrolyte, respectively, in a first half-cell. For example, the metal can be Zn. The RFBs can also utilize a second electrolyte having I−, anions of Ix (for x≧3), or both in an aqueous solution, wherein the I− and the anions of Ix (for x≧3) compose an active redox couple in a second half-cell. |
| US09748594B2 |
Polymer of fluorine-containing sulfonated poly(arylene ether)s and method of manufacturing the same
A polymer of fluorine-containing sulfonated poly(arylene ether)s and a manufacturing method thereof are provided. The polymer is formed by processing a nucleophilic polycondensation between a fluorine-containing monomer having an electron-withdrawing group and a multi-phenyl monomer. A main structure of the polymer of fluorine-containing sulfonated poly(arylene ether)s has a first portion with fluoro or trifluoromethyl substituted phenyl groups, and a second portion with sulfonated phenyl groups. |
| US09748593B2 |
Polymer electrolyte composition, and polymer electrolyte membrane, membrane electrode complex and solid polymer-type fuel cell each produced using same
The present invention provides: a polymer electrolyte composition which can achieve excellent proton conductivity under slightly humidified conditions, excellent mechanical strength and excellent physical durability, has excellent practicality, and can be produced using a nitrogen-containing additive, wherein the nitrogen-containing additive can prevent the elution of the additive under a strongly acidic atmosphere during the operation of a fuel cell, has excellent chemical stability so as to tolerate a strongly acidic atmosphere, can be dissolved in various general-purpose organic solvents, has superior processability, can be mixed with an ionic-group-containing polymer, can prevent the occurrence of phase separation during the formation of a film, and can prevent the formation of an island-in-sea-like phase separation structure or the occurrence of bleeding out during the formation of a film; and a polymer electrolyte membrane, a membrane electrode assembly and a polymer electrolyte fuel cell, each of which is produced using the polymer electrolyte composition. The polymer electrolyte composition according to the present invention comprises at least an ionic-group-containing polymer (A) and a nitrogen-containing additive (B), said polymer electrolyte composition being characterized in that the nitrogen-containing additive (B) is represented by a specific structural formula. |
| US09748592B2 |
Electrolyte generation within a fuel cell
An exemplary method of providing an electrolyte for a fuel cell comprises including a electrolyte precursor within a fuel cell. An electrolyte is generated within the fuel cell from the precursor. An exemplary fuel cell system includes a cell stack assembly. A manifold is associated with the cell stack assembly. An electrolyte precursor is within at least one of the cell stack assembly or manifold for generating an electrolyte within a fuel cell. |
| US09748591B2 |
Filtering device, in particular for the air to be supplied to a fuel cell
A filtering device features a carrier medium and activated carbon as adsorbent which is immobilized due to the addition of adhesive. |
| US09748585B2 |
Cooling system for fuel cells
A fuel cell stack assembly comprises a stack of fuel cells, each fuel cell having a cooling air conduit with an input/output ventilation aperture disposed on a ventilation face of the stack. The ventilation apertures form an array over said ventilation face of the stack. A first fan is configured to direct air flow through a first portion of the ventilation face and a second fan is configured to direct air flow through a second portion of the ventilation face. A reconfigurable plenum is in fluid communication with the first fan and the second fan and has a first configuration in which air is directed, by the first and second fans, through the first and second portions of the ventilation face in the same direction, and a second configuration in which air is directed, by at least one of the fans, respectively through the first and second portions of the ventilation face in opposing directions. When operating in the second configuration, the directions of air flow through the first and second portions of the ventilation face are periodically reversed. |
| US09748578B2 |
Battery and battery plate assembly
A battery plate assembly for a lead-acid battery is disclosed. The assembly includes a plates of opposing polarity each formed by an electrically conductive grid body having opposed top and bottom frame elements and opposed first and second side frame elements, the top frame element having a lug and an opposing enlarged conductive section extending toward the bottom frame element; a plurality of interconnecting electrically conductive grid elements defining a grid pattern defining a plurality of open areas, the grid elements including a plurality of radially extending vertical grid wire elements connected to the top frame element, and a plurality of horizontally extending grid wire elements, the grid body having an active material provided thereon. A highly absorbent separator is wrapped around at least a portion of the plate of a first polarity and extends to opposing plate faces. An electrolye is provided, wherein substantially all of the electrolyte is absorbed by the separator or active material. A method for assembling a battery is also disclosed. |
| US09748576B2 |
Polymer, binder and negative electrode including the polymer, and lithium battery including the negative electrode
A polymer including a first repeating unit including at least one carboxyl group substituted with a cation and a second repeating unit including at least one carboxyl group substituted with a moiety containing a dihydroxyphenyl group. |
| US09748571B2 |
Cathode material with oxygen vacancy and manufacturing process thereof
A cathode material with oxygen vacancy is provided. The cathode material includes a lithium metal phosphate compound having a general formula LiMPO4-Z, wherein M represents at least one of a first-row transition metal, and 0.001≦z≦0.05. |
| US09748568B2 |
Manganese oxide nanoparticles, methods and applications
Manganese oxide nanoparticles having a chemical composition that includes Mn3O4, a sponge like morphology and a particle size from about 65 to about 95 nanometers may be formed by calcining a manganese hydroxide material at a temperature from about 200 to about 400 degrees centigrade for a time period from about 1 to about 20 hours in an oxygen containing environment. The particular manganese oxide nanoparticles with the foregoing physical features may be used within a battery component, and in particular an anode within a lithium battery to provide enhanced performance. |
| US09748562B2 |
Negative active material, negative electrode including the negative active material, and lithium secondary battery including the negative electrode
A negative active material including graphite; silicon nanowires; and silicon nanoparticles, wherein a silicon nanowire of the silicon nanowires and a silicon nanoparticle of the silicon nanoparticles are each disposed on a particle of the graphite to form a composite with the graphite. |
| US09748560B2 |
Negative electrode for alkaline secondary battery, outer case for alkaline secondary battery and alkaline secondary battery
Disclosed is a negative electrode for an alkaline secondary battery, which can suppress elution of iron to improve the long-period storage property of the battery capacity even under conditions in which elution of iron in a substrate into an electrolyte solution tends to occur, and which can also suppress lowering of initial capacity and increase in internal resistance. Even under conditions in which the elution of iron in the substrate into an electrolyte solution tends to occur, including a case where there is a thin conductive protecting layer at the surface or where the conductive protecting layer has defects, by adding magnesium or a magnesium compound to the negative electrode for an alkaline secondary battery (excluding the case where magnesium is contained as a constituent element of a hydrogen storage alloy), the elution of iron can be suppressed, and thereby, the long-period storage property of the battery capacity can be improved and the lowering of the initial capacity and the increase in internal resistance can be suppressed. |
| US09748559B2 |
Positive electrode active material for non-aqueous secondary battery and method of manufacturing thereof
A positive electrode active material for non-aqueous secondary battery includes core particles containing a lithium transition metal composite oxide, and a covering layer covering, that covers a surface of the core particle. The covering layer contains niobium and carbonate ions, and the carbonate ions are present at a concentration of from 0.2 weight % to 0.4 weight %. The positive electrode active material for non-aqueous secondary battery exhibits infrared absorption peaks at a wavenumber range of from 1320 cm−1 to 1370 cm−1, and at a wavenumber range of from 1640 cm−1 to 1710 cm−1. |
| US09748558B2 |
Method for preparing electrode materials and electrode materials produced therefrom
The present invention provides a method for preparing an electrode material, comprising providing an acidic plating bath; adding titanium dioxide in the form of powder, metal salt, and reductant to said acidic plating bath to obtain a precursor; and heat treating said precursor to obtain an electrode material. When the electrode material obtained by said method is applied to batteries, the batteries have not only high capacity, but also long lifetime. |
| US09748554B2 |
Electric storage device and method for manufacturing electric storage device
An electric storage device includes a container which houses an electric generating element, and a sealing plug which seals a liquid injecting hole into which an electrolyte is injected. The liquid injecting hole is provided in a bottom surface of a recessed portion provided to be recessed on one side surface of the container. The sealing plug includes an inserting portion to be inserted into the liquid injecting hole and a fitting portion to be fitted into the recessed portion. At least either a rim portion of the fitting portion or an opening rim portion of the recessed portion is provided with a plurality of plastic deformation portions. In each of n regions (n is an integer of at least 3) into which an outer circumference of the fitting portion or an inner circumference of the recessed portion is equally divided, one or more of the plastic deformation portion(s) is/are arranged, and, in each of regions into which the outer circumference of the fitting portion or the inner circumference of the recessed portion is halved with an arbitrary plastic deformation portion out of the plastic deformation portions set as a starting point, one or more of the plastic deformation portion(s) is/are arranged. An outer circumferential side surface of the fitting portion and an inner circumferential side surface of the recessed portion are welded over an entire circumference. |
| US09748552B2 |
Battery having protection components
A battery includes a shell, a core received in the shell and having first and second electrode tabs, and first and second protection components. Each of the first and second protection components includes two insulating layers and a conducting layer disposed between two insulating layers. The conducting layer of the first protection component defines a first end electrically connected to the first electrode tab and a second end configured as a free end. The conducting layer of the second protection component defines a first end electrically connected to the second electrode tab and a second end configured as a free end. |
| US09748549B2 |
Integrated cell separator/high voltage bus bar carrier assembly
An integrated cell separator/high voltage bus bar carrier assembly for a high voltage traction battery includes a cell separator having a plurality of cell separator walls and a plurality of bus bar retention walls carried by the plurality of cell separator walls. A high voltage bus bar is carried by the plurality of bus bar retention walls of the cell separator. |
| US09748548B2 |
Pouch frame with integral circuitry for battery module
A battery cell assembly for use in a battery module including a battery cell that includes a positive electrode and a negative electrode and a rigid frame coupled to the battery cell. The rigid frame includes a first frame connector and a second frame connector. The frame is configured to facilitate electrical coupling of the positive electrode of the battery cell with the first frame connector, and to facilitate electrical coupling of the negative electrode of the battery cell with the second frame connector. The first and second frame connectors are configured to interface with frame connectors of other battery cell assemblies to facilitate physical and electrical connection of a plurality of battery cell assemblies disposed in a stacked orientation relative to each other. |
| US09748546B2 |
High porosity silica-containing microporous sheets
A flexible microporous polymer sheet having first and second opposite major surfaces comprises a polymer matrix binding a filler component that exhibits high oil absorption capacity in its initial state before the start of material processing. The polymer matrix includes a polyolefin component and has three-dimensional interconnecting and interpenetrating pore and polymer networks through which the bound filler component is distributed from the first major surface to the second major surface. The polyolefin and filler components are included in amounts that result in a microporous polymer sheet having between about 75% and about 90% porosity and containing less than about 10 wt. % polyolefin component. Preferred polyolefin and filler components include ultrahigh molecular weight polyethylene and high oil absorption precipitated silica, respectively. |
| US09748542B2 |
Composite porous film having excellent heat resistance
To provide a composite porous film in which thermal shrinkage is satisfactorily suppressed even when temperature exceeds a melting temperature of a polyolefin resin, adhesion between a microporous membrane and a heat-resistant layer is improved, and dropout of an inorganic filler is suppressed. The composite porous film is composed of the heat-resistant layer formed of the inorganic filler and a binder, and the microporous membrane formed of the polyolefin resin, and the composite porous film having a primary particle size of the inorganic filler in the range of 5 nanometers to 100 nanometers. |
| US09748540B2 |
Power supply apparatus
The present invention aims to provide a power supply apparatus capable of suppressing a short circuit that occurs between adjacent battery cells.The power supply apparatus includes: a plurality of battery cells in which positive electrodes and negative electrodes are provided alternately and inversely with each other; a plurality of bus bars arranged in a straight line so as to series-connect the plurality of battery cells; a sheet-like insulation film disposed on at least one surface side of the plurality of bus bars; and a resin frame for fixing the plurality of battery cells, wherein an insulation portion for insulating the adjacent battery cells from each other is provided on the insulation film or in the resin frame. |
| US09748539B2 |
Battery module
A battery module includes a plurality of battery cells, an end plate, and bush members. The plurality of battery cells are arranged along a direction. The end plate is adjacent to an outermost battery cell among the plurality of battery cells. The bush members are at respective sides of the end plate. In the battery module, the end plate includes a first end plate adjacent to the outermost battery cell, the first end plate including a first material, and a second end plate at an outer side of the first end plate, the second end plate including a second material. The bush members are at respective sides of the first and second end plates and between the first and second end plates. |
| US09748536B2 |
Battery pack
A battery pack includes one or more bare battery cells, a frame case, and a top case. Each of the bare battery cells has first and second electrode tabs. The frame case surrounds an outer surface of the one or more bare cells. The top case is coupled to the frame case at one end of the one or more bare cells. In the battery pack, the frame case includes a warp preventing portion parallel to the top case. |
| US09748535B2 |
Battery pack and holster for mobile devices
Embodiments of this disclosure relate to battery packs and/or holsters and, more particular, to an external battery pack and/or holster for mobile electronic devices. |
| US09748534B2 |
Electric tool and battery pack for the electric tool
When a battery pack is mounted to a battery attachment part, the battery pack is slid in a horizontal direction (a direction substantially perpendicular to an upper-lower direction) with respect to the housing, e.g., along a long longitudinal direction of a battery-side rail part, such that tool-side rail parts of the battery attachment part are introduced into engaging recess portions of the battery pack. Thereby, the elastic members are fitted and compressed in the battery-side rail parts and the tool-side rail parts, so that the elastic members press upwards the battery-side rail part (e.g., the battery pack) and press downwards the tool-side rail parts (e.g., the housing). That is, the elastic members press the battery pack and the housing such that they come close to each other. |
| US09748533B2 |
Battery module
A battery module is provided including a secondary battery unit having a plurality of secondary batteries spaced from each other, the plurality of secondary batteries each including electrode terminals and a safety vent which are arranged on one side of the secondary battery unit; a compression plate wrapping at least a portion of the secondary battery unit and compressing the secondary battery unit together; and an insulation cover covering the electrode terminals and the safety vent, the insulation cover including a duct connected to the safety vent to guide gases exhausted from the safety vent to a first location, and a vent hole member coupled to the duct at the first location. |
| US09748532B2 |
Belt with built-in batteries
A belt with built-in batteries includes: a plurality of rechargeable batteries, each having a positive terminal and a negative terminal that protrude in two opposite directions; a positive reinforcing tab that electrically connects the positive terminals of the rechargeable batteries to each other; a negative reinforcing tab that electrically connects the negative terminals of the rechargeable batteries to each other; and a sheath that seals the positive and negative terminals of the rechargeable batteries and the positive and negative reinforcing tabs. |
| US09748528B2 |
Hard shell cell housing with vapour barrier layer
A hard shell cell housing for an individual alkali metal cell includes a housing main body with an interior space that is configured to accommodate cell components of the individual alkali metal cell, and a housing cover configured to close off the interior space. The housing main body is formed at least substantially from plastic, and further includes at least one vapor barrier layer. |
| US09748525B2 |
Light-emitting device having reduced in-plane variation
A first electrode having light transmissivity is formed on a first surface of a first light transmissive substrate and. An organic functional layer includes a light-emitting layer and is located on an opposite side to the first light transmissive substrate with the first electrode interposed therebetween. A second electrode is located on an opposite side to the first electrode with the organic functional layer interposed therebetween. A second surface which is a surface of the first light transmissive substrate on an opposite side to the above-mentioned first surface is fixed to the second light transmissive substrate, which has a bending rigidity higher than that of the first light transmissive substrate. First irregularities are formed in the second surface of the first light transmissive substrate, and second irregularities are formed in a surface of the second light transmissive substrate which faces the first light transmissive substrate. |
| US09748522B2 |
Illumination system comprising beam shaping element
The invention relates to an illumination system comprising a light emitting device and a beam shaping element for generating an angular distribution of the light emitted from the illumination system. The beam shaping element is configured for recycling at least a part of the light emitted from a light emitting surface of the light emitting device via reflection back towards the light emitting surface. The illumination system further comprises a diffuser arranged substantially parallel to the light emitting surface for diffusing at least part of the recycled light. The diffuser is constituted of a translucent diffuser and/or a diffusely reflective electrode layer of the light emitting device. Limiting the angular distribution by recycling light, using the beam shaping element for recycling light via reflection, reduces glare when the illumination system is used in general lighting applications. The diffuser avoids that the recycled light is confined between the beam shaping element and the light emitting surface of the light emitting element. The recycling is preferably done via total internal reflection at the beam shaping element. The presence of the diffuser improves the efficiency of the illumination system. |
| US09748518B2 |
Thin-film packaging method and organic light-emitting device
A thin-film packaging method and an organic light-emitting device are provided. The method includes following steps: forming an OLED layer on a TFT substrate, forming a first inorganic packaging layer on the OLED layer, forming a coupling agent unit on the first inorganic packaging layer, and forming an organic packaging layer on the coupling agent unit. Wherein, the organic packaging layer includes a buffer sublayer and a resist sublayer sequentially formed. The coupling agent unit generates chemical reactions with the first inorganic packaging layer and the buffer sublayer in order to increase an adhesive strength between the first inorganic packaging layer and the organic packaging layer so that they are not easily to be separated, and have a good water and oxygen insulation property. |
| US09748517B2 |
Organic insulating material and flexible display including the same
An organic insulating material and a flexible display device are disclosed. The organic insulating material comprises an acrylic polymer having a cinnamoyl moiety. |
| US09748516B2 |
Functional film
An environmentally sensitive electronic device package including a first adhesive, at least one first side wall barrier, a first substrate, and a second substrate is provided. The first adhesive has a first surface and a second surface opposite to the first surface. The first side wall barrier is distributed in the first adhesive. The first substrate is bonded with the first surface. The first substrate has an environmentally sensitive electronic device formed thereon and the environmentally sensitive electronic device is surrounded by the first side wall barrier. The second substrate is bonded with the second surface. A manufacturing method of the environmentally sensitive electronic device package is also provided. |
| US09748515B2 |
Organic light-emitting diode display and method of manufacturing the same including a sealant with a plurality of openings and islands formed within the openings
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a first substrate and a second substrate facing each other, a display unit formed between the first and second substrates and a sealant formed between the first and second substrates and bonding the first and second substrates. The sealant includes a sealing portion surrounding and sealing the display unit, the sealing portion having a plurality of first openings separate from each other along a circumferential direction of the display unit. The sealant also includes an adhesion reinforcing portion including a plurality of islands that are respectively formed inside the first openings and separate from the sealing portion. |
| US09748512B2 |
See-through organic light emitting display device and method for manufacturing the same
A see-through organic light emitting display device including a light emitting region having a transparent anode, an organic light emitting layer, and a transparent cathode, and a see-through region having a transparent auxiliary electrode, which is configured to transmit external light. The transparent auxiliary electrode can be made from the same material as the transparent anode and separated from the transparent anode, and the transparent cathode extends into the see-through region so as to be electrically connected with the transparent auxiliary electrode. |
| US09748507B2 |
Single electron transistor having nanoparticles of uniform pattern arrangement
A transistor and a fabrication method thereof. A transistor includes a channel region including linkers, formed on a substrate, and metallic nanoparticles grown from metal ions bonded to the linkers, a source region disposed at one end of the channel region, a drain region disposed at the other end of the channel region opposite of the source region, and a gate coupled to the channel region and serving to control migration of charges in the channel region. The metallic nanoparticles have a substantially uniform pattern arrangement in the channel region. |
| US09748503B2 |
Organic electroluminescent materials and devices
Bis(tridentate) osmium(II) complexes containing phosphite groups useful as phosphorescent emitters are disclosed. The disclosed osmium(II) complexes have higher oxidation potential then previously known osmium(II) complexes. An organic light emitting device having an organic layer that includes the disclosed osmium(II) complex is also disclosed. |
| US09748499B2 |
Organometallic compounds and organic light-emitting devices comprising the same
An organometallic compound represented by Formula 1 below is disclosed. An organic light-emitting device including at least one organometallic compound represented by Formula 1 is also disclosed. |
| US09748496B2 |
Nitrogenated heterocyclic derivative, electron-transporting material for organic electroluminescent elements, and organic electroluminescent element using same
A specific nitrogen-containing heterocyclic compound having a urea structure, an electron transporting material containing the nitrogen-containing heterocyclic compound, and an organic electroluminescence device including a light emitting layer and an electron transporting layer between a cathode and an anode in which the electron transporting layer includes the electron transporting material or the nitrogen-containing heterocyclic derivative. An organic EL device exhibiting high emission efficiency even at low voltage and a material for organic EL devices are described. |
| US09748495B2 |
Carbazole derivative, light-emitting element material, light-emitting element, light-emitting device, electronic device, and lighting device
A carbazole derivative represented by the general formula (1) is provided. In the formula, Ar1 represents a substituted or unsubstituted aryl group having 6 to 10 carbon atoms which form a ring; α and β independently represent a substituted or unsubstituted arylene group having 6 to 12 carbon atoms which form a ring; R1 represents an alkyl group having 1 to 4 carbon atoms or a substituted or unsubstituted aryl group having 6 to 10 carbon atoms which form a ring; and R11 to R17 and R21 to R28 independently represent hydrogen, an alkyl group having 1 to 4 carbon atoms, or a substituted or unsubstituted aryl group having 6 to 10 carbon atoms which form a ring. |
| US09748493B2 |
Aromatic amine-terphenyl compounds and use thereof in organic semiconducting components
The present invention relates to aromatic amine-terphenyl compounds and use thereof in organic semiconducting components. The organic semiconducting components may contain at least one layer that includes one or more of the aromatic amine-terphenyl compounds, and the layer may be a charge transporting layer or an emitter layer. The organic semiconducting components may be organic light-emitting diodes or photovoltaic components. |
| US09748492B2 |
Organic electroluminescent device
Provided are an amine compound having a benzofluorene structure and further having a dibenzofuran structure and/or a dibenzothiophene structure, and an organic electroluminescent device containing a cathode, an anode and an organic thin film layer intervening between the cathode and anode, the organic thin film layer comprising one layer or plural layers comprising at least an emitting layer, at least one layer of the organic thin film layer comprising the aforementioned amine compound solely or as a component of a mixture. |
| US09748489B2 |
Copolymer and organic solar cell comprising same
The present specification provides a copolymer and an organic solar cell including the same. |
| US09748488B2 |
Organic electronic material, ink composition, and organic electronic element
Provided is an organic electronic material which is excellent in storage stability in the case as an ink composition, and able to prepare, at a high yield, an organic electronic element capable of reducing the driving voltage and of being driven stably for a long period of time, and an ink composition including the organic electronic material. The organic electronic material is characterized in that it contains at least an ionic compound represented by the following general formula (1), and a compound including a charge transporting unit, and the ink composition including the material.[In the general formula (1), Ra to Rc each independently represent a hydrogen atom (H), an alkyl group, or a benzyl group, and N is not bonded to an aryl group. A represents an anion.] |
| US09748487B2 |
Polymers based on naphthodiones
The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (I), and compounds of formula (III), wherein Y, Y15, Y16 and Y17 are independently of each other a group of formula and their use as IR absorber, organic semiconductor in organic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers and compounds according to the invention can have excellent solubility in organic solvents and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers and compounds according to the invention are used in organic field effect transistors, organic photovoltaics and photodiodes. |
| US09748486B2 |
Organic light emitting device with increased light out coupling
The invention relates to an organic light-emitting device (OLED) comprising at least: a first electrode; a second electrode; an organic light emissive layer arranged between said first electrode and said second electrode; and an organic charge transport layer arranged between said first electrode and said emissive layer, wherein i) the charge transport layer is patterned or provided with a periodic surface structure on a surface of the charge transport layer facing the emissive layer, and/or ii) an alignment layer which allows for charge transport to the emissive layer is provided between said charge transport layer and said emissive layer, which alignment layer promotes alignment of the optical dipoles of molecules of said light emissive layer towards a common preferred direction of the molecular axes. The use of the patterned or structured charge transport layer and/or the alignment layer provides improved light out coupling from the OLED layer stack, i.e. increased external quantum efficiency. |
| US09748484B2 |
Apparatus for fabricating OLED display device and method of fabricating OLED display using the apparatus
An apparatus for fabricating an organic light-emitting diode (OLED) display device includes a chamber, a stage in the chamber to support an array substrate, a cover plate in the chamber above the stage, and a solvent absorption plate on a first surface of the cover, the solvent absorption plate including a solvent, and the solvent absorption plate facing the stage to have the array substrate face the solvent absorption plate. |
| US09748479B2 |
Memory cells including vertically oriented adjustable resistance structures
A memory cell is provided that includes a vertically-oriented adjustable resistance material layer, a control terminal disposed adjacent the vertically-oriented adjustable resistance material layer and coupled to a word line, and a reversible resistance-switching element disposed on the vertically-oriented adjustable resistance material layer. The control terminal is configured to adjust a resistance of the vertically-oriented adjustable resistance material layer. |
| US09748477B2 |
Method of forming a conductive filament in a living resistive memory device including a pre-forming step to form a localised path of oxygen vacancies from an interface layer
A resistive random access memory device includes a first electrode; a solid metal oxide electrolyte; and a second electrode, the first and second electrodes being respectively arranged on either side of the solid metal oxide electrolyte, the second electrode being capable of supplying mobile ions circulating in the solid metal oxide electrolyte to the first electrode to form a conductive filament between the first and second electrodes when a potential difference is applied between the first and second electrodes. The device further includes an interface layer including a metal oxide, the interface layer extending at least partially onto the first electrode, the solid metal oxide electrolyte extending at least partially onto the interface layer. |
| US09748475B2 |
Memory devices including phase change material elements
Memory devices having a plurality of memory cells, with each memory cell including a phase change material having a laterally constricted portion thereof. The laterally constricted portions of adjacent memory cells are vertically offset and positioned on opposite sides of the memory device. Also disclosed are memory devices having a plurality of memory cells, with each memory cell including first and second electrodes having different widths. Adjacent memory cells have the first and second electrodes offset on vertically opposing sides of the memory device. Methods of forming the memory devices are also disclosed. |
| US09748474B2 |
Nano-scale electrical contacts, memory devices including nano-scale electrical contacts, and related structures and devices
Electrical contacts may be formed by forming dielectric liners along sidewalls of a dielectric structure, forming sacrificial liners over and transverse to the dielectric liners along sidewalls of a sacrificial structure, selectively removing portions of the dielectric liners at intersections of the dielectric liners and sacrificial liners to form pores, and at least partially filling the pores with a conductive material. Nano-scale pores may be formed by similar methods. Bottom electrodes may be formed and electrical contacts may be structurally and electrically coupled to the bottom electrodes to form memory devices. Nano-scale electrical contacts may have a rectangular cross-section of a first width and a second width, each width less than about 20 nm. Memory devices may include bottom electrodes, electrical contacts having a cross-sectional area less than about 150 nm2 over and electrically coupled to the bottom electrodes, and a cell material over the electrical contacts. |
| US09748473B2 |
Quantum well device with lateral electrodes
An apparatus includes a substrate having a planar top surface, a sequence of crystalline semiconductor layers located on the planar surface, and first and second sets of electrodes located over the sequence. The sequence of crystalline semiconductor layers has a 2D quantum well therein. The first set of electrodes border opposite sides of a lateral region of the sequence and are controllable to vary a width of a non-depleted portion of the quantum well along the top surface. The second set of electrodes border first and second channels between the lateral region and first and second adjacent lateral areas of the sequence and are controllable to vary widths of non-depleted segments of the quantum well in the channels. The electrodes are located such that straight lines connecting the first and second lateral areas via the channels either pass between one of the electrodes and the substrate or are misaligned to an effective [1 1 0] lattice direction of the sequence. |
| US09748464B2 |
Athletic activity monitoring device with energy capture
Aspects relate to an energy harvesting device adapted for use by an athlete while exercising. The device may utilize a mass of phase-change material to store heat energy, the stored heat energy subsequently converted into electrical energy by one or more thermoelectric generator modules. The energy harvesting device may be integrated into an item of clothing, and such that the mass of phase change material may store heat energy as the item of clothing is laundered. |
| US09748462B2 |
Floating heat sink support with conductive sheets and LED package assembly for LED flip chip package
A floating heat sink support with copper sheets for a LED flip chip package may include least two copper sheets and a flexible polymer for fixing the copper sheets, where the copper sheets separated from each other, and where each of the copper sheets is electrically connected with a positive or negative pole of a LED flip chip. Further, a LED package assembly may comprise the floating heat sink support as mentioned above and one or more LED chips welded in a flip chip manner on the floating heat sink support. A number of copper sheets in the floating heat sink support are heated separately and expand separately to avoid the breakage of a chip substrate resulting from the thermal expansion of a whole bulk of copper sheet, thereby improving the reliability of the LED package structure and prolonging the service life of a LED light source. |
| US09748461B2 |
Light emitting diodes with enhanced thermal sinking and associated methods of operation
Solid state lighting devices and associated methods of thermal sinking are described below. In one embodiment, a light emitting diode (LED) device includes a heat sink, an LED die thermally coupled to the heat sink, and a phosphor spaced apart from the LED die. The LED device also includes a heat conduction path in direct contact with both the phosphor and the heat sink. The heat conduction path is configured to conduct heat from the phosphor to the heat sink. |
| US09748460B2 |
LED back end assembly and method of manufacturing
An LED device and method of manufacture including separately coupling a thin flexible interposer and an LED die to a heat sink structure and then electrically coupling the interposer and the LED die together with a wirebond. A specifically shaped perimeter of an aperture within the interposer negates the need for a cavity or alignment markings within the heat sink structure by limiting the orientation in which the die fits within the aperture. Alternatively, an LED device and method of manufacture include coupling a rigid circuit board to an LED die such that electrical contacts of the die are electrically coupled with electrical input/output terminals of the circuit board. This die/board unit is then able to be coupled to a heat sink structure to form a portion of the device. |
| US09748458B2 |
Light emitting diode module and method of manufacturing the same
A light emitting diode module includes a substrate, a first soldering section, a second soldering section, a block and a light emitting diode die. The substrate has a top surface and includes a circuit structure. The block is formed on the top surface. The soldering section and the second solder section are formed on the top surface of the substrate and electrically connected with the circuit structure. The block is positioned between the first soldering section and the second solder section. A height of the block is larger than thicknesses of the first soldering section and the second soldering section. The light emitting diode die includes a first electrode and a second electrode being respectively electrically connected to the first soldering section and the second soldering section. The block is positioned between the first soldering section and the second soldering section. |
| US09748452B2 |
Light-emitting element package
One embodiment comprises: a body having a cavity which includes a bottom and sides; a light-emitting element arranged within the cavity of the body; a molding part arranged within the cavity so as to seal the light-emitting element; and a lens which includes a light incident surface and a light emitting surface and is arranged on the molding part, wherein the diameter of the light incident surface of the lens is smaller than a maximum diameter of the cavity, and the height of the lens is lower than the diameter of the light incident surface of the lens. |
| US09748451B2 |
Radiation-emitting component, transparent material and filler particles, and method of producing same
A radiation-emitting component includes a radiation source; a transparent material disposed in the beam path of the component and including a polymer material and filler particles, wherein the filler particles include an inorganic filler material and a phosphonic acid derivative or phosphoric acid derivative attached to a surface thereof and through which the filler particles are crosslinked with the polymer material. |
| US09748448B2 |
LED module
An LED module A1 is provided with: a first lead 1 including a die-bonding portion 12 with a mount surface 12a, and a front-end sunk portion 14; a second lead 2 including a wire-bonding portion 22 and spaced apart from the first lead 1; an LED chip 3 mounted on the mount surface 12a and provided with a first electrode terminal 31 and a second electrode terminal 32; a wire 61 connecting the second electrode terminal 32 and the wire-bonding portion 22; and a support member 4 including a protective portion 42 and supporting the leads 1 and 2. The protective portion covers the front-end sunk portion 14 with the mount surface 12a exposed, and includes an inclined portion 42a that becomes thinner as proceeding from the die-bonding portion 12 toward the lead 2. |
| US09748446B2 |
Semiconductor light emitting device
Disclosed is a semiconductor light emitting device, including: a plurality of semiconductor layers grown sequentially on a growth substrate; a first electrode part, which is in electrical communication with the first semiconductor layer and supplies one of electrons or holes thereto; a second electrode part, which is in electrical communication with the second semiconductor layer and supplies the other one of electrons or holes thereto; and a non-conductive reflective film, which is formed on the plurality of semiconductor layers for reflecting the light generated in the active layer towards the growth substrate and has an opening formed therein, wherein at least one of the first and second electrode parts includes a lower electrode exposed at least partly through the opening; an upper electrode provided on the non-conductive reflective film; and an electrical connection, which comes into contact with the lower electrode by passing through the opening and is in electrical communication with the upper electrode. |
| US09748442B2 |
Light emitting diodes and associated methods of manufacturing
Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material. |
| US09748441B2 |
Dry etching method of manufacturing semiconductor light emitting device substrate
A method of manufacturing a semiconductor light emitting device, including arranging a plurality of particles in a monolayer on a substrate, dry etching the plurality of particles arranged to provide a void between the particles in a condition IN which the particles are etched while the substrate is not substantially etched; and dry etching the substrate using the plurality of particles after the particle etching step as an etching mask, thereby forming an uneven structure on one surface of the substrate. |
| US09748434B1 |
Systems, method and apparatus for curing conductive paste
One embodiment can provide a system for curing conductive paste applied on photovoltaic structures. The system can include a wafer carrier for carrying a plurality of photovoltaic structures and a heater. The wafer carrier can include a surface element that is in direct contact with the photovoltaic structures and is substantially thermally insulating. The heater can be positioned above the wafer carrier. The heater can include a heated radiation surface that does not directly contact the photovoltaic structures. |
| US09748432B2 |
Automated assembly and mounting of solar cells on space panels
The present disclosure provides methods of fabricating a multijunction solar cell panel in which one or more of the steps are performed using an automated process. In some embodiments, the automated process uses machine vision. |
| US09748428B2 |
Light detection device including a semiconductor light detection element with a through-hole electrode connection, a mounting substrate and a light-transmissive substrate
A semiconductor light detection element includes a plurality of avalanche photodiodes operating in Geiger mode and formed in a semiconductor substrate, quenching resistors connected in series to the respective avalanche photodiodes and arranged on a first principal surface side of the semiconductor substrate, and a plurality of through-hole electrodes electrically connected to the quenching resistors and formed so as to penetrate the semiconductor substrate from the first principal surface side to a second principal surface side. A mounting substrate includes a plurality of electrodes arranged corresponding to the respective through-hole electrodes on a third principal surface side. The through-hole electrodes and the electrodes are electrically connected through bump electrodes, and a side surface of the semiconductor substrate and a side surface of a glass substrate are flush with each other. |
| US09748425B2 |
Photoelectric conversion element and photovoltaic cell
A photoelectric conversion element includes a PN junction formed from an N-type oxide layer and a P-type oxide layer. The P-type oxide layer is formed from an oxide having a perovskite structure. |
| US09748417B2 |
Composition for forming solar cell electrode and electrode produced from same
A composition for solar cell electrodes and electrodes fabricated using the same. The composition includes a silver (Ag) powder; a first glass frit containing PbO and a second glass frit containing V2O5 and TeO2; and an organic vehicle. The composition includes two types of glass frits on PbO and V2O5-TeO2, respectively, thereby minimizing contact resistance and adverse influence on a p-n junction of silicon solar cells. |
| US09748416B2 |
Optical detector apparatus, method, and applications
An optical device including a shaped electrode on a substrate thereof utilizes total internal reflection to provide improved transmission of electromagnetic radiation (‘light’) to the substrate compared to standard electrode designs that involve flat electrode surfaces. Redirection of incident light by a tilted or otherwise shaped contact or material added on the contact provides otherwise reflected light to an open surface region of the substrate. Optional plasmon mediated focusing of incident p-polarized light may be realized. |
| US09748415B2 |
Fast process flow, on-wafer interconnection and singulation for MEPV
A method including providing a substrate comprising a device layer on which a plurality of device cells are defined; depositing a first dielectric layer on the device layer and metal interconnect such that the deposited interconnect is electrically connected to at least two of the device cells; depositing a second dielectric layer over the interconnect; and exposing at least one contact point on the interconnect through the second dielectric layer. An apparatus including a substrate having defined thereon a device layer including a plurality of device cells; a first dielectric layer disposed directly on the device layer; a plurality of metal interconnects, each of which is electrically connected to at least two of the device cells; and a second dielectric layer disposed over the first dielectric layer and over the interconnects, wherein the second dielectric layer is patterned in a positive or negative planar spring pattern. |
| US09748414B2 |
Self-activated front surface bias for a solar cell
A self-activated front surface bias for photovoltaic solar cell assembly is provided. The solar cell assembly comprises a front surface electrical bias activated by electrical energy generated by the solar cell assembly. The front surface bias improves generation efficiency for said solar cell assembly. |
| US09748412B2 |
Highly responsive III-V photodetectors using ZnO:Al as N-type emitter
A photodiode includes a p-type ohmic contact and a p-type substrate in contact with the p-type ohmic contact. An intrinsic layer is formed over the substrate and including a III-V material. A transparent II-VI n-type layer is formed on the intrinsic layer and functions as an emitter and an n-type ohmic contact. |
| US09748402B2 |
Semiconductor element and organic light emitting display device having a semiconductor element
A semiconductor element includes a substrate, a gate electrode, an active layer, a contact layer, a first electrode, and a second electrode. The gate electrode is disposed on the substrate. The gate insulation layer is disposed on the gate electrode. The active layer is disposed on the gate insulation layer, and includes a first end portion and a second end portion that is opposite the first end portion. The contact layer overlaps the second end portion of the active layer. The first electrode is in contact with the first end portion. The second electrode is spaced apart from the first electrode, and is in contact with the contact layer. |
| US09748401B2 |
Transistor and semiconductor device
Manufactured is a transistor including an oxide semiconductor layer, a source electrode layer and a drain electrode layer overlapping with part of the oxide semiconductor layer, a gate insulating layer overlapping with the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and a gate electrode overlapping with part of the oxide semiconductor layer with the gate insulating layer provided therebetween, wherein, after the oxide semiconductor layer which is to be a channel formation region is irradiated with light and the light irradiation is stopped, a relaxation time of carriers in photoresponse characteristics of the oxide semiconductor layer has at least two kinds of modes: τ1 and τ2, τ1<τ2 is satisfied, and τ2 is 300 seconds or less. In addition, a semiconductor device including the transistor is manufactured. |
| US09748400B2 |
Semiconductor device
A semiconductor device in which a transistor using an oxide semiconductor containing In, Zn, or the like for a channel region can be driven like a p-channel transistor is provided. The semiconductor device includes a transistor and an inverter, wherein an output of the inverter is input to a gate of the transistor, a channel region of the transistor includes an oxide semiconductor film containing In, Zn, or Sn, and each channel region of transistors in the inverter contains silicon. When a high voltage is input to the inverter, a low voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned off. When a low is input to the inverter, a high voltage is output from the inverter and is input to the gate of the transistor, so that the transistor is turned on. |
| US09748394B2 |
FinFET having a multi-portioned gate stack
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure. The gate stack includes a first portion and a second portion adjacent to the fin structure, and the first portion is wider than the second portion. |
| US09748390B2 |
Semiconductor device and method of forming the same
A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film. |
| US09748385B1 |
Method for forming vertical Schottky contact FET
A semiconductor structure containing a vertical Schottky contact transistor is provided in which the contact resistance as well as the junction resistance is improved. The vertical Schottky contact transistor includes a bottom Schottky contact source/drain structure and a top Schottky contact source/drain structure located at opposing ends of a semiconductor channel region. The bottom Schottky contact source/drain structure includes a base portion and a vertically extending portion. |
| US09748383B2 |
Transistor
A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent. |
| US09748382B1 |
Self aligned top extension formation for vertical transistors
A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region. |
| US09748379B2 |
Double exponential mechanism controlled transistor
The present disclosure relates to a tunnel FET device with a steep sub-threshold slope, and a corresponding method of formation. In some embodiments, the tunnel FET device has a dielectric layer arranged over a substrate. A conductive gate electrode and a conductive drain electrode are arranged over the dielectric layer. A conductive source electrode contacts the substrate at a first position located along a first side of the conductive gate electrode. The conductive drain electrode is arranged at a second position located along the first side of the conductive gate electrode. By arranging the conductive gate electrode over the dielectric layer at a position laterally offset from the conductive drain electrode, the conductive gate electrode is able to generate an electric field that controls tunneling of minority carriers, which can change the effective barrier height of the tunnel barrier, and thereby improving a sub-threshold slope of the tunnel FET device. |
| US09748376B2 |
Power FET with integrated sensors and method of manufacturing
A semiconductor device and a method of making are disclosed. The device includes a substrate, a power field effect transistor (FET), and integrated sensors including a current sensor, a high current fault sensor, and a temperature sensor. The structure of the power FET includes a drain contact region of a first conductivity type disposed in the substrate, a drain drift region of the first conductivity type disposed over the drain contact region, doped polysilicon trenches disposed in the drain drift region, a body region of a second conductivity type, opposite from the first conductivity type, disposed between the doped polysilicon trenches, a source region disposed on a lateral side of the doped polysilicon trenches and in contact with the body region, and a source contact trench that makes contact with the source region and with the doped polysilicon trenches. |
| US09748372B2 |
Semiconductor structure and method of forming the same
A method of forming a semiconductor structure includes growing a second III-V compound layer over a first III-V compound layer, wherein the second III-V compound layer has a different band gap from the first III-V compound layer. The method further includes forming a source feature and a drain feature over the second III-V compound layer. The method further includes forming a gate dielectric layer over the second III-V compound layer, the source feature and the drain feature. The method further includes implanting at least one fluorine-containing compound into a portion of the gate dielectric layer. The method further includes forming a gate electrode over the portion of the gate dielectric layer. |
| US09748368B2 |
Tunnel field-effect transistor (TFET) with supersteep sub-threshold swing
Technologies are generally described herein generally relate to tunnel field-effect transistor (TFETs) structures with a gate-on-germanium source (GoGeS) on bulk silicon substrate for sub 0.5V (VDD) operations. In some examples, the GoGeS structure may include an increase in tunneling area and, thereby, a corresponding increases in the ON-state current ION. In order to achieve supersteep sub-threshold swing, both the lateral tunneling due to gate electric-field and the non-uniform tunneling at the gate-edge due to field-induced barrier lowering (FIBL) may be suppressed through selection of component dimension in the device structure. Example devices may be fabricated using CMOS fabrication technologies with the addition of selective etching in the process flow. |
| US09748366B2 |
Etching oxide-nitride stacks using C4F6H2
An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions. |
| US09748365B2 |
SiGe and Si FinFET structures and methods for making the same
FinFET structures and methods for making the same. A method includes: creating a plurality of Silicon fins on a first region of a substrate, creating a plurality of Silicon-Germanium fins on a second region of the substrate, adjusting a Silicon fin pitch of the plurality of Silicon fins to a predetermined value, and adjusting a Silicon-Germanium fin pitch of the plurality of Silicon-Germanium fins to a predetermined value, where the creating steps are performed in a manner that Silicon material and Silicon-Germanium material used in making the plurality of fins will be on the semiconductor structure at a same time. |
| US09748364B2 |
Method for fabricating three dimensional device
A method for forming a three dimensional device. The method may include directing ions to an end surface of an extension region of a fin structure, the fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein the ions have trajectories extending in a plane perpendicular to the substrate plane and parallel to the fin axis, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the end surface is not covered by the gate structure. |
| US09748362B2 |
High-voltage normally-off field effect transistor with channel having multiple adjacent sections
A device having a channel with multiple voltage thresholds is provided. The channel can include a first section located adjacent to a source electrode, which is a normally-off channel and a second section located between the first section and a drain electrode, which is a normally-on channel. The device can include a charge-controlling electrode connected to the source electrode, which extends from the source electrode over at least a portion of the second section of the channel. During operation of the device, a potential difference between the charge-controlling electrode and the channel can control the on/off state of the normally-on section of the channel. |
| US09748358B2 |
Gap fill of metal stack in replacement gate process
A method for fabricating a semiconductor device comprises forming a replacement gate structure on a semiconductor layer of a substrate. The replacement gate structure at least including a polysilicon layer. After forming the replacement gate structure, a gate spacer is formed on the replacement gate structure. Atoms are implanted in an upper portion of the polysilicon layer. The implanting expands the upper portion of the polysilicon layer and a corresponding upper portion of the gate spacer in at least a lateral direction beyond a lower portion of the polysilicon layer and a lower portion of the spacer, respectively. After the atoms have been implanted, the polysilicon layer is removed to form a gate cavity. A metal gate stack is formed within the gate cavity. The metal gate stack includes an upper portion having a width that is greater than a width of a lower portion of the metal gate stack. |
| US09748355B2 |
Method for manufacturing oxide semiconductor transistor with low-nitrogen, low-defect insulating film
The amount of nitrogen that is transferred to an oxide semiconductor film of a transistor including the oxide semiconductor film is reduced. In addition, in a semiconductor device which includes a transistor including an oxide semiconductor film, change in electrical characteristics is suppressed and reliability is improved. After a nitrogen-containing oxide insulating film is formed over a transistor including an oxide semiconductor film where a channel region is formed, nitrogen is released from the nitrogen-containing oxide insulating film by heat treatment. Note that the nitrogen concentration which is obtained by secondary ion mass spectrometry (SIMS) is greater than or equal to the lower limit of detection by SIMS and less than 3×1020 atoms/cm3. |
| US09748353B2 |
Method of making a gallium nitride device
A method of making a GaN device includes: forming a GaN substrate; forming a plurality of spaced-apart first metal contacts directly on the GaN substrate; forming a layer of insulating GaN on the exposed portions of the upper surface; forming a stressor layer on the contacts and the layer of insulating GaN; forming a handle substrate on the first surface of the stressor layer; spalling the GaN substrate that is located beneath the stressor layer to separate a layer of GaN and removing the handle substrate; bonding the stressor layer to a thermally conductive substrate; forming a plurality of vertical channels through the GaN to define a plurality of device structures; removing the exposed portions of the layer of insulating GaN to electrically isolate the device structures; forming an ohmic contact layer on the second surface; and forming second metal contacts on the ohmic contact layer. |
| US09748351B2 |
Process for integrated circuit fabrication including a uniform depth tungsten recess technique
Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode. |
| US09748341B2 |
Metal-oxide-semiconductor (MOS) devices with increased channel periphery
A semiconductor device includes a drift layer disposed on a substrate. The drift layer has a non-planar surface having a plurality of repeating features oriented parallel to a length of a channel of the semiconductor device. Further, each the repeating features have a dopant concentration higher than a remainder of the drift layer. |
| US09748337B2 |
Semiconductor memory device
Three directions intersecting each other are referred to as first to third directions. A semiconductor memory device according to embodiments includes a semiconductor substrate having a top surface spread in the first and second directions, and a plurality of conductive layers laminated at predetermined intervals in the third direction on the semiconductor substrate. The semiconductor memory device further includes a columnar semiconductor layer having an interface that is in contact with the semiconductor substrate on a side surface. The columnar semiconductor layer is opposed to the plurality of conductive layers. The columnar semiconductor layer has the third direction as a lengthwise direction. The interface exists in a position deeper than the top surface of the semiconductor substrate in the third direction. |
| US09748334B1 |
Fabrication of nanomaterial T-gate transistors with charge transfer doping layer
A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric. |
| US09748331B2 |
Method for growing III-V epitaxial layers
Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device. |
| US09748330B2 |
Semiconductor device having self-isolating bulk substrate and method therefor
In one embodiment, a semiconductor device comprises a bulk semiconductor substrate that includes a first conductivity type floating buried doped region bounded above by a second conductivity type doped region and bounded below by another second conductivity semiconductor region. Dielectric isolation regions extend through the second conductivity doped region and the first conductivity floating buried doped region into the semiconductor region. Functional devices are disposed within the second conductivity type doped region. The first conductivity type floating buried doped region is configured as a self-biased region that laterally extends between adjacent dielectric isolation regions. |
| US09748326B2 |
Structure of integrated inductor
This invention discloses a structure of an integrated inductor, comprising: an outer metal segment which comprises a first metal sub-segment and a second metal sub-segment; an inner metal segment which is arranged inside an area surrounded by the outer metal segment and comprises a third metal sub-segment and a fourth metal sub-segment; and at least a connecting structure for connecting the outer metal segment and the inner metal segment. The first metal sub-segment corresponds to the third metal sub-segment, and the first metal sub-segment and the third metal sub-segment belong to different metal layers in a semiconductor structure. The second metal sub-segment corresponds to the fourth metal sub-segment, and the second metal sub-segment and the fourth metal sub-segment belong to different metal layers in a semiconductor structure. |
| US09748319B2 |
Thin film transistor array substrate and method of fabricating the same
Disclosed is a display device that may include a thin film transistor array substrate that includes a plurality of first sub-pixels and a plurality of second sub-pixels, wherein one of the plurality of first sub-pixels includes a first emission region and a first non-emission region, and one of the plurality of second sub-pixels includes a second emission region and a second non-emission region; a first bank pattern in the first and second non-emission regions, the first bank pattern including a hydrophilic material; and a second bank pattern on an upper surface of the first bank pattern, the second bank pattern includes a hydrophobic material. |
| US09748318B2 |
Auxiliary lines reducing resistance in a cathode of an organic light emitting display device
An organic light emitting diode (OLED) display device is described that includes a shared cathode between OLED pixels as well as auxiliary lines that are formed between rows and/or columns of the OLED pixels. As the cathode is shared between many if not all of the pixels of display device, resistance within the cathode can affect the brightness of those pixels that are further from the cathode's voltage source. The auxiliary lines serve to counteract the voltage drop caused by this resistance. The auxiliary lines are electrically connected to the cathode in close proximity to individual pixels of the display. |
| US09748316B2 |
Organic electroluminescent panel
The present invention provides an organic electroluminescent panel capable of increasing the luminous efficacy and decreasing the driving voltage of a top emission (TE) organic EL element. The organic electroluminescent panel of the present invention includes: a substrate; and an organic electroluminescent element provided on the substrate. The organic electroluminescent element is a top emission element that includes, in the order from the substrate side: an anode; a light-emitting layer; an electron transport layer; a first metal layer; a p-type oxide layer; and a transparent cathode. The top emission element is configured to emit light from the transparent cathode side. The light-emitting layer and the electron transport layer are each formed from an organic material. At least one of a mixture layer of a p-type oxide and a hole transport material and a second metal layer is provided between the electron transport layer and the transparent cathode. |
| US09748310B2 |
Structure and method to reduce shorting in STT-MRAM device
A method of making a magnetic random access memory (MRAM) device includes depositing a spacer material on an electrode; forming a magnetic tunnel junction (MTJ) on the spacer material that includes a reference layer in contact with the spacer material, a free layer, and a tunnel barrier layer; patterning a hard mask on the free layer; etching the MTJ and the spacer material to transfer a pattern of the hard mask into the MTJ and the spacer material; forming an insulating layer along a sidewall of the hard mask, the MTJ, and the spacer material; disposing an interlayer dielectric (ILD) on and around the hard mask, MTJ, and spacer material; etching through the ILD to form a trench that extends to a surface and sidewall of the hard mask and a sidewall of a portion of the MTJ; and disposing a metal in the trench to form a contact electrode. |
| US09748306B2 |
Radiation detectors, and methods of manufacture of radiation detectors
Radiation detectors are disclosed. The radiation detectors comprise a substrate and at least one radiation sensitive region on the substrate, the at least one radiation sensitive region comprising an array of elongate nanostructures projecting from the substrate. Methods of manufacture of such radiation detectors are also disclosed. |
| US09748303B2 |
Solid-state image pick-up apparatus, image pick-up system, and method of driving solid-state image pick-up apparatus
A solid-state image pick-up apparatus of an example includes a photoelectric conversion portion, a transfer transistor configured to transfer a charge in the photoelectric conversion portion, and a signal output circuit configured to supply selectively a first voltage to turn on the transfer transistor and a second voltage to turn off the transfer transistor to the transfer transistor. The signal output circuit is configured to supply the second voltage having a voltage value selected from two or more different voltage values based on an output signal from a pixel. |
| US09748296B2 |
Solid-state imaging device, method for producing solid-state imaging device and electronic apparatus
A solid-state imaging device, method for producing solid-state imaging device and electronic apparatus are provided. The solid-state imaging device includes a substrate, with a plurality of pixels formed in the substrate. In addition, a plurality of groups are formed in the substrate, and in particular in pixel isolation regions between adjacent pixels. The grooves extend from a first surface of the substrate towards a second surface of the substrate. An embedded film extends into the grooves. At least some of the grooves include a first stage near the first surface of the substrate and a second stage near the second surface of the substrate that are defined by walls of the grooves, wherein the first stage is wider than the second stage, and wherein a step is present between the first and second stages. In addition, the device includes a light shielding film adjacent the first surface of the substrate that overlies the grooves. A portion of the light shielding film is embedded in the embedded film that extends into the grooves. |
| US09748291B2 |
Imaging device having a third circuit with a region overlapping with a fourth circuit
An imaging device which offers an image with high quality and is suitable for high-speed operation is provided. The imaging device includes a first region to an n-th region (n is a natural number of 2 or more and 16 or less) each including a first circuit, a second circuit, a third circuit, and a fourth circuit. The first to third circuits each include a transistor in which silicon is used in an active layer or an active region. The fourth circuit includes a photoelectric conversion element and a transistor in which an oxide semiconductor is used in an active layer. The first circuit includes a region overlapping with the fourth circuit. The third circuit includes a region overlapping with the fourth circuit. |
| US09748289B2 |
Semiconductor device, its manufacturing method and electronic apparatus thereof
The present invention proposes a semiconductor device, its manufacturing method and to an electronic apparatus thereof equipped with the semiconductor device where it becomes possible to make a CMOS type solid-state imaging device, an imager area formed with a MOS transistor of an LDD structure without having a metal silicide layer of a refractory metal, an area of DRAM cells and the like into a single semiconductor chip. According to the present invention, a semiconductor device is constituted such that an insulating film having a plurality of layers is used, sidewalls at the gate electrodes are formed by etchingback the insulating film of the plurality of layers or a single layer film in the region where metal silicide layers are formed and in the region where the metal silicide layers are not formed, sidewalls composed of an upper layer insulating film is formed on a lower layer insulating film whose surface is coated or the insulating film of the plurality of layers remain unchanged. |
| US09748286B2 |
Thin film transistor substrate having metal oxide semiconductor and manufacturing the same
A method for manufacturing a thin film transistor substrate, the method can include a first mask process for forming a gate electrode on a substrate; a step for forming a gate insulating layer covering the gate electrode; a second mask process for forming a source electrode overlapping with one side of the gate electrode, and a drain electrode overlapping with other side of the gate electrode and being apart from the source electrode, on the gate insulating layer; and a third mask process for forming an oxide semiconductor layer extending from the source electrode to the drain electrode, and an etch stopper having the same shape and size with the oxide semiconductor layer on the oxide semiconductor layer. |
| US09748282B2 |
Thin film transistor array substrate having a gate electrode comprising two conductive layers
Provided is a thin film transistor array substrate having at least one thin film transistor. The thin film transistor includes a semiconductor layer having a channel area with a first doping concentration on a substrate, a source-drain area disposed at opposite sides of the channel area and with a second doping concentration greater than the first doping concentration, and a substantially undoped area extending from the source-drain area. The substrate has a gate insulating layer on the semiconductor layer and a gate electrode disposed on the gate insulating layer and overlapping the channel area in at least some portions. The substrate has a source electrode and a drain electrode, each insulated from the gate electrode and electrically connected to the source-drain area. The gate electrode includes a first gate electrode layer and a second gate electrode layer, wherein the second gate electrode layer is thicker than the first gate electrode layer. |
| US09748279B2 |
Display device
To provide a display device with excellent display quality, in a display device including a signal line, a scan line, a transistor, a pixel electrode, and a common electrode in a pixel, the common electrode is included in which an extending direction of a region overlapping with the signal line differs from an extending direction of a region overlapping with the pixel electrode in a planar shape and the extending directions intersect with each other between the signal line and the pixel electrode. Thus, a change in transmittance of the pixel can be suppressed; accordingly, flickers can be reduced. |
| US09748277B2 |
Array substrate, manufacturing method thereof, and display device
The present invention provides an array substrate, a manufacturing method thereof and a display device, relates to the field of display technology. The array substrate comprises: a substrate; a gate metal layer comprising gate lines; a source and drain metal layer comprising data lines, the gate lines and the data lines intersecting with each other to define a plurality of sub-pixel areas; a pixel electrode layer provided on the substrate, which comprises a plurality of pixel electrodes which are in one-to-one correspondence with the plurality of sub-pixel areas; a common electrode layer provided on the substrate, which is provided with a plurality of cutting hole at positions corresponding to spaces between the pixel electrodes; a first insulating layer provided between the pixel electrode layer and the common electrode layer; and a second insulating layer provided between the gate metal layer and the source and drain metal layer. |
| US09748273B2 |
Semiconductor device
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor. |
| US09748265B1 |
Integrated structures comprising charge-storage regions along outer portions of vertically-extending channel material
Some embodiments include an integrated structure having stacked conductive levels. At least some of the conductive levels are wordline levels and include control gate regions of memory cells. One of the conductive levels is a vertically outermost conductive level along an edge of the stack. Vertically-extending channel material is along the conductive levels. Some of the channel material extends along the memory cells. An extension region of the channel material is vertically outward of the vertically outermost conductive level. A charge-storage structure has a first region directly between the vertically outermost conductive level and the channel material, and has a second region which extends vertically outward of the vertically outermost conductive level and is along the extension region of the channel material. |
| US09748260B2 |
Nonvolatile semiconductor memory device and manufacturing method thereof
A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state. |
| US09748257B2 |
Semiconductor devices having dummy patterns and methods of fabricating the same
Provided are semiconductor devices and methods of fabricating the same. The semiconductor devices may include a substrate with a cell region and a peripheral region, a gate stack including gates stacked on the cell region of the substrate. At least one edge portion of the gate stack may have a staircase structure. The semiconductor devices may also include a channel that extend through the gate stack and is enclosed by a memory layer and at least two dummy patterns on the substrate. The at least two dummy patterns may be spaced apart from the gate stack and may be spaced apart from each other. |
| US09748256B2 |
Semiconductor device and method of forming the same
Provided is a semiconductor device including a memory gate structure and a select gate structure. The memory gate structure is closely adjacent to the select gate structure. Besides, an air gap encapsulated by an insulating layer is disposed between the memory gate structure and the select gate structure. |
| US09748254B2 |
Convex shaped thin-film transistor device having elongated channel over insulating layer in a groove of a semiconductor substrate
The present invention provides a semiconductor device that has a shorter distance between the bit lines and easily achieves higher storage capacity and density. The semiconductor device includes: first bit lines and an insulating layer that is provided between the first bit lines and in a groove. First faces of the first bit lines are aligned on a first line and second faces of the first bit lines are aligned on a second line. A first face of the insulating layer is disposed at a third line that is a first distance from the first line in a first direction and a second face of the insulating layer is disposed at a fourth line that is a second distance from the second line in a second direction. |
| US09748252B2 |
Antifuse element utilizing non-planar topology
Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In some embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region. |
| US09748250B2 |
Deep trench sidewall etch stop
Embodiments of the present invention provide a structure and method for fabrication of deep trenches in semiconductor-on-insulator structures. An upper portion of the deep trench cavity is formed to expose a sidewall of the buried insulator layer. A protective layer is disposed on the sidewall of the buried insulator layer. Then, the cavity is extended into the bulk substrate. The protective layer prevents over etch of the buried insulator layer during this process. The protective layer is then partially removed, such that the semiconductor-on-insulator (SOI) layer sidewall is exposed. The trench is then filled with a conductive fill material, such as polysilicon. The protection of the buried insulator (BOX) layer allows the trenches to be placed closer together while reducing the risk of a short circuit due to over etch, thereby increasing circuit density and product yield. |
| US09748247B2 |
Semiconductor device
A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region. |
| US09748246B2 |
Semiconductor integrated circuits having contacts spaced apart from active regions
First and second active regions are doped with different types of impurities, and extend in a first direction and spaced apart from each other in a second direction. First and third gate structures, which are on the first active region and a first portion of the isolation layer between the first and second active regions, extend in the second direction and are spaced apart from each other in the first direction. Second and fourth gate structures, which are on the second active region and the first portion, extend in the second direction, are spaced apart from each other in the first direction, and face and are spaced apart from the first and third gate structures, respectively, in the second direction. First to fourth contacts are on portions of the first to fourth gate structures, respectively. The first and fourth contacts are connected, and the second and third contacts are connected. |
| US09748244B2 |
Method for manufacturing semiconductor device and semiconductor device
A semiconductor device includes a first and second fin-shaped semiconductor layers on a substrate. A first insulating film is around the first and second fin-shaped layers. A first and second pillar-shaped semiconductor layers reside on the first and second fin-shaped layers, respectively. A width of a bottom of the first pillar-shaped semiconductor layer is equal to a width of a top of the first fin-shaped semiconductor layer, and a width of a bottom of the second pillar-shaped semiconductor layer is equal to the width of a top of the second fin-shaped semiconductor layer. First and second gate insulating films and first and second metal gate electrodes reside around the first and second pillar-shaped layers, respectively. A metal gate line is connected to the first and second metal gate electrodes and extends in a direction perpendicular to the first and second fin-shaped layers. |
| US09748242B2 |
Semiconductor device
A semiconductor device is provided that includes a composite semiconductor body including a high voltage depletion-mode transistor and a low voltage enhancement-mode transistor. The high voltage depletion-mode transistor is stacked on the low voltage enhancement-mode transistor so that an interface is formed between the high voltage depletion-mode transistor and the low voltage enhancement-mode transistor. The low voltage enhancement-mode transistor includes a current path coupled in series with a current path of the high voltage depletion-mode transistor, and a control electrode is arranged at the interface. |
| US09748239B2 |
Fin-double-gated junction field effect transistor
A method of forming a double-gated junction field effect transistors (JFET) and a tri-gated metal-oxide-semiconductor field effect transistor (MOSFET) on a common substrate is provided. The double-gated JFET is formed in a first region of a substrate by forming a semiconductor gate electrode contacting sidewall surfaces of a first channel region of a first semiconductor fin and a top surface of a portion of a first fin cap atop the first channel region. The tri-gated MOSFET is formed in a second region of the substrate by forming a metal gate stack contacting a top surface and sidewall surfaces of a second channel region of a second semiconductor fin. |
| US09748237B2 |
Semiconductor integrated circuit and logic circuit
Disclosed herein is a driver circuit including first and second n-channel transistors connected together in series between first and second nodes. The first n-channel transistor is comprised of n fin transistor(s) having an identical gate length and an identical gate width where n is equal to or greater than one, and has its gate connected to a first input node. The second n-channel transistor is comprised of m fin transistors having the same gate length and the same gate width where m is greater than n, and has its gate connected to a second input node. |
| US09748236B1 |
FinFET device with enlarged channel regions
A semiconductor device including a semiconductor layer, a plurality of semiconductor fins formed on a surface of the semiconductor layer and a plurality of gate electrodes formed over the surface of the semiconductor layer is provided. The semiconductor fins extend in parallel to each other along a first direction parallel to the surface of the semiconductor layer and have a first height in a second direction that is perpendicular to the first direction, and the gate electrodes comprise longitudinal portions extending parallel to the semiconductor fins along the first direction and, in particular, having a second height in the second direction lower than the first height. |
| US09748235B2 |
Gate stack for integrated circuit structure and method of forming same
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: forming a first work function metal over a set of fins having at least a first fin and a second fin; implanting the first work function metal with a first species; removing the implanted first work function metal from over the first fin such that a remaining portion of the implanted first work function metal remains over the second fin; forming a second work function metal over the set of fins including over the remaining portion of the implanted first work function metal; implanting the second work function metal with a second species; and forming a metal over the implanted second work function metal over the set of fins thereby forming the gate stack. |
| US09748232B2 |
Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region and a first drain region. The semiconductor device structure includes a first gate over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a first contact structure over the first source region. The first contact structure is electrically connected to the first source region. The semiconductor device structure includes a second contact structure over the first drain region. The second contact structure is electrically connected to the first drain region. The semiconductor device structure includes a conductive layer electrically connecting the first gate to the first contact structure and the second contact structure. |
| US09748231B2 |
Semiconductor device
A semiconductor device includes: a substrate; a first active region formed in the substrate and that includes a first region that has a first width and a second region including a second width larger than the first width and extended in a first direction; a second active region formed in the substrate and extended in parallel to the second region of the first active region; and an element isolation insulating film formed in the substrate and that partitions the first active region and the second active region, respectively, wherein the second region of the first active region or the second active region includes a depressed part depressed in a second direction that is perpendicular to the first direction in a plan view. |
| US09748230B2 |
Semiconductor apparatus having a trench Schottky barrier Schottky diode
A semiconductor apparatus having a trench Schottky barrier Schottky diode, which includes: a semiconductor volume of a first conductivity type, which semiconductor volume has a first side covered with a metal layer, and at least one trench extending in the first side and at least partly filled with metal. At least one wall segment of the trench, and/or at least one region, located next to the trench, of the first side covered with the metal layer, is separated by a layer, located between the metal layer and the semiconductor volume, made of a first semiconductor material of a second conductivity type. |
| US09748226B1 |
Decoupling capacitor
A device is disclosed that includes active areas, gates, and conductors. The active areas are disposed apart from each other. The gates are crossing over the active areas. The conductors are disposed over the active areas and disposed between the active areas. Each one of the conductors disposed between the active areas is arranged between adjacent two of the gates, and has an overlap with at least one corresponding gate of the gates to form at least one capacitor. |
| US09748225B2 |
Semiconductor device with power transistors coupled to diodes
The ringing of a switching waveform of a semiconductor device is restrained. For example, an interconnect (L5) is laid which functions as a source of a power transistor (Q3) and a cathode of a diode (D4), and further functioning as a drain of a power transistor (Q4) and an anode of a diode (D3). In other words, a power transistor and a diode coupled to this power transistor in series are formed in the same semiconductor chip; and further an interconnect functioning as a drain of the power transistor and an interconnect functioning as an anode of the diode are made common to each other. This structure makes it possible to decrease a parasite inductance between the power transistor and the diode coupled to each other in series. |
| US09748223B2 |
Six-transistor SRAM semiconductor structures and methods of fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM. |
| US09748220B1 |
Gate-bounded silicon controlled rectifier
A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first P-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a third semiconductor region. The N-type well region and the P-type well region are disposed in the substrate. The first N-type semiconductor region is disposed in the N-type well region. The first P-type semiconductor region is disposed in the P-type well region. The second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The third semiconductor region is located between the second N-type semiconductor region and the second P-type semiconductor region. |
| US09748218B1 |
Method and apparatus to facilitate direct surface cooling of a chip within a 3D stack of chips using optical interconnect
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space. |
| US09748216B2 |
Apparatus and method for a component package
A component package and a method of forming are provided. A first component package may include a first semiconductor device having a pair of interposers attached thereto on opposing sides of the first semiconductor device. Each interposer may include conductive traces formed therein to provide electrical coupling to conductive features formed on the surfaces of the respective interposers. A plurality of through vias may provide for electrically connecting the interposers to one another. A first interposer may provide for electrical connections to a printed circuit board or subsequent semiconductor device. A second interposer may provide for electrical connections to a second semiconductor device and a second component package. The first and second component packages may be combined to form a Package-on-Package (“PoP”) structure. |
| US09748215B2 |
Light emitting device
A light emitting device includes: at least one first light emitting element configured to emit ultraviolet light; at least one second light emitting element configured to emit light with a wavelength longer than that of the ultraviolet light emitted from the at least one first light emitting element; an electronic component including a resin portion on a surface thereof; and a substrate on which the at least one first light emitting element, the at least one second light emitting element, and the electronic component are mounted and disposed in that order along a first direction of the substrate. |
| US09748212B2 |
Shadow pad for post-passivation interconnect structures
Interconnect structures, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, an interconnect structure includes a first post-passivation interconnect (PPI) layer. The first PPI layer includes a landing pad and a shadow pad material proximate the landing pad. A polymer layer is over the first PPI layer, and a second PPI layer is over the polymer layer. The second PPI layer includes a PPI pad. The PPI pad is coupled to the landing pad by a via in the polymer layer. The shadow pad material is proximate the PPI pad and comprises a greater dimension than a dimension of the PPI pad. The shadow pad material is disposed laterally around the PPI pad. |
| US09748210B2 |
Method for transfer of semiconductor devices
A method of transferring semiconductor devices to a product substrate includes positioning a surface of the product substrate to face a first surface of a semiconductor wafer having the semiconductor devices thereon, and actuating a transfer mechanism to cause the transfer mechanism to engage a second surface of the semiconductor wafer. The second surface of the semiconductor wafer is opposite the first surface of the semiconductor wafer. Actuating the transfer mechanism includes causing a pin to thrust against a position on the second surface of the semiconductor wafer corresponding to a position of a particular semiconductor device located on the first surface of the semiconductor wafer, and retracting the pin to a rest position. The method further includes detaching the particular semiconductor device from the second surface of the semiconductor wafer, and attaching a particular semiconductor device to the product substrate. |
| US09748208B2 |
Light-emitting device
A light-emitting device includes a substrate, and a plurality of light-emitting arrays or light-emitting groups arranged on the substrate. The light-emitting arrays or light-emitting groups include a plurality of LED elements connected in parallel with a pair of adjacent electrodes. The number of the LED elements constituting each of the light-emitting arrays or the light-emitting groups differs in each of the light-emitting arrays or the light-emitting groups. Of the plurality of light-emitting arrays arranged in parallel with each other or the light-emitting groups arranged in a line, the number of the LED elements of the light-emitting arrays or the light-emitting groups positioned inside the substrate is more than the number of the LED elements of the light-emitting arrays or the light-emitting groups positioned outside the substrate. |
| US09748207B2 |
Bonded dies with isolation
An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies. |
| US09748206B1 |
Three-dimensional stacking structure and manufacturing method thereof
A three-dimensional stacking structure and the manufacturing method(s) thereof are described. The stacking structure includes at least a bottom die, a top die and a spacer protective structure. The bottom die include contact pads in the non-bonding region. The top die is stacked on the bottom die without covering the contact pads of the bottom die and the bottom die is bonded with the top die through bonding structures there-between. The spacer protective structure is disposed on the bottom die and covers the top die to protect the top die. By forming an anti-bonding layer before stacking the top dies to the bottom dies, the top die can be partially removed to expose the contact pads of the bottom die for further connection. |
| US09748202B2 |
Semiconductor device
A semiconductor device includes a first circuit board having a first chip and a second chip mounted on a first base, the second chip having a greater height from the first base than that of the first chip; and a second circuit board having a third chip and a fourth chip mounted on a second base, the fourth chip having a greater height from the second base than that of the third chip, the second circuit board being disposed overlapping with the first base such that the second base faces the first chip, and the second base not contacting the second chip. |
| US09748193B2 |
Printed circuit board and semiconductor package using the same
A printed circuit board (PCB) includes: a base substrate including a top surface including an electronic device mounting region; chip connection pads that are provided on the electronic device mounting region; a conductive pattern group that is provided on the top surface of the base substrate and includes an extended conductive pattern extending between two adjacent chip connection pads from among the chip connection pads, the extended conductive pattern being spaced apart from each of the two adjacent chip connection pads; and a solder resist layer that covers a part of the extended conductive pattern and is spaced apart from the chip connection pads. |
| US09748190B2 |
Low cost and ultra-thin chip on wafer on substrate (CoWoS) formation
Methods of making and an integrated circuit device. An embodiment method includes patterning a first polymer layer disposed over a first copper seed layer, electroplating a through polymer via in the first polymer layer using the first copper seed layer, a via end surface offset from a first polymer layer surface, forming a second polymer layer over the first polymer layer, the second polymer layer patterned to expose the via end surface, and electroplating an interconnect in the second polymer layer to cap the via end surface using a second copper seed layer. |
| US09748188B2 |
Method of forming a bump on pad (BOP) bonding structure in a semiconductor packaged device
The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated bonding structures on either the package and/or the bonding substrate and by orienting such bonding structures, the bonding structures are designed to withstand bonding stress caused by thermal cycling to reduce cold joints. |
| US09748187B2 |
Wafer structure and method for wafer dicing
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed. |
| US09748182B2 |
Wafer processing method
Disclosed herein is a wafer processing method including a stacked member removing step of applying a laser beam having an absorption wavelength to a stacked member through a protective film along each division line formed on the front side of a wafer, thereby performing ablation to remove the stacked member present on each division line, a dividing step of applying an external force to the wafer to divide the wafer into individual device chips along each division line where a modified layer is previously formed, and a plasma etching step of supplying an etching gas in a plasma state to the wafer from the front side thereof after performing the stacked member removing step or after performing the dividing step, thereby removing damage due to the ablation in the stacked member removing step. |
| US09748181B1 |
Methods and apparatus for crack propagation prevention and enhanced particle removal in scribe line seals
An example apparatus includes a plurality of scribe streets arranged in rows and columns on the surface of a semiconductor wafer; and a plurality of integrated circuit dies arranged in rows and columns and spaced apart by the scribe streets. Each integrated circuit die includes plurality of active areas; a plurality of insulator layers overlying the active areas; a plurality of conductor layers interspersed with and separated by ones of the insulator layers; and a passivation layer overlying a top portion of the uppermost one of the conductor layers. A scribe seal in a scribe region surrounds the periphery of the integrated circuit dies, the scribe seal covered by the passivation layer; and a crack arrest structure is located surrounding and spaced from the scribe seal, and including an opening in the passivation layer that extends to and exposes the upper surface of the crack arrest structure. Methods are disclosed. |
| US09748180B2 |
Through-body via liner deposition
Techniques are disclosed for through-body via liner structures and processes of forming such liner structures in an integrated circuit. In an embodiment, an integrated circuit includes a silicon semiconductor substrate having one or more through-silicon vias (TSVs), although other through-body vias can be used as will be appreciated in light of this disclosure. Each TSV extends through at least a portion of the substrate, for example, from one side (e.g., top) of the substrate to the opposite side of the substrate (e.g., bottom), or from one internal layer of the substrate to another internal layer. A liner is disposed between the substrate and each TSV. The liner is formed of multiple alternating layers of dissimilar insulation films (e.g., tensile films and compressive films) sandwiched together. |
| US09748174B1 |
Three-dimensional memory device having multi-layer diffusion barrier stack and method of making thereof
An alternating stack of insulating layers and spacer material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are removed to form backside recesses. The backside recesses are sequentially filled with a continuous layer stack including a first continuous metallic nitride layer, a continuous tungsten layer, a second continuous metallic nitride layer, and a continuous metal fill layer. The continuous layer stack is patterned to form electrically conductive layers. Each electrically conductive layer includes a liner stack of a first metallic nitride liner, a tungsten liner, and a second metallic nitride liner. The liner stack is a diffusion barrier for high diffusivity species such as fluorine and boron. |
| US09748172B2 |
Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines
A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines. |
| US09748170B2 |
Semiconductor devices having staggered air gaps
A semiconductor device includes a substrate, a plurality of first conductive patterns disposed on the substrate and a plurality of second conductive patterns disposed on the first conductive patterns. Respective air gaps are disposed between adjacent ones of the first conductive patterns overlying a first region of the substrate, while adjacent ones of the first conductive patterns overlying a second region of the substrate do not have air gaps disposed therebetween. The air gaps may include first air gaps, and the device may further include second air gaps disposed between adjacent ones of the second conductive patterns in the second region. Adjacent ones of the second conductive patterns overlying a second region of the substrate may not have air gaps disposed therebetween. |
| US09748168B2 |
Substrate with routing
A substrate having an edge; a first and second active trace, wherein the first active trace corresponds to a first signal of a differential pair and the second active trace corresponds to a second signal of the differential pair; and a first and second conductive via which are located at different distances from the edge. The first active trace is routed to the first conductive via, and the second active trace is routed around the first conductive via to the second conductive via such that the second active trace is between the first conductive via and the edge. The substrate includes a first plating trace in electrical contact with the first active trace, and a second plating trace in electrical contact with the second active trace, wherein the first and second plating traces are routed to the edge on different metal layers of the substrate. |
| US09748166B2 |
Semiconductor devices including control and load leads of opposite directions
A device includes a carrier and a semiconductor chip arranged over a surface of the carrier. The semiconductor chip includes a control electrode and a load electrode. A first lead is electrically coupled to the control electrode and extends away from the control electrode in a first direction. A second lead is electrically coupled to the load electrode and extends away from the load electrode in a second direction opposite the first direction. |
| US09748164B2 |
Semiconductor device
A lead frame of high quality which can endure direct bonding to the electrodes of a semiconductor element and a metal member, and a semiconductor device of high reliability which utilizing the lead frame. The lead frame includes a pair of lead frame portions which are arranged spaced apart from and opposite to each other to be electrically connected to a pair of electrodes of a semiconductor element respectively, and a pair of support bars which are arranged spaced apart from the lead portions and extending from a side of either one of the lead portions to a side of the other lead portion. |
| US09748159B2 |
Electronic device provided with an integral conductive wire and method of manufacture
An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to the mounting face and is electrically connected to the electrical connection network. A primary encapsulation block embeds the integrated circuit chip and extends above and around the integrated circuit chip on the mounting face of the supporting substrate. An opening is provided in the primary encapsulation block to at least partially uncover an electrical contact. An additional wire made from an electrically conductive material has an end that is electrically connected to the electrical contact. An additional encapsulation block above the primary encapsulation block embeds the additional wire. |
| US09748157B1 |
Integrated circuit packaging system with joint assembly and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof includes: a base substrate having a bottom pad; an integrated circuit device mounted on the base substrate; an interposer having a package interconnect mounted on the base substrate, the package interconnect includes an underside base portion having an irregular surface characteristic of a coining process; and an encapsulation between the interposer and the base substrate. |
| US09748155B2 |
Printed circuit board
A printed wiring board includes a power supply conductor pattern arranged on one conductor layer, one ground conductor pattern arranged on the one conductor layer, and another ground conductor pattern arranged on the another conductor layer so as to be opposed to the power supply conductor pattern. The power supply conductor pattern includes a power supply pad on which a terminal of a capacitor is to be bonded. The one ground conductor pattern includes a ground pad on which another terminal of the capacitor is to be bonded. A slit is formed in the another ground conductor pattern so as to pass through a projection portion defined by projecting the power supply pad onto the another ground conductor pattern and divide a projection portion defined by projecting the power supply conductor pattern onto the another ground conductor pattern. |
| US09748153B1 |
Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of side-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of tip-to-side shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured. |
| US09748148B2 |
Localized stress modulation for overlay and EPE
Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system. |
| US09748145B1 |
Semiconductor devices with varying threshold voltage and fabrication methods thereof
Semiconductor device fabrication methods are provided which include: providing a structure with at least one region and including a dielectric layer disposed over a substrate; forming a multilayer stack structure including a threshold-voltage adjusting layer over the dielectric layer, the multilayer stack structure including a first threshold-voltage adjusting layer in a first region of the at least one region, and a second threshold-voltage adjusting layer in a second region of the at least one region; and annealing the structure to define a varying threshold voltage of the at least one region, the annealing facilitating diffusion of at least one threshold voltage adjusting species from the first threshold-voltage adjusting layer and the second threshold-voltage adjusting layer into the dielectric layer, where a threshold voltage of the first region is independent of the threshold voltage of the second region. |
| US09748142B2 |
FinFETs with strained well regions
A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band. |
| US09748141B2 |
Semiconductor device and method for manufacturing the same
Provided are a semiconductor device and a method for manufacturing the same. An example method may include: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate, wherein the first semiconductor layer is doped; patterning the second and first semiconductor layers to form an initial fin; forming a dielectric layer on the substrate to substantially cover the initial fin, wherein a portion of the dielectric layer on top of the initial fin has a thickness sufficiently less than that of a portion of the dielectric layer on the substrate; etching the dielectric layer back to form an isolation layer, wherein the isolation layer partially exposes the first semiconductor layer, thereby defining a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer. |
| US09748138B2 |
Metal layer end-cut flow
A method of patterning a metal layer is disclosed. The method includes providing a substrate and forming a material layer over the substrate. The method includes forming a second material layer over the first material layer. The method includes performing a first patterning process to the second material layer to form a trench in the second material layer. The first patterning process defines a width size of the trench, the width size being measured in a first direction. The method includes performing a second patterning process to the trench to transform the trench. The second patterning process defines a length size of the transformed trench. The length size is measured in a second direction different from the first direction. The method also includes filling the transformed trench with a conductive material. |
| US09748125B2 |
Continuous substrate processing system
A processing chamber having a plurality of movable substrate carriers stacked therein for continuously processing a plurality of substrates is provided. The movable substrate carrier is capable of being transported from outside of the processing chamber, e.g., being transferred from a load luck chamber, into the processing chamber and out of the processing chamber, e.g., being transferred into another load luck chamber. Process gases delivered into the processing chamber are spatially separated into a plurality of processing slots, and/or temporally controlled. The processing chamber can be part of a multi-chamber substrate processing system. |
| US09748117B2 |
Substrate treating apparatus and substrate treating method
Provided is a substrate treating apparatus. The substrate treating apparatus includes a chamber, a support member disposed within the chamber to support a substrate, and an exhaust member for exhausting a gas within an inner space of the chamber to the outside of the chamber. A trap space for collecting fumes contained in the gas is defined in the exhaust member. |
| US09748114B2 |
Method for forming through silicon via in N+ epitaxy wafers with reduced parasitic capacitance
A semiconductor device includes an epitaxy layer formed on semiconductor substrate, a device layer formed on the epitaxy layer, a trench formed within the semiconductor substrate and including a dielectric layer forming a liner within the trench and a conductive core forming a through-silicon via conductor, and a deep trench isolation structure formed within the substrate and surrounding the through-silicon via conductor. A region of the epitaxy layer formed between the through-silicon via conductor and the deep trench isolation structure is electrically isolated from any signals applied to the semiconductor device, thereby decreasing parasitic capacitance. |
| US09748113B2 |
Method and apparatus for controlled dopant incorporation and activation in a chemical vapor deposition system
Embodiments include systems and methods for producing semiconductor wafers having reduced quantities of point defects. These systems and methods include a tunable ultraviolet (UV) light source, which is controlled to produce a raster of a UV light beam across a surface of a semiconductor wafer during epitaxial growth to dissociate point defects in the semiconductor wafer. In various embodiments, the tunable UV light source is configured external to a Metal Organic Chemical Vapor Deposition (MOCVD) chamber and controlled such that the UV light beam is directed though a window defined in a wall of the MOCVD chamber. |
| US09748111B2 |
Method of fabricating semiconductor structure using planarization process and cleaning process
A method for fabricating a semiconductor structure includes following steps. First, a first layer, a second layer and a third layer are sequentially formed on the substrate. The second layer is conformally disposed on the top surface of the first layer. The second layer and the first layer have different compositions, and the third layer and the second layer also have different compositions. Then, a planarizing process is performed on the third layer until portions of the second layer are exposed. Afterwards, hydrofluoric acid and aqueous oxidant are concurrently or sequentially provided to the remaining second and third layers. Finally, an etch back process is carried out to remove all the second layer and portions of the first layer. |
| US09748104B2 |
Method of depositing film
A method of depositing a film is provided. In the method, one operation of a unit of film deposition process is performed by carrying a substrate into a processing chamber, by depositing a nitride film on the substrate, and by carrying the substrate out of the processing chamber after finishing depositing the nitride film on the substrate. The one operation is repeated a predetermined plurality of number of times continuously to deposit the nitride film on a plurality of substrates continuously. After that, an inside of the processing chamber is oxidized by supplying an oxidation gas into the processing chamber. |
| US09748095B2 |
Controlled manufacturing method of metal oxide semiconductor and metal oxide semiconductor structure having controlled growth crystallographic plane
A method of controlling a growth crystallographic plane of a metal oxide semiconductor having a wurtzite crystal structure by using a thermal chemical vapor deposition method includes controlling a growth crystallographic plane by allowing the metal oxide semiconductor to grow in a non-polar direction by using a source material including a thermal decomposition material that reduces a surface energy of a polar plane of the metal oxide semiconductor. |
| US09748091B2 |
Substrate treatment apparatus and substrate treatment method
In one embodiment, a substrate treatment apparatus includes a housing configured to house a substrate. The apparatus further includes a chemical supplying module configured to supply one or more chemicals in a gas state to the substrate in the housing, the one or more chemicals including a first chemical that contains a silylation agent. The apparatus further includes a cooling module configured to cool the substrate in the housing while any of the one or more chemicals is supplied to the substrate in the housing. |
| US09748089B2 |
Method for producing mirror-polished wafer
A method for producing mirror-polished wafer, the method produces a plurality of mirror-polished wafers by performing, on plurality of silicon wafers obtained by slicing a silicon ingot, slicing strain removing step of removing strain on a surface caused by slicing, etching step of removing strain caused by the slicing strain removing step, and double-side polishing step of performing mirror polishing on both surfaces of the silicon wafers subjected to etching, each step being performed by batch processing, wherein silicon wafers which are processed in double-side polishing step by batch processing are selected from silicon wafers processed in same batch in the slicing strain removing step and the number of silicon wafers to be selected is made to be equal to the number of silicon wafers processed in the slicing strain removing step or submultiple thereof. As a result, a method that can produce mirror-polished wafers having high flatness is provided. |
| US09748083B2 |
Method of tandem mass spectrometry
A method of tandem mass spectrometry is disclosed. A quasi-continuous stream of ions from an ion source (20) and having a relatively broad range of mass to charge ratio ions is segmented temporally into a plurality of segments. Each segment is subjected to an independently selected degree of fragmentation, so that, for example, some segments of the broad mass range are fragmented while others are not. The resultant ion population, containing both precursor and fragment ions, is analyzed in a single acquisition cycle using a high resolution mass analyzer (150). The technique allows the analysis of the initial ion population to be optimized for analytical limitations. |
| US09748081B2 |
Method of manufacturing semiconductor device and sputtering apparatus
Reliability of a semiconductor device is improved, and use efficiency of a sputtering apparatus is increased. When depositing thin films over a main surface of a semiconductor wafer using a magnetron sputtering apparatus in which a collimator is installed in a space between the semiconductor wafer and a target installed in a chamber, a region inner than a peripheral part of the collimator is made thinner than the peripheral part. Thus, it becomes possible to suppress deterioration in uniformity of the thin film in a wafer plane, which may occur as the integrated usage of the target increases. |
| US09748080B2 |
Cu—Ga alloy sputtering target and method for producing same
According to the present invention, a Cu—Ga alloy sputtering target which is a sintered body has a composition with 29.5 atom % to 43.0 atom % of Ga and a balance of Cu and inevitable impurities. A Cu—Ga alloy crystal particle in the sintered body has a structure in which γ phase particles are dispersed in a γ1-phase crystal particle. A method for producing the sputtering target includes a step of performing normal pressure sintering by heating a molded body formed of a powder mixture of a pure Cu powder and a Cu—Ga alloy powder in a reducing atmosphere, and a step of cooling the obtained sintered body at a cooling rate of 0.1° C./min to 1.0° C./min, at a temperature having a range of 450° C. to 650° C. |
| US09748077B2 |
Substrate processing device and substrate processing method
Disclosed is an apparatus and method of processing substrate, wherein the apparatus comprises a process chamber; a substrate supporter for supporting at least one of substrates, wherein the substrate supporter is provided in the process chamber, and is rotated at a predetermined direction; a chamber lid confronting with the substrate supporter, the chamber lid for covering the process chamber; and a gas distributor having a plurality of gas distribution modules for distributing gas to the substrate, wherein the plurality of gas distribution modules are connected to the chamber lid, wherein each of the gas distribution modules includes a power source electrode and a ground electrode confronting each other, a plasma discharge space is formed between the power source electrode and the ground electrode, and the plasma discharge space is not overlapped with a thin film formation region of the substrate supported by the substrate supporter. |
| US09748073B2 |
Analysis method using electron microscope, and electron microscope
An analysis method using an electron microscope, detects by a first electronography detector an electron beam transmitted through or scattered by a sample to detect an ADF image of the sample, detects by a second electronography detector the electron beam passing through the first electronography detector to detect an MABF image, adjusts a focal point of the electron beam to be located on the film of the sample to obtain first and second electronographies by the second and first electronography detectors, respectively, adjusts the focal point of the electron beam to be located on the substrate of the sample to obtain third and fourth electronographies by the second and first electronography detectors, respectively, aligns positions of the second and fourth electronographies based on the first and third electronographies, and after the aligning, subtracts the fourth electronography from the second electronography to obtain an image of the film. |
| US09748072B2 |
Lower dose rate ion implantation using a wider ion beam
In an exemplary process for lower dose rate ion implantation of a work piece, an ion beam may be generated using an ion source and an extraction manipulator. The extraction manipulator may be positioned at a gap distance from an exit aperture of the ion source. A current of the ion beam exiting the extraction manipulator may be maximized when the extraction manipulator is positioned at an optimal gap distance from the exit aperture. The gap distance at which the extraction manipulator is positioned from the exit aperture may differ from the optimal gap distance by at least 10 percent. A first potential may be applied to a first set of electrodes. An x-dimension of the ion beam may increase as the ion beam passes through the first set of electrodes. The work piece may be positioned in the ion beam to implant ions into the work piece. |
| US09748071B2 |
Individually switched field emission arrays
An electron beam apparatus is disclosed that includes a plurality of current source elements disposed in at least one field emitter array. Each current source element can be a gated vertical transistor, an ungated vertical transistor, or a current controlled channel that is proximate to an optically-modulated current source. The electron beam apparatus includes a plurality of field emitter tips, each field emitter tip of the plurality of field emitter tips being coupled to a current source element of the plurality of current source elements. The electron beam apparatus is configured to allow selective activation of one or more of the current source elements. |
| US09748070B1 |
X-ray tube anode
An X-ray tube includes a cathode and an anode. The cathode is configured to generate an electron beam. The anode has at least one hole that faces the electron beam, the hole having sidewalls and a floor. The electron beam impinges on one or more of the sidewalls of the at least one hole so as to emit a first X-ray beam at angles that are not orthogonal to a surface of the anode. The electron beam also impinges on the floor of the at least one hole so as to emit a second X-ray beam, at least some of which is emitted at an angle that is orthogonal to the surface of the anode. |
| US09748067B2 |
Positioning apparatus for an electron beam
A positioning apparatus is provided for an electron beam of an electron tube, the apparatus including a first DC voltage circuit having a high potential difference and a second DC voltage circuit having a smaller potential difference, having in each case a first potential level and a second potential level, and a deflection module, which has two inputs and at least one deflection coil, wherein the at least one deflection coil is connected between the two inputs of the deflection module. |
| US09748065B2 |
Sealed contact device
A sealed contact device capable of maintaining a function for drawing a generated arc to disappear rapidly and reliably for a long period. An electromagnetic relay includes a housing, a stationary contact and a moving contact which are disposed opposite to each other in the housing, and a pair of permanent magnets and disposed opposite to the stationary contact and the moving contact. An arc generated between the stationary contact and the moving contact is drawn due to a current conducting between the stationary contact and the moving contact and magnetic forces of the permanent magnets. An arc shield member is disposed in a position in which an arc in the housing is induced. |
| US09748064B2 |
Fail-safe circuit
A fail-safe circuit enables a switch to turn on/off according to a signal from an external device if a microcomputer that controls the turning on/off of the switch falls into an abnormal state and is reset, and if the power supply for a circuit that backs up the control of the switch is lost. The fail-safe circuit includes a microcomputer that controls the turning on/off of a switch based on an instruction signal from an input terminal, a watchdog circuit that generates a reset signal based on a watchdog pulse from the microcomputer, and a transistor for masking a watchdog pulse for resetting a flip-flop circuit that is set by the reset signal. If a voltage supplied by a power supply circuit is lost, a transistor turns off, and therefore the switch turns on/off according to an instruction signal supplied to an output terminal via a resistor and a diode. |
| US09748063B2 |
Overvoltage protection element
An overvoltage protection element with a housing, an overvoltage-limiting component arranged in the housing, and with two connection elements for electrically connecting the overvoltage protection element to the current or signal path to be protected, wherein, normally, the connection elements are each in electrical contact with a pole of the overvoltage-limiting component. Reliable and effective electrical connection in the normal state and reliable isolation of a defective overvoltage-limiting component are ensured by the fact that a thermally expandable material is arranged within the housing in a way that, in the event of thermal overloading of the overvoltage-limiting component, the position of the overvoltage-limiting component is changed by expansion of the thermally expandable material relative to the position of the connection elements in a way that causes at least one pole of the overvoltage-limiting component to be out of electrical contact with the corresponding connection element. |
| US09748060B2 |
Hybrid cutoff member for an electric circuit
A hybrid interrupter member for an electrical circuit, the interrupter member including a static interrupter component and an electromechanical interrupter component. The static component is mounted on a support carrying electrical contacts for the static component, the support being configured, on receiving a command to interrupt, to move in such a manner as to withdraw at least one of the electrical contacts from its respective pin, thereby forming the electromechanical interrupter component. |
| US09748056B2 |
Illuminated-type push-button switch and keyboard
A push-button switch (1) is arranged such that, once a user presses an operation button (8), a switch body (20) performs an operation, and light from an LED (21) passes through a transmission plate (70) and then illuminates the operation button (8). A structure (700) is provided on a lower surface (70b) of the transmission plate (70) to refract the light from the LED (21) so that the refracted light is reflected within the transmission plate (70) and then guided to an upper circumferential wall (71) of the transmission plate (70). |
| US09748053B2 |
Visible disconnect switch interlock assembly
A visible disconnect switch (VDS) interlock assembly is provided. The VDS interlock assembly is movable between a CBA, first lockout position, wherein a CBA second contact assembly cannot move when a VDS second contact assembly is in a first position, and a VDS, second lockout position, wherein a VDS second contact assembly cannot move when the CBA second contact assembly is in a second position. Further, the VDS interlock assembly is placed in an open position in between where the CBA, first lockout position and the VDS, second lockout position; from the open position the VDS interlock assembly may be moved into one of the CBA, first lockout position or the VDS, second lockout position. |
| US09748050B2 |
Keyswitch module and keyboard
A keyswitch module includes a bottom plate, a movable plate, a keycap, and a connecting assembly. The moving plate is stacked with the bottom plate and capable of moving between a first position and a second position relative to the bottom plate. The movable plate moves a horizontal stroke from the first position to the second position. The connecting assembly is operatively connected to the bottom plate and connected to the keycap. A forced portion of the connecting assembly is configured to be moved by a forcing structure of the movable plate to make the keycap move between an opening position and a closing position relative to the bottom plate. When the movable plate is located at the first position, the forcing structure and the forced portion are separated by a distance, and the keycap is located at the opening position. |
| US09748047B2 |
Connector arranged between two cylindrical energy storage assemblies
The invention relates to a module comprising at least two electrical energy storage assemblies (20), each storage assembly comprising: a tubular element (21) comprising a so-called side face (23), and at least one cover (50) for covering one of the ends of the tubular element. Said module is characterized in that it also comprises a connecting body (60) for electrically connecting the two assemblies, the connecting body comprising at least one portion, each portion being separate from at least one of the storage assemblies (20), and the connecting body extends between the two storage assemblies such that the height of each storage assembly connected to the connecting body is equal to the height of a storage assembly that does not have a connecting body. |
| US09748046B2 |
Power storage device
A power storage device that includes a first adhesive member between a first current collector and a second surface layer, and a second adhesive member between a second current collector and a first surface layer. A first electrolyte retaining layer is provided between the first adhesive member and the first current collector. A second electrolyte retaining layer is provided between the second adhesive member and the second current collector. |
| US09748045B2 |
Nonaqueous lithium storage element
Provided is a nonaqueous lithium storage element which is obtained by housing an electrode body and a nonaqueous electrolyte solution containing a lithium salt in an outer case, said electrode body being composed of a negative electrode that is composed of a negative electrode collector and a negative electrode active material layer laminated on one or both surfaces of the negative electrode collector, a positive electrode that is composed of a positive electrode collector and a positive electrode active material layer laminated on one or both surfaces of the positive electrode collector, and a separator. |
| US09748042B2 |
Multilayer feedthrough capacitor
An element body includes principal surfaces opposing each other in a first direction, first side surfaces opposing each other in a second direction perpendicular to the first direction, and second side surfaces opposing each other in a third direction perpendicular to the first and second directions. A length in the first direction of the element body is smaller than a length in the second direction of the element body and a length in the third direction of the element body. Each of the first and second terminal signal electrodes and the terminal ground electrode includes an electrode portion disposed on the principal surface. A thickness of the electrode portion of the terminal ground electrode is smaller than a thickness of the electrode portion of the first terminal signal electrode and smaller than a thickness of the electrode portion of the second terminal signal electrode. |
| US09748040B2 |
Electronic control device for controlling actuators
An electronic control device for controlling at least one rotatably arranged actuator includes electronic components, such as a device for the contact-free reception of electrical energy and the contact-free reception of signals, a device for generating magnetic fields, and a common housing that encloses the electronic components and assimilates them. The control device is rotatable and designed for attaching on or into a component rotating around a rotational axis. |
| US09748039B2 |
Wireless energy transfer resonator thermal management
A resonator structure for wireless power transfer includes a first piece and a second piece of magnetic material disposed adjacent to one another, a spacer disposed between the first and second pieces of magnetic material forming a gap of 1 mm or less between the first and second pieces of magnetic material, and an electrical conductor wound to form a plurality of loops. The electrical conductor is disposed on the first and second pieces of magnetic material. The resonator structure includes a thermal conductor positioned in contact with the electrical conductor and at least one of the first and second pieces of magnetic material. |
| US09748037B2 |
Power supply system and wireless power supply method
The power supply system includes: movable power-receiving units, each power-receiving unit including at least one power-receiving device used to receive electric power from outside of the power-receiving unit and at least one power-supplying device used to supply, to the outside of the power-receiving unit, at least part of electric power received by the power-receiving device; and a power-supplying unit used to supply electric power to the power-receiving device of one power-receiving unit of the power-receiving units. |
| US09748035B2 |
Methods for forming chip-scale electrical components
A method of forming a planar, low loss electrical component such as an inductor or transmission line is provided. A channel can be formed on a top surface of a substrate. A threading plate can be positioned on an upper surface of the channel. A wire or fiber can be introduced through the substrate, the channel, and the threading plate. The wire or fiber can then be guided into the channel using the threading plate. The substrate and the threading plate can then be removed. |
| US09748033B2 |
Integrated transformer
An integrated transformer includes a primary inductor and a secondary inductor wherein the primary inductor includes a B turns spiral winding formed by a first metal layer and an A turns winding formed by a second metal layer, wherein the A turns winding formed by the second metal layer and the innermost turns of the B turns spiral winding formed by the first metal layer are substantially overlapped; and the secondary inductor includes a C turns winding at least formed by the second metal layer, wherein the C turns winding formed by the second metal layer of the secondary inductor and a portion of the winding formed by the first metal layer of the primary inductor are substantially overlapped, wherein A is not bigger than B, and A is not bigger than C. |
| US09748029B2 |
Method of producing grain-oriented electrical steel sheet
In a method of producing a grain-oriented electrical steel sheet by hot rolling a steel slab having a chemical composition comprising C: 0.001 to 0.10 mass %, Si: 1.0 to 5.0 mass %, Mn: 0.01 to 0.5 mass %, S and/or Se: 0.005 to 0.040 mass %, sol. Al: 0.003˜0.050 mass % and N: 0.0010 to 0.020 mass %, subjecting to single cold rolling or two or more cold rollings including an intermediate annealing therebetween to a final thickness, performing primary recrystallization annealing, and thereafter applying an annealing separator to perform final annealing, a temperature range of 550° C. to 700° C. in a heating process of the primary recrystallization annealing is rapidly heated at an average heating rate of 40 to 200° C./s, while any temperature zone of from 250° C. to 550° C. is kept at a heating rate of not more than 10° C./s for 1 to 10 seconds, whereby the refining of secondary recrystallized grains is attained and grain-oriented electrical steel sheets are stably obtained with a low iron loss. |
| US09748026B2 |
Hexagonal ferrite magnetic powder for magnetic recording, method for producing hexagonal ferrite magnetic particles, and magnetic recording medium
Provided are hexagonal ferrite magnetic powder for magnetic recording, being comprised of hexagonal ferrite magnetic particles having a crystalline metal oxide adhered to a surface thereof, a method for producing hexagonal ferrite magnetic particles having a crystalline metal oxide adhered to a surface thereof, and a magnetic recording medium. |
| US09748025B2 |
Magnetoresistive current limiter
A magnetoresistive current limiter, comprising a substrate, a magnetoresistive sensor layer, a first insulating layer, a coil, a second insulating layer, a magnetic shield layer, and an input electrode and output electrode. The coil is located between the magnetic shield layer and the magnetoresistive sensor layer. The first and second insulating layers are isolated from the magnetoresistive sensor layer and the coil, and from the coil and the magnetic shield layer, respectively; the magnetoresistive sensor layer and the coil are connected in series, and are connected to the input electrode and the output electrode. The magnetoresistive sensor layer comprises N rows of array-type magnetic tunnel junction lines; the coil comprises 2*N+M (N>1, M=−1 or 3) conductive lines in series or N+M (N>1, M=0 or 2) conductive lines in parallel; current flows in the same direction into the conductive lines located above or below the tunnel junction lines and produces, at the magnetic tunnel junction lines, a uniform magnetic field. The magnetic tunnel junction of the magnetically sensitive axis is perpendicular to the magnetic tunnel junction lines, and the magnetoresistive sensor layer has the feature of a monotonic or axisymmetric linear rise in resistance to the magnetic field. The magnetoresistive current limiter has the features of rapid response, continuous operation, and ability to increase or decrease current. |
| US09748021B2 |
Cable connections
A plurality of telecommunications connections are installed in a distribution network by connecting a series of distribution points using a multicore cable comprising a plurality of cores having a common enclosure, some of the cores carrying fiber tubes into which optical fiber may later be introduced, and other cores carrying an electrical power supply. One or more cores may be diverted from a longer cable run to serve a local distribution point by rupturing a web connecting the core to the rest of the cable, thus allowing the remaining cores to be uninterrupted at the point of divergence. An alternative embodiment intended for underground use provides for apertures to be opened in a protective sheath to expose the individual cores required to be diverted to a local distribution point. |
| US09748012B2 |
Method for manufacturing metal grating structure, metal grating structure manufactured by the method, and X-ray imaging device using the metal grating structure
According to a method for manufacturing a metal grating structure of the present invention, in filling a concave portion formed in a silicon substrate (30), for instance, a slit groove (SD) with metal by an electroforming method, an insulating layer (34) is formed in advance on an inner surface of the slit groove (SD) as an example of the concave portion by a thermal oxidation method. Accordingly, the metal grating structure manufacturing method is advantageous in finely forming metal parts of the grating structure. A metal grating structure of the present invention is manufactured by the above manufacturing method, and an X-ray imaging device of the present invention is incorporated with the metal grating structure. |
| US09748011B2 |
Packaging for transporting and/or storing radioactive materials, including improved means for attaching a shock-absorbing cover
The invention relates to a packaging for transporting and/or storing radioactive materials, comprising a packaging body extending along a longitudinal direction, and further including at least one shock-absorbing cover mounted on one of both longitudinally opposite ends of the packaging body, the absorbing cover comprising attaching portions (44) on said packaging body, each attaching portion defining a clearing hole (58) through which an element (24) screwed in the packaging body passes. According to the invention, the attaching portion (44) has a deformable area (54) which, in the case of an outer bias on the absorbing cover leading to a contact strain between the screwed element (24) and the clearing hole (58), is designed to plastically deform. |
| US09748008B2 |
Nuclear power plant control system and nuclear power plant control method
A nuclear power plant control system (3) is provided with detection units (30a to 30d) which detect phenomena that occurs in a nuclear power plant for each of four systems, a trip control device (20) which starts, in the case where a signal that indicates an occurrence of the phenomenon is input from at least a predetermined number of signal lines out of signal lines of two systems, processing corresponding to the phenomenon, and majority circuits (50a and 50b) which are provided for each signal line of the two systems and each output, in the case where the phenomenon is detected by N or more detection units out of the detection units (30a to 30d), a signal that indicates an occurrence of the phenomenon to a corresponding signal line. |
| US09748007B2 |
Method, system, and apparatus for the thermal storage of energy generated by multiple nuclear reactor systems
A method, system, and apparatus for the thermal storage of energy generated by multiple nuclear reactor systems including diverting a first selected portion of energy from a portion of a first nuclear reactor system of a plurality of nuclear reactor systems to at least one auxiliary thermal reservoir, diverting at least one additional selected portion of energy from a portion of at least one additional nuclear reactor system of the plurality of nuclear reactor systems to the at least one auxiliary thermal reservoir, and supplying at least a portion of thermal energy from the auxiliary thermal reservoir to an energy conversion system of a nuclear reactor of the plurality of nuclear reactors. |
| US09748005B2 |
Apparatus and method to inspect nuclear reactor components in the core annulus, core spray and feedwater sparger regions in a nuclear reactor
This invention generally concerns robotic systems and is specifically concerned with an improved apparatus and method for inspecting nuclear reactor components in limited access areas, such as, the core annulus, core spray and feedwater sparger regions of a nuclear reactor. This invention includes an apparatus for remotely operating and positioning at least one inspection device for inspecting at least one component in an annulus region of a reactor pressure vessel of a nuclear power plant. The apparatus includes a track, a braking system and a frame assembly which has a frame movably connected to the track, at least one mast assembly and at least one mast positioning assembly. The at least one inspection device is attached to the at least one mast assembly. In certain embodiments, the at least one mast assembly includes a mast that is capable of becoming rigidly stable in both an extended tube form and a retracted rolled form. |
| US09748003B2 |
Efficient coding for memory redundancy
A system may be provided that provides redundancy for a plurality of embedded memories such as SRAMs. The system may include one or more decoders, each capable of decoding a selection address to identify a defective one of the embedded memories. |
| US09748001B2 |
Bad column management with bit information in non-volatile memory systems
Column based defect management techniques are presented. Each column of the memory has an associated isolation latch or register whose value indicates whether the column is defective, but in addition to this information, for columns marked as defective, additional information is used to indicate whether the column as a whole is to be treated as defective, or whether just individual bits of the column are defective. The defective elements can then be re-mapped to a redundant element at either the appropriate bit or column level based on the data. When a column is bad, but only on the bit level, the good bits can still be used for data, although this may be done at a penalty of under programming for some bits, as is described further below. A self contained Built In Self Test (BIST) flow constructed to collect the bit information through a set of column tests is also described. Based on this information, the bad bits can be extracted and re-grouped into bytes by the controller or on the memory to more efficiently use the column redundancy area. |
| US09748000B2 |
Magnetic element, skyrmion memory, solid-state electronic device data recording apparatus, data processing apparatus, and communication apparatus
Provided is a skyrmion memory circuit capable of circularly transferring a magnetic element skyrmion, comprising one or more current paths in a magnet having a closed-path pattern that are provided surrounding an end region including an end portion of the magnet in a plane of the magnet with the closed-path pattern, and applying current between an outer terminal connected to an outer circumferential portion of the closed-path pattern and an inner circumference electrode connected to an inner circumferential portion of the closed-path pattern, transferring the skyrmion in a direction substantially perpendicular to the direction of the applied current, and circulating the skyrmion in the magnet with the closed-path pattern. |
| US09747999B2 |
Compact eFuse array with different MOS sizes according to physical location in a word line
A array of electrically programmable fuse (eFuse) units includes at least one connecting switch connecting two adjacent eFuse units. Each eFuse unit includes an eFuse, a write switch for passing through a first portion of a write current, a read/write switch for passing through a second portion of the write current or a read current, and a common node. The eFuse, the write switch, the read/write switch, and the at least one connecting switch are connected to each other at the common node. By turning on and off the at least one connecting switch, the current is split among the eFuse units, so that the size of the write switch can be reduced, thus reducing the total area of the array. |
| US09747998B2 |
Test method of semiconductor memory device and semiconductor memory system transferring fail address data from a volatile to a non-volatile memory array using an error-correction code engine
A test method of the semiconductor memory device including a memory cell array and an anti-fuse array includes detecting failed cells included in the memory cell array; determining a fail address corresponding to the detected failed cells; storing the determined fail address in a first region of the memory cell array; and reading the fail address stored in the first region to program the read fail address in the anti-fuse array. According to the test method of a semiconductor memory device and the semiconductor memory system, since the test operation can be performed without an additional memory for storing an address, the semiconductor memory device and the test circuit can be embodied by a small area. |
| US09747995B2 |
Nonvolatile memory devices, operating methods thereof and memory systems including the same
Nonvolatile memory devices, operating methods thereof, and memory systems including the same. A nonvolatile memory device may include a memory cell array and a word line driver. The memory cell array may include a plurality of memory cells. The word line driver may be configured to apply word line voltages to a plurality of word lines connected to the plurality of memory cells, respectively. Magnitudes of the word line voltages may be determined according to locations of the plurality of word lines. |
| US09747993B2 |
Memory systems
Technologies are generally described for a memory system that may be a solid-state drive (SDD). The memory system may include memory blocks, where each memory block may have multiple memory pages, and each memory page may have multiple memory cells. The memory cells may have multiple programmed states. In various examples, a method to control the memory system may include determining one or more memory pages to be analyzed, identifying read threshold voltages of each memory cell associated with the memory pages to be analyzed, performing statistical analysis on the identified read threshold voltages, and determining a distribution of the read threshold voltages based at least in part on the statistical analysis. |
| US09747992B1 |
Non-volatile memory with customized control of injection type of disturb during read operations
A non-volatile memory system includes one or more control circuits configured to read memory cells. The reading of the programmed memory cells includes applying one or more voltages to perform boosting of a channel region associated with unselected memory cells, allowing the boosting of the channel region for a portion of time while applying the one or more voltages, preventing/interrupting the boosting of the channel region while applying the one or more voltages for a duration of time based on position of a memory cell selected for verification, applying a compare signal to the memory cell selected for reading, and performing a sensing operation for the memory cell selected for reading in response to the compare signal. |
| US09747989B1 |
Memory device and control method thereof
A memory device and a control method of the memory device are provided. The memory device includes a decoding circuit, Q switching circuits and Q blocks. The decoding circuit generates Q select signals. A k-th select signal of the Q select signals has a first select voltage. The other (Q−1) select signals have a second select voltage. The Q switching circuits receive an erase voltage, and generate Q common source line signals according to the Q select signals. A k-th common source line signal of the Q common source line signals generated by a k-th switching circuit of the Q switching circuits has the erase voltage. The Q blocks receive the Q common source line signals, respectively. A k-th block of the Q blocks is erased according to the k-th common source line signal. |
| US09747986B2 |
Transistor design for use in advanced nanometer flash memory devices
Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed. |
| US09747981B2 |
Apparatuses, devices and methods for sensing a snapback event in a circuit
Example subject matter disclosed herein relates to apparatuses and/or devices, and/or various methods for use therein, in which an application of an electric potential to a circuit may be initiated and subsequently changed in response to a determination that a snapback event has occurred in a circuit. For example, a circuit may comprise a memory cell that may experience a snapback event as a result of an applied electric potential. In certain example implementations, a sense circuit may be provided which is responsive to a snapback event occurring in a memory cell to generate a feed back signal to initiate a change in an electric potential applied to the memory cell. |
| US09747980B2 |
Semiconductor memory device and method for temperature compensation using temperature-resistance-voltage functions
A semiconductor device includes: a physical parameter sensing circuit configured to sense a variation of a physical parameter; an applying parameter generating circuit coupled to the physical parameter sensing circuit, configured to adjust an applying parameter from the variation of the physical parameter based on a transfer function which defines relationship between the physical parameter and the applying parameter; and a main circuit, coupled to the physical parameter sensing circuit and the applying parameter generating circuit, wherein the applying parameter generated by the applying parameter generating circuit is used to compensate effect on operations of the main circuit caused by the variation of the physical parameter. |
| US09747977B2 |
Methods and systems for verifying cell programming in phase change memory
Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages. |
| US09747975B2 |
Multi-level phase change memory
A phase change memory may be formed which is amenable to multilevel programming. The phase change material may be formed with a lateral extent which does not exceed the lateral extent of an underlying heater. As a result, the possibility of current bypassing the amorphous phase change material in the reset state is reduced, reducing the programming current that is necessary to prevent this situation. In addition, a more controllable multilevel phase change memory may be formed in some embodiments. |
| US09747973B2 |
Solid state storage device and data writing method to prevent data loss during program cycle
A data writing method for a solid state storage device includes following steps. A step (a) is performed to judge whether a shutdown command is issued from a host. In a step (b), if the solid state storage device confirms that the shutdown command is not issued from the host, plural program procedures are performed. Consequently, plural write data in a buffer are stored to a triple-level cell flash memory according to a program order. In a step (c), if the solid state storage device confirms that the shutdown command is issued from the host, plural redundant data are added to the plural write data, the write data are stored into the buffer, and the plural program procedures are performed. Consequently, the plural write data in the buffer are stored to the triple-level cell flash memory according to the program order. |
| US09747971B2 |
Row hammer refresh command
A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row. |
| US09747969B1 |
Charge sharing between memory cell plates using a conductive path
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. A first ferroelectric memory cell may be used to charge a second ferroelectric memory cell by transferring charge from a plate of first ferroelectric memory cell to a plate of the second ferroelectric memory cell. In some examples, prior to the transfer of charge, the first ferroelectric memory cell may be selected for a first operation in which the first ferroelectric memory cell transitions from a charged state to a discharged state and the second ferroelectric memory cell may be selected for a second operation during which the second ferroelectric memory cell transitions from a discharged state to a charged state. The discharging of the first ferroelectric memory cell may be used to assist in charging the second ferroelectric memory cell. |
| US09747966B2 |
Semiconductor memory device for sensing memory cell with variable resistance
According to one embodiment, a semiconductor memory device includes a memory cell; a reference signal generation circuit; a sense amplifier; a first transistor configured to electrically couple the memory cell and a first input terminal of the sense amplifier; a second transistor configured to electrically couple the reference signal generation circuit and a second input terminal of the sense amplifier; a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor; a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor; and a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor. |
| US09747962B2 |
Semiconductor device, electronic component, and electronic device
A semiconductor device which can write and read multilevel data is provided. A node connecting a source or a drain of an OS transistor and a gate of an OS transistor can hold the distribution of a plurality of potentials. A circuit configuration is employed in which the potential of the node is changed by capacitive coupling to control a conduction state of the OS transistor whose gate is connected thereto so that the potential of a gate of a Si transistor is changed. The potential of the gate of the Si transistor is changed positively in accordance with the potential change by capacitive coupling and is changed negatively in accordance with another transistor. In accordance with a change in value of current flowing through the Si transistor is detected, written data is read. |
| US09747960B2 |
Apparatuses and methods for converting a mask to an index
The present disclosure includes apparatuses and methods related to converting a mask to an index. An example apparatus comprises an array of memory cells and periphery logic configured to: generate an indicator mask by resetting, in response to a first control signal, a second digit of a mask different from a first digit of the mask that is set; and convert, in response to a second control signal, a digit position in the indicator mask of the first digit that is set to an identifier value as an index. |
| US09747955B2 |
Disc drive actuator assembly with bearing cooling
Various aspects of the present disclosure are directed toward a disc drive actuator assembly including an e-block, a plurality of bearings, and one or more heat transfer components. The heat transfer component(s) operates to conductively draw heat from the plurality of bearings through the e-block, and convectively dissipate the heat into an atmosphere in contact therewith. The heat transfer component(s) mitigates temperature rise of the bearings during operation of a disc drive, thereby mitigating bearing lubricant outgassing from within the bearings. |
| US09747953B1 |
Disk drive base unit with communicating groove extending outside outer circumferential portion of connector
A base member of a disk drive apparatus includes a window portion, a first groove, and a communicating groove. The window portion passes through a bottom plate portion of the base member in an axial direction. The first groove is defined in an upper surface of the bottom plate portion around the window portion. A connector includes a board portion and an electrode terminal on a lower surface of the board portion. The board portion is on the upper surface of the bottom plate portion to cover the window portion, the first groove, and a portion of the communicating groove. The communicating groove extends from the first groove up to a position outside of an outer circumferential portion of the connector. An adhesive layer is between the upper surface of the bottom plate portion and the lower surface of the board portion. |
| US09747950B2 |
Use of program-schedule text and closed-captioning text to facilitate selection of a portion of a media-program recording
In one aspect, an example method involves a computing device accessing first data representing a program schedule of a media program; accessing second data representing closed-captioning text of the media program; making a determination that first text of the program schedule has at least a threshold extent of similarity with second text of the closed-captioning text, where a portion of the media program was recorded proximate a time when a portion of the second data representing the second text of the closed-captioning text was generated; using the first text of the program schedule as a basis to select a portion of the program schedule; and responsive to at least the determination, storing third data indicative of a correlation between the selected portion of the program schedule and the recorded portion of the media program. |
| US09747942B2 |
Variable written track widths for attribute-based storage
A storage device controller is configured to select one of multiple written track widths for a storage location based on a write attribute of data to be recorded at the storage location. According to one implementation, the storage device controller is further configured to select a power level for a heat-assisted magnetic recording (HAMR) device based on the write attribute. |
| US09747941B2 |
Method for applying supplementary attribute information to E-book content and mobile device adapted thereto
A method that applies supplementary attribute information to the e-book content is provided. The method includes retrieving the e-book content; identifying objects in the retrieved e-book content; selecting one or more of the objects; defining one or more screen alteration attribute values regarding the selected objects; collecting an application condition for applying the defined screen alteration attribute values to the selected objects; and generating the supplementary attribute information by binding the defined screen alteration attribute values to the selected objects, and an action condition. |
| US09747937B1 |
Multi-purpose resistive sensor for a heat-assisted magnetic recording device
An apparatus comprises a slider having an air bearing surface (ABS) and a near-field transducer (NFT) at or near the ABS. An optical waveguide is configured to couple light from a laser source to the NFT. A resistive sensor comprises an ABS section situated at or proximate the ABS and a distal section extending away from the ABS to a location at least lateral of or behind the NFT. The resistive sensor is configured to detect changes in output optical power of the laser source and contact between the slider and a magnetic recording medium. |
| US09747936B1 |
Data storage device filtering sensor signal to optimize shock and thermal pop detection
A data storage device is disclosed comprising a head actuated over a disk, and a sensor configured to generate a sensor signal representing at least one of a shock and a thermal popping affecting the data storage device. The sensor signal is first filtered based on a first frequency range corresponding to the shock to generate a shock signal, and second filtered based on a second frequency range corresponding to the thermal popping to generate a pop signal, wherein the second frequency range is different from the first frequency range. The shock signal and the pop signal are individually processed, for example, to log a disturbance event, to abort a write operation, or to generate a feed-forward servo compensation signal. |
| US09747935B1 |
Heat assisted magnetic recording writer having pole coupled with the NFT
A heat assisted magnetic recording (HAMR) write apparatus has a media-facing surface (MFS) and is coupled with a laser that provides energy. The HAMR write apparatus includes a waveguide, a near-field transducer (NFT), a pole and coil(s) for energizing the pole. The waveguide is optically coupled with the laser and directs a first portion of the energy toward the MFS. The NFT is optically coupled with the waveguide. The pole writes to a region of the media and includes a pole tip. A first portion of the pole tip is at the MFS and is separated from the NFT in a down track direction. A second portion of the pole tip is recessed from the MFS and between the first portion and the NFT. |
| US09747932B1 |
Magnetic recording head and disk device comprising the same
According to one embodiment, a magnetic recording head includes an air bearing surface, a magnetic core including a main magnetic pole and a write shield arranged to face the main magnetic pole with a write gap, a coil, and a high-frequency oscillator provided between the main magnetic pole and the write shield in the write gap. The magnetic core includes an opposite surface facing a film surface of the high-frequency oscillator, a magnetic layer, and a nonmagnetic layer in which magnetic microparticles are dispersed. The nonmagnetic layer is provided outside the magnetic layer in at least a part of the opposite surface of the magnetic core. |
| US09747928B1 |
Data storage device modifying write operation when a laser mode hop is detected
A data storage device is disclosed comprising a first head actuated over a first disk surface, wherein the first head comprises a laser configured to heat the first disk surface while writing data to the first disk surface. A write power is applied to the laser when executing a first write operation, and the first write operation is paused when a transient increase in the output power of the laser is detected. In another embodiment, a write-verify of the written data is executed when a transient decrease in the output power of the laser is detected. |
| US09747926B2 |
Hotword recognition
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for receiving audio data corresponding to an utterance, determining that the audio data corresponds to a hotword, generating a hotword audio fingerprint of the audio data that is determined to correspond to the hotword, comparing the hotword audio fingerprint to one or more stored audio fingerprints of audio data that was previously determined to correspond to the hotword, detecting whether the hotword audio fingerprint matches a stored audio fingerprint of audio data that was previously determined to correspond to the hotword based on whether the comparison indicates a similarity between the hotword audio fingerprint and one of the one or more stored audio fingerprints that satisfies a predetermined threshold, and in response to detecting that the hotword audio fingerprint matches a stored audio fingerprint, disabling access to a computing device into which the utterance was spoken. |
| US09747924B2 |
Sound verification
In some examples, sound verification may include a speaker device that may be configured to transmit sound at a dynamic volume level and a listening device that may be configured to receive the sound and provide feedback to the speaker device based on the received sound. The primary transceiver device may be further configured to adjust the dynamic volume level based on the feedback provided by the secondary transceiver device. |
| US09747923B2 |
Voice audio rendering augmentation
An audio rendering device enhances voice audio such that audible voice is not overwhelmed by other aspects of the soundtrack. The device attenuates right and left channels in an audio stream in response to a detected voice component in the audio stream, and boosts the voice component in the audio stream based on the level of attenuation of the right and left channels. Voice components are distinguished from the non-voice components by separating center channel and mono information from the left, right and surround channels. Non-voice components are attenuated down towards a non-voice threshold level based on an attenuation ratio. Voice components are boosted up toward a voice threshold level, so that the spoken voice is more audible to viewers and not overwhelmed or drowned out by the non-voice aspects of the soundtrack. |
| US09747919B2 |
Sound processing apparatus and recording medium storing a sound processing program
A sound processing apparatus includes a first calculator that calculates first power based on a first signal received by a first microphone that is among the first microphone and a second microphone; a second calculator that calculates second power based on a second signal received by the second microphone; a gain calculator that calculates a gain on the basis of the ratio of the first power to the second power; and a multiplier that processes the second signal using the gain calculated by the gain calculator. |
| US09747915B2 |
Adaptive codebook gain control for speech coding
In accordance with one aspect of the invention, a selector supports the selection of a first encoding scheme or the second encoding scheme based upon the detection or absence of the triggering characteristic in the interval of the input speech signal. The first encoding scheme has a pitch pre-processing procedure for processing the input speech signal to form a revised speech signal biased toward an ideal voiced and stationary characteristic. The pre-processing procedure allows the encoder to fully capture the benefits of a bandwidth-efficient, long-term predictive procedure for a greater amount of speech components of an input speech signal than would otherwise be possible. In accordance with another aspect of the invention, the second encoding scheme entails a long-term prediction mode for encoding the pitch on a sub-frame by sub-frame basis. The long-term prediction mode is tailored to where the generally periodic component of the speech is generally not stationary or less than completely periodic and requires greater frequency of updates from the adaptive codebook to achieve a desired perceptual quality of the reproduced speech under a long-term predictive procedure. |
| US09747913B2 |
Apparatus and method determining weighting function for linear prediction coding coefficients quantization
An apparatus determining a weighting function for line prediction coding coefficients quantization converts a linear prediction coding (LPC) coefficient of an input signal into one of a line spectral frequency (LSF) coefficient and an immitance spectral frequency (ISF) coefficient and determines a weighting function associated with one of an importance of the ISF coefficient and importance of the LSF coefficient using one of the converted ISF coefficient and the converted LSF coefficient. |
| US09747912B2 |
Reuse of syntax element indicating quantization mode used in compressing vectors
In general, techniques are described for indicating reuse of a syntax element that indicates a quantization mode used when compressing a vector. A device comprising a processor and a memory may perform the techniques. The processor may be configured to obtain a bitstream comprising a vector in a spherical harmonics domain. The bitstream may further comprise an indicator for whether to reuse, from a previous frame, at least one syntax element indicative of a quantization mode used when compressing the vector. The memory may be configured to store the bitstream. |
| US09747907B2 |
Digital watermark detecting device, method, and program
According to an embodiment, a digital watermark detecting device includes a residual signal extractor, a voiced period estimator, a storage, a phase estimator, and a watermark determiner. The residual signal extractor is configured to extract a residual signal from a speech signal. The voiced period estimator is configured to estimate a voiced period based on the speech signal. The storage is configured to store pulse signals modulated in advance so as to have different phases. The phase estimator is configured to clip the voiced period in units of an analysis frame having a predetermined length, and perform pattern matching between the residual signal in the analysis frame and the pulse signals to estimate phase of the speech signal. The watermark determiner is configured to, based on a sequence of phases estimated by the phase estimator, determine whether a digital watermark is embedded in the speech signal or not. |
| US09747906B2 |
Determining media device activation based on frequency response analysis
Methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to determine media device activation based on frequency response analysis are disclosed. Example methods disclosed herein include determining a reference frequency response based on first frequency values of an audio signal used to perform watermark detection for a first time interval during which a media device has been determined to be active. Such example methods also include determining a second frequency response based on second frequency values of the audio signal used to perform watermark detection for a second time interval different from the first time interval. Such example methods further include comparing the second frequency response with the reference frequency response to determine whether the media device was active during the second time interval. |
| US09747900B2 |
Method and apparatus for using image data to aid voice recognition
A device performs a method for using image data to aid voice recognition. The method includes the device capturing image data of a vicinity of the device and adjusting, based on the image data, a set of parameters for voice recognition performed by the device. The set of parameters for the device performing voice recognition include, but are not limited to: a trigger threshold of a trigger for voice recognition; a set of beamforming parameters; a database for voice recognition; and/or an algorithm for voice recognition, wherein the algorithm can include using noise suppression or using acoustic beamforming. |
| US09747893B2 |
Unsupervised training method, training apparatus, and training program for an N-gram language model based upon recognition reliability
A computer-based, unsupervised training method for an N-gram language model includes reading, by a computer, recognition results obtained as a result of speech recognition of speech data; acquiring, by the computer, a reliability for each of the read recognition results; referring, by the computer, to the recognition result and the acquired reliability to select an N-gram entry; and training, by the computer, the N-gram language model about selected one of more of the N-gram entries using all recognition results. |
| US09747890B2 |
System and method of automated evaluation of transcription quality
Systems and methods automatedly evaluate a transcription quality. Audio data is obtained. The audio data is segmented into a plurality of utterances with a voice activity detector operating on a computer processor. The plurality of utterances are transcribed into at least one word lattice with a large vocabulary continuous speech recognition system operating on the processor. A minimum Bayes risk decoder is applied to the at least one word lattice to create at least one confusion network. At least conformity ratio is calculated from the at least one confusion network. |
| US09747889B2 |
Reverberant sound adding apparatus, reverberant sound adding method, and reverberant sound adding program
A reverberant sound adding apparatus includes a noise generator configured to generate a noise, an impulse noise generator configured to generate an impulse noise comprising an impulse sequence with random time intervals, an addition noise generator configured to generate an addition noise by adding the noise to the impulse noise, an impulse response generator configured to generate a modified impulse response by multiplying the addition noise by an amplitude characteristic of an impulse response that indicates acoustic characteristics of a space, and an impulse response convolver configured to convolve an input audio signal with the modified impulse response. |
| US09747886B2 |
Method for cancelling noise of audio signal and electronic device thereof
An apparatus and method for cancelling a noise of an audio signal in an electronic device are provided. The electronic device includes a communication module configured to provide a voice call service with a counterpart electronic device, a memory configured to store one or more noise cancellation variables, and a processor configured to, when a call with the counterpart electronic device is configured through the communication module, select a noise cancellation variable corresponding to a reception signal strength from the memory and cancel an audio signal noise based on a noise cancellation variable corresponding to the reception signal. |
| US09747883B2 |
Acoustic insulator mat with liquid applied sprayable coating and method for making the same
The disclosed acoustic insulator mat includes a first absorber layer made of a non-woven fibrous material. The non-woven fibrous material comprises a mesh of intertwined fibers that defines a plurality of cavities. The first absorber layer has a first side and a second side. Peripheral cavities are arranged along the second side of the first absorber layer between peripheral fibers. A coating is disposed on the second side of the first absorber layer. The coating is adhered to the peripheral fibers and thus includes a plurality of discontinuities at the peripheral cavities such that the coating provides a partial barrier to noise at the second side of the first absorber layer. The acoustic insulator mat may optionally include a second absorber layer that is retained on the first absorber layer by the coating. A method of manufacturing the acoustic insulator mat is also disclosed. |
| US09747881B2 |
Beat detection and enhancement
A system encourages experimentation with audio frequency and speaker technologies while causing an inanimate figure to appear to dance. The system applies a bandpass filter to an incoming audio stream (e.g., in a low frequency bass band). The system monitors the magnitude of the audio content in a frequency band of interest. When an amplitude peak or other threshold magnitude is detected, a controller injects a short pulse (e.g., 3 cycles) of a sub-audible low frequency sine wave to a platform. Preferably, the sub-audible low frequency sine wave is at a resonance frequency of the platform to maximize its movement. The figure is positioned on the platform and appears to dance to the beat of the music. |
| US09747874B2 |
Electronic guitar pick and method
An electronic guitar pick, system, system and method may include an enclosure forming a cavity, the enclosure having a first end that is substantially pointed and a second end opposite the first end that is substantially flat, the enclosure having a thickness proximate the cavity greater than a thickness proximate the first end. The electronic guitar pick, system, and method may further include a sensor contained, at least in part, within the cavity and configured to generate a sensor output based on an interaction with the enclosure and a sensory output device, communicatively coupled to the sensor, configured to output a sensory output based, at least in part, on the sensor output. |
| US09747863B2 |
Method for combined transformation of the scale and aspect ratio of a picture
A source image is transformed into a destination image having a target aspect ratio. A reference region in the source image is defined. An extended region of interest of the source image having the target aspect ratio and containing the reference region is defined. A set of candidate image regions of increasing resolutions from the extended region of interest is determined, each having the target aspect ratio and containing the reference region. Candidate image regions are scaled to form a candidate target images. A quality metric is used to select a target image providing the best quality metric value. |
| US09747862B2 |
Method of immersive rendering for wide field of view
A method, apparatus, and system is presented by which images of virtual objects displayed in augmented reality systems, virtual reality systems, or immersive display systems for realistic rendering of wide field of view, may be corrected to provide for reduction of registration errors regarding real objects or locations. |
| US09747860B2 |
Method of driving display panel and display apparatus for performing the same
A method of driving a display panel includes generating a high data voltage having a high gamma corresponding to a grayscale of input image data, generating a low data voltage having a low gamma less than the high gamma corresponding to the grayscale of the input image data and outputting the high data voltage and the low data voltage to pixels of a display panel. Of the high data voltage and the low data voltage, only the low data voltage is outputted to the pixels of the display panel during at least one frame. |
| US09747852B2 |
Method for driving liquid crystal display device
The liquid crystal display device includes a first substrate provided with a terminal portion, a switching transistor, a driver circuit portion, and a pixel circuit portion including a pixel transistor and a plurality of pixels, a second substrate provided with a common electrode electrically connected to the terminal portion through the switching transistor, and liquid crystal between a pixel electrode and the common electrode. In a period during which a still image is switched to a moving image, the following steps are sequentially performed: a first step of supplying the common potential to the common electrode; a second step of supplying a power supply voltage to the driver circuit portion; a third step of supplying a clock signal to the driver circuit portion; and a fourth step of supplying a start pulse signal to the driver circuit portion. |
| US09747851B2 |
Compensation method of Mura phenomenon
The present invention provides a compensation method of Mura phenomenon. By dividing the LCD display panel into a plurality of display partitions, and selecting a pre-selected pixel dot of a determined position in each display partition and obtaining gray scale compensation data thereof at the respectively selected gray scales, and then, calculating the respective interpolation coefficients of the requested pixel dots in the corresponding display partitions, the compensation data of partial pixel dots in the respective gray scales and the respective interpolation coefficients of the requested pixel dots can be utilized to calculate the gray scale compensation data of all pixel dots in all gray scales. The calculation difficulty is reduced to lower the computation. The consumption of the hardware storage space is decreased and the Mura compensation result can be ensured. The time and effort can be saved and it can be simple and quick. |