| Document | Document Title |
|---|---|
| US09712518B2 |
Apparatus used for security information interaction
The invention provides an apparatus used for security information interaction comprising a first system management device for providing an operational environment for routine applications and a second system management device for providing an operational environment in a safe mode for security applications so as to perform a security information interaction process. The apparatus used for security information interaction disclosed by the invention has a high safety and a wide applicability and is low in cost. |
| US09712514B2 |
Super-session access to multiple target services
A method of establishing privileged communication sessions to target services unifies multiple sub-sessions into a single super-session. The user client requests access to target services. The request includes authentication credentials. Using the authentication credentials, privileged credentials are retrieved for target services requiring privileged access. Interactive sub-sessions are established between an intermediate element and respective target services. Required credentials are provided by the intermediate element to the target services. The interactive sub-sessions are unified into a single super-session on the intermediate element, and the super-session is established with the user client. The super-session provides the user client with interactive control of each of the interactive sub-sessions. Data communication between the user client and the target services is conducted via the intermediate element. |
| US09712511B2 |
Mobile cloud service architecture
Techniques are described for implementing a cloud computer system to facilitate communication between a computing device (e.g., a mobile computing device) and enterprise computer systems. In certain embodiments, the cloud computer system may receive, from a computing device, a request for a service provided by an enterprise computer system. The cloud computer system may determine security authentication of a user for the requested service. A security protocol may be determined for a requested enterprise computer system and a security token may be generated for the request according to the determined security protocol. The request may be sent to the requested enterprise computer system. In some embodiments, security authentication for a request to an enterprise computer system may be determined based on previous authentication. The cloud computer system may be configured to communicate with several different enterprise computer systems according to their supported protocols (e.g., communication protocol and/or security protocol). |
| US09712510B2 |
Systems and methods for securely submitting comments among users via external messaging applications in a cloud-based platform
Systems and methods are disclosed for facilitating secure commenting on content items among collaborators via external messaging applications in a collaborative cloud-based environment. In one embodiment, the system receives a response to a notification associated with a content item from a collaborator via an external messaging application. The response can include a text-based comment associated with the content item and secure message information provided by the notification including a message and a message authentication code. The system then determines a validity of the response. The validity of the response can include verifying the integrity of the message using the message authentication code. |
| US09712506B2 |
Methods, apparatuses, system and computer programs for key update
It is disclosed a method comprising monitoring validity of limited-validity key information, acquiring, from a network entity upon invalidity of the limited-validity key information, limited-validity transaction identification information based on unlimited-validity identification information identifying a terminal, generating new limited-validity key information based on the acquired limited-validity transaction identification information, and transmitting the acquired limited-validity transaction identification information to a network element. |
| US09712500B2 |
Distributed computing utilizing homomorphic encryption
A method for determining a compute amount contributed by a device is provided. The method comprises receiving encrypted data from a processor of a customer system and parsing the encrypted data into a plurality of encrypted subsets. Then, the method associates a token specific to the device with an encrypted subset of the plurality of encrypted subsets to produce a packaged subset. The packaged subset is sent to the device. In response, a processed packaged subset that includes the token is received. The compute time contributed by the device is determined from the token of the processed packaged subset. |
| US09712498B2 |
Systems and devices for encrypting, converting and interacting with medical images
A network device and a peripheral device for attachment with a medical imaging device provides for the encryption and conversion of a medical image into a secure and standardized image file format as well as the communication of the encrypted and/or converted image to a secure server on a remote network. The devices may monitor all medical image files generated on the medical imaging device and encrypt and convert selected medical image files for transmission to a remotely connected device on another network, such as a server or a mobile device. An encryption and conversion unit may be incorporated within the hardware and software of a medical imaging device or another network device in order to provide the capability for encrypting a medical image for transmission to a remote network and for converting the medical image to a format that is compatible with a destination device or network. |
| US09712490B1 |
Identifying applications for intrusion detection systems
An intrusion detection system (“IDS”) device is described that includes a flow analysis module to receive a first packet flow from a client and to receive a second packet flow from a server. The IDS includes a forwarding component to send the first packet flow to the server and the second packet flow to the client and a stateful inspection engine to apply one or more sets of patterns to the first packet flow to determine whether the first packet flow represents a network attack. The IDS also includes an application identification module to perform an initial identification of a type of software application and communication protocol associated with the first packet flow and to reevaluate the identification of the type of software application and protocol according to the second packet flow. The IDS may help eliminate false positive and false negative attack identifications. |
| US09712489B2 |
Client device address assignment following authentication
Methods and systems are described for assigning the proper internet protocol (IP) address to a client device following authentication of the client device on a network. In particular, at commencement of an authentication procedure of the client device, a role is associated with the client device that denies all DHCP renews/requests. By assigning a role to the client device 103 with a “deny DHCP renew/request” rule at the commencement of an authentication procedure, the systems and methods described herein ensure that a race condition does not allow the client device to renew an IP address in an old segment of the network. Accordingly, the client device may avoid a possibly improper IP address in a segment of the network system in which the client device is no longer associated with or operating on. |
| US09712486B2 |
Techniques for the deployment and management of network connected devices
A method, system, and computer program product for Internet of Things (IoT) network-connected devices. Embodiments include methods and systems for registering one or more listener devices (e.g., mobile phones or tablets, etc.) to receive messages from one or more notification devices (e.g., web cameras, etc.). A notification server is selected from among multiple notification servers to receive notification messages from the notification devices and then to forward (e.g., through a push service, etc.) portions of or variations of the notification messages to the listener devices. In some embodiments, the selection of the notification server is based on load balancing between the multiple notification servers and/or push servers. In some embodiments, the selection of a notification server and/or push server is based on a provisioning file. |
| US09712485B2 |
Dynamic DNS-based service discovery
Techniques are provided for performing dynamic DNS-SD. In an embodiment, an apparatus includes one or more databases, one or more transceivers to receive a first Domain Name System (DNS) query from a first computing device, the first DNS query defining a first service discovery name space, and one or more processors in communication with each of the one or more databases and the one or more transceivers. The one or more processors generate and append a first metadata associated with the first computing device to the first DNS query. The one or more transceivers transmit the first DNS query and the first metadata to a Domain Name System (DNS) server computer, receive, from the DNS server computer, a first response responsive to the first DNS query, and relay, to the first computing device, the first response. |
| US09712480B2 |
Apparatus and method for requesting and transferring contents
Disclosed are an apparatus and method enabling a user to efficiently share contents. A user of an electronic device performs an image capturing by use of a camera, thereby generating an image capture event. According to the image capture event, the electronic device obtains address information of a content transferring apparatus and transfers a content requesting message to the content transferring apparatus having the address information. Upon reception of the content requesting message, the content transferring apparatus provides the electronic device with contents in execution and status information of the content. The electronic device uses the content and the status information to restore a status of the content which has been executed in the content transferring apparatus. |
| US09712473B2 |
Methods, systems, and user interfaces for community-based location ratings
Methods, system, and user interfaces for providing a user interface enabling community-based map functionalities for users of a social networking system are described. One method includes providing a user interface (UI) that includes a geographic map portion and a rating portion. The geographic map portion depicts a geographic area and includes a set of location identifiers, and the rating portion includes a set of rating list elements. Each rating list element includes a rating input UI element allowing the user to rate a location that the social networking system has determined that the user has visited. The method also includes receiving a first rating for a first location, which is generated through use of the rating portion. The method further includes, responsive to said receiving of the first rating, modifying the user interface to indicate that the first rating was received. |
| US09712467B2 |
Iterative method to successfully send large electronic messages
Iterative techniques for successfully sending large electronic messages are provided. In one aspect, a method of sending an electronic message is provided. The method includes the steps of: transmitting the electronic message from a sender to a recipient, wherein a size of the electronic message exceeds an electronic message size limit for the recipient; receiving a message from the recipient that the size of the electronic message exceeds the electronic message size limit for the recipient; automatically dividing the electronic message into at least two segments; and transmitting the at least two segments to the recipient. Additionally, the recipient's preferences for receiving large electronic messages from the sender may also be taken into account. |
| US09712465B2 |
Coaching with collaborative editing
A method has acts for coupling from a computerized server executing software on a processor from a non-transitory medium to two or more computerized appliances operated by persons in a contact center, and updating text composition and editing results in real time in a display of each of the computerized appliances as any person operating a coupled computerized appliance composes or edits in a text-based communication application. |
| US09712464B2 |
Multichannel gateway, multiplex transmission line communication system, multiplex transmission line communication method and computer-readable recording medium storing program
A multichannel gateway is provided such that a line manager detects the lines status and updates line information in a memory. A packet acquirer acquires a packet for transmission from a terminal, and a segmentation necessity determiner calculates a packet sizes (segment sizes) based on the line information so that if the packet is segmented and transmitted to each line, the transmission time will be the same. When the segmentation necessity determiner determines based on the segment sizes that segmentation of the packet is necessary, a packet divider segments the packet into the segments, attaches a header and generates transmission packets. A packet transmitter transmits the transmission packets by way of the corresponding lines to other terminals. A packet combiner removes the headers from the transmission packets received by a packet receiver and combines the packets in the received order. |
| US09712459B1 |
Low-to-high speed cut-through communication
This disclosure describes techniques and apparatuses enabling low-to-high speed cut-through communication without creating an overrun condition. By so doing, the techniques and/or apparatuses enable communication interfaces to communicate at higher speed, such as by avoiding store-to-forward latency. |
| US09712457B2 |
Server directed client originated search aggregator
A system for automated aggregation of search results provided in response to search queries/requests to multiple network resources is provided. The search requests are originated by client devices, at the direction of a server, to the various network resources. A user, using a client device, enters a search request that is provided to the server. The search request may include one or more search terms. The server identifies which network resources, out of a set of available network resources, are likely to provide relevant results to the user's query. The server may modify the search request to increase the likelihood that the search request will return relevant results. The identified list of resources is then provided back to the client device, along with the modified search request if applicable, which then originates and transmits the search request to each of the identified resources or subset thereof. |
| US09712456B2 |
Live partition mobility with shared persistent reservations
According to one embodiment of the present invention, a method is provided. The method may include a computer registering a first instance of a logical partition on a source server with a logical unit and placing a first persistent reservation on the logical unit, wherein the first persistent reservation indicates that only the first instance of the logical partition can hold a reservation on the logical unit. The method may further include the computer registering a second instance of the logical partition on a destination server with the logical unit and downgrading the first persistent reservation, such that the first and second instances of the logical partition can hold persistent reservations on the logical unit. The method may further include the computer placing, by one or more computer processors, a second persistent reservation on the logical unit. |
| US09712454B2 |
Method and system for provisioning computing resources
A method, computer-readable medium, and system for provisioning computing resources across multiple cloud providers and/or data centers are disclosed. A graphical user interface is used to select a plurality of computing resources and at least one cloud provider and/or at least one data center for providing the plurality of computing resources. Scripts associated with the at least one cloud provider and/or at least one data center are accessed, where each script is capable of automatically setting up a computing resource on an associated cloud provider or associated data center. The scripts are then used to automatically allocate and/or configure the computing resources on the at least one cloud provider and/or at least one data center. As such, computing resources can be automatically provisioned using a generic graphical user interface and without a user having skills or credentials specific to each cloud provider and/or data center. |
| US09712452B2 |
System and methods for improving support of a virtual subscriber identity module (SIM) in a multi-SIM wireless communication device
Methods and devices for scheduling data packet transmissions on a multi-subscriber identity module (SIM) wireless communication device having at least a first SIM and a virtual SIM (VSIM) application associated with a shared radio frequency (RF) resource may include detecting registration of a SIM profile for the VSIM application, in which the VSIM application is provisioned to operate as a VSIM, and determining whether a VSIM management procedure is required for the VSIM. When a VSIM management procedure is required for the VSIM, the wireless communication device may tag data packets associated with the required VSIM management procedure, select a prioritization policy for data packet transmissions on the RF resource, and apply the selected prioritization policy within a transmission queue on the RF resource. |
| US09712447B2 |
Point-to-multipoint path computation for wide area network optimization
In some examples, a controller for a network includes a path computation module configured for execution by one or more processors to obtain configuration information for at least one point-to-multipoint label switched path (P2MP LSP); obtain, from the network via at least one protocol, network topology information defining a network topology for the network; determine, based on the network topology, a first solution comprising first respective paths through the network for the at least one P2MP LSP; determine, after generating a modified network topology based on the network topology, a second solution comprising second respective paths through the network for the at least one P2MP LSP. The controller also includes a path provisioning module configured for execution by the one or more processors to configure the network with the solution of the first solution and the second solution having the lowest total cost. |
| US09712440B2 |
Connectivity system for multi-tenant access networks
A system may provide connectivity service in a multi-tenant network. A first node in the multi-tenant network can receive data packets, each of the data packets identifying one of a plurality of tenant devices. The first node can determine an Internet Protocol (IP) address associated with each of the data packets. The first node can determine a Virtual Local Area Network Identifier (VLAN ID) based on the IP address, the VLAN ID being a unique identifier of a respective one of the tenants. The first node can add the VLAN ID of a corresponding one of the tenants into a header of each of the data packets. The first node can transport the data packets to a second node in the multi-tenant network via a multi-tenant network tunnel protocol. |
| US09712437B2 |
Transmitting data
Apparatus has at least one processor and at least one memory having computer-readable code stored therein which when executed controls the at least one processor to perform a method comprising: causing each of first and second transmitter interfaces to transmit data over a respective communications path including one or more logical connections; and causing each of first and second transmission parameter calculating modules, associated respectively with the first and second transmitter interfaces, to perform: monitoring the transmission of data over its respective communications path, using results of monitoring the transmission of data over its respective communications path to calculate a path speed value for transmitting data over its respective communications path, and causing the path speed value to be used in the transmission of data over its respective communications path. |
| US09712433B2 |
Maintaining and communicating nodal neighboring information
In one embodiment, a nodal device receives information from each of its neighboring nodes in a network. The information identifies a link quality between the nodal device and each of its neighboring nodes. The link quality information is stored in one or more bloom filters in the nodal device such that a table having a compressed format is provided in the bloom filter. The table includes probabilistic identifiers to identify link quality between the nodal device and each of its neighboring nodes. |
| US09712431B2 |
Methods for managing transaction in software defined network
Disclosed are methods for managing transactions in a software defined network (SDN). A method performed in a controller may comprise generating a group message for modifying flow entries of a plurality of flow tables related to each other in a switch; and transmitting the group message to the switch. Thus, a plurality of flow tables having relevance to each other can be simultaneously modified so that modifications on a plurality of switches can be synchronized, and consistency of them can be guaranteed. |
| US09712429B1 |
System and method for unmarshalled routing
In distributed object computing, messages from a source node to a destination node are often required to be routed via one or more intermediate nodes. In order to enhance efficiency of the relay process, a message envelope of a message may include a node list field that specifies the routing path of the message. The communication protocol for communicating the message may specify that when a message is received into a particular node, the node analyzes the node list field. If the identity of the node is last in the node list field, then the node is the destination node and thus the node unmarshals the message. Otherwise, the node forwards the message to the next node in the field list without unmarshalling the message. |
| US09712428B2 |
Wireless terminal device, method for generating number of alternative paths, and wireless communication system
A wireless terminal device includes a transmitter configured to receive a first packet including path information and a first number of paths of each path and a second packet including a second number of paths between a transmission origin wireless terminal device and a destination wireless terminal device, which is sent from the transmission origin wireless terminal device, and a processor configured to multiply the first number of the paths between an own wireless terminal device and the transmission origin wireless terminal device with another first number of paths between the own wireless terminal device and the destination wireless terminal device and calculate a number of alternative paths of the own wireless terminal device by subtracting the multiplied value from the second number of the paths which is received. |
| US09712426B2 |
Multi-domain routing computation method and device, path computation element and routing network
Disclosed is a multi-domain routing computation method, including: when it is determined that there are two or more domains deployed with a Path Computation Elements (PCE) in a network, a routing path is computed, between a PCE of a first domain and a PCE of a last domain among the two or more domains deployed with a PCE, using an extended Backward-Recursive PCE-Based Computation (BRPC) algorithm, and the routing path is computed using a Routing Controller (RC) in domains other than the two or more domains deployed with a PCE. Further disclosed are a multi-domain routing computation device, a path computation element and a routing network. The present disclosure can improve greatly optimality of path computation and has a fairly high efficiency for the path computation. |
| US09712422B2 |
Selection of service nodes for provision of services
Methods and apparatus are disclosed for enabling selection of a remote service node from a plurality of possible nodes, each capable of providing a service, and each associated with a service node control entity. The method comprises: receiving a user request in respect of a service required by a user, the request containing a first user device routing identifier relating to the location in the network of the user device, and a service indication indicative of an appropriate service provider; identifying from the service indication a service node control entity associated with the service provider; sending to the service node control entity a service node request containing a second user device routing identifier differing from the first user device routing identifier but selected at least partly in dependence thereon; receiving from the service node control entity an indication of a remote service node capable of providing the required service; and providing an indication of the remote service node to the user device. |
| US09712420B2 |
Method and medium for implicit relationship discovery based on cumulative co-temporal activity
Implied relationships between entities, such as network endpoints, are automatically discovered based on co-temporal events. Events involving pairs of endpoints, such as messaging events in which one endpoint acts as a source and another endpoint acts as a destination, may be detected. Edges between nodes representing those endpoints and other nodes representing other endpoints involved in other recent (co-temporal) events may be added to a progressively constructed graph. Over time, such edges may be progressively weighted in response to the detection of further co-temporal events involving the same endpoints. Relationships between endpoints may be implied based on the resulting accumulated weights of edges linking those endpoints' nodes in the graph even if there is no express relationship between those endpoints in any real-word context (e.g., even if those endpoints are not directly connected in any network, and even if no single event involves both of those endpoints together). |
| US09712418B2 |
Automated network control
Embodiments are directed to automatically controlling network and service quality across datacenters. In one scenario, a computer system identifies portions of work that are to be performed within the datacenter. The computer system creates a request for change (request) in a change management system, where the change management system is configured to store and manage the implementation of requests within the datacenter. Then, upon implementation of the created request, the computer system polls the status of the request to determine whether the portions of work identified in the request can now be performed and, upon determining that the portions of work identified in the request can be performed, the computer system performs the portions of work according to the request. Performance of the specified work according to a request allows for workflows to be controlled based on the request. |
| US09712411B2 |
Progressive deployment and termination of canary instances for software analysis
A data processing method, comprising: using computing apparatus, causing instantiating a plurality of baseline application instances that are running a first version of software, and one or more canary application instances that are running a second version of the software; using computing apparatus including a load balancer, causing selectively routing a first proportion of incoming requests to the baseline instances, and routing a second proportion of the incoming requests to the canary instances; monitoring the plurality of canary instances to collect performance data for performance metrics; determining that the performance data indicates a negative performance issue, and in response thereto: using computing apparatus, automatically updating the first proportion to be larger and updating the second proportion to be smaller, and then reconfiguring the load balancer based upon the first proportion and the second proportion; terminating one or more of the canary application instances. |
| US09712410B1 |
Local metrics in a service provider environment
Technology for provision and use of local metrics in a multi-tenant service provider environment is provided. In one example, a method may include receiving service provider environment metrics from a computing instance and receiving local metrics from a local machine in a multi-tenant service provider environment. The local metrics may be combined with the service provider environment metrics and provided for display together. |
| US09712407B2 |
Hierarchical temporal clustering, metric clustering and attribute clustering of electronic terminal reports to identify electronic terminals for analysis
A method of performing operations on a processor of an application analysis computer includes obtaining reports from electronic terminals. The reports contain metrics for operation of instances of an application processed by the electronic terminals and attributes of the electronic terminals characterizing their application processing platforms. Metrics clusters of the reports are generated based on the metrics. Attribute clusters of the reports are generated based on the attributes contained in the reports of one of the metrics clusters which satisfy a defined metric rule. One of the attribute clusters, which contains reports obtained from less than a threshold number of distinct electronic terminals, is identified. Identifiers of the electronic terminals are determined based on the attributes contained in the reports in the one of the attribute clusters. Information is communicated based on the identifiers of the electronic terminals. |
| US09712406B2 |
Method and apparatus for analyzing and verifying functionality of multiple network devices
A network device test station (“TS”) is capable of simultaneously testing and verifying a group of routers and/or switches at the same time. The TS includes a user interface (“UI”), a test bed engine, and a TS manager. The UI facilitates interactive communication between TS and user via an interactive graphical representations showing, for example, test configurations and test results. The test bed engine uses a set of test beds to conduct tests on attached devices or routers which are also known as device under tests (“DUTs”) or unit under tests (“UUTs”). The TS manager is configured to provide a test environment with one or more emulated communication networks for verifying functionalities of every DUT. |
| US09712397B2 |
Method for gathering traffic analytics data about a communication network
There is provided a method for gathering traffic analytics data about a communication network that includes applying a heuristic that focuses on specific attributes of the communications relationships between the system assets of a network. |
| US09712393B2 |
Network loop prevention
Systems, methods and computer readable media for network loop detection and prevention are described. Some implementations can include a computerized method comprising detecting, at a first switch, a loop condition in a network, and generating, at the first switch, a localize loop message having an instance count and a path list. The method can also include setting, at the first switch, the instance count of the localize loop message to a first value, and transmitting, from the first switch, the localize loop message to a second switch. The method can further include detecting, at the second switch, a loop in the network; and sending, from the second switch, a localize loop response message to the first switch. |
| US09712390B2 |
Encoding traffic classification information for networking configuration
Methods and apparatus for encoding traffic classification information for a networking configuration system are disclosed. At a networking configuration server, a hierarchy of network traffic categories and corresponding networking configuration options are generated. In addition, steps of a procedure usable to classify network traffic units into the categories are determined. Data structures to represent the hierarchy and the procedure are constructed at the networking configuration server and provided to a computing device of a distributed system to be used to schedule network transmissions. |
| US09712387B2 |
Method and system for content aggregation via a broadband gateway
A broadband gateway, which enables communication with a plurality of devices, handles at least one physical layer connection to at least one corresponding network access service provider. The broadband gateway determines network channel conditions for a requested service and identifies a user profile for a requesting device. The broadband gateway negotiates a service profile for the requested service with the at least one network access service provider based on the determined network conditions and the identified user profile. Content may be acquired and received for the requested service from the at least one network access service provider utilizing the negotiated service profile. The broadband gateway aggregates and assembles the received content. The resulting assembled content is communicated to the requesting device for the requested service. The broadband gateway may relay content among peer devices. Content conversion may be performed during the relay communication to match user profiles of subsequent peer devices. |
| US09712386B1 |
Grouping routing resources for isolated virtual network traffic management
A connectivity manager (CM) of a provider network establishes a plurality of ERGs (edge resource groups), each comprising at least an edge router and a network marker translation agent (NMTA). The CM selects a particular ERG to be used for network traffic between a first set of resources of a virtual computing service of the provider network and a second set of resources outside the provider network. To enable connectivity between the first and second set of resources, the CM initiate propagation of (a) routing metadata to an edge router of the particular ERG and/or (b) a network marker mapping entry to an NMTA of the particular ERG. |
| US09712382B2 |
Retrieving console messages after device failure
A service controller of a computing device can store console messages so that an external management device can retrieve the console messages after a malfunction or crash of the computing device. For example, the service controller can be configured to redirect serial output (e.g., console messages, system log messages, system error message, etc.) to a network interface controller for transmission over a network connection. The service controller can be configured to store the console messages in non-volatile memory of the service controller. The service controller can receive a request for the stored console messages and transmit the stored console messages to an external device. |
| US09712367B2 |
Radio communications system and method with increased transmission capacity based on frequency twisted waves
A method of implementing Orbital Angular Momentum (OAM) for radio communications in general and LTE in particular. Common prior art so far recreate the vorticity (axial rotation of the Poynting vector) by using ring-shaped antenna arrays. This application proposes to create the vorticity in signal processing without the need of any space diversity (i.e. work with a single antenna). An Hilbert transform is applied in frequency domain to the Fourier transform of the analytical representation of a band-limited OFDM signal. The Hilbert transform is then approximated by a development in series into orthogonal twisted modes. This can be seen as an inverse Fourier transform of the complex analytical signal. Therefore an OAM IFFT based transmitter is proposed where parallel IFFTs are performed for each OAM mode and superimposed. |
| US09712366B2 |
Data receiving method and receiver
A data receiving method and receiver are provided. A receiver determines the length of a pre-tail and the length of a post-tail of a frame by obtaining a start time and an end time of the main part of the signal of the frame at a fixed time, and determines a start time and an end time of a frame receiving window according to the start time and the end time of the main part of the signal of the frame and according to the length of the pre-tail and the length of the post-tail; and receiving a frame between the start time and the end time of the frame receiving window, so that the receiver can accurately and completely receive the main part of the signal and the pre-tail and post-tail of each frame to accurately and completely receive signals. |
| US09712364B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
A method and an apparatus for transmitting broadcast signals thereof are disclosed. The apparatus for transmitting broadcast signals, the apparatus comprises an encoder for encoding service data corresponding to each of a plurality of data transmission path, wherein each of the data transmission path carries at least one service component, an encoder for encoding signaling data, a frame builder for building at least one signal frame including the encoded service data, a modulator for modulating the at least one signal frame by an OFDM (Orthogonal Frequency Division Multiplex) scheme and a transmitter for transmitting the broadcast signals carrying the at least one modulated signal frame. |
| US09712363B2 |
Transmitting circuit, transceiver, communication system, and method for transmitting data
A transmitting circuit, a transceiver, a communication system, and a method for transmitting data. The transmitting circuit includes a digital interface circuit configured to obtain, in a predetermined bandwidth, data to be sent, and decompose the data into N parallel sub digital signal flows; a digital modulation circuit configured to modulate the N sub digital signal flows to obtain N modulated signals; a frequency relocation circuit configured to perform frequency relocation on the N modulated signals; a synthesizer configured to modulate M modulated signals of the N modulated signals that have undergone frequency relocation into a bandwidth signal; a digital to analog converter configured to receive the bandwidth signal, and perform digital to analog conversion on the bandwidth signal to obtain an analog signal; an up-conversion circuit configured to receive the analog signal, and convert the analog signal into a radio frequency signal. |
| US09712358B2 |
Range extension mode for WiFi
A method for generating a physical layer (PHY) data unit for transmission via a communication channel is described where the PHY data unit conforms to a first communication protocol. Orthogonal frequency division multiplexing (OFDM) symbols for a data field of the PHY data unit are generated according to a range extension coding scheme that corresponds to a range extension mode of the first communication protocol. A preamble of the PHY data unit is generated, the preamble having i) a first portion that indicates a duration of the PHY data unit and ii) a second portion that indicates whether at least some OFDM symbols of the data field are generated according to the range extension coding scheme. The first portion of the preamble is formatted such that the first portion of the preamble is decodable by a receiver device that conforms to a second communication protocol, but does not conform to the first communication protocol, to determine the duration of the PHY data unit based on the first portion of the preamble. The PHY data unit is generated to include the preamble and the data field. |
| US09712354B2 |
Modulation and equalization in an orthonormal time-frequency shifting communications system
A method of receiving data including receiving, on one or more carrier waveforms, signals representing a plurality of data elements of an original data frame wherein each of the data elements are represented by cyclically time shifted and cyclically frequency shifted versions of a known set of waveforms. The method further includes generating, based upon the signals, a received data frame and generating an equalized data frame by performing an equalization operation using elements of the received data frame, the equalization operation correcting for distortion introduced into the signals during propagation of the carrier waveforms through a channel. |
| US09712353B2 |
Data transmission between asynchronous environments
A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency. |
| US09712350B2 |
Transmission device with channel equalization and control and methods for use therewith
Aspects of the subject disclosure may include, for example, a transmission device that includes at least one transceiver configured to modulate data to generate a plurality of first electromagnetic waves in accordance with channel control parameters. A plurality of couplers are configured to couple at least a portion of the plurality of first electromagnetic waves to a transmission medium, wherein the plurality of couplers generate a plurality of second electromagnetic waves that propagate along the outer surface of the transmission medium. A training controller is configured to generate the channel control parameters based on channel state information received from at least one remote transmission device. Other embodiments are disclosed. |
| US09712346B2 |
Continuous phase modulation method and emitter implementing said method
A continuous phase modulation method comprises the following steps: receiving a sequence of digital data symbols a(n) to be emitted; transforming the sequence of symbols a(n) to be emitted into a transformed sequence of symbols b(n), each symbol b(n) of which is equal to the sum of a symbol a(n) to be emitted and of a corrective factor equal to a transformation Tf applied to a plurality of differences (a(n)-a(n−1)) between two consecutive symbols to be emitted, the transformation Tf applied being a combination c of at least two differences between two consecutive symbols of the sequence to be emitted, transformed by the application of a non-linear function f; filtering the sequence of transformed symbols b(n) with a shaping filter and modulating the filtered sequence with a phase modulator; said transformation Tf being defined so as to minimize interference between modulated symbols filtered by a receiving filter. |
| US09712341B2 |
Methods, systems, and computer readable media for providing E.164 number mapping (ENUM) translation at a bearer independent call control (BICC) and/or session intiation protocol (SIP) router
The subject matter described herein includes methods, systems and computer readable media for providing E.164 number mapping (ENUM) translation at a bearer independent call control (BICC) and/or session initiation protocol (SIP) router. One aspect of the subject matter described herein includes a system for providing ENUM translation. The system includes an ENUM database. The system also includes a signaling router for receiving a bearer independent call control (BICC) signaling message that includes a first call party identifier, for obtaining, from the ENUM database, a first SIP address associated with the first call party identifier, for generating a first SIP signaling message that includes the first SIP address, and for routing the first SIP signaling message to a destination SIP node. |
| US09712336B2 |
Communication apparatus, communication method, computer program, and communication system
Even when the lengths of data items to be transmitted to users are not the same, the frames multiplexed at the same time finally have the same frame length and are transmitted.Even when the lengths of frames for the users are not the same at the time when a transmission request is received from a higher layer, a communication apparatus reconfigures at least two of the frames having short lengths into a frame having a long length through Aggregation so that the frames finally have the same frame length and transmits the frames at the same time in a multiplexed manner. On the transmitter side, the transmission power used per destination communication station can be increased due to a decrease in the total number of multiplexed frames. On the receiver side, an unstable AGC operation can be prevented. |
| US09712331B1 |
Systems and methods for performing conflict resolution and rule determination in a policy realization framework
Various systems and methods for providing a policy realization framework for a communications network are disclosed. The policy realization framework can be an application and service layer policy framework that is separate and distinct from the network layer policy framework. As such, policy decisions can be made remote from the network layer, and common policies across multiple networks are possible. Methods and systems for providing these and other features are disclosed. A policy intelligence rules system for a policy realization framework, and methods of implementing a policy intelligence rules system, are also disclosed. |
| US09712328B2 |
Computer network, network node and method for providing certification information
A computer network for data transmission between network nodes, the network nodes being authenticatable to one another by authentication information of a public key infrastructure, with a root certificate authority configured to generate the authentication information for the public key infrastructure. The root certificate authority is arranged separate from the computer network and is not linked to the computer network. A network node of the computer network comprises an authentication information storage, a processor, a network communication device and an initialization device having an initialization communication device and a temporary authentication information storage that can be read out by the processor. |
| US09712323B2 |
Detection of unauthorized entities in communication systems
Methods and systems are provided for detection of unauthorized entities in communication systems. The method includes obtaining a secret string by a first network element and generating a random number by the first network element. The method also includes computing a first cryptographic result by the first network element. The first cryptographic result is based on a cryptographic function, the secret string, and the random number. The method further includes attempting to transmit, by the first network element, a first packet that includes the random number to a second network element using a layer 2 packet terminating protocol. The method includes receiving, within a configured time, a second packet including a second cryptographic result at the first network element, and terminating transmission to the second network element when a second cryptographic result is different from the first cryptographic result. |
| US09712322B2 |
Controlling exposure of sensitive data and operation using process bound security tokens in cloud computing environment
Exposure of sensitive information to users is controlled using a first security token containing user identity and user credentials to represent the user who requests services, and a second security token containing two other identities, one identifying the token issuer and the other identifying the owning process. When requesting services, the token-owning process sends a security token to indicate who is making the request, and uses its key to digitally sign the request. The token-owning process signs the request to indicate that it endorses the request. A receiving server accepts a request if (1) the token-owning process endorses the request by signing the request; (2) the token is valid (token is signed by its issuer and the digital signature is verified and unexpired); (3) user entity, which can be a real user or a deployment or a server process, that is represented by the token has the authorization to access the specified resources; and (4) the token-owning process is authorized to endorse the user entity represented by the token to access the specified resources. |
| US09712320B1 |
Delegatable pseudorandom functions and applications
Techniques are provided for delegating evaluation of pseudorandom functions to a proxy. A delegator delegates evaluation of a pseudorandom function to a proxy, by providing a trapdoor τ to the proxy based on a secret key k and a predicate P using an algorithm T, wherein the predicate P defines a plurality of values for which the proxy will evaluate the pseudorandom function, wherein the plurality of values comprise a subset of a larger domain of values, and wherein the trapdoor τ provides an indication to the proxy of the plurality of values. A proxy evaluates a pseudorandom function delegated by a delegator by receiving a trapdoor τ from the delegator that provides an indication of a plurality of values to be evaluated, wherein the plurality of values comprise a subset of a larger domain of values; and evaluating an algorithm C on the trapdoor τ to obtain the pseudorandom function value for each of the plurality of values. The trapdoor τ can be provided to the proxy using a Gordreich, Goldwasser, Micali (GGM) binary tree representation. |
| US09712319B2 |
Method and apparatus to encrypt plaintext data
Disclosed is an apparatus and method for encrypting plaintext data. The method includes: receiving at least one plaintext data input; applying a Nonce through a function to the at least one plaintext data input to create Nonced plaintext data outputs and/or to intermediate values of a portion of an encryption function applied to the at least one plaintext data input to create intermediate Nonced data outputs; and applying the encryption function to at least one of the Nonced plaintext data outputs and/or the intermediate Nonced data outputs to create encrypted output data. The encrypted output data is then transmitted to memory. |
| US09712318B2 |
Data synchronization method and data transmission system to carry out such a method
A method for synchronizing data transmitted between at least one transmit terminal (TE) and a receive terminal (TR) via a transmission channel (CD) with unmanaged latency, comprising the steps: (a) in said or in each transmit terminal, generating at least one synchronization signal (SSYNC) having a known temporal relationship with the time of transmission of at least one data packet (SEEG) to be synchronized; (b) transmitting said or each data packet to be synchronized on said transmission channel with unmanaged latency, and said or each synchronization signal on an auxiliary transmission channel (CS) with managed latency; (c) in said receive terminal, receiving said or each data packet to be synchronized and said or each synchronization signal; and (d) synchronizing said or each data packet received by said receive terminal by means of said synchronization signal. Data acquisition device for carrying out such a method. |
| US09712317B2 |
Carrier synchronization appropriate for ALM NFC data transmission
In some aspects, the disclosure is directed to methods and systems for carrier synchronization in active load modulation for near field communications. A broadcast carrier is received from a remote device and mixed with a locally-generated carrier and modulated data. A carrier synchronization circuit synchronizes the locally-generated carrier with the broadcast carrier based on an identified phase error from a double Cartesian-to-polar mapping of the mixed locally-generated carrier and broadcast carrier. In some implementations, the system also includes a modulation suppression circuit for providing unmodulated carrier signals to the carrier synchronization circuit or suppressing modulation distortion to maintain frequency and phase tracking despite the presence of data. |
| US09712316B2 |
Reception apparatus, phase error estimation method, and phase error correction method
In a phase error corrector, a signal extractor extracts received reference signals from received signals, and an error vector calculator calculates the error vectors of phase errors by comparing the extracted received reference signals with a known reference signal that is to be transmitted. A representative vector calculator divides, according to frequency, the error vectors into two or more groups and calculates representative vectors for the respective groups. A correction value calculator calculates, on the basis of the representative vectors, phase correction values for the respective frequencies. A phase corrector uses the calculated phase correction values to correct the phase errors for the respective frequencies. |
| US09712315B1 |
Reference clocked retimer model
A method of analyzing a transient response of an electronic circuit includes forming a model of a retimer and receiving an analyzing the output signal of the retimer. The model includes: a signal input circuit that receives an input signal; a clock input circuit that receives a reference clock signal; a slicer that samples a signal produced by the signal input circuit based on the reference clock signal; and an output signal circuit that forms an output signal from a sample taken by the slicer and that is based on the reference clock signal. |
| US09712313B2 |
Systems for multi-peak-filter-based analog self-interference cancellation
A system for multi-peak filter-based analog self-interference cancellation includes a transmit coupler that samples the analog transmit signal to create a sampled analog transmit signal; an analog self-interference canceller, using multi-peak filters, that generates an analog self-interference cancellation signal; and a receive coupler that combines the analog self-interference cancellation signal with the analog receive signal. |
| US09712311B2 |
Method and apparatus of mapping one or more messages onto transmission resource
Method in a network node of mapping one or more messages onto transmission resource for transmitting to a wireless device. The one or more messages are processed by the network node. The network node and the wireless device are adapted to be comprised in a wireless communications network. The network node maps the one or more processed messages onto the transmission resource. This is performed according to indexing information comprised in the one or more messages, and to a precalculated mapping table. The precalculated mapping table is calculated prior to obtaining the one or more messages to be mapped. The network node, the communications network, a second network node, a core network node in the wireless communications network, and methods therein are described. |
| US09712309B2 |
Techniques for improving channel estimation and tracking in a wireless communication system
A technique for performing channel tracking and/or channel estimation in a wireless communication device includes receiving a reference signal and one or more non-error propagation physical channel signals. In general, the one or more non-error propagation physical channel signals must be correctly decoded before a data channel can be decoded. Channel tracking and/or channel estimation are/is then performed based on the reference signal and at least one of the one or more non-error propagation physical channel signals. |
| US09712308B2 |
Method for enhancing small cell
Disclosed is a method for enhancing a small cell. A method for enhancing a small cell in a terminal applying inter-site CA includes the steps of: causing a terminal to transmit the uplink control information (UCI) of at least one of the macro cells controlled by a macro cell base station through the macro cell; and causing the terminal to transmit the uplink control information of at least one of the small cells controlled by a small cell base station through the small cell. |
| US09712307B2 |
Method for transmitting and receiving system information via a broadcast channel (BCH) and a downlink shared channel (DL—SCH)
A method for receiving system information via a broadcast control channel (BCCH) to which a broadcast channel (BCH) and a downlink shared channel (DL_SCH) are mapped, the method including receiving, by a user equipment (UE), a block of first system information from a base station via the BCH, and receiving, by the UE, a first block of second system information from the base station via the DL_SCH. The first block of second system information is scheduled with a fixed time offset. The method further includes receiving, by the UE, a plurality of second blocks of second system information from the base station via the DL_SCH. |
| US09712304B2 |
Method for configuring reference signal for multi-antenna-based beamforming in wireless communication system and device for same
A method by which a base station transmits a reference signal to a terminal in a wireless communication system is disclosed. Particularly, the method comprises the steps of determining a reference signal resource interval expressed as a unit of one or more resource blocks (RBs), setting reference signal resources for a downlink bandwidth defined by a plurality of RBs, according to the reference signal resource interval, and transmitting the reference signal to the terminal by using the set reference signal resources, wherein the reference signal resource interval is determined on the basis of the number of reference signal antenna ports for which quasi co-location (QCL) can be assumed. |
| US09712303B2 |
Grouping based reference signal transmission for massive MIMO scheme
A reference signal transmission scheme is presented. A first user equipment (UE) receives first information identifying which uplink subframe of a plurality of subframes is enabled to transmit an uplink reference signal, and receives second information identifying a sequence used for the uplink reference signal from a base station. The first information is used to identify a different uplink subframe to a first UE group including the first UE and a second UE group other than the first UE group. The second information is determined to assign different orthogonal sequences to each of UEs of the first UE group. The first UE transmits the uplink reference signal to the base station at the uplink subframe identified by the first information using the sequence identified by the second information. |
| US09712302B2 |
Frame structure design for new carrier type (NCT)
A system and method utilizes a selected PRB configuration for a new carrier type for a 3GPP-type wireless network. A downlink signal is received that comprises a demodulation reference signal pattern in at least one predetermined subframe of the downlink signal. The subframe comprises a first predetermined number of the plurality of orthogonal frequency division multiplex (OFDM) symbols comprising synchronization signals for a legacy version of the downlink signal and the demodulation reference signal pattern comprising a second predetermined number of OFDM symbols that are different from the first predetermined number of the plurality of OFDM symbols. After receiving the downlink signal, the demodulation reference signal pattern in the downlink signal is demodulated. |
| US09712298B2 |
Wireless communication system using distributed antennas and method for performing the same
Provided are a wireless communication system and method using distributed antennas. A physical channel and reference signal (RS) transmission/reception method for downlink and uplink communication using a plurality of points is provided for a case in which the plurality of points have different physical cell identities (PCIs), or in a wireless communication environment using distributed antennas in which the plurality of points belong to the same cell and have the same PCI. Also, a method of transmitting a physical channel and an RS in an uplink and a downlink by introducing a virtual cell identity (VCI) is provided. Further, a cooperative transmission method using a plurality of points is provided, so that communication efficiency of a wireless communication system using distributed antennas can be improved. |
| US09712296B2 |
Hybrid zero-forcing beamforming method and apparatus
Communication methods of a base station and a terminal are provided. The communication method of the base station includes receiving feedback information including ray gain information from a terminal, configuring a Radio Frequency (RF) precoder to minimize a Frobenius norm of a total transmit precoder of the base station, and configuring a baseband precoder based on Zero-Forcing (ZF). The communication method of the terminal includes receiving a pilot signal from a base station; estimating a channel of the terminal using the pilot signal; configuring ray gain information based on information of the estimated channel; and feeding back a codebook index corresponding to the ray gain information to the base station. |
| US09712294B2 |
Method for performing wireless switching
A wireless communication system includes an infrastructure device for transmitting and receiving communications to and from a plurality of wireless user terminals. Each wireless user terminal includes a receiver and a controller that receives a plurality of orthogonal frequency division multiplexing (OFDM) signals on a first carrier frequency of a downlink. Each of the plurality of OFDM signals includes carrier frequency assignment information indicating a carrier frequency to transmit uplink data and spatial pattern information indicating a spatial pattern. In response to the carrier frequency assignment information of each of the plurality of OFDM signals, a transmitter and the controller of the wireless user terminal transmit a plurality of uplink signals. Each of the plurality of uplink signals are transmitted on the indicated carrier frequency and using the indicated spatial pattern. |
| US09712293B2 |
Method and apparatus of communication
In a radio communication system, a number of downlink component carriers can be aggregated for communication between a network node and a User Equipment (UE). A set of downlink component carriers is determined from the number of downlink component carriers. A downlink control channel for the UE is arranged to include information being usable for identifying at least one downlink component carrier of the set of downlink component carriers. A channel quality report is to be provided for each one of the at least one identified downlink component carrier. |
| US09712292B2 |
Apparatus for transmitting broadcast signal, apparatus for receiving broadcast signal, method for transmitting broadcast signal, and method for receiving broadcast signal
An apparatus for transmitting a broadcast signal according to one embodiment of the present invention comprises: an encoder for encoding data pipe (DP) data corresponding to a DP which transmits at least one broadcast service or broadcast service component; a mapper for mapping the encoded DP data on a constellation; a time interleaver for time-interleaving the mapped DP data; a frame builder for generating at least one signal frame builder for generating at least one signal frame including the time-interleaved DP data; a pilot inserting unit for inserting signal frame, according to at least one pilot pattern; an OFDM modulator for OFDM-modulating the at least one generated signal frame using OFDM parameters; and a transmitter for transmitting at least one broadcast signal including the at least one modulated signal frame. |
| US09712287B2 |
System and method of redundancy based packet transmission error recovery
A receiver is configured to receive packets that correspond to at least a subset of a sequence of packets and that include error correction data. The error correction data of a first packet of the packets includes a partial copy of a second packet. A buffer is configured to store the packets. An analyzer is configured to determine whether a first particular packet of the sequence is missing from the buffer, to determine whether a partial copy of the first particular packet is stored in the buffer as error correction data in a second particular packet, to update a value based at least in part on whether the first particular packet is missing from the buffer and the partial copy of the first particular packet is stored in the buffer, and to adjust an error recovery parameter based at least in part on the value. |
| US09712273B2 |
Orbital angular momentum multiplexing for digital communication
Optical signals with different orbital angular momentum (OAM) modes are used to multiplex data for different receiver together or a light signal. The OAM based multiplexing may be used in addition to other multiplexing schemes such as time division multiplexing, polarization multiplexing and so on. Capacity of existing optical network infrastructure can be increased significantly using OAM modulation, and data communication can be secured at the same time. |
| US09712272B2 |
User equipment and method for dynamic non-orthogonal multiple access communication
Embodiments pertain to systems, methods, and component devices for dynamic non-orthogonal multiple access (NOMA) communications. A first example embodiment includes user equipment (UE) configured to receive a first downlink control indicator (DCI) from an evolved node B (eNB) and process the first subframe as a first higher power NOMA subframe in response to a first power ratio signal. The DCI includes the first power ratio signal for a first NOMA subframe. The UE may then receive, from the eNB, a second DCI, the second DCI comprising a second power ratio signal for a second subframe and process, by the UE, the second subframe as a second lower power NOMA subframe in response to the second power ratio signal. Additional embodiments may further use another DCI with a third power ratio signal to configure the UE to receive orthogonal multiple access (OMA) communications. |
| US09712268B2 |
Level control apparatus and storage medium
In a group level control section, a largest output level among those in channels belonging to a relevant group is selected automatically as a group level. By operating a control part of a channel level control section displayed on a basic screen, an output level of an input channel corresponding to the operated channel level control section can be controlled. Further, by operating a control part of a group level control section, output levels of the input channels belonging to the group can be collectively controlled with difference in levels among the input channels being maintained. |
| US09712259B2 |
Canister antenna producing a pseudo-omni radiation pattern for mitigating passive intermodulation (PIM)
A canister antenna including a radar transparent housing disposed about an axis and enclosing an antenna assembly having a plurality of integrated radiating elements. The radiating elements are configured to: (ii) produce a pseudo-omnidirectional radiation pattern of RF energy about the axis and (ii) selectively orient at least one null along a radial of the axis. |
| US09712257B1 |
Digitally-controlled impedance control for dynamically generating drive strength for a transmitter
An apparatus, and method therefor, relates generally to a transmitter. In such an apparatus, a decoder is configured to receive a data input and control signals and to generate state signals responsive to a control signal of the control signals and data polarity the data input. Select circuitry is configured to receive coded signals to replace the data input with a pull-up code and a pull-down code of the coded signals responsive to the state signals and the control signals for propagation of the pull-up code and the pull-down code in place of the data input. |
| US09712256B2 |
Method and system for capturing media by using BAN
A method and system for capturing media data using an Body Area Network, BAN, wherein the BAN comprises a BAN enabled media capturing device associated with a first user and at least one BAN enabled communication device associated with a second user, wherein a BAN link is established through the body of the second user between the capturing device and the communication device, when the second user touches the capturing device, settings, related to capturing media data and related to said second user, are downloaded to the capturing device by using the established BAN link and media data is captured with the capturing device by using the downloaded settings wherein the capturing is triggered by the second user. |
| US09712247B2 |
Low bit rate signaling with optical IQ modulators
In one embodiment, a method includes receiving an optical input signal to be modulated by an IQ modulator. The method includes applying data to first and second modulators during a first operation, and applying a first pattern of data to the first modulator and a second pattern of data to the second modulator during a second operation. The second operation results in an optical output signal of the IQ modulator having a low power output and a high power output. The first and second patterns are defined to provide respective desired average powers for a predefined time period based on the low and high power outputs. In another embodiment, a method includes indentifying a transmitter in an optical system by low bit rate signaling. Low bit rate signaling includes receiving an optical input signal from an optical source and transmitting identification data of the transmitter. |
| US09712246B2 |
Infrared audio systems and related methods
A transmitter for transmitting audio signals via infrared light includes a first mounting board and a first plurality of narrow angle LED emitters and a first plurality of wide angle LED emitters attached to a front surface of the first mounting board. The first plurality of narrow angle LED emitters and the first plurality of wide angle LED emitters are configured to emit a beam of infrared light having a wide portion and a narrow portion, the wide portion being proximate the LED emitters and the narrow portion being distal to the LED emitters. An infrared audio system includes a transmitter and an expansion transmitter. The expansion transmitter may include a second plurality of narrow angle LED emitters and a second plurality of wide angle LED emitters. A method of making a transmitter includes attaching a plurality of narrow angle LED emitters and a plurality of wide angle LED emitters to a mounting board of a transmitter. |
| US09712245B2 |
Optical transmission module
Provided is an inexpensive and compact optical transmission module having high coupling efficiency between an optical fiber and a light projecting element and/or a light receiving element. This optical transmission module includes a lead frame including an electric wiring pattern formed therein, a resin housing formed through insert-molding of the lead frame, and an electric device mounted on the lead frame and including a light projecting element for photoelectric conversion. The lead frame forms a slit positioning an optical fiber to be coupled and a reflection mirror reflecting and condensing light from the light projecting element to the optical fiber. |
| US09712237B2 |
Optical distribution method, device, and system
The present invention provide an optical distribution method that includes determining, a first optical distribution frame and a second optical distribution frame, and generating first port indication information and second port indication information according to fiber patch cord setting information; and sending the first port indication information to the first optical distribution frame, sending the second port indication information to the second optical distribution frame, receiving a first port identity and a fiber patch cord identity corresponding to the first port identity which are sent by the first optical distribution frame, and receiving a second port identity and a fiber patch cord identity corresponding to the second port identity which are sent by the second optical distribution frame. |
| US09712236B2 |
Feedback-based configuration of a hybrid fiber-coaxial network
Circuitry of a fiber node which is configured to couple to an optical link and an electrical link may comprise an electrical-to-optical conversion circuit for transmitting on the optical link. The circuitry may be operable to receive signals via the optical link. The circuitry may select between or among different configurations of the electrical-to-optical conversion circuit based on the signals received via the optical link. The signals received via the optical link may be intended for one or more gateways served by the fiber node or may be dedicated signals intended for configuration of the circuitry. The circuitry may be operable to generate feedback and insert the feedback into a datastream received from one or more gateways via the electrical link prior to transmitting the datastream onto the optical link. |
| US09712235B2 |
Resource allocation in PON networks via wave-front multiplexing and de-multiplexing
A data communication system comprises a wave-front multiplexer configured to wave-front multiplex first electronic signals into second electronic signals. The data communication system further comprises an electronic-to-optical converter configured to convert a third electronic signal carrying information associated with the second electronic signals into a first optical signal; and an optical transferring module configured to split the first optical signal into second optical signals, wherein each of the second optical signals carries the same data as the first optical signal carries. The data communication system further comprises optical-to-electronic converters configured to convert the second optical signals into fourth electronic signals; and wave-front demultiplexers each configured to wave-front demultiplex one of the fourth electronic signals into fifth electronic signals equivalent to the first electronic signals respectively. |
| US09712234B1 |
Location aware communication system using visible light transmission
A visible light communication system identifies the location of a mobile device using light intensities corrected by mobile device orientation. This location can be used to generate a dynamic cluster of visible light transmitters about the mobile device providing improved “handoff” between transmitters and reduced shadowing. |
| US09712232B2 |
Apparatus and method for OTDR transmitter noise compensation
An optical device with integrated Optical Time Domain Reflectometer (OTDR) functionality and method for the same is provided. The optical device includes a transmitter and an Optical Time Domain Reflectometer (OTDR) module, The transmitter is configured to generate an Optical Time Domain Reflectometer (OTDR)-modulated optical supervisory channel (OSC) signal by applying an OTDR modulation to an optical supervisory channel (OSC) signal using an OTDR signal and to transmit the OTDR-modulated OSC signal. The OTDR module is configured to generate the OTDR signal, to monitor a returned light signal, to determine transmitter noise compensation information, and to generate OTDR trace information using transmitter noise compensation information and the monitored returned light signal. |
| US09712231B2 |
Multiple narrow bandwidth channel access and MAC operation within wireless communications
A wireless communication device is implemented to include a communication interface and a processor. The processor is configured to process communications associated with the other wireless communication devices within the wireless communication system to determine one or more traffic characteristics of those communications as well as one or more class characteristics of the other wireless communication devices. The processor is configured to classify the communications into one or more access categories based on the one or more traffic characteristics and is configured to classify the other devices into one or more device class categories based on the one or more class characteristics. The processor is then configured to generate one or more channel access control signals based on these classifications. The communication interface of the device is configured to transmit the one or more channel access control signals to one or more of the other devices. |
| US09712229B2 |
GPS time-aiding and frequency correction
A system and method for time-aiding an autonomous Global Positioning System device over a Bluetooth connection allows for a faster time to fix by allowing faster acquisition of time and ephemeris data. The time-aiding information may be distributed in a one-to-one manner or in a manner that allows for the synchronization of multiple devices. |
| US09712226B2 |
Multi-way diversity receiver with multiple synthesizers in a carrier aggregation transceiver
Certain aspects of the present disclosure provide multi-way diversity receivers with multiple synthesizers. Such a multi-way diversity receiver may be implemented in a carrier aggregation (CA) transceiver. One example wireless reception diversity circuit generally includes three or more receive paths for processing received signals and two or more frequency synthesizing circuits configured to generate local oscillating signals to downconvert the received signals. Each of the frequency synthesizing circuits is shared by at most two of the receive paths, and each pair of the frequency synthesizing circuits may generate a pair of local oscillating signals having the same frequency. |
| US09712224B2 |
Antenna switching for dual radio devices
Systems and methods for antenna selection in a wireless terminal with two radios are provided. Signals received using first and second antennas are demodulated by first and second modems according to first and second protocols. A receive path between the second antenna and the second modem can be controlled to receive signals according to the first protocol. A performance measure of demodulating, according to the first protocol, a signal received using the second antenna is determined. The performance measure may be determined using a mirror module in the second modem or using a search module in the first modem. The wireless terminal switches antennas so that the first modem demodulates a signal received using the second antenna, if the performance measure for using the second antenna is such that the switch would improve performance of the first modem. |
| US09712221B2 |
Apparatus, system and method of beamforming
Some demonstrative embodiments include apparatuses, devices, systems and methods of beamforming. For example, a first station may be configured to transmit to a second station a plurality of sector sweep (SSW) frames of a first beamforming transmission of a beamforming procedure, a SSW frame of the first beamforming transmission including a duration value to indicate a time until at least a beginning of a second beamforming transmission subsequent to the first beamforming transmission; and to receive from the second station one or more SSW frames of the second beamforming transmission. |
| US09712220B2 |
Communication system for spatially-encoded wireless communications
A method of spatially-encoded wireless transmission using a wireless communications device that is configured with an electromagnetic radiator involves applying a modulated carrier to one or more radiator elements of the electromagnetic radiator. The radiator elements are selected based on instantaneous samples of baseband information, and the modulated carrier is generated from the baseband information. The modulated carrier is then transmitted via the selected radiator elements. |
| US09712218B2 |
Method and apparatus for facilitating high data rate transmission in the wireless communication
A method for a wireless device capable of receiving and transmitting a signal includes receiving a reference signal from a second wireless device through a communication channel, estimating the communication channel, using the reference signal, selecting a pair of an analog digital converter (ADC) quantizer and an input distribution, based on the estimated communication channel, and sending information on the selected input distribution and the ADC quantizer to the second wireless device. A wireless device capable of wirelessly receiving and transmitting a signal includes a transceiver configured to receive a reference signal from a second wireless device through a communication channel, and a processor configured to estimate the communication channel, using the reference signal, selecting a pair of an ADC quantizer and an input distribution, based on the estimated communication channel, and sending information on the selected input distribution and the ADC quantizer to the second wireless device. |
| US09712217B2 |
Parallel channel training in multi-user multiple-input and multiple-output system
This disclosure describes systems, and methods related to parallel channel training in communication networks. A first computing device comprising one or more processors and one or more transceiver component may receive a first connection request from a second computing device, and a second connection request from a third computing device. The first computing device may send the first training field to the second computing device based at least in part on the first connection request and sending in parallel, the second training field to the third computing device based at least in part on the second connection request. The first computing device may establish a first spatial channel stream with the second computing device based at least in part on the first training field and a second spatial channel stream with the third computing device based at least in part on the second training field. |
| US09712215B1 |
System and method of beamforming with reduced feedback
A system and method of beamforming may reduce feedback requirements. In some implementations, a beamforming technique may employ a diagonal matrix as a beamforming matrix. In some antenna phase beamforming strategies, a diagonal beamforming matrix in which the diagonal elements have a constant magnitude may be employed. Accordingly, a beamforming system may be utilized with few feedback information bits being transmitted from the beamformee; such a system may also minimize or eliminate power fluctuations among multiple transmit antennae. |
| US09712214B2 |
Channel state information feedback method for coordinated multi-point system and associated user equipment
The present disclosure provides a method in a UE for feeding back channel state information (CSI) and the UE. The method comprises: acquiring a set of CSI processes which are configured by a transmission point (TP) to participate in multi-antenna multi-TP coordination; acquiring a sub-band (SB) inheritance which is configured by a TP for a CSI process from the set of CSI processes; calculating the CSI based on the configuration for the CSI process; and feeding the calculated CSI back to a TP. The present disclosure has the advantages of simple implementation and low signalling overhead and is applicable to enhanced 4G systems and to 5G systems. |
| US09712213B2 |
Mobile communication system
In a mobile communication system, an RRM measurement set is set as a collection of cells to become targets on which a UE performs a process of detecting whether or not radio communication is allowed. Among the cells in the RRM measurement set, a CoMP measurement set is set as a collection of cells to become candidates on which the UE performs a process of detecting whether or not coordinated communication (CoMP communication) is allowed. Among the cells of the CoMP measurement set, a CoMP active set is set as a collection of cells to become targets on which the UE performs the process of detecting whether or not CoMP communication is allowed. |
| US09712211B2 |
Quadrature demodulator for a very high bit rate RFID receiver
A quadrature demodulator not requiring analog mixers. The demodulation is made using a first integrator and a second integrator which are controlled by square logic signals at twice the frequency of the carrier, the received signal being alternatively integrated by the first integrator and the second integrator over periods of time equal to a quarter period of time of the carrier frequency. The samples of the first and second integrators are sampled and subtracted from each other. The successive samples are combined in a first and a second combining module for providing in-phase and quadrature component samples. This demodulator can further be provided with a synchronization module IQ and a symbol synchronization module. |
| US09712210B2 |
Method and system for supplying energy to at least one mobile component in a wireless communications system, in particular to RFID tags of an RFID system
A method and system supply energy to at least one mobile component in a wireless communications system, in particular to RFID tags of an RFID system. In the method for supplying energy to at least one mobile component in a wireless communications system with two or more base stations, coherent electromagnetic waves are transmitted by at least two of the base stations. In the system of base stations of a wireless communications system, at least two of the base stations are designed for transmitting coherent electromagnetic waves. |
| US09712209B2 |
Planar spiral induction coil having increased quality (Q)-factor and method for designing planar spiral induction coil
A planar spiral induction coil includes a strip-shaped coil having at least one turn. The at least one turn has a width that changes as a distance from a beginning of the strip-shaped coil increases in a length direction of the strip-shaped coil. Each turn of the at least one turn has a respective width that causes an equal current to flow through each turn of the at least one turn. |
| US09712208B2 |
Method and apparatus for training vector coefficient of vectored digital subscriber line
The present invention provides a method and an apparatus for training a Vector coefficient of a vectored digital subscriber line, where the method includes: after a handshake phase is executed for a joining line, calculating, by using a pilot estimation method, an initial precoding coefficient and an initial cancellation coefficient that represent interference from the joining line to a normal working line; and after a channel discovery phase is executed for the joining line, compensating the initial precoding coefficient and the initial cancellation coefficient by using a compensation factor, to obtain a precoding coefficient and a cancellation coefficient that represent the interference from the joining line to the normal working line, wherein the compensation factor is obtained according to a signal power change or a signal phase change of the joining line. The present invention improves efficiency of Vector coefficient training. |
| US09712202B2 |
Multi-functional mobile phone protection case and manufacturing method thereof
The present invention discloses a multi-functional mobile phone protection case and a manufacturing method thereof. The multi-functional mobile phone protection case comprises an upper cover, a main case, a screen rubber coating and a back case; the upper cover is installed on top of the main case through a pin; volume keys are provided at the upper left side of the main case; and a mobile phone fixing pad and a rope are provided from top to bottom of the lower left side of the main case, respectively; and a power key, a padlock and a fixing button are provided from top to bottom of the right side of the main case, respectively; back case is installed on rear side of the main case through a bracket locking mechanism; an arm band buckle is fixed to rear side of the back case through a second arm band fixing clip and a first arm band fixing clip, a fabric band is provided on the front end of the arm band buckle; a waterproof earphone plug and a waterproof acoustic transmission film is set up from left to right of the bottom of the upper cover, respectively. Through unique structure and manufacturing process design, the present invention can achieve integration of multiple functions, simple and sensible structure design, and not only waterproof, anti-collision and anti-freezing functions, but also sports adaption, portability and multi-style compatibility. |
| US09712198B1 |
Apparatus and method for providing background real-time second order input intercept point calibration
An apparatus and method. The method includes filtering an output of an in-phase (I-mixer); filtering an output of a quadrature-mixer (Q-mixer); converting an output of a first low pass filter (LPF); converting an output of a second LPF; buffering an output of a first analog-to-digital converter (ADC); buffering an output of a second ADC; buffering a transmitter signal; generating a reference signal from an output of a transmitter (TX) data capture buffer; removing DC from the reference signal; and adaptively tuning an I-mixer digital-to-analog (DAC) code and a Q-mixer DAC code from an output of a first receiver (RX) data capture buffer, an output of a second RX data capture buffer, an output of a DC removal unit, and a predetermined step size for each of the I-mixer DAC code and the Q-mixer DAC code. |
| US09712197B2 |
Tunable notch filter and contour tuning circuit
Aspects of this disclosure relate tuning an impedance presented to a common port of a multi-throw switch and a tunable notch filter coupled to the common port. The impedance presented to the common port can be tuned based on an impedance associated with a throw of the multi-throw switch that is activated. According to embodiments of this disclosure, a shunt inductor in parallel with a tunable capacitance circuit can tune the impedance presented to the common port of the multi-throw switch. In certain embodiments, the tunable notch filter includes a series LC circuit in parallel with a tunable impedance circuit. |
| US09712191B2 |
Apparatus and method for use with antenna array
Embodiments of the present invention provide an apparatus (200) for feeding an antenna array (207) comprising at least first and second antenna elements (2071, 2072). The apparatus comprises a first transmitting element (2011) configured to receive a first base band signal (202-i) and to feed a first feed signal (2041) to a first antenna element (2071), the first transmitting element (2011) comprising a first power amplifier (2031). The apparatus also comprises a second transmitting element (2012) configured to receive a second base band signal (2022) and to feed a second feed signal (2042) to a second antenna element (2072), the second transmitting element (2012) comprising a second power amplifier (2032). A tapering control unit (205) is adapted to provide a tapering function between the first feed signal to the first antenna element and the second feed signal to the second antenna element. |
| US09712189B2 |
Error correction capability improvement in the presence of hard bit errors
A soft output detector is programmed with a first set of parameters. Soft information is generated according to the first set of parameters, including likelihood information that spans a maximum likelihood range. Error correction decoding is performed on the soft information generated according to the first set of parameters. In the event decoding is unsuccessful, the soft output detector is programmed with a second set of parameters, soft information according is generated to the second set of parameters (including likelihood information that is scaled down from the maximum likelihood range), and error correction decoding is performed on the soft information generated according to the second set of parameters. |
| US09712188B2 |
Decoding data stored with three orthogonal codewords
In one embodiment, a method includes reading packets of data from M parallel data tracks of a magnetic tape to obtain a plurality of (D+P)-symbol codewords which are logically arranged in nM encoded blocks, each packet including a row of an encoded block, where each encoded block includes an array having rows and columns of code symbols, wherein symbols of each of the (D+P)-symbol codewords are distributed over corresponding rows of the nM encoded blocks, decoding sub-blocks from rows and columns of a plurality of product codewords from the nM encoded blocks, each product codeword including a logical array of code symbols having the rows which include respective row codewords and the columns which include respective column codewords, where each sub-block includes a logical array having rows and columns of data symbols, combining the sub-blocks to form a block of data, and outputting the block of data. |
| US09712187B2 |
SC-LDPC codes for wireless communication systems: framework and zigzag-window decoder
A receiver, such as a mobile station or base station, includes a sliding window-decoder. An antenna in the receiver is configured to receive a protograph-based spatially coupled low density parity check (SC-LDPC) code from a transmitter. The sliding window-decoder is configured to perform a SC-LDPC decoding operation on the SC-LDPC code using a sliding window. The SC-LDPC code includes a parity check matrix. The sliding window includes a subset of protograph sections on which decoding calculations are iteratively performed. The sliding window-decoder performs a stopping rule configured to cease the decoding calculations as a function of a syndrome of one or more check nodes (CNs) in the sliding window. |
| US09712186B1 |
Serial memory interface circuitry for programmable integrated circuits
A programmable integrated circuit may be provided with a memory interface for communicating with an external memory over a serial communications path. To accommodate a variety of different memory interface protocols while satisfying low-latency performance criteria, part of the memory interface may be formed from programmable logic and part of the memory interface may be formed from hardwired circuitry. The programmable logic of the memory interface may be used to implement packet formation logic that creates packets that include empty fields for sequence number information, acknowledgement information, and cyclic redundancy check information. The hardwired circuitry of the memory interface may be used to insert a sequence number, an acknowledgement, and cyclic redundancy check information into the empty fields. |
| US09712185B2 |
System and method for improved fractional binary to fractional residue converter and multipler
Methods and systems for residue number system based ALUs, processors, and other hardware provide the full range of arithmetic operations while taking advantage of the benefits of the residue numbers in certain operations. |
| US09712184B2 |
Sigma-delta modulator
A sigma-delta modulator comprising a plurality of filter stages in series with each other, wherein at least one of the plurality of filter stages is configured to provide a filter-output-signal; and a plurality of gain stages, each gain stage configured to provide a gain-output-signal. The sigma-delta modulator also includes a filter-output-switching-element configured to selectively couple the filter-output-signal to an input terminal of one of the plurality of gain stages; and a plurality of filter-input-switching-elements. Each of the plurality of filter-input-switching-elements is associated with one of the plurality of filter stages, wherein the plurality of filter-input-switching-elements are configured to selectively couple one of the gain-stage-output-signals to an input terminal of its associated one of the plurality of filter stages. |
| US09712183B2 |
Axially and centrally symmetric current source array
A current source device having a current source array includes a plurality of current source units, a plurality of least significant bits, and a plurality of most significant bits. The current source units are arranged along a plurality rows and columns of a current source array. Each of the least significant bits includes a first amount of current source units is placed at the geometric center of the current source array. Each of the most significant bits includes a second amount of current source units. The second amount is the first amount multiplied by a positive integer. The two adjacent bits in the most significant bits are centrally symmetrical to the geometric center. |
| US09712182B1 |
Digital to analog conversion circuit and method
A digital to analog conversion circuit, DAC, comprises a number of serializing lanes, each serializing lane comprising at least two bit inputs, and each serializing lane being configured to output the two bit inputs serially via a serialized output port at a predetermined first clock rate. The DAC further comprises a number of non-serializing lanes, each non-serializing lane comprising at least two bit inputs and each non-serializing lane being configured to output the two bit inputs in parallel each via a separate parallel output port, at a second clock rate, which is half the clock rate of the first clock rate, and a current switching network comprising a bit input port for every one of the serialized output ports and for every one of the parallel output ports and being configured to produce a output current, based on the signals received via the bit input ports. |
| US09712179B2 |
Method and system for broadband analog to digital converter technology
Methods and systems are provided for reconstructing bands in received signals. A first band in a received multiband signal may be reconstructed, during processing of the multiband signal, when the first band is self-aliased during sampling of a second band. The reconstructing may comprise generating a plurality of components corresponding to the first band, based on the sampling of the second band, and combining the plurality of components to reconstruct the first band. Generating a first component may comprise applying high-pass filtering and/or decimation to an input corresponding to an output of the sampling of the second band. Generating a second component may comprise applying low-pass filtering and/or re-sampling to an input corresponding to an output of the sampling of the second band. An adjustment may be applied, when generating the second component, based on sampling of the first band. The adjustment may comprise a subtraction from sampling output. |
| US09712173B2 |
Clock signal stop detection circuit
A semiconductor device detects an edge of input data input into a data retention circuit to which a clock signal is supplied, resets a first count value obtained by counting an edge detection frequency with a clock signal, resets a second count value obtained by counting the edge detection frequency with an inverted clock signal, and thereby detects an abnormality of the clock signal in accordance with a situation that either of the first count value and the second count value has reached a value indicative of an overflow state. |
| US09712172B2 |
Devices with an array of superconducting logic cells
A device including an array of superconducting logic cells, where each of the superconducting logic cells is configured to receive at least one input and provide at least one output, is provided. Each of the superconducting logic cells includes at least one Josephson junction, whose state changes based on at least a biasing condition caused by a phase of a first clock or a phase of a second clock. The array of the superconducting logic cells is configured to perform at least one operation based at least on a connection arrangement of the array of the superconducting logic cells. |
| US09712171B2 |
Clocked all-spin logic circuit
Described is a latch comprising: a first all-spin logic (ASL) device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a clock signal; and a third ASL device coupled to the second ASL device, wherein the first and third ASL devices have respective magnets coupled to a power supply terminal. Described is a flip-flop which comprises: a first ASL device; a second ASL device coupled to the first ASL device, the second ASL device controllable by a first clock signal; a third ASL device coupled to the second ASL device, the third ASL device controllable by a second clock signal, the second clock signal being out of phase relative to the first clock signal; and a fourth ASL device coupled to the third ASL device, wherein the first and fourth ASL devices have respective magnets coupled to a power supply terminal. |
| US09712170B2 |
Level-shifting latch
A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input signal. The level-shifting latch circuit also includes a first latch, having a first node and a second node, for storing the input signal in the first voltage domain, and a second latch, having a third node and a fourth node, for storing the input signal in the second voltage domain. In addition, the level-shifting circuit also includes a first switching element which provides a path to transfer a low voltage at the first node to the third node, and a second switching element which provides a path to transfer a low voltage at the second node to the fourth node. |
| US09712167B2 |
Threshold voltage dependent power-gate driver
Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units. |
| US09712159B2 |
Differential signal driving circuit
A differential driving circuit includes a source current source, a sink current source, an H-bridge circuit, an error detector unit and a circuit network. The H-bridge circuit is connected to the source current source and the sink current source, that has a first output terminal and a second output terminal, and that generates differential output from the first output terminal and the second output terminal. The error detector unit adjusts a common mode voltage at the first output terminal and the second output terminal of the H-bridge circuit by controlling at least one of the source current source and the sink current source. The circuit network is configured by resistors and capacitors connected to the first output terminal and the second output terminal of the H-bridge circuit. |
| US09712156B2 |
Solid state power controllers
A solid state power controller (SSPC) includes a main feed line, a load line, and a P-channel field effect transistor (PCFET) connecting between the main feed line and the load line and including an off state and an on state. The on state electrically connects the main feed line and the load line and the off state electrically disconnects the main feed line and the load line. The SSPC also includes a channel control operatively connected to the PCFET to control the PCFET between the off state and the on state. |
| US09712148B2 |
Switching device driving apparatus
A switching device driving apparatus for preventing arm short circuit is provided, including: a first switching device driving unit for receiving a control signal for controlling a first switching device and a second switching device so that they will not turn ON at the same time and outputting an ON/OFF drive signal to the first switching device; and a second switching device driving unit for receiving the control signal and outputting an ON/OFF drive signal to the second switching device, in which the first switching device driving unit outputs a drive signal for increasing the delay of the ON timing of the first switching device with respect to the OFF timing of the second switching device with increase in ambient temperature. |
| US09712147B2 |
Method for driving a transistor device and electronic circuit
Disclosed is a method and a drive circuit. The method includes measuring a frequency of an input signal received by a drive circuit and driving a transistor device by the drive circuit based on the input signal such that a switching speed of the transistor is dependent on the measured frequency. The drive circuit is configured to receive an input signal, to measure a frequency of the input signal, and to drive a transistor device based on the input signal such that a switching speed of the transistor is dependent on the measured frequency. |
| US09712145B2 |
Delay line circuit with variable delay line unit
A delay line circuit includes a plurality of delay circuits and a variable delay line circuit. The plurality of delay circuits receives an input signal and to generate a first output signal. The first output signal corresponds to a delayed input signal or an inverted input signal. The variable delay line circuit receives the first output signal. The variable delay line circuit includes an input end, an output end, a first and a second path. The input end is configured to receive the first output signal. The output end is configured to output a second output signal. The first path includes a first plurality of inverters and a first circuit. The second path includes a second plurality of inverters and a second circuit. The received first output signal is selectively transmitted through the first or second path based on a control signal received from a delay line controller. |
| US09712143B2 |
System and method for a reduced harmonic content transmitter for wireless communication
A system includes a voltage-controlled oscillator (VCO) to generate an output signal based on an input voltage and a multi-stage delay network to receive the output signal from the VCO. Each stage of the delay network produces a phase-shifted output signal. The system includes a multi-stage digital-to-analog converter (DAC) network, where each stage of the DAC network is associated with a corresponding stage of the delay network. Each stage of the DAC network receives the phase-shifted output signal from its corresponding stage of the delay network and generates a weighted output signal based on the received phase-shifted output signal. The DAC network combines the weighted output signal of each stage. A weighting factor for each stage of the DAC network is selected to reduce harmonic content of the combination of weighted output signals. |
| US09712142B2 |
High frequency semiconductor device
Certain embodiments provide a high frequency semiconductor device including a plurality of unit FETs, an input dividing/matching circuit, an output combining/matching circuit, and a low-frequency-oscillation-suppressing-circuit. The input dividing/matching circuit has an input end and a plurality of divided output ends connected to the unit FETs, and is symmetrical about a center axis of the input end. The output combining/matching circuit has an output end and a plurality of divided input ends connected to the unit FETs, and is symmetrical about a center axis of the output end. The low-frequency-oscillation-suppressing-circuit is connected to at least one of the input end of the input dividing/matching circuit and the output end of the output combining/matching circuit. |
| US09712140B1 |
Tunable multi-path filter
A tunable multi-path filter, a method for filtering a radio frequency signal with the tunable multi-path filter, and a communication device including the tunable multi-path filter. In one embodiment, the tunable multi-path filter includes a voltage controlled current source, an oscillator source, and at least two filter paths. The voltage controlled current source for receiving a radio frequency (RF) signal and generating a current signal. The oscillator source for generating a tunable clock signal. Each of the at least two filter paths are coupled to the voltage controlled current source and the oscillator source, and are configured to generate an output voltage signal based at least in part on the current signal and the tunable clock signal. In some embodiments, the tunable multi-path filter further includes a carrier signal rejection component that is configured to reduce the carrier feedthrough in the output voltage signals. |
| US09712139B2 |
Elastic wave filter device
An elastic wave filter device includes serial and parallel arms and a plurality of elastic wave resonators. Each elastic wave resonator includes an IDT electrode. In the case where a direction in which electrode fingers extend is taken as a width direction of the IDT electrode, the IDT electrode includes a central area at a center in the width direction, a low acoustic velocity area at an outer side portion of the central area, and a high velocity area at a farther outer side portion thereof. A width of the low acoustic velocity area of at least one elastic wave resonator differs from a width of the low acoustic velocity area of the other elastic wave resonators. |
| US09712137B2 |
Resonation device, method of manufacturing resonation device, electronic apparatus, and moving object
A method of manufacturing resonation device (a quartz crystal oscillator) includes the steps of applying a thermosetting thermal insulating connection material and an electrically-conductive connection material, which is higher in curing temperature than the thermosetting thermal insulating connection material, on a principal surface of a substrate, mounting fixation terminals of a resonator (a quartz crystal resonator), which has a heating element, and to which the fixation terminals and connection terminals are connected, in application positions of the insulating connection material on the substrate, and connection terminals in application positions of the electrically-conductive connection material, and heating the insulating connection material and the electrically-conductive connection material based on a reflow profile to make the insulating connection material and the electrically-conductive connection material cure in this order. |
| US09712136B2 |
Nano- and microelectromechanical resonators
A resonator includes a piezoelectric plate and interdigitated electrode(s). The interdigitated electrode includes a plurality of conductive strips disposed over a top surface of the piezoelectric plate. A two-dimensional mode of mechanical vibration is excited in a cross sectional plane of the piezoelectric plate in response to an alternating voltage applied through the interdigitated electrode. The two-dimensional mode of mechanical vibration is a cross-sectional Lamé mode resonance (CLMR) or a degenerate cross-sectional Lamé mode resonance (dCLMR). |
| US09712134B2 |
Ultra-wideband impedance tuner
A mechanical impedance tuner has at least two probe carriages mounted for movement along an axis parallel to the center conductor. The at least two probe carriages including a first probe carriage and a second probe carriage. Each probe carriage has at least N probes where N is an integer equal to or greater than one, and at least one of the N probes is mechanically different or of different nominal geometry from the probes on at least one of the other carriages so that each such probe has an non-identical frequency response. |
| US09712133B2 |
Switchable signal routing circuit
A switchable signal routing circuit for routing a signal between at least one input port and at least one output port is provided. The ports are connected via variable resistors to a common node, wherein the switchable signal routing circuit is configured to set resistance values of the variable resistors in dependence on a number of active ports. |
| US09712122B2 |
Distortion compensation apparatus and wireless communication equipment
A distortion compensation apparatus that compensates for distortion of an amplifier is provided. The distortion compensation apparatus includes: a distortion compensation processing section that performs a predistortion process for a signal provided to the amplifier, based on an amplifier model of the amplifier, and outputs a compensated signal; an estimation section that estimates the amplifier model; and a filter. The estimation section estimates the amplifier model, based on the compensated signal and a monitor signal obtained by monitoring an output of the amplifier. The monitor band of the monitor signal provided to the estimation section is narrower than a frequency band of the compensated signal. The filter is provided so as to eliminate an influence of a signal component outside the monitor band among signal components of the compensated signal, on the estimation of the amplifier model by the estimation section. |
| US09712121B2 |
Circuits for linearizing an output signal of a non-linear component and related devices and methods
This disclosure provides a circuit for linearizing an output signal Sout produced by a non-linear component based on an input signal x(n). The circuit comprises a primary pre-distorter module configured to generate a pre-distorted signal y(n) based on the input signal x(n) and a primary pre-distortion function parameterized by a pre-distortion parameter λ and to feed the pre-distorted signal y(n) to the non-linear component. The circuit comprises an estimation module. The estimation module is configured to receive samples z(n) of the output signal Sout, and to determine the pre-distortion parameter λ. The estimation module comprises a secondary pre-distorter module configured to generate a secondary pre-distorter output signal r(n) based on a secondary pre-distortion function and the samples z(n) of the output signal Sout. The secondary pre-distorter module is configured to determine the pre-distortion parameter λ based on a previously determined pre-distortion parameter stored on a data storage, the secondary pre-distorter output signal r(n) and the pre-distorted signal y(n) provided by the primary pre-distorted module. The determining comprises correlating the input signal x(n) with an error signal between the pre-distorted signal y(n) and the secondary pre-distorter output signal r(n). |
| US09712120B2 |
Systems and methods for optimizing amplifier operations
Methods and systems for optimizing amplifier operations are described. The described methods and systems particularly describe a feed-forward control circuit that may also be used as a feed-back control circuit in certain applications. The feed-forward control circuit provides a control signal that may be used to configure an amplifier in a variety of ways. |
| US09712118B2 |
Amplifier circuit and method
An amplifier circuit comprises a first amplifier configured to amplify a first input signal. The output of the first amplifier is coupled to an output node via a first transmission line, the first transmission line comprising a first portion having a first characteristic impedance and a first length, and a second portion having a second characteristic impedance and a second length. A second amplifier is configured to amplify a second input signal. The output of the second amplifier is coupled to the output node via a second transmission line, the second transmission line comprising a first portion having a first characteristic impedance and a first length, and a second portion having a second characteristic impedance and a second length. An auxiliary amplifier is configured to amplify a third input signal. The output of the auxiliary amplifier is coupled via an auxiliary transmission line network to a first intersection between the first and second portions of the first transmission line, and to a second intersection between the first and second portions of the second transmission line. |
| US09712114B2 |
Systems and methods for delay calibration in power amplifier systems
A power amplifier system is provided. The power amplifier system includes a power supply to generate a supply voltage based on an input signal, a power amplifier powered by the supply voltage to amplify the input signal and generate an output signal, a delay determiner to determine a delay mismatch between the input signal and the supply voltage, and a programmable delay block coupled to the delay determiner to compensate for the determined delay mismatch between the input signal and the supply voltage. The delay determiner determines the delay mismatch based on a first delay between the input and output signals when the input signal is below a threshold and a second delay between the input and output signals when the input signal is above the threshold. |
| US09712112B1 |
Dynamic noise mitigation in integrated circuit devices using local clock buffers
Embodiments are directed to a method of mitigating voltage noise events. The method includes detecting the presence of a voltage noise event at the integrated circuit device. Thereafter, one or more local clock buffers (LCBs) is selected for dampening. A type of dampening is selected for the LCBs. Finally, the dampening is applied to the LCB while the voltage noise event is occurring. |
| US09712110B2 |
Resonator element, resonator, resonator device, oscillator, electronic apparatus, and moving object
A resonator element includes a quartz crystal substrate in which a plane including X and Z′ axes is set as a main plane and a direction oriented along a Y′ axis is a thickness direction. The quartz crystal substrate includes a first region in which thickness shear vibration is generated, a second region that has a thickness thinner than the first region, and first protrusions that are disposed between one pair of electrode pads disposed to be lined in a direction oriented along a Z′ axis on a mounted side of the second region. When Lx is a length of the first protrusions along the X axis and λ is a wavelength of flexural vibration of the quartz crystal substrate, a relation of “λ/2×(2n+1)−0.1λ≦Lx≦λ/2×(2n+1)+0.1λ” (where n is a positive integer) is satisfied. |
| US09712109B2 |
Resonation device, oscillator, electronic apparatus, and moving object
In a crystal resonator, a resonator element is installed in a package via a first bonding member and a second bonding member, and when viewed from above, a distance between a first bonding center and a second bonding center is set to be L1, and a length of a perpendicular line drawn to a virtual line which connects the first bonding center and the second bonding center from the resonation area center is set to be L2, a relationship expressed by 0 |
| US09712108B2 |
Corded lattice based floating photovoltaic solar field with independently floating solar modules
Provided herein is a floating photovoltaic solar device designed to reduce the effect of wind forces without the use of external control or power. The device includes a floating anchored frame with a means for connecting an internal corded lattice; a corded lattice suspended within the floating frame and forming a set of polygonal cells in which independently floating solar photovoltaic modules are positioned. Access for scheduled and unscheduled maintenance may be provided by a floating service gantry. The system is modular and several devices may be connected in a honeycomb-like structure. |
| US09712106B2 |
Rail-less roof mounting clamp assembly components
A rail-less roof mounting system for installing photovoltaic (PV) modules on a roof structure comprises a base mount assembly that engages with a clamp assembly and attaches to the roof structure. The base mount assembly comprises a base member having a waterproof means, a block slider, a top slider and a covering means. An elevated seal portion of a block slider includes a borehole to receive the waterproof means. A vertical engaging portion of the block slider is attached with a sliding seal member of the top slider. The clamp assembly includes a clamp member and a plate member and the clamp member is attached with a track of the top slider. The clamp member interlocks the PV modules to provide a corner-to-corner coupling arrangement, which enables the connection of PV module corners to adjacent PV module corners by sandwiching above and beneath frame members of the PV modules. |
| US09712104B2 |
Control method of over-temperature protection, driver chip and control system of over-temperature protection
A control method of over-temperature protection, a driver chip and a control system of over-temperature protection are disclosed. The control method includes the following steps: a driver chip provides an output voltage to drive a DC fan. A temperature of the driver chip is detected by an over-temperature detection module. When the temperature of the driver chip is higher than a first threshold value, the power supplying to the driver chip is stopped, so that the driver chip can cool down. After the temperature of the driver chip is lower than a second threshold value, the driver chip is restarted. A preset voltage is provided to the DC fan by the driver chip and the DC fan rotates at a preset rotational speed which is higher than the rotational speed. |
| US09712102B2 |
Programming control method for servo fan and programming control device thereof
A programming control method for a servo fan and a programming control device thereof are provided in the embodiment of the invention. The programming control device is coupled to a motor. The programming control device includes an input/output interface, a micro processing unit and a function circuit. The function circuit is coupled to the input/output interface and the micro processing unit. The function circuit updates the firmware according to a magnitude of an operation voltage. |
| US09712100B2 |
Electric rotating machine and control method therefor
When a rotating machine unit is under at least a predetermined operation condition in a motor mode or when the rotating machine unit is under at least a predetermined operation condition in an electric power generator mode, there is performed electric-power conversion control in which there are combined rectangular wave energization control where an armature winding is energized with a rectangular wave and duty energization control where the armature winding is energized with the rectangular wave at a predetermined duty ratio. |
| US09712099B2 |
Divided phase AC synchronous motor controller
A phase windings circuit for a motor includes at least two phase windings forming one half of motor phase windings of the circuit and at least two other phase windings forming another half of the motor phase windings of the circuit. A direct current (DC) power supply is located at least approximately at a midpoint of the motor phase windings to receive alternating current (AC) power transferred from one or more of the phase windings and convert the AC power to DC power. A first stage power switch circuit comprises at least one power switch outside of the DC power supply and is electrically connected at least approximately at a midpoint between phase windings on each half of the circuit. A second stage power switch circuit comprises at least one other power switch outside of the DC power supply and is electrically connected at least approximately at the midpoint of the divided phase windings to receive AC power from the motor divided phase windings. A non-collapsing DC power supply component prevents the DC power supply from collapsing when the at least one power switch or the at least one other power switch is on and conducting. |
| US09712098B2 |
Safety system and method for pump and motor
Embodiments of the invention provide a variable frequency drive system and a method of controlling a pump driven by a motor with the pump in fluid communication with a fluid system. The drive system and method can provide one or more of the following: a sleep mode, pipe break detection, a line fill mode, an automatic start mode, dry run protection, an electromagnetic interference filter compatible with a ground fault circuit interrupter, two-wire and three-wire and three-phase motor compatibility, a simple start-up process, automatic password protection, a pump out mode, digital input/output terminals, and removable input and output power terminal blocks. |
| US09712096B2 |
Control apparatus and control method for AC rotary machine, and electric power steering apparatus
This invention is concerning obtaining a control apparatus and a control method for an AC rotary machine, with which a voltage command can be used up to a saturation voltage in each group of windings even when dimension differences exist between the groups of windings. A voltage saturation determination unit determines whether or not voltage saturation has occurred in a first winding group or a second winding group on the basis of at least one of a voltage and a current relating to the first winding group and the second winding group, and when determination is made that voltage saturation has occurred in either the first winding group or the second winding group, generates a voltage saturation determination signal for reducing a gain of at least one axial direction component on a rotational two-axis coordinate system. |
| US09712095B2 |
Efficient damping of vibrations of an electric machine
A first active part of a poly-phase electric machine is connected to a converter having a control facility. The control facility updates a base commutation angle using the target speed value and determines direct-axis and quadrature-axis component values of currents and a commutation angle supplied to the machine. Target and component quadrature-axis values are provided to a quadrature-axis portion of a current controller that determines a target value of the quadrature-axis voltage component. Target and component current values are supplied to a direct-axis portion of the current controller, which determines a target value of the direct-axis voltage component therefrom. The target value of the direct-axis and quadrature-axis voltage components and the commutation angle are used to determine the target output voltages provided to the converter. A damping commutation angle determined using target values of the quadrature-axis and direct axis voltage components is used to adjust the of the voltage. |
| US09712092B2 |
Motor control apparatus and operation method for the same
Provided are a motor control apparatus controlling a motor including a stator and progressing or retreating a screw so that pressure is formed in a piston provided in a brake for braking a vehicle, and an operation method thereof and the motor control apparatus includes: the motor including a rotor with a permanent magnet and a coil forming an electromagnetic field; an encoder outputting an encoder pulse and a reference pulse to correspond to rotation of the motor; and an electronic control unit controlling the motor based on the encoder pulse and the reference pulse of the encoder, wherein the location of the rotor is determined based on the encoder pulse and the reference pulse input from the encoder when the motor rotates by forcibly rotating the motor to control the motor when the motor starts, thereby starting the motor when the hall sensor is abnormal or even though the hall sensor is not provided by controlling the motor. |
| US09712087B2 |
Piezoelectric element drive circuit and robot
A piezoelectric element drive circuit includes a piezoelectric element that has a piezoelectric substance whose thickness is 0.05μ to 20 μm and two electrodes which interpose the piezoelectric substance therebetween, an inductor that is connected to the piezoelectric element in parallel, and a drive voltage generation circuit that applies a drive voltage including an AC component to the piezoelectric element and the inductor. |
| US09712083B2 |
Method and device for switching operation mode of a five-level inverter
A method and device for switching an operation mode of a five-level inverter are provided. The method includes: determining a first three-level operation mode as a three-level operation mode to be switched to from a five-level operation mode in a case that a PV input voltage is higher than a bridge line-line voltage command value; switching, after the operation mode is switched to the first three-level operation mode, the operation mode from the first three-level operation mode to a second three-level operation mode, in a case that a junction temperature of a switching device operating in the first three-level operation mode exceeds a first preset value; and switching the operation mode from the second three-level operation mode to the first three-level operation mode in a case that the junction temperature of a switching device operating in the second three-level operation mode exceeds a second preset value. |
| US09712077B2 |
Active rectifier and circuit for compensating for reverse current leakage using time delay scheme for zero reverse leakage current
A method of compensating for reverse current leakage in an active rectifier may include advancing an output of a comparator by a predetermined period of time by applying a predetermined offset voltage to a reference voltage input to the comparator, and activating a switch based on the output of the comparator. The method may also include deactivating the switch when a predetermined time delay elapses from a point in time at which the switch was activated. |
| US09712075B2 |
Method of controlling single-phase voltage source AC/DC converter and interconnection system
A method of controlling a single-phase voltage source AC/DC converting circuit has internal equivalent impedance as seen from an AC terminal, for converting power from a DC voltage source connected to a DC terminal to single-phase AC power or for converting single-phase AC power from a single-phase AC source connected to the AC terminal to DC power in accordance with a pulse width of a gate signal generated based on a PWM command. |
| US09712073B2 |
Flexible rectifier for providing a variety of on-demand voltages
An apparatus comprising a first rectifier, wherein an output of the first rectifier is coupled to a first terminal, a second rectifier, wherein an output of the second rectifier is coupled to a second terminal, a first electronic switch configured to selectively route an alternating current (AC) signal to the first rectifier or the second rectifier, an inverter configured to operate in the event that the first electronic switch does not receive the AC signal to receive a direct current (DC) signal, and convert the DC signal to a second AC signal, a second electronic switch configured to selectively route the DC signal from the first terminal or the second terminal to the inverter, and a third electronic switch configured to selectively route the second AC signal to the first rectifier or the second rectifier. |
| US09712072B2 |
Inverter device
A power converter converts input power into DC power. A first switching element is connected between an output node and a high voltage node of the power converter. A second switching element is connected between the output node and a low voltage node of the power converter. First to third driver circuits have first to third power supply nodes to be supplied with first to third operating voltages based on first to third voltages at the output node, the low voltage node, and the high voltage node, respectively. The first to third driver circuits drive the first to third switching elements based on the first to third voltages, respectively. A rectifier circuit is connected between the power supply nodes of the first and second driver circuits, and supplies a current from the power supply node of the first driver circuit toward the power supply node of the third driver circuit. |
| US09712069B2 |
Distributed-constant type transformer for voltage conversion
A transformer of distributed-constant type is provided between an AC power supply with a frequency f and a load with a resistance value R, and includes: a first converter connected to the AC power supply and having a length of λ/4; and a second converter provided between an end of the first converter and the load, and having a length of λ/4, where a wavelength at the frequency f is λ. Such a transformer has a small size and a light weight, and does not need a coil, an iron core, and the like as used in a conventional transformer. |
| US09712066B2 |
Assisted zero voltage switching for a DC-to-DC converter
An apparatus includes a first auxiliary switch connected to a positive connection of a switching leg of a DC-to-DC converter. The switching leg includes a first main switch and a second main switch connected at a main switch midpoint. A second auxiliary switch is connected between a negative connection of the switching leg and the first auxiliary switch. A connection point between the first and second auxiliary switches is an auxiliary midpoint. An auxiliary inductor connects the auxiliary midpoint and the main switch midpoint. The main switch midpoint is also connected to other converter elements. The first and second main switches include a first capacitance a second capacitance. A switch regulation module regulates the first and second auxiliary switches to control current in the auxiliary inductor to provide or remove charge from the first and second capacitances to induce zero voltage switching for the first and second main switches. |
| US09712062B2 |
Symmetrical power converter
A switched-capacitor circuit has two capacitors and two MOSFETs that cross-couple the capacitors, connecting the anode of one to the cathode of the other, and vice-versa. When either MOSFET is on, the capacitors are in series; the order alternates as the MOSFETs alternate. A reversing cyclical voltage suitable as a primary drive for a transformer is generated. If the MOSFETs alternate with no dead-time, a square-wave excitation is generated. With off-time, a pwm excitation is generate. Charge is maintained on the switched-capacitors using a symmetrical common-mode inductor. A bifilar winding is center-tap as its input, and the ends of the bifilar winding are connected to the capacitors. The capacitors are effectively in parallel. Because the charging current flows and returns through each leg of the inductor equally, it cannot magnetize the inductor core or cause any flux change. Because any voltages induced in the windings are common-mode, flux change in the core does not affect the charging current. The ac voltage generated when the capacitors switch is across the full inductor. Not only does the inductance attenuate any noise, the center-tap is between equal and opposite negative and positive voltages, which cancel. There is very little noise at the input. The circuit is reciprocal, so it can be used to rectify a transformer output. Two can be used as a bi-directional transformer isolated power converter. Several modules using 1 to 1 transformers can be stacked for a power converter having a higher ratio of input to output voltage. |
| US09712061B1 |
Power converter overvoltage system
Power converters their methods of operation are described. An example method includes regulating an output using a switching circuit that responds to a control signal. The method includes comparing a feedback voltage from the output to a reference voltage using an error amplifier to create an error voltage, and comparing the error voltage to a ramp voltage from a periodic ramp signal using a comparator to create a PWM signal. The PWM signal is used in combination with the switching circuit to regulate the output. The method includes: clamping the error voltage, using a clamping circuit, if the error voltage drops below a lowest value for the periodic ramp signal while the power converter is regulating a load; and unclamping the error voltage, using the clamping circuit, if the error voltage rises above the lowest value for the periodic ramp signal while the power converter is regulating the load. |
| US09712058B1 |
High speed tri-level input power converter gate driver
Various methods and devices that involve electronic circuits are disclosed. A disclosed method includes buffering an input signal using a first buffer. The first buffer is powered by a supply voltage and a reference voltage. The method also includes buffering the input signal using a second buffer. The second buffer is powered by the reference voltage and a ground voltage. The method also includes level shifting a first buffer output signal of the first buffer to a voltage range using a first level shifter, and level shifting a second buffer output signal of the second buffer to the voltage range using a second level shifter. The voltage range is larger than a delta between the supply voltage and the reference voltage. The reference voltage is greater than one quarter of the supply voltage and less than three quarters of the supply voltage. |
| US09712057B1 |
Feedback control circuit and method thereof
Disclosed are a feedback control circuit and a method thereof. The feedback control circuit includes a voltage comparator, a calibration voltage generator and processor. The voltage comparator receives a middle-point voltage and a calibration voltage, compares the middle-point voltage and calibration voltage, and outputs a reference voltage pulse signal. The calibration voltage generator generates the calibration voltage and outputs it to a switch driving circuit and the voltage comparator. The processor compares the pulse widths of the reference voltage pulse signal and a predetermined voltage pulse signal, and accordingly outputs a control signal to the calibration voltage generator to fine tune the calibration voltage. The switch driving circuit outputs a switch driving signal to a switching regulating circuit to adjust the timing when to turn on or off switches in the switching regulating circuit. |
| US09712056B1 |
Three-phase power switching for ungrounded wye circuits
A power control system includes a multi-phase power source, an ungrounded multi-phase load, a plurality of power switching circuits and a plurality of zero-crossing circuits. The multi-phase power source includes a plurality of phase power outputs. The plurality of power switching circuits are each connected to provide power from one of the plurality of phase power outputs to the ungrounded multiphase load. The plurality of zero-crossing circuits are connected to provide control signals to the plurality of power switching circuits. Each of the plurality of zero-crossing circuits are connected between one of the plurality of power phase outputs and an ungrounded reference. |
| US09712052B2 |
Power supply apparatus with cable voltage drop compensation
A power supply apparatus is provided. The power supply apparatus includes a first power pin, a second power pin, a DC output regulator, a current sensing circuit, and a compensation circuit. The first and second power pins are coupled to an external load through a first wire and a second wire respectively. The DC output regulator receives an input voltage and a feedback voltage and generates an output voltage and an output current. The current sensing circuit senses the output current and generates a sensing voltage. The compensation circuit generates a compensation voltage responding to the sensing voltage. The compensation voltage is a sum of a voltage drop on the first wire and a voltage drop on the second wire. The compensation circuit compensates the output voltage according to the compensation voltage, such that a load voltage of the external load is kept at a stable voltage value. |
| US09712048B2 |
Algorithm for passive power factor compensation method with differential capacitor change and reduced line transient noise
A computer-implementable control algorithm that measures: 1) the reactive power; 2) the power factor; 3) the voltage; and 4) the line frequency. The algorithm calculates the differential compensation capacitance required that is either positive (capacitance to be added), or negative (capacitance to be removed). The new compensation capacitance is calculated from the sum or difference of the differential compensation capacitance and the current compensation capacitance. The algorithm compares the capacitor switching bit pattern for the current compensation capacitance and the capacitor switching bit pattern for the new compensation capacitance, and selects a capacitor switching bit map accordingly. The capacitor switch combination for the new compensation capacitance is switched in incrementally according to the capacitor switching bit map. To reach the selected capacitor switch combination, only one switch is switched at a time to minimize the line transient noise. This part of the algorithm continues to run until the PF is corrected, with the capacitor switches being switched on/off each delayed by a millisecond interval to minimize line transient noise. |
| US09712047B2 |
Power factor controller with error feedback, and a method of operating such a power factor controller
A power factor controller is disclosed, in which error feedback is provided my means of a parallel combination of at least two error feedback channels. By providing at least two error feedback channels, the stability associated with, for instance, a continuously integrated feedback loop with relatively long time constant, may be combined with a fast transient response associated with, for instance, a sample-and-hold error feedback.A method of operating such a power factor controller is also disclosed. |
| US09712045B2 |
System and method for a startup cell circuit
According to an embodiment, a circuit comprising includes a first switching circuit coupled to a power supply input, a second switching circuit coupled to an output of the first switching circuit, a supply capacitor coupled to the second switching circuit, and a startup cell coupled to the power supply input and the supply capacitor. The startup cell is configured to electrically couple the power supply input to the supply capacitor when the second switching circuit is not actively switching. The startup cell is also configured to electrically decouple the power supply input from the supply capacitor when the second switching circuit is actively switching. |
| US09712039B2 |
In-vehicle power conversion system
An in-vehicle power conversion system, which can shield a circuit unit without using a particular shield member and can achieve reduction in cost and size, is obtained. Included are: a conductive housing having an opening; and a multilayer printed wiring board in which circuit units are mounted and one layer is a GND plane. The multilayer printed wiring board is assembled to an opening surface of an opening of the conductive housing to form a closed space; and the GND plane of the multilayer printed wiring board is electrically connected to the conductive housing to shield the circuit units stored in the closed space surrounded by the conductive housing and the multilayer printed wiring board. |
| US09712037B2 |
Insulated power supply apparatus for power conversion apparatus including series of connections of upper and lower arms switching elements connected to each other
An insulated power supply apparatus is for a power conversion circuit including at least one series connection of an upper arm switching element and a lower arm switching element connected in series to each other. The insulated power supply apparatus includes an upper arm and lower arm transformers for supplying a driving voltage to the upper arm and lower arm switching elements, respectively, and performs control such that the output voltage of a specific one of the secondary coils of the upper arm and lower arm transformers is kept at a target voltage. |
| US09712035B1 |
Electrospray based diffusion pump for high vacuum applications
An electrospray diffusion pump with an upper vacuum chamber coupled to a lower vacuum chamber by a cylinder having an aperture in the upper chamber at the center of a conductive extractor ring. A conductive tube is positioned in the upper chamber and is axially aligned with the conductive extractor ring. The conductive tube is coupled to receive a conductive or semi-conductive spray fluid. A voltage source is coupled between the conductive tube and the extractor ring and adjusted to form a Taylor Cone that provides a jet of charged droplets at the tip of the conductive tube, the charged droplets are attracted to the extractor ring and pass into the aperture, then through the cylinder into the second chamber. The charged droplets have nearly zero vapor pressure and transfer ambient gas at a first pressure from the upper chamber to the lower chamber at a lower pressure. |
| US09712034B2 |
Electromechanical actuator to reduce heating effects
The application describes an electromechanical actuator for generating a mechanical force to be transferred to an apparatus. The electromechanical actuator comprises an electromagnetic coil, a connecting member, and a magnet. The connecting member is mechanically coupled between the electromagnetic coil and the apparatus and is configured to transfer the mechanical force from the electromagnetic coil to the apparatus. The magnet is disposed between the electromagnetic coil and the apparatus and includes a channel in which the electromagnetic coil is disposed, the channel having a channel opening that faces away from the apparatus, the magnet further having a central hole through which the connecting member extends. |
| US09712028B2 |
Stator having three-line connection structure, BLDC motor using same, and driving method therefor
Provided are a stator having a three-coil wiring structure, a BLDC motor using the same, and a driving method thereof, in which coils are wound by using a three-coil wiring method, to thus minimize a ratio between slots and poles, and to thereby reduce cogging noise, and a gap between cores is set small, to thus increase an effective area between a magnet and a core and to thereby reduce leakage magnetic flux. The BLDC motor includes: a stator having a plurality of split cores that are disposed between an inner rotor and an outer rotor, and on which coils of three phases are connected and wound in a three-phase drive method, in which the plurality of split cores include a number of core groups in which the coils of the respective phases are wound on three consecutive split cores in sequence of a forward direction, a reverse direction, and a forward direction, and the three consecutive split cores generate magnetic flux in opposite directions to each other. |
| US09712025B2 |
Magnet inserting apparatus for magnet insertion into magnet insertion slots of rotor core and method thereof
A magnet inserting apparatus inserts a plurality of magnet parts into each of the magnet insertion slots provided in the rotor core of a motor. The magnet inserting apparatus comprises a guiding unit equipped with a magnet inlet and a magnet outlet and is configured to align the plurality of magnet parts inserted through the magnet inlet until the inserted magnet parts are ejected from the magnet outlet, and to guide the aligned magnet parts so as to be inserted from the magnet outlet to the magnet insertion slot. A size of the magnet inlet of the guiding unit is larger than a size of the magnet insertion slot, a size of the magnet outlet is the same as or smaller than the size of the magnet insertion slot, and the guiding unit is formed so that a shape from the magnet inlet to the outlet becomes a taper shape. |
| US09712015B2 |
Motor of a ceiling fan
A motor of a ceiling fan includes: a shaft having two shoulder surfaces facing in opposite axial directions of the shaft, with the shaft coupling with a stator; and a bearing sleeve receiving two bearings for supporting the shaft, with an annular flange formed at an end of the bearing sleeve. The annular flange and one of the shoulder surfaces of the shaft clamp and position one of the bearings. A rotor has a housing coupling with the bearing sleeve, with the housing having a connecting portion. The connecting portion and the other one of the shoulder surfaces of the shaft clamp and position the other one of the bearings. |
| US09712004B2 |
Permanent magnet rotor with permanent magnet modules arranged on the rotor
A permanent magnet rotor comprising a rotor rim and a plurality of permanent magnet modules arranged on the outer or inner circumference of the rotor rim, the permanent magnet modules extending generally along an axial direction and being of substantially constant axial-cross section, and comprising a base adapted to be fixed to the rim of the generator rotor, one or more permanent magnets, and one or more pole pieces, wherein each of the permanent magnets has a circumferential magnetic orientation and is substantially rectangular in axial cross-section and wherein each of the permanent magnets is inclined with respect to the central radial plane of the module. |
| US09711998B2 |
Power transmitting device, power receiving device, power supply system, and power supply method
Provided are a power transmitting device, a power receiving device, a power supply system, and a power supply method able to supply electric power by emitting electromagnetic waves. A power transmitting device (110) comprises: a calculating unit (122) for calculating the maximum value for the emitted output of electromagnetic waves meeting exposure standards on the basis of a response delay time measured by the communication link between the power transmitting device (110) and a power receiving device (150); a power transmitting unit (128) for transmitting power via a power supply link with the power receiving device (150) at an output not exceeding the maximum value; an anomaly detecting unit (126) for detecting an anomaly in the power supply link on the basis of communication with the power receiving device (150) via the communication link; and an output control unit (124) for controlling the output on the basis of the detection of an anomaly in the power supply link. |
| US09711994B2 |
Electronic device and its operation system
An electronic device carried around by the user is desired to be used for a long period. In order to achieve this, a high-capacity battery may be incorporated. Since a high-capacity battery is large, its incorporation in an electronic device increases the weight of the electronic device. An electronic device used while being implanted in the body of the user, provided with an emergency power supply, is provided. In an electronic device provided with a plurality of batteries, a transmitting portion and a receiving portion conduct wireless charging among different batteries, and the battery to be charged or used is selected by a power supply management circuit depending on the circumstances. |
| US09711993B2 |
Opportunistic charging of an electronic device
One embodiment of the present invention sets forth a technique for charging an electronic device. The technique includes determining that the electronic device is proximate to a first induction coil that is included in a plurality of induction coils that are disposed in a steering wheel. The technique further includes, in response to determining that the electronic device is proximate to the first induction coil, causing electrical current to be supplied to the first induction coil to charge the electronic device. |
| US09711991B2 |
Wireless energy transfer converters
Described herein are improved configurations for a wireless power converter that includes at least one receiving magnetic resonator configured to capture electrical energy received wirelessly through a first oscillating magnetic field characterized by a first plurality of parameters, and at least one transferring magnetic resonator configured to generate a second oscillating magnetic field characterized by a second plurality of parameters different from the first plurality of parameters, wherein the electrical energy from the at least one receiving magnetic resonator is used to energize the at least one transferring magnetic resonator to generate the second oscillating magnetic field. |
| US09711986B2 |
Vacuum cleaner and a battery pack therefor
A battery pack suitable for handheld appliance, the battery pack including a plurality of cells and a circuit board associated with the cells, wherein a power terminal is associated with the circuit board and configured to transmit power to an appliance, in use, the battery pack further including a momentary switch operatively connected to the circuit board and movable between closed and open positions by an actuator wherein, when in the open position the power terminal is configured by the circuit to a power delivery state and, when in the closed position, the power terminal is configured by the circuit to a power disabled state. |
| US09711983B2 |
Device, system and method for charging a battery
A device, system and method for charging a battery are provided. The device comprises: a USB (Universal Serial Bus) port; a battery in communication with the USB port; and, circuitry in communication with the USB port and the battery, the circuitry configured to: transmit a power control signal over the USB port, the power control signal comprising data indicative of one or more of a power, a voltage and a current to be received over the USB port to charge the battery; and, responsively receive the power for charging the battery over the USB port. |
| US09711982B2 |
Information notifying device
An information notifying device in accordance with the present disclosure includes a first communication circuit, a second communication circuit, a clock, and a controller. The first communication circuit receives first information regarding an estimated arrival time at which transportation equipment will arrive at a destination. The second communication circuit receives second information regarding a remaining battery capacity of a battery installed in an external device. The clock keeps a current time. The controller calculates a first charging time necessary to charge the external device to a fully charged state based on the second information, and outputs information prompting to charge the external device at a first timing based on the first information, the current time and the first charging time. |
| US09711978B2 |
Remote charging system
A charging device is provided for communicating with one or more consumer devices for remotely charging at least one of them upon demand of the consumer. The charging device comprises a transmitter unit associated with an antenna unit comprising a power antenna for defining at least one charging zone for transmitting charging power toward it; a receiver for receiving signals from consumers located within the charging zone; and a controller unit configured to be responsive to a request signal from a consumer indicative of demand for charging, to initiate a charging process of the consumer by radiation from the power antenna toward the consumer to supply power required for operating a functional unit of the consumer. The power antenna may comprise an array of directional antenna elements, each defining the charging zone within a different angular segment of entire charging space defined by a radiation pattern of the antenna array. |
| US09711975B2 |
Power bank circuit and the method thereof
A power bank circuit controlling power switches to operate at different modes in accordance with different external coupling situations is discussed. The power bank circuit may be coupled to either a power source, a digital device, or a plurality of series coupled batteries at a high voltage port; and may be coupled to either a power source, a digital device, or a single battery at a low voltage port. |
| US09711970B2 |
Non-contact power supply system and control method for non-contact power supply system
A non-contact power supply system, in which a first transmission efficiency of supply power in the case of supplying power in a first power supply mode of directly supplying power from a power supply apparatus to a power receiving apparatus and also supplying power to the power receiving apparatus through a relay apparatus, and a second transmission efficiency in the case of supplying the power in a second power supply mode of directly supplying the power from the power supply apparatus to the power receiving apparatus and not supplying the power from the power supply apparatus to the power receiving apparatus through the relay apparatus are compared. |
| US09711969B2 |
Method and apparatus for transmitting wireless power to multiple wireless power receivers
A method and apparatus are provided for transmitting wireless power in a wireless power network managed by a wireless power transmitter. The method includes transmitting first charging power to a first wireless power receiver; detecting a second wireless power receiver; and transmitting second charging power to the second wireless power receiver. |
| US09711967B1 |
Off grid backup inverter automatic transfer switch
A power conversion system for use with an alternate energy source includes a first inverter, a battery, and a second inverter, each of which receives power from the alternate energy source. The output of the first inverter and the grid are each connected to at least one electrical load via a load center. The battery is charged via a charger connected to the alternate energy source. This stored energy powers a selected portion of the electrical loads during a failure of the utility grid. The second inverter is connected between the battery and a transfer switch. During normal grid operation, the second inverter is disabled and the transfer switch connects the load center to the selected electrical loads. During a failure of the utility grid, the first inverter is disabled, the second inverter is enabled, and the transfer switch connects the second inverter to the selected electrical loads. |
| US09711966B2 |
Method and device for monitoring a converter
A converter is described, in particular a DC/DC converter for use in a motor vehicle, including: a converter circuit, which is situated between a first network and a second network to convert a direct current or alternating current at an input terminal on the input side into a direct current or alternating current at the output terminal on the output side, the direct current or alternating current on the input side and the direct current or alternating current on the output side being based on a shared potential; a first monitoring circuit, which is situated between the input terminal and the converter circuit to detect a current flow into the converter circuit; a second monitoring circuit, which is situated between the output terminal and the converter circuit to detect a current flow into the converter circuit; a first separation element, which is situated between the input terminal and the converter circuit to establish a connection between the input terminal and the converter circuit and/or a second separation element, which is situated between the output terminal and the converter circuit, to establish a connection between the output terminal and the converter circuit. |
| US09711964B2 |
Method and system for operating a power generation and delivery system
A method for controlling operation of a power generation and delivery system while increasing a power output of the power generation and delivery system is described. The method includes, monitoring an output parameter of the power generation and delivery system and determining a rate of change of the output parameter as a function of time. A reactive current command signal is generated a as a function of the determined rate of change of the output parameter. Operation of a power converter is controlled based at least partially on the reactive current command signal to facilitate maintaining a substantially constant terminal voltage as the power output of the power generation and delivery system is increased. |
| US09711959B2 |
Chain link
A link of an energy chain has two parallel side flaps and at least one horizontal web. The two side flaps and the at least one horizontal web are connected to each other by positioning, pivoting and engaging. Two pivoting groups are provided, including in each case a contact surface and a relevant intake for positioning the contact surface in such a way that the pivoting groups in the positioned state form a pivoting axis transversely to the longitudinal axis of the chain link. Furthermore, two engagement groups are provided which in each case are formed by a locking element and a relevant abutment for receiving the locking element. A chain link can be assembled in a simple manner by a plurality of different horizontal webs and side flaps, wherein the connection between the horizontal web and the side flap cannot be randomly released. |
| US09711957B2 |
Screwless and seamless cover plate and cover plate assemblies that comprise one or more retention members that selectively engage and substantially conform to the outer surface and edges of an electrical outlet or switch, or audio, data, or video plug, cable, or connector, to releasably secure the cover plate sub-assembly thereto
Cover plates are provided for electrical fixtures including a screwless cover plate and/or cover plate assembly for electrical devices that cover the fixtures but provide holes for plugs, light switches, audio, data, or video connectors, and that optionally do not show screw or attachment holes, and where the cover plate is part of a cover plate assembly that comprises one or more retention members selectively engage and substantially conform to the outer surface and edges of the electrical outlet or switch, or audio, data, or video plug, cable, or connector, to releasably secure the cover plate sub-assembly thereto. |
| US09711954B2 |
Snap-in shutter system for rack out circuit breakers
The present disclosure provides a shutter system (150) for a cradle (100) of a rack out circuit breaker, which includes two rail assemblies (200, 300), a shutter (400) and a cam actuator (280). A first of the rail assemblies is configured to snap into an interior surface of one of the side walls (102, 104) of a cradle, and a second of the rail assemblies is configured to snap into an interi- or surface of an opposing side wall of the cradle. Each rail assembly includes a snap-in lock assembly and a slider movable between a front and back of the cradle along a corresponding side wall. |
| US09711951B2 |
Spark plug
A spark plug having a resistor disposed within a through hole of an insulator and between a center electrode and a metal terminal so as to be spaced apart from the center electrode in a direction of an axial line; and a conductive glass seal layer provided between the resistor and the center electrode and electrically connecting the resistor and the center electrode to each other, the conductive glass seal layer has a diameter of 3.9 mm or less, and a joined surface of the conductive glass seal layer and the resistor has a convex shape toward the center electrode side. A length α from a rear end to a front end of the joined surface and a maximum length β of the conductive glass seal layer in the direction of the axial line meets a relation of α/β≧0.4. |
| US09711950B2 |
Dense wavelength beam combining with variable feedback control
An external cavity laser apparatus according to an embodiment of the invention is provided. The external cavity laser apparatus includes a plurality of beam emitters that collectively emit a plurality of emitted beams that each includes a primary component emitted beam. A first reflective element is configured to reflect the plurality of primary component emitted beams and a first polarizing optic disposed in the optical path of the plurality of primary component emitted beams is configured to rotate a polarization of each primary component emitted beam to produce a first rotated primary component beam having a first linear polarization and a second rotated primary component beam having a second linear polarization. A polarized beam splitter is configured to direct first feedback system output component beams into an output beam, and to direct second feedback system output component beams to the plurality of beam emitters as feedback beams. |
| US09711948B2 |
Terahertz quantum cascade laser implementing a {hacek over (C)}erenkov difference-frequency generation scheme
A terahertz source implementing a {hacek over (C)}erenkov difference-frequency generation scheme in a quantum cascade laser. The laser includes an undoped or semi-insulating InP substrate with an exit facet that is polished at an angle between 10° to 40°. The laser further includes a first waveguide cladding layer(s) in contact with an active layer (arranged as a multiple quantum well structure) and a current extraction layer on top of the substrate. Furthermore, the laser includes a second waveguide cladding layer(s) on top of the active layer, where the first and second waveguide cladding layers are disposed to form a waveguide structure by which terahertz radiation generated in the active layer is guided inside the laser. The terahertz radiation is emitted into the substrate at a {hacek over (C)}erenkov angle relative to a direction of the nonlinear polarization wave in the active layer, and once in the substrate, propagates towards the exit facet. |
| US09711946B2 |
Vertical cavity surface emitting laser and atomic oscillator
A vertical cavity surface emitting laser includes: a substrate; a laminated body which is provided over the substrate; and a resin layer which is provided on at least a side surface of the laminated body, wherein the laminated body at least includes a first mirror layer provided over the substrate, an active layer provided over the first mirror layer, and a second mirror layer provided over the active layer, in a plan view, a length of the laminated body in a first direction is greater than a length of the laminated body in a second direction orthogonal to the first direction, and in the plan view, a length of the resin layer in the first direction is greater than a length of the resin layer in the second direction. |
| US09711945B2 |
Method of designing semiconductor laser device, method of designing raman amplifier, methods of manufacturing semiconductor laser device, semiconductor laser device, raman amplifier, and optical communication system
A method of designing a semiconductor laser device includes: controlling a distance between the output-side reflection unit and the second reflection unit and an effective optical feedback κ to the semiconductor laser element, the effective optical feedback κ defined by a below-presented formula (1) including a circulating time τ of the light in the semiconductor laser element, a reflectivity R1 of the output-side reflection unit, and a reflectivity R2 of the second reflection unit; selecting a semiconductor laser device in which an LFF period is equal to or smaller than 20 ns as a semiconductor laser device in which high speed switching occurs between an FBG mode and an FP mode; and using the selected semiconductor laser device as an semiconductor laser device oscillating in a coherent collapse mode. κ=(1/τ)×(1−R1)×(R2/R1)1/2 (1) |
| US09711940B2 |
Laser source with reduced linewidth
In the field of narrow linewidth laser sources and a laser device that comprises a laser source and a waveguide of determined refractive index with which it is coupled, a waveguide is single-mode and includes at least four reflectors in the form of trenches etched into the waveguide and irregularly distributed along the waveguide, the distance separating two neighbouring reflectors being above 1 μm, and the waveguide and the laser source have respective lengths such that the length of waveguide over which the reflectors are located is greater than the length of the laser source itself. |
| US09711933B1 |
Laser system and laser outputting method
A laser system and a laser outputting method are disclosed. The method comprises: providing a oscillator, wherein the oscillator comprises a pump light source, a cavity and a mode locked controller; utilizing the pump light source to emit a pump light into the cavity; outputting first laser pulses to the spectrum converter; utilizing a wavelength conversion chip of the spectrum converter to convert the first laser pulses to second laser pulses; utilizing at least one photo-detector to detect a power of the second laser pulses; controlling the mode locked controller to modulate a mode-locked status of the cavity when the power of the second laser pulses is lower than a threshold value. |
| US09711927B2 |
Heuristic laser device using an apparatus for producing laser pulses, and corresponding heuristic method
A laser device includes an apparatus for producing amplified laser pulses, using a plurality of amplifying optical fibers, and groups the basic amplified pulses into an overall amplified pulse, as well as a target, onto which the overall amplified pulse is directed such as to generate a predetermined physical process thereon, which causes a change of state in the target. The laser device is configured to measure at least one distinctive parameter of the generated physical process; adjust at least one characteristic for adjusting the basic amplified laser pulses; and analyze a plurality of measurements for different adjustments. The device analyzes the measurements many times in loops for different laser pulse adjustment characteristics, enabling an optimization by a heuristic method. Also provided is a heuristic optimization method implemented by the laser device. |
| US09711923B2 |
ARJ45 to RJ45 adapter
A communication adapter that includes an RJ45 jack with a plurality of plug interface contacts and an ARJ45 plug including a plurality of plug contacts. The plug interface contacts are in electrical communication with the plug contacts. The RJ45 jack and the ARJ45 plug are connected by a housing. |
| US09711920B2 |
System and connector configured for macro motion
A connecter system is configured for macro motion. Two mating terminals are configured so that during macro motion cycles, the resistance between two terminals does not substantially increase. One terminal can have multiple, somewhat spherical-shaped mating surfaces while a mating surface on the other terminal can be flat. The mating terminals can be configured to provide desirable resistance performance after more than 5000 cycles of macro motion. |
| US09711914B2 |
Cable connector assembly having a stopping member for avoiding light scattering
A cable connector assembly includes a cable and an electrical connector electrically connected with the cable, and the electrical connector includes a mating member, a printed circuit board electrically connected with the mating member, a light emitting element electrically connected with the printed circuit board and a light guide element for transmitting the light emitted by the light emitting element, having a receiving room, wherein the light emitting element is received in the receiving room, and the printed circuit board includes a soldering portion electrically connected with the matting member and an extension portion rearwardly extending from the soldering portion, and the cable connector assembly further includes a stopping member disposed between the soldering portion and the light guide element and abutting against the light guide element, to block the receiving room of the light guide element. |
| US09711910B2 |
Waterproof electrical connector assembly and method of manufacturing same
A waterproof electrical connector assembly includes: an insulative housing; plural contacts retained to the housing; a metallic shield secured to the housing; an insulative cover enclosing the shield to define a rear chamber; a substrate connected to the contacts and having an edge portion, the edge portion extending forwardly into the rear chamber; and a sealing member filling the rear chamber. A method for manufacturing such a waterproof electrical connector assembly includes: mounting a metallic shield to a combined insulative housing and electrical contacts; connecting a substrate to the electrical contacts; enclosing an insulative cover over the shield and an edge portion of the substrate to define a chamber; and sealing the chamber. |
| US09711908B2 |
Electrical connector having improved terminals
An electrical connector, defining an insertion port, a mating direction, a transverse direction perpendicular to the mating direction, and a vertical direction perpendicular to the mating direction and the transverse direction, includes an insulative housing, a number of terminals retained in the insulative housing, and a metal shell attached to the insulative housing. Each terminal has a soldering portion. The terminals have a number of grounding contacts, power contacts, and signal contacts. A maximum width of the power contact and the grounding contact is larger than that of the signal contact along the transverse direction. |
| US09711903B2 |
Connector system with RFID circuit
A connector is provided that includes an RFID circuit. Before the connector is mated with a corresponding connector the RFID circuit is tuned so that it does not function in a desired manner at a desired frequency. Once the connector is mated the tuning of the RFID circuit is modified so that the RFID circuit functions in the desired manner at the desired frequency. |
| US09711891B2 |
Electrical junction box with ventilation hole in a hood portion
An electrical junction box includes a circuit board and a case. The case holds the circuit board therein. The case includes case components bonded to each other such that the case components are liquid-tight to each other. One of the case components includes a connector portion that is liquid-tight to another portion of the one of the case components. The connector portion includes a hood portion to which a mating connector is to be connected. The hood portion includes a ventilation hole that communicates with internal space of the case. |
| US09711887B1 |
Electrical connector
An electrical connector includes an insulating housing, a terminal module, two adhesive films and a shielding shell. The insulating housing defines two rows of terminal grooves. The terminal module assembled to the insulating housing includes a plurality of conductive terminals. Front ends of the conductive terminals project into the terminal grooves. Each of the two adhesive films includes an insulation layer and an adhesive layer. The adhesive layer is disposed to a rear end of an inner surface of the insulation layer. The adhesive layer of one of the two adhesive films is adhered to a top wall of the insulating housing, and the adhesive layer of the other adhesive film is adhered to a bottom wall of the insulating housing. The insulating housing together with the terminal module and the adhesive films are received in a receiving space of the shielding shell. |
| US09711885B2 |
Fixing structure of separate leaf spring
A fitting cylinder section 11 of a female terminal main body 10 includes a first side plate 11a from which a columnar body 15 for a rivet protrudes as one in a plurality of side wall plates forming a square cylinder shape, a leaf spring 20 fixed to the fitting cylinder section 11 has a rivet insertion hole 21a into which the columnar body 15 for the rivet can be inserted, and the fitting cylinder section 11 has a structure in which the leaf spring 20 is fixed to an inner section thereof by performing the press-molding in the square cylinder shape section after rivet-retaining the leaf spring 20 to the first side plate 11a in a deployment shape and before performing the press-molding in the square cylinder shape. |
| US09711884B2 |
Terminal connection structure and semiconductor apparatus
A terminal connection structure includes a male terminal; and a female terminal having an elasticity and configured to have the male terminal fitted therein such that the female terminal sandwiches the male terminal from opposite sides; wherein the male includes a base material, a first primary coat coated on the base material, a second primary coat coated on the first primary coat, and a surface layer coated on the second primary coat, and the first primary coat and the second primary coat have different hardnesses. |
| US09711883B2 |
Cable connection structure and cable connector including same
A cable connector includes a connection end portion of a flexible board, in which a rectangular reinforcing plate molded of a conductive resin material is fixed to part of an upper surface of a ground plate. The connection end portion of the flexible board is electrically connected to a printed circuit board through the cable connector. |
| US09711882B2 |
Printed circuit board mounted terminal headers
An electrical terminal header assembly is configured for attachment to a substrate and includes a header body having a terminal mounting cavity formed therein and a first locking member. An electrical terminal has a terminal body and a terminal post extending outwardly from the terminal body, is disposed in the terminal mounting cavity, and is retained therein by the first locking member. The terminal post extends outwardly from the header body and is configured for attachment to the substrate. |
| US09711880B2 |
Connector with floating housing
A connector includes a plurality of contacts each including a contacting portion, provided at one end, that contacts a counterpart connector, a lead portion, provided at another end, that contacts a substrate, and a spring portion, provided between the contacting portion and the lead portion, that elastically deforms; a floating housing, fixed to the contacting portions of the plurality of contacts that are aligned in two columns of contacts, that fits with the counterpart connector; a first fixed housing, provided between the two columns of contacts, that is fixed to the substrate, and a second fixed housing, fixed to the first fixed housing, that sandwiches a portion adjacent to the lead portion of each of the plurality of contacts with the first fixed housing. |
| US09711879B2 |
Clamp interconnect
An apparatus including a bridge member and a clamp is disclosed. The bridge member is positioned in a first plane and has a substrate with a first surface and a second surface; and a plurality of distinct conductive pillars formed on the second surface of the substrate. The clamp has a body, a proximal end and a distal end. The body is positioned in a second plane above the first plane with the second plane being within 2 degrees of parallel to the first plane. The proximal end is positioned along the second plane; and the distal end has a plurality of prongs. The distal end is offset from the second plane in a direction toward the bridge member such that each prong contacts the first surface of the substrate. |
| US09711874B2 |
Terminal and manufacturing method of terminal
A terminal (10) is to be connected to an electric wire (W) which includes a core wire made of a fiber conductor (1). In a state of inserting a bare part of the fiber conductor in a barrel portion (11) of the terminal, the barrel portion is swaged while a swage amount is gradually increased as progressing in an electric wire insertion direction, which gradually expands the barrel portion in a width direction (D). |
| US09711869B1 |
Hexaferrite slant and slot MIMO antenna element
A MIMO antenna for mobile devices has a system board, and two or more microstrip lines extending along a top surface of the system board. The MIMO antenna additionally includes a ground plane extending along a bottom surface of the system board, wherein the ground plane has a Y-shaped slot. The MIMO antenna further includes one or more pairs of miniature antenna elements attached to the top surface of system board in contact with the at least two microstrip lines, wherein the antenna elements are slanted at ±45° with respect to a center Z of an X Y coordinate system, and center of a radiation sphere, located proximate the Y-shaped slot. |
| US09711868B2 |
In-building-communication apparatus and method
An In-Building Communications system is disclosed which permits communication in tunnels, underground parking garages, tall buildings such as skyscrapers, buildings having thick walls of concrete or metal, and/or any building which has communication dead zones due to electromagnetic shielding. The invention includes a portable bi-directional amplifier (BDA) system, an outdoor antenna system attached to the building or independently mountable, an indoor antenna system attached to the building or independently mountable inside the building, and a standardized, In-Building Communications (IBC) interface box affixed preferably to the exterior of the building. The interface box communicates with antenna systems attached to the building. The fire department or other emergency response personnel carry portable outdoor and indoor antenna systems and a portable, lithium-ion battery powered, bi-directional amplifier (BDA) system which may be connected to the building during an event such as a fire, earthquake, or an act of terrorism or whenever radio coverage enhancement is required. The portable BDA system is simply connected to the standardized, IBC interface box and powered thus restoring communications within. |
| US09711864B2 |
Antenna device of a mobile terminal
An antenna device of a mobile terminal having improved performance by utilizing a metal object located in proximity to the antenna device as an antenna radiator is provided. The antenna device includes an antenna pattern connected to a feeder and a ground line, and a metal component positioned on the antenna pattern and including a metal that forms an antenna radiator. |
| US09711861B2 |
Antenna device
An antenna device includes a dielectric substrate, a conductor plate that is placed on one surface of the dielectric substrate, that includes a first slot element, a second slot element, and one or more slits, and a ground conductor that is placed at a specified distance from the conductor plate in a first direction. A center of the first slot element is placed between a center of the second slot element and a center of each of slits, in a second direction. |
| US09711858B1 |
Impedance-controlled dual-feed antenna
Antenna structures and methods of operating the same of a dual-feed antenna of an electronic device are described. A dual-feed antenna includes a first antenna element coupled to a controllable circuit that is coupled a first radio frequency (RF) feed, and a second antenna element coupled to a second RF feed. The controllable circuit is configured to electrically connect the first antenna element to the first RF feed in a first antenna configuration and to electrically connect the first antenna element to ground in a second antenna configuration. During the second antenna configuration, the second antenna element is driven by the second RF feed. |
| US09711856B2 |
Electronic device and coil module
An electronic device incorporated with a coil module that achieves favorable communication characteristics is provided. In an electronic device incorporated with a coil module, the coil module includes a loop coil wounded in a planar shape and a sheet-shaped magnetic sheet which is formed of a magnetic material and which overlaps with a part of the loop coil, and the magnetic sheet is arranged on at least one side extending from a center of the loop coil. |
| US09711851B1 |
Unmanned vehicle, system and method for transmitting signals
Some embodiments are directed to an unmanned vehicle for transmitting signals. The unmanned vehicle includes a transmitting unit that is configured to transmit a signal towards an object. The unmanned vehicle also includes a control unit that is in communication with at least one companion unmanned vehicle. The control unit is configured to determine a position of the at least one companion unmanned vehicle relative to the unmanned vehicle. The control unit is further configured to control the transmitting element based on at least the position of the at least one unmanned vehicle such that the transmitting element forms a phased-array transmitter with a transmitting element of the at least one companion unnamed vehicle, the phased-array transmitter emitting a transmission beam in a predetermined direction. |
| US09711848B2 |
Antenna device and communication terminal apparatus
An antenna device includes an antenna element and an impedance converting circuit connected to the antenna element. The impedance converting circuit is connected to a power-supply end of the antenna element. The impedance converting circuit is interposed between the antenna element and a power-supply circuit. The impedance converting circuit includes a first inductance element connected to the power-supply circuit and a second inductance element coupled to the first inductance element. A first end and a second end of the first inductance element are connected to the power-supply circuit and the antenna, respectively. A first end and a second end of the second inductance element are connected to the antenna element and ground, respectively. |
| US09711847B2 |
Apparatus and method for integrating a reduced-sized antenna with an accessory connector
A system including a base affixed to a radio. The base includes a first base connector and a second base connector with a plurality of radial interconnectors positioned around the perimeter of the first base connector. The system includes an antenna connector including a first antenna connector and a second antenna connector with a plurality of radial interconnectors positioned around the perimeter of the first antenna connector. The first base connector is connected to the first antenna connector to form a central radio frequency (RF) coaxial connection and a first transmission line for a first antenna. The second antenna connector is connected to the second base connector to form a second transmission line and a plurality of radial connections around the perimeter of the central RF coaxial connection. The plurality of radial connections is configured to function as a signal carrier and/or an additional RF element. |
| US09711836B1 |
Tunable high isolation circulator
A system for improving port isolation of a three port circulator device includes a power splitter having a power splitter input and two power splitter outputs. A first circulator has a first circulator first port, a first circulator second port, and a first circulator third port, and the first circulator first port is electrically coupled to the first of the two power splitter outputs. A second circulator has a second circulator first port, a second circulator second port, and a second circulator third port, and the second circulator first port is electrically coupled to the second of the two power splitter outputs. A first trimmer is electrically coupled to the first circulator third port and a second trimmer is electrically coupled to the second circulator third port. The system further includes a power combiner having two power combiner inputs and one power combiner output, and the first of the two power combiner inputs is electrically coupled to the first trimmer and the second of the two power combiner inputs is electrically coupled to the second trimmer. |
| US09711835B2 |
Apparatus and methods related to junction ferrite devices having improved insertion loss performance
Disclosed are apparatus and methods related to junction ferrite devices having improved insertion loss performance. In some implementations, a ferrite disk assembly can be configured for a radio-frequency (RF) circulator. The disk assembly can include a ferrite-based disk having a ferrite portion and a metalized layer formed on a grounding surface of the disk to improve electrical contact between the grounding surface of the disk with an external grounding surface. The ferrite-based disk can further include a dielectric portion disposed around the periphery of the ferrite center portion. In some embodiments, the metalized layer can be a silver layer formed on the grounding surface of the disk and having a desired thickness. |
| US09711834B2 |
Irreversible circuit element and module
An irreversible circuit element includes first and second high pass isolators each including first and second center electrodes intersecting with and being insulated from each other on a ferrite to which a direct-current magnetic field is applied with a permanent magnet. One end of the first center electrode is an output port and the other end thereof is an input port, and one end of the second center electrode is another output port and the other end thereof is a ground port. A pass frequency band of the first isolator is higher than a pass frequency band of the second isolator. Respective output portions of the first and second isolators are electrically connected and defined as one output terminal, and a low pass filter LPF is inserted between the output terminal and the output port of the second isolator. |
| US09711831B2 |
Holographic mode conversion for transmission lines
The present disclosure provides systems and methods associated with mode conversion for electromagnetic field modification. A mode converting structure (holographic metamaterial) is formed with a distribution of dielectric constants chosen to convert an electromagnetic radiation pattern from a first mode to a second mode to attain a target electromagnetic radiation pattern that is different from the input electromagnetic radiation pattern. A solution to a holographic equation provides a sufficiently accurate approximation of a distribution of dielectric constants that can be used to form a mode converting device for use with one or more transmission lines, such as waveguides. One or more optimization algorithms can be used to improve the efficiency of the mode conversion. |
| US09711826B2 |
Nonaqueous electrolyte secondary battery
A nonaqueous electrolyte secondary battery is prevented from decreasing the remaining capacity and returned capacity at the time of continuous charge at high voltages and high temperatures. The battery has positive and negative electrodes, and a nonaqueous electrolytic solution containing ethylene carbonate and fluoroethylene carbonate as a solvent. The positive electrode contains a positive-electrode active material with the fine particles of a rare earth element compound deposited on its surface in a dispersed state. |
| US09711823B2 |
Electrolyte having eutectic mixture of hetero cyclic compound and lithium salt and electrochemical device containing the same
An electrolyte includes an eutectic mixture composed of (a) a hetero cyclic compound having a predetermined chemistry figure, and (b) an ionizable lithium salt. An electrochemical device having the electrolyte. The eutectic mixture included in the electrolyte exhibits inherent characteristics of an eutectic mixture such as excellent thermal stability and excellent chemical stability, thereby improving the problems such as evaporation, ignition and side reaction of an electrolyte caused by the usage of existing organic solvents. |
| US09711821B2 |
Lithium secondary battery and preparation thereof
The present invention provides a lithium secondary battery and the preparation thereof, more specifically a lithium secondary battery comprising an electrode assembly having a cathode, an anode, and a separator interposed between the cathode and the anode; and a non-aqueous electrolyte solution impregnated in the electrode assembly, wherein the separator further comprises a layer having a plurality of destroyed capsules dispersed therein, the layer being formed on at least one surface of the separator coming into contact with the cathode and the anode, and the destroyed capsules has a film formed from a binder polymer and inorganic particles dispersed therebetween. The lithium secondary battery of the present invention can be prepared without the separate introducing process of a non-aqueous electrolyte solution, and has a separator exhibiting improved mechanical property and safety. |
| US09711819B2 |
Mount structure for fuel cell stack
A mount structure includes a mount member, and a bracket member. An upper surface of the bracket member, which is connected to a lower portion of a fuel cell stack, includes an upper surface cut formed by cutting the bracket member in a depth direction, and the upper surface cut extends in a surface direction. A lower surface of the bracket member, which is opposite to the upper surface, includes a lower surface cut formed by cutting the bracket member in the depth direction, and the lower surface cut extends in the surface direction. |
| US09711816B2 |
Low equivalent weight polymers
Described herein is a composition comprising: a polymer derived from (a) a fluorinated olefin monomer; (b) a highly fluorinated sulfur-containing monomer of the formula: CX1X2═CX3[(CX4X5)w—O—R1—SO2Y] where X1, X2, X3, X4, and X5 are independently selected from H, Cl, or F; w is 0 or 1; R1 is a non-fluorinated or fluorinated alkylene group; and Y is selected from F, Cl, Br, I, or OM, where M is a cation; and (c) a polyfunctional monomer comprising at least two functional groups, wherein the functional groups are selected from the group consisting of: (i) a fluorovinyl ether group, (ii) a fluoroallyl ether group, (iii) a fluorinated olefinic group, and (iv) combinations thereof; articles thereof; and a method of making such polymers. |
| US09711814B2 |
Fuel cell system and control method therefor
A fuel cell system includes an accumulated current value measuring unit. The accumulated current value measuring unit measures an accumulated current value by time integration of current output from the fuel cell in a period during which oxygen is produced by water-splitting reaction in an anode of a negative voltage cell. A control unit uses a first correlation between the accumulated current value in the oxygen generation period and an oxygen consumption rate in the anode and a second correlation between a current density of the fuel cell in the oxygen generation period and an oxygen production rate in the anode to obtain a current density at or below which the amount of oxygen in the anode may be reduced, and causes the fuel cell to output electric power at a current density lower than the obtained current density. |
| US09711813B2 |
Fuel cell system and start up control method for the fuel cell system
A scavenging process is performed on the anode side by opening an air supply valve to remove liquid droplets in a fuel gas flow field using the compressed air from an air compressor. During the scavenging process, when a start up signal from an ignition switch is received, the start up of a fuel cell is prohibited until the gas in the fuel gas flow field is replaced completely by air. |
| US09711811B2 |
End plate of fuel cell
An end plate arranged on one end of a fuel cell unit includes a plate body, which is formed from a metal material, and a gas-liquid separator, which includes a housing into which emission from the fuel cell unit is drawn in. The gas-liquid separator separates water from the emission and drains the separated water out of the housing. The housing is formed from a resin material and is in contact with the plate body. |
| US09711806B2 |
Device and method for heating fuel cell stack and fuel cell system having the device
Provided is device and method for heating fuel cell stack and fuel cell system having the device. The fuel cell system includes: a power generating unit having fuel cell stacks arranged with an interval defined between the stacks; an outlet manifold unit provided outside each fuel cell stack and guiding a reaction mixture discharged from each stack to outside; an inlet manifold unit provided on each stack at a location opposed to the outlet manifold unit based on the stack, the inlet manifold unit supplying fuel and air supplied through a fuel supply pipe and an air supply pipe into the stack; and a subsidiary fuel supply unit for supplying subsidiary fuel into the outlet manifold unit such that the subsidiary fuel is burnt in the outlet manifold unit so as to heat both the outlet manifold unit and the stack coming into contact with the outlet manifold unit. |
| US09711803B2 |
Carbon catalyst, method for manufacturing the carbon catalyst, and electrode and battery using the carbon catalyst
Provided are a carbon catalyst having an excellent activity and a method of manufacturing a carbon catalyst, and an electrode and a battery each using the carbon catalyst. The method of manufacturing a carbon catalyst according to the present invention includes a carbonizing step S2, the step involving heating a raw material containing a thermoplastic resin, a metal, and a conductive carbon material to coat the surface of the conductive carbon material with the molten thermoplastic resin and to carbonize the thermoplastic resin on the surface of the conductive carbon material so that the carbon catalyst is obtained. |
| US09711802B2 |
Preparing method of alloy catalyst using polydopamine coating and alloy catalyst thereby
Provided is a method for preparing an alloy catalyst for fuel cells having excellent catalytic activity and high durability. The method includes coating a platinum or platinum-transition metal catalyst supported on carbon with polydopamine as a capping agent. The method for preparing an alloy catalyst supported on carbon uses polydopamine as a capping agent for a platinum or platinum-transition metal catalyst supported on carbon, and thus provides a binary or ternary platinum alloy catalyst supported on carbon having a small particle size and high alloying degree despite the subsequent high-temperature heat treatment. In addition, polydopamine (PDA) is a highly adhesive material and allows thin and uniform coating, and thus inhibits particle size growth during heat treatment while allowing easy diffusion of a transition metal into the metal. As a result, it is possible to provide an alloy catalyst provided with a core-shell structure having a surface layer formed of platinum alone and showing a high alloying degree. Finally, it is possible to provide an alloy catalyst having excellent catalytic activity and durability. Further, since polydopamine (PDA) is capable of self-polymerization at room temperature, PDA coating is carried out without additional reagents or equipment. Thus, the method has high processability and cost-efficiency. |
| US09711801B2 |
Three-dimensional net-like aluminum porous body, electrode using the aluminum porous body, nonaqueous electrolyte battery using the electrode, and nonaqueous electrolyte capacitor using the electrode
Provided are a three-dimensional net-like aluminum porous body in which the diameter of cells in the porous body is uneven in the thickness direction of the porous body; a current collector and an electrode each using the aluminum porous body; and methods for producing these members. The porous body is a three-dimensional net-like aluminum porous body in a sheet form, for a current collector, in which the diameter of cells in the porous body is uneven in the thickness direction of the porous body. When a cross section in the thickness direction of the three-dimensional net-like aluminum porous body is divided into three regions of a region 1, a region 2 and a region 3 in this order, the average cell diameter of the regions 1 and 3 is preferably different from the cell diameter of the region 2. |
| US09711799B1 |
Copper foil having uniform thickness and methods for manufacturing the copper foil
The present disclosure relates to an improved electrodeposited copper foil having uniform thickness and methods for manufacturing the electrodeposited copper foil. The electrodeposited copper foil typically has one to four interfacial lines through the cross-sectional area of the foil and a weight deviation less than 2.0%. The disclosure also relates to a process for making the electrodeposited copper foil that includes the addition of one or more insulative masks to the surface of a dimensionally stable anode. The insulative mask is cut to correspond to areas of variation in electrodeposited copper foil, such that the mask causes interferences with the electrodeposition process to even out the variation. |
| US09711798B2 |
Lithium electrode and lithium secondary battery comprising the same
The present disclosure relates to a lithium electrode, comprising an electrode composite comprising a porous metallic current collector, and lithium metal inserted into pores present in the metallic current collector; and a protective membrane for lithium ion conduction, the protective membrane being formed on at least one surface of the electrode composite.The lithium electrode according to the present disclosure can increase contact surface between lithium metal and a current collector to improve the performances of a lithium secondary battery, and can exhibit uniform electron distribution therein to prevent the growth of lithium dendrites during the operation of a lithium secondary battery, thereby improving the safety of a lithium secondary battery. Furthermore, even though the lithium electrode is coated with a protective membrane for lithium ion conduction on the surface thereof, the protective membrane can be prevented from being peeled off during the charge and discharge of a lithium secondary battery. |
| US09711797B2 |
Coated particles for lithium battery cathodes
Particles of cathodic materials are coated with polymer to prevent direct contact between the particles and the surrounding electrolyte. The polymers are held in place either by a) growing the polymers from initiators covalently bound to the particle, b) attachment of the already-formed polymers by covalently linking to functional groups attached to the particle, or c) electrostatic interactions resulting from incorporation of cationic or anionic groups in the polymer chain. Carbon or ceramic coatings may first be formed on the surfaces of the particles before the particles are coated with polymer. The polymer coating is both electronically and ionically conductive. |
| US09711796B2 |
Binder composition for secondary battery, cathode and lithium battery including the binder composition
In an aspect, a binder composition for a secondary battery including a first fluoropolymer binder including a tetrafluoroethylene polymer binder, a second fluoropolymer binder including a vinylidene fluoride binder, and a non fluoropolymer binder is provided. |
| US09711795B2 |
Anode electrodes for secondary battery and lithium secondary battery containing the same
Disclosed is an anode for secondary batteries, in which an anode mixture including an anode active material and a binder is coated on a current collector, wherein the binder includes a homopolymer having a molecular weight of 1,000,000 to 1,400,000 and the anode active material includes a lithium metal oxide represented by Formula 1 below: LixMyOz (1) wherein M is Ti, Sn, Cu, Pb, Sb, Zn, Fe, In, Al, or Zr; and x, y, and z are determined according to oxidation number of M. |
| US09711794B2 |
Lithium secondary battery having anode containing aqueous binder
Disclosed is a lithium secondary battery that includes an anode coated with an anode mixture including an anode active material, a cathode coated with a cathode mixture including a cathode active material, and a non-aqueous electrolyte, wherein the anode mixture includes, as aqueous binders, carboxymethyl cellulose (CMC) having a degree of substitution of a hydroxyl group (—OH) with a carboxymethyl group (—CH2CO2H) of 0.7 to 1.2, a molecular weight (Mn) of 500,000 to 900,000, and a pH of 6.5 to 8.0 and styrene-butadiene rubber (SBR) having a particle diameter of 90 nm to 150 nm and a tensile strength of 90 kgf to 160 kgf, and the anode has an electrode coating amount of 10 to 20 mg/cm2 and that enhances electrode processability and reduces a swelling phenomenon. |
| US09711793B2 |
Vanadium oxysulfide based cathode materials for rechargeable battery
A cathode active composite containing an amorphous composite of vanadium oxide and an inorganic sulfide is provided. In one embodiment the composite contains vanadium pentoxide and phosphorous pentasulfide. An elctrochemical cell and a reversible battery having a cathode containing the cathode active composite are also provided. In one embodiment the battery is a magnesium battery. |
| US09711791B2 |
Non-aqueous organic electrolyte secondary cell
In a non-aqueous organic electrolyte secondary cell, the counter charge capacity ratio (A/C) between the cathodes and the anodes represented by the following formula is set to within the range from 1.10 to 1.35, A/C=β×(anode charge capacity×α)/(cathode charge capacity×η×τ) where α is the electrode area coefficient defined as (anode area)/(cathode area) and α>1.0, β is a design coefficient and 0.85≦β≦1.15, η is the charge-discharge efficiency ratio defined as (charge-discharge ratio at 25° C.)/(charge-discharge ratio at 55° C.), and τ is the temperature characteristic coefficient defined as (charge capacity at 55° C.)/(charge capacity at 25° C.). |
| US09711790B2 |
Nonaqueous electrolyte battery and battery pack
According to one embodiment, a nonaqueous electrolyte battery including a positive electrode and a negative electrode is provided. The positive electrode includes LiNixM1−xO2 wherein M is a metal element including Mn, and x is within a range of 0.5≦x≦1. The negative electrode includes graphitized material particles and a layer. The graphitized material particles have an interplanar spacing of (002), according to an X-ray diffraction method, of 0.337 nm or less. The layer includes a titanium-containing oxide. The layer covers at least a part of a surface of the graphitized material particles. |
| US09711785B2 |
Negative electrode slurry composition, lithium ion secondary battery negative electrode, and lithium ion secondary battery
Provided is a negative electrode slurry composition including a binder resin, a water-soluble polymer, and a negative electrode active material, wherein the binder resin including (A) a styrene-butadiene copolymer latex having a gel amount of 70 to 98% and having a glass transition temperature in dynamic viscoelasticity measurement with a single peak at −30° C. to 60° C. and (B) a polymer latex formed of a hetero-phase structure having a glass transition temperature in dynamic viscoelasticity measurement with at least one peak at −100° C. to 10° C. and having a glass transition temperature in dynamic viscoelasticity measurement with at least one peak at 10° C. to 100° C., and the negative electrode active material including a carbon-based active material and a silicon-based active material. |
| US09711784B2 |
Electrode fabrication methods and associated systems and articles
Sulfur-based electrodes, and associated systems and methods for their fabrication, are generally described. Certain embodiments relate to sulfur-based electrodes with smooth external surfaces. According to some embodiments, relatively large forces can be applied to compositions from which the sulfur-based electrodes are made during the fabrication process. In some such embodiments, the compositions can maintain relatively high porosities, even after the relatively large forces have been applied to them. Methods in which liquids are employed during the electrode fabrication process are also described. |
| US09711782B2 |
Positive electrode and nonaqueous electrolyte battery
According to one embodiment, there is provided a positive electrode including a positive electrode active material-including layer including a positive electrode active material, which includes a lithium-manganese oxide LiMn2-xMxO4, and a conductive agent. In the positive electrode active material-including layer, an average particle diameter d50 is within 2 μm to 5 μm, a particle diameter d10 and a particle diameter d90, where a cumulative frequency from a smaller side is, respectively, 10% and 90%, is within 0.5 μm to 3 μm and within 4 μm to 10 μm, respectively, in a particle size distribution. X, represented by X=(d50−d10) /d50 is within 0.4 to 0.8. Y, represented by Y=(d90−d50)/d90 is within 0.2 to 0.6. |
| US09711780B2 |
Battery pack containing PCM employed with safety member having a protection circuit with a fusing part
A battery pack including a battery cell having an electrode assembly of a cathode/separator/anode structure mounted in a battery case together with an electrolyte in a sealed state, and a protection circuit module (PCM) electrically connected to the battery cell. The PCM includes a protection circuit board (PCB) electrically connected to the battery cell, the PCB being provided on a region where a circuit is connected with a conductive pattern including a fusing part, having relatively high resistance, configured to fuse itself for interrupting the flow of current when a large amount of current is conducted. |
| US09711772B2 |
Porous separator with water-based organic/inorganic complex coating, a method for preparing the same, and an electrochemical device using the same
There is provided a separator used in an electrochemical device and more particularly, to a porous separator in which an organic/inorganic complex coating layer is applied to a porous substrate, a method for preparing the same, and an electrochemical device using the same. |
| US09711771B2 |
Porous membranes filled with nano-particles, separators, batteries, and related methods
A membrane includes a porous membrane or layer made of a polymeric material having a plurality of surface treated (or coated) particles (or ceramic particles) having an average particle size of less than about 1 micron dispersed therein. The polymeric material may be selected from the group consisting of polyolefins, polyamides, polyesters, co-polymers thereof, and combinations thereof. The particles may be selected from the group consisting of boehmite (AlOOH), SiO2, TiO2, Al2O3, BaSO4, CaCO3, BN, and combinations thereof, or the particles may be boehmite. The surface treatment (or coating) may be a molecule having a reactive end and a non-polar end. The particles may be pre-mixed in a low molecular weight wax before mixing with the polymeric material. The membrane may be used as a battery separator. |
| US09711766B2 |
Energy storage apparatus
An energy storage apparatus includes a base arranged adjacently to an energy storage device and forming a passage between the base and the energy storage device, a holder that holds the energy storage device and a spacer, and an insulator arranged between the spacer and the holder. The insulator includes a first insulating portion arranged between the spacer and the holder, and a first sealing portion being in contact with an extending portion. |
| US09711765B1 |
Rapid replacement battery system
A replacement battery system design incorporating a pivoting battery holster and other features enabling one-handed battery removal for devices requiring a battery. |
| US09711757B2 |
Organic electroluminescent display device and method of manufacturing the same
An organic electroluminescent display device including a rear substrate, an organic electroluminescent portion disposed on a surface of the rear substrate, the organic electroluminescent portion including a first electrode, an organic layer, and a second electrode in sequence, a front substrate coupled to the rear substrate at an internal surface of the front substrate to seal an internal space in which the organic electroluminescent portion is accommodated, thereby isolating the organic electroluminescent portion from the outside, a transparent moisture-absorbing layer coated on the internal surface of the front substrate, and a sealant disposed between the rear substrate and the transparent moisture-absorbing layer to couple the front substrate and the rear substrate. |
| US09711756B2 |
Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus includes: a substrate; a pixel electrode disposed on the substrate; an intermediate layer that is disposed on the pixel electrode and includes an organic light-emitting layer; a facing electrode disposed on the intermediate layer; and a thin film encapsulating layer disposed on the facing electrode, wherein the thin film encapsulating layer includes: a first inorganic film and a second inorganic film, which are disposed on the facing electrode; a first organic film that is disposed between the first inorganic film and the second inorganic film and has a first thickness; and a second organic film that is disposed on the second inorganic film and has a second thickness greater than the first thickness. |
| US09711750B1 |
Method of forming a conductive pattern and method of manufacturing an organic light-emitting display including the same
A conductive material layer for forming a conductive pattern is formed on a substrate. A photosensitive organic material layer is formed on the conductive material layer. The photosensitive organic material layer is irradiated through a halftone mask. The halftone mask includes a first mask region having a boundary corresponding to an edge of the conductive pattern, a second mask region, and a third mask region disposed between the first mask region and the second mask region. A first pattern including a first region corresponding to the first mask region and a second region corresponding to the third mask region is formed by removing the photosensitive organic material layer. The conductive material layer is etched using the first pattern as a hard mask to form the conductive pattern having exposed lateral surfaces. A second pattern is formed that covers the lateral surfaces of the conductive pattern by reflowing the first pattern. |
| US09711749B2 |
Organic light emitting display apparatus and method for manufacturing the same
An organic light emitting display (OLED) device, and a method for manufacturing the OLED device are discussed. The OLED device according to one embodiment includes a substrate; an anode formed on the substrate; a bank formed on the substrate to partially overlap the anode; an organic light emitting element including a portion of a common layer on the anode and another portion of the common layer on the bank, the portion of the common layer on the bank being thinner than the another portion of the common layer on the anode; and a cathode fanned above the portion of the common layer on the anode and the another portion of the common layer on the bank. |
| US09711747B2 |
White organic light emitting device
Disclosed is a white organic light emitting device for enhancing emission efficiency and a color viewing angle or a color reproduction rate. The white organic light emitting device includes a first emission part between a first electrode and a second electrode, the first emission part having a first emission layer, a second emission part on the first emission part, the second emission part having a second emission layer, and a third emission part on the second emission part, the third emission part having a third emission layer. At least two emission layers of the first to third emission layers emit lights having a same color to enhance emission efficiency and a color viewing angle, and the at least two emission layers are adjacent to each other. |
| US09711743B1 |
Reconfigurable electronics using conducting metal-organic frameworks
A device including a porous metal organic framework (MOF) disposed between two terminals, the device including a first state wherein the MOF is infiltrated by a guest species to form an electrical path between the terminals and a second state wherein the electrical conductivity of the MOF is less than the electrical conductivity in the first state. A method including switching a porous metal organic framework (MOF) between two terminals from a first state wherein a metal site in the MOF is infiltrated by a guest species that is capable of charge transfer to a second state wherein the MOF is less electrically conductive than in the first state. |
| US09711742B2 |
Four coordinated platinum and palladium complexes with geometrically distorted charge transfer state and their applications in light emitting devices
Described herein are platinum and palladium compounds with geometrically distorted charge transfer state, applications and methods for the preparation thereof. The platinum and/or palladium compounds described herein are capable of emitting light and can be used in light emitting devices. |
| US09711737B2 |
Photoelectric conversion element and solid-state imaging device
Provided is a photoelectric conversion element including a photoelectric conversion material layer that is constituted by an organic material having more excellent sensitivity and responsiveness than those of conventional ones.The photoelectric conversion element of the present invention includes: (a-1) a first electrode and a second electrode which are disposed apart from each other; and (a-2) a photoelectric conversion area which is disposed between the first electrode and the second electrode, wherein the photoelectric conversion area includes multiple layers and at least one of the multiple layers is formed of a dioxaanthanthrene-based compound represented by the structural formula (1). |
| US09711735B2 |
Delayed fluorescence compound, and organic light emitting diode and display device using the same
Discussed is a delayed fluorescence compound of Formula 1: wherein n is 1 or 0, and A is selected from Formula 2: wherein D is selected from Formula 3: and each of “L1” and “L2” is independently selected from Formula 4: wherein R1 in the Formula 2 is selected from hydrogen or phenyl, and each of X, Y, and Z is independently selected from carbon and nitrogen, and wherein at least two selected from X, Y, and Z are nitrogen, and R2 in the Formula 4 is selected from one of hydrogen and C1 alkyl through C10 alkyl. |
| US09711734B2 |
Organic light-emitting device
An organic light-emitting device including a first electrode; a second electrode facing the first electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer, wherein the organic layer includes a first compound represented by Formula 1, below, and a second compound represented by Formula 2, below, |
| US09711725B2 |
Method for producing organic semiconductor element
In the method for producing an organic semiconductor element having a semiconductor layer according to the present invention, an optical system for irradiating a laser beam with a wavelength of at least 4 μm and a donor substrate prepared by forming an organic semiconductor film on a surface of a supporting member having a laser beam transmittance of at least 50% are used; and the donor substrate and a substrate to be treated serving as a semiconductor element are opposite one another; the laser beam is irradiated from the supporting member side; the laser beam is scanned while modulating in accordance with the semiconductor layer to be formed; and the organic semiconductor film is transferred to the substrate to be treated so as to form the semiconductor layer. |
| US09711724B2 |
Mask and mask assembly
A mask has both ends supported on a frame while tensile force is applied in a first direction. The mask includes: a mask main body having a band shape which is extended in the first direction; a plurality of active patterns spaced apart in the first direction from each other in the mask main body and having a first shape; a plurality of first ribs surrounding borders of the plurality of respective active patterns and defining a shape of the active pattern; and a plurality of first dummy patterns surrounding the plurality of first ribs, respectively, and having a second shape. |
| US09711723B2 |
Display and method of manufacturing the same, unit, transfer printing method, organic electroluminescence unit and method of manufacturing the same, and electronic apparatus
A display includes: a first light emitting layer to be transferred to a first region on a substrate; a second light emitting layer to be transferred to a second region on the substrate; and a level-difference forming member forming a first level difference between the first region and the second region, the first level difference suppressing attachment of the first light emitting layer to the second region when the first light emitting layer is transferred to the first region. |
| US09711710B2 |
Piezoelectric sheet, method for manufacturing piezoelectric sheet, and manufacturing apparatus
A specific region of a polylactic acid sheet is heated by a microwave. To allow the polylactic acid sheet to exhibit piezoelectricity in the thickness direction of the polylactic acid sheet, a high voltage is applied to the heated polylactic acid sheet in the thickness direction of the polylactic acid sheet, and thereby the screw axes of at least a part of the polylactic acid molecules are relatively aligned with the thickness direction. Then the polylactic acid sheet is rapidly cooled, and thereby the polylactic acid molecules are immobilized. The same step is executed for other regions of the polylactic acid sheet, and thereby piezoelectricity is imparted to a wide area of the polylactic acid sheet in the thickness direction. The resultant piezoelectric sheet is capable of exhibiting a high piezoelectricity in the thickness direction. |
| US09711709B2 |
Transducer systems
Transducer systems with reduced acoustic noise coupling are disclosed herein. In some embodiments, a transducer system includes pressure balancing features to prevent a floating portion of the transducer system from contacting a fixed portion of the transducer system, or to reduce the degree to which the floating portion is urged into contact with the fixed portion by process pressure or atmospheric pressure. In some embodiments, a transducer system includes one or more acoustic dampening elements, interruption grooves, annular projections, or dampening washers to reduce acoustic noise coupling between various components of the transducer system or between the transducer system and a flowcell in which the transducer system is mounted. |
| US09711707B2 |
Method for manufacturing an electronic device
A method for manufacturing an electronic device includes a through electrode forming step of forming a through electrode on an insulating base substrate; an electronic element mounting step of mounting an electronic element on one surface of the base substrate; a cover body placing step of bonding a cover body accommodating the electronic element; a conductive film forming step of forming a conductive film on the other surface of the base substrate and on an end face of the through electrode exposing on the other surface; an electrode pattern forming step of forming an electrode pattern on the end face of the through electrode and on the surface of the periphery of the end face while leaving the conductive film; and an external electrode forming step of forming an external electrode by accumulating an electroless plated film on the surface of the electrode pattern by an electroless plating method. |
| US09711702B2 |
Light emitting device and method of manufacturing the same
Disclosed is a light emitting device and a method of manufacturing the same. The light emitting device includes a body, a first electrode installed in the body and a second electrode separated from the first electrode, a light emitting chip formed on one of the first and second electrodes, and electrically connected to the first and second electrodes, and a protective cap projecting between the first and second electrodes. |
| US09711701B2 |
High-voltage solid-state transducers and associated systems and methods
High-voltage solid-state transducer (SST) devices and associated systems and methods are disclosed herein. An SST device in accordance with a particular embodiment of the present technology includes a carrier substrate, a first terminal, a second terminal and a plurality of SST dies connected in series between the first and second terminals. The individual SST dies can include a transducer structure having a p-n junction, a first contact and a second contact. The transducer structure forms a boundary between a first region and a second region with the carrier substrate being in the first region. The first and second terminals can be configured to receive an output voltage and each SST die can have a forward junction voltage less than the output voltage. |
| US09711700B2 |
Light emitting device and method for producing the same
A light emitting device includes a light emitting element and a package. The package includes a first lead frame, a second lead frame, and a resin. The first lead frame has a first surface on which the light emitting element is provided. The first lead frame has a first overlap portion. The second lead frame is spaced apart from the first lead frame and has a second overlap portion. The first overlap portion and the second overlap portion overlap at an overlap position so that the first lead frame extends from the overlap position toward a first direction and a second direction opposite to the first direction and so that the second lead frame extend from the overlap position toward a third direction and a fourth direction opposite to the third direction as viewed along a line substantially perpendicular to the first surface. |
| US09711697B2 |
Terahertz modulator
According to one aspect, the present invention concerns a terahertz modulator (1) intended to be used in a given frequency band of use. The modulator comprises a semi-conductor polar crystal (330) presenting a Reststrahlen band overlapping said frequency band of use and presenting at least one interface with a dielectric medium, coupling means (330) allowing the resanant coupling of an interface phonon polariton (IPhP) supported by said interface and of an incident radiation (2) of pre-determined frequency lying in said frequency band of use and means of control (22) apt to modify the intensity of the coupling between said interface phonon polariton and said incident radiation (2) by modification of the dielectric function of the polar crystal in the Reststrahlen band of the polar crystal (10). |
| US09711693B2 |
Method of fabricating semiconductor device using gang bonding and semiconductor device fabricated by the same
A semiconductor device including a first lead electrode and a second lead electrode; a semiconductor stack structure disposed on the member, the semiconductor stack structure including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active region interposed between the first and second conductive semiconductor layers; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; a plating layer configured to bond the semiconductor stack structure to the member; and a first wavelength converter that covers at least side surfaces of the semiconductor stack structure. |
| US09711692B2 |
Display device using semiconductor light emitting devices having different structures
A display device using semiconductor light emitting devices is disclosed. The display device includes a substrate, a plurality of first electrodes disposed on the substrate, a light emitting device array comprising a plurality of semiconductor light emitting devices electrically connected to the first electrodes, constituting individual pixels, and having different brightnesses increasing from one side of a current input direction of each of the first electrodes to the other side of the current input direction, and a plurality of second electrodes electrically connected to the semiconductor light emitting devices. Thus, brightness variation caused by power loss may be reduced in a display device of PM type using light emitting device array, thereby reducing load effect that is a problem of the device of PM type using light emitting device array. |
| US09711687B2 |
Light emitting device with improved extraction efficiency
In embodiments of the invention, a semiconductor structure comprising a III-nitride light emitting layer disposed between an n-type region and a p-type region is grown on a substrate. The substrate is a non-III-nitride material. The substrate has an in-plane lattice constant asubstrate. At least one III-nitride layer in the semiconductor structure has a bulk lattice constant alayer and [(|asubstrate−alayer|)/asubstrate]*100% is no more than 1%. A surface of the substrate opposite the surface on which the semiconductor structure is grown is textured. |
| US09711685B2 |
Sapphire substrate and method for manufacturing the same and nitride semiconductor light emitting element
A sapphire substrate provided with a plurality of projections on a principal surface on which a nitride semiconductor is grown to form a nitride semiconductor light emitting element. The projections have a substantially triangular pyramidal-shape the projections having a plurality of side surfaces and a pointed top. The side surfaces have an inclination angle of between 53° and 59° from a bottom of the projections. The side surfaces are crystal-growth-suppressed surfaces on which a growth of the nitride semiconductor is suppressed relative to a portion of the principal surface located between adjacent projections. A bottom of the projections has a substantially triangular shape having three outwardly curved arc-shaped sides, and each of the side surfaces has a substantially triangular shape having vertexes located at the top of the projection and at both ends of a respective side of the bottom of the projection. |
| US09711683B2 |
Semiconductor device and the method of manufacturing the same
The present application discloses a semiconductor device comprising a crystalline substrate having a first region and a second region, a nuclei structure on the first region, a first crystalline buffer layer on the nuclei structure, a void between the second region and the first crystalline buffer layer, a second crystalline buffer layer on the first crystalline buffer layer, an intermediate layer located between the first crystalline buffer layer and the second crystalline buffer layer, and a semiconductor device layer on the second crystalline buffer layer. |
| US09711674B2 |
Methods for producing photovolaic material and device able to exploit high energy photons
The present invention concerns methods for producing photovoltaic material and a device able to exploit high energy photons. The photovoltaic material is obtained from a conventional photovoltaic material having a top surface intended to be exposed to photonic radiation, having a built-in P-N junction delimiting an emitter part and a base part and comprising at least one area or region specifically designed, treated or adapted to absorb high energy or energetic photons, located adjacent or near at least one hetero-interface. According to the invention, this material is subjected to treatments resulting in the formation of at least one semiconductor based metamaterial field or region being created, as a transitional region of the or a hetero-interface, in an area located continuous or proximate to the or an absorption area or region for the energetic photons of the photonic radiation impacting said photovoltaic material. |
| US09711673B2 |
Display device with photovoltaic cells integrated into the screen and improved screen luminosity and reflectivity
A display device comprising at least: (a) a plurality of photovoltaic active areas and a plurality of holes, two neighboring photovoltaic active areas forming an opening; (b) one or more artificial light sources; (c) a plurality of light concentrators and reflective opaque disposed between said light sources and said photovoltaic active areas. This device wherein said hubs of light are arranged so that the light emitted from artificial light sources is directed by the light concentrators through the holes. |
| US09711672B2 |
Heating and power generating apparatus using solar energy
A heating and power generating apparatus comprises: a frame installed on the roof of a building and having a predetermined area; a plurality of power generating units arranged inside the frame to collect sunlight and generate electricity; and a hot water supply unit buried inside of the frame to absorb sunlight and perform heating and hot water supply. According to the present invention, hot water can be generated by sunlight in the winter to supply hot water and heat a house, and power can be generated by sunlight in the summer to supply power for cooling a room and thus conserve the electrical energy used in a cooler, thus promoting energy saving and environmental protection. |
| US09711664B2 |
Flexible transparent solar cell and production process of the same
The invention provides a flexible transparent solar cell and a production process of the same, and belongs to the technical field of solar cell. The flexible transparent solar cell comprises: a flexible transparent substrate, a transparent front-electrode, a cell unit, a transparent back-electrode and a transparent encapsulating layer, which are disposed in this order; the transparent front-electrode comprising a metallic grid thin film layer and a graphene layer; and the transparent back-electrode comprising a nano metal layer and a graphene layer. The invention can be used in production of flexible transparent solar cell, in order to improve conductivity and transparency of solar cells. |
| US09711661B2 |
Semiconductor device and manufacturing method thereof
A technique of suppressing leak current in a semiconductor device is provided. A semiconductor device, comprises: a semiconductor layer made of a semiconductor; an insulating layer configured to have electric insulation property and formed to cover part of the semiconductor layer; a first electrode layer formed on the semiconductor layer, configured to have a work function of not less than 0.5 eV relative to electron affinity of the semiconductor layer and extended to surface of the insulating layer to form a field plate structure; and a second electrode layer configured to have electrical conductivity and formed to cover at least part of the first electrode layer. A distance between an edge of a part of the first electrode layer that is in contact with the semiconductor layer and the second electrode layer is equal to or greater than 0.2 μm. |
| US09711657B2 |
Silicide process using OD spacers
A device includes a semiconductor substrate including an active region. The active region includes a first sidewall. An isolation region extends from a top surface of the semiconductor substrate into the semiconductor substrate. The isolation region has a second sidewall, wherein a lower portion of the first sidewall joins a lower portion of the second sidewall to form an interface. A dielectric spacer is disposed on an upper portion of the first sidewall. A silicide region is over and contacting the active region. A sidewall of the silicide region contacts the dielectric spacer, and the dielectric spacer has a top surface substantially lower than a top surface of the silicide region. |
| US09711656B2 |
Semiconductor device
To provide a semiconductor device having a structure capable of suppressing deterioration of its electrical characteristics which becomes apparent with miniaturization. The semiconductor device includes a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a source electrode and a drain electrode in contact with the second oxide semiconductor film; a third oxide semiconductor film over the second oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the third oxide semiconductor film; and a gate electrode over the gate insulating film. A first interface between the gate electrode and the gate insulating film has a region closer to the insulating surface than a second interface between the first oxide semiconductor film and the second oxide semiconductor film. |
| US09711652B2 |
Semiconductor device
A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor device is provided which includes a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide insulating layer over the gate insulating layer, an oxide semiconductor layer being above and in contact with the oxide insulating layer and overlapping with the gate electrode layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer includes a silicon film containing nitrogen. The oxide insulating layer contains one or more metal elements selected from the constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is larger than that of the oxide insulating layer. |
| US09711649B2 |
Transistors incorporating metal quantum dots into doped source and drain regions
Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions. |
| US09711647B2 |
Thin-sheet FinFET device
A thin-sheet non-planar circuit device such as a FinFET and a method for forming the device is disclosed. In some exemplary embodiments, the device includes a substrate having a top surface and a feature disposed on the substrate that extends above the top surface. A material layer disposed on the feature. The material layer includes a plurality of source/drain regions and a channel region disposed between the source/drain regions. A gate stack is disposed on the channel region of the material layer. In some such embodiments, the feature includes a plurality of side surfaces, and the material layer is disposed on each of the side surface surfaces. In some such embodiments, the feature also includes a top surface and the material layer is further disposed on the top surface. In some embodiments, the top surface of the feature is free of the material layer. |
| US09711645B2 |
Method and structure for multigate FinFET device epi-extension junction control by hydrogen treatment
Embodiments are directed to forming a structure comprising at least one fin, a gate, and a spacer, applying an annealing process to the structure to create a gap between the at least one fin and the spacer, and growing an epitaxial semiconductor layer in the gap between the spacer and the at least one fin. |
| US09711642B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes: an n-type first source region and first drain region formed in a surface of a p-type epitaxial layer; an n-type first source drift region and first drain drift region formed so as to individually surround the first source region and the first drain region; and a p-type first diffusion region formed in a first channel region and having a higher concentration than the epitaxial layer, the semiconductor device having p-type first withstand voltage maintaining regions formed between the first diffusion region, and the first source drift region and first drain drift region respectively, the first withstand voltage maintaining regions having a lower concentration than the first diffusion region. |
| US09711640B2 |
Vertical conduction integrated electronic device protected against the latch-up and relating manufacturing process
A vertical conduction integrated electronic device including: a semiconductor body; a trench that extends through part of the semiconductor body and delimits a portion of the semiconductor body, which forms a first conduction region having a first type of conductivity and a body region having a second type of conductivity, which overlies the first conduction region; a gate region of conductive material, which extends within the trench; an insulation region of dielectric material, which extends within the trench and is arranged between the gate region and the body region; and a second conduction region, which overlies the body region. The second conduction region is formed by a conductor. |
| US09711639B2 |
Multiple shielding trench gate FET
A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The trenches have field plates under the gate; the field plates are adjacent to the drift region and have a plurality of segments. A dielectric liner in the trenches separating the field plates from the drift region has a thickness great than a gate dielectric layer between the gate and the body. The dielectric liner is thicker on a lower segment of the field plate, at a bottom of the trenches, than an upper segment, immediately under the gate. The trench gate may be electrically isolated from the field plates, or may be connected to the upper segment. The segments of the field plates may be electrically isolated from each other or may be connected to each other in the trenches. |
| US09711634B2 |
Semiconductor device including a super junction MOSFET
A super junction MOSFET includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n− region with a lower impurity concentration than the n-type drift region. With this structure, it is possible to provide a super junction MOSFET which prevents a sharp rise in hard recovery waveform during a reverse recovery operation. |
| US09711632B2 |
Intra-band tunnel FET
The present disclosure relates to an intra-band tunnel FET, which has a symmetric FET that is able to provide for a high drive current. In some embodiments, the disclosed intra-band tunnel FET has a source region having a first doping type and a drain region having the first doping type. The source region and the drain region are separated by a channel region. A gate region may generate an electric field that varies the position of a valence band and/or a conduction band in the channel region. By controlling the position of the valence band and/or the conduction band of the channel region, quantum mechanical tunneling of charge carries between the conduction band in the source region and in the drain region or between the valence band in the source region and in the drain region can be controlled. |
| US09711631B2 |
Dual trench-gate IGBT structure
An IGBT device includes a substrate having a bottom semiconductor layer of a first conductivity type and an upper semiconductor layer of a second conductivity type, at least one first gate formed in a corresponding first trench disposed over the substrate, and a second gate formed in a second trench disposed over the bottom semiconductor layer. The first and second trenches are provided with gate insulators on each side of the trenches and filled with polysilicon. The second trench extends vertically to depth deeper than the at least one first trench. The IGBT device further includes a body region of the first conductivity type provided between the at least one first gate and/or the second gate, and at least one stacked layer provided between a bottom of the at least one first gate and a top of the upper semiconductor layer. The at least one stacked layer includes a floating body region of the second conductivity type provided on top of a floating body region of the first conductivity type. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09711629B2 |
Semiconductor device having low-dielectric-constant film
Provided is a semiconductor device including a plurality of trenches, including an emitter electrode; a floating layer of a first conduction type provided between adjacent trenches; and a low-dielectric-constant film provided between the floating layer and the emitter electrode, in which a dielectric constant of the low-dielectric-constant film is less than 3.9. Also provided is a semiconductor device further including a gate electrode formed in the trenches, in which capacitance between the gate electrode and the floating layer is greater than capacitance between the emitter electrode and the floating layer. |
| US09711625B2 |
Method for manufacturing thin-film transistor
A method for manufacturing a thin-film transistor includes: forming a first metal layer of a pattern including a gate on a substrate through pattern formation operations; forming a gate insulation layer on the substrate and the first metal layer and forming an oxide semiconductor layer, of which an orthogonal projection is cast on the gate, on the gate insulation layer within a thin-film transistor area and an etch stop layer on the oxide semiconductor layer, in which two etching operations are applied to the patternized oxide semiconductor layer and etch stop layer; forming a patternized second metal layer on the thin-film transistor area and an exposed portion of the gate insulation layer, forming a patternized insulation protection layer on the substrate and the patternized second metal layer, and forming a patternized pixel electrode on the insulation protection layer. |
| US09711624B1 |
Methods for direct measurement of pitch-walking in lithographic multiple patterning
Methods and apparatus for measuring pitch-walking are disclosed. Embodiments include forming parallel, spaced mandrels in test sites on a substrate; performing two SIT processes, forming first-fourth fins in the substrate for each mandrel; designating spaces between first and second and between third and fourth fins as β, between first and fourth fins of adjacent mandrels as α, and between second and third fins as γ in each test site; applying a first lithomask over fins at a first test site selecting spaces designated as one of α, β, or γ and the adjacent fins; applying a second lithomask over fins at a second test site selecting second spaces, designated as a different one of α, β, or γ and the adjacent fins; measuring the selected first and second spaces; determining differences between the measured first and second spaces; and adjusting processes for forming fins based on the differences. |
| US09711623B2 |
FinFETs with vertical Fins and methods for forming the same
In a method for forming a device, a (110) silicon substrate is etched to form first trenches in the (110) silicon substrate, wherein remaining portions of the (110) silicon substrate between the first trenches form silicon strips. The sidewalls of the silicon strips have (111) surface orientations. The first trenches are filled with a dielectric material to from Shallow Trench Isolation (STI) regions. The silicon strips are removed to form second trenches between the STI regions. An epitaxy is performed to grow semiconductor strips in the second trenches. Top portions of the STI regions are recessed, and the top portions of the semiconductor strips between removed top portions of the STI regions form semiconductor fins. |
| US09711619B1 |
Stress memorization and defect suppression techniques for NMOS transistor devices
In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer. |
| US09711616B2 |
Dual-channel field effect transistor device having increased amplifier linearity
A dual-channel field effect transistor (FET) device having increased amplifier linearity and a method of manufacturing same are disclosed. In an embodiment, the device includes a channel layer having a top surface and provided within a channel between a source electrode and a drain electrode. A barrier layer is formed on the channel layer in alternating first and second barrier thicknesses along the channel. The first barrier thicknesses form thinner regions and the second barrier thicknesses form thicker regions. A gate electrode is deposited on the barrier layer. The thinner regions have a first pinch-off voltage and the thicker regions have a larger second pinch-off voltage, such that the thinner and thicker regions are configured to turn on at different points on a drain current-gate voltage transfer curve. Transfer curve linearity is increased as a function of the gate voltage. |
| US09711615B2 |
Multichannel devices with improved performance and methods of making the same
A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge having sloping sidewalls. The multichannel ridge comprises a plurality of heterostructures that each form a channel of the multichannel ridge, wherein a parameter of at least one of the heterostructures is varied relative to other heterostructures of the plurality of heterostructures. The transistor device further comprises a three-sided gate contact that wraps around and substantially surrounds the top and sides of the multichannel ridge along at least a portion of its depth. |
| US09711614B2 |
Fabrication of III-nitride power device with reduced gate to drain charge
A III-nitride power switch that includes a III-nitride heterojunction, field dielectric bodies disposed over the heterojunction, and either gate conductive bodies that do not overlap the top surface of the field dielectric bodies or power contacts that do not overlap field dielectric bodies or both. |
| US09711613B2 |
Stacked graphene field-effect transistor
In an aspect of the present invention, a graphene field-effect transistor (GFET) structure is formed. The GFET structure comprises a wider portion and a narrow extension portion extending from the wider portion that includes one or more graphene layers edge contacted to source and drain contacts, wherein the source and drain contacts are self-aligned to the one or more graphene layers. |
| US09711599B2 |
Wide bandgap high-density semiconductor switching device and manufacturing process thereof
A switching device, such as a barrier junction Schottky diode, has a body of silicon carbide of a first conductivity type housing switching regions of a second conductivity type. The switching regions extend from a top surface of the body and delimit body surface portions between them. A contact metal layer having homogeneous chemical-physical characteristics extends on and in direct contact with the top surface of the body and forms Schottky contact metal portions with the surface portions of the body and ohmic contact metal portions with the switching regions. The contact metal layer is formed by depositing a nickel or cobalt layer on the body and carrying out a thermal treatment so that the metal reacts with the semiconductor material of the body and forms a silicide. |
| US09711598B2 |
Two-dimensional condensation for uniaxially strained semiconductor fins
Techniques are disclosed for enabling multi-sided condensation of semiconductor fins The techniques can be employed, for instance, in fabricating fin-based transistors. In one example case, a strain layer is provided on a bulk substrate. The strain layer is associated with a critical thickness that is dependent on a component of the strain layer, and the strain layer has a thickness lower than or equal to the critical thickness. A fin is formed in the substrate and strain layer, such that the fin includes a substrate portion and a strain layer portion. The fin is oxidized to condense the strain layer portion of the fin, so that a concentration of the component in the strain layer changes from a pre-condensation concentration to a higher post-condensation concentration, thereby causing the critical thickness to be exceeded. |
| US09711597B2 |
Semiconductor element, method for manufacturing same, and semiconductor integrated circuit
The present invention provides a semiconductor element that can be manufactured easily at a low cost, can obtain a high tunneling current, and has an excellent operating characteristic, a method for manufacturing the same, and a semiconductor integrated circuit including the semiconductor element. The semiconductor element of the present invention is characterized in that the whole or a part of a tunnel junction is constituted by a semiconductor region made of an indirect-transition semiconductor containing isoelectronic-trap-forming impurities. |
| US09711596B2 |
Semiconductor device including a semiconductor sheet interconnecting a source region and a drain region
A semiconductor device includes a substrate, a first source/drain (S/D) region, a second S/D region, and a semiconductor sheet. The first S/D region is disposed on the substrate. The second S/D region is disposed above the first S/D region. The semiconductor sheet interconnects the first and second S/D regions and includes a plurality of turns. A method for fabricating the semiconductor device is also disclosed. |
| US09711593B2 |
Dummy gate for a high voltage transistor device
A semiconductor device and methods for forming the same are provided. The semiconductor device includes a first doped region and a second, oppositely doped, region both formed in a substrate, a first gate formed overlying a portion of the first doped region and a portion of the second doped region, two or more second gates formed over the substrate overlying a different portion of the second doped region, one or more third doped regions in the second doped region disposed only between the two or more second gates such that the third doped region and the second doped region having opposite conductivity types, a source region in the first doped region, and a drain region in the second doped region disposed across the second gates from the first gate. |
| US09711591B2 |
Methods of forming hetero-layers with reduced surface roughness and bulk defect density of non-native surfaces and the structures formed thereby
Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface. |
| US09711586B2 |
Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus includes a substrate, thin film transistors (TFTs), and organic light-emitting diode elements (OLEDs). First wirings have a first width and a first height and second wirings have a second width and a second height, in which the first wirings and the second wirings are formed in at least a portion of areas between the OLEDs. Third wirings connect the first wirings and the second wirings and have a third width smaller than the first width of the first wirings and the second width of the second wirings or have a third height smaller than the first height of the first wirings and the second height of the second wirings. An insulating layer covers at least a portion of the first and second wiring portions and exposes at least a portion of the third wirings. |
| US09711576B2 |
Display, method of manufacturing display and electronic device
A display including a light-emitting element is provided. The light-emitting element includes a lower display electrode, an organic layer including a light-emitting layer, and an upper display electrode, wherein the lower display electrode is formed in a source-drain electrode layer or a gate electrode layer. A method of manufacture and an electronic device including the display are also provided. |
| US09711567B2 |
Process for fabricating an integrated circuit cointegrating a FET transistor and an OxRAM memory location
The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove. |
| US09711565B2 |
Semiconductor devices comprising magnetic memory cells
Memory cells are disclosed. Magnetic regions within the memory cells include an alternating structure of magnetic sub-regions and coupler sub-regions. The coupler material of the coupler sub-regions antiferromagnetically couples neighboring magnetic sub-regions and effects or encourages a vertical magnetic orientation exhibited by the neighboring magnetic sub-regions. Neighboring magnetic sub-regions, spaced from one another by a coupler sub-region, exhibit oppositely directed magnetic orientations. The magnetic and coupler sub-regions may each be of a thickness tailored to form the magnetic region in a compact structure. Interference between magnetic dipole fields emitted from the magnetic region on switching of a free region in the memory cell may be reduced or eliminated. Also disclosed are semiconductor device structures, spin torque transfer magnetic random access memory (STT-MRAM) systems, and methods of fabrication. |
| US09711563B2 |
Method of manufacturing semiconductor device having an insulating film in trenches of a semiconductor substrate
A method of manufacturing a semiconductor device includes forming, over a semiconductor substrate comprising a first region and a second region, a patterned first film in which an upper face of a portion located over the first region is positioned at a lower height from the semiconductor substrate than an upper face of a portion located over the second region, forming, over the first film, a second film which is an insulating film, a portion of the second film penetrating the first film and being located inside a trench of the semiconductor substrate, and polishing the second film to remove a portion of the second film located over the first film. An occupancy of the trench in the first region is lower than an occupancy of the trench in the second region. |
| US09711557B2 |
Semiconductor image sensors having channel stop regions and methods of fabricating the same
A semiconductor device includes a light-receiving element which outputs electric charges in response to incident light, and a drive transistor which is gated by an output of the light-receiving element to generate a source-drain current in proportion to the incident light, wherein the drive transistor include a first gate electrode, a first channel region which is disposed under the first gate electrode, first source-drain regions which are disposed at respective ends of the first channel region and that have a first conductivity type, and a first channel stop region which is disposed on a side of the first channel region, and that separates the light-receiving element and the first channel region, the first channel stop region having a second conductivity type that is different from the first conductivity type. |
| US09711556B2 |
Semiconductor image sensor structure having metal-filled trench contact
An image sensor structure includes a region of semiconductor material having a first major surface and a second major surface. A pixel structure is within the region of semiconductor material and includes a plurality of doped regions and a plurality of conductive structures. A metal-filled trench structure extends from the first major surface to the second major surface. A first contact structure is electrically connected to a first surface of the conductive trench structure, and a second contact structure electrically connected to a second surface of the conductive trench structure. In one embodiment, the second major surface is configured to receive incident light. |
| US09711549B2 |
Imaging device
An imaging device which is capable of taking images with high quality and can be manufactured at low cost is provided. A first circuit includes a first transistor and a second transistor and a second circuit includes a third transistor and a photodiode. The first transistor and the third transistor are each an n-channel transistor including an oxide semiconductor layer as an active layer, and the second transistor is a p-channel transistor including an active region in a silicon substrate. The photodiode is provided in the silicon substrate. A region in which the first transistor and the second transistor overlap each other with an insulating layer positioned therebetween is provided. A region in which the third transistor and the photodiode overlap each other with the insulating layer positioned therebetween is provided. |
| US09711548B2 |
Methods of manufacturing semiconductor devices
Methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode. |
| US09711538B2 |
Display device
A display device includes two or more pixels disposed in a pixel area in which two or more data lines intersect two or more gate lines; a common electrode commonly disposed on the pixels; a first gate high voltage supplied through a first gate voltage line, a portion of the first gate high voltage overlapping the common electrode; a second gate high voltage supplied through a second gate voltage line, a portion of the second gate high voltage overlapping the common electrode; a connecting line structure in contact with the common electrode, and extending from the common electrode in a direction toward a position in which the common electrode does not overlap the first gate voltage line. |
| US09711527B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and at least one columnar member. The stacked body is provided on the substrate. In the stacked body, a plurality of insulating films and a plurality of electrode films are layered together alternately. The semiconductor pillar is provided in the stacked body and extends in a stacking direction of the stacked body. The charge storage film is provided between the semiconductor pillar and the stacked body. The columnar member is provided in the stacked body and extends in the stacking direction. A lower portion of the columnar member is provided in the substrate. |
| US09711522B2 |
Memory hole structure in three dimensional memory
In a three dimensional nonvolatile memory, memory holes extend vertically through two or more physical levels in which memory cells are formed. Memory hole structures are formed in memory holes to include vertical channels. Vertical trenches are subsequently formed to divide memory hole structures into two or more vertical NAND strings. |
| US09711516B2 |
Non-volatile memory having a gate-layered triple well structure
A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer. |
| US09711511B1 |
Vertical channel transistor-based semiconductor memory structure
A semiconductor memory structure (e.g., SRAM) includes vertical channels with a circular, square or rectangular cross-sectional shape. Each unit cell can include a single pull-up vertical transistor and either: one pull-down vertical transistor and one pass-gate vertical transistor; or two or more of each of the pull-down and pass-gate vertical transistors. The structure may be realized by providing adjacent layers of undoped semiconductor material, forming vertical channels for vertical transistors, the vertical channels situated on each of the adjacent layers, doping a first half of each of the adjacent layers with a n-type or p-type dopant, doping a second half of each of the adjacent layers with an opposite type dopant to that of the first half, forming wrap-around gates surrounding the vertical channels, and forming top electrodes for the vertical transistors. |
| US09711509B2 |
Semiconductor device
To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a plurality of capacitors, and an isolation insulating film. The interlayer insulating film is located over the substrate. The capacitors are located in a plurality of recesses, respectively. The recesses each have an opening in the surface of the interlayer insulating film. The isolation insulating film lies in the interlayer insulating film. The isolation insulating films are located between recesses adjacent to each other in plan view. Further, the isolation insulating film is made of a material different from that of the interlayer insulating film. |
| US09711498B2 |
Semiconductor device, inverter circuit, driving device, vehicle, and elevator
A semiconductor device according to an embodiment includes a plurality of circuit units each including a substrate, a first electrode on a first side of the substrate, a second electrode aligned with the first electrode on the first side of the substrate, a third electrode on a second side of the substrate, and a first switching element and a second switching element. The switching elements are aligned on the substrate between the first electrode, second electrode and third electrode, electrically connected in series between the first electrode and the second electrode, and having the third electrode electrically connected therebetween. In two of the adjacent circuit units, the first side of one circuit unit and the first side of the other circuit unit are adjacent to each other, and the second side of the one and the second side of the other are adjacent to each other. |
| US09711492B2 |
Three dimensional structures within mold compound
A method including forming at least one passive structure on a substrate by a build-up process; introducing one or more integrated circuit chips on the substrate; and introducing a molding compound on the at least one passive structure and the one or more integrated circuit chips. A method including forming at least one passive structure on a substrate by a three-dimensional printing process; introducing one or more integrated circuit chips on the substrate; and embedding the at least one passive structure and the one or more integrated circuit chips in a molding compound. An apparatus including a package substrate including at least one three-dimensional printed passive structure and one or more integrated circuit chips embedded in a molding material. |
| US09711489B2 |
Multiple pixel surface mount device package
Emitter packages and LEDs displays utilizing the packages are disclosed, with the packages providing advantages such as reducing the cost and interconnect complexity for the packages and displays. One emitter package comprises a casing with a plurality of cavities, each cavity having at least one LED. A lead frame structure is included integral to the casing, with the at least one LED from each of the cavities mounted to the lead frame structure. The package is capable of receiving electrical signals for independently controlling the emission from a first and second of the cavities. One LED display utilizes the LED packages mounted in relation to one another to generate a message or image. The LED packages comprise multiple pixels each having at least one LED, with each package capable of receiving electrical signals for independently controlling the emission of at least a first and second of the pixels. |
| US09711486B2 |
Stacked semiconductor device
A stacked semiconductor device includes: a plurality of stacked integrated-circuit chips that are to be mounted onto a substrate and including at least one power-supply target chip; a decoupling through-electrode transmission line including a decoupling power-supply-side through-electrode wiring line coupled to a power-supply terminal of the at least one power-supply target chip and a decoupling ground-side through-electrode wiring line coupled to a ground terminal of the at least one power-supply target chip; a resistor and a capacitor provided one of the a plurality of integrated-circuit chips that is located at a termination of the decoupling through-electrode transmission line, the resistor having an impedance substantially equal to a characteristic impedance of the decoupling through-electrode transmission line, wherein the resistor and the capacitor are coupled in series. |
| US09711484B2 |
Semiconductor package with semiconductor die directly attached to lead frame and method
In one embodiment, a semiconductor package includes a semiconductor die having conductive pads. A lead frame is directly connected to the conductive pads using an electrochemically formed layer or a conductive adhesive layer thereby facilitating an electrical connection between the conductive pads of the semiconductor die and the lead frame without using separate wire bonds or conductive bumps. |
| US09711478B2 |
Semiconductor device with an anti-pad peeling structure and associated method
A semiconductor device with an anti-pad peeling structure is disclosed. The semiconductor device includes: a semiconductor substrate including a Through Substrate Via (TSV); a dielectric layer on the semiconductor substrate and including a plurality of recesses therein; and a pad above the semiconductor substrate to cover a portion of the dielectric layer and extend to the recesses; wherein the pad extends to the plurality of recesses, and a plurality of contact points are confined in the recesses between the pad and the conductive layer, and each of the contact points is at least partially excluded from a boundary of the TSV when being seen from a top-down perspective. |
| US09711477B2 |
Dummy flip chip bumps for reducing stress
A device includes a metal pad over a substrate. A passivation layer includes a portion over the metal pad. A post-passivation interconnect (PPI) is electrically coupled to the metal pad, wherein the PPI comprises a portion over the metal pad and the passivation layer. A polymer layer is over the PPI. A dummy bump is over the polymer layer, wherein the dummy bump is electrically insulated from conductive features underlying the polymer layer. |
| US09711471B2 |
Semiconductor device package, electronic device and method of manufacturing electronic devices using wafer level chip scale package technology
A semiconductor device package comprising a circuit chip and a wafer level chip scale package is designed for reducing capacitive interactions which exist between electrically conducting portions of the circuit chip and under-bump metallization areas of the package. Such design is beneficial in particular for under-bump metallization areas which are dedicated to transferring signals having frequencies above 30 GHz. |
| US09711470B2 |
Package on package structure and method for forming the same
The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small. |
| US09711464B2 |
Semiconductor chip with anti-reverse engineering function
A structure and a method. The structure includes a semiconductor substrate; a stack of wiring levels from a first wiring level to a last wiring level, the first wiring level closest to the semiconductor substrate and the last wiring level furthest from the semiconductor substrate, the stack of wiring levels including an intermediate wiring level between the first wiring level and the last wiring level; active devices contained in the semiconductor substrate and the first wiring level, each wiring level of the stack of wiring levels comprising a dielectric layer containing electrically conductive wire; a trench extending from the intermediate wiring level, through the first wiring level into the semiconductor substrate; and a chemical agent filling the trench, portions of at least one wiring level of the stack of wiring levels not chemically inert to the chemical agent or a reaction product of the chemical agent. |
| US09711462B2 |
Package arrangement including external block comprising semiconductor material and electrically conductive plastic material
In various embodiments, a package arrangement may be provided. The package arrangement may include at least one chip. The package arrangement may further include encapsulation material at least partially encapsulating the chip. The package arrangement may also include a redistribution structure over a first side of the chip. The package arrangement may further include a metal structure over a second side of the chip. The second side may be opposite the first side. The package arrangement may additionally include at least one of a semiconductor structure and an electrically conductive plastic material structure electrically coupled to the redistribution structure and the metal structure to form a current path between the redistribution structure and the metal structure. |
| US09711459B2 |
Multi-layer substrate with an embedded die
The present disclosure relates to a multi-layer substrate structure with an embedded die to miniaturize designs and improve performance. The multi-layer substrate structure includes a core layer having a cavity and a die mounted within the cavity. The die has a die body, a die conductive element on a top surface of the die body, and a dielectric layer over the die conductive element. The multi-layer substrate structure also includes a substrate conductive element formed over a portion of a top surface of the core layer and extending over at least a portion of the die conductive element. Overlapping portions of the die conductive element and the substrate conductive element are separated by the dielectric layer and form an electronic component. |
| US09711458B2 |
Structure and formation method for chip package
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a polymer layer over the semiconductor die and the package layer. The chip package further includes a dielectric layer over the polymer layer. The dielectric layer is substantially made of a semiconductor oxide material. In addition, the chip package includes a conductive feature in the dielectric layer electrically connected to a conductive pad of the semiconductor die. |
| US09711457B2 |
Semiconductor devices with recessed interconnects
Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a conductive feature extending through a semiconductor substrate such that the conductive feature has a first end and a second end opposite the first end, and wherein the second end projects outwardly from a surface of the substrate. The method can further include forming a dielectric layer over the surface of the substrate and the second end of the conductive feature such that the dielectric layer has an original thickness. The method can also include removing a portion of the dielectric layer to an intermediate depth less than the original thickness such that at least a portion of the second end of the conductive feature is exposed. |
| US09711453B2 |
Semiconductor devices including a capping layer
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided. |
| US09711449B2 |
Ruthenium metal feature fill for interconnects
A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a ruthenium (Ru) metal layer to at least partially fill the feature, and heat-treating the substrate to reflow the Ru metal layer in the feature. |
| US09711446B2 |
Resin composition
Resin compositions containing (A) an epoxy resin, (B) a curing agent, and (C) an inorganic filler in which the content of (C) the inorganic filler is 55% by mass or higher with respect to 100% by mass of a non-volatile component within the resin composition, the average particle diameter of (C) the inorganic filler is 0.05 to 0.35 μm, the product of the specific surface area (m2/g) of (C) the inorganic filler and the true density of (C) the inorganic filler is 1 to 77 m2/g and the moisture permeation of a cured product obtained by thermally cured the resin composition is 0.05 to 2.8 g·mm/m2·24 h are useful for making printed wiring boards. |
| US09711442B1 |
Semiconductor structure
A semiconductor structure is provided. The semiconductor structure includes an electronic component and a board structure. The board structure includes a dielectric layer structure and at least one elastomer. The dielectric layer structure has a mount region and a peripheral region surrounding the mount region. The electronic component is disposed on the mount region, and the peripheral region has at least one first through hole. The elastomer is disposed in the first through hole. |
| US09711440B2 |
Wiring board and method for manufacturing the same
A wiring board includes a core substrate including an insulating layer and a conductor layer formed on the insulating layer, and a build-up layer laminated on the substrate and including an inter-layer insulating layer and a conductor layer laminated on the inter-layer. The substrate has opening penetrating through the insulating layer such that surface of the conductor layer in the substrate is forming bottom of the opening, the substrate has a via conductor formed in the opening and including plating filling the opening, the conductor layer in the substrate includes a metal foil, the conductor layer in the build-up layer includes a metal foil, and the metal foil in the substrate has surface in contact with the surface of the insulating layer such that the surface of the metal foil in the substrate has surface roughness smaller than surface roughness of surface of the metal foil in the build-up layer. |
| US09711439B2 |
Printed wiring board and method for manufacturing the same
A printed wiring board includes an insulating layer including insulating material, and a conductor layer formed on a surface of the insulating layer and including conductor pads and conductor patterns such that the conductor pads are positioned to connect one or more electronic components and that the conductor patterns are formed between the conductor pads. The conductor patterns are formed such that each conductor pattern has a pattern width of 3 μm or less and that the conductor patterns have a pattern interval of 3 μm or less between adjacent conductor patterns, and the insulating layer has recess portions formed on the surface between the conductor patterns at least along the conductor patterns such that the recess portions have a depth in a range of 0.1 μm to 2.0 μm relative to a contact interface at which the conductor patterns and the insulating layer are in contact with each other. |
| US09711435B2 |
Semiconductor device
A semiconductor device is provided. The semiconductor device may include a frame portion on which at least one semiconductor chip is arranged; a plurality of leads electrically connected to the semiconductor chip; and a mold portion formed on the frame portion to surround a part of the frame portion on which the semiconductor chip and the plurality of leads are arranged, wherein a gap between closest portions of the respective leads is at least 2.9 mm. |
| US09711433B2 |
Semiconductor device, method of manufacturing the same, and electronic device
A semiconductor device includes: a first semiconductor element; a first substrate provided on the first semiconductor element and including a cavity with reduced pressure; coolant held inside the cavity; a second semiconductor element provided on the first substrate; and a heat spreading member thermally connected to the first substrate and provided with a hole communicated with the cavity. |
| US09711429B2 |
Semiconductor device having a substrate housed in the housing opening portion
In a semiconductor device, an insulating substrate housed in an housing opening portion of a resin case includes an insulating board, a first metal layer formed on the upper surface of the insulating board, a second metal layer which is formed on an outer peripheral edge portion of the upper surface of the insulating board and is in contact with a level difference portion, and a third metal layer formed on the under surface of the insulating board and leveled with or protruding from the under surface of the resin case. The first and second metal layers are formed by etching copper foil formed on the insulating board so that these metal layers have the same thickness. The thickness of the second metal layer may be changed relatively freely according to the housing depth of the resin case. Thus, the semiconductor device may be made thin. |
| US09711423B2 |
Methods for manufacturing semiconductor device and for detecting end point of dry etching
A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof. |
| US09711421B1 |
Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells
Improved processes for manufacturing wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes, including GATE-snake-open and/or GATE-snake-resistance failure modes. Such processes may involve evaluating Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s). |
| US09711419B2 |
Substrate backside texturing
Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside. |
| US09711418B2 |
Composite substrate with a high-performance semiconductor layer and method of manufacturing the same
Provided is a composite substrate which has a high-performance semiconductor layer. A composite substrate of the present invention comprises: a supporting substrate which is formed of an insulating material; a semiconductor layer which is formed of a single crystal semiconductor that is superposed on and joined to the supporting substrate; and interfacial inclusions which are present in the interface between the supporting substrate and the semiconductor layer at a density of 1012 atoms/cm2 or less, and which are formed of a metal element that is different from the constituent elements of the supporting substrate and the semiconductor layer. |
| US09711417B2 |
Fin field effect transistor including a strained epitaxial semiconductor shell
A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process. |
| US09711415B2 |
Device for high-K and metal gate stacks
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region. |
| US09711413B2 |
High performance CMOS device design
A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. |
| US09711411B2 |
Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure and a second gate structure on the substrate; forming a contact etch stop layer (CESL) on the first gate structure, the second gate structure, and the substrate; removing part of the CESL between the first gate structure and the second gate structure; and forming an interlayer dielectric (ILD) layer on the CESL. |
| US09711409B2 |
Fin arrangement and method for manufacturing the same
A fin arrangement and a method for manufacturing the same are provided. An example method may include: patterning a substrate to form an initial fin on a selected area of the substrate; forming, on the substrate, a dielectric layer to substantially cover the initial fin, wherein a portion of the dielectric layer located on top of the initial fin has a thickness substantially less than that of a portion the dielectric layer located on the substrate; and etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion of the initial fin is used as a fin. |
| US09711407B2 |
Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells. |
| US09711406B2 |
Method and apparatus for plasma dicing a semi-conductor wafer
The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma. |
| US09711399B2 |
Direct plasma densification process and semiconductor devices
An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz. |
| US09711396B2 |
Method for forming metal chalcogenide thin films on a semiconductor device
In some aspects, methods of forming a metal chalcogenide thin film are provided. According to some methods, a metal chalcogenide thin film is deposited on a substrate in a reaction space in a cyclical deposition process where at least one cycle includes alternately and sequentially contacting the substrate with a first vapor-phase metal reactant and a second vapor-phase chalcogen reactant. In some aspects, methods of forming three-dimensional structure on a substrate surface are provided. In some embodiments, the method includes forming a metal chalcogenide dielectric layer between a substrate and a conductive layer. In some embodiments the method includes forming an MIS-type contact structure including a metal chalcogenide dielectric layer. |
| US09711390B2 |
Shallow trench isolation trenches and methods for NAND memory
A method of forming a shallow trench isolation trench in a semiconductor substrate is described. The method includes forming a trench in a region of the substrate, forming a liner in the trench, wherein the liner includes a first dielectric material, adhering a halogen element to the liner, forming a second dielectric material in the trench, annealing the first dielectric material and the second dielectric material, exposing a portion of a surface of the second dielectric material, and isotropically etching the exposed portion of the surface of the second dielectric material to form an air gap in the shallow trench isolation trench. |
| US09711389B2 |
Automatic module apparatus for manufacturing solid state drives (SSD)
An automatic module apparatus for manufacturing a solid state drive (SSD) includes a labeling apparatus, one or more test handler apparatuses and a sorting apparatus. The labeling apparatus is for printing a label on a SSD mounted on a carrier tray. The one or more test handler apparatuses are for transporting the carrier tray on which the labeled SSD is mounted and for testing the labeled SSDs to determine whether the labeled SSDs have any defects. The SSD sorting apparatus is for transporting the carrier tray on which the tested SSDs are mounted and sorting non-defective defective SSDs tested by the test handler apparatuses. The SSD labeling apparatus, the test handler apparatuses, and the SSD sorting apparatus are in-line and automated. |
| US09711388B2 |
Substrate holder and a device and a method for treating substrates
A substrate holder having a plate element for receiving a substrate includes at least one recess in a first side and spacers in the at least one recess. At least one opening is fluidly connected to the recess and is connectable to an external gas delivery/exhaust unit. At least one notch or channel radially surrounds the recess. At least one opening is fluidly connected to the notch or channel and is connectable to an external gas delivery/exhaust unit. A circumferential web radially surrounds the recess and is located between the recess and the notch or channel. A first circumferential contact surface is formed on the upper side of the web and radially surrounds the recess, such that a substrate abutting against the first contact surface forms an enclosed chamber with the recess. A second circumferential contact surface radially surrounds the notch or channel. |
| US09711383B2 |
Fabrication method of semiconductor devices and fabrication system of semiconductor devices
In aspects of the invention, a holding stage of a pick up system can include a first stage on which a semiconductor chip is mounted with an adhesive sheet put in between, a second stage supporting the first stage, and an evacuation pipe. The first stage can be provided with a plurality of grooves, projections each being formed with side walls of adjacent grooves, and air holes connected to the grooves. The semiconductor chip can be mounted on the first stage so that the whole end portion of the semiconductor chip does not position on one groove. Then, a closed space surrounded by the adhesive sheet and the first and second stages and can be evacuated to make the semiconductor chip held on the projections. Thereafter, the semiconductor chip can be picked up by a collet. |
| US09711381B2 |
Methods and apparatus for post-chemical mechanical planarization substrate cleaning
A method and apparatus for cleaning a substrate after chemical mechanical planarizing (CMP) is provided. The apparatus comprises a housing, a substrate holder rotatable on a first axis and configured to retain a substrate in a substantially vertical orientation, a first pad holder having a pad retaining surface facing the substrate holder in a parallel and spaced apart relation, the first pad holder rotatable on a second axis disposed parallel to the first axis, a first actuator operable to move the pad holder relative to the substrate holder to change a distance between the first axis and the second axis, and a second pad holder disposed in the housing, the second pad holder having a pad retaining surface facing the substrate holder in a parallel and spaced apart relation, the second pad holder rotatable on a third axis parallel to the first axis and the second axis. |
| US09711377B2 |
Method of manufacturing semiconductor device
Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member. |
| US09711371B2 |
Method of etching organic film
An organic film can be etched while suppressing damage on an underlying layer. A method of etching the organic film includes etching the organic film within a processing vessel of a plasma processing apparatus which accommodates a processing target object. A processing gas containing a hydrogen gas and a nitrogen gas is supplied into the processing vessel, and plasma of the processing gas is generated. Further, a flow rate ratio of the hydrogen gas to a flow rate of the processing gas is set to be in a range from 35% to 75%, and a high frequency bias power for ion attraction to the processing target object is set to be in a range from 50 W to 135 W, in the etching of the organic film. |
| US09711369B2 |
Method for forming patterns with sharp jogs
The present disclosure provides a method for forming patterns in a semiconductor device. The method includes forming a main pattern on a substrate; forming a spacer on sidewalls of the main pattern; forming a cut pattern having an opening by a first lithography process; and performing a cut process to selectively remove portions of the spacer within the opening of the cut pattern while the main pattern remains unetched, thereby defining a circuit pattern by the main pattern and the spacer. The circuit pattern includes a sharp jog. |
| US09711366B2 |
Selective etch for metal-containing materials
Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. A remote plasma is used to excite the halogen-containing precursor and a local plasma may be used in embodiments. Metal-containing materials on the substrate may be pretreated using moisture or another OH-containing precursor before exposing the resulting surface to remote plasma excited halogen effluents in embodiments. |
| US09711357B1 |
Method of manufacturing a semiconductor device with epitaxial layers and an alignment structure
A semiconductor device is manufactured in a semiconductor body by forming an initial mask on a process surface of a semiconductor layer, openings in the mask exposing a part of the semiconductor layer in alignment structure and super-junction structure areas. A recess structure is formed in the semiconductor layer at portions of the process surface that are exposed by the openings, the recess structure in the alignment structure area constituting an initial alignment structure. Dopants are introduced into the semiconductor layer through portions of the process surface that are exposed by the openings of the initial mask. The dopants introduced in the super-junction area constitute part of a super-junction structure. A thickness of the semiconductor layer is increased by growing an epitaxial layer. The initial alignment structure is imaged into the process surface. Dopants are introduced into the semiconductor layer by using a mask aligned to the initial alignment structure. |
| US09711356B2 |
Method for manufacturing thin-film transistor by implanting ions into channel region for lowering leakage current
The present invention discloses a method for manufacturing a thin-film transistor, comprising the steps of: forming a semiconductor active layer, and a doped semiconductor active layer; forming a source-drain metal layer; forming a channel region; and implanting ions for lowering the TFT leakage current into the surface of the semiconductor active layer in the channel region via ion implantation after forming the channel region. The invention further relates to a thin-film transistor, a TFT array substrate and a display device. The invention has the following beneficial effects: by implanting ions for lowering the TFT leakage current into the channel region, the electrical performance of a TFT may be improved, and the thickness of a semiconductor active layer in a channel region may be changed controllably. |
| US09711353B2 |
Method for manufacturing compound semiconductor epitaxial substrates including heating of carrier gas
An aspect of the present disclosure resides in a method for manufacturing a compound semiconductor epitaxial substrate including a substrate and a compound semiconductor epitaxial layer disposed on the substrate, the method including providing the substrate, heating a carrier gas, preparing a mixed gas by mixing the heated carrier gas with at least a portion of a source gas that is a source for the compound semiconductor epitaxial layer, the source gas having a lower temperature than the heated carrier gas, and forming the compound semiconductor epitaxial layer on the substrate by supplying the mixed gas onto the substrate. |
| US09711350B2 |
Methods for semiconductor passivation by nitridation
In some embodiments, a semiconductor surface having a high mobility semiconductor may be effectively passivated by nitridation, preferably using hydrazine, a hydrazine derivative, or a combination thereof. The surface may be the semiconductor surface of a transistor channel region. In some embodiments, a semiconductor surface oxide layer is formed at the semiconductor surface and the passivation is accomplished by forming a semiconductor oxynitride layer at the surface, with the nitridation contributing nitrogen to the surface oxide to form the oxynitride layer. The semiconductor oxide layer may be deposited by atomic layer deposition (ALD) and the nitridation may also be conducted as part of the ALD. |
| US09711346B2 |
Method to fabricate a high performance capacitor in a back end of line (BEOL)
A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench. |
| US09711344B2 |
Semiconductor device manufacturing method using a multilayer resist
To improve the manufacturing yield of a semiconductor device, there is to provide a method of manufacturing a semiconductor device using a multilayer resist, in which before performing water repelling processing for immersion exposure on a wafer, an anti-reflection film, an underlayer film, and an intermediate film applied to a wafer edge portion are eliminated through rinse processing. |
| US09711342B2 |
Gas-discharge lamp
The invention describes a gas-discharge lamp (1) comprising a vessel (5), which vessel (5) is partially coated with at least one longitudinal stripe (SH, SH′) arranged on the surface of the vessel (5) below a horizontal plane (P) through a longitudinal axis (X) through the centre of the lamp (1) such that, on each side of the lamp, an angle (βH1, βH2) subtended at the lamp centre by the horizontal plane (P) and an upper edge (16, 17) of the longitudinal stripe (SH, SH′) on that side of the lamp comprises at least 10°, more preferably at least 13°, most preferably at least 15°. The invention also describes a reflector (8) for a lamp (1), comprising a reflective interior surface realized to deflect light (L20A, L20B, L21A, L21B) originating from the lamp (1) outward to give a specific beam profile (3) with a bright/dark cut-off line (31) and a shoulder (32), and wherein the lamp (1), in particular a lamp (1) according to any of claims 1 to 12, is positioned horizontally in the reflector (8), and wherein the reflective interior surface comprises at least one beam-shaping region (81 A, 81B) realised to deflect a portion (L21A, L21B) of the light (L20A, L20B, L21A, L21B), emitted from the lamp (1) between 7.5° and 15° below a horizontal plane (P), at a specific region (21A, 21B) within the beam profile (3). The invention further describes a lighting assembly (9) comprising such a reflector (8) and a lamp (1), in particular a lamp (1) according to the invention. |
| US09711338B2 |
Ion source for mass spectrometry
Systems and methods for delivering a sample to a mass spectrometer are provided. In one aspect, the system can include a sample source for generating a sample plume entrained in a primary gas stream in a first flow direction at a first flow rate, and a gas source for generating a secondary gas stream along a second flow direction different from the first flow direction and at a second flow rate greater than the first flow rate. The sample source and the gas source can be positioned relative to one another such that the primary gas stream intersects the secondary gas stream so as to generate a resultant gas stream propagating along a trajectory different from said first and second direction to bring the sample to proximity of a sampling orifice of the mass spectrometer. |
| US09711335B2 |
System and method for balancing consumption of targets in pulsed dual magnetron sputtering (DMS) processes
A sputtering system and method are disclosed. The system has at least one dual magnetron pair having a first magnetron and a second magnetron, each magnetron configured to support target material. The system also has a DMS component having a DC power source in connection with switching components and voltage sensors. The DMS component is configured to independently control an application of power to each of the magnetrons, and to provide measurements of voltages at each of the magnetrons. The system also has one or more actuators configured to control the voltages at each of the magnetrons using the measurements provided by the DMS component. The DMS component and the one or more actuators are configured to balance the consumption of the target material by controlling the power and the voltage applied to each of the magnetrons, in response to the measurements of voltages at each of the magnetrons. |
| US09711331B2 |
Frequency tuning for pulsed radio frequency plasma processing
This disclosure describes systems, methods, and apparatus for pulsed RF power delivery to a plasma load for plasma processing of a substrate. In order to maximize power delivery, a calibration phase using a dummy substrate or no substrate in the chamber, is used to ascertain a preferred fixed initial RF frequency for each pulse. This fixed initial RF frequency is then used at the start of each pulse during a processing phase, where a real substrate is used and processed in the chamber. |
| US09711329B2 |
System and method to improve productivity of hybrid scan ion beam implanters
A method for improving the productivity of a hybrid scan implanter by determining an optimum scan width is provided. A method of tuning a scanned ion beam is provided, where a desired beam current is determined to implant a workpiece with desired properties. The scanned beam is tuned utilizing a setup Faraday cup. A scan width is adjusted to obtain an optimal scan width using setup Faraday time signals. Optics are tuned for a desired flux value corresponding to a desired dosage. Uniformity of a flux distribution is controlled when the desired flux value is obtained. An angular distribution of the ion beam is further measured. |
| US09711325B2 |
Charged-particle microscope providing depth-resolved imagery
A method of examining a sample using a charged-particle microscope, comprising mounting the sample on a sample holder; using a particle-optical column to direct at least one beam of particulate radiation onto a surface S of the sample, thereby producing an interaction that causes emitted radiation to emanate from the sample; using a detector arrangement to detect at least a portion of said emitted radiation, the method of which comprises embodying the detector arrangement to detect electrons in the emitted radiation; recording an output On of said detector arrangement as a function of kinetic energy En of said electrons, thus compiling a measurement set M={(On, En)} for a plurality of values of En; using computer processing apparatus to automatically deconvolve the measurement set M and spatially resolve it into a result set R={(Vk, Lk)}, in which a spatial variable V demonstrates a value Vk at an associated discrete depth level Lk referenced to the surface S, whereby n and k are members of an integer sequence, and spatial variable V represents a physical property of the sample as a function of position in its bulk. |
| US09711317B2 |
Air ionization module
The invention relates to air ionization modules with ionization tubes removably arranged in mounts and to a support comprising the mounts. The air ionization modules are characterized in particular in that as little condensation as possible occurs while enriching an air flow with ions. For this purpose, the support has two mutually spaced plates, a first plate being an assembly plate and a second plate being a circuit board comprising the mounts. Furthermore, a body made of a heat-insulating material is located between the plates such that the second plate is arranged so as to be heat-insulated relative to the first plate. The air ionization module is used to generate ions in an air flow for at least one inner room of a building. Ionized air leads to a separation of multiple odor-causing molecules, an eradication of microorganisms, a degradation of volatile gaseous hydrocarbons, and a reduction of the oxide potential of the air, for example. In this manner, a comfortable, near-natural air is produced in the room supplied with the air. |
| US09711316B2 |
Method of cleaning an extraction electrode assembly using pulsed biasing
A system and method of improving the performance and extending the lifetime of an ion source is disclosed. The ion source includes an ion source chamber, a suppression electrode and a ground electrode. In the processing mode, the ion source chamber may be biased to a first positive voltage, while the suppression electrode is biased to a negative voltage to attract positive ions from within the chamber through an aperture and toward the workpiece. In the cleaning mode, the ion beam is defocused so that it strikes the suppression electrode and the ground electrode. The voltages applied to the ion source chamber and the electrodes are pulsed to minimize the possibility of glitches during this cleaning mode. |
| US09711314B2 |
Compact magnet system for a high-power millimeter-wave gyrotron
A compact magnet system for use in a high-power microwave tube includes an electromagnetic coil surrounded on three sides by permanent magnets. More particularly, constituent components include a first tubular retaining member; the electromagnetic coil that fits within the first tubular retaining member and that has a central cavity; first permanent magnets positioned to extend radially from the central cavity so that like poles of the first permanent magnets wrap around the central cavity along a first side of the solenoid coil; and second permanent magnets positioned to extend radially from the central cavity so that opposite poles to the first permanent magnets wrap around the central axis along the second side of the solenoid coil. Optional added components include two sets of permanent magnets, one set on each side of the coil and a pole piece located adjacent to an end of the first tubular retaining member. |
| US09711309B2 |
Relay including processor providing control and/or monitoring
A relay includes a first terminal, a second terminal, a third terminal, a fourth terminal, separable contacts electrically connected between the first and second terminals, an actuator coil comprising a first winding and a second winding, the first winding electrically connected between the third and fourth terminals, the second winding electrically connected between the third and fourth terminals, a processor, an output, a first voltage sensing circuit cooperating with the processor to determine a first voltage between the first and second terminals, and a second voltage sensing circuit cooperating with the processor to determine a second voltage between the third and fourth terminals. The processor determines that the separable contacts are closed when the first voltage does not exceed a first predetermined value and the second voltage exceeds a second predetermined value and responsively outputs a corresponding status to the output. |
| US09711306B2 |
Switch apparatus for connection with a DC circuit
A switch apparatus usable in a DC circuit employs a rotatable shaft having conductors that are removably connected with two or more pairs of contacts that are situated on line conductors and load conductors and that are connected in parallel by the conductors on the shaft. In rotating the shaft to open the switch, one pair of the contacts is electrically disconnected prior to electrical disconnection of the other pair of contacts. Further rotation of the shaft causes the other pair of contact to eventually become disconnected. Electrical arcs thus form only at the air gaps between the other pair of contacts and the conductor. Magnetic field elements in the form of permanent magnets are situated in the vicinity of the air gaps of only the other pair of contacts and apply Lorentz forces to the arcs to extinguish them. |
| US09711303B2 |
Dome-shaped assembly and handheld electronic device including dome-shaped assembly
A dome-shaped element disposable in a keyboard of an electronic device is provided. The dome-shaped element includes a concave surface originating at a center and terminating at a periphery. The concave surface includes an annular array of elastic elements extending from the center to the periphery. At least one of the elastic elements includes a first portion with a first slope proximate to the center and a second portion with a second slope proximate to the periphery. The concave surface is deflectable between an un-deflected position and a deflected position and is configured to affect an operation of the electronic device in the deflected position. |
| US09711296B2 |
Energy storage method and system using defect-engineered nanostructures
An energy storage device includes a first electrode and a second electrode comprising nanostructures. The nanostructures comprise defects that increase charge storage capabilities of the energy storage device. A method of fabricating an energy storage device includes producing a nanomaterial comprising nanostructures and generating defects in the nanomaterial using an electrophilic or nucleophilic additive for increasing charge storage capability of the nanomaterial. |
| US09711292B2 |
Method of manufacturing positive electrode active material for lithium ion battery
At least one of an aqueous solution A containing lithium, an aqueous solution B containing iron, manganese, cobalt, or nickel, and an aqueous solution C containing a phosphoric acid includes graphene oxide. The aqueous solution A is dripped into the aqueous solution C, so that a mixed solution E including a precipitate D is prepared. The mixed solution E is dripped into the aqueous solution B, so that a mixed solution G including a precipitate F is prepared. The mixed solution G is subjected to heat treatment in a pressurized atmosphere, so that a mixed solution H is prepared, and the mixed solution H is then filtered. Thus, particles of a compound containing lithium and oxygen which have a small size are obtained. |
| US09711290B2 |
Curved RF electrode for improved Cmax
The present invention generally relates to a MEMS device and a method of manufacture thereof. The RF electrode, and hence, the dielectric layer thereover, has a curved upper surface that substantially matches the contact area of the bottom surface of the movable plate. As such, the movable plate is able to have good contact with the dielectric layer and thus, good capacitance is achieved. |
| US09711287B2 |
High voltage high current vacuum integrated circuit
A high voltage, high current vacuum integrated circuit includes a common vacuum enclosure that includes at least two cold-cathode field emission electron tubes, and contains at least one internal vacuum pumping means, at least one exhaust tubulation, vacuum-sealed electrically-insulated feedthroughs, and internal electrical insulation. The cold-cathode field emission electron tubes are configured to operate at high voltage and high current and interconnected with each other to implement a circuit function. |
| US09711282B2 |
Power reception device, power transmission device, and power transfer system
A power reception device includes a power reception unit having a first capacitor, receiving electric power in a non-contact manner from an externally provided power transmission unit, a first housing case housing the power reception unit inside, and a first anchor member anchoring the first capacitor. The first housing case includes a first shield defining a region where an electromagnetic field developed around the power reception unit is emitted. The first capacitor is anchored by the first anchor member at a position spaced apart from the first shield. |
| US09711281B2 |
Method of manufacturing an ignition coil assembly
A method of assembling the ignition coil assembly including a first spool, a first coil, and a second spool. The first coil is wound around a first spool outer surface. The first spool and the first coil are disposed within a cavity of the second spool and an electrically insulating material injected into an annular space defined between a first coil outer surface and a second spool inner surface. The first spool is configured to allow a decrease of a circumference of the first spool when the first coil is wound around an outer surface of the first spool. Decreasing the circumference of the first spool increases the annular space sufficient to inject the electrically insulating material into the annular space without creating substantial voids in the electrically insulating material. |
| US09711277B2 |
Non-contact power supply system
A non-contact power supply system includes a power supply device and a power reception device. The power supply device includes primary coils arranged on a power supply surface and configured to be excited at an operational frequency. The power reception device includes a secondary coil configured to induce current using resonance phenomenon based on alternating flux from the primary coils when arranged on the power supply surface. The operational frequency that excites the primary coil is set at or in the proximity of a resonance frequency of a resonance system formed when the secondary coil is located at an intermediate position between two of the primary coils that are adjacent to each other. |
| US09711275B2 |
Externally mounted fuse box on a liquid-filled transformer and method for servicing
A fuse box mounted on a liquid-filled transformer is disclosed. The fuse box may include one or more fuse link assemblies securing one or more fuses within a base fuse box, a fuse holder coupling the one or more fuse link assemblies within the base fuse box, wherein the one or more fuse link assemblies are pulled-up from the fuse holder by hand to remove the one or more fuse link assemblies from the base fuse box. The fuse box may include a retaining ring to fasten the fuse holder to the one or more fuse link assemblies. The fuse box may include a method for servicing a fuse box on a liquid-filled transformer. |
| US09711270B2 |
Electronic component
A common mode choke coil as an electronic component includes a laminate. The laminate includes insulating layers stacked in a thickness direction and has a recess sinking in a stacking direction of the insulating layers. The laminate includes at least one coil conductor therein. The recess is filled with a magnetic resin material. The magnetic resin material is formed of a magnetic powder-containing resin that is a mixture of a soft magnetic metal powder and a thermosetting resin. The soft magnetic metal powder has an average particle size of 12 μm or less. The magnetic powder-containing resin contains 65 vol % or more and 85 vol % or less of the soft magnetic metal powder. |
| US09711269B2 |
Torque motor actuator with an armature stop
A torque motor actuator includes a first magnetic pole piece, a second magnetic pole piece, an armature, and an armature stop. The second magnetic pole piece is spaced apart from the first magnetic pole piece to define an armature gap. The armature is disposed in the armature gap and is spaced apart from the first and second magnetic pole pieces. The armature includes a magnetically permeable material and has a central portion, a first arm, and a second arm. The armature is rotationally mounted at the central portion, and the first and second arms extend, in opposite directions, from the central portion. The armature stop extends from the first arm, and comprises a non-magnetic material. The armature stop is configured, upon rotation of the armature, to selectively engage one of the first or second magnetic pole pieces to thereby limit armature rotation. |
| US09711267B2 |
Support structure for cylindrical superconducting coil structure
An arrangement for supporting a cylindrical superconducting coil structure has recesses in an axial end-surface of the coil structure, and support brackets that individually horizontally protrude into the recesses, such that a vertical loading on the support brackets bears the weight of the coil structure. Opposite ends of the support brackets engage a support member, which supports the support brackets engaged therein, thereby also bearing the weight of the coil structure. |
| US09711264B2 |
Winding layers composed of different materials
Fewer insulation layers can be used by virtue of using hydrophobic electrically conductive materials around a main insulation around a conductive bar. There are several more layers of conductive and/or non-conductive material. |
| US09711258B2 |
Wire harness and method for manufacturing wire harness
A wire harness includes: a tubular outer member; a conductive path which is inserted in and protected by the outer member; and a vibration suppressing member which reduces a movable range of the conductive path to suppress shakes of the conductive path. The vibration suppressing member includes an inward projection portion which projects inward from a tube inner surface of the outer member in a state in which the vibration suppressing member is attached to the outer member from a side of a tube outer surface after insertion of the conductive path. |
| US09711255B2 |
Ultraviolet-emitting material and ultraviolet light source
There is provided an ultraviolet-emitting material that is formed so as to include Mg1−xZnxO (0 |
| US09711252B1 |
High energy beam diffraction material treatment system
A coherent beam treatment system produces a first and second energy beam that are coherent at a treatment location. An energy beam includes a neutron beam, a proton beam, an electron beam, acoustic waves, a laser and x-ray. An energy beam may be defined by a wave, such as a sinusoidal wave having a frequency and amplitude. A control system may produce a first and second beam that have coherence at a treatment location. Coherence is a location where two beams have matching wave profiles. A beam may be defined by a simple sinusoidal equation wherein the frequency and amplitude are constant as a function of time. A beam may be defined by a complex wave equation, wherein the frequency or amplitude change as a function of time. A control system may modulate one or more of the beam equations to change a location of coherence. |
| US09711250B2 |
Tritium direct conversion semiconductor device having increased active area
A betavoltaic power source. The betavoltaic power source comprises a source of beta particles, a substrate with shaped features defined therein and a InGaP betavoltaic junction disposed between the source of beta particles and the substrate, and also having shaped features therein responsive to the shaped features in the substrate, the InGaP betavoltaic junction device for collecting the beta particles and for generating electron hole pairs responsive thereto. |
| US09711241B2 |
Method and apparatus for optimized memory test status detection and debug
Embodiments contained in the disclosure provide a method for memory built-in self-testing (MBIST). The method begins when a testing program is loaded, which may be from an MBIST controller. Once the testing program is loaded MBIST testing begins. During testing, memory failures are determined and written to a failure indicator register. The writing to the failure indicator register occurs in parallel with the ongoing MBIST testing. An apparatus is also provided. The apparatus includes a memory data read/write block, a memory register, a memory addressor, and a memory read/write controller. The apparatus communicates with the memories under test through a memory address and data bus. |
| US09711236B2 |
Methods and apparatus to program multi-level cell memory using target-only verify
A disclosed example includes generating a first binary value corresponding to a first sensed threshold voltage of a multi-level cell (MLC) memory cell corresponding to a first time at which a bias voltage is applied to a temporary bias cache capacitor of the MLC memory cell; generating a second binary value corresponding to a second sensed threshold voltage of the MLC memory cell corresponding to a second time at which the bias voltage is not applied to the temporary bias cache capacitor of the MLC memory cell; and based on the first and second binary values, selecting whether to program the MLC memory cell using a full program pulse or a partial program pulse. |
| US09711235B2 |
Nonvolatile memory device, storage device having the same, operating method thereof
A nonvolatile memory device includes a voltage generating circuit configured to generate voltages applied to word lines corresponding to a selected memory block among memory blocks. The voltage generating circuit includes voltage source lines having linear voltages, a first voltage generating unit configured to generate a first voltage and apply the generated first voltage to a first voltage source line among the voltage source lines, a second voltage generating unit configured to generate a second voltage and apply the generated second voltage to a second voltage source line among the voltage source lines, and a linear voltage generator having a resistor string connected between the first voltage source line and the second voltage source line. At least one of the voltage source lines has a voltage distributed between the first voltage and the second voltage. |
| US09711233B2 |
Systems and methods for sub-zero threshold characterization in a memory cell
Systems and methods relating generally to data processing, and more particularly to systems and methods for characterizing a solid state memory. In one embodiment, the systems and methods may include programming a first cell of a solid state memory device to a negative voltage, programming a second cell of the solid state memory device to a positive voltage, wherein the second cell is adjacent to the first cell, calculating a voltage shift on the negative voltage programmed to the first cell, characterizing a shifted voltage level on the first cell as an interim voltage, and subtracting the voltage shift from the interim voltage to yield an actual voltage on the first cell. |
| US09711232B2 |
Dynamic non-volatile memory operation scheduling for controlling power consumption of solid-state drives
A memory device and a method for rescheduling memory operations for dynamically controlling power consumption of the memory device is disclosed. The method includes receiving a plurality of memory operations for a plurality of memory arrays of a memory device via a memory channel; storing the plurality of memory operations in a plurality of queues associated with the memory array; receiving a power budget associated with the plurality of memory arrays; determining one or more candidate memory operations in the plurality of queues to meet the power budget for a time window; dynamically rearranging the plurality of memory operations in the plurality of queues and generating rescheduled memory operations that meet the power budget for the time window; and fetching the rescheduled memory operations to the plurality of memory arrays. |
| US09711228B1 |
Apparatus and methods of operating memory with erase de-bias
Methods of operating a memory include developing first and second voltage levels in first and second semiconductor materials, respectively, forming channel regions for first and second groupings of memory cells, respectively, of a string of series-connected memory cells during an erase operation while applying a third voltage level to control gates of the first grouping of memory cells and applying a fourth voltage level to control gates of the second grouping of memory cells. Apparatus include different groupings of memory cells of a string of series-connected memory cells adjacent respective portions of semiconductor material having a first conductivity type and separated from adjacent portions of semiconductor material having the first conductivity type by portions of semiconductor material having a second conductivity type, and a controller configured to apply respective and different voltage levels to control gates of memory cells of respective different groupings of memory cells during an erase operation. |
| US09711226B2 |
Semiconductor memory device
A semiconductor memory device includes a first well of a first conductivity type, a memory cell array including a plurality of memory cells stacked above the first well, the memory cells including a first memory cell transistor, a first wiring above the memory cells array and electrically connected to the first memory cell transistor, and a controller configured to execute an erase operation in which an erase voltage is applied to the first wiring while the first well is in an electrically floating state. |
| US09711225B2 |
Regrouping and skipping cycles in non-volatile memory
A non-volatile memory system utilizes multiple programming cycles to write units of data, such as a logical page of data, to a non-volatile memory array. User data is evaluated before writing to determine whether programming can be skipped for bay addresses. The system determines whether programming can be skipped for an initial set of bay groups. If a bay group cannot be skipped, the system determines whether the bay group includes individual bays that may be skipped. Bays are regrouped into new bay groups to reduce the number of BAD cycles during programming. Independent column addressing for multiple bays within a bay group is provided. During a column address cycle, a separate column address is provided to the bays to select different columns for programming within each bay. By simultaneously programming multiple column addresses during a single column address cycle, the system may skip programming for some column address cycles. |
| US09711223B2 |
Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
Some embodiments include apparatus and methods having a string of memory cells, a conductive line and a bipolar junction transistor configured to selectively couple the string of memory cells to the conductive line. Other embodiments including additional apparatus and methods are described. |
| US09711222B2 |
Content addressable memory cells and memory arrays
A content addressable memory cell is provided that includes plurality of transistors having a minimum feature size F, and a plurality of memory elements coupled to the plurality of transistors. The content addressable memory cell occupies an area of between 18F2 and 36F2. |
| US09711221B1 |
Nonvolatile range-checking content addressable memory
A computer memory provides for range-matching capabilities using a hybrid combination of transistors and multiple resistive memory devices serving in a dual capacity as storage and logic. The result is an extremely compact, nonvolatile range-matching, content addressable memory. |
| US09711215B2 |
Apparatus and method to optimize STT-MRAM size and write error rate
Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row. |
| US09711213B2 |
Operational signals generated from capacitive stored charge
Methods, a memory device, and a system are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the memory cell to enter a conductive state. Once in the conductive state, the memory cell can be set or reset by a pulse formed from parasitic capacitive discharge from various paths coupled to the memory cell. |
| US09711211B2 |
Dynamic threshold voltage compaction for non-volatile memory
Based on performance during programming, the non-volatile memory cells are classified as fast programming memory cells and slow programming memory cells (or other classifications). At a separate time for each programmed state, threshold voltage distributions are compacted based on the classification. |
| US09711208B2 |
Semiconductor storage device with reduced current in standby mode
There is provided a semiconductor storage device in which memory cells can easily be set at a proper potential in standby mode, along with a reduction in the area of circuitry for controlling the potential of source lines of memory cells. A semiconductor storage device includes static-type memory cells and a control circuit. The control circuit includes a first switching transistor provided between a source line being coupled to a source electrode of driving transistors and a first voltage, a second switching transistor provided in parallel with the first switching transistor, and a source line potential control circuit which makes the first and second switching transistors conductive to couple the source line to the first voltage, when the memory cells are operating, and sets the first switching transistor non-conductive and sets a gate electrode of the second switching transistor coupled to the source line in standby mode. |
| US09711206B2 |
Performing logical operations using sensing circuitry
The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry coupled to the array of memory cells. The sensing circuitry includes a primary latch and a secondary latch. The primary latch is coupled to a pair of complementary sense lines and selectively coupled to a pair of adjacent complementary sense lines. The secondary latch is selectively coupled to the primary latch. The primary latch and secondary latch are configured to shift a data value between the pair of adjacent complementary sense lines and the primary latch. The primary latch and secondary latch are configured to shift the data value from the pair of adjacent complementary sense lines without activating a row line. |
| US09711205B2 |
Method of use time management for semiconductor device and semiconductor device including use time managing circuit
A use time managing method of a semiconductor device may include (1) measuring an amount of accumulated operation time of the semiconductor device and when the amount is reached to a predetermined value, generating a unit storage activation signal; (2) repeating step (1) to generate one or more additional unit storage activation signals, thereby generating a plurality of unit storage activation signals, wherein the predetermined values are different for each repeating step; (3) storing data indicating each occurrence of generating the unit storage activation signals; and (4) detecting use time of the semiconductor device based on the cumulatively stored data. |
| US09711204B1 |
Semiconductor device(s) and method of refreshing the semiconductor device
A method of refreshing a semiconductor device may be provided. A semiconductor device may include a refresh control circuit and a memory circuit. The refresh control circuit may be configured to compare addresses generated based on a command with fail addresses to generate a normal word line signal and a redundancy word line signal which are enabled during a predetermined time section from a point of time that the command is inputted to the refresh control circuit. The memory circuit may be configured to inactivate a fail word line connected to a failed memory cell based on the addresses if the normal word line signal is enabled and activates a redundancy word line replacing the fail word line if the redundancy word line signal is enabled. |
| US09711203B2 |
Memory device including boosted voltage generator
A boosted voltage generator may include a difference voltage generator, a first charging circuit, a second charging circuit and a switch circuit. The difference voltage generator generates a difference voltage to a first node, based on a reference voltage and a power supply voltage. The first charging circuit, connected between the first node and a ground voltage, charges the difference voltage therein during a first phase in response to a first pulse signal. The second charging circuit, connected between the first node and the ground voltage, charges the difference voltage therein during a second phase in response to a second pulse signal. The switch circuit, connected to a second node in the first charging circuit, a third node in the second charging circuit and an output node, provides a boosted voltage following a target level to the output node during each of the first phase and the second phase. |
| US09711202B2 |
Electronic device
This technology provides an electronic device. An electronic device in accordance with an implementation of this document may include a semiconductor memory, and the semiconductor memory may include: an under layer including a plurality of material layers having a different crystal structures; a first magnetic layer formed over the under layer and having a variable magnetization direction; a tunnel barrier layer formed over the first magnetic layer; and a second magnetic layer formed over the tunnel barrier layer and having a pinned magnetization direction. |
| US09711200B2 |
Method for computing with complementary networks of magnetic tunnel junctions
A magnetic tunnel junction (MTJ) device is provided that includes a MTJ element and a control wire. The MTJ element includes a top ferromagnet layer formed of a first magnetic material, a tunneling layer, and a bottom ferromagnet layer formed of a second magnetic material. The tunneling layer is mounted between the top ferromagnet layer and the bottom ferromagnet layer. The control wire is configured to conduct a charge pulse. A direction of charge flow in the control wire extends substantially perpendicular to a magnetization direction of the top ferromagnet layer. The control wire is positioned sufficiently close to the top ferromagnet layer to reverse the magnetization direction of the top ferromagnet layer when the charge pulse flows therethrough while not reversing the magnetization direction of the bottom ferromagnet layer when the charge pulse flows therethrough. |
| US09711196B2 |
Configuration bit sequencing control of nonvolatile domain and array wakeup and backup
A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains. |
| US09711193B2 |
Driving signal control circuit and driving apparatus
A driving signal control circuit includes a discharge circuit, a counter circuit, and a control circuit. The discharge circuit is configured to compare a monitored voltage and a reference voltage, and generate a discharge signal. The monitored voltage is proportional to a core voltage. The counter circuit is configured to perform an up/down count operation according to the discharge signal, and generate a count signal. The control circuit is configured to generate a driving signal which has an enable period proportional to the count signal. |
| US09711190B2 |
Stabilizing circuit
A stabilizing circuit is provided that is connected to a biased voltage. The stabilizing circuit is configured to inhibit a change in voltage of the biased voltage caused by a first change in voltage of one or more nodes that are connected to the biased voltage through a first parasitic capacitance. In some embodiments, the stabilizing circuit induces a voltage on the biased voltage through a second parasitic capacitance that changes from a first voltage level to a second voltage level during the first change in voltage such that a total change in parasitic voltage that is induced at the biased voltage during the first change in voltage is close to 0 V. |
| US09711189B1 |
On-die input reference voltage with self-calibrating duty cycle correction
A buffer circuit with an adjustable reference voltage is presented. The buffer circuit with adjustable reference voltage has an input buffer circuit that is connected to a data input and a reference voltage. The output of the input buffer circuit is connected an eye monitor circuit that generates a transition signal based on a number of transitions of an output of the input buffer circuit. The output from the eye monitor circuit is that processed by a calibration control circuit that transmits a selection signal to a multiplexer. The multiplexer selects a level of the reference voltage based on the selection signal from the calibration control circuit. |
| US09711186B2 |
System and method for streaming and recording video
Dynamic buffering of streaming temporal video is disclosed. In at least one embodiment, a non-transitory memory is provided for storing machine instructions that are to be executed by a computer. The machine instructions may implement the following functions: streaming temporal video having a current incomplete segment, dynamically buffering the current incomplete segment to store data associated thereto and a current incomplete segment buffer, and receiving a first input to obtain a start time marker. A video segment may be generated including the current incomplete segment data and video data from the streaming temporal video occurring after the start time marker. The dynamic buffering may include buffering an I-frame and one or more P-frames. For example, only a most recent I-frame may be buffered and then cleared when a new I-frame is generated. The size of the dynamic buffer may be adjusted based on the size/number of P-frames and/or I-frames. |
| US09711173B2 |
Apparatus and method for setting slider surface potential
An apparatus includes a slider body of a disk drive. The slider body is electrically coupled to a plurality of end bond pads. A voltage applied to one more of the end bond pads sets a surface potential of the slider body. |
| US09711172B1 |
Magnetic recording device and reading method
According to one embodiment, a magnetic disk device includes a disk including a tracks including a servo region, a light irradiator configured to irradiate the disk with light and heat the disk with the light, a head including a write head configured to write data in a range irradiated and heated with the light, and a read head configured to read data from the tracks, a controller configured to write first data to be used for offset detection in a first region of the tracks, read the first data from the first region with reference to servo data in the servo region, detect an offset of the read head based on an amplitude of a first signal of the first data, and control a position of the read head based on the offset. |
| US09711171B2 |
Spin-signal enhancement in a lateral spin valve reader
A lateral spin valve reader that includes a detector structure located proximate to a bearing surface and a spin injection structure located away from the bearing surface. The lateral spin valve reader also includes a channel layer extending from the detector structure to the spin injection structure. An exterior cladding, disposed around the channel layer, suppresses spin-scattering at surfaces of the channel layer. |
| US09711167B2 |
System and method for real-time speaker segmentation of audio interactions
A system and method for real-time processing a signal of a voice interaction. In an embodiment, a digital representation of a portion of an interaction may be analyzed in real-time and a segment may be selected. The segment may be associated with a source based on a model of the source. The model may updated based on the segment. The updated model is used to associate subsequent segments with the source. Other embodiments are described and claimed. |
| US09711166B2 |
Decimation synchronization in a microphone
An external clock signal having a first frequency is received. A division ratio is automatically determined based at least in part upon a second frequency of an internal clock. The second frequency is greater than the first frequency. A decimation factor is automatically determined based at least in part upon the first frequency of the external clock signal, the second frequency of the internal clock signal, and a predetermined desired sampling frequency. The division ratio is applied to the internal clock signal to reduce the first frequency to a reduced third frequency. The decimation factor is applied to the reduced third frequency to provide the predetermined desired sampling frequency. Data is clocked to a buffer using the predetermined desired sampling frequency. |
| US09711165B2 |
Process and associated system for separating a specified audio component affected by reverberation and an audio background component from an audio mixture signal
Processes are described herein for transforming an audio mixture for which a specific component is affected by reverberation, into a specific dry component (i.e. unaffected by the reverberation) and a background component. In the process described herein, the long-term effects of reverberation are explicitly taken into account by modelling the spectrogram of the specific component as the result of a matrix convolution along time between the spectrogram of the specific dry component and a reverberation matrix. Parameters of the model are estimated iteratively by minimizing a cost-function measuring the divergence between the spectrogram of the mixture signal and the model of the spectrogram of the mixture signal. |
| US09711162B2 |
Method and apparatus for environmental noise compensation by determining a presence or an absence of an audio event
A method of environmental noise compensation a speech audio signal is provided that includes estimating a fast audio energy level and a slow audio energy level in an audio environment, wherein the speech audio signal is not part of the audio environment, and applying a gain to the speech audio signal to generate an environment compensated speech audio signal, wherein the gain is updated based on the estimated slow audio energy level when the estimated fast audio energy level is not indicative of an audio event in the audio environment and the estimated gain is not updated when the estimated fast audio energy level is indicative an audio event in the audio environment. |
| US09711160B2 |
Smart dock for activating a voice recognition mode of a portable electronic device
A dock for a portable electronic device including a housing, a connector extending from the housing to connect the portable electronic device to the dock, a microphone integrated within the housing, and a processor. The processor is operatively coupled to receive audio input from the microphone, and in response to the audio input, transmit a message to the portable electronic device via the connector to activate a voice recognition mode of the portable electronic device. |
| US09711155B2 |
Noise filling and audio decoding
A noise filling method is provided that includes detecting a frequency band including a part encoded to 0 from a spectrum obtained by decoding a bitstream; generating a noise component for the detected frequency band; and adjusting energy of the frequency band in which the noise component is generated and filled by using energy of the noise component and energy of the frequency band including the part encoded to 0. |
| US09711149B2 |
Display apparatus for performing voice control and voice controlling method thereof
A display apparatus and a voice controlling method thereof are provided. The voice controlling method includes receiving a voice of a user; converting the voice into text; and sequentially changing and applying a plurality of different determination criteria to the text until a control operation corresponding to the text is determined; and performing the determined control operation to control the display apparatus. |
| US09711145B2 |
Word-level correction of speech input
The subject matter of this specification can be implemented in, among other things, a computer-implemented method for correcting words in transcribed text including receiving speech audio data from a microphone. The method further includes sending the speech audio data to a transcription system. The method further includes receiving a word lattice transcribed from the speech audio data by the transcription system. The method further includes presenting one or more transcribed words from the word lattice. The method further includes receiving a user selection of at least one of the presented transcribed words. The method further includes presenting one or more alternate words from the word lattice for the selected transcribed word. The method further includes receiving a user selection of at least one of the alternate words. The method further includes replacing the selected transcribed word in the presented transcribed words with the selected alternate word. |
| US09711140B2 |
Detecting self-generated wake expressions
A speech-based audio device may be configured to detect a user-uttered wake expression and to respond by interpreting subsequent words or phrases as commands. In order to distinguish between utterance of the wake expression by the user and generation of the wake expression by the device itself, directional audio signals may by analyzed to detect whether the wake expression has been received from multiple directions. If the wake expression has been received from many directions, it is declared as being generated by the audio device and ignored. Otherwise, if the wake expression is received from a single direction or a limited number of directions, the wake expression is declared as being uttered by the user and subsequent words or phrase are interpreted and acted upon by the audio device. |
| US09711136B2 |
Speech recognition device and speech recognition method
A speech acquisition unit 1 acquires an original speech uttered freely by a user. A speech data processing unit 7 processes an original speech signal to generate a processed speech signal. An acoustic model switching unit 4 determines one acoustic model from among a plurality of acoustic models 3-1 to 3-x, based on a recognition score for each languagein which a speech recognition unit 5 performs a recognition process on time series data on an acoustic feature of the processed speech signal to be calculated by using the acoustic models 3-1 to 3-x for individual languages. |
| US09711133B2 |
Estimation of target character train
A desired character train included in a predefined reference character train, such as lyrics, is set as a target character train, and a user designates a target phoneme train that is indirectly representative of the target character train by use of a limited plurality of kinds of particular phonemes, such as vowels and a particular consonants. A reference phoneme train indirectly representative of the reference character train by use of the particular phonemes is prepared in advance. Based on a comparison between the target phoneme train and the reference phoneme train, a sequence of the particular phonemes in the reference phoneme train that matches the target phoneme train is identified, and a character sequence in the reference character train that corresponds to the identified sequence of the particular phonemes is identified. The thus-identified character sequence estimates the target character train. |
| US09711131B2 |
Sound zone arrangement with zonewise speech suppression
A system and method for arranging sound zones in a room including a listener's position and a speaker's position with a multiplicity of loudspeakers disposed in the room and a multiplicity of microphones disposed in the room. The method includes establishing, in connection with the multiplicity of loudspeakers, a first sound zone around the listener's position and a second sound zone around the speaker's position, and determining, in connection with the multiplicity of microphones, parameters of sound conditions present in the first sound zone. The method further includes generating in the first sound zone, in connection with the multiplicity of loudspeakers, and based on the determined sound conditions in the first sound zone, speech masking sound that is configured to reduce common speech intelligibility in the second sound zone. |
| US09711130B2 |
Adaptive noise canceling architecture for a personal audio device
A personal audio device, such as a wireless telephone, includes an adaptive noise canceling (ANC) circuit that adaptively generates an anti-noise signal from a reference microphone signal that measures the ambient audio and an error microphone signal that measures the output of an output transducer plus any ambient audio at that location and injects the anti-noise signal at the transducer output to cause cancellation of ambient audio sounds. A processing circuit uses the reference and error microphone to generate the anti-noise signal, which can be generated by an adaptive filter operating at a multiple of the ANC coefficient update rate. Downlink audio can be combined with the high data rate anti-noise signal by interpolation. High-pass filters in the control paths reduce DC offset in the ANC circuits, and ANC coefficient adaptation can be halted when downlink audio is not detected. |
| US09711129B2 |
Extraordinary acoustic absorption induced by hybrid resonance and electrical energy generation from sound by hybrid resonant metasurface
A sound absorbing metamaterial comprises an acoustic impedance-matched surface configured to minimize reflection from an incident acoustic wave. The surface is comprised of an elastic or flexible membrane and a substantially rigid mass mounted on the membrane. A relatively solid surface is provided as a reflective surface and is positioned behind the membrane. The reflective surface is separated by a predetermined distance from the elastic or flexible membrane and forms a fluid space between the membrane and the solid surface. The mass mounted on the membrane, in combination with the elastic membrane establish a plurality of eigenfrequencies. |
| US09711127B2 |
Multi-sensor signal optimization for speech communication
Systems, methods, and apparatus for facilitating multi-sensor signal optimization for speech communication are presented herein. A sensor component including acoustic sensors can be configured to detect sound and generate, based on the sound, first sound information associated with a first sensor of the acoustic sensors and second sound information associated with a second sensor of the acoustic sensors. Further, an audio processing component can be configured to generate filtered sound information based on the first sound information, the second sound information, and a spatial filter associated with the acoustic sensors; determine noise levels for the first sound information, the second sound information, and the filtered sound information; and generate output sound information based on a selection of one of the noise levels or a weighted combination of the noise levels. |
| US09711121B1 |
Latency enhanced note recognition method in gaming
The present invention relates to the field of audio recognition, in particular to computer implemented note recognition methods in a gaming application. Furthermore, the present invention relates to improving latency of such audio recognition methods. One of the embodiments of the invention described herein is a method for note recognition of an audio source. The method includes: dividing an audio input into a plurality of frames, each frame having a pre-determined length, conducting a frequency analysis of at least a set of the plurality of frames, based on the frequency analysis, determining if a frame is a transient frame with a frequency change between the beginning and end of the frame, comparing the frequency analysis of each said transient frame to the frequency analysis of an immediately preceding frame and, based on said comparison, determining at least one probable pitch present at the end of each transient frame, and for each transient frame, outputting pitch data indicative of the probable pitch present at the end of the transient frame. |
| US09711120B1 |
Piano-type key actuator with supplemental actuation
The present invention provides a piano-type key actuator that employs supplemental actuation so as to enable an associated key to become engaged when a typical actuation force is applied anywhere along its entire length, including from within the immediate vicinity of its pivot point, where the key would otherwise be unusable for playing due to the prohibitively large actuation force that would generally be required in this area. By eliminating the unusable portion of a key, a full-function keyboard can be provided in a more compact and portable form. |
| US09711114B1 |
Display apparatus and method of displaying using projectors
A display apparatus and a method of displaying via the display apparatus. The display apparatus includes at least one context image projector or at least one context display for rendering a context image, wherein an angular width of a projection of the rendered context image ranges from 40 degrees to 220 degrees, and at least one focus image projector for rendering a focus image, wherein an angular width of a projection of the rendered focus image ranges from 5 degrees to 60 degrees. An arrangement is made to combine the projection of the rendered focus image with the projection of the rendered context image to create a visual scene. |
| US09711113B2 |
Information code, information code producing method, information code reader, and system which uses information code
A two-dimensional information code is provided. In the code area of this information code, there are formed a specification pattern region in which predetermined-shape specification patterns, such as position detecting patterns, are arranged, a data recording region in which data are recorded using plural types of cells, and an error-correction code recording region in which error correction codes are arranged using the plural types of cells. In the code area, a free space is formed at a position located outside the specification pattern region, the data recording region, and the error-correction code recording region. Data are not recorded by cells in the free space and error correction on the error correction codes is not applied to the free space. The free space has a size larger in area than a single cell. |
| US09711112B2 |
Control signal generation circuit and control signal generation method for controlling luminance in a display device
A control signal generation circuit includes: a first circuit unit which controls, according to inputted video signals, light-up amount of each pixel of a display panel where a plurality of pixels constituted by including a white sub-pixel are disposed; and a second circuit unit which controls luminance of a backlight that lights up the display panel from a back surface. The second circuit unit calculates a saturation feature value in one frame from the saturation value of each pixel, generates a signal for controlling the luminance of the backlight based thereupon, and calculates a luminance increase rate by using the saturation value of each pixel and the saturation feature value. The first circuit unit performs luminance decreasing processing of each pixel according to the luminance increase rate, and supplements the saturation of each pixel according to the light-up amount of the white sub-pixels. |
| US09711111B2 |
High dynamic range display using LED backlighting, stacked optical films, and LCD drive signals based on a low resolution light field simulation
An HDR display is a combination of technologies including, for example, a dual modulation architecture incorporating algorithms for artifact reduction, selection of individual components, and a design process for the display and/or pipeline for preserving the visual dynamic range from capture to display of an image or images. In one embodiment, the dual modulation architecture includes a backlight with an array of RGB LEDs and a combination of a heat sink and thermally conductive vias for maintaining a desired operating temperature. |
| US09711109B2 |
Data processing apparatus for transmitting/receiving compression-related indication information via display interface and related data processing method
A data processing apparatus includes a compressor and an output interface. The compressor generates a compressed display data by compressing a display data according to a compression algorithm. The output interface appends first indication information in a first output bitstream, appends second indication information in a second output bitstream, and outputs the first output bitstream and the second output bitstream via a display interface. The first output bitstream is derived from the compressed display data. The first indication information is set in response to the compression algorithm employed by the compressor. The first indication information is different from the second indication information. The display interface is arranged for coupling to a driver circuit. |
| US09711106B1 |
Display method and display device
The present invention provides a display method and a display system, which belong to the field of display technology and solve a problem of large power consumption in the case of light-load images in existing display methods. The display method includes steps of: detecting, when a frame of image is displayed, a variation degree of data voltages on respective data lines; determining, according to the detection result, a load size of the displayed image; and adjusting, according to the determination result, an operating frequency of a charge pump, and outputting, by the charge pump, a voltage corresponding to the operating frequency to a gate driving unit, so that a gate driving voltage is provided to a gate line by the gate driving unit. The overall power consumption of a display system can be reduced and the performance thereof can be improved by the display method according to the present invention. |
| US09711105B2 |
Gate signal line driving circuit for noise suppression and display device
A gate signal line driving circuit which suppresses noises in a gate signal and a display device which uses the gate signal line driving circuit are provided. A first basic circuit provided to a gate signal line driving circuit includes a HIGH voltage applying switching element which applies a HIGH voltage to gate signal lines in response to a signal HIGH period, and a LOW voltage applying switching circuit which applies a LOW voltage to the gate signal lines in response to a signal LOW period. In response to a signal HIGH period, a switch of the LOW voltage applying switching circuit of the first basic circuit is turned off based on a signal applied to a switch of the HIGH voltage applying switching element of a second basic circuit which assumes a signal HIGH period earlier than the first basic circuit. |
| US09711095B2 |
Electronic apparatus, security processing method and storage medium
According to one embodiment, an electronic apparatus includes a first detector, a second detector, a third detector and a security controller. The first detector detects a speed of movement of the electronic apparatus. The second detector detects a direction of the movement. The third detector detects whether the electronic device is located in a first area. The security controller updates position information wherein the position information is indicative of a first position in the first area, and executes a monitoring process based on the position information, detection information of the first detector and detection information of the second detector. |
| US09711089B2 |
Scan driving circuit and display device
A scan driving circuit, including a multi-stage shift register unit that outputs scan signals by stage under control of a clock signal (CKR, CKBR), the shift register unit includes an output terminal for outputting the scan signals, the scan driving circuit further includes a multi-stage signal generating unit, with an n-th stage signal generating unit is connected respectively to an output terminal of an n-th stage shift register unit and an output terminal of an (n+j)-th stage shift register unit, the n-th stage signal generating unit is configured to convert an outputted first level into a second level under triggering of a scan signal outputted by the n-th stage shift register unit, and convert an outputted second level into a first level under triggering of a scan signal outputted by the (n+j)-th stage shift register unit; the n and j both are positive integers. |
| US09711086B2 |
Display device having shared column lines
A display device having at least a plurality of pixel circuits, connected to signal lines to which data signals in accordance with luminance information are supplied, arranged in a matrix, wherein pixel circuits of odd number columns and even number columns adjacent sandwiching an axis in a column direction parallel to an arrangement direction of the signal lines have a mirror type circuit arrangement symmetric about the axis of the column direction, and there are lines different from the signal lines between signal lines of adjacent pixel circuits. |
| US09711081B2 |
Organic light emitting diode display and method for driving the same
An organic light emitting diode display and a method for driving the same are disclosed. The organic light emitting diode display includes a display panel including a plurality of pixels, a display panel driver configured to drive signal lines of the display panel, and a timing controller configured to divide one frame into a plurality of subframes, convert data of an input image into a bit pattern, map the bit pattern to the plurality of subframes, control an operation of the display panel driver, and adjust a writing speed for writing data and/or an erase speed for turning off pixels of the plurality of pixels during at least one compensation subframe of the plurality of subframes such that the write speed and the erase speed are different from each other. |
| US09711080B2 |
Timing controller, driving method thereof, and display device using the same
Disclosed are a timing controller, a driving method thereof, and a display device using the same. The timing controller includes a memory configured to sequentially store input video data of respective frames, a determiner configured to compare the input video data of respective frames to determine whether a scene is changed, and a converter configured to, when it is determined by the determiner that the scene is changed, in the same scene section until the scene is changed and then changed to another scene, reduce luminance of the input video data included in the scene section, and output image data with reduced luminance. |
| US09711078B2 |
Display device
Disclosed herein is a display device, including: a display panel having a display area having a plurality of pixels each composed of one or more sub-pixels, a first image and a second image being alternately displayed adjacent to each other in the sub-pixels, the first image and the second image being displayed in visual directions different from each other so as to be adapted to be discriminated from each other; and a crosstalk correcting portion having a crosstalk correcting table, configured to carry out crosstalk correction for images different from one another by using the crosstalk correcting table; wherein the display area is divided into a plurality of areas, and gamma correction which differs so as to correspond to the plurality of areas obtained through the division, respectively, is carried out for an image as an object of the crosstalk correction. |
| US09711066B2 |
Endoscope simulator
The Invention provides a method of determining a position of an object in a virtual environment and for assessing a performance in the movement of said object. Preferred embodiments provide an improved endoscope simulator and means for assessing performance in the use of an endoscope. |
| US09711053B1 |
Off-screen traffic information indicator
An offscreen traffic information indicator system includes signal receivers for receiving traffic messages from proximate air and ground vehicles and a traffic indicator for determining the positions of the host aircraft and the proximate vehicles based on the traffic messages. Based on the locations of the host aircraft and proximate vehicles and their proximity to airport runways, the traffic indicator may designate runways as relevant runways (or receive relevant runway designations from the flight management system of the host aircraft) and designate proximate vehicles as relevant to the host aircraft. A display unit may display, along with a dynamic map of a region near the host aircraft, relevant runway indicators for relevant runways within the mapped region and offscreen traffic indicators for relevant aircraft positioned outside the mapped region. |
| US09711051B2 |
Method of determining the position of a vehicle in a traffic lane of a road and methods for detecting alignment and risk of collision between two vehicles
A method for determining a positioning of a subject motor vehicle in a traffic lane of a highway is provided, including: acquiring a number of traffic lanes of the highway; acquiring an image of the highway showing at least a lateral part of the highway; acquiring a datum relating to a direction of travel of the subject motor vehicle on the highway; receiving by the subject motor vehicle one message from another motor vehicle, the message including a first information item relating to a positioning of the other motor vehicle, and a second information item relating to a direction of travel of the other motor vehicle; and deducting the positioning of the subject motor vehicle in one of the traffic lanes, as a function of the number of traffic lanes, the datum, the acquired image, the first and second information item. |
| US09711045B1 |
System and method for traffic preemption emitter type detection and response
A traffic preemption system comprising a vehicle preemption unit configured to mount to a vehicle and transmit a signal comprising one or more identifying pulses, a detection unit configured to, receive the signal transmitted by the vehicle preemption unit, identify a characteristic of the vehicle preemption unit using the one or more identifying pulses, and calculate a timing delay based on the identified characteristic of the vehicle preemption unit, and an intersection preemption unit configured to receive the timing delay from the detection unit and change a traffic light in response to the timing delay. |
| US09711042B2 |
Method and a module for controlling pieces of equipment by sound pulse
Disclosed are methods and devices for controlling pieces of equipment by sound pulses, which include operations and means for determining characteristics of a vector defined by two sound pulses received by at least two receivers. In various implementations, the characteristics may comprise at least the direction and possibly also the sense and the norm of the vector, and these sound pulses may be generated in a zone defined relative to the receivers. The methods and devices may also include operations and means for controlling a piece of equipment where the command applied to the equipment may be determined at least by the direction of the vector. |
| US09711041B2 |
N-phase polarity data transfer
System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. Data is selectively transmitted as N-phase polarity encoded symbols or as packets on differentially driven connectors. A data transfer method comprises encoding data and control signals in a sequence of symbols to be transmitted on a plurality of connectors, and transmitting the sequence of symbols on the plurality of connectors. Each symbol may be transmitted using a combination of a phase state of a first pair of connectors, a polarity of a second pair of connectors, and a selection of at least one undriven connector. Transmission of each symbol in the sequence of symbols may cause a change of state for at least one of the plurality of connectors. |
| US09711033B2 |
System and method for collecting medical waste that monitors the waste for objects that may have been inadvertantly discarded
A mobile cart that holds a bag for receiving solid waste generated during a medical or surgical procedure. The cart includes a sensor that monitors whether or not an object containing metal is placed in the bag. A processor monitors the signal output by the sensor. If the sensor signal indicates that an object with a minimal amount of metal is placed in the bag, the processor momentarily asserts an audible alarm and continuously asserts a light alarm. The light alarm remains asserted until turned off. If, while the light alarm is on, the sensor signal indicates a second object with the minimal amount of waste is placed in the container, the processor again momentarily asserts the audible alarm. This provides notice that it may be necessary to investigate the contents of the bag to determine if not one but two or more objects were inadvertently discarded. |
| US09711031B2 |
Communication state display method and communication state display device
Provided is a communication state display method, the method being used to check a communication state of a communication device that transmits/receives signals to/from a different apparatus by serial communication, the method including: stretching a pulse width of a signal transmitted/received between the communication device and the different apparatus by serial communication; and causing current to flow through an indicator in response to the signal having the stretched pulse width to light the indicator during the current flow. |
| US09711025B1 |
Warning system
A warning system for emergency first responders approaching high voltage power lines, said warning system comprising: a sensor unit; a warning unit. The sensor unit includes a sensor unit comprising: an encasement, an antenna, a voltage meter; a power source; and a transponder. The sensor unit and the warning unit are separated from one another and adapted such that the sensor unit can be attached to the roof of an emergency vehicle or shoes of an emergency responder, and the warning unit can be attached to a dashboard of the emergency vehicle of the body of the emergency responder, and be able to project a warning image for the emergency responder to view. |
| US09711024B2 |
Blasting system protection
A method of controlling the operation of a blasting system which includes the steps of monitoring for the occurrence of electromagnetic interference (EMI) within a defined zone and initiating an alarm upon detection of such interference wherein the initiation of the alarm can automatically inhibit or suspend the operation of the blasting system. |
| US09711019B2 |
Marker with a bone shaped magnetic core
Systems (100) and methods (1700) for providing a marker (102). The methods comprise forming a magnetic core (200) having a bone shape defined by two end portions (208, 212) and a center potion (210) disposed between the two end portions. The end portions each have a cross-sectional area larger than a cross-sectional area of the center portion. A coil (224) is disposed around the center portion. The coil is coupled to a passive electronic component (206) so as to form a resonator. The resonator is disposed in a housing (126) of the marker. The resonator resonates when an interrogation signal is produced by a transmitter circuit (112) located remote from and in proximity to the marker, whereby a variation in a magnetic field occurs. |
| US09711017B2 |
Method, system and wireless device with power management for monitoring protective headgear
A wireless device includes a sensor module generates a wake-up signal and sensor data in response to motion of protective headgear, wherein the sensor data includes acceleration data. A device processing module generates event data in response to the sensor data. A short-range wireless transmitter transmits a wireless signal that includes the event data. A power management module selectively powers the short-range transmitter and the device processing module in response to the wake-up signal. |
| US09711011B2 |
Gaming devices having game modifiers usable between games and stages within games
Embodiments of the present invention are directed to the use of game modifiers that are triggered in a first game and are used in game stages in a subsequent second game. According to some embodiments, a gaming device is configured to play a multi-stage game of chance. After each stage is completed in a first game, it is determined whether any of the game stages have triggered modifications of one or more game modifiers that are used in one or more corresponding game stages in a subsequently played game. The altered game modifiers may modify prizes associated with an incremented one of the game stages in the subsequent game so that the altered modifiers move between game stages in multiple games. |
| US09711010B2 |
Bad beat insurance
In various embodiments, a system and a method of implementing bad beat insurance are disclosed. After a stage of a portion of a game is played, it is determined that a player is favored to win the portion of the game. After the portion of the game is completed, it is determined that the player has suffered a bad beat. The player is compensated at least partially for a loss that the player incurred as a consequence of suffering the bad beat. |
| US09711009B2 |
Card game with fixed rules
Some embodiments include a game of poker in which player actions are fixed by game rules. |
| US09711006B2 |
Electronic method of gaming, a game controller and a gaming system
An electronic method of gaming comprising independently conducting at least two different games in individual ones of a plurality of display areas, each different game conducted based on game data specific to the game, the game data of each different game defining a set of game play rules for the specific game comprising a base game portion carried out each time the specific game is played and a first feature game portion carried out upon a first trigger condition being met such that there are a plurality of base game portions and a plurality of first game portions corresponding to respective ones of the plurality of different games, and upon a first trigger condition being met in respect of one of the games, conducting, in each of the display areas, separate instances of the first feature game portion of the specific game in respect of which the first trigger condition was met, to determine whether to make one or more awards to the player. |
| US09711005B2 |
Mobile gaming system
A gaming apparatus comprising a number of mobile gaming devices and gaming means to provide wagering games to players using the mobile gaming devices. The apparatus comprises at least one credit entering device for entering credit in association with the respective mobile devices, wherein the credit entering device has means for detecting the identity of a mobile device presented to it for crediting and means for receiving a credit amount to be associated with the presented mobile gaming device, and wherein the gaming means includes a memory for storing a respective credit amount in association with identifying data of each respective mobile gaming device. |
| US09711002B2 |
Upright gaming machine having a dual chute
The present invention provides a gaming machine including a cabinet housing which houses a receiver and a dispenser. An opening extends through the housing. A receiver chute extends between the opening and the receiver, with the receiver chute having a first receiver portion. Similarly, a dispenser chute extends between the opening and the dispenser, with the dispenser chute having a first dispenser portion. The first receiver portion and the first dispenser portion are coextensive, such that the cabinet housing both receives and dispenses currency and currency-type media at the opening. |
| US09710997B2 |
System and method for synchronizing indicators associated with a plurality of gaming machines
A system and method for synchronizing indicators of electronic gaming machines. The system providing a plurality of electronic gaming machines each having a control array and at least one electronic display operatively connected thereto, at least one lighting device operatively connected to the plurality of gaming machines and control circuitry, including a programmable processor, operatively connected to the lighting device. The lighting device having elements to present synchronized lighting effects at the plurality of gaming machines, the synchronized lighting effects including an attract mode and an emotive mode. The system registering a condition on at least one gaming machine and electrically transmitting a signal to the lighting device. The lighting device initiating a predetermined lighting effect at the plurality of machines in response to the registered condition. |
| US09710992B2 |
Automatic product dispensing machine
An automatic product dispensing machine comprises: a frame (2) delimiting at least a housing chamber (3); a magazine (4) arranged internally of the housing chamber (3), for containing a series of products (5); at least a display (8) interposed between the housing chamber (3) and the external environment; a control unit (9) active on the display (8) and configured such as to enable visualizing images and/or information. The control unit (9) is further configured such as to switch the display (8) between at least two of the following three operative conditions: a visualizing condition, in which it reproduces at least a datum and/or image that is externally visible, a condition of transparency, in which at least a product (5) contained in the magazine (4) is viewable via the display (8) and a superposing condition, in which at least a product (5) is viewable via the display (8) and at least a datum and/or image and/or film relating to the product is reproduced on the display. |
| US09710990B1 |
Cash management system capable of verifying all of banknotes delivered from backyard area to verification headquarter at one time
A cash management system includes a cloud server, a banknote cash unit and a verification center. The banknote cash unit senses serial numbers of banknotes introduced therein for obtaining serial number data corresponding to the banknotes. The banknote cash unit further uploads the serial number data to the cloud server, such that the verification center downloads the serial number data. The verification center senses the banknotes sent thereto for obtaining the verification data corresponding to the banknotes sent to the verification center and determines whether the serial number data matches the verification data. Accordingly, the cash management system is able to verify all of banknotes delivered from backyard area to verification headquarter at one time. |
| US09710988B2 |
Marginal marks with pixel count
A system, method and computer program for tabulating votes and creating an audit trail is provided. A ballot processing device may include a paper feed mechanism, a computer, a ballot processing application loaded on the computer, and a digital scanning device linked to the computer. The ballot processing application may process the digital image to establish a series of processing results defining one or more voting results for the paper ballot, and also an audit trail. The ballot processing application may process the digital image to define the voting results based on criteria established by election officials, including ambiguous mark criteria. The audit trail enables election officials to verify that particular paper ballots have been processed correctly in accordance with these criteria. |
| US09710985B2 |
Vehicle control apparatus
A vehicle control apparatus includes: a vehicle-mounted transmitter which transmits a first response request signal; a vehicle-mounted receiver which receives, from a portable device, a response signal to the first response request signal; and a controller which allows an operation for welcoming a user carrying the portable device to a vehicle according to a reception state of the response signal. When intermittently transmitting the first response request signal at predetermined intervals via the vehicle-mounted transmitter, the controller determines whether condition set in advance is established. When the condition is established, the controller transmits a second response request signal different from the first response request signal. According to whether the vehicle-mounted receiver receives, from the portable device, a response signal to the second response request signal, the controller stops transmission of the second response request signal and then suppresses transmission of the first response request signal. |
| US09710982B2 |
Hub key service
In embodiments of a hub key service, a device includes a communication interface for communication coordination with one or more associated devices of the device, and the associated devices correspond to hub members. A hub manager is implemented to generate an electronic key that includes access permissions, which are configurable to enable controlled access for the hub members, such as to a building, vehicle, media device, or location. The hub manager can then correlate the electronic key with the device to enable access to the building, vehicle, media device, or location with the device utilized as the electronic key. |
| US09710980B1 |
Biometric attendance tracking system and method using mobile devices
Aspects of the disclosure provide a host mobile device for tracking attendance of a plurality of attendees each operating an attendee mobile device. The host mobile device includes a processor configured to execute program instructions, and a memory configured to store program instructions for causing the processor to receive an access request including attendee identification information of an attendee from an attendee mobile device, determine whether a first set of access conditions are satisfied in response to the access request, and allow the attendee mobile device to submit biometric information of an attendee to the host mobile device when the set of access conditions are satisfied. The first set of access conditions includes whether an operation distance between the host mobile device and the attendee mobile device is shorter than a preconfigured threshold distance defining a border of an area for a session attendees have registered for. |
| US09710978B1 |
Access control system using optical communication protocol
System for controlling access comprises a reader unit (108) which is disposed at a portal (102) to a controlled access area (118) and a wearable access device (WAD) (114) which is worn by a user (116). The reader and the WAD implement a bidirectional optical communication protocol (BOCP) to communicate digital data. The WAD receives an interrogation signal from the reader for initiating an access control interaction. At least one of the reader and the WAD uses a predetermined optical beam width (142, 308) and a boresight direction (140, 306) of an optical beam associated with the wireless optical communication link to facilitate a selective determination as to whether the WAD will respond to the interrogation signal with a reply signal to continue with the access control interaction. |
| US09710974B2 |
Video game processing apparatus and video game processing program
A video game processing apparatus for controlling progress of a video game while displaying a three-dimensional avatar, arranged within a virtual space, on a display screen of a the display device is provided. A three-dimensional partial model is generated on the basis of two-dimensional image data inputted by a user of the video game processing apparatus. The three-dimensional partial model constitutes at least apart of a body of a three-dimensional avatar, including a face portion of the three-dimensional avatar. A plurality of three-dimensional partial models thus generated is stored in a three-dimensional partial model memory. At least one three-dimensional partial model for each scene in the video game is specified from the plurality of three-dimensional partial models. The display device is caused to display the three-dimensional avatar, which includes the specified three-dimensional partial model, in a corresponding scene on the display screen. |
| US09710972B2 |
Immersion photography with dynamic matte screen
A method may include displaying, on one or more display devices in a virtual-reality environment, a visual representation of a 3-D virtual scene from the perspective of a subject location in the virtual-reality environment. The method may also include displaying, on the one or more display devices, a chroma-key background with the visual representation. The method may further include recording, using a camera, an image of the subject in the virtual-reality environment against the chroma-key background. |