| Document | Document Title |
|---|---|
| US09692480B2 |
Method and apparatus for coordinating a cell on a plurality of resource blocks
A method and an apparatus for coordinating a cell on a plurality of resource blocks, and a method for selecting, by a central control device, a mode for coordinating a cell on a plurality of resource blocks in a communication system including a base station and the central control device are disclosed. The method for coordinating a cell comprises: determining whether the cell needs to be muted on at least one resource block; determining a ratio of the resource block on which the cell is muted to the plurality of resource blocks, in a case where the cell needs to be muted on the at least one resource block; and determining, based on the ratio, the resource block on which the cell is muted among the plurality of resource blocks, the resource block being a time resource block, a frequency resource block or a time-frequency resource block. |
| US09692467B2 |
User apparatus and interference reduction process method
A user apparatus for use in a radio communication system, including: an interference reduction process unit configured to reduce, from a received signal received by the user apparatus, an interference signal that becomes interference to a desired signal so as to obtain the desired signal; an interference reduction process execution determination unit configured to measure reception quality of the interference signal, and to determine whether to regard the interference signal as a target of interference reduction processing based on the reception quality, wherein the interference reduction process execution determination unit determines whether to regard the interference signal as the target of interference reduction processing by comparing a first indicator value of the interference signal that is estimated from the reception quality with a second indicator value that is used for transmission of the interference signal. |
| US09692465B1 |
Aggregate interference model and use thereof to evaluate performance of a receiver
A computer implemented hybrid method determines a modeled aggregate interference power distribution at a receiver resulting from multiple radio frequency (RF) interferers. The method determines a respective interference power distribution for each interferer. The method also determines, among the interference power distributions, (i) first interference power distributions that meet a Central Limit Theorem (CLT) criterion, and (ii) second interference power distributions that do not meet the CLT criterion. The method combines the first interference power distributions using the CLT to produce the normal combined interference power distribution, and convolves the second interference power distributions with each other and the normal combined interference power distribution to produce the aggregate interference power distribution. |
| US09692461B2 |
Amplifier module
An amplifier module includes a magnitude detector configured to detect a magnitude of a reflection coefficient, and a phase detector configured to detect a phase of the reflection coefficient The magnitude detector includes an incident signal amplifier configured to amplify an incident signal, an output level controller configured control a level of an output of the incident signal amplifier, a reflected signal amplifier configured to amplify a reflected signal, and a comparator configured to compare an output of the incident signal amplifier with an output of the reflected signal amplifier to output a comparison result indicating whether the magnitude of the reflection coefficient is equal to or greater than a threshold determined based on the control signal. |
| US09692460B2 |
Avionic information transmission system
This system for transmitting avionic information of the type including means for transmitting data frames through at least one transmission network based on avionic switches, intended for corresponding receiving means. The system further includes means for determining the crossing time by at least some of the data frames of at least some of the switches and means on the network for transmitting a corresponding crossing time information frame associated with this data frame, intended for corresponding receiving means. |
| US09692457B2 |
Removing error patterns in binary data
A method and a device for removing pathologic error patterns in binary data are proposed. The method comprises the operations of identifying a pathologic error pattern in the binary data, and inverting all bits of the identified pathologic error pattern. |
| US09692455B2 |
Multi channel memory with flexible code-length ECC
Apparatuses and methods for error correction and detection of data from memory on a plurality of channels are described. An example apparatus includes: a first memory cell array including first input/output nodes; a second memory cell array including second input/output nodes and third input/output nodes; a first error correcting code (ECC) control circuit including fourth input/output nodes and fifth input/output nodes; and a second ECC control circuit including sixth input/output nodes coupled respectively to the third input/output nodes of the second memory cell array. The fourth input/output nodes of the first ECC control circuit are coupled respectively to the first input/output nodes of the first memory cell array. The fifth input/output nodes of the first ECC are coupled respectively to the second input/output nodes of the second memory cell array. |
| US09692452B2 |
Data deduplication with adaptive erasure code redundancy
Example apparatus and methods combine erasure coding with data deduplication to simultaneously reduce the overall redundancy in data while increasing the redundancy of unique data. In one embodiment, an efficient representation of a data set is produced by deduplication. The efficient representation reduces duplicate data in the data set. Redundancy is then added back into the data set using erasure coding. The redundancy that is added back in adds protection to the unique data associated with the efficient representation. How much redundancy is added back in and what type of redundancy is added back in may be controlled based on an attribute (e.g., value, reference count, symbol size, number of symbols) of the unique data. Decisions concerning how much and what type of redundancy to add back in may be adapted over time based, for example, on observations of the efficiency of the overall system. |
| US09692447B2 |
Three dimensional grid compression storage
Various embodiments for data compression by a processor. Levels of data distribution are configured for data processing, including a first level of the data distribution incorporating a GRID network of data storage nodes, and a second level of the data distribution incorporating a GRID network of compressive nodes in communication with the GRID network of data storage nodes. Input/output (I/O) for an associated storage volume is load balanced between the data storage nodes, as data passes through the first level into the second level to be compressed or uncompressed. |
| US09692446B2 |
Delta-Sigma ADC with wait-for-sync feature
An integrated circuit (IC) chip containing a Delta-Sigma (ΔΣ) filter module for a ΔΣ analog-to-digital converter and a method of providing analog to digital conversion are disclosed. The IC chip includes a ΔΣ filter that is connected to receive a digital data stream created by a ΔΣ modulator, provide a multibit data value when a counter reaches a selected number of received bits, and reset the counter responsive to receiving a synchronization pulse. The IC chip also includes a FIFO buffer connected to store the multibit data value only when a synchronization flag is on and to send an interrupt towards a processing unit only after storing a selected number of multibit data values. The IC chip further includes a synchronization module connected to turn on the synchronization flag responsive to receiving the synchronization pulse and to turn off the synchronization flag responsive to the sending of the interrupt. |
| US09692444B1 |
Neutralizing voltage kickback in a switched capacitor based data converter
In accordance with embodiments of the present disclosure, a method of neutralizing voltage kickback associated with a reference buffer of a switched capacitor based data converter having a first switched capacitor coupled to an output node of the reference buffer wherein the first switched capacitor comprises at least one first capacitor and at least one first switch may be provided. The method may include coupling a passive network to the output node of the reference buffer in response to a presence of a condition for encountering the voltage kickback in order to create an approximately equal and opposite voltage kickforward by the passive network to at least partially neutralize the voltage kickback. |
| US09692443B2 |
Circuit and method
Embodiments of the present invention create a circuit having a digital-to-time converter with a high-frequency input for receiving a high-frequency signal, a digital input for receiving a first digital signal, and a high-frequency output for the provision of a chronologically delayed version of the HF signal. In addition, the circuit has an oscillator arrangement for the provision of the high-frequency signal, having a phase-locked loop for adjusting a frequency of the high-frequency signal. The digital-to-time converter is designed to chronologically delay the received high-frequency signal based on the first digital signal received at its digital input. |
| US09692441B2 |
AD converter and AD conversion method
A successive approximation ADC capable of reducing deterioration in AD conversion accuracy due to noise is provided. An AD converter according to an embodiment includes: a DA converter that generates a comparison voltage based on a sampling value obtained by sampling an analog signal, and a successive approximation control signal; a reference voltage generation circuit that generates a reference voltage used for the successive approximation process; a comparator that compares the comparison voltage with the reference voltage and outputs a successive approximation result; a successive approximation processing unit that generates the successive approximation control signal based on the successive approximation result; and a storage unit that stores an expected value of the AD conversion process. The reference voltage generation circuit generates the reference voltage based on the expected value stored in the storage unit. |
| US09692436B2 |
Background calibration of sampler timing errors in flash analog to digital converters
A method for background calibration of sampler offsets in an Analog to Digital Converter (ADC), according to which one of the samplers of the ADC is established as a reference sampler, whose threshold and timing offsets will be the criterion for adjusting threshold offsets and timing offsets of all other samplers. Then each of the other samplers of the ADC, one at a time, is calibrated by selecting an uncalibrated sampler and establishing it as the current Sampler Under Calibration (SUC); disregarding contribution of the SUC to the output of the ADC; adjusting the threshold of the SUC to be identical to the threshold of the reference sampler; performing one-bit cross-correlation between the reference sampler and the SUC; establishing an error surface representing the threshold offset and timing offset of the SUC with respect to the reference sampler; adjusting the threshold and the timing of the SUC to be equal to the threshold and timing of the reference sampler; restoring level of the SUC to its original threshold with respect to the overall ADC and restoring contribution of the SUC to the output of the ADC. |
| US09692433B2 |
Voltage regulator with load compensation
A voltage regulation system provides a relatively stable voltage source without introducing the typical costs of a ground buffer. The disclosed voltage regulation system includes a voltage regulator that is operative to detect a change of the load current and regulate a current bypass mechanism to stabilize a total supply current. For example, the voltage regulator includes a current sensor and a current compensation circuit. The current sensor is configure to generate a current compensation signal based on the load current change, whereas the current compensation circuit is configured to adjust a bypass current in response to the current compensation signal. As a result, the bypass current dynamically compensates the load current change such that the ground voltage of a variable load becomes relatively stable over a range of load currents. |
| US09692432B2 |
Gas cell, quantum interference device, atomic oscillator, electronic device, and moving object
A gas cell includes an internal space in which metal atoms and a buffer gas are sealed. The buffer gas includes a gas mixture including nitrogen gas and argon gas. The mole fraction of the argon gas in the gas mixture is equal to or greater than 15% and equal to or less than 40%. |
| US09692427B2 |
Apparatus and methods for phase-locked loops with soft transition from holdover to reacquiring phase lock
Provided herein are apparatus and methods for phase-locked loops (PLLs). In certain configurations, a clock system includes a PLL, a control circuit, and a holdover circuit that is electrically coupled to an input of the PLL's loop filter via a holdover switch and a variable resistor. The control circuit generates an input clock signal for the PLL based on a selected reference clock signal. When the control circuit determines that the selected reference clock signal is unreliable, the control circuit disables the PLL's feedback loop and turns on the holdover switch. After the selected reference clock signal is changed or otherwise becomes reliable, the control circuit enables the PLL's feedback loop while keeping the holdover switch turned on, and controls a resistance of the variable resistor over time to provide a soft transition from holdover to reacquiring phase lock. |
| US09692426B2 |
Phase locked loop system with bandwidth measurement and calibration
A phase locked loop (PLL) system includes a PLL and a calibration circuit. The PLL has a reference clock input, a voltage controlled oscillator (VCO) clock output, and a feedback clock output. The calibration circuit provides a reference clock signal to the reference clock input of the PLL, induces first and second phase disturbances between the reference clock signal and a feedback clock signal, measures respective first and second zero crossing times of a phase error between the reference clock signal and the feedback clock signal, and estimates a bandwidth of the PLL in response to an average of the first and second zero crossing times. |
| US09692425B2 |
Oscillator, electronic apparatus, and moving object
An oscillator includes a control voltage generator that generates a control voltage between a first reference voltage and a second reference voltage with a digital signal, and a voltage controlled oscillation circuit that outputs a signal at a frequency in response to the control voltage. The control voltage generator includes a first D/A conversion circuit of resistor voltage-dividing type that generates a voltage between the first reference voltage and the second reference voltage. |
| US09692423B2 |
System and method for circuit quantum electrodynamics measurement
A system for quantum computation and a readout method using the same are provided. In some aspects, the system includes at least one qubit circuit coupled to a resonant cavity, wherein each of the at least one qubit circuit is described by multiple quantum states, and a controller configured to provide microwave irradiation to the resonant cavity such that a quantum state information of the at least one qubit circuit is transferred to a resonant cavity occupation. The system also includes a readout circuit, coupled to the resonant cavity, configured to receive signals corresponding to the resonant cavity occupation, and generate an output indicative of the quantum states of the at least one qubit circuit. Optionally, the system further includes at least one single flux quantum (“SFQ”) circuit coupled to the readout circuit and configured to receive the output therefrom. |
| US09692422B2 |
Programmable logic integrated circuit
In a programmable logic integrated circuit, providing a spare circuit in preparation for the occurrence of a defective element results in a redundant circuit configuration. A programmable logic integrated circuit according to the present invention has: a plurality of logic blocks; a switch block for switching the connections between row and column wires by nonvolatile switch elements for switching; and a shifter block for connecting an input/output wire to said switch block. The shifter block includes a redundant wire and is equipped with nonvolatile switch elements for shifting that control the connections of the wires constituting said redundant wire and said row wires. |
| US09692421B2 |
Non-volatile latch circuit and logic circuit, and semiconductor device using the same
A novel non-volatile latch circuit and a semiconductor device using the non-volatile latch circuit are provided. The latch circuit has a loop structure in which an output of a first element is electrically connected to an input of a second element and an output of the second element is electrically connected to an input of the first element through a second transistor. A transistor using an oxide semiconductor as a semiconductor material of a channel formation region is used as a switching element, and a capacitor is provided to be electrically connected to a source electrode or a drain electrode of the transistor, whereby data of the latch circuit can be retained, and a non-volatile latch circuit can thus be formed. |
| US09692420B2 |
Programmable circuit components with recursive architecture
A circuit component that is adjustable at run time and a method of designing the circuit are disclosed. The component contains a hierarchy of recursive levels in which a bottom level is a compound element made from two connected simple elements, and each higher level contains two compound elements connected in the same fashion. The described circuit allows for a large number of available values of the component value to be arranged in a logarithmic fashion rather than a linear one as in the prior art, thus generally reducing errors between any desired value for the component and the available values. In addition, such compound elements reduce the power dissipated by the analog element and the susceptibility to noise as compared to prior art adjustable components without adversely affecting the overall gain of the circuit. |
| US09692417B1 |
Transition glitch suppression circuit
A transition glitch suppression circuit can be used to remove unwanted glitches occurring within a time delay of the rising edge or falling edge of a signal. The transition glitch suppression circuit has a delay element that can delay the input signal by the time delay to generate a delayed input signal. The transition glitch suppression circuit also has first and second logic circuits that process the input signal and the delayed input signal to generate corresponding outputs. A multiplexer provides the output signal for the suppression circuit by selecting between the output of the first logic circuit and the output of the second logic circuit based on the value of the output signal. |
| US09692412B2 |
Surface protective sheet, electronic device, and method for manufacturing electronic device component
Provided is a surface protective sheet whereby antifouling properties are enhanced and excellent wiping properties and sliding properties are ensured, the present invention is a surface protective sheet (1) having a protective film (3) on a surface of a substrate (2). The protective film (3) is configured from a cured product of a curable composition, the curable composition includes a coating material and a curable resin. The coating material is configured from a reaction product of at least compounds A, B, C and D. Compound A is an acrylic polymer having a hydroxyl group in a side chain thereof, compound B is a diisocyanate, compound C is a polyether polyol, and compound D is a photopolymerizable compound having both a hydroxyl group and a photopolymerizable group. The content of the coating material and the curable resin in the curable composition is preferably 2 parts by mass or more and 40 parts by mass or less of the coating material and 60 parts by mass or more and 98 parts by mass or less of the curable resin when the total amount of the coating material and the curable resin is 100 parts by mass. |
| US09692411B2 |
Integrated level sensing printed circuit board
A level sensing circuit board featuring at least one processor and at least one memory including computer program code, where the at least one memory and computer program code are configured, with the at least one processor, to cause the apparatus at least to: respond to a signal containing information related to the electrical conductivity of a material causing a stimulus to a sensing plate that corresponds to a positive plate of a capacitor directly connected to an input of a comparator that forms part of a variable frequency oscillator; and determine a proportional response containing information about the material causing the stimulus to the sensing plate based at least partly on the signal received. The level sensing circuit may be used as a means to turn a pump on or off based on a sensed fluid level. |
| US09692407B2 |
Circuit and method for detection of failure of the driver signal for parallel electronic switches
There is described a method for driving paralleled electronic switches via a drive signal processing circuit (1) connected to respective driver circuits (5A, 5B) associated with said electronic switches (7 A, 7B). During the turn-off intervals of the electronic switch, the driver circuit sends a fault signal to the drive signal processing circuit. During the turn-off intervals of the electronic switch, the driver circuit masks the fault signal coming from the drive circuit of the electronic switch. |
| US09692406B2 |
Power device drive circuit
A power device drive circuit reduces the short-circuit resistance of a power device that switches an input voltage. The power device drive circuit includes an output amplifier that applies a control voltage to a control terminal of the power device so as to be turned on and off, and an internal power supply circuit that generates a drive voltage of the output amplifier in accordance with a change in the input voltage, thereby causing the control voltage to change. In particular, the internal power supply circuit reduces the drive voltage of the output amplifier when the input voltage rises, thereby reducing the short-circuit current of the power device. |
| US09692402B2 |
Method, apparatus, system for centering in a high performance interconnect
In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern. |
| US09692400B2 |
Pulse width widener and a memory system including the same
A pulse width widener includes a delay circuit, a processing circuit, and a latch circuit. The delay circuit generates a first signal by delaying an input signal including a first pulse by a delay time. The processing circuit generates a second signal, and the second signal includes information of a second pulse that is temporally extended from the first pulse when a width of the first pulse is smaller than the delay time, based on the first and second signals. The latch circuit stores the second signal and outputs the second pulse as an output signal. |
| US09692397B2 |
Carbon based CMOS sensor ring oscillator
A structure is provided for sensing an analyte in an environment. The structure may include a ring oscillator on a semiconductor substrate, the ring oscillator includes an AND gate, an odd number of inverters, and a carbon device connected in series, the carbon device is exposed to an environment such that a frequency of the ring oscillator changes when the carbon device is exposed to the analyte in the environment. |
| US09692394B1 |
Programmable low power high-speed current steering logic (LPHCSL) driver and method of use
An integrated circuit comprising, a voltage regulator circuit and a programmable low power high-speed current steering logic (LPHCSL) driver circuit coupled to a common supply voltage. The voltage regulator circuit includes a native source follower transistor having a negative threshold voltage to provide more headroom for the voltage regulator to operate. The LPHCSL driver circuit includes a plurality of selectable output driver legs and a plurality of programmable resistors. The ability to use a common supply voltage and the ability to select multiple output impedance drivers reduces the die area without increasing the complexity of the integrated circuit. |
| US09692388B2 |
High frequency module comprising a band-pass LC filter and a piezoelectric resonator
Provided is a high frequency module capable of reducing size and cost. A high frequency module includes an LC filter having an inductor formed through a thin film process and a capacitor also formed through a thin film process, and a piezoelectric resonator that is connected in series to the LC filter and serves as a trap filter having a resonant frequency at the outside of a passing band of the LC filter. |
| US09692384B2 |
System and method for audio volume control
Method for audio volume control, the method comprising the steps of: receiving (301) a volume change request; changing (304) the volume according to a volume change step; the method being characterized in that the volume change step determination (302) is executed by applying one or more rules wherein each rule provides a definition of at least two ranges, with respect to a monitored condition, wherein the volume change step, associated with each such range, is different; storing a new volume change step in a volume step register (120). |
| US09692381B2 |
Symmetric linear equalization circuit with increased gain
Circuits providing low noise amplification with continuous time linear equalization are described. An exemplary circuit includes four amplification elements, such as MOS transistors. The amplification elements are arranged in differential pairs, and the differential pairs are cross-coupled with a frequency-dependent coupling, such as a capacitive coupling, to enhance high-frequency gain. The outputs of the amplification elements are combined to provide an output representing inverted and un-inverted sums of differences in the input signals. |
| US09692376B2 |
Controlled switched capacitor coefficients
A switched capacitor circuit including two or more capacitors arranged in a switched capacitor circuit configuration with a comparator comparing a node whose potential varies with the charging of one or more of the switched capacitors. The switched capacitor circuit also has two or more current sources scaled relative to one another coupled to the capacitors and to the comparator, where the current from one current source charges at least two of the capacitors in series during the charge portion of the cycle, and the other current source charges at least one of but at least one fewer of the capacitor(s) during the charge portion of the cycle, and where the current sources are enabled at the beginning of the charge portion of the cycle, but where the comparator disables the current sources once the node reaches a reference potential. |
| US09692372B2 |
Amplifier for electrostatic transducers
A class D audio amplifier provides both an audio output signal and a DC bias voltage to an electrostatic transducer (9). In the amplifier, a modulated sequence of pulses is generated by an input module (1) in response to an input audio signal. The sequence of pulses is amplified by an output module (3) using high speed switching output transistors (4, 5). An output signal is generated by applying a low pass filter (8) to the amplified pulses, and the output signal is provided to the transducer to produce audible output. The amplified sequence of pulses is also used to drive a voltage multiplier module (10) to provide bias voltage for the electrostatic transducer (9). In other embodiments, the bias voltage is provided by a bias voltage module which reverses the bias voltage at intervals, and a phase reverser (13) reverses the phase of the signals fed to the output module (3) simultaneously with reversal of the bias voltage. |
| US09692370B2 |
Biasing circuitry
A biasing circuitry is disclosed. The biasing circuitry includes a biasing module, electrically connected to a power amplifier; and a control series, having an end electrically connected to a positive voltage, and another end electrically connected to the biasing module. The control series includes a switch unit, controlled by a control voltage to be on or off; and a voltage-drop unit, connected to the switch unit in series. The voltage-drop unit is configured to adjust a bias point of the power amplifier. |
| US09692367B2 |
T-shaped power amplifier cooling plate
Cooled electronic circuitry may include multiple and substantially parallel circuitry surfaces, each containing power amplifier circuitry, having a side edge, and includes material between at least a portion of the base plate and the side edge that provides a level of thermal conductivity of at least 167 W/m-k; and a cooling plate having a flat surface attached to each of the side edges of the circuitry surfaces in a thermally-conductive manner. |
| US09692365B2 |
Electronic preamplifier system
A graphene microphone preamplifier is a minimalist design working in class A with large quiescent current in a push-pull configuration, with automatic balancing of voltage imbalance. |
| US09692363B2 |
RF power transistors with video bandwidth circuits, and methods of manufacture thereof
Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor, an impedance matching circuit, and a video bandwidth circuit. The impedance matching circuit is coupled between the transistor and an RF I/O (e.g., an input or output lead). The video bandwidth circuit is coupled between a connection node of the impedance matching circuit and a ground reference node. The video bandwidth circuit includes a plurality of components, which includes an envelope inductor and an envelope capacitor coupled in series between the connection node and the ground reference node. The video bandwidth circuit further includes a first bypass capacitor coupled in parallel across one or more of the plurality of components of the video bandwidth circuit. |
| US09692357B2 |
Power amplifier modules with bifet and harmonic termination and related systems, devices, and methods
One aspect of this disclosure is a power amplifier module that includes a power amplifier die including a power amplifier configured to amplify a radio frequency (RF) signal, the power amplifier including a heterojunction bipolar transistor (HBT) and a p-type field effect transistor (PFET), the PFET including a semiconductor segment that includes substantially the same material as a layer of a collector of the HBT, the semiconductor segment corresponding to a channel of the PFET; a load line electrically connected to an output of the power amplifier and configured to provide impedance matching at a fundamental frequency of the RF signal; and a harmonic termination circuit electrically connected to the output of the power amplifier and configured to terminate at a phase corresponding to a harmonic frequency of the RF signal. Other embodiments of the module are provided along with related methods and components thereof. |
| US09692355B2 |
Oscillator for high-frequency signal generation
An oscillator for high-frequency signal generation is disclosed. Provided according to the present invention is an oscillator for high-frequency signal generation comprising: a first transistor comprising a first collector for receiving a power supply voltage from a load, a first base connected to a ground, and a first emitter connected to the first base; and a second transistor comprising a second collector for receiving a power supply voltage from the load, a second base connected to a ground, and a second emitter connected to the second base, the oscillator having a common-base cross-coupled structure in which the first collector and the second emitter are cross-coupled and the second collector and the first emitter are cross-coupled. |
| US09692352B2 |
Solar collector and conversion array
A solar array for collecting sunlight that is converted into electricity. The array includes an arrangement of solar collectors strategically positioned on a frame to maximize the amount of sunlight collected in relation to the size of the array. The collectors are plate like members with a reflective side and shaped so that sunlight collected by the reflective side is concentrated at a location away from the reflective side. The collectors are recumbently positioned in rows with their respective reflective sides directed away from the array frame. The collectors are spaced apart so that no collector casts shade on any part of another collector and substantially no sunlight between adjacent collectors. |
| US09692347B2 |
Airflow-confirming HVAC systems and methods with variable speed blower
Systems and methods involve controlling a variable-speed blower in a heating, ventilating, and air conditioning (HVAC) system to ensure the setting of a blower-proving switch to confirm airflow in a building. In one instance, a method involves ramping up the variable-speed blower so that the associated static pressure reaches a making point pressure of the blower-proving switch and then reducing the power to a desired power level. The method may also include maintaining the power level above a breaking point pressure. Other systems and methods are presented. |
| US09692345B2 |
Motor drive device
A motor drive device is provided which is able to reduce loss between a drive power source and a controller. The motor drive device includes a plurality of motors, a single drive power source which drives these motors, and a controller which controls energizing times during which motor coils of the plurality of motors are energized, by a PWM drive method. The controller includes phase shift portion which sets a PWM signal for causing a current to flow to the motor, into a phase different per motor. By the phase shift portion setting the PWM signal for causing a current to flow to the motor into a phase different per motor, so-called overlap of energizing times of currents is avoided. |
| US09692343B2 |
Controller calculating a distribution value to control electric current flow
A controller controls a rotating electric machine that has a plurality of winding wire groups, by using an instruction calculator, a temperature calculator, a distributor, and an electric current control section. The instruction calculator calculates an assist instruction value regarding a drive of the machine. The machine has systems each having a combination of a winding wire group and an inverter. The distributor distributes the assist instruction value among the winding wire groups according to system temperatures, for the calculation of torque instruction values for the respective winding wire groups. In such manner, an overheat of the machine and the inverters is prevented. |
| US09692342B2 |
Brushless motor and motor control device
A brushless motor for an electric power steering device that assists a steering operation includes: a stator having a plurality of winding sets for a plurality of systems respectively; and a rotator having a ferrite magnet. In the motor, a maximum current flowing without any demagnetization at high temperature is large. Hence, the torque of the motor is easily ensured at high temperature. In particular, when a failure occurs in one system, it is easy to ensure the torque of the normal system even at high temperature. |
| US09692339B2 |
Method and system for estimating differential inductances in an electric machine
A self-commissioning method for estimating differential inductances in an electric machine, such as e.g. a synchronous reluctance machine or interior permanent magnet machine, with cross-magnetization effects is provided. The electric machine is driven with PWM voltages to explore current plurality of operating points of the currents in the electric machine while keeping the electric machine at standstill or quasi-standstill. At each operating point PWM switching voltage transients are used as a small-signal excitation. Currents of the electric machine are measured by means of oversampling, which permit the reconstruction of the waveforms including the current ripple within a PWM period caused by the PWM switching transients. Finally, the differential inductances at each operating point are determined based on the determined direct and quadrature current waveforms and voltages. |
| US09692338B2 |
Automatic and adaptive defluxing device and method implementing such a device
A vector control driving device is provided for an electric motor receiving an operating setpoint, with stator windings receiving a driving current and producing a rotating magnetic field, the windings generating a voltage at terminals of the motor, a rotor producing a magnetic field to follow the rotating magnetic field, the device generating current in a vector domain, and configured to carry out a transform of the current from the vector domain to a real domain allowing for generation of the driving current, and configured to carry out an inverse transform of a parameter measured in the real domain on the stator windings into a transform of the parameter in the vector domain, and comparing the value of the inverse transform of the parameter with a predefined maximum parameter value, which can drive the generating of the current in the vector domain. An automatic and adaptive defluxing method is provided. |
| US09692332B2 |
Power conversion device
A failure in the activation, of a motor, caused by external noise superimposed on an induced voltage is reduced. A detection circuit is connected to a connection node provided between an upper-arm switching element and a lower-arm switching element, and detects the induced voltage of a fan motor before activation. The switching controller activates the fan motor in accordance with a result of detection by the detection circuit. While the detection circuit detects the induced voltage, the switching controller performs switching control which involves alternately turning ON and OFF of the lower-arm switching element. |
| US09692331B2 |
BLDC adaptive zero crossing detection
BLDC adaptive zero crossing detection compares BEMF voltages from a floating phase of a BLDC motor to a reference voltage, measures a rising time interval during a rising BEMF period when the BEMF voltages are greater than the reference voltage, and a falling time interval during a falling BEMF period when the BEMF voltages are less than the reference voltage. The reference voltage is adjusted so that the rising and falling time intervals are substantially the same, thereby causing the drive voltage to be in phase with the motor self-generated voltage, thus ensuring maximum efficiency of the BLDC motor. |
| US09692330B2 |
Motor driving device
The present invention provides a motor driving device without an additional signal line for identifying whether a motor rotates stably. The motor driving device (21) includes a control circuit (100) for receiving an acceleration signal (SU) and a deceleration signal (SD), and generating a driver control signal (S10); a driving circuit (200) for generating a motor driving signal (S3) according to the driver control signal (S10); and a phase-locked identifying circuit (500) for monitoring an input mode of the acceleration signal (SU) and the deceleration signal (SD), and identifying whether the motor rotation speed is stable at the desired target rotation speed. |
| US09692329B2 |
Magnetic sensor and an integrated circuit
The present teaching relates to a magnetic sensor comprising an input port, a magnetic field detecting circuit that generates a magnet detection signal, an output control circuit that controls operation of the magnetic sensor, and an output port. The magnetic field detecting circuit includes a magnetic sensing element that detects an external magnetic field and output a detection signal, a signal processing element configured to amplify the detection signal and removing interference from the detection signal, and an analog-digital conversion element configured to convert the processed detection signal into a magnet detection signal, and the output control circuit controls the magnetic sensor to operate in at least one of a first state and a second state responsive to at least the magnet detection signal, wherein the signal processing element comprises a folded cascode amplifier. |
| US09692326B2 |
Circuit and method for reducing inrush current of a three phase motor
A method and circuit for starting a three-phase motor in a manner that reduces inrush current normally associated with starting an AC motor. The method uses the circuit to start the three phase motor gradually with three phase alternating current having relatively low frequency and gradually increasing the frequency up to or above the motor operating frequency over a period of time and then switching in a steady state or static three phase alternating power supply to power the three phase motor. |
| US09692324B2 |
System comprising a secondary device with a piezoelectric actuator wirelessly supplied and controlled by a primary device
A system for contactless transmission of energy and control signals between a primary device and a secondary device. The primary device has a primary set with at least one primary coil and an electronic supply driver for supplying primary signals to the primary set of primary coils. A secondary device has a secondary set with at least one secondary coil, at least one piezoelectric actuator, and electronic components including a resonant circuit powered by the secondary set. The piezoelectric actuator is powered and controlled through the secondary set of secondary coils and the electronic components. |
| US09692322B2 |
Inverter with improved shoot through immunity
An inverter phase leg for a DC-AC inverter includes a high supply line and a low supply line across which a DC voltage is provided. A high side gate controlled switch is connected to the high supply line and a low side gate controlled switch is connected to the low supply line, with an output node between the high side switch and the low side switch. An inverting driver is connected to the high side gate controlled switch. The inverting driver's voltage source is configured in such a way as to hold the high side gate controlled switch off during the turn on cycle until the driver output has overcome the negative bias generated across the high side switch gate, producing high immunity to spurious turn on. A digital isolator is connected between the inverting driver and a control signal for switching the inverter phase leg. A differential transmitter and differential receiver may be used to further increase noise immunity. |
| US09692318B2 |
Synchronous rectifier, use of such a synchronous rectifier in a switching power supply, as well as a switching power supply
A synchronous rectifier, which rectifies an alternating voltage signal as an input signal and/or forwards a dc voltage signal as an input signal for use as an output signal. Included is a rectifying unit composed of at least one controllable switch element; a smoothing unit, which is connected to the rectifying unit and smooths the signal rectified or forwarded by the rectifying unit, in order to provide a smoothed signal for use as output signal; a control logic, which controls the rectifying unit based on the input signal and the output signal coming from the smoothing unit. |
| US09692314B2 |
Detection circuit and three-phase AC-to-AC power converting apparatus incorporating the same
A detection circuit for an AC-to-AC power converter includes a voltage divider circuit that has three AC input terminal coupled respectively to three input ends of a power converter which are to receive respectively three AC input power signals with different phases, and that receives a predetermined first reference voltage. Upon receiving one AC input power signal, the voltage divider circuit outputs a divided voltage, which during an active period of the one AC input power signal, is greater than a predetermined second reference voltage, to a comparator, which also receives the predetermined second reference voltage, such that the comparator outputs a detection signal that is in an active state when the one AC input power signal is. |
| US09692313B1 |
DC-AC conversion circuit having a first “double ended” DC pulse stage and a second AC stage
A voltage converter system includes a first DC-AC voltage converter that converts a first DC voltage signal to a first AC voltage signal. A DC link converts the first AC voltage signal to a second DC voltage signal. A second DC-AC voltage converter converts the second DC voltage signal to a second AC voltage signal. In another configuration a DC-AC voltage converter converts a DC voltage signal to a first AC voltage signal. An AC-AC voltage converter converts the first AC voltage signal to a second, lower-frequency AC voltage signal. In yet another configuration a first voltage converter portion converts a DC voltage signal to pulses of DC voltage. A second voltage converter portion converts the pulses of DC voltage to a relatively low-frequency AC voltage signal. The voltage converter system is selectably configurable as a DC-AC voltage converter or an AC-DC voltage converter. |
| US09692312B2 |
Power conversion apparatus, and air-conditioning apparatus using the same
A power conversion apparatus includes a rectifier, a converter including a reactor, a switching element, and a reverse current prevention element, a smoothing capacitor configured to smooth the output voltage, a current detector configured to detect a reactor current, a voltage detector configured to detect the output voltage, and a converter control unit configured to control operation of the switching element of the converter. The converter-control unit includes a switching command calculation unit configured to calculate a switching command value responsive to a ratio of the rectified voltage to the output voltage in accordance with the output voltage and the reactor current, a switching control unit configured to control operation of the switching element in accordance with the switching command value, and a supply abnormality determination unit configured to determine occurrence of a momentary power failure or voltage sag in accordance with the switching command value. |
| US09692311B2 |
High-voltage direct current converter including a 12-pulse diode recitifier connected in series with a voltage-source converter
The present invention relates to a high-voltage direct current (HVDC) converter comprising: a 12-pulse diode rectifier having two three-phase bridge diode rectifiers connected in series to rectify, to 12 pulses, alternating current (AC) power inputted from a point of connection on the sea; and a voltage-source converter connected in series to a lower end of the 12-pulse diode rectifier, wherein the voltage-source converter controls a voltage of the AC power inputted from the point of connection on the sea and a DC link voltage of the voltage-source converter. |
| US09692305B2 |
Resonant DC/DC power converting circuit and method for controlling the same
A method for controlling a resonant DC/DC power converting circuit is provided. The resonant DC/DC power converting circuit having a converter output and a converter input comprises at least two converters having similar structures and outputs connected in parallel as said converter output, and a controller. Each converter comprises a full-bridge inverter unit and a resonant unit. The full-bridge inverter unit is configured with at least four switches. The resonant unit is coupled with said full-bridge inverter unit. The controller outputs two groups of driving control signals to drive four switches in said two converters respectively. The method comprises: making said two converters operate at the same frequency and interleave with preset phase shift; and making two of driving control signals in one group interleave with preset angle to reduce output current of said converter corresponding controlled thereby, when output currents of said two converters are not approximately equal. |
| US09692293B2 |
Power conversion circuit having fault protection and voltage balance functions
A circuit includes a switching module, a control module, and a driving module. The driving module is electrically coupled between the control module and the switching module for generating a driving signal. The driving module includes a normal driving unit and a fault protection unit. The normal driving unit is for turning on and off the switching module according to a first command signal from the control module. The fault protection unit is for lowering the driving signal from a driving value to a protection value according to a second command signal from the control module during a fault protection period after the control module receives a fault signal. |
| US09692281B2 |
Method for producing rotor laminated core
There is provided a method for producing a rotor laminated core by laminating circular core pieces. The method determines a first blanking area, a second blanking area and a third blanking area in the magnetic steel board, wherein the first blanking area defines a shape of the core piece, the second blanking area defines a shape of a magnet-insertion hole, and the third blanking area defines a shape of an arbitrary part in the magnetic steel board. The method also forms a temporary aperture in the second blanking area, forms a thinning part which extends from the temporary aperture to the third blanking area, and blanks the first blanking area, the second blanking area and the third blanking area, thereby producing each circular core piece including the thinning part and magnet-insertion holes formed in a circumferential direction. |
| US09692280B2 |
Laminated core, VR type resolver and production method for laminated core
A production method for a rotor core for a VR type resolver has a structure in which one protrusion is formed on an inner edge thereof in which the rotor cores can be rotated and laminated without increasing cost. In a production method of a rotor core for a VR type resolver, a plurality of tabular rotor core pieces are laminated. In this case, in the rotor core pieces, four protrusions are simultaneously formed, one of them is left, the remainder thereof is removed, and rotating lamination is carried out. |
| US09692279B2 |
Wound field rotating machine with capacitive power transfer
An electrical rotating machine, such as a generator or motor, communicates power from a stationary location to the rotating rotor of the rotating machine via opposed pairs of capacitor plates, one plate of each pair rotating with the rotor and one plate of each pair fixed not to rotate. In one embodiment, separation between the plates of the pair is provided by a cushion of entrapped air. |
| US09692278B2 |
DC motor for driving assemblies of a motor vehicle
A DC motor for driving components of a motor vehicle includes a housing radially surrounding a stator and a rotor. An end plate axially bond to the DC motor comprises a center which has a drive shaft project there-through, and two connection contacts projecting therefrom which supply a voltage to the DC motor. A printed circuit board has electronic components providing an interference-suppression arranged thereon. The printed circuit board comprises conductor paths, a central opening having the drive shaft projects there-through, and two plug-through openings having the two connection contacts project there-through. An earth connection device producing an earth connection of the printed circuit board is provided as a metal sheet arranged axially between the printed circuit board and the end plate. The metal sheet comprises a first contact element connected to the housing, and a second contact element connected to the conductor paths of the printed circuit board. |
| US09692277B2 |
Integrated electric motor assembly
An integrated drive system assembly is provided that combines an electric motor, a power inverter assembly and a gearbox into a single, multi-piece enclosure. Combining these components into a single enclosure reduces weight, reduces drive system complexity, reduces system volume, simplifies assembly integration into an electric vehicle, reduces manufacturing cost, allows the flexible and lengthy electrical cables between the power inverter and the electric motor to be replaced with short, low loss, rigid bus bars, and simplifies component cooling by allowing the use of a common thermal management system. The common thermal management system includes a liquid coolant loop that is thermally coupled to the electric motor, the power inverter assembly and the gearbox. |
| US09692275B2 |
Alternative energy generator
Approaches presented herein enable an alternative energy generator to generate electricity and scaled voltage by placing stationary rare earth magnets on a rotating plate in such a manner that an electric current is produced when the magnets on the plate are moved and the magnet flux lines cut across a stationary metal coil. More specifically, one or more stationary metal coils are positioned near a rotating plate on which a set of magnets are places, the metal coils oriented to be crossed by magnetic flux lines of the magnets. Alternatively, a set of magnets or metal coils are place on a rotating plate with one or more stationary magnets oriented near to yield crossed magnetic flux lines. The rotating plate may be driven by a motor, a hand crank, or any human motion with a set of gears to facilitate rotational torque. |
| US09692273B2 |
Spindle motor, electronics device and disk drive apparatus
A rotating portion of a spindle motor includes a rotor magnet, a circular plate portion, and an annular raised portion that projects downward from the circular plate portion. A stationary portion includes a stator, a base portion, and an annular recessed portion configured to accommodate the raised portion. The raised portion includes an inner circumferential surface and an outer circumferential surface. The inner circumferential surface is positioned radially opposite a first side surface of the recessed portion with a first minute gap intervening therebetween. The outer circumferential surface is positioned radially opposite a second side surface of the recessed portion with a second minute gap intervening therebetween. The first minute gap has an axial dimension greater than an axial dimension of a seal portion. |
| US09692272B2 |
Electric machine and associated method
A bearing assembly cooperates with a bearing seat formed in a bearing housing and includes a bearing having an inner ring, an outer ring and a rolling element in engagement with the rings and an anti-rotation device. The anti-rotation device engages the outer ring to the bearing housing limiting rotation of the outer ring within the bearing seat. The anti-rotation device includes a first feature engaging the outer ring and a second feature engaging the bearing housing. The features limit the rotation of the outer ring within the bearing seat. The first feature has a resilient protrusion with a contact surface for engagement with the outer ring. |
| US09692268B2 |
Conductive wire unit and generator with closed magnetic path
A stator for a generator, comprises a coil support frame and a conductive wire unit arranged on the coil support frame, wherein the conductive wire unit comprises one basic conductive wire unit or a plurality of stacked basic conductive wire units, the basic conductive wire unit comprises a conductive wire layer and a magnetic-conducting sheet conformably stacked on and insulated from the conductive wire layer. A generator with closed-magnetic-path comprises a rotor and a stator, wherein the stator comprises the above conductive wire unit having a magnetic-conducting base plate, wherein the stator further comprises a magnetic yoke, the rotor comprises a transmission shaft, the conductive wire unit is fixedly connected in the magnetic yoke, at least a magnetic-conducting plate is coaxially connected on the transmission shaft, a magnet is connected on the magnetic-conducting plate, of which a magnetic pole is arranged towards the conductive wire unit. |
| US09692266B2 |
Spoke-type PM machine with bridge
A rotor of a permanent magnet synchronous machine includes a rotor core structure. A first set of apertures are formed in a first radial layer of the rotor core structure having a first set of permanent magnets disposed therein forming respective poles. A second set of apertures formed in a second radial layer of the rotor core structure of each pole. A third set of apertures is formed in a third radial layer of the rotor core structure. A second set of permanent magnets is inserted within the third set of apertures. A plurality of bridges each extends across a respective side of each of the third set of apertures in the third radial layer. The plurality of bridges provides structural support of the rotor core structure when operating. The plurality of bridges are integrally formed as single-piece laminations. |
| US09692259B2 |
Power management and priority charging assignments
Systems and methods are provided for managing power to devices in a network, using a centralized power allocation controller. The method of managing power consumption of a plurality of devices includes receiving scheduled upcoming calendar events and/or activities from one or more of a plurality of devices connected in a network. The method further includes centrally managing power consumption of a device of the plurality of devices in the network based on the scheduled upcoming calendar events and/or activities. |
| US09692257B2 |
Control device, conversion device, control method, and electricity distribution system
In a control device configured to control power to be supplied to a specific load from at least one of a converter that has a power generator and a storage battery, and a commercial power supply, the control device determines whether the commercial power supply is in a power failure state or a power distribution state, in which: when determining that the commercial power supply is in a power distribution state, the control device causes both of the converter and the commercial power supply to be connected to the specific load; and when determining that the commercial power supply has made a transition from a power distribution state to a power failure state, the control device causes the commercial power supply to be disconnected from the specific load while maintaining the connection between the converter and the specific load. |
| US09692252B2 |
Lock wireless charging system
A lock wireless charging system includes a gateway (10) and a door lock (20). The gateway (10) includes a first micro-processing unit (101), a first signal-fetching unit (102), a first charging unit (103), a first signal-processing unit (104) and a first antenna unit (105). The door lock (20) includes a second micro-processing unit (201), a second signal-fetching unit (202), a second charging unit (203), a second signal-processing unit (204), a second antenna unit (205) and a storage unit (206). The first antenna unit (105) outputs the identification and sensing signals. The door lock (20) fetches and transmits the identification signal to the second micro-processing unit (201) to determine. The second micro-processing unit (201) responds to the first micro-processing unit (101) with a responsive identification signal. If the identification is successful, the sensing signal is converted into electricity, so the second charging unit (203) charges the storage unit (206). |
| US09692250B2 |
Systems and methods for smart wireless charging
Systems and methods for power distribution allocation are provided. A system may establish a first wireless connection between the system and a first mobile device. The system may receive a first charge request from the first mobile device comprising first mobile device information, and may identify charging system policies based at least in part on the first charge request. The system may determine a first charge program for the first mobile device based at least in part on the first charge request and the one or more charging system policies, where the first charge program comprises a power allocation of the first mobile device with respect to other mobile devices connected to the charging system. The system may wirelessly charge the first mobile device, based at least in part on the first charge program. |
| US09692245B2 |
Battery management system and power connector
Example aspects of the present disclosure are directed to an improvement of an energy storage system. The energy storage system includes a power connector and a battery management system (BMS). The power connector includes a connector body having a first face and a second face which is disposed oppositely to the first face. A first terminal and a second terminal can be disposed on the first face. The first terminal and the second terminal can be configured to electrically couple the BMS to a positive conductor and a negative conductor to form a power connection, Moreover, a first current shunt can be disposed on the second face and electrically coupled to the first terminal, while the second current shunt can be disposed on the second face and electrically coupled to the second terminal. |
| US09692241B2 |
Method for improving call quality during battery charging and electronic device thereof
A method of operating an electronic device is provided. The method includes determining whether a specific event has occurred, when the specific event has occurred, determining whether a battery level is less than a set level, and when the battery level is less than the set level, changing a path of an electric current introduced from a power supply from a first path to a second path. |
| US09692238B2 |
Wireless power transmission system and power transmitting device
A power transmitting device includes a power transmitting circuit that converts second DC power input from a DC power supply to AC power, a power transmitting antenna and a control circuit that receives a voltage value of the first DC power from the power receiving device. The control circuit changes a frequency of the AC power that is transmitted to the power receiving antenna, detects, from the received voltage values, a first frequency corresponding to a local minimum value of the voltage values and a second frequency corresponding to the voltage value that takes a local maximum value at a frequency higher than the first frequency, and sets the frequency of the AC power transmitted to the power receiving antenna to a frequency between the first frequency and the second frequency. |
| US09692235B2 |
Managing continuity of the supply of power to electric equipment
The supply of an electric equipment material (5), such as a telecommunications station, is implemented in priority by an intermittent power source (6), and makes use as much as possible of batteries (31) and as little use as possible of a fuel cell electrochemical generating unit (4) for increasing the life of the latter. The equipment and the generating unit are supplied by the source so as to produce and stock fuel in the generating unit when the power of the source exceeds the operation power of the equipment and the batteries are in full charge. Destocking the fuel in the generating unit, supplying the equipment by the generating unit and charging the batteries by the generating unit are carried out as soon as the power of the batteries is at a discharge threshold and until the batteries reach the full charge. |
| US09692234B2 |
Systems and methods for distributing power using photovoltaic resources and a shifting battery system
The present invention is an apparatus and method for delivering energy using a renewable resource. The method includes providing a photovoltaic energy source and applying energy storage to the photovoltaic energy source via a battery storage unit. The energy output from the photovoltaic energy source and the battery system is controlled using a battery control system. The battery control system predicts peak load, develops a schedule that includes when to begin discharging power and when to stop discharging power, shifts power to the battery storage unit when excess power is available, and prioritizes the functionality of the battery storage unit and the photovoltaic energy source. |
| US09692233B2 |
Method for controlling an energy storage system
A method for controlling an energy storage system. The same battery system shall support multiple services at the same time. During a planning phase, the multiple services to be provided are determined, based on the market situation and the capabilities of the energy storage system, and prioritized according to predefined criteria. During an operation phase, the power and energy status of the energy storage system is periodically monitored, and compared against the power and energy demands of the multiple services, in order to determine whether at each time instance, the multiple services can indeed be supported at the same time. In case power and/or energy limits are exceeded by the multiple services, at least one service is interrupted to allow the operation of the energy storage system to be within power/energy limits again. The interrupted service(s) is resumed when the power/energy limits are met. |
| US09692230B2 |
Device with dual power sources
A wearable device includes a sensor, auxiliary electronics, a primary power supply configured to harvest radio frequency (RF) radiation received from an external reader and use the harvested RF radiation to power the sensor, and an auxiliary power supply configured to harvest energy other than that received from the external reader and use the harvested energy to supply power to the sensor and/or the auxiliary electronics. The external reader may supply less power in response to operation of the auxiliary power supply. Additionally or alternatively, in response to a determination that the auxiliary power supply is unable to supply power, the wearable device may disable all auxiliary electronics but for the sensor. In response to a determination that the primary power supply is unable to supply power but the auxiliary power supply is able to supply power, the wearable device may retain operating parameters in the memory storage unit using the auxiliary power supply. |
| US09692228B2 |
ESD protection control circuit and system
An electrostatic discharge (ESD) protection control circuit for an output pad of an integrated circuit includes an output driver and a control switch. The output driver, coupled to the output pad, includes a first output transistor for outputting power or signals to the output pad. The control switch, for improving ESD protection on the output pad when closed, includes a first connection terminal, coupled to a gate terminal of the first output transistor; a second connection terminal, coupled to a ground terminal; and a control terminal, coupled to a first power supply terminal. |
| US09692226B2 |
Circuit interruption device
An extinguishing branch (28) for an electrical circuit (32) includes: a snubber circuit (36) including an energy storage limb (40), wherein the energy storage limb (40) includes first and second energy storage limb portions separated by a first junction (46) to define a first voltage divider, and each energy storage limb portion includes at least one energy storage device (48,50); and an arrester limb (38) connected across the energy storage limb (40), wherein the arrester limb (38) includes first and second arrester limb portions separated by a second junction (52) to define a second voltage divider, and each arrester limb portion includes at least one arrester element (54,56), wherein the first and second junctions (46,52) are connected to define a voltage divider bridge, and the voltage divider bridge is electrically coupleable to the electrical circuit (32) so as to provide, in use, a driving voltage to drive the electrical circuit (32). |
| US09692225B2 |
Hybrid DC breaker
A hybrid DC breaker, comprises a main current circuit, a transfer current circuit, an over-voltage limiting circuit and a control system, wherein the main current circuit, the transfer current circuit and the over-voltage limiting circuit are connected in parallel. The transfer current circuit consists of circuits 1-4, wherein the circuit 1 and the circuit 4 are connected in series at first and then connected with the main current circuit in parallel; a pre-charged capacitor is connected with the circuit 4 in parallel after being connected with the circuit 3 in series; and, one end of the circuit 2 is connected with the left end of the main current circuit while the other end thereof is connected with a connection point of the pre-charged capacitor and the circuit 3. |
| US09692221B2 |
Junction box and contactor device
An electrical junction box includes a casing, a first installation space, a second installation space, and a connection part arranged in the casing the connection part includes a main body, a first connection end, and a second connection end. The main body is used for connecting to a cable; the first connection end, connected to the main body, is located in the first installation space, and is used for connecting to a contactor; and the second connection end, arranged on the first connection end, is located in the second installation space, and may be used for connecting to a resistance wire. The resistance wire may be connected to the second connection end without passing over the junction box, which is not only advantageous for fastening and installing the junction box, but also facilitates the connection and installation of the cable. |
| US09692211B2 |
Vertical cavity surface emitting laser array
A VCSEL array includes a base substrate, VCSEL element columns arranged in a row direction (y direction) on a front-surface side of the base substrate and parallel wiring lines that connect the VCSEL element columns in parallel with each other. Each of the VCSEL element columns includes a plurality of VCSEL elements arranged in a column direction (x direction) and a plurality of series wiring lines. The plurality of series wiring lines serially connect every two VCSEL elements that are adjacent to each other in the column direction among the plurality of VCSEL elements in such an orientation that the forward directions of the two VCSEL elements match. Insulating grooves are formed on the base substrate. The insulating grooves electrically insulate the VCSEL element columns from each other. The insulating grooves electrically insulate the VCSEL elements from each other. |
| US09692209B2 |
High-concentration active doping in semiconductors and semiconductor devices produced by such doping
In a method of forming a photonic device, a first silicon electrode is formed, and then a germanium active layer is formed on the first silicon electrode while including n-type dopant atoms in the germanium layer, during formation of the layer, to produce a background electrical dopant concentration that is greater than an intrinsic dopant concentration of germanium. A second silicon electrode is then formed on a surface of the germanium active layer. The formed germanium active layer is doped with additional dopant for supporting an electrically-pumped guided mode as a laser gain medium with an electrically-activated n-type electrical dopant concentration that is greater than the background dopant concentration to overcome electrical losses of the photonic device. |
| US09692200B2 |
Fiber laser
The present disclosure discloses a fiber laser, including a laser seed source, an amplifying optical path, an output optical isolator and an optical fiber cylinder; wherein, the amplifying optical path is connected to the laser seed source and the output optical isolator, the laser seed source is used to output optical source, the amplifying optical path includes a first stage amplifying optical path and a second stage amplifying optical path, the first stage amplifying optical path is connected to the laser seed source and the second stage amplifying optical path respectively, the output optical source is output via the output optical isolator after two-stage amplifying; the second stage amplifying optical path comprises a multi-mode active optical fiber; the multi-mode active optical fiber is coiled on the optical fiber cylinder. By the disposing way above, the present disclosure may improve output optical beam quality of the fiber laser. |
| US09692198B2 |
Method of manufacturing an electrically conductive extension/compression spring
An electrically conductive spring having first and second coils defining first and second electrical pathways for completing an electric circuit between two components which may move relative to each other. In one embodiment, the spring is a double start helical spring with first and second coils extending between respective, electrically insulated ends with the coils extending in alternating, spaced relation to each other. |
| US09692192B2 |
Multi connector, wiring method thereof and display apparatus having the same
Disclosed are a multi connector, a wiring method thereof and a display apparatus having the same that is configured to use a common interface (CI) module for data communication between an electronic apparatus and an external apparatus or a plug used for an electronic connection of elements, regardless of standard conditions such as the number of terminals. The multi connector includes a body portion including a first slot portion and a second slot portion; a substrate portion including a substrate having a first surface; a plurality of first connection terminals provided on the first surface and extending to an inside of the first slot portion; and a plurality of second connection terminals provided on the first surface and extending to an inside of the second slot portion. |
| US09692189B2 |
Safe socket and use thereof
A safety socket includes one or multiple socket bodies. A socket body has a live wire receptacle and a neutral wire receptacle, and includes a live wire connection circuit, a neutral wire connection circuit, and a locking and controlling mechanism. When the live wire pin and the neutral wire pin of a power plug are respectively inserted into the live wire receptacle and the neutral wire receptacle of the socket body, the locking and controlling mechanism is activated and is switched to the operating state so as to connect the live wire connection circuit and the neutral wire connection circuit. When the locking and controlling mechanism is in the idle state, the live wire connection circuit and the neutral wire connection circuit are disconnected. The safety socket can effectively prevent electric shock and is water-proof, thereby preventing electric shock accidents and ensuring the safe usage of the safety socket. |
| US09692188B2 |
Flexible electrical connector insert with conductive and non-conductive elastomers
A connector insert comprising conductive wire and a plurality of layers of conductive and non-conductive elastomers, and methods of fabrication thereof. |
| US09692187B2 |
Assembly of cable connection apparatus and electrical connector
An assembly of a cable connection apparatus and an electrical connector, includes a mating plug having an insulating body and multiple terminals, a circuit board having a notch depressed from an edge at a side of the circuit board toward a center direction of the circuit board and a metal conductor disposed in the notch or at an edge of the notch, and a cable having at least one conducting wire. The terminals are conducted to the circuit board. The conducting wire is inserted into the corresponding notch along a depression direction of the notch, and conducted to the metal conductor, thereby reducing the height of a soldering end of the conducting wire protruding from a surface of the circuit board. Thus, a metal casing outside the circuit board may wrap the circuit board without having a protruding portion for reserving the soldering end. |
| US09692186B2 |
High-speed electrical connector
A high-speed electrical connector employs a plurality of electrical contacts held together by a dielectric frame. The contacts are electrically coupled to a substrate within the connector. A gasket may be disposed between the dielectric frame and the substrate and configured to block the flow of an overmold material between the dielectric frame and the substrate such that voids are formed between the contacts. The dielectric frame and the overmold may be made from materials containing silica aerogel. The voids and the aerogel materials result in reduced parasitic capacitance between the contacts enabling higher data transfer speeds. |
| US09692185B2 |
Shielded connector
The present invention provides a shielded connector that can reduce the entire size thereof while preventing an increase in the number of components. A shielding shell includes a shell body provided to an outer side of a housing, and a thermally conductive holding member that supports an insulating container portion of a fuse, so the heat generated by the fuse is dissipated to outside, thereby reducing the space between the housing and the fuse and reducing the entire size of the shielded connector. Also, the shielding shell functions as both a heat dissipation member and a magnetic shield, thus, an increase in the number of components can be prevented. |
| US09692184B2 |
Electronic device
An electronic device includes the memory card connector including a loading opening for the memory card in the side face thereof and has a first sidewall and a second sidewall facing each other, the printed wire board on which a ground is formed, and a resin case having an opening portion, through which the memory card is inserted and formed in the sidewall of the loading opening. On the second main face of the printed wire board, there are formed a first electrode and a second electrode that are connected with the ground, that are disposed on the respective ends thereof at the loading opening side, and that are independent from each other, and the first electrode is disposed below the first sidewall of the memory card connector and the second electrode is disposed below the second sidewall of the memory card connector. |
| US09692183B2 |
Receptacle connector with ground bus
A receptacle connector includes a housing having a slot configured to receive a mating connector therein. Signal contacts are held by the housing. The signal contacts include signal mating segments and signal mounting segments. The signal mating segments include signal mating interfaces that are exposed within the slot for engagement with the mating connector. Ground contacts are held by the housing. The ground contacts include ground mating segments and ground mounting segments. The ground mating segments include ground mating interfaces that are exposed within the slot for engagement with the mating connector. A ground bus electrically commons the ground contacts with each other. The ground contacts and the ground bus are integrally fabricated as a single, unitary, continuous structure. |
| US09692180B2 |
Electrical connectors and printed circuits having broadside-coupling regions
An electrical connector that includes a circuit board having a board substrate that has opposite board surfaces and a thickness measured along an orientation axis that extends between the opposite board surfaces. The circuit board has associated pairs of input and output terminals and signal traces that electrically connect the associated pairs of input and output terminals. The input and output terminals being configured to communicatively coupled to mating and cable conductors, respectively. Each associated pair of input and output terminals is electrically connected through a corresponding signal trace that has a conductive path extending along the board substrate between the corresponding input and output terminals. At least two signal traces form a broadside-coupling region in which the conductive paths of the at least two signal traces are stacked along the orientation axis and spaced apart through the thickness and extend parallel to each other for a crosstalk-reducing distance. |
| US09692174B1 |
Circular rapid joint connector
A circular rapid-joint connector, which includes a sliding bush with multiple extension sections and recession areas provided on an end thereof; an elastic element provided on the inner edge of the sliding bush; a holding unit joined with the sliding bush movably, the outer edge thereof having a limiting unit capable of limiting each of the extension sections; and a connector plug penetrating into the sliding bush and joined with the holding unit. In assembling, direct docking with a connection socket by the connector plug is available for the connection socket to push away the sliding bush. After the connection socket and the connector plug are snap-fitting, the sliding bush is pushed back by the elastic element automatically, such that the sliding bush is locked in the outer edge of the connection socket to complete the operation of assemblage. |
| US09692173B2 |
Feedthrough wire connector for use in a medical device
A feedthrough filter capacitor assembly comprising a terminal pin connector is described. The terminal pin connector is designed to facilitate an electrical connection between the terminal pin comprising a multitude of compositions to a circuit board of an implantable medical device. The terminal pin connector comprises a clip portion positioned within a connector housing. The connector clip mechanically attaches to the terminal pin of the feedthrough with at least one prong and an exterior surface of the connector housing electrically contacts the circuit board, creating an electrical connection therebetween. The connector housing comprises a material that is conducive to a weld or solder attachment process to the circuit board. The feedthrough filter capacitor assembly is particularly useful for incorporation into implantable medical devices such as cardiac pacemakers, cardioverter defibrillators, and the like, to decouple and shield internal electronic components of the medical device from undesirable electromagnetic interference (EMI) signals. |
| US09692169B2 |
Connection system between an electrical or electronic device and a plug connector unit and use of the connection system
A connection system between an electrical or electronic device and a plug connector unit, the device including first electrical terminals, which are aligned in parallel to one another with the aid of a first positioning device within a connection area of the device, and second electrical terminals, which cooperate with the first electrical terminals, being aligned with the first electrical terminals with the aid of a second positioning device in a plug connector housing of the plug connector unit. |
| US09692168B1 |
Header assembly
A header assembly includes a dielectric housing, an electrically conductive outer contact, and a center contact. The housing has a front panel that defines a contact opening therethrough between a front side and a rear side of the front panel. The housing also includes a base panel extending from the rear side of the front panel. The base panel mounts to a circuit board. The outer contact includes a mating segment that extends through the contact opening of the housing and defines a channel that receives the center contact therein. The outer contact also includes a mounting segment that engages the base panel of the housing and is disposed between the base panel and the circuit board. The mounting segment couples and electrically terminates to the circuit board. |
| US09692166B2 |
Electrical receptacle connector and electrical plug connector
An electrical receptacle connector is disclosed. The electrical receptacle connector includes a plurality of upper-row receptacle terminals and lower-row receptacle terminals. The plurality of upper-row receptacle terminals and lower-row receptacle terminals have 180 degree symmetrical, dual or double orientation design which enable the electrical plug connector to be inserted into the electrical receptacle connector in either of two intuitive orientations. Each of the receptacle terminals includes a flat contact portion, a soldering portion and a connecting portion. The flat contact portion is extended from one end of the connecting portion, and the soldering portion is extended from the other end of the connecting portion. The width of the connecting portion is different from the width of the flat contact portion. |
| US09692154B2 |
Safe jumper methodology utilizing switch embedded connection clamps
A clamp includes a first and second handle parts that are pivotable relative to each other and biased closed. A first electrical contactor is associated with the first handle part, and a second electrical contactor is associated with the second handle part. The first electrical contactor and the second electrical contactor are positioned such that in the closed position of the clamp, a circuit connection between the first electrical contactor and the second electrical contactor is open, and in the open position, the circuit connection is closed. |
| US09692152B2 |
Wall plate connector system
A wall plate connector system includes a wall plate terminal block extending from a wall plate base. The wall plate terminal block includes a terminal block body having a front, a rear, a first end and a second end. The terminal block body has contact channels and wire channels open to corresponding contact channels to receive electrical wires during a poke-in termination. Terminal contacts are received in corresponding contact channels and each include a poke-in spring beam and a header beam. A header assembly is removably coupled to the wall plate terminal block and includes header contacts configured to be terminated to a control circuit board. Each header contact has a mating beam. At least one of the mating beam and the header beam is a resiliently deflected spring beam configured for repeated mating and unmating at separable mating interfaces. |
| US09692150B2 |
Tool-less coaxial cable connector
A coaxial cable connector includes a cylindrical body having a longitudinal axis, a front end, an opposed rear end, an interior, and an inner surface bounding the interior. A cylindrical inner post extends through the cylindrical body, supports the cylindrical body, and has an outer surface. A coupling nut is carried on the inner post at the front end of the cylindrical body. A first thread is formed on the inner surface of the body and has a ramped entrance directed toward the rear end of the body and a blunt end directed toward the front end of the body. A second thread is formed on the outer surface of the inner post and has a ramped entrance directed toward the rear end of the body, a blunt end directed toward the front end of the body, and a plurality of stops therebetween. |
| US09692149B2 |
Coaxial connector and connecting section
A coaxial connector includes a housing, and a bushing which is attached to the housing and on which the leading end of the coaxial cable is placed. In the coaxial connector, the housing includes a first circular cylinder and a crimping portion holding the bushing, the bushing is press-contacted to an insulation film by a force from the crimping portion, a socket includes a contact portion enclosed by the first circular cylinder and an attachment portion that is press-contacted to the insulation film by a force from the bushing and is connected to a second central conductor through cutting and removing part of the insulation film, and a minimum length from the center of the first circular cylinder to the crimping portion is longer than a maximum length from the center of the outer conductor to an outer edge of the receptacle. |
| US09692148B2 |
Connection terminal
A connection terminal includes: an electric wire connection part; a terminal connection part formed in a flat-plate shape; an insertion hole provided in the terminal connection part and connected to a mated member by insertion of a bolt; an erect wall located around the insertion hole and provided integrally with and protrusively from the terminal connection part; and a fracture part provided at the terminal connection part between the erect wall and the insertion hole and configured to separate a part of the terminal connection part from the mated member by a pull force in a state where the bolt is inserted. The fracture part includes: a first slit provided so as to be partially curved along the insertion hole between the erect wall and the insertion hole; and a second slit provided so as to continue to the first slit and to reach the erect wall. |
| US09692146B2 |
Contact element
A contact element for connecting to a cable having a braided shield includes a spring contact sleeve and a crimp sleeve. The spring contact sleeve has an annular ring and spring contacts arranged circumferentially on one end of the annular ring. The spring contact sleeve and the crimp sleeve form an enclosed hollow cavity between one another when the crimp sleeve is joined to the annular ring. The hollow cavity is configured to fully receive therein an exposed portion of the braided shield provided for connection of the contact element to the cable. |
| US09692145B2 |
Mechanical lug with dovetail interlock feature
The present invention is directed to a mechanical lug with interlocking features that secures an electrical conductor. The mechanical lug has a main body and a mounting tongue extending from the main body. The main body includes an inner flange and an outer flange. The inner flange has a horizontal member and an interlocking member with angled pockets. The outer flange has hooks with a tapered face positioned in the angled pockets of the interlocking member of the inner flange thereby forming a dovetail interlock. |
| US09692144B1 |
Electric connector
An electric connector (10) includes a first connector seat (1) and a second connector seat (2). The first connector seat (1) has plural cable clamps (11), and each cable clamp (11) includes a pair of U-shaped rods (12). Each pair of U-shaped rods (12) has a pocket (121), two inner sides (122), and two outer sides (123). The two inner sides (122) have plural cable fixing slots (124), and the cable fixing slots (124) have a slot width (h) tapered towards the first connector seat (1). The second connector seat (2) has plural pins (21), and each pin (21) is passed and coupled to each pocket (121). |
| US09692141B2 |
Antenna array of inverted-L elements optionally for use as a base station antenna
An antenna for receiving and/or transmitting electromagnetic radiation, e.g. circularly polarized waves. The antenna is built of three parts. A radiating element in the form of a sequentially rotated array of 4 dual inverted-L shaped surfaces, where each individual radiating element is fed with the same magnitude and a 90° sequential phase difference for the purpose of creating right or left hand circular polarization. A ground plane. And optionally, a structure that resembles a dual so-called choke ring structure on which the array is mounted. This structure improves the axial ratio and radiating pattern of the radiating elements and also serves as housing/shielding of the accompanying electronics like low noise amplifiers and power conditioning. |
| US09692138B2 |
Antenna device
A substrate includes a dielectric plate and a conductive layer formed on both surfaces of the dielectric plate, and a first cutout is formed in the conductive layer on both surfaces of the substrate so as to extend inward from part of a first edge of the substrate. A first radiation electrode is connected to the conductive layer at a first point located on an outer peripheral line of the first cutout. A first reflector plate is disposed in a location further inward in the substrate from the first edge than the first point. The reflector plate is electrically connected to the conductive layer, and faces toward the first point. Thus an antenna device that is suited to miniaturization and that is capable of increasing directivity is provided. |
| US09692137B2 |
Annular slot antenna
An annular slot antenna includes an inner conductor divided by a dielectric gap into a rear section and a front section. An inner conductor of a coaxial feed line is contacted with the front section of the inner conductor and the outer conductor of the coaxial feed line is contacted with the rear section. |
| US09692135B1 |
Direct transition from a waveguide to a buried chip
An assembly for confining electromagnetic radiation in a waveguide. The assembly comprises a waveguide, comprising walls surrounding a cavity and an aperture in the walls that opens to the cavity, and a substrate assembly disposed in the aperture. The substrate assembly comprises a substrate comprising an antenna, wherein the antenna is located within the cavity and is configured for transmission of radiation within the cavity. The substrate assembly comprises an integrated circuit (IC) electrically connected to the substrate, where the IC comprises semi-conductor components and a ground plane on one side of the IC. The ground plane is located between the IC semi-conductor components and the antenna. The ground plane is located across the aperture to reduce the area of the aperture and to reflect some of the radiation directed to the aperture back into the cavity. |
| US09692134B2 |
Broadband dual polarization omni-directional antenna with dual conductive antenna bodies and associated methods
An antenna includes first and second conductive antenna bodies. The first conductive antenna body has first and second opposing ends with an enlarged width medial portion therebetween, a first slot extending from at least adjacent the first end to at least adjacent the second end, and first antenna feed points adjacent the first slot for a first polarization. The second conductive antenna body has first and second opposing ends with an enlarged width medial portion therebetween, a second slot extending from at least adjacent the first end to at least adjacent the second end, and second antenna feed points adjacent the second slot for the first polarization. The first end of the second conductive antenna body is adjacent the second end of the first conductive antenna body. Third antenna feed points are between the first and second conductive antenna bodies for a second polarization. |
| US09692132B2 |
Antenna apparatus having patch antenna
An antenna apparatus includes a dielectric substrate, a ground plate, a patch antenna provided with a patch radiating element, and a plurality of EBGs (Electromagnetic Band Gaps). The EBGs are composed of patch-shaped patterns formed on a surface of the substrate and connecting conductors electrically connecting the patch-shaped patterns and the ground plate. Each EBG is arranged to provide an EBG absent region having no EBG on the surface of the substrate. The patch radiating element is arranged within the EBG absent region. The EBG absent region is formed such that distances (absent distances) in a dominant polarized wave direction changes into a plurality of types depending on the position on a vertical patch line, where the distances range, to the boundary of the region, from an arbitrary position on the virtual patch line which is perpendicular to the dominant polarized wave direction of the patch antenna. |
| US09692131B2 |
Antenna and the manufacturing method thereof
A method of manufacturing an antenna is provided. The method includes steps of providing a substrate including a feed-in terminal and a ground terminal; and forming a ground conductor structure on the substrate extended from the feed-in terminal to the ground terminal and including a first conductor extended along a first direction, a second conductor extended from the first conductor along a second direction, a third conductor extended from the second conductor along a third direction, and a fourth conductor extended from the third conductor along a fourth direction, wherein a first obtuse angle is formed between the first direction and the second direction, a second obtuse angle is formed between the second direction and the third direction, and an acute angle is formed between the third direction and the fourth direction. |
| US09692129B2 |
Planar antenna for RFID reader and RFID PDA incorporating the same
A planar antenna comprising: a substrate (10) having opposed first (10A) and second (10B) flat faces; the first flat face comprising a first ground (12), a second ground (14), a feed track (16) there between and an antenna pattern (18) and the opposed second flat face comprising a third ground (20); the third ground being connected to first and second grounds for assuring the continuity of the ground plane with the feeding; and the antenna pattern forms a coil line disposed into the remaining surface of the first flat face and comprises two overlapped loops in such a way that the antenna pattern is substantially auto-complementary. |
| US09692128B2 |
Antenna device and wireless communication device
An antenna device includes a first coil antenna and a second coil antenna. The first coil antenna includes a coil conductor having a rectangular or substantially rectangular spiral shape and located on a non-magnetic insulating base member. The second coil antenna includes two coil conductors located on a non-magnetic insulating base member. The two coil conductors are disposed and wound such that loops of a magnetic field that is generated by applying a current to the two coil conductors are perpendicular or substantially perpendicular to a coil axis of the coil conductors. |
| US09692127B2 |
Antenna device and antenna system
An antenna device includes: a ground plate; a first patch, provided on one surface side of the ground plate and including two first power feeding portions provided in a region surrounded by a first contour at positions spaced away from a first position with a first distance, configured to resonate with a first frequency; a second patch, provided between the ground plate and the first patch and including two second power feeding portions provided in a region surrounded by a second contour at positions spaced away from a second position with a second distance and a slit formed in the region, configured to resonate with a second frequency lower than the first frequency; and an inter-patch connection portion configured to electrically couple the first position of the first patch and the second position of the second patch. |
| US09692124B2 |
Antenna structures and methods thereof that have disparate operating frequency ranges
A system that incorporates the subject disclosure may include, for example, a circuit for receiving a request to initiate a first multiple-input and multiple-output (MIMO) communication session and a second MIMO communication session, and configuring a first antenna configuration and a second antenna configuration to enable the first MIMO communication session and the second MIMO communication session. The first MIMO communication session shares spectrum from the first antenna configuration and the second antenna configuration, and the second MIMO communication session utilizes spectrum from the second antenna configuration that differs from the shared spectrum. Other embodiments are disclosed. |
| US09692123B2 |
Systems and methods of controlling antenna radiation patterns
In a particular embodiment, a method of controlling a radiation pattern includes selecting a signal processing characteristic to vary based on a radiation pattern to be emitted by an antenna array of a wireless device, wherein the antenna array includes a plurality of antennas, wherein the signal processing characteristic provides a target resultant radiation pattern, and wherein the signal processing characteristic is applies to less than all elements of the antenna array, and varying the signal processing characteristic across time, frequency, or a combination thereof. |
| US09692113B2 |
Antenna on sapphire structure
An antenna on a sapphire structure. The antenna includes a sapphire structure having a first side, and a second side positioned opposite the first side. The antenna also includes a first antenna trace positioned on the first side of the sapphire structure, and a second antenna trace positioned on the second side of the sapphire structure. Additionally, the antenna includes at least one via formed through the sapphire structure. The at least one via electrically connects the first antenna trace to the second antenna trace. |
| US09692109B1 |
Mount for co-locating an access point and an antenna
A mount for an antenna for an access point includes a base for attachment to a mounting structure; a tray operably attached to the base. The tray is pivotable about an axis of rotation. The tray is for attaching thereto an antenna. The tray is angularly positionable about the axis for positioning the antenna at a desired direction. The base is U-shaped including a base portion and first and second portions extending from the base portion. The tray is U-shaped including a base wall and first and second portions extending from the base wall. The first and second portions of the base are operably attached to said first and second portions of the tray. |
| US09692104B2 |
Communication device, communication method, and a computer-readable recording medium
A transmission system that can continue communication even if a tracking error exists and to reduce interference on other transponders when transmitting a video and audio between an endstation facility and another endstation facility via a transponder mounted on communications satellite. This transmission system includes a tracking antenna that tracks a transponder, a tracking error calculation circuit that obtains a tracking error in a tracking operation of the tracking antenna, a transmission level control circuit that obtains a transmission level of a signal in response to the tracking error, and a transmitter that transmits the signal at the obtained signal level via the tracking antenna to the transponder of the communication target. |
| US09692096B2 |
Partially-submerged battery cells for vehicle energy-storage systems
Provided are cooling subsystems for energy-storage systems comprising: a coolant section having a coolant circulated therein; a non-coolant section having a fluid other than the coolant disposed therein; a plurality of battery cells having a coated portion and a non-coated portion, the coated portion being disposed in the coolant section, and the non-coated portion being disposed in the non-coolant section. Some embodiments may also comprise a retainer disposed between the coolant section and the non-coolant section, the retainer holding the plurality of battery cells, the retainer forming a seal around the plurality of battery cells, the seal preventing the flow of coolant from the coolant section to the non-coolant section. |
| US09692095B2 |
Fully-submerged battery cells for vehicle energy-storage systems
Provided are cooling subsystems for energy-storage systems comprising: a coolant section having a coolant circulated therein; a plurality of battery cells having a coated portion, the coated portion being disposed in the coolant section, the coolant section configured so that the plurality of battery cells are substantially fully covered by the coolant; and a retainer disposed in the coolant section, the retainer holding the plurality of battery cells, the retainer having a plurality of flow channels, the coolant flowing through the flow channels. |
| US09692094B2 |
Heat sink having two or more separated channels arranged vertically with common inlet and common outlet
The present disclosure discloses a heat sink with two or more separated channels. The heat sink according to the present disclosure includes a cooling channel through which a refrigerant passes to cool a secondary battery by an indirect cooling method, the secondary battery including a cell assembly in which at least two unit cells are stacked, each unit cell including a positive electrode plate, a separator, and a negative electrode plate, and a plurality of positive and negative electrode tabs protruding from the positive and negative electrode plates of each unit cell is electrically connected to positive and negative leads, respectively, wherein the cooling channel has two or more separated channels, the two or more separated channels have branches inside to allow a coolant to flow in each of the channels, and the branches are vertically arranged. According to the present disclosure, provision of a heat sink having a uniform cooling effect is enabled. |
| US09692093B2 |
Reduced order battery thermal dynamics modeling for controls
A vehicle includes a traction battery that is comprised of a number of cells. A controller operates the traction battery according to a temperature for each of the cells. The temperature is based on a number of coefficients representing a contribution of at least one cell boundary thermal condition and a heat generated in the cell to a steady-state temperature at a predetermined location within the cell. The contributions may be filtered to predict a dynamic response of the temperature to changes in the boundary thermal conditions and the heat generated in the cell. The coefficients may be derived from a full-order model. The resulting reduced-order model requires less execution time while achieving accuracy similar to the full-order model. In addition, a range of characteristic temperatures may be obtained for each cell. |
| US09692092B2 |
Battery pack for a motor vehicle
A battery pack includes a battery module having a set of battery cells and at least one cooling device. Each cooling device includes a heat collecting plate, a heat duct, and a heat dissipating element. The heat collecting plate is in contact with an outer surface of at least one battery cell of the set of battery cells. The heat duct is in contact with the heat collecting plate. The heat dissipating element has a circular orifice in which the heat duct is positioned. The heat duct contains a fluid. A connection between the heat dissipating element and the heat duct is established by tinning. A method for producing the battery pack is provided. |
| US09692088B2 |
Method for restoring battery capacity, method for restoring battery pack capacity, device for restoring battery capacity, and device for restoring battery pack capacity
This method for restoring battery capacity is provided with an oxygen-generating/exhausting step for charging a nickel-metal-hydride storage battery, causing the generation of oxygen gas in a positive electrode, opening a safety valve device, and discharging at least a portion of the oxygen gas through the safety valve device to the outside of the battery. The battery temperature when starting the step is in the range of −30 to 10° C. and the SOC is in the range of (30-Ta) to 100%, or the battery temperature (Ta) is in the range of 10 to 50° C. and the SOC is in the range of 20-100%. |
| US09692087B2 |
Ohmically modulated battery
A rechargeable battery whose ohmic resistance is modulated according to temperature is disclosed. |
| US09692085B2 |
Lithium ion secondary battery
It is an object of this exemplary embodiment to provide a lithium ion secondary battery using a positive electrode active material having an operating potential of 4.5 V or more, the lithium ion secondary battery having excellent high temperature cycle characteristics. This exemplary embodiment is a lithium ion secondary battery comprising a positive electrode and a negative electrode capable of intercalating and deintercalating lithium, a separator between the positive electrode and the negative electrode, and an electrolytic solution containing a nonaqueous electrolytic solvent, wherein the positive electrode comprises a positive electrode active material operating at a potential of 4.5 V or more versus lithium, the separator comprises cellulose, a cellulose derivative, or a glass fiber, and the nonaqueous electrolytic solvent comprises a fluorinated solvent. |
| US09692083B2 |
Lithium-ion battery having organic-inorganic hybrid solid electrolyte
Methods are described for forming insulating hybrid organic-inorganic solid electrolytes on conducting electrodes that are active materials in Li-ion batteries by electrochemical deposition, and for forming second conducting electrodes on the solid electrolytes using aqueous slurries, whereby Li-ion battery cells having solid electrolytes are generated. X-ray photoelectron spectroscopy is utilized for determining that the solid electrolytes are defect and pinhole free. |
| US09692080B2 |
Head plate
The invention relates to a head plate, fixing the end of a tube bundle with a number of, in particular, porous tubes with a membrane in sealing manner. The head plate is made from a metal or a metal alloy with a melting point lower than the lowest failure temperature for a tube material and/or the membrane. |
| US09692079B2 |
Laminated plate repeating fuel cell unit for an SOFC stack
An improved SOFC repeating fuel cell unit comprising three flat plates and a cell retainer. The three flat plates are metallurgically joined (brazed or laser welded) into a subassembly to which is added the fuel cell and cell retainer (which may also be joined as a second subassembly). Each flat plate performs a specific set of functions and can be optimized for those functions. Since the plates are flat and designed to overlap in loaded areas, the fuel cell unit is not prone to dimensional collapse which eliminates the internal reinforcements of the prior art design. The cell retainer is formed to provide a self-locating and locking feature for the fuel cell and decouples thermal stresses from the thin ceramic fuel cell. |
| US09692078B2 |
High-performance rechargeable batteries with fast solid-state ion conductors
A high-performance rechargeable battery using ultra-fast ion conductors. In one embodiment the rechargeable battery apparatus includes an enclosure, a first electrode operatively connected to the enclosure, a second electrode operatively connected to the enclosure, a nanomaterial in the enclosure, and a heat transfer unit. |
| US09692077B2 |
Aqueous redox flow batteries comprising matched ionomer membranes
This invention is directed to aqueous redox flow batteries comprising ionically charged redox active materials and ionomer membranes, wherein the charge of the redox active materials is of the same sign as that of the ionomer, so as to confer specific improvements. |
| US09692076B2 |
Electrolyte composition for solid oxide fuel cell, and solid oxide fuel cell
The invention provides an electrolyte composition for solid oxide fuel cells, and a solid oxide fuel cell. The electrolyte composition has high electrical conductivity over a wide temperature range and is capable of imparting excellent output characteristics to a solid oxide fuel cell. Specifically, the invention provides a scandium oxide-stabilized zirconium oxide-based electrolyte composition used in a solid oxide fuel cell. The composition contains a compound represented by chemical formula (1): (ZrO2)1-x-a(Sc2O3)x(M2O3)a (1), wherein 0.09≦x≦0.11 and 0 |
| US09692072B2 |
Anion exchange electrolyte membrane, membrane-electrode assembly for fuel cell including the same, and fuel cell including the same
Disclosed is an anion exchange electrolyte membrane including: a base polymer having a polar group; and a graft chain having a specific structural unit. The graft chain is, for example, a polymer chain that is formed from diallyldimethylammonium chloride as a monomer. |
| US09692067B2 |
BOP system of solid oxide fuel cell, solid oxide fuel cell stack module, and method for operating the solid oxide fuel cell
The present invention relates to a balance of plant (BOP) system of solid oxide fuel cells including a burner, a reformer, a steam generator, and heat exchangers, wherein the burner, the reformer and the steam generator are laid sequentially on top of each other to transmit the flames and burned gas generated from the burner directly to the reformer and the steam generator disposed sequentially on top of the burner, and the heat exchangers introduce the flue gas discharged from the steam generator thereinto and preheat the process air to be supplied to cathodes of stacks. |
| US09692064B2 |
Fuel cell system
A fuel cell system according to the present invention comprises a fuel gas supply system that supplies a fuel gas from a fuel supply source to a fuel cell that includes a stack including a plurality of cells, and a fuel off-gas circulation system that resupplies fuel off-gas to the stack. The fuel off-gas circulation system includes: a mixed fuel gas flow path formed such that a mixed fuel gas containing the fuel off-gas and the fuel gas flows in a direction along an inner surface of a manifold installed in the stack; and a point of merger where the fuel off-gas and the fuel gas merge with each other to produce the mixed fuel gas, the point of merger being arranged on one surface side of the manifold. With such configuration, the heat exchange efficiency of the fuel off-gas and the fuel gas can be increased, and ice resulting from water in the fuel off-gas can be prevented from flowing into the fuel cell stack. |
| US09692060B2 |
Particulate carbon catalyst including nitrogen and metal and method for producing the same
A particulate carbon catalyst in which particles having a particle diameter of 20 nm-1 μm account for a volume fraction of at least 45%, and the content of nitrogen atoms is 0.1-10 atomic % relative to the amount of carbon atoms. |
| US09692059B2 |
Manufacturing method of metal catalyst-supporting carrier, metal catalyst-supporting carrier, manufacturing method of fuel cell and catalyst supporting device
There is provided a technique that suppresses a variation in particle diameter of a metal catalyst in the process of supporting the metal catalyst on a carrier. A CNT substrate having carbon nanotubes (CNTs) as the carrier arrayed thereon is placed in a processing chamber. Carbon dioxide is supplied to the processing chamber. After the carbon dioxide in the processing chamber is made supercritical, a complex solution in which a platinum complex is dissolved is supplied to the processing chamber. A sample temperature denoting temperature of the CNTs is controlled to be higher than an ambient temperature in the processing chamber. The CNT substrate is heated, such that a temperature difference between the ambient temperature and the sample temperature repeats increasing and decreasing. After the state of the supercritical fluid is changed to a non-supercritical state, the CNT substrate is heated, so as to cause the metal catalyst to deposit on the surface of the CNTs. |
| US09692058B2 |
Electrode for fuel cell and production method of electrode for fuel cell, membrane electrode assembly and fuel cell
This electrode for fuel cell comprises: carbon nanotubes; a catalyst for fuel cell supported on the carbon nanotubes; and an ionomer provided to coat the carbon nanotubes and the catalyst for fuel cell, wherein when a length of the carbon nanotubes is represented by La [μm] and an inter-core pitch of the carbon nanotubes is represented by Pa [nm], the length La and the inter-core pitch Pa satisfy two expressions given below: 30≦La≦240; and 0.351×La+75≦Pa≦250. |
| US09692056B1 |
Dual current collectors for battery electrodes
Batteries having improved current collection are provided. In some implementations, an electrode structure of a battery may include an active material and two or more current collectors in electrical communication with the active material. In some implementations, an electrode structure of a battery may include two or more current collector layers. According to various implementations, the electrode structure may or may not include a current collector substrate. In some implementations, a battery anode includes a current collector substrate in electronic contact with nanostructured active material. In order to ensure that electronic communication between the active material and the current collector substrate is maintained throughout the life of the battery, a second electronically conductive path is provided in the form of a current collector layer over the nanostructured active material. The additional layer is thin and electronically conductive, and does not interfere adversely with battery operation. |
| US09692055B2 |
Battery cell having a coated electrode and the production thereof
A battery cell (10) having a positive electrode (3) and a negative electrode (1), wherein the, in particular, negative electrode (1) comprises a coating (5) containing a polymer which contains catechol groups and the coating (5) is a dry coating, is described. |
| US09692047B2 |
Positive electrode active material for non-aqueous electrolyte secondary battery and non-aqueous electrolyte secondary battery
A positive electrode active material for a non-aqueous electrolyte secondary battery according to an example of an embodiment of the present disclosure includes a lithium composite oxide as a main component. The ratio of a number of moles of Ni in the lithium composite oxide to a total number of moles of metal elements in the lithium composite oxide other than Li is larger than 30 mol %. The lithium composite oxide includes particles each including aggregated primary particles having a volumetric average particle size of 0.5 μm or more and at least one element selected from W, Mo, Nb, and Ta is dissolved in the lithium composite oxide. |
| US09692046B1 |
Electrode material for lithium-ion secondary battery
An electrode material for a lithium-ion secondary battery of the present invention includes particles which are made of LiFexMn1-w-x-y-zMgyCazAwPO4 (here, A represents at least one element selected from the group consisting of Co, Ni, Zn, Al, and Ga, 0.05≦x≦0.35, 0.01≦y≦0.08, 0.0001≦z≦0.001, and 0≦w≦0.02) and have an orthorhombic crystal structure, a 0.1 CA capacity during constant-current charge in a range of 4.0 V to 4.3 V is 100 mAh/g or more, and a ratio (1 CA/0.1 CA) of a 1 CA capacity to the 0.1 CA capacity during the constant-current charge in the range of 4.0 V to 4.3 V is 0.60 or more. |
| US09692041B2 |
Lithium battery and method of preparing cathode active material for the lithium battery
A lithium battery and a method of preparing the lithium battery, wherein the lithium battery includes: a cathode layer including a cathode active material including a core, and an ion conductive phosphate coating layer on a surface of the core; an anode layer; and a solid electrolyte layer that is disposed between the cathode layer and the anode layer, wherein the solid electrolyte layer includes a sulfide solid electrolyte. |
| US09692040B2 |
Electrode coated with a film obtained from an aqueous solution comprising a water-soluble binder, production method thereof and uses of same
A method of preparing an electrochemical electrode which is partially or totally covered with a film that is obtained by spreading an aqueous solution comprising a water-soluble binder over the electrode and subsequently drying same. The production cost of the electrodes thus obtained is reduced and the surface porosity thereof is associated with desirable resistance values. |
| US09692039B2 |
Nanostructured materials for electrochemical conversion reactions
The disclosure is related to battery systems. More specifically, embodiments of the disclosure provide a nanostructured conversion material for use as the active material in battery cathodes. In an implementation, a nanostructured conversion material is a glassy material and includes a metal material, one or more oxidizing species, and a reducing cation species mixed at a scale of less than 1 nm. The glassy conversion material is substantially homogeneous within a volume of 1000 nm3. |
| US09692036B2 |
Destructive battery closure
An article including: a battery support containing battery lead wires attached to terminals; an opposing battery support attached to the battery support to create a battery closure; one or more batteries having battery contacts in the opposing battery support; and one or more activation tabs; wherein the terminals are attached to spring-loaded members; wherein the one or more activation tabs are spaced between the terminals and the battery contacts; wherein the spring-loaded members provide a biasing force that biases the terminals against the activation tabs keeping the one or more activation tabs in place in either a first position or a second position of the opposing battery support; wherein the opposing battery support is securely connected to the battery support in both the first position and the second position; and wherein the biasing force is greater in the second position than in the first position. |
| US09692033B2 |
Manufacturing method of sealed battery
The invention provides a manufacturing method of a sealed battery that includes a power generating element, a housing member, a lid member, a collector terminal member, and a first insulating member. This manufacturing method includes compressing the first insulating member with a protruding portion of the lid member. The method includes measuring a position of the lid member and a compression load applied by the lid member, and stopping compressing when a slope of the change in the compression load with respect to the position of the lid member reaches a predetermined value. |
| US09692032B2 |
Rechargeable battery
A thin film is used in a metallic collector in order to increase the volume energy density. However, the strength of the thin film is low, so when a negative plate or a positive plate is directly joined to a terminal base portion, even an insignificant load might cause damage, such as cutting of the metallic collector. Even in a structure where the metallic collector is joined to a highly-conductive plate-like metal or a highly-conductive plate-like resin, and where the collecting plate is joined to a terminal base portion, the connection between the collecting plate and the terminal base portion affects the battery properties. The present invention provides a rechargeable battery including an electrode group in which a metallic collector having a negative active material layer formed on a surface, a separator retaining an electrolyte, and another metallic collector having a positive active material layer formed on a surface are alternately disposed in a layered manner into a strip shape such that the separator is interposed between the two kinds of metallic collectors, and electrode plate tabs formed at ends of the two kinds of metallic collectors are joined to each of metallic collecting plates by a predetermined number, and the metallic collecting plates are joined together with pressing plates, by fitting between a bolt and a nuts, to a terminal base portion having a through-hole for the bolt. |
| US09692031B2 |
Bus bar assembly for electrified vehicle batteries
A bus bar assembly according to an exemplary aspect of the present disclosure includes, among other things, a plurality of battery cells and a bus bar assembly that electrically connects the plurality of battery cells. The bus bar assembly includes a flexible cable, a voltage sense lead connected to the flexible cable, and a bus bar connected to the voltage sense lead. |
| US09692029B2 |
Connecting piece for connecting poles of two batteries or battery cells and production method for a connecting piece for connecting poles of two batteries or battery cells
A connecting piece includes a stamped metal sheet for conductively connecting poles of two batteries or battery cells, which connecting piece has a main body with a recess, wherein at least one insert element is arranged in the inner region of at least one recess. Either the insert elements have a groove on the circumferential face thereof, said groove running at least in regions of the circumference, or the main body has a groove on the inner face of the at least one recess therein, said groove running at least in regions of the circumference. The respectively corresponding component has a projection which is generated by material displacement when the two or one of the two components are/is pressed and which engages in the groove in an interlocking manner, so that the main body and each insert element are connected to one another, in an interlocking manner at least in regions, along the circumference of the insert element. |
| US09692021B2 |
Electrical storage device with improved sealing property
An electrical storage device includes a case, an electrode assembly accommodated in the case, an electrode terminal, a terminal insulating member, and an annular sealing member. The electrode terminal has a base located inside the case and a polar column portion, which projects from the base. An inner surface of the case at the circumference of the through hole and/or a tip end of the terminal insulating member on the side corresponding to the base has a tapered portion. A cross-sectional shape of the tapered portion in a direction in which the base and the inner surface face of the case each other is inclined to the outside in the radial direction of the through hole from the side corresponding to the base toward the through hole. |
| US09692020B2 |
Organic electroluminescent device and method for fabricating the same
Disclosed an organic electroluminescent device and a method for fabricating the same. The device may include a thin film transistor disposed on a substrate; a first electrode formed for each pixel on the thin film transistor; a first pixel define layer formed to cover an edge portion of the first electrode; a second pixel define layer formed on the first pixel define layer; an organic layer formed on the first electrode; and a second electrode formed on the organic layer. |
| US09692018B2 |
Organic light emitting display apparatus reducing reflection of external light
An organic light emitting display apparatus includes: a substrate divided into an emission area and a non-emission area; a pixel electrode disposed in the emission area; an intermediate layer disposed on the pixel electrode, including an organic emission layer; a counter electrode covering the intermediate layer; an external light reflection layer disposed on the counter electrode, the external light reflection layer being configured to reflect a portion of incident visible rays; and absorb and transmit another portion of the incident visible rays; a phase control layer disposed between the counter electrode and the external light reflection layer, being configured to control a phase of a light reflected by the counter electrode to destructive interfere with light reflected by the external light reflection layer; a thin-film encapsulating layer disposed on the external light reflection layer; and a black matrix disposed on the thin-film encapsulating layer in the non-emission area. |
| US09692014B2 |
Display device
A display device includes a substrate; a transistor provided on the substrate; a first insulating film provided on the substrate and the transistor; a second insulating film provided on the first insulating film; an individual pixel electrode provided on the second insulating film; a light emitting layer provided on the individual pixel electrode; a common electrode provided on the light emitting layer; and a contact hole running through the first insulating film and the second insulating film and connecting a source or a drain of the transistor with the pixel electrode. The second insulating film has at least one recessed portion reaching the first insulating film; and the individual pixel electrode is provided along a top surface of the second insulating film and the first recessed portion. |
| US09692008B2 |
Organic electroluminescent display device
An organic electroluminescent display device includes a display region configured to display pixels; a frame region configured to surround the display region; a substrate; an organic electroluminescent element disposed on the substrate; a sealing member configured to cover the organic electroluminescent element; a lead wire disposed on the substrate and extending from a region covered with the sealing member to an outer side of the sealing member; and one or more organic insulators disposed within the frame region instead of within the display region. The lead wire includes two opposite side portions. The one organic insulator or each organic insulator covers part of at least one of the two side portions. The sealing member covers the one or more organic insulators. |
| US09692002B2 |
Organic light emitting display device
Disclosed is an organic light emitting display device that comprises a first light emitting unit between a first electrode and a second electrode, the first light emitting unit including a first hole transporting layer and a first light emitting layer; and a second light emitting unit between the first light emitting unit and the second electrode, the second light emitting unit including a second hole transporting layer and a second light emitting layer that emits a light of the same color as a light emitted by the first light emitting layer. An increase in driving voltage caused by a shift of an emission zone in the first light emitting layer or the second light emitting layer by prolonged driving is minimized which solves a problem of increased power consumption and improves the lifetime of the organic light emitting display device. |
| US09692001B2 |
Display device
The display device includes a first organic electroluminescence element which includes an anode and a cathode which form a pair, and a light emitting layer which is formed between the anode and the cathode on a substrate. The light emitting layer includes a plurality of sub-light emitting layers which perform light emitting of colors which are respectively different. Each of the plurality of sub-light emitting layers is doped with a quantum dot light emitting material corresponding to a color to be emitted. A current with current density corresponding to a position of a sub-light emitting layer of a desired color among the plurality of sub-light emitting layers is injected to the light emitting layer, and the sub-light emitting layer of the desired color performs light emitting. |
| US09691997B2 |
Devices having dielectric layers with thiosulfate-containing polymers
A semiconductor device can be prepared with a gate dielectric layer that comprises: (1) a photochemically or thermally crosslinked product of a photocurable or thermally curable thiosulfate-containing polymer that has a Tg of at least 50° C. and that comprises: an organic polymer backbone comprising (a) recurring units comprising pendant thiosulfate groups; and further comprises charge balancing cations, and (2) optionally, an electron-accepting photosensitizer component. |
| US09691993B2 |
Organic electroluminescent materials and devices
A compound having the structure of Formula M(LA)x(LB)y(LC)z is disclosed. In the structure: ligand LA is ligand LB is and ligand LC is while M is a metal having an atomic number greater than 40; x is 1 or 2; and y and z are 0, 1, or 2. In addition, X1, X2, X3, and X4 are C or N; wherein two adjacent RB form a six-membered aromatic ring E fused to ring B, where ring E is further substituted by RE, and (a) at least one RE is fused to ring E and has a structure selected from the group consisting of (b) at least one RA is fused to ring A and has a structure selected from the group consisting of or (c) both (a) and (b). Formulations and devices, such as OLEDs, that include the compound of Formula M(LA)x(LB)y(LC)z are also described. |
| US09691990B2 |
Compound, organic electronic element using same, and electronic device using the latter
The present invention relates to a compound, which is represented by one chemical formula among the chemical formulas (1) to (3), an organic electronic element comprising the compound, and an electronic device comprising the organic electronic element. The compound is characterized by comprising at least one phenyl group having at least one substitution with deuterium or tritium. |
| US09691988B2 |
Organic electroluminescent element, light-emitting material for organic electroluminescent element, and light-emitting device, display device, and illumination device using said element
An organic electroluminescent element using a compound represented by the following general formula emits dark blue light and has a small change in the chromaticity during luminance modulation: wherein each of R1 to R8 represents a hydrogen atom or a substituent; A1 to A4 represent CR31 or N; L and X each independently represent any one of CR32R33, NR34, O, S, and SiR35R36; and each of R31 to R36 represents a hydrogen atom or a substituent. |
| US09691982B2 |
Method of manufacturing thin film transistor
A method of manufacturing a thin film transistor is disclosed. In one aspect, the method includes forming an active layer over a substrate and forming a gate insulating layer containing a dopant over the active layer. The method also includes irradiating laser light onto the gate insulating layer such that the dopant of the gate insulating layer diffuses into the active layer. |
| US09691981B2 |
Memory cell structures
The present disclosure includes memory cell structures and method of forming the same. One such method includes forming a memory cell includes forming, in a first direction, a select device stack including a select device formed between a first electrode and a second electrode; forming, in a second direction, a plurality of sacrificial material lines over the select device stack to form a via; forming a programmable material stack within the via; and removing the plurality of sacrificial material lines and etching through a portion of the select device stack to isolate the select device. |
| US09691973B2 |
Semiconductor device and dielectric film including a fluorite-type crystal
A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p. |
| US09691970B2 |
Magnetoresistive devices and methods for manufacturing magnetoresistive devices
A magnetoresistive device includes a substrate and an electrically insulating layer arranged over the substrate. The magnetoresistive device further includes a first free layer embedded in the electrically insulating layer and a second free layer embedded in the electrically insulating layer. The first free layer and the second free layer are separated by a portion of the electrically insulating layer. |
| US09691969B2 |
Semiconductor integrated circuit and method of making the same
The present disclosure relates to a semiconductor integrated circuit which includes a substrate, a first patterned conductive layer, a first magnetic tunnel junction (MTJ) stack and a second MTJ stack. The first patterned conductive layer is over the substrate. The first MTJ stack, which is over the first patterned conductive layer, has a first size. The second MTJ stack, which is over the first patterned conductive layer, has a second size different from the first size. |
| US09691967B2 |
Magnetic memory devices having perpendicular magnetic tunnel structures therein
Magnetic memory cells include a magnetic tunnel junction and a first electrode, which is electrically coupled to the magnetic tunnel junction by a first conductive structure. This conductive structure includes a blocking layer and a seed layer, which extends between the blocking layer and the magnetic tunnel junction. The blocking layer is formed as an amorphous metal compound. In some of the embodiments, the blocking layer is a thermally treated layer and an amorphous state of the blocking layer is maintained during and post thermal treatment. |
| US09691966B2 |
Surface-mounted collision sensor, and method for collision detection
An apparatus assembly of a medical apparatus is equipped for collision detection by attaching a polyvinylidene fluoride (PVDF) cover assembly to at least one rigid surface of the apparatus assembly, with a resilient material between the PVDF cover assembly and the rigid surface. The PVDF assembly is composed of a PVDF foil with electrically conductive layers on opposite sides thereof. A protective layer covers the PVDF cover assembly. Electrical leads are connected to the conductive layers, and the piezoelectric property of the PVDF foil produces a voltage across the leads when a force associated with a collision acts on the PVDF foil. A detection circuit detects this voltage and initiates an appropriate response to the collision. |
| US09691963B2 |
Capacitive coupled resonator and filter device with comb electrodes and support pillars separating piezoelectric layer
A capacitive coupled resonator device includes a substrate, a bottom electrode, a piezoelectric layer, a top electrode, and at least one set of support pillars positioned between the piezoelectric layer and the top electrode and/or between the piezoelectric layer and the bottom electrode. The top electrode includes a first top comb electrode having a first top bus bar and first top fingers extending in a first direction from the first top bus bar, and a second top comb electrode having a second top bus bar and second top fingers extending in a second direction from the second top bus bar, the second direction being substantially opposite the first direction such that the first and second top fingers form a top interleaving pattern. The at least one set of support pillars separates at least one of the top and bottom electrodes from the piezoelectric layer, respectively, thereby defining corresponding air-gaps. |
| US09691960B1 |
Carrier, carrier leadframe, and light emitting device and method for manufacturing same
A carrier leadframe, including a frame body and a carrier, is provided. The frame body includes at least one supporting portion, and the carrier includes a shell and at least one electrode portion and is mechanically engaged with the frame body via the supporting portion. A method for manufacturing the carrier leadframe as described above, as well as a light emitting device made from the carrier leadframe and a method for manufacturing the device, are also provided. The carrier leadframe has carriers that are separate in advance and mechanically engaged with the frame body, thereby facilitating the quick release of material after encapsulation. Besides, in the carrier leadframe as provided, each carrier is electrically isolated from another carrier, so the electric measurement can be performed before the release of material. Therefore, the speed and yield of production of the light emitting device made from the carrier leadframe is improved. |
| US09691959B2 |
Light emitting device package
A packaged light emitting device die includes a package body having a profiled leadframe embedded in a body of reflecting material. The leadframe is exposed on mounting surface only on at least one solder bonding area. Solder is present only on the at least one solder bonding area and not elsewhere. The reflecting material provides the reflecting parts of the package so there is no need for a reflective layer to be deposited on leadframe. Moreover, the reflecting material can function as a solder resist to self-align the solder to the at least one solder bonding area. |
| US09691955B2 |
Solid state lighting devices with improved contacts and associated methods of manufacturing
Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile. |
| US09691949B2 |
Submount based light emitter components and methods
Submount based light emitter components and related methods are disclosed. In some aspects, light emitter components include a ceramic submount, at least a first pair of electrical traces disposed on a first side of the submount, at least a first pair of electrical contacts disposed on a second side of the submount, at least one light emitter chip disposed on the first side of the submount, and a non-ceramic reflector disposed about the at least one light emitter chip. The first pair of electrical contacts is configured to electrical communicate with the first pair of electrical traces. The at least one chip is configured to electrically communicate with the first pair of electrical traces. At least a portion of the reflector is configured to conceal a portion of each trace of the first pair of electrical traces. |
| US09691948B2 |
Method for manufacturing light emitting device with preferable alignment precision when transferring substrates
A method for manufacturing a light emitting device is provided. Multiple epitaxial structures and multiple bonding pads formed thereon are formed on a growth substrate. A first adhesive layer is formed on the growth substrate, wherein the first adhesive layer encapsulates the epitaxial structures and the bonding pads. A first substrate is provided on the first adhesive layer. The growth substrate is removed, so as to expose the epitaxial structures and the first adhesive layer. A second substrate and a second adhesive layer disposed thereon are provided, wherein the epitaxial structures are adhered on the second substrate by the second adhesive layer. The first adhesive layer and the first substrate are removed. |
| US09691938B2 |
Advanced electronic device structures using semiconductor structures and superlattices
Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity. |
| US09691937B2 |
Light-emitting device manufacturing method
Provided is a method that can manufacture a light-emitting device in which quantum dot is used and which has a high luminous efficiency. A light-emitting device (1) is manufactured that includes: a cell (10) including first and second glass plates (11, 12) facing and spaced apart from each other; and quantum dot (17) encapsulated in the cell (10). Prior to the encapsulation of the quantum dot (17), a reduction step of reducing moisture adsorbed on the inside walls of the cell (10) is performed. |
| US09691936B2 |
Manufacturing method of LED carrier
An LED carrier includes a substrate, a metallic layer, an insulating layer, and a reflecting layer. The metallic layer is disposed on the substrate and has a die bonding region and a ring-shaped wiring region separated from the die bonding region. A region arranged between the die bonding region and the ring-shaped wiring region is defined as an insulating region. The insulating layer at least partially covers the insulating region. The reflecting layer is arranged above the die bonding region and at least partially covers the top surface of the insulating layer. Moreover, the instant disclosure also provides a manufacturing method of an LED carrier. |
| US09691933B2 |
Radiation and temperature hard multi-pixel avalanche photodiodes
The structure and method of fabricating a radiation and temperature hard avalanche photodiode with integrated radiation and temperature hard readout circuit, comprising a substrate, an avalanche region, an absorption region, and a plurality of Ohmic contacts are presented. The present disclosure provides for tuning of spectral sensitivity and high device efficiency, resulting in photon counting capability with decreased crosstalk and reduced dark current. |
| US09691927B2 |
Solar cell apparatus and method of fabricating the same
A solar cell apparatus according to the embodiment includes a support substrate; a back electrode layer on the support layer; a light absorbing layer on the back electrode layer; a plurality of buffer layers on the light absorbing layer, the plurality of buffer layers having a bandgap gradually increased from a bottom thereof to a top thereof; and a window layer on the buffer layers. |
| US09691921B2 |
Textured metallic back reflector
Embodiments of the invention generally relate to device fabrication of thin films used as solar devices or other electronic devices, and include textured back reflectors utilized in solar applications. In one embodiment, a method for forming a textured metallic back reflector which includes depositing a metallic layer on a gallium arsenide material within a thin film stack, forming an array of metallic islands from the metallic layer during an annealing process, removing or etching material from the gallium arsenide material to form apertures between the metallic islands, and depositing a metallic reflector layer to fill the apertures and cover the metallic islands. In another embodiment, a textured metallic back reflector includes an array of metallic islands disposed on a gallium arsenide material, a plurality of apertures disposed between the metallic islands and extending into the gallium arsenide material, a metallic reflector layer disposed over the metallic islands, and a plurality of reflector protrusions formed between the metallic islands and extending from the metallic reflector layer and into the apertures formed in the gallium arsenide material. |
| US09691917B2 |
Back contact having selenium blocking layer for photovoltaic devices such as copper-indium-diselenide solar cells
A photovoltaic device (e.g., solar cell) includes: a front substrate (e.g., glass substrate); a semiconductor absorber film; a back contact including a first conductive layer of or including copper (Cu) and a second conductive layer of or including molybdenum (Mo); and a rear substrate (e.g., glass substrate). A selenium blocking layer is provided between at least the Cu inclusive layer and the Mo inclusive layer. |
| US09691916B2 |
Synthesis of three-dimensional graphene foam: use as supercapacitors
The invention relates to three-dimensional crystalline foams with high surface areas, high lithium capacity, and high conductivity for use as electrode materials and methods for their fabrication. In additional embodiments, the invention also relates to the use of three-dimensional crystalline foams as supercapacitors for improved charge and energy storage. |
| US09691913B2 |
Solar cell module and method for manufacturing same
A solar cell module is provided with: a plurality of solar cells, each of which comprises a first electrode and a second electrode that are formed on a photoelectric conversion unit; and a wiring material that is fitted on the first electrode and the second electrode using an adhesive and connects the solar cells with each other. The adhesive is provided so as to extend beyond a region (R) directly below the wiring material and to adhere to a lateral surface of the wiring material. The solar cell module has a pore in the region (R) directly below the wiring material. |
| US09691912B1 |
Devices having nanoscale structures and methods for making same
In one embodiment, a device includes a substrate having a top surface and cavity that defines generally vertical walls, a thin film of material that has been deposited on the walls of the cavity, and a further material that fills the cavity, wherein a top edge of the thin film is exposed and forms a trace that is flush with the top surface of the substrate and has substrate material on one side and the further material on the other side. |
| US09691911B1 |
Semiconductor device
A semiconductor device include a substrate, a first well region formed in the substrate, a first isolation structure formed in the first well region, a Schottky barrier structure formed on the first well region, and a plurality of assist structures formed on the first well region. The substrate includes a first conductivity type, the first well region includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary to each other. The assist structures physically contact the first well region. |
| US09691909B2 |
Current aperture diode and method of fabricating the same
A diode and a method of making same has a cathode an anode and one or more semiconductor layers disposed between the cathode and the anode. A dielectric layer is disposed between at least one of the one or more semiconductor layers and at least one of the cathode or anode, the dielectric layer having one or more openings or trenches formed therein through which the at least one of said cathode or anode projects into the at least one of the one or more semiconductor layers, wherein a ratio of a total surface area of the one or more openings or trenches formed in the dielectric layer at the at least one of the one or more semiconductor layers to a total surface area of the dielectric layer at the at least one of the one or more semiconductor layers is no greater than 0.25. |
| US09691907B1 |
Non-volatile memory device and manufacturing method thereof
A non-volatile memory device includes a plurality of memory cells. Each memory cell includes a vertical channel, a control gate, a floating gate, and an erase gate disposed on a substrate. The vertical channel extends upwards in a vertical direction. The control gate, the floating gate, and the erase gate surround the vertical channel respectively, and a part of the floating gate is surrounded by the control gate. The erase gate is disposed between the substrate and the floating gate in the vertical direction, and the floating gate include a tip extending toward the erase gate. The vertical channel and electrodes surrounding the vertical channel, such as the control gate, the floating gate, and the erase gate, are used to reduce the area of the memory cell on the substrate of the non-volatile memory device in the present invention. The density of the memory cells may be enhanced accordingly. |
| US09691902B2 |
Semiconductor device
A semiconductor device includes a first pattern on a first active region, a second pattern on a second active region, and a third pattern on a third active region. The first pattern is spaced from the second pattern by a first interval corresponding to the width of a first recess between the first and second active regions. The second pattern is spaced from the third pattern by a second interval corresponding to the width of a second recess between the second and third active regions. The first, second, and third patterns includes gate patterns, and the first and second recesses include semiconductor material with a conductivity type different from the active regions. The semiconductor material in one recess extends higher than the semiconductor material in the other recess. The first, second, and third patterns have the same width, and the first and second recesses have different depths. |
| US09691901B2 |
Semiconductor device
A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer. |
| US09691898B2 |
Germanium profile for channel strain
The present disclosure relates to a transistor device having a strained source/drain region comprising a strained inducing material having a discontinuous germanium concentration profile. In some embodiments, the transistor device has a gate structure disposed onto a semiconductor substrate. A source/drain region having a strain inducing material is disposed along a side of the gate structure within a source/drain recess in the semiconductor substrate. The strain inducing material has a discontinuous germanium concentration profile along a line extending from a bottom surface of the source/drain recess to a top surface of the source/drain recess. The discontinuous germanium concentration profile provides improved strain boosting and dislocation propagation. |
| US09691892B2 |
High voltage transistor operable with a high gate voltage
A semiconductor device includes a first load contact, a second load contact and a semiconductor region positioned between the first and second load contacts. The semiconductor region includes: a first semiconductor contact zone in contact with the first load contact; a second semiconductor contact zone in contact with the second load contact; a first conductivity type semiconductor drift zone between the first and second semiconductor contact zones, wherein the semiconductor drift zone couples the first semiconductor contact zone to the second semiconductor contact zone. The semiconductor device further comprises: a trench comprising a control electrode and an insulator. The control electrode extends for at least 75% of the semiconductor drift zone. A drift zone doping concentration and an extension of the semiconductor drift zone defines a blocking voltage of the semiconductor device. The insulator is configured for insulating a voltage that amounts to at least 50% of said blocking voltage. |
| US09691889B2 |
Integrated power device
A semiconductor device that includes a plurality of isolated half-bridges formed in a common semiconductor die. |
| US09691887B2 |
Semiconductor device with variable resistive element
A semiconductor device includes a semiconductor body including a drift zone that forms a pn junction with an emitter region. A first load electrode is at a front side of the semiconductor body. A second load electrode is at a rear side of the semiconductor body opposite to the front side. One or more variable resistive elements are electrically connected in a controlled path between the drift zone and one of the first and second load electrodes. The variable resistive elements activate and deactivate electronic elements of the semiconductor device in response to a change of the operational state of the semiconductor device. |
| US09691884B2 |
Monolithic three dimensional NAND strings and methods of fabrication thereof
Methods of making a monolithic three dimensional NAND string that include forming a stack of alternating first material layers and second material layers over a substrate, where each of the second material layers includes a layer of a first silicon oxide material between two layers of a second silicon oxide material different from the first silicon oxide material, etching the stack to form a front side opening in the stack, forming a memory film over a sidewall of the front side opening, and forming a semiconductor channel in the front side opening such that at least a portion of the memory film is located between the semiconductor channel and the sidewall of the front side opening, where at least one of an air gap or a material which has a dielectric constant below 3.9 is formed between the respective two layers of second silicon oxide material. |
| US09691881B2 |
Manufacturing method of thin film transistor substrate
The invention provides a manufacturing method of a thin film transistor substrate including: sequentially forming a gate electrode, a gate insulating layer covering the gate electrode, an active material layer, and a photo-sensitive material layer on a first substrate; performing a photolithography process by using a half tone mask to form a protective layer which is above the gate electrode and has a first recess and a second recess; wet etching the active material layer by using the protective layer as a mask to form an active layer; removing a portion of the protective layer at bottoms of the first recess and the second recess to expose a first portion and a second portion of the active layer respectively; forming a first electrode connecting to the first portion; and forming a second electrode connecting to the second portion. |
| US09691880B2 |
Semiconductor device with enhanced 3D resurf
A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and spaced from one another along a first lateral dimension, and a drift region in the semiconductor substrate and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions. The drift region has a notched dopant profile in a second lateral dimension along an interface between the drift region and the drain region. |
| US09691876B2 |
Enhanced gate replacement process for high-K metal gate technology
The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is formed over a portion of the high-k dielectric layer. A second capping layer is formed over the first capping layer and the high-k dielectric layer. A dummy gate electrode layer is formed over the second capping layer. The dummy gate electrode layer, the second capping layer, the first capping layer, and the high-k dielectric layer are patterned to form an NMOS gate and a PMOS gate. The NMOS gate includes the first capping layer, and the PMOS gate is free of the first capping layer. The dummy gate electrode layer of the PMOS gate is removed, thereby exposing the second capping layer of the PMOS gate. The second capping layer of the PMOS gate is transformed into a third capping layer. |
| US09691875B2 |
Method of manufacturing nitride semiconductor device
A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360° C. for 8 to 240 hours on the transistor; and after the high-temperature annealing, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360° C. |
| US09691870B2 |
Semiconductor device
A semiconductor device including a semiconductor substrate and an electrode formed from an alloy containing aluminum, silicon and titanium. The silicon content in the electrode is from 0.5 to 1.0% by weight relative to the total weight of the electrode, the titanium content in the electrode is from 0.8 to 3.0% by weight relative to the total weight of the electrode, and the thickness of the electrode is at least 1 μm. |
| US09691868B2 |
Merging lithography processes for gate patterning
Methods for fabricating devices on a die, and devices on a die. A method may include patterning a first region to create a first gate having a first gate length and a first contacted polysilicon pitch (CPP) with a first process. The first CPP is smaller than a single pattern lithographic limit. The method also includes patterning the first region to create a second gate having a second gate length or a second CPP with a second process. The second CPP is smaller than the single pattern lithographic limit. The second gate length is different than the first gate length. |
| US09691863B2 |
Self-aligned contact for trench power MOSFET
Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. Alternatively, the device has an oxide layer over the conductive material in the gate trenches and over portions of mesas between every two adjacent contact structures. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09691861B2 |
Method for analyzing discrete traps in semiconductor devices
A method analyzes traps in a semiconductor device by determining a first-order derivative of a signal representing an operation of the semiconductor device over time to produce a signal rate change. The traps in the semiconductor device are analyzed based on lifetimes corresponding to peaks of the signal rate change. |
| US09691859B2 |
Silicon carbide semiconductor device
There is provided a silicon carbide semiconductor device allowing for integration of a transistor element and a Schottky barrier diode while avoiding reduction of an active region and decrease of a breakdown voltage. A silicon carbide semiconductor device includes a silicon carbide layer. The silicon carbide layer includes: a first region defining an outer circumference portion of an element region in which a transistor element is provided; and a JTE region provided external to the first region in a drift layer and electrically connected to the first region. The first region is provided with at least one opening through which the drift layer is exposed. The silicon carbide semiconductor device further includes a Schottky electrode provided in the opening and forming a Schottky junction with the drift layer. |
| US09691858B2 |
Silicon carbide semiconductor device and manufacturing method therefor
A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance. |
| US09691852B2 |
Semiconductor device
An element isolation trench is formed in a substrate and is formed along each side of a polygon in a planar view. A first trench is formed in the substrate and extends in a direction different from that of any side of the trench. A first-conductivity type region is formed on/over apart located on the side of an end of the first trench in the substrate. Accordingly, when an impurity region that extends in a depth direction in the substrate is formed by forming the trench in the substrate and diagonally implanting an impurity into the trench, the impurity is prevented from being implanted into a side face of a groove such as a groove for element isolation and so forth impurity implantation into the side face of which is not desired. |
| US09691851B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes one nanowire structure disposed on semiconductor substrate and extending in first direction on semiconductor substrate. Each nanowire structure includes plurality of nanowires extending along first direction and arranged in second direction, the second direction being substantially perpendicular to first direction. Each nanowire is spaced-apart from immediately adjacent nanowire. A gate structure extends in third direction over first region of nanowire structure, the third direction being substantially perpendicular to both first direction and second direction. The gate structure includes a gate electrode. Source/drain regions are disposed over second region of nanowire structure, the second region being located on opposing sides of gate structure. The gate electrode wraps around each nanowire. When viewed in cross section taken along third direction, each nanowire in nanowire structure is differently shaped from other nanowires, and each nanowire has substantially same cross-sectional area as other nanowires in nanowire structure. |
| US09691839B2 |
Metal-insulator-metal (MIM) capacitor with insulator stack having a plurality of metal oxide layers
Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack. |
| US09691837B2 |
Organic light emitting diode display reducing parasitic capacitance
An organic light emitting diode display includes a plurality of pixels. At least one pixel is connected to a scan line receive a scan signal, a data line to receive a data signal, and voltage line to receive a driving voltage. The at least one pixel includes a switching transistor including a switching drain electrode to output the data voltage, a driving transistor including a driving source electrode connected to the switching drain electrode, and an organic light emitting diode connected to a driving drain electrode of the driving transistor. The driving source electrode is separated from the data line. |
| US09691830B2 |
Organic electroluminescent display panel, its manufacturing method and display device
An organic electroluminescent display panel, its manufacturing method and a display device are disclosed. In the organic electroluminescent display panel, a pixel definition layer provided therein has opening regions corresponding to pixel areas in the OLED, and each of the opening regions has an opening larger than a bottom surface of the opening region (300). An upper surface (a) of the pixel definition layer is formed from a hydrophobic material, and an inclination surface (b) of the pixel definition layer corresponding to each of the opening regions is formed from a hydrophilic material. The above OLED can assure the uniformity of the film layers formed after the pixel definition layer can be guaranteed to improve the light emitting performance of the OLED. |
| US09691828B2 |
Display apparatus having thin films including nanoparticles
The invention provides a display apparatus and a method for manufacturing the same, relates to the field of display technology, and solves the problem of low display luminance due to the existing display apparatus being affected by other film layers. A display apparatus comprises a light emitting unit and further comprises several layers of thin film located in the light emission path of the light emitting unit, and at least one of the several layers of thin film has nanoparticles. |
| US09691827B2 |
Display device
According to an aspect, a display device includes a display unit in which a plurality of pixels are arranged in a matrix along two directions intersecting with each other. Each of the pixels includes three sub-pixels corresponding to three of four colors including a first color, a second color, a third color, and a fourth color. An area of one sub-pixel among the three sub-pixels is larger than the area of each of the other two sub-pixels. A sub-pixel of the fourth color is one of the other two sub-pixels. Pixels each including the sub-pixel of the fourth color are not adjacent to each other in at least one of the two directions in the display unit. |
| US09691825B2 |
Light-emitting element, light-emitting device, electronic device, and lighting device including semi-transmissive and semi-reflective electrodes
Provided is a light-emitting device which can emit monochromatic lights with high color purity due to a microcavity effect and which can provide a white light with a broad spectrum when the monochromatic lights are combined. The light-emitting device has a red-, green-, blue-, and yellow-emissive light-emitting elements each of which has a reflective electrode and a semi-transmissive and semi-reflective electrode. The red-, green-, blue-, and yellow-emissive light-emitting elements have the same structure other than the reflective electrode and a layer in contact with the reflective electrode to selectively emit red, green, blue, and yellow lights, respectively. Red, green, and blue color filters are also provided over the red-, green-, blue-, light-emitting elements, respectively. An EL layer is commonly shared by the red-, green-, blue-, and yellow-emissive light-emitting elements, and the semi-transmissive and semi-reflective electrode covers an edge portion of the EL layer. |
| US09691824B2 |
OLED panel, manufacturing method thereof and display device
The present invention provides an OLED panel, a manufacturing method thereof and a display device. The OLED panel includes a substrate, an OLED light emitting unit that is provided on the substrate and a cover plate that is provided above the OLED light emitting unit, wherein a frit is provided in an area between the cover plate and the substrate corresponding to and surrounding a periphery of the light emitting unit, the frit being used for bonding the cover plate and the substrate together so as to hermetically package the OLED light emitting unit, and a supplementary packaging structure is further provided in an area between the cover plate and the substrate corresponding to a periphery of the frit, the supplementary packaging structure being used for assisting the frit to package the OLED light emitting unit and support the cover plate and the substrate. |
| US09691823B2 |
Image sensors and electronic devices including the same
Image sensors, and electronic devices including the image sensors, include a first photoelectronic device including at least one of a blue photoelectronic device sensing light in a blue wavelength region, a red photoelectronic device sensing light in a red wavelength region, and a green photoelectronic device sensing light in a green wavelength region, and a second photoelectronic device stacked on one side of the first photoelectronic device without being interposed by a color filter, wherein the second photoelectronic device senses light in an infrared region. |
| US09691822B2 |
Organic light emitting diode display and manufacturing method thereof
An organic light emitting diode display including: a substrate; a plurality of first signal lines on the substrate extending in a first direction; a first insulating layer covering the substrate and the first signal lines; a plurality of auxiliary signal lines formed on the first insulating layer and overlapping the first signal lines; a second insulating layer covering the auxiliary signal lines; a plurality of first signal line connecting members formed on the second insulating layer while overlapping parts of the auxiliary signal lines; a plurality of second signal lines crossing the first signal lines; a plurality of switching transistors and a plurality of driving transistors connected with the first signal lines and the second signal lines; and a plurality of organic light emitting diodes electrically connected to the driving transistors, where the first signal line connecting members connect the first signal lines to the auxiliary signal lines. |
| US09691821B2 |
Vertical cross-point arrays for ultra-high-density memory applications
An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized. |
| US09691820B2 |
Block architecture for vertical memory array
Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell. |
| US09691818B2 |
Three dimensional semiconductor device having lateral channel
A 3D semiconductor device and a method of manufacturing the same are provided. The 3D semiconductor device includes a semiconductor substrate, an active line formed on the insulating layer, including a source region, a drain region and a channel region positioned between the source region and the drain region, a gate electrode located on a portion of the active line, corresponding to a region between the source region and the drain region, and extending to a direction substantially perpendicular to the active line, and a line-shaped common source node formed to be electrically coupled to the source region and extending substantially in parallel to the gate electrode in a space between gate electrodes. The source region and the drain region of the active line are formed of a first material and the channel region of the active line is formed of a second material being different from the first material. |
| US09691816B2 |
Magnetic memory devices
Magnetic memory devices are provided. A magnetic memory device includes a Magnetic Tunnel Junction (MTJ) structure on a contact. Moreover, the magnetic memory device includes an insulating structure and an electrode between the MTJ structure and the contact. In some embodiments, a first contact area of the electrode with the MTJ structure is smaller than a second contact area of the insulating structure with the MTJ structure. |
| US09691810B1 |
Curved image sensor
An image sensor includes a plurality of photodiodes arranged in an array and disposed in a semiconductor material with pinning wells disposed between individual photodiodes in the plurality of photodiodes. The image sensor also includes a microlens layer. The microlens layer is disposed proximate to the semiconductor material and is optically aligned with the plurality of photodiodes. A spacer layer disposed between the semiconductor material and the microlens layer. The spacer layer has a concave cross-sectional profile across the array, and the microlens layer is conformal with the concave cross-sectional profile of the spacer layer. |
| US09691807B2 |
CMOS image sensor structure
A semiconductor device includes a substrate, a logic gate structure, a photosensitive gate structure, a hard mask layer, a first spacer, a first source, a first drain, a second spacer, a second source and a second drain. The logic gate structure and the photosensitive gate structure are disposed on a surface of the substrate. The hard mask layer covers the logic gate structure, the photosensitive gate structure and the surface of the substrate. The first spacer overlies the hard mask layer conformal to a sidewall of the logic gate structure. The first source and drain are respectively disposed in the substrate at two opposite sides of the logic gate structure. The second spacer overlies the hard mask layer conformal to a sidewall of the photosensitive gate structure. The second source and drain are respectively disposed in the substrate at two opposite sides of the photosensitive gate structure. |
| US09691800B2 |
Image sensor and electronic device having the same
An image sensor includes a substrate including photoelectric conversion elements for a plurality of unit pixels, which are two-dimensionally arranged in a pixel array; a light transmission member on the substrate; a grid structure in the light transmission member and having multiple layers; and a light collection member on the light transmission member, wherein the grid structure is tilted for respective chief ray angles of the plurality of unit pixels according to locations of the plurality of unit pixels in the pixel array. |
| US09691799B2 |
Thin film transistor substrate and display using the same
The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate, and a display using the same. A display includes a first thin film transistor including a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode, and a first drain electrode; a second thin film transistor including a second gate electrode, an oxide semiconductor layer on the second gate electrode, a second source electrode, and a second drain electrode; and an intermediate insulating layer including a nitride layer and an oxide layer on the nitride layer, the intermediate insulating layer disposed on the first gate electrode and the second gate electrode and under the oxide semiconductor layer. |
| US09691797B2 |
Display device
A display device according to one aspect of the present invention includes a plurality of scanning lines (10a) and a plurality of signal lines (11a); a plurality of pixel thin-film transistors; a common scanning interconnect (10b); and a plurality of protective diodes (6) (protective elements). At least a part of a plurality of connecting interconnects that electrically connect the common scanning interconnect with the plurality of protective diodes are constituted by connecting interconnects (11e) on the same layer as the signal lines. The surface area of overlapping parts between a plurality of semiconductor layers of thin-film transistors and the scanning lines and the surface area overlapping parts between the plurality of semiconductor layers and the common scanning interconnect are substantially equal. |
| US09691795B2 |
Display apparatus and manufacturing method thereof
An exemplary embodiment of the described technology relates generally to a display apparatus including a plurality of pixels and corresponding to one area of a substrate for displaying an image, and a pad area corresponding to another area of the substrate, the pad area including a lower electrode configured to transmit an electric signal to the pixels, and a plurality of pad electrodes electrically connecting the lower electrode and a driving chip, wherein each of the pad electrodes includes a first contact surface for contacting the lower electrode, a second contact surface for contacting the driving chip, and an oxide layer on a surface of the pad electrode that is exposed to the outside, and that connects the first contact surface and the second contact surface. |
| US09691786B1 |
Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a first semiconductor layer; and a memory cell array on the first semiconductor layer, the memory cell array including a source line, a second semiconductor layer, and a conductive layer, those are sequentially disposed in a first direction and the memory cell array further including a third semiconductor layer which is columnar and extends in the first direction and a charge accumulation film disposed between the conductive layer and the third semiconductor layer, wherein the second semiconductor layer includes a first impurity region of a first conductivity type disposed at a position of the third semiconductor layer as viewed from the first direction and a second impurity region adjacent to the first impurity region which has a second conductivity type different from the first conductivity type. |
| US09691781B1 |
Vertical resistor in 3D memory device with two-tier stack
A vertical, columnar resistor in a semiconductor device is provided, along with techniques for fabricating such a resistor. The resistor may be provided in a peripheral area of a 3D memory device which has a two-tier or other multi-tier stack of memory cells. The structure and fabrication of the resistor can be integrated with the structure and fabrication of the stack of memory cells. The resistor may comprise doped polysilicon. In an example implementation, a polysilicon pillar extends a height of a first tier of the stack and a metal pillar above the polysilicon pillar extends a height of a second tier of the stack. |
| US09691780B2 |
Interdigitated capacitor in split-gate flash technology
The present disclosure relates to an inter-digitated capacitor that can be formed along with split-gate flash memory cells and that provides for a high capacitance per unit area, and a method of formation. In some embodiments, the inter-digitated capacitor has a well region disposed within an upper surface of a semiconductor substrate. A plurality of trenches vertically extend from the upper surface of the semiconductor substrate to positions within the well region. Lower electrodes are arranged within the plurality of trenches. The lower electrodes are separated from the well region by a charge trapping dielectric layer arranged along inner-surfaces of the plurality of trenches. A plurality of upper electrodes are arranged over the semiconductor substrate at locations laterally separated from the lower electrodes by the charge trapping dielectric layer and vertically separated from the well region by a first dielectric layer. |
| US09691778B2 |
Multiheight contact via structures for a multilevel interconnect structure
Contact openings extending to sacrificial layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. In one embodiment, pairs of an electrically conductive via contact and electrically conductive electrodes can be simultaneously formed as integrated line and via structures. In another embodiment, encapsulated unfilled cavities can be formed in the contact openings by non-conformal deposition of a material layer, electrically conductive electrodes can be formed by replacement of portions of the sacrificial layers, and the electrically conductive via contacts can be subsequently formed on the electrically conductive electrodes. Electrically conductive via contacts extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liner. |
| US09691769B2 |
Memory device having buried gate and method of fabricating the same
A memory device includes a substrate including active areas and isolation areas, trenches in the isolation areas, active patterns in the active areas, the active patterns protruding from the substrate, isolation layers filling the trenches, gate trenches crossing the active patterns and the isolation layers, and gate line stacks filling the gate trenches, a first width of the gate trench in the isolation layer being greater than a second width of the gate trench in the active pattern. |
| US09691768B2 |
Nanowire or 2D material strips interconnects in an integrated circuit cell
An integrated circuit design tool includes a cell library. The cell library includes entries for a plurality of cells, entries in the cell library including specifications of particular cells in a computer executable language. At least one entry in the cell library can comprise a specification of physical structures and timing parameters of a circuit including a first transistor, a second transistor, and an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising one or more nanowires or 2D material strips arranged in parallel. An integrated circuit including the circuit is described. |
| US09691767B2 |
Semiconductor device and manufacturing method of semiconductor device
A manufacturing method of a semiconductor device according to a disclosed embodiment includes: implanting a first impurity into a first region of a semiconductor substrate, forming a semiconductor layer on the semiconductor substrate, forming a trench in the semiconductor layer and the semiconductor substrate, forming an isolation insulating film in the trench, implanting a second impurity into a second region of the semiconductor layer, forming a first gate insulating film and a first gate electrode in the first region, forming a second gate insulating film and a second gate electrode in the second region, forming a first source region and a first drain region at both sides of the first gate electrode, and forming a second source region and a second drain region at both sides of the second gate electrode. |
| US09691764B2 |
FinFET cell architecture with power traces
A finFET block architecture suitable for use of a standard cell library, is based on an arrangement including a first set of semiconductor fins in a first region of the substrate having a first conductivity type, and a second set of semiconductor fins in a second region of the substrate, the second region having a second conductivity type. A patterned gate conductor layer including gate traces in the first and second regions, arranged over channel regions of the first and second sets of semiconductor fins is used for transistor gates. Patterned conductor layers over the gate conductor layer are arranged in orthogonal layout patterns, and can include a plurality of floating power buses over the fins in the first and second regions. |
| US09691759B2 |
Semiconductor device including semiconductor substrate, silicon carbide semiconductor layer, unit cells, source, and gate
A semiconductor device includes a first silicon carbide semiconductor layer, a source including a source pad and a source wiring, a gate including a gate pad and a gate wiring, first unit cells disposed in a first element region, and second unit cells disposed in a second element region. In a plan view, the first and second element regions are adjacent to each other with the gate wiring between the first and second element regions. A first electrode including the gate electrode of each first unit cell is disposed in the first element region and electrically connected to the gate. A second electrode including the gate electrode of each second unit cell is disposed in the second element region and not electrically connected to the gate. The first and second electrodes are separated below the gate wiring. |
| US09691749B2 |
Exclusion zone for stress-sensitive circuit design
A semiconductor structure less affected by stress and a method for forming the same are provided. The semiconductor structure includes a semiconductor chip. Stress-sensitive circuits are substantially excluded out of an exclusion zone to reduce the effects of the stress to the stress-sensitive circuits. The stress-sensitive circuits include analog circuits. The exclusion zone preferably includes corner regions of the semiconductor chip, wherein the corner regions preferably have a diagonal length of less than about one percent of the diagonal length of the semiconductor chip. The stress-sensitive analog circuits preferably include devices having channel lengths less than about five times the minimum channel length. |
| US09691747B1 |
Manufacture of wafer—panel die package assembly technology
Disclosed is a process, structure, equipment and apparatus directed to a low cost, high volume approach for the assembly of ultra small die to three-dimensional (3D) or 2.5D semiconductor packages. |
| US09691746B2 |
Methods of manufacturing stacked semiconductor die assemblies with high efficiency thermal paths
Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material. |
| US09691741B2 |
Method for producing optoelectronic semiconductor components and optoelectronic semiconductor component
A method for producing optoelectronic semiconductor components and an optoelectronic semiconductor component are disclosed. In an embodiment the method includes: A) creating a blank by pultrusion from a glass melt, B) shaping the blank into a billet-shaped optical element with a longitudinal axis, the optical element having a mounting side and a light outlet side, C) producing conductor tracks on the mounting side, D) mounting a plurality of optoelectronic semiconductor chips on the mounting side of the optical element and connecting them to the conductor tracks and E) separating the optical element into the optoelectronic semiconductor components, wherein each optoelectronic semiconductor component comprises at least two of the semiconductor chips, and wherein at least steps A) to D) are performed in the stated sequence. |
| US09691739B2 |
Semiconductor device and method of manufacturing same
In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a first semiconductor substrate having a first surface and a second surface opposite the first surface, a first insulating film formed on the first surface, a first hole formed in the first insulating film and partially extending into the first semiconductor substrate, a second hole formed in the second surface, a first electrode entirely filling the first hole, and a conductive film conformally formed in the second hole. The conductive film is electrically connected to a bottom surface of the first electrode and leaves a third hole in the first semiconductor substrate open. The third hole is configured to receive a second electrode of a second semiconductor substrate. |
| US09691738B2 |
Bonding package components through plating
A method includes aligning a first electrical connector of a first package component to a second electrical connector of a second package component. With the first electrical connector aligned to the second electrical connector, a metal layer is plated on the first and the second electrical connectors. The metal layer bonds the first electrical connector to the second electrical connector. |
| US09691734B1 |
Method of forming a plurality of electronic component packages
A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system. |
| US09691732B2 |
Semiconductor package with elastic coupler and related methods
A semiconductor package includes: a die coupled to a substrate; a housing coupled to the substrate and at least partially enclosing the die within a cavity of the housing, and; a pin fixedly coupled to the housing and electrically coupled with the die. The pin includes a reversibly elastically deformable lower portion, which in implementations includes a spring, configured to compress to prevent a lower end of the pin from lowering beyond a predetermined point relative to the substrate when the housing is lowered to be coupled to the substrate. The pin is fixedly coupled in a top of the housing and is configured to be coupled with the substrate by lowering the housing towards the substrate. In implementations the pin includes two rigid portions coupled together only with a coil spring, the spring biasing the rigid portions away from one another when the housing is lowered towards the substrate. |
| US09691731B2 |
Package-on-package assembly with wire bonds to encapsulation surface
A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby. |
| US09691725B2 |
Integrated semiconductor device and wafer level method of fabricating the same
The present disclosure provides one embodiment of a stacked semiconductor device. The stacked semiconductor device includes a first substrate; a first bond pad over the first substrate; a second substrate including a second electrical device fabricated thereon; a second bond pad over the second electrical device over the second substrate, the second bond pad electrically connecting to the second electrical device; a second insulation layer over the second bond pad having a top surface, the second insulation layer being bonded toward the first bond pad of the first substrate; and a through-substrate-via (“TSV”) extending from a surface opposite to the first bond pad through the first substrate and through the top surface of the second insulation layer to the second bond pad. |
| US09691722B2 |
Surface mount high-frequency circuit
A surface mount high-frequency circuit is configured such that a plurality of ground pads 41 and a plurality of external connection ground conductors 51 are discretely disposed to surround a signal line pad 42 and an external connection signal line conductor 52, and a plurality of interlayer connection ground conductors 31 and that a plurality of columnar ground conductors 12 are discretely disposed to surround an interlayer connection signal line conductor 32. Thus, it is possible to suppress radiation of an unnecessary signal to the outside using a simple production process that is completed by only a wafer process without separately preparing a component such as a shield cover case. |
| US09691717B2 |
Fabricating process for package substrate
A core substrate is prepared first, a bottom redistribution layer RDL1 is formed. Any warpage of the RDL1 is suppressed by the core substrate. In a later process, warpage is further suppressed by a molding compound encapsulating the core substrate. A plurality of metal pillars are formed passing through the core substrate longitudinally; a top redistribution layer RDL2 is then formed on a top surface of the metal pillars. |
| US09691708B1 |
Semiconductor package and manufacturing method thereof
A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a molded semiconductor device, a first redistribution layer, a second redistribution layer, and a plurality of through interlayer vias. The molded semiconductor device includes a die. The first redistribution layer is disposed on a first side of the molded semiconductor device. The second redistribution layer is disposed on a second side of the molded semiconductor device opposite to the first side, wherein the second redistribution layer includes a patterned metal layer having an interconnection circuit portion electrically connected to the die and a metal ring surrounding and insulated from the interconnection circuit portion. The through interlayer vias are located right under the metal ring and extending through the molded semiconductor device to be electrically connect the first redistribution layer and the second redistribution layer. |
| US09691707B2 |
Semiconductor device and method of forming 3D dual side die embedded build-up semiconductor package
A semiconductor device has a plurality of semiconductor die. A substrate is provided with bumps disposed over the substrate. A first prefabricated insulating film is disposed between the semiconductor die and substrate. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The bumps include a copper core encapsulated within copper plating. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The substrate includes a conductive layer formed in the substrate and coupled to the bumps. The semiconductor die is disposed between the bumps of the substrate. The bumps and the semiconductor die are embedded within the first prefabricated insulating film. A portion of the first prefabricated insulating film is removed to expose the bumps. The bumps electrically connect the substrate to the interconnect structure. |
| US09691705B2 |
Ultrathin superlattice of MnO/Mn/MnN and other metal oxide/metal/metal nitride liners and caps for copper low dielectric constant interconnects
An electrical device including an opening in a low-k dielectric material, and a copper including structure present within the opening for transmitting electrical current. A liner is present between the opening and the copper including structure. The liner includes a superlattice structure comprised of a metal oxide layer, a metal layer present on the metal oxide layer, and a metal nitride layer that is present on the metal layer. A first layer of the superlattice structure that is in direct contact with the low-k dielectric material is one of said metal oxide layer and a final layer of the superlattice structure that is in direct contact with the copper including structure is one of the metal nitride layers. |
| US09691703B2 |
Bond pad structure with dual passivation layers
A bond pad structure with dual passivation layers is disclosed. The bond pad structure includes: a pad material layer on a first passivation layer; a protection layer on the top surface of the pad material layer; a second passivation layer covering on the first passivation layer and the protection layer; and an opening formed through the second passivation layer and the protection layer to expose the pad material layer. |
| US09691702B2 |
Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates
In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114′) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided. |
| US09691699B2 |
Circuit structure and method for manufacturing the same
A method for manufacturing a circuit structure is described as follows. Two patterned circuit layers are formed on a core layer. The patterned circuit layers are located on two opposite surfaces of the core layer. A patterned insulating layer is respectively formed on each of the patterned circuit layers. The patterned insulating layers respectively expose a portion of the patterned circuit layers. The core layer is removed so as to expose an upper surface of each of the patterned circuit layers and a top surface of each of the patterned insulating layers. The upper surface of each of the patterned circuit layers is aligned with the top surface of each of the patterned insulating layers. |
| US09691696B2 |
Interposers with circuit modules encapsulated by moldable material in a cavity, and methods of fabrication
Stacked dies (110) are encapsulated in an interposer's cavity (304) by multiple encapsulant layers (524) formed of moldable material. Conductive paths (520, 620.3) connect the dies to the cavity's bottom wall (304B) and, through TSVs passing through the bottom wall, to a conductor below the interposer. The conductive paths can be formed in segments each of which is formed in a through-hole (514) in a respective encapsulant layer. Each segment can be formed by electroplating onto a lower segment; the electroplating current can be provided from below the interposer through the TSVs and earlier formed segments. Other features are also provided. |
| US09691694B2 |
Substrate comprising stacks of interconnects, interconnect on solder resist layer and interconnect on side portion of substrate
An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal. |
| US09691684B2 |
Integrated circuit device including through-silicon via structure and decoupling capacitor and method of manufacturing the same
An integrated circuit device is provided which includes a through-silicon via (TSV) structure and one or more decoupling capacitors, along with a method of manufacturing the same. The integrated circuit device may include a semiconductor structure including a semiconductor substrate, a TSV structure passing through the semiconductor substrate, and a decoupling capacitor formed in the semiconductor substrate and connected to the TSV structure. The TSV structure and the one or more decoupling capacitors may be substantially simultaneously formed. A plurality of decoupling capacitors may be disposed within a keep out zone (KOZ) of the TSV structure. The plurality of decoupling capacitors may have the same or different widths and/or depths. An isopotential conductive layer may be formed to reduce or eliminate a potential difference between different parts of the TSV structure. |
| US09691682B2 |
Optoelectronic semiconductor component having an electrically insulating element
An optoelectronic semiconductor component includes an optoelectronic thin-film chip; and a thermally conductive and electrically insulating element, wherein both the thin-film chip and the element are embedded in a molded body, a top surface of the thin-film chip and a bottom surface of the element are not covered by the molded body, the top surface of the thin-film chip is approximately flush with a top surface of the molded body, the bottom surface of the element is approximately flush with a bottom surface of the molded body, the molded body includes a first embedded conductor structure and a second embedded conductor structure, and the first conductor structure and the second conductor structure extends to the bottom surface of the molded body. |
| US09691681B2 |
Laser drilling encapsulated semiconductor die to expose electrical connection therein
A method of making an integrated circuit package that contains a semiconductor die having one or more electrical connections to an electronic circuit within the semiconductor die. The method may include: encapsulating the semiconductor die and its electrical connections in non-electrically conductive, encapsulation material; laser drilling the encapsulation material to expose one of the electrical connections within the integrated circuit package, thereby creating a via opening in an external surface of the encapsulation material to the electrical connection; and electroplating or sputtering over the via opening in the encapsulation material to create a conductive routing layer from the exterior surface of the encapsulation material to the electrical connection. |
| US09691680B2 |
Structured substrate
A structured substrate configured for epitaxial growth of a semiconductor layer thereon is provided. Structures can be formed on a side of the structured substrate opposite that of the growth surface for the semiconductor layer. The structures can include cavities and/or pillars, which can be patterned, randomly distributed, and/or the like. The structures can be configured to modify one or more properties of the substrate material such that growth of a higher quality semiconductor layer can be obtained. |
| US09691676B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a first semiconductor chip including a first surface and a plurality of first electrodes disposed on the first surface; a second semiconductor chip including a second surface which faces the first surface, a plurality of second electrodes each of which includes at least one end disposed on the second surface, and a plurality of first protrusions each of which surrounds the one end of each of the second electrodes on an electrode by electrode basis; a plurality of conductive joint materials each of which joins a third electrode included in the first electrodes to the one end of an electrode which faces the third electrode among the second electrodes; and a plurality of first underfill resins each of which is disposed inside one of the first protrusions and covers one of the conductive joint materials on a material by material basis. |
| US09691675B1 |
Method for forming an electrical device and electrical devices
A method for forming an electrical device includes attaching a semiconductor die on a carrier. The method further includes dispensing a fillet material at at least one edge of the semiconductor die arranged on the carrier. The method further includes dispensing an underfill material into a gap between the semiconductor die and the carrier after dispensing the fillet material. |
| US09691672B1 |
Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one GATE-short-related failure mode, one GATECNT-short-related failure mode, and one metal-short-related failure mode. |
| US09691671B2 |
Test key array
The present invention provides a test key array including a lower conductive pattern, and the lower conductive pattern includes a plurality of first L-shaped traces parallel to each other, an upper conductive pattern, where the upper conductive pattern includes a plurality of second L-shaped traces parallel to each other, the lower conductive pattern crosses to the upper conductive pattern, and a plurality of cross regions are defined between the lower conductive pattern and the upper conductive pattern, and a plurality of conductive plugs, disposed on parts of the cross regions, electrically connecting to the lower conductive pattern and the upper conductive pattern. |
| US09691670B2 |
Manufacturing method of array substrate
An embodiment of the present invention provides a manufacturing method of an array substrate comprising forming a gate detecting pattern on the array substrate with gate lines and common electrode lines formed thereon, the gate detecting pattern being arranged on one side of a pixel region of the array substrate and used to connect all the common electrode lines for pixel units; and performing a short circuit or a open circuit detection, wherein if the difference between a signal received by a receiving terminal for a gate line and a signal transmitted from a transmitting terminal for the gate line is larger than a predetermined detection threshold value, it is determined that short circuit between the gate line and a common electrode line or open circuit in the gate line occurs. |
| US09691668B2 |
Wafer carrier
A wafer carrier comprises a supporting body having an opening therein, wherein said opening in said supporting body has a concave sidewall and a bottom surface in said supporting body which is curved in cross section; a plurality of vertical supporting rods configured to support and contact a wafer received in said opening and to displace said wafer from the bottom surface of the opening in said supporting body; wherein one of said supporting rods has an end for contacting and supporting said wafer; and wherein when viewing from a top view of the wafer carrier, one of said supporting rods has a base lining on the concave sidewall of said opening in said supporting body, a first concave side opposite to the base and two second concave sides connecting the base and the first concave side. |
| US09691666B2 |
Layout architecture for performance improvement
An integrated circuit is provided. The integrated circuit includes a first contact disposed over a first source/drain region, a second contact disposed over a second source/drain region, a polysilicon disposed over a gate, the polysilicon interposed between the first contact and the second contact, a first polysilicon contact bridging the polysilicon and the first contact within an active region, and an output structure electrically coupled to the first polysilicon contact. |
| US09691665B2 |
Semiconductor structure with self-aligned spacers and method of fabricating the same
A method of fabricating a semiconductor with self-aligned spacer includes providing a substrate. At least two gate structures are disposed on the substrate. The substrate between two gate structures is exposed. A silicon oxide layer is formed to cover the exposed substrate. A nitride-containing material layer covers each gate structure and silicon oxide layer. Later, the nitride-containing material layer is etched to form a first self-aligned spacer on a sidewall of each gate structure and part of the silicon oxide layer is exposed, wherein the sidewalls are opposed to each other. Then, the exposed silicon oxide layer is removed to form a second self-aligned spacer. The first self-aligned spacer and the second self-aligned spacer cooperatively define a recess on the substrate. Finally, a contact plug is formed in the recess. |
| US09691664B1 |
Dual thick EG oxide integration under aggressive SG fin pitch
A method of forming a thick oxide layer over fins for EG devices and a thinner oxide layer over fins for SG devices on the same substrate and the resulting device are provided. Embodiments include forming a first set of fins over a first portion of a Si substrate; forming a second set of fins over a second portion of the Si substrate spaced from the first portion; forming an iRAD SiO2 layer over the first and second sets of fins; forming a polysilicon layer over the iRAD SiO2 layer over the first set of fins; forming a radical SiO2 layer over the iRAD SiO2 layer over the second set of fins and over the polysilicon layer; forming a mask over the radical SiO2 layer over the second set of fins; removing the polysilicon layer; and removing the mask and the iRAD SiO2 layer from the first set of fins. |
| US09691662B2 |
Field effect transistors having multiple effective work functions
Selective deposition of a silicon-germanium surface layer on semiconductor surfaces can be employed to provide two types of channel regions for field effect transistors. Anneal of an adjustment oxide material on a stack of a silicon-based gate dielectric and a high dielectric constant (high-k) gate dielectric can be employed to form an interfacial adjustment oxide layer contacting a subset of channel regions. Oxygen deficiency can be induced in portions of the high-k dielectric layer overlying the interfacial adjustment oxide layer by deposition of a first work function metallic material layer and a capping layer and a subsequent anneal. Oxygen deficiency can be selectively removed by physically exposing portions of the high-k dielectric layer. A second work function metallic material layer and a gate conductor layer can be deposited and planarized to form gate electrodes that provide multiple effective work functions. |
| US09691660B2 |
Method for forming interconnects
A method of forming an interconnect composed of metallized lines and vias in a workpiece includes forming metal lines in a workpiece, with the metal lines disposed in longitudinally spaced-apart line segments, the line segments spaced apart from each other end-to-end; and forming vias in a workpiece, wherein at least one end of a first formed metal line constrains one cross-sectional dimension of a second formed via, or wherein at least one end of a first formed via constrains one cross-sectional dimension of a second formed metal line. |
| US09691657B2 |
Interconnect wires including relatively low resistivity cores
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1. |
| US09691654B1 |
Methods and devices for back end of line via formation
Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed. |
| US09691652B2 |
Carrier device and ceramic member
A ceramic member, in a carrier device, including: a plurality of ceramic layers; a clamping electrode formed on a first ceramic layer among the plurality of ceramic layers and inside of the plurality of ceramic layers, and configured to attract a dielectric material by electrostatic force; an electric heating element formed on a second ceramic layer, which is more distant from a side holding a carried object than the first ceramic layer among the plurality of ceramic layers, and configured to generate heat using electric power; a power feed port; a land formed on a third ceramic layer among the plurality of ceramic layers, and configured to receive electric power through the power feed port; and a via arranged to pass through at least one of the plurality of ceramic layers and provided as a conductive material to electrically connect the electric heating element with the land. |
| US09691645B2 |
Bolted wafer chuck thermal management systems and methods for wafer processing systems
A workpiece holder includes a puck, first and second heating devices in thermal communication with respective inner and outer portions of the puck, and a thermal sink in thermal communication with the puck. The first and second heating devices are independently controllable, and the first and second heating devices are in greater thermal communication with the puck, than thermal communication of the thermal sink with the puck. A method of controlling temperature distribution of a workpiece includes flowing a heat exchange fluid through a thermal sink to establish a reference temperature to a puck, raising temperatures of radially inner and outer portions of the puck to first and second temperatures greater than the reference temperature, by activating respective first and second heating devices disposed in thermal communication with the radially inner and outer portions of the puck, and placing the workpiece on the puck. |
| US09691644B2 |
Supporting unit, substrate treating device including the same, and method of manufacturing the supporting unit
Provided is a supporting unit. The supporting unit includes: a supporting plate including a substrate on a top surface thereof; and a heater having a predetermined pattern at a bottom surface of the supporting plate and heating the supporting plate, wherein the heater includes: a first metal plating layer applied on the bottom surface of the supporting plate along the predetermined pattern; an anti-oxidation layer of a conductive material applied on the first metal plating layer along the predetermined pattern; and a second metal plating layer of a conductive material applied on the anti-oxidation layer in a portion of the pattern. |
| US09691643B2 |
Etching apparatus
An etching apparatus includes a controller configured to control a high frequency power supply to supply a high frequency power to a mounting table for etching a polymer layer formed on a base layer placed on the mounting table, using plasma generated from a predetermined gas supplied from a gas supply source by the high frequency power, the polymer layer having a periodic pattern of a first polymer and a second polymer formed by self-assembling the first polymer and the second polymer of a block copolymer that is capable of being self-assembled, the high frequency power being set for etching the polymer layer using the generated plasma such that the second polymer is removed and a pattern of the first polymer is formed for subsequently etching the base layer using the pattern of the first polymer as a mask. |
| US09691642B2 |
Device for measuring undulation of brake disc in railway wheel with brake discs
A device for measuring undulation of a brake disc in a railway wheel with brake discs includes a wheel support supporting a hub's bore of the railway wheel; a first displacement gauge for measuring a height displacement of the brake disc frictional surface for one round to follow rotation of the wheel support; and a second displacement gauge for measuring a height displacement of a railway wheel rim surface for one round to follow rotation of the wheel support. A computing unit calculates a difference between maximum and minimum values of the height displacement of the frictional surface by acquiring measurement data from the first displacement gauge, calculates a difference between the maximum and minimum values of the height displacement of the rim's surface by acquiring measurement data from the second displacement gauge, and derives a difference between the both calculated differences as brake disc undulation. |
| US09691637B2 |
Method for packaging an integrated circuit device with stress buffer
A method of fabricating a plurality of semiconductor devices includes attaching a plurality of integrated circuit (IC) die to a substrate including forming electric connections between contacts on the IC die and contacts on the substrate. After the IC die is attached to the substrate, a first encapsulating material is placed over stress-sensitive areas of the IC die. The first encapsulating material includes thirty percent or less of filler particles greater than a specified size. A second encapsulating material is placed over the first encapsulating material. The second encapsulating material includes sixty percent or more of filler particles. |
| US09691632B2 |
Epitaxial wafer and a method of manufacturing thereof
An epitaxial wafer comprises a silicon substrate wafer having first and second sides, and a silicon epitaxial layer deposited on the first side, and optionally one or more additional epitaxial layers on top of the silicon epitaxial layer, at least one of the silicon epitaxial layer or at least one of the one or more additional epitaxial layers being doped with nitrogen at a concentration of 1×1016 atoms/cm3 or more and 1×1020 atoms/cm3 or less. The epitaxial wafer is produced by depositing the silicon epitaxial layer and/or at least one of the one or more additional epitaxial layers, at a deposition temperature of 940° C. or less through chemical vapor deposition in the presence of a deposition gas atmosphere containing one or more silicon precursor compounds and one or more nitrogen precursor compounds. |
| US09691627B2 |
Methods of forming semiconductor devices using auxiliary layers for trimming margin
A method of fabricating a semiconductor device includes forming a linear preliminary mask pattern in a first direction on a substrate. The preliminary mask pattern is patterned to provide a plurality of mask patterns that are aligned end-to-end with one another on the substrate and are separated by an exposed portion of the substrate between respective facing ends of the plurality of mask patterns. An auxiliary layer is formed to cover at least sidewalls of the facing ends to reduce a size of the exposed portion to provide a reduced exposed portion of the substrate and the reduced exposed portion of the substrate is etched to form a trench defining active patterns in the substrate aligned end-to-end with one another. |
| US09691624B2 |
Method for manufacturing fin structure
Provided is a method for manufacturing a fin structure. The method may include forming an initial fin on a substrate, forming a dielectric layer on the substrate to cover the initial fin, planarizing the dielectric layer by sputtering, and further etching the dielectric layer back to expose a portion of the initial fin, wherein the exposed portion serves as a fin. |
| US09691623B2 |
Semiconductor structures having low resistance paths throughout a wafer
A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path. |
| US09691622B2 |
Pre-fill wafer cleaning formulation
A pre-fill solution for application onto a substrate surface prior to a fill operation is provided, the fill operation defined by application of an electroless deposition solution onto the substrate surface to deposit a metallic material in an etched feature, the substrate surface having metallic contaminants generated from an etch operation that generated the etched feature in the substrate surface, the pre-fill solution effective for preventing the electroless deposition solution from depositing on the metallic contaminants, the pre-fill solution comprising: a surfactant, the surfactant configured to enhance wetting of the substrate surface, the concentration of the surfactant in the solution being approximately in the range of 10 ppm to 2000 ppm, wherein the surfactant is an amphoteric surfactant; oxalic acid dihydrate; and hypophosphorous acid as a pH adjusting agent configured to reduce the pH of the solution to approximately less than 2 during the application onto the substrate surface. |
| US09691621B2 |
Silicide region of gate-all-around transistor
The disclosure relates to a semiconductor device and methods of forming same. A representative structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate having a channel region disposed between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprise a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region. |
| US09691614B2 |
Methods of forming different sized patterns
A method includes forming a template portion to provide a first opening trench portion surrounding a first isolated pattern, and forming an array of pillars on an underlying layer; forming a separation wall layer including first separation wall portions surrounding sidewalls of the pillars, and forming second separation wall portions covering sidewalls of the first opening trench portion; forming a block copolymer layer on the separation wall layer; forming first domains in gaps between the pillars, and forming second domains surrounding and separating the first domains by annealing the block copolymer layer; forming second openings by selectively removing the first domains; forming third openings between the second openings, and forming a fourth opening adjacent to the first isolated pattern by selectively removing the pillars and the template portion; and forming fifth openings, which extend from the second and third openings and penetrate the underlying layer, and forming a sixth opening, which extends from the fourth opening and penetrates the underlying layer. |
| US09691612B2 |
Process for preparing graphene on a SiC substrate based on metal film-assisted annealing
Provided is a process for preparing graphene on a SiC substrate, based on metal film-assisted annealing, comprising the following steps: subjecting a SiC substrate to a standard cleaning process; placing the cleaned SiC substrate into a quartz tube and heating the quartz tube up to a temperature of 750 to 1150° C.; introducing CCl4vapor into the quartz tube to react with SiC for a period of 20 to 100 minutes so as to generate a double-layered carbon film, wherein the CCl4 vapor is carried by Ar gas; forming a metal film with a thickness of 350 to 600 nm on a Si substrate by electron beam deposition; placing the obtained double-layered carbon film sample onto the metal film; subsequently annealing them in an Ar atmosphere at a temperature of 900 to 1100° C. for 10-30 minutes so as to reconstitute the double-layered carbon film into double-layered graphene; and removing the metal film from the double-layered graphene, thereby obtaining double-layered graphene. Also provided is double-layered graphene prepared by said process. |
| US09691605B2 |
Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer. |
| US09691598B2 |
Ionizer and mass spectrometer including first section for ionizing sample under atmospheric pressure while vaporizing or desorbing the sample component and second section for generating corona discharge
In the ionizer of the present invention, a stream of gas spouted from a nozzle (18) of a DART ionization unit (10) vaporizes and ionizes the components in a sample (25). Gaseous sample-component molecules which have not been ionized by that process are subsequently ionized by a reaction with a reactant ion produced by a corona discharge generated from a needle electrode (20). Such a two-stage ionization of the sample-component molecules improves the ionization efficiency. A needle-electrode support mechanism (21) adjusts the position and/or angle of the needle electrode (20) and thereby controls a potential gradient. Therefore, a specific sample-derived ion species can be efficiently introduced into an ion introduction tube (31) and be detected with a high level of sensitivity. |
| US09691595B2 |
Modulation of instrument resolution dependant upon the complexity of a previous scan
Systems and methods are used to analyze a sample using variable detection scan resolutions. A tandem mass spectrometer is instructed to perform at least two scans of a sample with different detection scan resolutions using a processor. The tandem mass spectrometer includes a mass analyzer that allows variable detection scan resolutions. The selection of the different detection scan resolutions can be based on one or more properties of sample compounds. The properties may include a sample compound molecular weight distribution that is calculated from a molecular weight distribution of expected compounds or is determined from a list of molecular weights for one or more known compounds. The tandem mass spectrometer can also be instructed to perform an analysis of the sample before instructing the tandem mass spectrometer to perform the at least two scans of the sample. |
| US09691592B2 |
Plasma source enhanced with booster chamber and low cost plasma strength sensor
A method to improve plasma discharge efficiency by attaching one or more booster chambers to the main discharge chamber is disclosed here. The booster chamber functions as a plasma discharge amplification device for the main discharge chamber. It improves plasma density significantly, especially at pressure below 50 mTorr. Compared with traditional inductively coupled plasma (ICP) source, the strength of the plasma source enhanced with booster chamber has been improved several folds at low pressure conditions. Booster chamber can also be used as a convenient high speed plasma etching and deposition processing chamber for small samples. A method to gauge plasma strength by measuring plasma emission intensity has also been disclosed in this application. |
| US09691591B2 |
Plasma processing apparatus
The microwave plasma processing apparatus includes a power feeding rod that applies high frequency wave for RF bias, the upper end of which is connected to a susceptor, and the lower end of which is connected to a high frequency output terminal of a matcher in a matching unit; a cylindrical external conductor that encloses around the power feeding rod serving as an internal conductor; and a coaxial line. The coaxial line is installed with a choke mechanism configured to block undesired microwave that enters the line from a plasma producing space in a chamber, and leakage of the microwave to an RF feeding line is prevented in the middle of the line, thereby suppressing the microwave leakage. |
| US09691586B2 |
Apparatus of plural charged-particle beams
A multi-beam apparatus for observing a sample with high resolution and high throughput is proposed. In the apparatus, a source-conversion unit changes a single electron source into a virtual multi-source array, a primary projection imaging system projects the array to form plural probe spots on the sample, and a condenser lens adjusts the currents of the plural probe spots. In the source-conversion unit, the image-forming means is on the upstream of the beamlet-limit means, and thereby generating less scattered electrons. The image-forming means not only forms the virtual multi-source array, but also compensates the off-axis aberrations of the plurality of probe spots. |
| US09691584B1 |
Ion source for enhanced ionization
An ion source having improved life is disclosed. In certain embodiments, the ion source is an IHC ion source comprising a chamber, having a plurality of electrically conductive walls, having a cathode which is electrically connected to the walls of the ion source. Electrodes are disposed on one or more walls of the ion source. A bias voltage is applied to at least one of the electrodes, relative to the walls of the chamber. In certain embodiments, fewer positive ions are attracted to the cathode, reducing the amount of sputtering experienced by the cathode. Advantageously, the life of the cathode is improved using this technique. In another embodiment, the ion source comprises a Bernas ion source comprising a chamber having a filament with one lead of the filament connected to the walls of the ion source. |
| US09691583B2 |
Imaging and processing for plasma ion source
Applicants have found that energetic neutral particles created by a charged exchange interaction between high energy ions and neutral gas molecules reach the sample in a ion beam system using a plasma source. The energetic neutral create secondary electrons away from the beam impact point. Methods to solve the problem include differentially pumped chambers below the plasma source to reduce the opportunity for the ions to interact with gas. |
| US09691581B2 |
Fuse arrangement
A fuse arrangement includes a first safety fuse and a second safety fuse connected electrically in parallel with each other. The fuse arrangement also includes an end plate mechanically coupled to the first and second safety fuses to form a structural unit so that both safety fuses must be inserted/removed to/from an electrical power distribution installation at the same time. Furthermore, the electrical parallel connection of the two safety fuses, rather than a single relatively larger safety fuse, may allow the maximum current strength of an electrical power distribution installation to be maintained while the current is split between the two safety fuses so the size of the fuse arrangement may be reduced. |
| US09691579B2 |
Package MEMS switch and method
An electronic device and methods including a switch formed in a chip package are shown. An electronic device and methods including a switch formed in a polymer based dielectric are shown. Examples of switches shown include microelectromechanical system (MEMS) structures, such as cantilever switches and/or shunt switches. |
| US09691570B1 |
Modular tactile switch
Modular button components are described that comprise a tactile switch coupled to a center portion of the modular button component and at least one electrical contact. A bracket extends beyond a length of the center portion of the modular component. In various embodiments, the tactile switch, the bracket and the at least one electrical contact are insert molded into a single assembly to form the modular button component that is detachably coupled to a printed circuit board. |
| US09691569B2 |
Light-transmissible keycap and manufacturing method thereof
A light-transmissible keycap and the manufacturing method thereof are provided. The light-transmissible keycap has multiple light-transmissible symbol areas, and each light-transmissible symbol area has at least one character assigned with a color. Each light-transmissible symbol area is covered with only one light-transmissible color layer. Thus, when an external light is emitted from a light source beneath the keycap, the external light will only pass through one light-transmissible color layer covering that light-transmissible symbol area, and not pass through the light-transmissible color layer covering the other light-transmissible symbol area. Therefore, a bleeding problem due to multiple light-transmissible color layers overlapped and covering the same light-transmissible symbol area is avoided. |
| US09691564B2 |
Mounting plate
A mounting plate is disclosed for supporting a circuit breaker accessory part. In an embodiment, the mounting plate includes a holding device, configured to hold the mounting plate on a wall of a housing of a circuit breaker and a fastening device, configured to fasten the circuit breaker accessory part to the mounting plate. |
| US09691563B2 |
Operation unit
An operation unit includes an operation part that is provided to be movable up and down along a movement axis, functions as a push-button switch at a first position, and functions as a joystick lever at a second position above the first position in the movement axis direction; and an operation part-detecting part that senses pressing of the operation part when the operation part is at the first position, and senses a direction in which the operation part has inclined when the operation part is at the second position. |
| US09691562B2 |
Electric switching device with enhanced Lorentz force bias
An electric switch is disclosed. The electric switch has a first terminal, a second terminal, a contact sub-assembly comprising at least two contact members disposed in a current path between the first and second terminals, the contact sub-assembly having a connecting position in which the contact members contact each other and an interrupting position in which the contact members are spaced apart from each other a Lorentz force generator comprising a first conductor member and a second conductor member, and at least one support Lorentz force generator. The Lorentz force generator and the at least one support Lorentz force generator both bias the contact sub-assembly into the connecting position, the current path extending from the first terminal to the second terminal through the contact sub-assembly in the connecting position. |
| US09691559B2 |
Circuit breaker
A circuit breaker includes: fixed contact points; and a moving contact assembly. The moving contact assembly includes: a shaft; a moving contact that is held in the shaft; and springs that apply torque to the moving contact. The shaft includes: stopping faces that are formed in a direction opposite to the direction in which the moving contact rotates; and guiding faces that are curved from the stopping faces. The moving contact includes: first surfaces that are formed on the radius of rotation of the moving contact; and sliding surfaces that are located at an angle to the first surfaces and slanted toward the center of rotation with respect to the line of action of a tangential force of torque at the points of contact with the guiding faces. |
| US09691548B2 |
High-voltage capacitor
A high-voltage capacitor includes a gas-tight enclosure containing interleaved electrodes. The dielectric of the capacitor is a pressurized gas at a pressure of at least 6 bar, and preferably 10 or 15 bar. In order to withstand this level of internal pressure, the insulating body section of the capacitor may be formed of a high-strength polymeric material. |
| US09691545B2 |
Developing bulk exchange spring magnets
A method of making a bulk exchange spring magnet by providing a magnetically soft material, providing a hard magnetic material, and producing a composite of said magnetically soft material and said hard magnetic material to make the bulk exchange spring magnet. The step of producing a composite of magnetically soft material and hard magnetic material is accomplished by electrophoretic deposition of the magnetically soft material and the hard magnetic material to make the bulk exchange spring magnet. |
| US09691542B2 |
Inductor and display apparatus including the same
An inductor configured to be mounted on a printed circuit board is provided. The inductor includes a drum core including a cylindrical body and first and second flanges extending from opposite ends of the cylindrical body, a coil wound around the cylindrical body, a plurality of pins on which opposite ends of the coil are wound, wherein each of the plurality of pins has one end fixed to the second flange and another end configured to be fixed to the printed circuit board, and at least one projection which protrudes from the second flange and is configured to support the inductor to stand vertically on the printed circuit board. |
| US09691538B1 |
Magnetic devices for power converters with light load enhancers
A magnetic device includes a magnetic core, one or more first windings, and one or more second windings. Each first winding forms a respective first turn around a respective first winding center axis, and each second winding forms a respective second turn around a common second winding center axis that is orthogonal to each first winding center axis. Another magnetic device includes a magnetic core, a plurality of first windings forming respective first winding turns, and a second winding forming a second winding turn. Each first winding turn is within the second winding turn, as seen when the magnetic device is viewed cross-sectionally in a first direction. Yet another magnetic device includes a magnetic core, one or more first windings, and one or more second windings magnetically isolated from the one or more first windings. |
| US09691537B2 |
Power supply module
A power supply module is disclosed. the power supply module includes a coil including a coil body and connecting terminals; an electronic component including at least an integrated circuit chip; a magnetic core configured to enclose in and around the coil body, wherein a recess is provided on at least one side surface of the magnetic core, the electronic components are located in the recess, and an opening is provided on at least one side wall of the recess; a connector configured to be tightly attached to and cover the side surface where the recess is provided, and be electrically connected with the coil and the electronic component; and a heat conducting material provided in the recess and configured to cover the electronic component. |
| US09691535B2 |
Filter device
A filter device is electrically connected between a power supply and a power converter including a converter unit for rectifying inputs and an inverter unit for inversely converting outputs of the converter unit. The filter device includes a casing; a filter reactor housed inside the casing, for removing a high-frequency component; and a booster reactor housed inside the casing and disposed below the filter reactor, for boosting a voltage of a current having passed through the filter reactor. The booster reactor includes an iron core, a coil wound around the iron core, and a spacer interposed between inner and outer circumferential portions of the coil to form an air passage for passing air introduced into the casing. The booster reactor is stored in the casing so that the air that has passed through the air passage passes through a periphery of the filter reactor disposed immediately above the booster reactor. |
| US09691533B2 |
Magnetic circuit
A magnetic circuit, provided with a short magnet and short magnet that are arranged in an array, and a yoke and a yoke provided so as to sandwich the short magnet and short magnet. The short magnet and short magnet, are arranged, that have a space between them that is a predetermined gap or less in the arrangement direction of the array respectively. In addition, the short magnet and short magnet are arranged so that one magnetic pole is located on the side toward one of the pair of yokes and, and the other magnetic pole is located on the side toward the other yoke. |
| US09691531B2 |
Magnet apparatus
A magnet apparatus which comprises a first vacuum chamber, a second vacuum chamber, a first magnet disposed within the first vacuum chamber such that the first magnet can be thermally isolated from the exterior of the first vacuum chamber, and a load connector extending from the first vacuum chamber into the second vacuum chamber so that a load on the first magnet can be transferred to the second vacuum chamber, wherein the load connector is in thermal contact with the first magnet and can be thermally isolated from the exterior of the first vacuum chamber and the exterior of the second vacuum chamber. |
| US09691527B2 |
Shielding structure and wire harness using conductive resin mold and non-metallic fiber braid
A shielding structure includes a conductive resin molded product, and a non-metallic fiber braid which is formed in a tubular shape by using multiple ultrathin strands made of conductive non-metallic fibers. A distal end of the non-metallic fiber braid is welded to the conductive resin molded product in the shielding structure. |
| US09691526B2 |
Method for making carbon nanotube composite film
A method for making carbon nanotube composite film is provided. An original carbon nanotube film includes carbon nanotubes joined end to end by van der Waals attractive force. The carbon nanotubes substantially extend along a first direction. A patterned carbon nanotube film is formed by patterning the original carbon nanotube film to define at least one row of through holes arranged in the original carbon nanotube film along the first direction. Each row of through holes includes at least two spaced through holes. The patterned carbon nanotube film is treated with a polymer solution. The patterned carbon nanotube film is shrunk into the carbon nanotube composite film. |
| US09691522B2 |
Method of making down-hole cable
A system and method for a down-hole cable is provided. The down-hole cable includes an insulated conductor portion. A filler layer abuts and encapsulates the insulated conductor portion, wherein the filler layer is substantially formed with a foamed fluoropolymer. An armor shell is applied to the exterior of the foamed fluoropolymer filler layer. |
| US09691521B2 |
Rectangular insulated wire and electric generator coil
A rectangular insulated wire includes a rectangular conductor having a generally rectangular cross section, a thermosetting resin layer provided to cover the rectangular conductor, and a plurality of thermoplastic resin layers provided on the thermosetting resin layer. An adhesion strength between the thermosetting resin layer and the thermoplastic resin layer is 50 gf/mm to 100 gf/mm. |
| US09691518B2 |
Medical cable
A medical cable includes a plurality of cables, a braided shield covering a circumference of the plurality of cables together and being formed of tubular braided strands, and a jacket covering a circumference of the braided shield. The braided strands includes a copper foil yarn, which includes a highly stretchable polyethylene terephthalate monofilament yarn having a tensile strength of not lower than 700 MPa and an elongation of not lower than 50 percent and not higher than 100 percent, and a copper strip wound helically at a pitch around a surface of the highly stretchable polyethylene terephthalate monofilament yarn. The copper foil yarn has an entire push and recover ratio of not lower than 80 percent. |
| US09691515B2 |
Bus bar assembly comprising a memory metal composition
A power distribution system element formed via an additive manufacturing technique, such as applying a conductive material to a memory metal substrate, are discussed herein. In operation (e.g. in response to delivering current through the distribution system), the memory metal contracts while the conductive material expands. The result is distribution system element having reduced thermal expansion, which can be net zero coefficient of thermal expansion. |
| US09691513B1 |
Pedestal alignment tool for an orienter pedestal of an ion implant device
A pedestal alignment tool for adjusting an orienter pedestal of an ion implant device is provided, wherein the pedestal is configured to orient a wafer prior to implantation in the ion implant device, the pedestal alignment tool comprising supporting elements configured for contacting a surface of the pedestal, a base comprising a top surface and openings for receiving the supporting elements, and adjustment means configured for adjusting lengths of the supporting elements over which the supporting elements protrude from the top surface of the base. |
| US09691510B2 |
Equipment protecting enclosures
Biomass (e.g., plant biomass, animal biomass, and municipal waste biomass) is processed to produce useful intermediates and products, such as energy, fuels, foods or materials. For example, systems and methods are described that can be used to treat feedstock materials, such as cellulosic and/or lignocellulosic materials, in a vault in which the equipment is protected from radiation and hazardous gases by equipment enclosures. The equipment enclosures may be purged with gas. |
| US09691508B2 |
System and method for determining a state of operational readiness of a fuel cell backup system of a nuclear reactor system
A method for determining a state of operational readiness of a fuel cell backup system of a nuclear reactor system includes monitoring a readiness state of a fuel cell system associated with a nuclear reactor system, and providing a readiness determination of the fuel cell system by comparing the monitored state of readiness of the fuel cell system to an established operating readiness state, the established operating readiness state a function of at least one characteristic of the nuclear reactor system. An apparatus includes a fuel cell monitoring system configured to monitor a readiness state of a fuel cell system associated with a nuclear reactor system, and a readiness determination system configured to provide a readiness determination of the fuel cell system by comparing the monitored state of readiness of the fuel cell system to an established operating readiness state. |
| US09691506B2 |
High dielectric insulated coax cable for sensitive impedance monitoring
A boiling water reactor core power level monitoring system includes a desired length of high dielectric, non-linear material insulated coaxial type cable in close proximity to the reactor core and a time domain reflectometry apparatus configured to measure a temporary characteristic impedance change associated with the coaxial type cable in response to at least one of neutron or gamma irradiation generated via the reactor core. |
| US09691505B2 |
Dynamic application of error correction code (ECC) based on error type
Error correction in a memory subsystem includes determining whether an error is a transient error or a persistent error, and adjusting an approach to ECC (error checking and correction) based on error type. The type of error can be determined by a built in self-test. If the error is a persistent error, the memory controller can perform in erasure mode, including correcting an erasure for an identified error location prior to applying an ECC correction algorithm. Otherwise, if the error is transient, the memory controller can perform standard full ECC correction by applying the ECC correction algorithm. |
| US09691503B2 |
Allocation technique for memory diagnostics
An apparatus for allocating computer memory for memory diagnostics is disclosed. The apparatus may include a processor and memory that stores code executable by the processor, and may include code that identifies an unreserved amount of memory in a computer system, code that requests a portion of the memory based on the unreserved amount of memory, and code that determines whether an allocated portion of the memory comprises non-contiguous memory addresses. In some embodiments, the apparatus includes code that locks the allocated portion of the memory in response to the allocated portion consisting solely of contiguous memory addresses, and code that performs a memory diagnostic test on the allocated portion of the memory. |
| US09691497B2 |
Programmable devices with current-facilitated migration and fabrication methods
Programmable devices and fabrication methods thereof are presented. The programmable devices include, for instance, a first electrode and a second electrode electrically connected by a link portion. The link portion includes one material of a metal material or a semiconductor material and the first and second electrodes includes the other material of the metal material or the semiconductor material. For example, the link portion facilitates programming the programmable device by applying a programming current between the first electrode and the second electrode to facilitate migration of the one material of the link portion towards at least one of the first or second electrodes. In one embodiment, the programming current is configured to heat the link portion to facilitate the migration of the one material of the link portion towards the at least one of the first or second electrodes. |
| US09691496B1 |
High density ROM cell with dual bit storage for high speed and low voltage
Disclosed is a ROM memory including a first bitcell including a transistor to store two bits and first and second bit lines to read data stored in the bitcell, a second bitcell including a second transistor connected to the first transistor and sharing the first and second bit lines, and a virtual ground line adjacent the bit lines configured to ground the bitcells. |
| US09691495B2 |
Memory array with RAM and embedded ROM
A memory array with RAM and embedded ROM including multiple RAM cells, a ROM cell, and a ROM enable circuit. Each RAM cell has a RAM cell structure with a first and second power terminals and configured to operate as a RAM cell when the memory array is in a RAM mode. The ROM cell has the same RAM cell structure in which at least one transistor is modified to cause the ROM cell to have a predetermined logic state. The ROM enable circuit enables bit lines of the ROM cell to control supply voltages provided to the power terminals of the RAM cells so that they settle to predetermined logic states in a ROM mode. The modified transistor has a pseudo transistor structure having a modified substrate that operates as a resistance, such as a doping region in the substrate having the same polarity type as the substrate. |
| US09691492B1 |
Determination of demarcation voltage for managing drift in non-volatile memory devices
A predetermined pattern of bits is written to a non-volatile memory device prior to powering down the non-volatile memory device. A plurality of voltages are applied to the non-volatile memory device to determine which voltage of the plurality of voltages allows the predetermined pattern of bits to be read with a least amount of error. The determined voltage is set to be a demarcation voltage for reading from the non-volatile memory device. |
| US09691491B2 |
Methods and apparatus to track bit cell current using temperature and voltage dependent reference currents
An example method to track bit cell current in a memory architecture. An example method disclosed herein includes generating a first reference current dependent on bit cell temperature. The example method includes generating a second reference current dependent on bit cell voltage and supplying a third reference current of constant magnitude. In examples disclosed herein, the example method involves summing the first reference current, the second reference current, and the third reference current. The example method includes determining, with a sense amplifier, a bit cell logic state based on the first reference current, the second reference current, and the third reference current. |
| US09691490B2 |
Semiconductor memory device including dummy memory cells and memory system including the same
The semiconductor memory device includes a memory cell array including a first plurality of normal memory cells and a second plurality of dummy memory cells in a stacked configuration over a substrate, a first plurality of normal word lines electrically coupled to the first plurality of normal memory cells, and a second plurality of dummy word lines electrically coupled to the second plurality of dummy memory cells, wherein the first plurality of normal memory cells includes at least one bad memory cell and each of the at least one bad memory cells are is replaced with a dummy memory cell from among the second plurality of dummy memory cells. |
| US09691489B2 |
Nonvolatile semiconductor memory device with first and second read operations with different read voltages
A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value. |
| US09691485B1 |
Storage system and method for marginal write-abort detection using a memory parameter change
A storage system and method for marginal write-abort detection using a memory parameter change is provided. In one embodiment, a method for detecting a write abort is provided that is performed in a storage system having a memory. The method comprises reading a lower page in memory; determining if any data is written in the lower page; and in response to determining that no data is written in the lower page: increasing source voltage for memory cells in the lower page; re-reading the lower page; determining if a read failure exists in the re-read lower page; and in response to determining that a read failure exists in the re-read lower page, detecting a write abort. Other embodiments are possible, and each of the embodiments can be used alone or together in combination. |
| US09691483B1 |
Content addressable memory with banks
In one aspect, techniques for providing a banked content addressable memory (CAM) with counters are provided. A dictionary word may be divided into a plurality of banks. A counter may be associated with each bank of the plurality of banks. The counter may count the number of times a segment of an input word aligned with the bank does not match. A scheduler may schedule comparison of banks with higher probability of not matching before banks with lower probability of not matching. The probability of not matching may be based on the counters. |
| US09691474B2 |
Memory system
A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code. |
| US09691472B2 |
Non-volatile memory device and method of programming the same
A non-volatile memory device and a method of programming a non-volatile memory device including a plurality of memory cells that are stacked in a vertical direction over a substrate and connected to n word lines, wherein n is an integer greater than or equal to 3. The method includes programming memory cells of second to n−1-th word lines, from among first to n-th word lines that are sequentially disposed in the vertical direction over the substrate, to a multi-level state, wherein a multi-level program operation is sequentially performed from the second to n−1-th word lines in an order in which the word lines are disposed; and programming memory cells of the first word line to a single level state after the programming memory cells of the second to n−1-th word lines to a multi-level state. |
| US09691470B1 |
Apparatus and method for restricted range memory calibration
An apparatus and method for a restricted range calibration is disclosed. A system includes a memory coupled to a memory controller. The memory controller is coupled to receive a clock signal, and is configured to operate in different performance states corresponding to different frequencies of the clock signal. The memory controller provides a data strobe signal to synchronize transfers of data to and from the memory. When operating in a first performance state, the memory controller may perform a first calibration of a delay applied to the data strobe signal. Performing the first calibration includes varying the delay over a first range of values. Thereafter, responsive to returning to the first performance state from another performance state, the memory controller may perform a second calibration. The second calibration includes varying the delay over a second range of values that is less than the first range. |
| US09691465B2 |
Thyristors, methods of programming thyristors, and methods of forming thyristors
Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors. |
| US09691462B2 |
Latch offset cancelation for magnetoresistive random access memory
Systems and methods relate to operations on a magnetoresistive random access memory (MRAM) bit cell using a circuit configured in multiple phases. In a sensing circuit phase, the circuit configured to determine a first differential voltage between a data voltage across the bit cell and a reference voltage. In a pre-amplifying phase, the circuit is configured to pre-amplify the first differential voltage to generate a pre-amplified differential voltage, which does not have offset voltages that may arise due to process variations. In a sense amplifier phase, the circuit is configured to amplify the pre-amplified differential voltage in a latch. Generation of the pre-amplified differential voltage cancels offset voltages which may arise in the latch. In a write phase, the circuit is further configured to write a write data value to the MRAM bit cell. |
| US09691459B2 |
Semiconductor memory device including shorted variable resistor element of memory cell
A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected. |
| US09691454B2 |
Memory controller with phase adjusted clock for performing memory operations
In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be. |
| US09691453B1 |
Efficient calibration of memory devices
A system and method for efficient data eye training reduces the time and resources spent calibrating one or more memory devices. A reference voltage (Vref) calibration mechanism reduces the time and resources for calibration by reducing the number of tests needed to sufficiently determine the boundaries of the data eye of the memory device by using a combination of small steps and small steps to find a preferred reference voltage. In one example, the Vref calibration mechanism uses small steps of the reference voltage in a first range above a nominal reference voltage to find a maximum eye width then uses small steps to more precisely find the maximum eye width. If a maximum reference voltage is found in the first range then the second range below the nominal reference voltage does not need to be tested thereby saving additional time and resources. |
| US09691451B1 |
Write assist circuit and method therefor
A circuit includes a first driver to provide a first driver signal at an output. The first driver signal corresponds to a voltage operatively coupled to a VSS terminal of the first driver when driving a logic low. A first capacitor includes a first terminal coupled to the VSS terminal of the first driver. A boost circuit includes a first input coupled to the output of the first driver and a first output coupled to a second terminal of the first capacitor. The boost circuit is configured to cause the first capacitor to provide a boosted voltage at the VSS terminal. |
| US09691450B1 |
Storage method and apparatus for random access memory using codeword storage
A memory circuit, such as an embedded DRAM array, stores information as groups of bits or data using information coding in storage and retrieval data, instead of each bit being stored separately. Write data words can be mapped to storage format words that are stored and defined by a Hadamard matrix. The storage format word is stored as charge levels in an addressable memory location. For retrieving stored data, charge levels are read from the storage cells and interpreted to a valid storage format word. Hadamard code maximal likelihood decoding can be used to derive a read data word corresponding to a previously written write data word. The write data word is then output as the result of a read of the selected addressable location, or a portion thereof. The mapping can be two or more Hadamard matrix mappings concatenated for each of a plurality of storage format words. |
| US09691444B2 |
Buffer die in stacks of memory dies and methods
Memory devices and methods of making and operating them are shown. Memory devices shown include stacked memory dies with one or more buffer dies included. In one such memory device, a command die communicates with one or more downstream memory dies through the one or more buffer dies. The one or more buffer dies function to repeat signals, and can potentially improve performance for higher numbers of memory dies in the stack. |
| US09691443B2 |
Apparatuses and methods for compensating for process, voltage, and temperature variation in a memory
Systems and methods are described for compensating for variations in process, voltage, temperature, or combinations thereof in an apparatus. An example apparatus may be a memory circuit. A pre-driver circuit and driver circuit may be associated with the memory circuit. A reference generator may provide the pre-driver circuit with reference signals that are insensitive to process, voltage, and temperature. The pre-driver circuit may receive the reference signals and the pre-driver circuit output ramping rate may then be made less sensitive to variations in process, voltage, and temperature. The pre-driver circuit output may then be supplied to a driver circuit that may then output a final driver data output with reduced noise. |
| US09691442B2 |
Memory device with reduced on-chip noise
In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device. |
| US09691436B2 |
Top cover and disk drive apparatus
A case of a disk drive apparatus includes a housing in which a disk is accommodated, and a top cover arranged to close an opening of the housing. The top cover includes a top cover body and a flow control member. The top cover body is a plate-shaped member arranged to extend perpendicularly to a central axis. The flow control member is fixed to a lower surface of the top cover body. The flow control member includes a lower surface arranged axially opposite to at least a portion of an upper surface of the disk. |
| US09691433B2 |
Medical image diagnosis apparatus and medical image proccessing apparatus
A medical image diagnosis apparatus including an image collection system that collects first dynamic images extending over a first period and a display control circuit that uses the first dynamic images and time information related to an image corresponding to a first predetermined time phase in the first period to simultaneously display the first dynamic images, the first predetermined time phase, and a relationship of the image currently displayed with a time phase in the first period at least in a predetermined period going back from the predetermined time phase in a monitor. |
| US09691425B2 |
Laminating magnetic cores for on-chip magnetic devices
A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer. |
| US09691422B1 |
Slider air-bearing surface designs with efficiency-flattening hole
Disclosed herein are hard disk drive sliders having an air-bearing surface (ABS) with an efficiency-flattening hole (EFH). The sliders comprise a trailing edge pad that has a first surface at a first level with a first perimeter, a second surface at a second level, the second level being below the first level, the second surface being substantially parallel to the first surface, the second surface having a second perimeter, wherein the second perimeter is within the first perimeter, and a third surface at a third level, the third level being below the second level, the third surface being substantially parallel to the first and second surfaces, the third surface having a third perimeter, wherein the third perimeter is within the second perimeter. |
| US09691421B2 |
Writing spirals with accurate slope on a disk drive media
A reference spiral is written on a recording surface of a magnetic storage disk that is free of position or timing information. The reference spirals are written on the recording surface with a substantially uniform slope by using open loop control of the position of a read/write head in conjunction with an iterative learning control scheme. A voltage profile applied to a voice coil motor is adapted over multiple iterations of moving the read/write head across the recording surface to closely approximate a target voltage profile, and the reference spiral is written using the adapted voltage profile. In addition, ramp contact detection based on actuator current profile may be employed to achieve full utilization of available actuator stroke. |
| US09691419B1 |
ESD protection surface charge control recording head
Electrostatic discharge protection can be afforded to a data recording head in accordance with various embodiments. A data recording head may consist of a circuit having a preamp ground connected to a ground substrate via a ground trace. The ground trace can consist of a first leg connected to the ground substrate and a second leg with an open connection extending from a dice line. |
| US09691418B1 |
Adaptive write fault thresholds
Systems and methods for determining a relationship between write fault threshold and temperature are described. The systems and methods include measuring an operating temperature of the storage device, determining a current operating temperature of the storage device, determining whether the current operating temperature of the storage device satisfies a temperature threshold, and upon determining the current operating temperature of the storage device satisfies the temperature threshold, modifying a write fault threshold associated with a data track of the storage device. |
| US09691416B1 |
Microwave assisted magnetic recording head with trailing shield heat sink
A magnetic write head having a heat sink structure located adjacent to a trailing magnetic shield. The heat sink structure prevents heat generated by the magnetic oscillator current from causing damage to and reducing reliability of the magnetic write head. The trailing magnetic shield is substantially aligned with the magnetic oscillator, allowing the heat sink structure to wrap around the sides and back of the trailing magnetic shield and to provide good heat conduction away from the write pole, magnetic oscillator and trailing magnetic shield. The heat sink structure can be constructed of a material such as Ru, TiN, Cu, Au, Ag and AlN, and is preferably constructed of Au, which has excellent thermal properties. |
| US09691414B1 |
Tape head with narrow skiving edges fitted to transducers
A tape head includes a body, which includes a transducer. The transducer may be a read or write element, respectively configured so as for the tape head to read from or write to a tape, in operation. The body exhibits a tape-bearing surface, which is typically configured to face and interact with the tape, in operation. The tape head further includes a closure. The closure is fixed on a leading side or a trailing side of the body and includes a skiving edge vis-à-vis the transducer. The skiving edge is adjoined by non-skiving edges. Finally, the closure has a top surface that meets the skiving edge; the top surface is level with the tape-bearing surface. Also included are related devices; tape head apparatuses for recording and/or reproducing tapes, comprising such tape heads; and methods of fabrication thereof. |
| US09691413B2 |
Identifying sound from a source of interest based on multiple audio feeds
Methods and systems for identifying sound from a source of interest are provided for herein. In some embodiments, a first audio feed is captured by a first microphone and a second audio feed is captured by a second microphone. The first microphone may be located closer in proximity to the source of interest than the second microphone. The first audio feed can be processed utilizing the second audio feed to produce a first processed audio feed that can enable identification of sound originating from the source of interest. In some embodiments, the second audio feed can be additionally processed utilizing the first audio feed to produce a second processed audio feed. In such embodiments, frequencies from the first processed audio feed can be compared against frequencies of the second processed audio feed to identify sound originating from the source of interest. Other embodiments may be described and/or claimed herein. |
| US09691412B2 |
Conferencing system and method for controlling the conferencing system
A communication system and a method can be configured to facilitate the performance of a conference. The system can include a conference organizer terminal and at least two participants' terminals each assigned to respective conference participants who each log in to start a conference on the communication system. The communication system can be configured to calculate a decision situation at a particular point in time of the ongoing conference by analyzing the views expressed by the conference participants during the conference and send data relating to the decision situation for that point in time to the conference organizer's terminal and/or other conference participant terminals for use in facilitating the conference. IN some embodiments, such data can be used to assist the conference participants' in recognizing when there is a consensus made on at least one decision to be made during the conference. |
| US09691410B2 |
Frequency band extending device and method, encoding device and method, decoding device and method, and program
The present invention relates to a frequency band extending device and method, an encoding device and method, a decoding device and method, and a program, whereby music signals can be played with higher sound quality due to the extension of frequency bands.A bandpass filter 13 divides an input signal into multiple sub-band signals, a feature amount calculating circuit 14 calculates feature amount using at least one of the multiple divided sub-band signals and the input signal, a high frequency sub-band power estimating circuit 15 calculates an estimated value of a high frequency sub-band power based on the calculated feature amount, a high frequency signal generating circuit 16 generates a high frequency signal component based on the multiple sub-band signals divided by the bandpass filter 13, and the estimated value of the high frequency sub-band power calculated by the high frequency sub-band power estimating circuit 15. A frequency band extending device 10 extends the frequency band of the input signal using a high frequency signal component. The present invention may be applied to a frequency band extending device, for example. |
| US09691406B2 |
Method for encoding audio signals, apparatus for encoding audio signals, method for decoding audio signals and apparatus for decoding audio signals
The invention introduces a new concept for hierarchical coding of HOA content. A method for encoding a hierarchical audio bitstream comprises rendering a HOA input signal to surround sound, encoding the surround sound for a base layer output signal, decoding the encoded surround sound to obtain a reconstructed surround sound signal, performing dimensionality reduction on the received HOA input signal, calculating a residual between the dimensionality-reduced HOA signal and the reconstructed surround sound signal, encoding the residual signal, and multiplexing structural information about the HOA input signal, the encoded residuals and the encoded surround sound into a bitstream to obtain a hierarchical audio bitstream. |
| US09691402B1 |
Spectral translation/folding in the subband domain
The present invention relates to a new method and apparatus for improvement of High Frequency Reconstruction (HFR) techniques using frequency translation or folding or a combination thereof. The proposed invention is applicable to audio source coding systems, and offers significantly reduced computational complexity. This is accomplished by means of frequency translation or folding in the subband domain, preferably integrated with spectral envelope adjustment in the same domain. The concept of dissonance guard-band filtering is further presented. The proposed invention offers a low-complexity, intermediate quality HFR method useful in speech and natural audio coding applications. |
| US09691397B2 |
Device and method data for embedding data upon a prediction coding of a multi-channel signal
A device for embedding data upon a prediction coding of a multi-channel signal includes a storage unit to store a code book that includes a plurality of prediction parameter sets, each of the plurality of prediction parameter sets including a plurality of kinds of prediction parameters for a processing regarding the prediction coding. The device extracts a plurality of candidates of a prediction parameter set for the multi-channel signal from the code book, wherein the plurality of candidates are capable of suppressing a prediction error in the prediction coding within a predetermined range, converts an embedding object that is at least part of the data in accordance with a number corresponding to a number of the candidates, selects, from the plurality of candidates, the prediction parameter set corresponding to the converted embedding object, and multiplexes the selected prediction parameter set with coded data which are down-mixed from the multi-channel signal. |
| US09691396B2 |
Speech/audio signal processing method and apparatus
The present invention discloses a speech/audio signal processing method and apparatus. In an embodiment, the speech/audio signal processing method includes: when a speech/audio signal switches bandwidth, obtaining an initial high frequency signal corresponding to a current frame of speech/audio signal; obtaining a time-domain global gain parameter of the initial high frequency signal; performing weighting processing on an energy ratio and the time-domain global gain parameter, and using an obtained weighted value as a predicted global gain parameter, where the energy ratio is a ratio between energy of a historical frame of high frequency time-domain signal and energy of a current frame of initial high frequency signal; correcting the initial high frequency signal by using the predicted global gain parameter, to obtain a corrected high frequency time-domain signal; and synthesizing a current frame of narrow frequency time-domain signal and the corrected high frequency time-domain signal and outputting the synthesized signal. |
| US09691395B1 |
System and method for taxonomically distinguishing unconstrained signal data segments
A system and method are provided for taxonomically distinguishing grouped segments of signal data captured in unconstrained manner for a plurality of sources. The system comprises a vector unit constructing for each of the grouped signal data segments at least one vector of predetermined form. A sparse decomposition unit selectively executes in at least a training system mode a simultaneous sparse approximation upon a joint corpus of vectors for a plurality of signal segments of distinct sources. The sparse decomposition unit adaptively generates at least one sparse decomposition for each vector with respect to a representative set of decomposition atoms. A discriminant reduction unit executes during the training system mode to derive an optimal combination of atoms from the representative set. A classification unit executes in a classification system mode to discover for an input signal segment a degree of correlation relative to each of the distinct sources. |
| US09691393B2 |
Voice print identification for identifying speakers at an event
Voice print identification for identifying speakers at an event is provided. A plurality of speakers at an event are recorded and associated with identity indicators. Voice prints for each speaker are associated with each of the plurality of recorded speakers. Determining based on the event, the list of attendees for the event, and the identity indicators, whether the voice print for at least one speaker corresponds to a known. |
| US09691391B2 |
Clustering of audio files using graphs
Systems and methods to perform speaker clustering determine which audio segments appear to include sound generated by the same speaker. Speaker clustering is based on creating a graph in which a node represents an audio segment and an edge between two nodes represents a relationship and/or correspondence that reflects a probability, likelihood, or other indication that the two nodes represent audio segments of the same speaker. This graph is analyzed to detect individual communities of nodes that associate to an individual speaker. |
| US09691390B2 |
System and method for performing dual mode speech recognition
A system and method is presented for performing dual mode speech recognition, employing a local recognition module on a mobile device and a remote recognition engine on a server device. The system accepts a spoken query from a user, and both the local recognition module and the remote recognition engine perform speech recognition operations on the query, returning a transcription and confidence score, subject to a latency cutoff time. If both sources successfully transcribe the query, then the system accepts the result having the higher confidence score. If only one source succeeds, then that result is accepted. In either case, if the remote recognition engine does succeed in transcribing the query, then a client vocabulary is updated if the remote system result includes information not present in the client vocabulary. |
| US09691384B1 |
Voice action biasing system
Methods, systems, and apparatus for determining that a software application installed on a user device is compatible with a new voice action, wherein the new voice action is specified by an application developer of the software application. One or more trigger terms for triggering the software application to perform the new voice action are identified. An automatic speech recognizer is biased to prefer the identified trigger terms of the new voice action over trigger terms of other voice actions. A transcription of an utterance generated by the biased automatic speech recognizer is obtained. The transcription of the utterance generated by the biased automatic speech recognizer is determined to include a particular trigger term included in the identified trigger terms. Based at least on determining that the transcription of the utterance generated by the biased automatic speech recognizer includes the particular trigger term, execution of the new voice action is triggered. |
| US09691383B2 |
Multi-tiered voice feedback in an electronic device
This invention is directed to providing voice feedback to a user of an electronic device. Because each electronic device display may include several speakable elements (i.e., elements for which voice feedback is provided), the elements may be ordered. To do so, the electronic device may associate a tier with the display of each speakable element. The electronic device may then provide voice feedback for displayed speakable elements based on the associated tier. To reduce the complexity in designing the voice feedback system, the voice feedback features may be integrated in a Model View Controller (MVC) design used for displaying content to a user. For example, the model and view of the MVC design may include additional variables associated with speakable properties. The electronic device may receive audio files for each speakable element using any suitable approach, including for example by providing a host device with a list of speakable elements and directing a text to speech engine of the host device to generate and provide the audio files. |
| US09691377B2 |
Method and device for voice recognition training
A method on a mobile device for voice recognition training is described. A voice training mode is entered. A voice training sample for a user of the mobile device is recorded. The voice training mode is interrupted to enter a noise indicator mode based on a sample background noise level for the voice training sample and a sample background noise type for the voice training sample. The voice training mode is returned to from the noise indicator mode when the user provides a continuation input that indicates a current background noise level meets an indicator threshold value. |
| US09691374B2 |
Processing a stream of ordered input data
A data processing system is provided for performing processing operations upon an ordered stream of input data values to form an ordered stream of output data values. A select circuit (18) includes select interval generation circuitry (34) which determines a number (interval number) of input data values between each data value to be selected for output from among the ordered stream of input data values. This interval number varies with position within the ordered stream of input data values. The select circuit (18) can thus perform selection of input data values in accordance with an interval number which may be varied, for example, in accordance with a linear piecewise approximation of an desired curve or, in other embodiments, in a piecewise quadratic variation approximating a desired curve. The processing techniques may be used, for example, in beam forming application, such as 3D beam forming of ultrasonic images. |
| US09691371B1 |
Air adsorbing and sound absorbing structure
An air adsorbing and sound absorbing structure with a first portion comprising a first material comprising an open-celled foam with an air-adsorbing material coupled to the foam, where the first portion has a first air adsorption capacity and a first density. There is a second portion fixed to or integral with the first portion, wherein the second portion comprises one or more of: a different material than the first material, a second air adsorption capacity that is different than the first air adsorption capacity, and a second density that is different than the first density. |
| US09691370B1 |
Acoustical panels
Acoustical materials of the type provided in panel form for purposes of controlling or adjusting the acoustics of an interior space, such as an auditorium or concert hall, conference room, etc., and commonly referred to as architectural acoustical panels or ceiling panels. A panel comprises multiple layers, such as a surface layer which faces the room or sound source, which in turn comprises wood veneer laminated to a supporting layer and defines a plurality of microperforations extending entirely through, the surface layer. An acoustical absorbing layer may be a wood wool material or, most preferably, high-density fiberglass having a particular orientation, along with a combination of a support material or ribbing, which may define a plurality of cells in which the fiberglass lies. A back support layer may be perforated or solid. The density and orientation of the sound absorbing material combine with the density and quality of the microperforations to produce substantial improvement in sound absorption over a broad range of frequencies. |
| US09691368B2 |
Multifunctional digital musical instrument
An electronic musical instrument includes a database including timbre data corresponding to a plurality of musical instruments an acoustic data input unit configured to display an acoustic data input position corresponding to a selected one of the musical instruments, detect whether the acoustic data input position is touched, and receive information on the touched acoustic data input position a mouthpiece detachably provided and having a shape corresponding to a shape of a mouthpiece of the selected musical instrument a wind sensor unit configured to measure an amount of air to generate loudness data a control unit configured to receive timbre data corresponding to the information on the touched acoustic data input position, receive the loudness data from the wind sensor unit, and synthesize the timbre data and the loudness data to output an acoustic sound signal of the selected musical instrument and a power supply unit configured to supply power. |
| US09691360B2 |
Alpha channel power savings in graphics unit
A graphics processing circuit and method for power savings in the same is disclosed. In one embodiment, a graphics processing circuit includes a number of channels. The number of channels includes a number of color component channels that are each configured to process color components of pixel values of an incoming frame of graphics information. The number of channels also includes an alpha scaling channel configured to process alpha values (indicative of a level of transparency) for the incoming and/or outgoing frames. The graphics processing circuit also includes a control circuit. The control circuit is configured to place the alpha scaling channel into a low-power state responsive to determining that at least one of the incoming or outgoing frames does not include alpha values. |
| US09691359B2 |
Vehicle display system with transparent display layer
The invention pertains to display method, a computer program for performing the steps of the display method and a display system (1), the display system having for example: at least one display unit (13, 16) arranged to present at least one display image, at least one memory unit (12, 15) comprising information related to for example descriptions of a set of default graphics display objects (W1-W3) and configuration data. The configuration data is arranged to define: at least one transparent display layer (L1-L3), at least one transparent display container (CO0-CO2) associated to the at least one transparent display layer and at least one display mode. Each of said at least one display mode comprising a predetermined selection of one or more of said at least one transparent display container of one or more of said at least one display layer. |
| US09691358B2 |
Electronic apparatus and method for outputting content
An electronic apparatus and a method of outputting content of the electronic apparatus outputs a synchronized content to a display apparatus and a projection-type display apparatus and a method of outputting a content of the electronic apparatus. The electronic apparatus includes an input/output unit connected with a display apparatus and a projection-type display apparatus, and a control unit configured to control the input/output unit, wherein the control unit outputs a synchronized content to the display apparatus and the projection-type display apparatus through the input/output unit. |
| US09691352B2 |
Control method and device thereof
A control method and a device thereof are provided, which are applied to an electronic device. The electronic device includes a display module and a projection module, and is capable of displaying output content through the display module or projecting the output content to a projection screen. The method includes: detecting a state of the projection module; acquiring a current display brightness of the display module as a first display brightness, in the case that it is detected that the projection module is controlled to perform projection; and controlling a display brightness of the display module to switch from the first display brightness to a second display brightness which is lower than the first display brightness. |
| US09691350B2 |
Display apparatus including light controlling parts and method of driving the same
A display apparatus includes: a pixel part including a plurality of pixels arranged substantially in a matrix form, where the matrix form includes a unit matrix having X columns in a horizontal direction and Y rows in a vertical direction, where X and Y are natural numbers; and a plurality of light controlling parts inclined with respect to the vertical direction of the pixels on the pixel part at an inclined angle of θ, where the inclined angle of θ satisfies the following equation: θ=tan−1((M×X)/(N×Y)), where M and N are different natural numbers. |
| US09691344B2 |
Liquid crystal display device having a master and slave drivers and driving method thereof
According to one embodiment, a power reception section connects to the battery side, and receives supply of power, a detection section detects a singular state where a voltage of the battery side has fallen to a value less than or equal to a predetermined voltage value, a shifting section receives a detection output of the singular state from the detection section to thereby shift to singular control, and a driver connection section connects the plurality of drivers to each other. If the detection section in one of the liquid crystal display drivers has detected the singular state, the shifting section executes the singular control, and the driver connection section notifies the other liquid crystal display drivers that the singular state has been detected. |
| US09691341B2 |
Data driver and display apparatus including the same
A data driver includes a digital-to-analog converter, a control signal output circuit, and an output buffer. The digital-to-analog converter generates first data voltages and second data voltages based on image data and a polarity control signal. Each first data voltage has a positive polarity, and each second data voltage has a negative polarity. The control signal output circuit outputs a first output control signal and a second output control signal based on the polarity control signal. A phase of the second output control signal is different from a phase of the first output control signal. The output buffer outputs the first data voltages based on the first output control signal and outputs the second data voltages based on the second output control signal. |
| US09691338B2 |
Liquid crystal display device
According to an aspect, the liquid crystal display device includes: an expansion coefficient determining unit that determines an expansion coefficient of each of partial areas based on a signal level of the first, the second, and the third colors; a luminance level determining unit that determines a luminance level of each partial area based on the signal level; a signal processing unit that uses the expansion coefficient to expand the signal level; and a light source control unit that controls brightness of a light source based on the expansion coefficient and the luminance level. The light source can change the brightness of the partial areas individually. The light source control unit controls the light source such that the brightness of the light source in a partial area having a luminance level equal to or higher than a predetermined threshold is higher than the brightness based on the expansion coefficient. |
| US09691329B2 |
Organic light emitting display device configured to measure deterioration information, and driving method thereof
An organic light emitting display device includes pixels positioned at crossing regions between data lines and scan lines, each of the pixels including an organic light emitting diode, a scan driver configured to supply a scan signal to scan lines, a data driver configured to drive the data lines, wherein the data driver includes, in each channel, a supply part comprising a digital-to-analog converter configured to generate data signals using second data supplied from outside in a driving period, and a deterioration part configured to measure deterioration information of the organic light emitting diode using the digital-to-analog converter in a sensing period. |
| US09691328B2 |
Pixel driving circuit, pixel driving method and display apparatus
The present disclosure relates to a pixel driving circuit, a pixel driving method and a display apparatus. In addition to a storage unit in a conventional pixel driving circuit, the pixel driving circuit comprises an auxiliary storage unit, which is charged to a data voltage in a charging phase and stables a gate potential of a driving unit when a data voltage write switch is turned off in a threshold voltage compensation phase, so that there is enough time for the storage unit of the driving unit to acquire the data voltage and a threshold voltage of the driving unit through self-discharge and the storage unit of the driving unit compensates for the driving unit in a driving phase. In this way, operating current of the driving unit is not influenced by the threshold voltage. |
| US09691318B2 |
Image display method and device and electronic apparatus
An image display method, device and electronic apparatus avoid to some extent a problem of a poor display effect due to adjusting an image purely depending on an RGB image conversion algorithm. The solution comprises obtaining a brightness value of current ambient light; performing image conversion on a frame of image having three primary color components to obtain a first display information, the first display information comprising four primary color gray scale values of each pixel in the image; adjusting the first display information to a second display information according to the brightness value, the second display information comprising four primary color gray scale values of each adjusted pixel; and displaying the image according to the second display information. |
| US09691317B2 |
Image display control method and image display control device
The present invention discloses an image display control method and an image display control device for realizing an ideal display result of chroma by compensating the chroma values of all sub-pixels used for displaying the current frame of an image. The image display control method comprises: acquiring chroma values, output by a signal source, of all sub-pixels needed when a display device displays the current frame of an image; adjusting the acquired chroma values of all the sub-pixels according to pre-stored chroma compensation values corresponding to respective sub-pixels to obtain adjusted chroma values corresponding to respective sub-pixels; and driving the display device according to the adjusted chroma values corresponding to respective sub-pixels to display the current frame of the image. |
| US09691316B2 |
Display device capable of clock synchronization recovery
Provided is a display device including a timing controller configured to output a clock synchronizing signal for a clock data recovery operation, and a plurality of source driving chips configured to perform the clock data recovery operation in response to the clock synchronizing signal, wherein each of the source driving chips includes a filter unit configured to determine whether the first and second detection signals are activated or deactivated in response to a voltage level of the clock synchronizing signal and to output an operation signal according to a comparative result of the first and second detection signals, and an internal clock generator configured to perform the clock data recovery operation in response to the activation state of the operation signal. |
| US09691315B2 |
Touch-type input device
A touch-type input device includes a touch panel including drive electrodes and sensor electrodes. Capacitors are formed at intersections of the drive electrodes and sensor electrodes. A controller determines whether a conductive foreign matter exists on the touch panel from raw data values indicating changes in the capacitances of the capacitors from initial reference values. The controller determines touching of the touch panel from control data values indicating changes in the capacitances of the capacitors from control reference values changed when a conductive foreign matter exists. When the raw data values indicate existence of a conductive foreign matter, the controller sets the control reference value of each capacitor to a raw data reference value corresponding to the present raw data value. The controller updates the initial reference value when the touch-type input device is activated and updates the control reference value when the control reference value is erroneous. |
| US09691311B1 |
Banner stand assembly
A banner stand assembly. The banner stand assembly includes pair of horizontal members that are insertable through channels in a banner, a plurality of vertical members removably securable therebetween, and a plurality of triangular support members having a flexible central portion slidably and removably secured to the vertical members. The support members are angularly adjustable via movement along the vertical members. The flexible central portion allows the angle of the banner to be adjusted and allows the banner stand assembly to maintain even footing on sloped terrain. The support members are individually height adjustable so that the banner stand assembly can support a banner on varied terrain. |
| US09691308B2 |
Lighted mounting apparatus
A lighted mounting apparatus for a promotional glass holder including a channel which is lined on the bottom by a LED strip, a pair of extrusions to receive and hold a promotional glass, and a low voltage power supply. |
| US09691306B2 |
Transparent display board with structure of double layer type and manufacturing method thereof
The present invention relates to a transparent electric billboard having a multilayer structure and a manufacturing method thereof, and more particularly, to a transparent electric billboard having a multilayer structure that have high insulation and soundproof effect by having a multilayer structure with spaces therein, and a method of manufacturing the transparent electric billboard. |
| US09691305B2 |
Pixel interleaving configurations for use in high definition electronic sign displays
Pixel interleaving configurations for use in high definition electronic sign displays where each and every scan line includes full red, green, and blue color representation to provide for high resolution electronic video sign displays. |
| US09691301B2 |
Apparatus and method for training local anesthesia techniques in dental applications
A safe needle for instructional use includes a bead affixed to the penetrating needle tip of a dental anesthetic needle. The safe needle allows unlimited practice of pre-invasive technique without the stress and safety issues of using an actual needle. |
| US09691300B2 |
Text-to-touch techniques
Text-to-touch techniques, in accordance with embodiment of the present technology, include apparatuses and methods for receiving content including textual portions and non-textual portions. The textual portions include letters, select words, numbers and punctuation having recognized Braille codes. The non-textual portions may include metadata, graphics, formatting, decorations, hyperlinks, radio buttons, submit buttons, check boxes, windows, icons, fields and/or the like. The systems and methods convert the textual portion to Braille codes and select non-textual portions to haptic feedback. The Braille code may then be output to a user. In addition, the haptic feedback associated with various Braille codes may also be output to the user along the associated Braille codes. |
| US09691296B2 |
Methods and apparatus for conversation coach
In exemplary implementations of this invention, a display screen and speakers present an audiovisual display of an animated character to a human user during a conversational period of a coaching session. The virtual character asks questions, listens to the user, and engages in mirroring and backchanneling. A camera and microphone gather audiovisual data regarding behavior of the user. After the conversational period, the display screen and speakers display feedback to the user regarding the user's behavior. For example, the feedback may include a plot of the user's smiles over time, or information regarding prosody of the user's speech. The feedback may also include playing a video of the user that was recorded during the conversational period. The feedback may also include a timeline of the human user's behavior. The virtual coaching may be provided over the Internet. |
| US09691295B2 |
Musical puzzle
This application discloses a game that engages a user in correctly reproducing the duration of notes (short, long) to reproduce a melody from a sequence of notes. The melody becomes recognizable when the durations are approximately correct. As a game, the processing system may score the selected durations and provide feedback to the gamer.This technology can be implemented as a method, device, system or article of manufacture. In addition, for some jurisdictions, it can be described as software that produces a technical effect. |
| US09691294B2 |
Computerized system for teaching, learning, and assessing the knowledge of STEM principles
An on-line teaching, learning and assessing system provides a teacher rapid feedback while teaching a classroom lesson on STEM principles by measuring student progress in learning the principles wherein student progress is measured by students' correct answers to assessment questions. The system includes at least one teacher computer and a plurality of student computers linked to the at least one teacher computer by a communications network. Each computer includes an input device and a touch sensitive screen for receiving handwritten input. The teacher inputs the teacher computer with at least one assessment question and at least one corresponding correct answer to the question, both inputs being handwritten using math expressions and STEM sketches. The student inputs the student computer with at least one student answer corresponding to the assessment question, the answer being handwritten using math expressions and STEM sketches. |
| US09691291B2 |
System and method for providing group learning via computerized student group assignments conducted based on student attributes and student-variable-related criteria
In certain implementations, group learning may be provided via computerized student group assignments. In an implementation, student information about students registered to take a course may be obtained. The student information may comprise attributes of the students that correspond to student variables. Group criteria information associated with the course may be obtained. The group criteria information may comprise first criteria indicating that a student group is to be diverse with respect to a first variable, and second criteria indicating that a student group is to be similar with respect to a second variable. The students may be assigned to student groups associated with the course based on the attributes, the first criteria, and the second criteria such that a student group associated with the course comprises a set of students that, as a whole, is diverse with respect to the first variable and similar with respect to the second variable. |
| US09691290B2 |
Systems for quantifying clinical skill
Systems for quantifying clinical skill of a user, comprising: collecting data relating to a surgical task done by a user using a surgical device; comparing the data for the surgical task to other data for another similar surgical task; quantifying the clinical skill of the user based on the comparing of the data for the surgical task to the other data for the other similar surgical task; outputting the clinical skill of the user. |
| US09691286B2 |
Data driven airplane intent inferencing
Method, system and computer program product for providing a predicted vehicle track and for providing alerts when two predicted vehicle tracks are closer than a threshold amount. A vehicle intent prediction model is generated based on past instance of tracks for a vehicle operation, known vehicle intent data for the past instances, and contextual factors, such as weather, airline operator, air vehicle type or configuration, day of the week, etc. for the past instances. The vehicle intent prediction model can be generated using one or more machine learning algorithms. A future vehicle trajectory for a current vehicle operation can be output by the vehicle intent prediction model using the current track and existing contextual factors for the current vehicle operation. In the event that two vehicles following their respective predicted vehicle future trajectories would be closer than a threshold distance, an alert can be provided. |
| US09691284B2 |
Methods and systems related to time triggered geofencing
Time Triggered Geo-fencing. At least some of the example embodiments are systems including: a processor; a wireless interface coupled to the processor; and a memory coupled to the processor. The memory stores a program that when executed by the processor, causes the processor to receive a set of variables related to a geo-fence to be established at a predetermined time for a preset duration; establish the geo-fence at the predetermined time, the geo-fence established for the preset duration; monitor a location of a vehicle using signals received by the processor; and send an alert related to the location of the vehicle if said monitoring indicates the vehicle has crossed the geo-fence within the preset duration. |
| US09691283B2 |
Obstacle alert device
An obstacle alert device notifies a driver of the presence of an obstacle approaching a vehicle without making it difficult to see a state of the periphery of the vehicle. The apparatus includes: a captured image obtainment unit that obtains a captured image of a scene of the periphery of the vehicle; a target captured image generation unit that generates a target captured image based on the captured image; an object presence determination unit that determines whether or not an object is present in an outside region that is on an outer side of the target captured image; a movement direction determination unit that determines a movement direction of the object in the outside region; and a notification image output unit that, in the case where the movement direction determination unit has determined that the object in the outside region is moving toward the center of the target captured image, sequentially displays a plurality of indicators, that appear for a set amount of time and then disappear, in different locations of the target captured image, starting with the side having the outside region in which the object is present and moving toward the center of the target captured image, and repeats this display while displaying the plurality of indicators in positions where the indicators partially overlap with each other, with the indicator displayed later being displayed over the indicator displayed immediately previous thereto at the areas where the indicators overlap. |
| US09691279B2 |
Drive assist apparatus
Provided is a drive assist apparatus: based on signal indication information on a traffic signal installed at at least one intersection located ahead of a self-vehicle in a travelling direction of the self-vehicle, distance information from the self-vehicle to the at least one intersection, and a running speed of the self-vehicle, a recommended speed at which the self-vehicle can pass through the at least one intersection during a period in which the traffic signal installed at the at least one intersection is green is calculated and is notified to the driver. In addition, when a difference obtained by subtracting an actual running distance from a predicted running distance in a case where the self-vehicle runs at the recommended speed exceeds a first threshold value, it is determined that the road has a traffic jam and the notification of the recommended speed is terminated. |
| US09691269B2 |
Multiple function arrangement for electronic apparatus and method thereof
The current invention relates to the reuse of elements in an device to provide multiple functions of function indication, remote control command reception and touch sensor. The device comprises an indicator element providing a first function of indicating to a user the operating state of the said device, a receiver element providing a second function of reception of remote control commands from a remote control device, means for combining the indicator element and the receiver element to provide a third function of touch sensor. The indicator element provides the first function during a subsequent second period of time and the receiver element providing the second function during the second of the time, the first and the second period of time being continuously alternated. |
| US09691266B2 |
Smart hazard detector drills
Systems and methods for initiating a drill by receiving an indication to start a drill. The indication to start the drill is received via a first network interface having a first network interface type. The drill is propagated to other devices in a network via a second network interface having a second network interface type. |
| US09691264B2 |
Security system health monitoring
An apparatus and method for determining at least one operational condition of a premises based system including at least one premises device. The apparatus includes a processor configured to perform a diagno stic procedure. The diagnostic procedure includes determining operational data of the premises based system, the operational data indicating at least one of a premises device and the apparatus is operating outside a failure range and performing predictive analysis based at least in part on the received operational data. The predictive analysis indicates whether the at least one of premises device and apparatus is likely to operate within the failure range within a predefined period of time. The diagnostic procedure includes causing a notification alert to be transmitted to at least one of a user interface device and remote monitoring center based on the predictive analysis. |
| US09691263B2 |
Systems and methods for monitoring conditions
Systems and methods for monitoring conditions are provided. A system can comprise a plurality of wireless transmitters and a plurality of repeaters. At least one wireless transmitter can be integrated into an alarm. The repeaters can be dispersed throughout a region at defined locations. The system can also include a computer to receive information communicated from the repeaters and the transmitters. The computer can include software for evaluating received information, identifying an alarm condition and an originating location of the alarm condition, and for reporting the alarm condition to a remote location. Other embodiments are also claimed and described. |
| US09691261B2 |
Home automation communications
A system includes a computing device programmed to receive an alert signal indicating an issue associated with a customer premises. The computing device is further programmed to transmit a notification signal to a plurality of remote devices, determine whether at least one of the plurality of remote devices has responded to the notification signal, and transmit an update signal to the other of the plurality of remote devices after one of the plurality of remote devices has responded to the notification. The update signal indicates that one of the plurality of remote devices has responded to the notification signal. |
| US09691260B2 |
Electronic device with orientation-based alert adjustment
Methods and apparatuses are disclosed that allow an electronic device to autonomously adapt one or more user alerts to the current operating environment of the electronic device. For example, some embodiments may include a method comprising providing a plurality of alert devices in an electronic device, determining an operating environment of the electronic device using a sensor of the electronic device, and actuating at least one of the plurality of alert devices that corresponds to the determined operating environment. |
| US09691257B2 |
Systems and methods for silencing an audible alarm of a hazard detection system
Hazard detection systems and methods according to embodiments described herein are operative to enable a user to interface with the hazard detection system by performing a touchless gesture. The touchless gesture can be performed in a vicinity of the hazard detection system without requiring physical access to the hazard detection system. This enables the user to interact with the hazard detection system even if it is out of reach. The hazard detection system can detect gestures and perform an appropriate action responsive to the detected gesture. In one embodiment, the hazard detection system can silence its audible alarm or preemptively turn off its audible alarm in response to a detected gesture. Gestures can be detected using one or more ultrasonic sensors, or gestures can be detected using a motion detector in combination with one or more ultrasonic sensors. |
| US09691255B2 |
Control device, and control system
To improve the accuracy of the determination on whether or not a moving object is present in a predetermined region, a control device for use in a system configured to conduct presence-or-absence determination on whether or not a moving object is present on the basis of detection by a first sensor provided in a predetermined compartment region, the control device comprising: a mode control section configured to control switching of an operation mode for the detection by the first sensor or the presence-or-absence determination; and an acquisition section configured to acquire a determination result of whether or not a moving object is present in an adjacent region adjacent to the predetermined compartment region and not including the predetermined compartment region; wherein the mode control section controls the switching of the operation mode in response to the determination result acquired by the acquisition section, is provided. |
| US09691248B2 |
Transition to accessibility mode
An approach is disclosed that provides assistance to disabled individuals when utilizing public spaces. In the approach, a wireless message is received at a detector of the system with the wireless message being from a device worn by a disabled individual. The wireless message includes impairment data pertaining to the disabled individual. In addition, reception of the wireless message indicates that the disabled individual has entered a physical area that provides accommodations to disabled individuals. The approach identifies an impairment pertaining to the disabled individual and adjusts a device setting of a device in the physical area based on the identified impairment of the disabled individual. |
| US09691246B2 |
Flame detector for monitoring a region adjacent to bodies of water and taking into consideration a degree of polarization present in the received light for the activation of a fire alarm
A flame detector, may be aligned to cover a region to be monitored near a body water. The flame detector has at least one radiation sensor and a downstream evaluation unit. The at least one radiation sensor is sensitive to light in the spectrum of open fire. The evaluation unit outputs a fire alarm in the event of fluctuations or flicker frequencies characteristic of open fire being detected. A linear polarizing filter positioned upstream of the radiation sensor(s) has a polarization plane rotated about a main receiving direction to largely suppress the horizontal component of the received light, based on the knowledge that light reflected from water surfaces is predominantly horizontally polarized. If characteristic flicker frequencies and a significant degree of polarization are simultaneously detected in the received light, the detector identifies sunlight reflected off bodies of water and modulated by the swell, and a false alarm output is inhibited. |
| US09691244B2 |
Multi-functional self-defensive spraying device
The present invention provides a multi-functional self-defensive spraying device comprising mainly a main body and a bottle body embedded in the main body. On the main body are disposed a control circuit composed of a microprocessor, an alarm module, a voice recognition module, an emitting module, and a GPS module, and a button connected to the control circuit. Inside the bottle body is disposed an internal pocket for housing chemical agents and in the internal pocket is disposed a high pressure gas cylinder. A string connects the high pressure gas cylinder to a pull ring exposed at an outer edge of the bottle body. At a top edge of the bottle body is disposed a nozzle head. When under attack, a user may press the nozzle head therefrom chemical agents will be sprayed to scare and deter the attacker. Also, when a user presses the button or shouts a particular sound, an alarm sound will be emitted and a rescue unit such as the police office will be notified of the attack and the whereabouts of the user. During an emergency, a user may remove the bottle body and pull the pull ring outwards to release pressure from the high pressure gas cylinder, causing the chemical agents to break through the top end of the internal pocket and the nozzle head. The user may speedily escape when the chemical agents are thus dispersed as in an explosion. |
| US09691243B1 |
Exit-code-based RFID loss-prevention system
Methods and systems are described for authorizing an item with an RFID tag to leave a facility. In one embodiment, a mobile device receives or determines an exit code (EC) to write into the tag in response to providing authorizing information. The EC may be based on information stored in the tag such as the tag's item identifier or other tag information (collectively an item identifier or II), a ticket value, other information such as the OC, a mobile identity or location, or any other suitable information. Upon verification of the EC, the tagged item is allowed to leave the facility. In another embodiment, the mobile device stores an item identifier (II) associated with the tag and provides authorizing information. Upon verifying the authorizing information and confirming that the stored II corresponds to the tagged item's II, the tagged item is allowed to leave the facility. |
| US09691241B1 |
Orientation of video based on the orientation of a display
Methods and systems involving the orienting of video data based on the orientation of a display are described herein. An example system may be configured to (1) receive first video data, the first video data corresponding to a first orientation of the image-capture device; (2) send the first video data to a second computing device; (3) receive, from the second computing device, first orientation data indicating a requested orientation of the image-capture device; (4) cause a visual depiction of the requested orientation to be displayed on a graphical display; (5) receive second video data, the second video data corresponding to a second orientation of the image-capture device, where the second orientation is closer to the requested orientation than is the first orientation; and (6) send the second video data to the second computing device. |
| US09691239B2 |
Electronic system for locating remote objects
Systems and methods for marking and locating objects in crowded environments, and more particularly, systems and methods that include a remote configured to communicate with a beacon having audio and visual indicators, are shown and described. One system comprises a remote including a housing, a tool extending from the housing, a movable sleeve configured to cover the tool, a first control circuit, a selection button coupled to the control circuit, a first transceiver, and a beacon including a second transceiver configured to communicate with the first transceiver, a second control circuit, an indicator electrically coupled to the second control circuit, and a latch mechanism, the tool configured to interact with the latch mechanism to securely couple the beacon. |
| US09691238B2 |
Crowd-based haptics
A system produces haptic effects. The system receives input data associated with an event, identifies an element of the event in the input data, generates the haptic effects based on the element of the event, and produces the haptic effects via a haptic output device. In one embodiment, the haptic effects are generated by haptifying the element of the event. In one embodiment, the haptic effects are designed haptic effects and are adjusted based on the element of the event. In one embodiment, the input data is associated with a crowd that attends the event, and the element of the event is caused by the crowd. In one embodiment, the input data includes haptic data collected by one or more personal devices associated with the crowd. In one embodiment, the input data is indicative of a location of the one or more personal devices associated with the crowd. |
| US09691236B1 |
System and method for controlling light emitting diodes using backplane controller or enclosure management controller
Aspects of direct to systems and methods for controlling LEDs by a backplane or enclosure management controller. A controller has multiple output ports, including M ports connecting to M row control lines and N ports connecting to N column control lines. At least (M*N) LEDs respectively connected to the M row control lines and N column control lines to form a virtual LED matrix. In operation, the controller monitors N storage drives of the system, and determines at least M states for each storage drive. Based on the M states for each storage drive, the controller determines a state of each LED being ON or OFF, and outputs control signals to the at least M row control lines and the at least N column control lines through the output ports based on the state of each LED, such that the LEDs display the states of the storage drives. |
| US09691233B2 |
Cassette for use with an automated banking machine that can receive power and communicate via magnetic induction
In an example embodiment, a document holding cassettes that can be used in an automated banking machine that includes circuitry that is wirelessly powered through inductive coupling. The cassette can wirelessly communicate with the automated banking machine through induction. |
| US09691223B2 |
Selectable intermediate result interleaved wagering system
A selectable intermediate result interleaved wagering system is disclosed. The system includes an interactive controller operatively connected to an application controller, and constructed to: communicate application telemetry; receive an intermediate offer; communicate an indication to accept the intermediate offer; receive an application resource associated with the intermediate offer; and receive a wager outcome. The system also includes a wager controller operatively connected to the application controller, the wager controller constructed to: receive the wager request; generate a wager outcome; and communicate the wager outcome. The system also includes the application controller operatively connecting the interactive controller to the wager controller by a network, the application controller constructed to: receive the application telemetry; generate the intermediate offer; communicate the intermediate offer; receive the indication to accept the intermediate offer; communicate the application resource associated with the intermediate offer; communicate the wager request; receive the wager outcome; and communicate the wager outcome. |
| US09691215B2 |
Gaming system and method for offering simultaneous play of multiple games
Gaming apparatus and methods of conducting a wagering game of chance. A gaming machine is disclosed which is configured for mutually concurrent play of a plurality of games of chance on a single display screen. A method of conducting a wagering activity includes providing a player with a plurality of differing games of chance, at least some of which are mutually concurrently playable on a single screen display of a gaming device and enabling mutually concurrent play of the plurality of differing games of chance on the single screen display. Various other gaming machine configurations and methods of play related to multiple differing games of chance on a single display screen are also disclosed herein. Networked gaming machines are also disclosed. |
| US09691210B2 |
Coin processing device and corresponding method for classifying coins
A coin processing device (10) and a method for classifying coins are provided. The coin processing device (10) includes at least one computerized controller (9) having a storage unit (36), and at least one coin channel (34) for guiding a coin (35). The at least one coin channel (34) includes at least one sensor (37) suitable for measuring a passage time of the coin (35). An accelerating device (43) is connected to the computerized controller (9) and is designed to accelerate the coin (35) in a reproducible manner. A target speed value for a specified coin (35) is stored in the storage unit (36). An actual speed value is calculated based on the transport time detected by the sensor (37). A coin class of the coin (35) is ascertained by the computerized controller (9) from the comparison of the target speed value and the actual speed value. |
| US09691207B2 |
Electronic lock with user interface
An electronic lock having one or more lock settings that can be updated using a mobile device. The mobile device includes an app that provides a user interface through which one or more lock settings of the electronic lock can be selected and modified. When the user has made the desired selections to the lock settings on the mobile device, the mobile device wirelessly transmits these settings to the electronic lock. The electronic lock is configured to update its lock settings based on the wireless communication from the mobile device. |
| US09691203B1 |
Door access control system permitting electronic and mechanical unlocking
A door access control system permitting electronic and mechanical unlocking includes a lock mounted to a door and an unlocking device matched with the lock. The lock can be set to be in a normal mode or an away mode. The unlocking device can be used to input a real-time unlocking identification information that is transmitted to the lock for comparison purposes. The lock can also be unlocked by a key. When the lock is set to be in the away mode, an alarm device is activated if the key is used. In this case, a first input device of the lock can be used to input a real-time alarm deactivating information to deactivate the alarm device. When the lock is set to be in the normal mode, the alarm device does not operate even if the key is used to unlock the lock. |
| US09691202B2 |
Inputting lock commands
A command can be input into an electronic lock by holding a data carrier in range of a reader of the lock. The lock provides an indicator for one or more commands. An indicated command can be selected using the data carrier. |
| US09691194B2 |
Systems and methods for assessing operational data for a vehicle fleet
Various embodiments of the present invention are directed to a fleet management system configured for capturing and evaluating vehicle telematics data, such as data captured from one or more vehicle telematics devices indicative of one or more vehicle dynamics, and service data, such as data captured from one or more portable data acquisition devices indicative of one or more service dynamics. In certain embodiments, the fleet management system is configured to associate captured vehicle telematics data with captured service data based on the contextual attributes of each, such as the time, date, and location of data capture. By synching the vehicle telematics data to the service data, the operational data can be uniquely assessed for various operational efficiencies. |
| US09691192B2 |
Method and apparatus for recall notification handling
In a first illustrative embodiment, a computer implemented method includes receiving a recall message from a remote source. The method also includes comparing the recall to stored vehicle data to determine if a recall repair has already been completed. The method further includes delivering the recall message to at least one vehicle occupant through a vehicle system, contingent on the non-completion of the recall repair. |
| US09691191B1 |
Methods and systems for automated real time continuous waveform electrical property monitoring and status reporting
A method for performing an integrated waveform analysis without the use of an external device is disclosed. The method includes receiving, at a processing device, at least one electrical waveform associated with a communications bus, extracting, with the processing device a plurality of real time parametric measurements of voltage samples for the at least one electrical waveform, comparing, with the processing device, the parametric measurements of voltage samples to stored data that is accessible to the processing device, the stored data related to expected electrical signal characteristics for the communications bus proximate at least one of system interfaces, hardware components, and interconnections associated with the communications bus, distinguishing any system interconnection degradations and hardware failures associated with the communications bus based on said comparing, and reporting, via the processing device, at least one of: extracted electrical signal parametric measurements are consistent with the stored electrical signal characteristics, electrical signal parameters are indicative of a system interconnection degradation, and electrical signal parameters are indicative of a hardware failure. |
| US09691190B2 |
Location based parking meter time reminder
In embodiments of the disclosure, location information can be used to automatically set a parking meter time reminder on a user's mobile device. For example, after determining that the user has parked once a destination has been reached, the user's location can be used to determine if the vehicle has been parked at a parking meter (or other timed parking), and a reminder can be set based on a time limit associated with that parking location. The reminder can display periodic notifications on the user's mobile device until it is detected that the user has driven the vehicle away from the parking spot. |
| US09691188B2 |
Tolling system and method using telecommunications
System, arrangement and method for tolling includes a location determining system arranged at least partly in a vehicle to determine the vehicle location during vehicular travel, a toll database including data about tolls for use of a plurality of lanes of a multi-lane roadway at a plurality of different geographic points, the toll data being different for different lanes of the multi-lane roadway at at least one geographic point, and a communications device arranged on the vehicle. A processor directs transmission including the determined vehicle location and an identification of the vehicle by the communications device to a remote site separate and apart from the vehicle. A toll is determined at the remote site based on the toll database and the vehicle location which is the lane-specific location of the vehicle or based on at least two vehicle locations each of which is a lane-specific location of the vehicle. |
| US09691187B2 |
Control device for vehicle hiring and control system using same
A control system for vehicle hiring includes a control device and a wireless smart key. The control device includes a first microprogram control unit. The wireless smart key includes a second microprogram control unit, a positive electrode and a negative electrode both electronically coupled to the second microprogram control unit. When the first microprogram control unit receives a first sensing signal or a second sensing signal, the first microprogram control unit is electronically coupled to the positive electrode and the negative electrode. |
| US09691186B2 |
Constraint of a subdivided model
A method of generating a design for a device is disclosed. The method includes electronically accessing a reference geometry representing the topology, and electronically accessing a source polygonal data model, where the source polygonal data model includes a plurality of source vertices. The method also includes modifying position characteristics of one or more of the source vertices, where the source vertices are modified so that after the source polygonal data model is subdivided, vertices in the subdivided polygonal data model corresponding with the modified source vertices conform to the reference geometry. The method also includes subdividing the source polygonal data model having the modified source vertices to generate the design, where subdividing the source polygonal data model causes vertices in the design to be positioned such that the design conforms with the reference geometry at least partly because of the modified position characteristics of the modified source vertices. |
| US09691182B1 |
System and method for adaptive display restriction in a headset computer
An apparatus for improving the safety of a driver while driving a car, the apparatus comprising a headset for combining an unobstructed view with a virtual overlay, the virtual overlay created from a virtual output provided to the headset, the virtual output having one or more portions, a memory, a processor, at least one input device coupled to the memory and capable of delivering input device data to the memory, an application stored in the memory that when executed by the processor determines characteristics of the driver or an environment around the driver based upon data from the at least one input device, and a controller that based on the determined characteristics performs one or more of the following: block a portion of the virtual output to the virtual overlay, alters at least a portion of the virtual output to the virtual overlay, or adds a new portion to the virtual output. |
| US09691181B2 |
Methods and systems for social sharing head mounted display (HMD) content with a second screen
Systems and method for processing video frames generated for display on a head mounted display (HMD) to a second screen are provided. One example method includes receiving the video frames formatted for display on the HMD, and while passing the video frames to the HMD, selecting a portion of content from the video frames and processing the portion of the content for output to a second screen. The video frames viewed in the HMD are a result of interactive play executed for viewing on the HMD. The second screen configured to render an undistorted view of the interactive play on the HMD. In one example, the method and system enable additional content to be rendered on the second screen (e.g., second screen content, such as social interactive play with others, other non-game content, player-player communication, etc.). |
| US09691177B2 |
Techniques for automatic occluder simplification using planar sections
Techniques are disclosed for simplifying an occluder representing 3D graphics data. Graphics data corresponding to one or more 3D objects is voxelized. A plurality of planes is generated to intersect the voxelized graphics data. Intersections between the planes and the voxelized graphics data are evaluated to identify corresponding slice polygons from the intersections. A subset of the planes is selected to maximize a correctness of a simplified occluder. The simplified occluder representing the object is generated from a union of the selected subset of the planes. |
| US09691173B2 |
System and method for rendering in accordance with location of virtual objects in real-time
There is provided a system and method for rendering in accordance with location of virtual objects in real-time. There is provided a method for persistent association of a graphic overlay with a virtual object in a displayable environment, comprising receiving a first three-dimensional coordinate of the virtual object in the displayable environment, determining a three-dimensional coordinate of the graphic overlay in accordance with the first three-dimensional coordinate of the virtual object, tracking a movement of the virtual object in the displayable environment by receiving one or more second three-dimensional coordinates of the virtual object, and modifying the three-dimensional coordinate of the graphic overlay in accordance with the one or more second three-dimensional coordinates of the virtual object. |
| US09691172B2 |
Furry avatar animation
Apparatuses, methods and storage medium associated with animating and rendering an avatar are disclosed herein. In embodiments, the apparatus may comprise an avatar animation engine to receive a plurality of fur shell texture data maps associated with a furry avatar, and drive an avatar model to animate the furry avatar, using the plurality of fur shell texture data maps. The plurality of fur shell texture data maps may be generated through sampling of fur strands across a plurality of horizontal planes. Other embodiments may be described and/or claimed. |
| US09691169B2 |
Compact font hinting
A system includes a computing device that includes a memory configured to store instructions. The computing device also includes a processor to execute the instructions to perform operations that include receiving data representing a glyph in a font to present the glyph on a display. In response to operations being executed to present the glyph on the display, operations include identifying one or more values shared by glyphs of the font for adjusting the appearance of the glyph, from a data table stored with the glyph in the font. Operations also include adjusting a representation of the glyph using the identified one or more shared values for presentation on the display. |
| US09691168B2 |
Image reconstruction using gradient projection for medical imaging applications
Techniques and systems are disclosed for estimating an unknown image from a plurality of cone-beam computed tomography (CBCT) image projections. The unknown image is estimated by solving for minima of an expression comprising a fidelity term that is a function of the plurality of image projections and a regularization term that is responsive to a sparsity of the CBCT image projections. The minima of the expression is iteratively estimated by calculating an image gradient of the function, determining a step size based on a based on a Barzilai-Borwein (BB) formulation and adjusting the minima estimate using the projected image gradient and a step size. |
| US09691165B2 |
Detailed spatio-temporal reconstruction of eyelids
Methods and systems of reconstructing an eyelid are provided. A method of reconstructing an eyelid includes obtaining one or more images of the eyelid, generating one or more image input data for the one or more images of the eyelid, generating one or more reconstruction data for the one or more images of the eyelid, and reconstructing a spatio-temporal digital representation of the eyelid using the one or more input image data and the one or more reconstruction data. |
| US09691164B2 |
System and method for symbol-space based compression of patterns
A method and system for symbol-space based pattern compression. The method includes identifying a plurality of basic image symbols in an input sequence; assigning, to each of the plurality of basic image symbols, at least one connecting port; generating an output sequence by replacing each identified basic image symbol with an identification symbol, wherein the output sequence indicates connections between pairs of the plurality of basic image symbols based on the connecting ports, wherein each identification symbol is not a previously used symbol; and storing the output sequence as a data layer. |
| US09691160B2 |
Device and method for motion estimation and compensation
A device for motion estimation in video image data is provided. The device comprises a motion estimation unit (11, 21) for estimating a current motion vector for an area of a current image by determining a set of temporal and/or spatial candidate motion vectors and selecting a best motion vector from the set of candidate motion vectors. The motion estimation unit (11, 21) is further adapted for substantially doubling one or more of the candidate motion vectors and for including the one or more substantially doubled candidate motion vectors in the set of candidate motion vectors. |
| US09691159B2 |
Local contraction measurements
A system (10) for quantification of uncertainty of contours includes a display (48) which displays a portion of a 4D image of at least a left ventricle over a plurality of cardiac phases. A measurement device (16) includes at least one processor (42) programmed to receive the 4D image (18) from an imaging device (12), receive a selected location on the myocardial wall of the left ventricle, cast a ray perpendicular to at least one of the myocardial wall or center of the left ventricle through the selected location, calculate a thickness the myocardial wall along the cast ray, evaluate myocardial wall motion over the range of the cardiac phases, calculate a quantification of the myocardial contractile function, and display the calculate a quantification of the myocardial contractile function on the display device (48). |
| US09691150B2 |
Image processing apparatus, image processing method and storage medium
An image processing apparatus includes: an image obtaining unit configured to obtain a first image by imaging an object using a first imaging apparatus, a second image by imaging the object using a second imaging apparatus, a third image by imaging the object using an image capturing unit whose position is associated with the second imaging apparatus; and an alignment unit configured to align the object in the first image with the object in the second image so that observation information of the object in the first image matches observation information of the object in the third image. |
| US09691148B2 |
Medical imaging analyzer and medical image processing method
According to one embodiment, a medical imaging analyzer includes an imaging unit, a calculator, and an analyzer. The imaging unit divides an area including an object of a subject to be captured into a plurality of partial areas such that the partial areas overlap each other to form an overlapping area, and administers a contrast agent to each of the partial areas to capture a plurality of time-series images. The calculator calculates, based on the transition of the pixel value in one of the time-series images having the overlapping area, the transition of the pixel value in the other time-series image having the overlapping area. The analyzer analyzes the time-series images based on the transition of the pixel value in the one and the other of the time-series images to obtain the hemodynamics of the subject. |
| US09691146B2 |
Non-touch optical detection of vital sign from amplified visual variations
A microprocessor is operably coupled to a camera from which patient vital signs are determined. A temporal-variation-amplifier of at least two images is operable to generate a temporal variation, a vital-sign generator is operable to generate at least one vital sign from the temporal variation and a display device is operable to display the at least one vital sign. |
| US09691143B2 |
Inspection apparatus and inspection apparatus system
A first output value evaluation device obtains an average value of output values of optical image data for each of unit regions and creates a distribution map of an average value in an inspected region. A first defect history management device creates a distribution map related with the shape of the pattern from the distribution map of the average value and holds the created distribution map. A second output value evaluation device obtains at least one of a variation value and deviation of the output value of each pixel in the unit region. A defect determination device compares the obtained value with a threshold value. A second defect history management device holds information of the output value determined as a defect in the defect determination device. A defect/defect history analysis device analyzes, and checks the information from the first defect history management device and the second defect history management device. |
| US09691138B2 |
System and method for adjusting pixel saturation
In one aspect, a computer-implemented method for adjusting pixel saturation may generally include accessing, by one or more computing devices, a target distribution function associated with at least one target image and an input distribution function associated with at least one input image. The target distribution function may define a target probability for a pixel saturation of each pixel within the target image(s). The input distribution function may define an input probability for an initial saturation value of each pixel within the input image(s), with the input image(s) differing from the target image(s). The method may also include associating, by the computing device(s), the initial saturation value of each pixel within the input image(s) with a target saturation value based on the input and target distribution functions and adjusting, by the computing device(s), the initial saturation value of each pixel within the input image(s) to the corresponding target saturation value. |
| US09691130B2 |
Adaptive screen interfaces based on viewing distance
Voice commands and gesture recognition are two mechanisms by which an individual may interact with content such as that on a display. In an implementation, interactivity of a user with content on a device or display may be modified based on the distance between a user and the display. An attribute such as a user profile may be used to tailor the modification of the display to an individual user. In some configurations, the commands available to the user may also be modified based on the determined distance between the user and a device or display. |
| US09691127B2 |
Method, apparatus and computer program product for alignment of images
In an example embodiment a method, apparatus and computer program product are provided. The method includes calculating directionality values for pixels of a first image and pixels of a second image, where a directionality value for a pixel is calculated based on gradient differences between the pixel and a plurality of neighboring pixels. The method includes determining a plurality of similarity values between the first image and the second images for a plurality of alignment positions of the first image and the second image based on the directionality values for the pixels of the first image and the directionality values for corresponding pixels of the second image. The method further includes selecting an alignment position from among the plurality of alignment positions for aligning the first image and the second image based on comparison of the plurality of similarity values. |
| US09691126B2 |
Systems and methods for recipient-side image processing
Systems, methods, and non-transitory computer readable media configured to create, process, and/or modify images are provided. Recipient image data associated with an original image captured by a second computing system can be received by a first computing system. A first intermediate image may be generated based on the recipient image data. A first viewable image for display on the first computing system may be generated based on the first intermediate image. |
| US09691123B2 |
Instrumentation of graphics instructions
Embodiments of graphics instruction instrumentor (“GII”) and a graphics profiler (“GP”) are described. The GII may facilitate profiling of execution of graphics instructions by one or more graphics processors. The GII may identify target graphics instructions for which execution profile information is desired. The GII may store instrumentation graphics instructions in a graphics instruction buffer. The instrumentation graphics instructions may facilitate the GP in collecting graphics profile information. For example, timestamp-storage instructions may be store timestamps before and after execution of the target graphics instructions. The GII also may store an interrupt-generation instruction to cause an interrupt to be sent to the GP so that the GP may begin collection of graphics profile data. The GII may store an event-wait instruction to pause the graphics processors until an event is received. Other embodiments may be described and claimed. |
| US09691116B2 |
Intelligent barcode systems
Systems and methods using intelligent barcodes for processing mail, packages, or other items in transport are provided. Systems and methods allowing end-to-end visibility of a mail stream by uniquely identifying and tracking mail pieces are also provided. Systems and methods include the use of standardized intelligent barcodes on mail pieces, a seamless process for mail acceptance, continuous mail piece tracking, and feedback on mail quality in real time. In one embodiment, systems and methods using intelligent barcodes allow a mailing service to provide enhanced acceptance, sorting, tracking, address correction, forwarding, and delivery services. In another embodiment, systems and methods using intelligent barcodes allow a mailing service to identify a mail piece as undeliverable-as-addressed (UAA) and determine a final disposition for the mail piece. In yet another embodiment, systems and methods using intelligent barcodes allow mailers more visibility into the mail stream and information on the quality of their mailings. |
| US09691109B2 |
Mechanism for reputation feedback based on real time interaction
A method for confirming that a user interacted with a resource provider before allowing the user to submit feedback associated with the resource provider is disclosed. A social network provider can query entities that are aware of the user's interaction history before activating a feedback function. Also, non-sensitive information can be used to identify the user. |
| US09691108B2 |
Determining logical groups without using personal information
Systems and methods for the forming of user device groups are presented. In one example, logical relationship information describing logical relationships among a plurality of user devices is accessed. Scores for each of a plurality of possible groups are generated based at least partially on the logical relationship information and information about a first user device, but the scores not being based on any personally identifiable information about the first user of the first user device. A first group is selected from the plurality of possible groups based on the scores. Then the first user device is added to the first group. |
| US09691105B2 |
Analyzing calendar to generate financial information
Techniques of analyzing a calendar to generate financial information are disclosed. In some embodiments, scheduled event data for at least one scheduled event is extracted from an electronic calendar. The scheduled event data can comprise corresponding time data and text for each one of the at least one scheduled event. A financial accounting entry for each one of the at least one scheduled event can be generated based on the extracted scheduled event data. The financial accounting entry can comprise an electronic record of business-related activity that can be used for a financial accounting purpose. Generating the financial accounting entry can comprise populating the financial accounting entry using the time data of the corresponding scheduled event. |
| US09691099B2 |
Methods and systems to alert a user of a network-based marketplace event
A system to alert a user of a network-based marketplace event. The system receives the network-based marketplace event and determines if the network-based marketplace event is associated with a network-based marketplace alert that has been requested by the user. If so, the system communicates the network-based marketplace alert to the client machine over a persistent connection, the network-based marketplace alert to alert the user of the network-based marketplace event. |
| US09691098B2 |
Method and system for managing and displaying product images with cloud computing
A method and system displaying and managing images of consumer products with cloud computing. A layout for plural selected consumer products is selected. An N-layer digital image of a shelf layout on which consumer products are displayed is created and stored in one or more cloud storage objects. The created N-layer digital image includes an M-layer hierarchy of vector images and/or visual overlays stored in one or more cloud storage objects in progressive resolution format and allows progressive resolution display without loss of image quality on the selected plural consumer products that appear in the N-layer digital image. The created N-layer digital image is displayed via a cloud communications network. The created image provides a virtual shopping experience that emulates a shopping experience in an actual retail store. |
| US09691094B2 |
Retail system and computer-implemented method for designing a customization of a product
A customer at a customer computer system transmits a page request to a retailer computer system. The retailer computer system transmits a product page and a script to the customer computer system. The script is executable by the customer computer system to transmit a customization request from the customer computer system to a customization computer system. The customization computer system inserts controls and a save selector onto the customer computer system. Use of the controls at the customer computer system allows for customization of an image of the product viewed on a display of the customer computer system to render a compound image. Selection of the save selector at the customer computer system causes transmission of a transmission packet from the customization computer system to the retailer computer system. The retailer computer system stores the compound image in a shopping cart associated with the customer computer system. |
| US09691092B2 |
Predicting and responding to customer needs using local positioning technology
Methods and systems for predicting and responding to customer needs using local positioning technology are presented. In some embodiments, a customer assistance computing platform may receive one or more attributes associated with a beacon signal received by a customer computing device and an identifier associated with the customer computing device. Subsequently, the computing platform may determine an identity of a customer using the customer computing device. The computing platform then may determine a location of the customer using the customer computing device based on the one or more attributes associated with the beacon signal. Thereafter, the computing platform may determine one or more predicted needs of the customer. Then, the computing platform may generate a notification based on the predicted needs of the customer and may send the notification to the customer computing device. |
| US09691091B2 |
Transportation service matching with location tracking and arrival estimation
Matches for transportation services with transportation service providers (TSPs) and providing tracking are combined with an option for location tracking of the load or transportation service. Bids are accepted for transportation services and, on acceptance, a request is made for the TSP or driver “opt-in” to location tracking through a mobile device. The system automatically communicates with the driver to confirm acceptance of mobile telephone tracking (opt-in) and location tracking is initiated. The location is reported according to a threshold, along with updated estimates of pick-up and of completion of delivery. The tracking provides substantially a “24/7” access to the location and updated estimated completion of delivery. Upon completion of delivery, the tracking is terminated (automatic opt-out). |
| US09691089B2 |
User to website guaranteed shopping
One embodiment is directed toward a process for a merchant inspection, where a guaranteed shopping server inspects online merchants to ensure they are reliable, financially stable, and committed to providing a great online shopping experience to the buyer/user. Next, this service monitors merchants on a regular basis, to ensure they deliver on their terms of sale, thus assuring purchasers of an overall safe online experience. Next, the guaranteed shopping service provides, a guarantee for added peace of mind for the purchaser. In accordance with one embodiment, a guarantee is provided to the buyer including ID theft protection, a purchase guarantee and a lowest price guarantee. As with other type of guarantees, certain restrictions and terms may apply. If a buyer does experience a problem with an online merchant, a benefit claim can be made and once the claim is validated, guaranteed shopping coverage can apply. |
| US09691085B2 |
Systems and methods of natural language processing and statistical analysis to identify matching categories
Combining the natural language processing of product descriptions and statistical analysis of payment data to classify consumers based on products purchased and merchants based on products sold. Systems and methods use natural language processing techniques to interpret the descriptions of item level purchase data to classify products that have been purchased by customers into micro-categories. Statistical deviation methods are applied to the payment data to calculate normalized mean product cost, after removing outliers. After determining the micro-categories of the products purchased and the mean product cost of the purchased products, the system and methods classify consumers and merchants into categories based at least in part on the product micro-categories, mean costs, and relative volume of product types sold by merchants to predict which consumers are likely to purchase from which merchants. |
| US09691083B2 |
Opportunity identification and forecasting for search engine optimization
A method of optimizing placement of references to an entity includes identifying at least search term to be optimized, determining a score for results of a search of a network with respect to the entity, determining costs associated with improving the score, and determining values associated with improving the score. |
| US09691082B1 |
Systems, devices, and methods for providing a dynamic subscription update feature in a wireless communications network
Systems, devices, and methods for providing a dynamic subscription update feature in a wireless communications network are disclosed herein. An exemplary system for providing a dynamic subscription update feature in a wireless communications network is configured to receive offline data and in-call data from a plurality of network entities for use in determining, in accordance with one or more rules, whether at least one subscriber is eligible to receive a subscription update offer and receive a response message indicating whether the at least one subscriber accepts or declines the offer. A device configured to receive a subscription update offer and respond with an acceptance or decline message is disclosed. Methods for operating the aforementioned system and device are also disclosed. |
| US09691077B2 |
Systems and methods for making awards based on telephony activity
An award system associated with a telephony communications system analyzes one or more users' telephony activity to determine if the telephony activity satisfies certain predetermined award rules. If a single user's telephony activity satisfies one or more award rules, the system makes an award to the user. The making of an award can include posting the award on a social networking site with which the user is associated. The analysis can also include collecting information about a predetermined type of telephony activity for multiple users of the system, and determining which of the multiple users has experienced the most of the predetermined type of telephony activity. An award is then granted to those users who experienced the most of the predetermined type of telephony activity. |
| US09691076B2 |
Demand response system having a participation predictor
A demand response management system having a participation predictor. There may be a storage device having information collected about past behavior, related to participation in a demand response program, about a customer. The information may incorporate determining a period of time since the customer last participated in a demand response program, a frequency of participation in demand response events by the customer, and a size of energy loads of the customer. A model of the customer may be developed from this and other information. A processor may be used to collect and process the information, develop a model, and to make a prediction of a customer's being selected to participate in an event based on the various operator selectable criteria. |
| US09691075B1 |
Name comparison
The present disclosure extends to comparing two or more names in a database of contact records. In embodiments, systems of the present disclosure execute a comparison of submitted names to determine if the records should be linked and/or merged. Embodiments of the present disclosure can compensate for irregularities in the database of contact records, including inconsistent name prefixes and suffixes, misspellings, typographical errors, misordered first/last names, and nicknames. |
| US09691068B1 |
Public-domain analyzer
Some implementations include searching for and analyzing public-domain-status information about works (such as e-books) over the Internet. A computer system may search for works recently made available online that are categorized as being in the public domain. Associated metadata is analyzed to generate a confidence level regarding whether the works are in the public domain or protected by copyright. Based on the confidence level, decisions can be made, such as whether to make the works available for free in a particular country. |
| US09691067B2 |
Validation database resident on a network server and containing specified distinctive identifiers of local/mobile computing devices may be used as a digital hardware key in the process of gaining authorized access to a users online website account such as, but not limited to, e-commerce website account, online financial accounts and online email accounts
The present invention consists of methods whereby local/mobile computing devices are registered by collecting a set of hardware and/or software distinctive identifiers to be saved in a validation database residing on a validation database server/Web server, such that the local/mobile computing device can be used as a digital hardware key for right of access and authorization of electronic transactions. This is done by comparing a regenerated set of hardware and/or software distinctive identifiers with those previously registered in the validation database in order to validate the identity of the local/mobile computing device. The invention consists of a first software program executing on a local/mobile computing device that generates the set of hashed and/or encrypted hardware and/or software distinctive identifiers and a second software program resident residing on a validation database server/Web server that manages the validation database. |
| US09691065B2 |
Automated transactions clearing system and method
Embodiments of the present invention are related to systems and methods of verifying the integrity of transactions that traverse through complex system workflows, and particularly, verifying the integrity of financial and non-financial transactions that traverse through a plurality of financial systems making up one or more system workflows. In one embodiment, a clearing system is disclosed to include a central clearing engine configured for processing a plurality of transactions by retrieving transaction data of at least one transaction of the plurality of transactions from at least one data source based on a selection received. After parsing the transaction data, the central clearing engine may verify transaction data integrity based on the transaction data and determine a result, and generate a report based on the result. |
| US09691064B2 |
System for packaging, processing, and activating a bundled greeting and gift card
A greeting card stored-value card combinations and methods of forming said combinations are provided. In one embodiment, these combinations include a greeting card comprising means for affixing a stored-value card thereto. These combinations also include a stored-value card affixed to the greeting card. A single identifier, such as a Stock-Keeping Unit (SKU) or a Universal Product Code (UPC), is assigned to the bundle that uniquely identifies the bundled greeting card and stored-value card. The single identifier provides identification means allowing the stored-value card to be activated. A single capture of the single identifier enables the customer to both purchase the greeting card stored-value card combination product as well as to activate the store-value card. |
| US09691059B1 |
Systems and methods for transactions using an ATM/credit/debit card and a second communications channel to an account holder's bank
Systems and methods for performing a transaction with a headless point-of-sale or automated teller machine (ATM) device are disclosed using a card having a second communications path to a financial services provider. A card having a display and radio frequency (RF) communications module may be authenticated with a headless point-of-sale device using a short-range RF communications link. Characteristics of the card may be set prior to the transaction. Transaction information may be provided to the display of the card from the headless point-of-sale device. A customer may confirm the transaction at the card using a touch-sensitive input area. During the processing, a communication may be made over the second communications path to authorize the transaction independently of the transaction processing path. A transaction may then be completed at the headless point-of-sale device. |
| US09691058B2 |
Automated budgeted transfer process for linked accounts
Embodiments for linking accounts and transferring funds between linked accounts include system for receiving financial account data and identifying at least one funding account and one or more receiving accounts from the account data. The systems determine a mapping strategy for linking the at least one funding account and one or more receiving accounts and link the at least one funding account and the one or more receiving accounts according to the mapping strategy. The systems further set parameters and execute a transfer of funds between the linked accounts in accordance with the parameters. |
| US09691054B2 |
Method for nonintrusive identification and ordering of component parts
A noninstrusive system and method of scanning an object having component parts includes a vendor based data repository of component parts and a matching processor to receive a scanned image representative of the assembled object and to provide suggested and/or matched component parts for purchase from the vendor. |
| US09691052B2 |
Method, a system and a server for business appointment scheduling using text messages
The present disclosure relates to a method, a system and a server using text messages for scheduling of business appointments. A server receives an initial text message having been transmitted over a wireless network by a mobile terminal. The initial text message includes a function keyword. Based on the function keyword, the server determines a type of requested service and creates a unique page identification for a scheduler page. The server transmits toward the mobile terminal over the wireless network, a reply text message including the unique page identification. The server detects an access of the scheduler page by the mobile terminal, the access including an entry of appointment data. An appointment is scheduled in the scheduler page, using the entered appointment data. |
| US09691048B1 |
Photoconductive multi-resonator chipless RFID
A chipless RFID transponder is disclosed. The transponder comprises an antenna and a plurality of resonant structures that together define a spectral signature of the RFID transponder. Each of the resonant structures comprises conductive portions separated by interstitial regions. A reversible photoconductive material is disposed in the interstitial regions of the resonant structures between the conductive portions. The photoconductive material is positioned so as to shift the spectral signature of the RFID when exposed to radiation. |
| US09691047B2 |
Observation platform for using structured communications
In a method of using structured communication in a plurality of observation platforms, within a first observation platform associated with a first radio range, a second communication device associated with a computer system receives a signal from a first communication device. A first characteristic of the signal corresponds to an audible source and a second characteristic of the signal corresponds to information indicative of a geographic position of the first communication device. The computer system: recognizes a first user associated with the first communication device; derives context information for the signal; and relays the signal, via a computer network, to a second computer system associated with a second observation platform. The second observation platform is associated with a second radio range outside of the first radio range. In the second observation platform, the signal is relayed via the second computer system to a derived destination in the second observation platform. |
| US09691043B2 |
Device and method for cross-referencing
A sample, which is embedded in a paraffin block, is placed on a tissue cassette (22) which carries a label (20) which may a bar code. When the sample is to be processed, the cassette is given to a microtome operator who scans the label (20) with, for example, a bar code reader (4). Scanning causes information to be displayed on a screen (12) and the operator verifies that what is on the screen matches what was on the label. The paraffin block is then placed in a microtome chuck (26) and sections are cut from the block. Concurrently with, or prior to sectioning, a number of slides (18) are dispensed (2) and are printed with a label (16) so that the sections can be mounted thereon. The slide label (16) is related to the cassette label (20). If the operator does not verify that the information displayed on the screen matches the information on the cassette label (20) and/or does not place the paraffin block in the microtome chuck (26) within an allocated time interval after scanning the cassette label (20), dispensing and labelling of slides (18) and/or operation of the microtome is prevented. This ensures accurate identification of samples within a laboratory as it does allow the operator the opportunity lose track of which samples were being processed. |
| US09691042B2 |
E-Business value web
A method and system is provided to manage and track changes in enterprise architectures. The invention provides a hierarchical visual management tool to manage and update relational information within an enterprise in a controlled fashion. The relationship may be maintained in a database and displayed via graphical user interface. Enterprise assets are categorized into such categories as goals, customer values or requirements, capabilities, resources, and the like. A hierarchy is constructed so that relationships between these various categories are identified and captured using the invention. Weights may be assigned to each element of the categories so that any proposed change to an enterprise architecture may be viewed so that a value can be ascertained and compared between other values of other proposed changes. In this manner, tracking and management of evolutionary changes to an architecture may be accomplished using relational information. |
| US09691037B2 |
Methods and systems for processing schedule data
Methods and systems comprising receiving travel request data; retrieving schedule data associated with the travel request data, the schedule data being further associated with a scheduled travel time; retrieving availability data associated with the travel request data, the availability data being further associated with an available travel time; generating representation data representing the schedule data and the availability data, the representation data representing the schedule data and/or the availability data differently based on a whether an itinerary complies with an organization's travel policies; and sending the representation data. |
| US09691035B1 |
Real-time updates to item recommendation models based on matrix factorization
A network-based enterprise or other system that makes items available for selection to users may implement real-time updates to item recommendation models based on matrix factorization. An item recommendation model may be maintained that is generated from a singular value decomposition of a matrix indicating selections of items by users. A user-specific update to the item recommendation model may be calculated in real-time for a particular user such that the calculation may be performed without performing another singular value decomposition to generate an updated version of the item recommendation model. Item recommendations may then be made based on the user-specific update and the item recommendation model. In various embodiments, the item recommendations may be made in response to an indication or request for item recommendations for the particular user. |
| US09691032B2 |
Knowledge discovery from belief networks
Techniques are disclosed herein for making predictions with respect to how content consumers will interact with a digital asset. For example, in the context of website visitors browsing digital assets provided via a website, web traffic data can be collected and modeled using a belief network. The belief network may represent a probability distribution for a set of variables that define the web traffic data. Examples of such variables include browser type, browsing session duration, geographic location, visitor demographic characteristics, and a browsing outcome. Certain of the embodiments disclosed herein can be used to extract knowledge from the belief network, thereby allowing statistical inferences to be drawn with respect to how certain classes of website visitors will interact with the website. The influence of one or more first variables (for example, geographic location) can be quantified with respect to one or more second variables (for example, the successful result indicator). |
| US09691031B2 |
Efficient fact checking method and system utilizing controlled broadening sources
An efficient fact checking system analyzes and determines the factual accuracy of information and/or characterizes the information by comparing the information with source information. The efficient fact checking system automatically monitors information, processes the information, fact checks the information efficiently and/or provides a status of the information. |
| US09691027B1 |
Confidence level threshold selection assistance for a data loss prevention system using machine learning
Machine-learning based detection (MLD) profiles can be used to identify sensitive information in documents. The MLD profile can be used to generate a confidence value for the document that expresses the degree of confidence with which the MLD profile can classify the document as sensitive or not. In one embodiment, a data loss prevention system provides or suggests a confidence level threshold to a user of the data loss prevention system by providing a confidence level threshold for the MLD profile to the user, the confidence level threshold to be used as the boundary between sensitive data and non-sensitive data. In one embodiment the provided confidence level threshold is determined by scanning a random data set using the MLD profile. |
| US09691017B2 |
Recombinase-based logic and memory systems
The invention provides, inter alia, recombinase-based systems that provide for integrated logic and memory in living cells. |
| US09691015B2 |
Memory card adapter and memory apparatus
Memory card adapters and/or a memory apparatuses may be provided. For example, a memory card adapter including a main housing section that corresponds to a memory card socket of a first standard, the main housing section including a card housing section, the card housing section configured to house a memory card of a second standard different from the first standard therein, a first surface of the main housing section defining a through-hole, the through-hole configured to expose a connection pin of the memory card to be housed in the housing section to an outside of the housing section, and a second surface of the main housing section defining a card insertion hole, the second surface being different from the first surface, the card insertion hole configured to receive the memory card into the card housing section may be provided. |
| US09691009B2 |
Portable optical reader, optical reading method using the portable optical reader, and computer program
The present invention provides a portable optical reader, an optical reading method using the portable optical reader and a computer program capable of detecting a high possibility of a reading error and notifying a user of a possibility of a reading error. A character string as a reading target is imaged and a character string is recognized based on the captured image. A plurality of reading formats defining an attribute of the character string is stored, and a first reading format matched with the recognized character string among a plurality of stored reading format is searched. Among the plurality of stored reading formats, a second reading format in which a character string matched with the first reading format as a partial character string is searched. Based on the search result, a possibility of a reading error regarding the recognized character string is notified. |
| US09691000B1 |
Orientation-assisted object recognition
A user attempting to obtain information about an object can capture image information including a view of that object, and the image information can be used with a matching or identification process to provide information about that type of object to the user. Information about the orientation of the camera and/or device used to capture the image can be provided in order to limit an initial search space for the matching or identification process. In some embodiments, images can be selected for matching based at least in part upon having a view matching the orientation of the camera or device. In other embodiments, images of objects corresponding to the orientation can be selected. Such a process can increase the average speed and efficiency in locating matching images. If a match cannot be found in the initial space, images of other views and categories can be analyzed as well. |
| US09690999B2 |
Remote recognition processing system and method
A computerized method for intelligently distributing computer processing of mail piece scan images across a plurality of mail piece scan image processors. The method can include receiving a mail piece scan image from a mail piece scan image job requestor and selecting one of a plurality of scan mail piece scan image processors to process said mail piece scan image. The mail piece scan image can be transmitted to said one of a plurality of plurality of mail piece scan image processors and a mail piece scan image processing result can be received from said one of a plurality of plurality of mail piece scan image processors. Post-processing operations can be performed based on said mail piece scan image processing result. The mail piece scan image processing result can be transmitted to said mail piece scan image processing requestor. |
| US09690989B2 |
Fossil recognition apparatus, systems, and methods
In some embodiments, an apparatus and a system, as well as a method and an article, may operate to acquire fluid image information from an imaging device having a field of view including fluid, the fluid image information including fossil image information. Additional activities may include processing the fossil image information to identify fossil types in the fluid as data that associates the fossil types with a formation from which the fluid was acquired, determining the location of a first borehole in the formation based on the data and offset records associated with a second borehole, and publishing the data in conjunction with indications of the location. Additional apparatus, systems, and methods are disclosed. |