| Document | Document Title |
|---|---|
| US09660784B2 |
Method and apparatus providing inter-transmission point phase relationship feedback for joint transmission CoMP
Systems and techniques for joint transmission cooperative multi-point. A set of n CSI reference signal resources are to be measured by a user device. The n CSI reference signal resources include at least one CSI reference signal resource spanning over at least two transmission points. Channel state information feedback corresponding to each CSI reference signal resource is configured. Upon receiving CSI from the user device, at least one precoder is selected for coherent joint cooperative multipoint transmission based on inter-transmission point phase relationship information. A co-phasing factor is derived from transmitted precoders over a cross-cell CSI reference signal resource, the derivation including transmission of reference signals using first and second precoding vectors on two ports, computation of a third vector using feedback based on the precoded reference signals, and computation of the co-phasing factor based on the first, second, and third vectors. |
| US09660779B2 |
Method, device, and system for transmitting reference signal
The present invention relates to the technical field of radio communications, and specifically relates to a method, device, and system for transmitting a reference signal, for use in solving the problem in the prior art that vertical-dimension channel estimation cannot be supported and thus 3D beamforming is not supported. The method of embodiments of the present invention comprises: a network side determines a subframe (31) used for bearing the reference signal, determines a pilot frequency port (32) of the reference signal, and transmits in the determined subframe the reference signal configured in the pilot frequency port, where all of the pilot frequency ports comprise at least one row of horizontal-dimension pilot frequency ports and one column of vertical-dimension pilot frequency ports, the reference signal configured in the horizontal-dimension pilot frequency ports is a horizontal-dimension reference signal, and the reference signal configured on the vertical-dimension pilot frequency ports is a vertical-dimension reference signal (33). Because the embodiments of the present invention are capable of transmitting the vertical-dimension reference signal, implementation of channel estimation on the vertical-dimension pilot frequency ports is allowed, and implementation of a dynamic 3D beamforming technology is allowed. |
| US09660776B2 |
Method and apparatus for providing antenna diversity in a wireless communication system
Apparatus and methods implementing transmission schemes that can flexibly achieve the desired spatial multiplexing order, spatial diversity order, and channel estimation overhead order are provided. For example, an apparatus is provided that includes a processor configured to allocate different subcarriers to different antennas at different times. A memory is coupled to the processor. The processor can be further configured to map a traffic channel to a specific sequence of the different subcarriers at the different times. The processor can also be further configured to transmit the traffic channel on only one of the different subcarriers at each time in the different times. The processor can be integrated with at least one of a base station and a terminal. |
| US09660775B2 |
System and method for punctured pilot transmission in a wireless network
In accordance with an embodiment, a method of operating a base station configured to communicate with at least one user device includes transmitting a first group of resource elements that include a time and a frequency. At least one of the first group's resource elements includes a reference element. It is determined if the at least one user device will decode a further resource element using the reference element of the at least one of the resource elements of the first group of resource elements. Based on the determining, if the user device will decode the further resource element, a second group of resource elements is transmitted, where at least one of the resource elements of the second group of resource elements corresponding with the at least one of the resource elements of the first group does not include a reference element. |
| US09660774B2 |
Determining and managing upstream profiles in DOCSIS 3.1 network environments
An example method for determining and managing upstream profiles in Data Over Cable Service Interface Specification (DOCSIS) 3.1 network environments is provided and includes determining, at a Converged Cable Access Platform (CCAP) core, channel conditions independent of any channel effect over a hybrid fiber coaxial (HFC) network between a remote physical layer (R-PHY) entity coupled to the CCAP core and a cable modem (CM) in the DOCSIS 3.1 network environment, and assigning an upstream profile to the CM based on the channel conditions. In specific embodiments, the channel conditions include signal to noise ratio (SNR), modulation error ratio (MER) or group delay. In some embodiments, assigning the upstream profile includes determining a quadrature amplitude modulation (QAM) order based on the SNR or MER, and determining a pilot pattern based on the group delay, the combination of the QAM order and the pilot pattern identifying the upstream profile. |
| US09660773B2 |
Method, user equipment and base station for controlling discontinuous reception (DRX) in wireless communication system
A method, a user equipment, an eNB are provided for controlling DRX in a wireless communication system. A method includes receiving, from a master evolved Node B (MeNB), an indication that a Slave eNB (SeNB) is to be monitored; and monitoring the SeNB, in response to the indicator. The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). |
| US09660769B2 |
Scalable service in a wireless communication system
A method for providing scalable service in a wireless communication system is disclosed. In this method, the transmitting side device performs initial transmission of base layer signals to a user equipment (UE) based on a HARQ (Hybrid Automatic Repeat Request) scheme, and performs transmission of enhancement layer signals to the UE after finishing the initial transmission of the base layer signals. The base layer signals and the enhancement layer signals are for one scalable service. The base layer signals can be independently used at the UE without the enhancement layer signals, while the enhancement layer signals cannot be used at the UE without the base layer signals. The transmitting side device further performs retransmission of the base layer signals determined to be retransmitted based on the HARQ scheme while performing the initial transmission of the enhancement layer signals. |
| US09660765B1 |
Method and apparatus for broadcast information reception in wireless communication systems
Low latency wireless communication applications require highly dynamic allocation of resources. Providing allocation information on a highly dynamic basis increases the overhead of control signaling for allocation. A technique known as blind decoding is used to reduce the control signaling overhead for allocation information. However, blind decoding may occasionally lead to invalid detection of allocation messages which in turn may lead to a number of problems such as wasted bandwidth, increased power consumption, reduced throughput, etc. A method and apparatus are disclosed that detect the invalid allocation messages by maintaining a record of previously received allocation messages and using it to check the validity of the newly received allocation messages. |
| US09660764B2 |
Broadcast transmitter and method of processing broadcast service data for transmission
A method is provided for processing broadcast data in a broadcast transmitter. Broadcast service data is randomized. The randomized broadcast service data is first-encoded to add parity data to the randomized broadcast service data. The first-encoded broadcast service data is second-encoded. The second-encoded broadcast service data is first interleaved. The first-interleaved broadcast service data is second-interleaved. Signaling data is encoded for signaling the broadcast service data. The encoded signaling data is third-interleaved. The third-interleaved signaling data is fourth interleaved. A frame is transmitted that is divided into a data region including the second-interleaved broadcast service data, a first signaling region including the fourth-interleaved signaling data and a second signaling region that includes at least one symbol that is used for synchronization and channel estimation. The frame includes known data. The encoded signaling data includes information for identifying the code rate and information related to the known data. |
| US09660763B2 |
Methods and apparatus employing FEC codes with permanent inactivation of symbols for encoding and decoding processes
Encoding of a plurality of encoded symbols is provided wherein an encoded symbol is generated from a combination of a first symbol generated from a first set of intermediate symbols and a second symbol generated from a second set of intermediate symbols, each set having at least one different coding parameter, wherein the intermediate symbols are generated based on the set of source symbols. A method of decoding data is also provided, wherein a set of intermediate symbols is decoded from a set of received encoded symbols, the intermediate symbols organized into a first and second sets of symbols for decoding, wherein intermediate symbols in the second set are permanently inactivated for the purpose of scheduling the decoding process to recover the intermediate symbols from the encoded symbols, wherein at least some of the source symbols are recovered from the decoded set of intermediate symbols. |
| US09660757B2 |
Low latency fiber optic local area network
The present invention is directed to a low latency fiber optic local area network with a network and a plurality of nodes connected through optical fibers. Each node has a plurality of bi-directional input/output interfaces. Each bi-directional input/output interface has a demultiplexer, at least one optical power coupler, a plurality of wavelength converters, and a plurality of internal optical waveguides. The internal optical waveguides extend from each wavelength converter and are for communication with the demultiplexer, the input fiber optic interface, and the optical fiber. Each optical power coupler has a fiber optic output interface for communication with other nodes, and each demultiplexer has a input fiber optic interface for communication with other nodes. |
| US09660756B2 |
Method for split spectrum signalling in an optical network
The example embodiments presented herein are directed towards an Optical Network Element, ONE, node (14), and corresponding method therein, for establishing multiple spectral routing in an optical transport network. The establishment of the multiple spectral routing features the use of a Split-Spectrum Label, SSL, (11) which comprises multiple definitions for spectral slots, where each definition has an absolute starting and an absolute ending frequency allocation. |
| US09660753B2 |
Optical add/drop multiplexer using integrated optical components
An optical add/drop multiplexer incorporates an integrated receiver module and an integrated transmitter which are interfaced to an intervening electrical network to provide an add/drop/pass-through functionality. The receiver module incorporates a wavelength demultiplexer which is in turn combined with optical/electrical converters PIN photodiodes, and amplifiers on a per wavelength basis to output a plurality of parallel electrical signals in response to a common optical input. The transmitter module combines an integrated plurality of drive circuits and lasers for converting a plurality of parallel input electrical signals to a plurality of optical signals, on a per wavelength basis, which in turn are coupled via an optical wavelength multiplexer to a common output optical fiber. The interconnected electrical network, ring mesh or tree, can provide a reconfigurable electrical add/drop interface to other portions of the network. |
| US09660752B2 |
Wavelength selective switch (WSS) based multiplexing architecture
An apparatus may include a plurality of wavelength selective switches (WSSs). The apparatus may include a plurality of transmitters. The transmitters may transmit a plurality of super-channels. The apparatus may include a plurality of passive power splitters corresponding to the plurality of transmitters. The plurality of passive power splitters may receive the plurality of super-channels. The plurality of passive power splitters may generate a respective set of power-split super-channels for each super-channel of the plurality of super-channels. The plurality of passive power splitters may transmit each power-split super-channel of the respective set of power-split super-channels to a corresponding WSS of the plurality of WSSs. A WSS, of the plurality of WSSs, may receive a plurality of power-split super-channels, of the respective sets of power-split super-channels, from the plurality of passive power splitters. The WSS may selectively route a portion of the plurality of power-split super-channels toward a receiver. |
| US09660749B2 |
Method for configuring a backhaul link subframe in a wireless communication system to which a carrier aggregation scheme is applied and an apparatus for the same
A method for configuring a backhaul link subframe in a wireless communication system to which a carrier aggregation scheme is applied and an apparatus for the same are disclosed. The method comprises determining one of a plurality of subframe configurations as a first subframe configuration for a primary component carrier allocated to the relay node; configuring subframe configuration candidates for one or more secondary component carriers allocated to the relay node on the basis of the determined first subframe configuration; determining a second subframe configuration for each of the one or more secondary component carriers by using the configured subframe configuration candidates; and transmitting and receiving a signal to and from the relay node in accordance with the first subframe configuration and the second subframe configuration. |
| US09660744B1 |
Systems and methods for adaptive frequency synchronization
In one embodiment, a method includes receiving transmission segments from at least one device over a plurality of channels pursuant to a channel-switching schedule, the channel-switching schedule comprising an iteratively-repeated channel sequence. The iteratively-repeated channel sequence comprises a plurality of channels, the channel-switching schedule specifying an assigned transmission duration for each channel. In addition, the method includes, for at least one channel of the plurality of channels, detecting interference during a time segment of the assigned transmission duration, the time segment comprising at least one of a beginning portion and an ending portion of the assigned transmission duration. Further, the method includes responsive to the detected interference, determining to shift, by a specified quantity of time, a future channel switch indicated by the iteratively-repeated channel sequence. |
| US09660742B2 |
Detecting signal leakage in cable networks
A signal leakage in a cable network may be detected by using a test device to obtain a spectrum of an electromagnetic wave propagating in vicinity of the cable network, and automatically detecting QAM channels in the obtained spectrum by detecting characteristic spectral roll-offs at boundary frequencies between QAM channels of the cable network. A test device may be used to determine which QAM channels are currently active on the cable network, thereby facilitating automatic QAM signal leakage detection. |
| US09660739B2 |
System and methods of testing adaptive antennas
The technology disclosed relates to systems and methods for testing adaptive antennas via a multi-probe anechoic chamber, which includes the emulation of real world conditions of a radio frequency (RF) signal reaching a device-under-test (DUT). The technology disclosed can be applied to test and evaluate a range of changed conditions. In one case, beamforming scenarios use separate spatial desired and interference signals, and the results can be compared to uniform interference. Based on performance for a segment of a test profile, the segment can be modified or expanded: shortened, repeated, or repeated with a modification—to fully evaluate the aspect being tested. Also, a dynamic profile that is utilized to evaluate a first device can be saved and repeated as a fixed profile for further testing of a first or second device. |
| US09660735B1 |
Systems and methods for mitigating interference at an access node
Systems and methods are also described for mitigating interference at an access node. It may determined, based on an interference metric for a first wireless device exceeding an interference criteria, that communication between the first wireless device and a cell of an access node is experiencing interference from a neighboring cell. At least one neighboring cell in which one or more beamformed signals are transmitted is identified as a potential interference source. The identified neighboring cell may be instructed to terminate transmission of a beamformed signal to at least a second wireless device. It may then be determined whether the interference metric for the first wireless device continues to exceed the interference criteria after the termination of the beamformed signal. And the second wireless device may be identified as an interference source when the interference metric for the first wireless device does not continue to exceed the interference criteria. |
| US09660733B2 |
Signal processing apparatus, signal processing method, and signal processing system
A signal processing apparatus includes: a filter; and a filter control circuit, wherein the filter control circuit is configured to: detect a power of signals output from the filter; determine one of a plurality of numerical ranges to which the power belongs; update a filter coefficient of the filter according to a determination result; count a number of the signals having the power of a first value or more; set an invalid area which becomes a target not to be determined for each of one or more boundaries between the plurality of numerical ranges when the number of the signals becomes a second value or more; and control a width of the invalid area based on the number of signals. |
| US09660726B2 |
LED light broad band over power line communication system
An LED light and communication system is in communication with a broadband over power line communications system. The LED light and communication system includes at least one optical transceiver. The optical transceiver includes a light support having a plurality of light emitting diodes and at least one photodetector attached thereto, and a processor. The processor is in communication with the light emitting diodes and the at least one photodetector. The processor is constructed and arranged to generate a communication signal. |
| US09660725B2 |
Identifier announcement and detection scheme for PoE fixtures
Techniques are presented herein to enable identification of light fixtures. A light fixture modulates light emitted by the light fixture with an identifier associated with the light fixture. The identifier may be encoded or encrypted before it is modulated. In one example, the identifier is a Universally Unique Identifier (UUID). A user device is positioned to detect light emitted by the light fixture. The user device demodulates the light to obtain the identifier. The identifier, time and location associated with detection of the identifier are sent to a management entity for use in provisioning the light fixture on a network. |
| US09660724B2 |
Communication apparatus and storage medium
There is provided a communication apparatus including a communication unit having an optical communication scheme and a different communication scheme from the optical communication scheme, a level setting unit configured to set a security level in data communication, and a communication scheme switching unit configured to switch communication schemes of the communication unit in accordance with the security level that is set by the level setting unit. |
| US09660721B2 |
Optical detector and amplifier for RF-detection having a position dependent capacitor with a displaceable membrane
An optical detector for detecting radio frequency (RF) signals, the optical detector comprising a light source and a photodetector, and an electrical circuit comprising a position dependent capacitor and a bias voltage source adapted for providing a bias voltage for biasing the position dependent capacitor, the position dependent capacitor comprising an electrode and a membrane being displaceable in reaction to RF signals incident on the membrane, the membrane being metallized, has a thickness of less than 1 μm and a quality factor, Qm, of at least 20,000, and the distance between the membrane and the electrode being less than 10 μm. |
| US09660717B2 |
Base station signal matching device and relay device including the same
A base station signal matching device configured to receive a base station signal from a base transceiver station (BTS), the base station signal matching device is embedded in a relay device, and the base station signal matching device includes a signal attenuation unit configured to receive the base station signal and attenuate the input power level of the base station signal; and a signal matching unit configured to receive the base station signal passing through the signal attenuation unit to match the base station signal suitable for signal processing of the relay device. |
| US09660715B2 |
Method for the detection of an electromagnetic signal by an antenna array, and device implementing said method
A method for detecting an electromagnetic signal comprises: applying to the received electromagnetic signal a plurality of time-frequency transforms, for each time/frequency cell of a given set of cells, calculating the energy of the vector made up of the spectra over all of the antenna elements, applying the following nonlinear function T to the result of the energy calculation: if the norm of the energy is below a first predetermined threshold s, the result of the function T is zero, if the norm of the energy is above or equal to the first threshold s, the result of the function T is equal to the norm of the energy minus the value of the first threshold s, integrating, over the set of time/frequency cells, the result of the nonlinear function T, comparing the result of the integration to a second predetermined threshold, to detect the presence of the signal. |
| US09660713B2 |
Method and apparatus for obtaining channel direction information
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE).The present disclosure discloses a method for obtaining channel direction information, which includes: transmitting a first detection signal and a second detection signal in at least one detection region, wherein there is differential information between the first detection signal and the second detection signal; receiving a signal receiving characteristic of the first detection signal and a signal receiving characteristic of the second detection signal from a receiver; and adjusting channel direction information (CDI) according to the signal receiving characteristic of the first detection signal and the signal receiving characteristic of the second detection signal. The present disclosure further discloses an apparatus for obtaining channel direction information. |
| US09660709B1 |
Systems and methods for calculating log-likelihood ratios in a MIMO detector
A method and a communication receiver have been described for calculating log-likelihood ratios in a communication receiver. The log-likelihood ratio is calculated for each bit of one or more subsymbols of each of the one or more spatial streams by computing effective noise on one or more spatial streams after considering noise terms resulting from MIMO detection estimates of the subsymbols on each spatial stream. Finally, signal to noise ratio is determined for one or more spatial streams from the effective noise and scaling bit log-likelihood ratios with the signal to noise ratio. |
| US09660701B2 |
Near field coupling devices and associated systems and methods
A near-field coupling device that may facilitate communications with a transponder is provided. The near-field coupling device may include a ground plane, a dielectric substrate, one or more conductive strips and a terminating load. The conductive strips together with the ground planes form coupling elements. The near-field coupling device further includes one or more switching elements for selectively connecting and disconnecting the coupling elements with a transceiver. The connected coupling elements define a total characteristic impedance. Using the switching element, the ratio between the total characteristic impedance of the connected coupling elements and the terminating load may be changed in order to adjust the distribution of an electromagnetic field along the coupling elements according to the type and position of the transponder to be processed. |
| US09660699B2 |
Detection apparatus, electric power receiving apparatus, electric power transmission apparatus, wireless electric power transmission system, and detection method
A method for wireless power transmission includes obtaining, via a Q-value circuit, first and second voltages at respective first and second nodes of a resonance circuit. The first and second voltages are effective to determine if foreign matter is present in a space affecting wireless power transmission. The method includes controlling a switching section between the Q-value circuit and the resonance circuit such that at least a part of the electric power transmission process occurs at a different time than when the first and second voltages are obtained. |
| US09660694B2 |
Radio unit and method performed by a radio unit operable in a base station system of a wireless communication network for reducing interference at the radio unit
Disclosed is a method performed by a radio unit (10) operable in a base station system of a wireless communication network, for reducing interference at the RU. The base station system comprises a baseband unit (30) the radio unit (10) and a plurality of radio heads (21-26) wherein the radio unit is connected to the plurality of radio heads via a number of metallic conductors (40), and wherein a signal is to be communicated to the radio unit at a first frequency range over one of the number of metallic conductors from one of the plurality of radio heads. The method comprises: detecting (206) if there is any near end crosstalk, NEXT, at a receiver of the RU, the receiver being connected to the one of the number of metallic conductors, and, when NEXT is detected, triggering (210) the one of the plurality of RHs to send the signal to be communicated over the one of the number of metallic conductors at a second frequency range different from the first frequency range where a lower NEXT is expected than at the first frequency range. Disclosed are also a corresponding radio unit and a computer program. |
| US09660693B1 |
Spatio-temporal signal monitoring
A spatio-temporal signal monitoring system includes a sampler configured to receive a radio frequency signal and obtain first compressive sensing measurements of said received signal at a first resolution level, and a signal detector configured to identify at least one signal of interest based on said first compressive sensing measurements and perform second compressive sensing measurements on said at least one signal of interest at a second resolution level, said second resolution level being higher than said first resolution level. The received signal may be analyzed as an array or image having two or more dimensions, based on frequency and on at least one other parameter, such as angle-of arrival, and may be analyzed at a higher level of resolution at the frequencies and angles corresponding to a signal of interest (SOI). Estimates of the frequency and/or the at least one other parameter may be generated by the system. The system may be used to monitor a wideband RF spectrum and/or track signals, such as frequency-hopping signals. |
| US09660690B2 |
Optimized data converter design using mixed semiconductor technology for flexible radio communication systems
A cellular radio architecture that includes a receiver module having a receiver delta-sigma modulator that converts analog receive signals to a representative digital signal. The architecture further includes a transmitter module having a transmitter delta-sigma modulator for converting digital data bits to analog transmit signals. Portions of the receiver and transmitter modules are fabricated with silicon germanium (SiGe) technologies and portions of the receiver and transmitter modules are fabricated with CMOS technologies. |
| US09660684B2 |
Housing for encasing a mobile computing device
An apparatus and a system for housing a device are described. The apparatus includes a housing that is configured such that a device may be fitted within the housing and thereby be protected, such as from shocks and/or liquid. The housing may include top and bottom members that may be removably coupled together so as to form the housing. Each top and bottom member includes a perimeter portion. The perimeter is defined by proximal and distal ends as well as opposing sides. The top and bottom members may include respective clasping mechanisms that extend along the perimeter of the top and bottom members and may be configured for engaging a third clasping mechanism, such as a locking comb or wedge feature. The clasping mechanisms are configured for coupling the top and bottom members with one another thereby sealing the housing, for instance, in a shock-proof and/or water tight seal. |
| US09660682B2 |
Apparatus for holding an electronic device
A holder for an electronic device includes a body, a first receptacle, and a second receptacle. The body includes a surface, a first end portion, a second end portion, a medial portion, and an attachment mechanism configured for attaching the body to a wearable band. The attachment mechanism includes one or more deformable attachment protrusions configured for insertion into one or more corresponding attachment apertures of the wearable band. The first and second receptacles are each configured for removably retaining the electronic device to the body. The first and second receptacles each define a respective cavity bounded by a stretchable opening. Each opening is configured to receive and retain a respective end of the electronic device as well as ends of other electronic devices having a range of sizes. |
| US09660677B2 |
Impulsive noise rejection
A method of rejecting impulsive noise in an OFDM receiver is described. The impulsive noise is rejected using channel state information (CSI) and is performed in the frequency domain. A noise power estimate (furthermore referred to as a noise value) is measured for a single OFDM symbol and compared to a threshold value, which may be generated based on a short-term average of OFDM symbols not corrupted by impulsive noise or predicted based on a small number of previously measured OFDM symbols not corrupted by impulsive noise. If the noise estimate for the particular OFDM symbol exceeds the threshold value, the CSI for that symbol is derated (i.e. modified) to reduce the influence of the information from this symbol on the decoding process. |
| US09660675B2 |
Digital predistortion and uptilt and cable communication
Otherwise incompatible digital predistortion and uptilt can be used together, such as in a cable television or other cable communications system having a frequency-dependent signal loss at high frequencies. The predistortion can be used to compensate for a nonlinear gain compression of a power amplifier at higher frequencies. Additional uptilt and equalizer circuits can be included to address deleterious distortion effects that may otherwise arise by using predistortion and uptilt together. Training and adaptation of various components are described. Fine and coarse uptilt adjustments can be provided. |
| US09660672B2 |
Method for operating electronic device for RF signal transmission and electronic device for the same
A method for operating an electronic device for transmission of a radio frequency (RF) signal includes selecting output power of a power amplifier (PA) required upon transmission of a signal with a second frequency through an antenna, determining a first PA operation voltage corresponding to the selected output power using first information stored in a memory of the electronic device and second information regarding a PA operation voltage corresponding to first output power of the PA at the second frequency, supplying the determined first PA operation voltage to the PA, and supplying input power corresponding to the selected output power at the second frequency to the PA. Other various embodiments are possible. |
| US09660671B2 |
Transformer and communication terminal device
In a transformer, first and second coils are provided on different substrate layers of a multilayer body. The first and second coil conductors are interlayer-connected to each other by interlayer connection conductors. A coil aperture defined by the first coil conductor and a coil aperture defined by the second coil conductor overlap each other when seen in a plan view from a laminating direction of the multilayer body. The first and second coil conductors are connected to each other at at least two places with the interlayer connection conductors interposed therebetween. A parallel connection portion including a first portion of the first coil conductor and a first portion of the second coil conductor is provided, and a series connection portion including a second portion of the first coil conductor and a second portion of the second coil conductor is provided. |
| US09660669B2 |
Encoding apparatus and encoding method thereof
An encoding apparatus which performs encoding such as Low Density Parity Check (LDPC) encoding is provided. The encoding apparatus includes: an encoder encoding input bits using a parity check matrix including a plurality of blocks, each being formed of a first information word sub-matrix and a first parity sub-matrix arranged next to each other, and a second information sub-matrix and a second parity sub-matrix arranged next to each other; a bit determiner determining a value of a last sub-parity bit among sub-parity bits generated by encoding the input bits with respect to a first block among the plurality of blocks; and a bit modifier reversing values of bits generated by encoding the input bits with respect to a second block next to the first block based on the value of the last parity bit among the sub-parity bits generated by the encoding with respect to the first block. |
| US09660657B2 |
Spread spectrum clock generator
A spread spectrum clock generator includes: a phase comparing unit that receives a reference clock signal and a feedback clock signal, and generates a control voltage corresponding to a phase difference between the reference clock signal and the feedback clock signal; a voltage-controlled oscillator that oscillates at an oscillating frequency corresponding to the control voltage, and generates an output clock signal; a delta-sigma modulator that receives a waveform signal for controlling spreading of a spectrum of the output clock signal, and outputs bits larger than 1 bit based on the waveform signal; a control circuit that controls a multiplication number according to an output signal of the delta-signal modulator; and a divider that generates the feedback clock signal by dividing the output clock signal according to the multiplication number controlled by the control circuit, and supplies the feedback clock signal to the phase comparing unit. |
| US09660655B2 |
Ultra low phase noise frequency synthesizer
A system for providing ultra low phase noise frequency synthesizers using Fractional-N PLL (Phase Lock Loop), Sampling Reference PLL and DDS (Direct Digital Synthesizer). Modern day advanced communication systems comprise frequency synthesizers that provide a frequency output signal to other parts of the transmitter and receiver so as to enable the system to operate at the set frequency band. The performance of the frequency synthesizer determines the performance of the communication link. Current days advanced communication systems comprises single loop Frequency synthesizers which are not completely able to provide lower phase deviations for errors (For 256 QAM the practical phase deviation for no errors is 0.4-0.5°) which would enable users to receive high data rate. This proposed system overcomes deficiencies of current generation state of the art communication systems by providing much lower level of phase deviation error which would result in much higher modulation schemes and high data rate. |
| US09660652B2 |
Differential driver with pull up and pull down boosters
A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground. |
| US09660647B2 |
Calibration device and memory system having the same
A calibration device for use in a memory system includes a bias circuit providing bias current, and a calibration unit generating a control signal for calibration. The bias circuit includes an internal resistor and measures a second bias current generated by mirroring a first bias current through the internal resistor, and adjusts the second bias current to generate the second bias current in a predetermined range as a third bias current. The calibration unit generates the control signal based on a comparison result between a reference voltage and a voltage generated based on the third bias current through an adjustable resistor. |
| US09660641B2 |
Devices with signal characteristic dependent control circuitry and methods of operation therefor
An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device. |
| US09660640B2 |
Switching circuits having ferrite beads
A circuit includes an electronic component package that comprises at least a first lead, a III-N device in the electronic component package, a gate driver, and a ferrite bead. The III-N device comprises a drain, gate, and source, where the source is coupled to the first lead. The gate driver comprises a first terminal and a second terminal, where the first terminal is coupled to the first lead. The ferrite bead is coupled between the gate of the III-N transistor and the second terminal of the gate driver. When switching, the deleterious effects of the parasitic inductance of the circuit gate loop are mitigated by the ferrite bead. |
| US09660634B1 |
Load driving circuit
When a battery power supply voltage is applied to a drain of an output transistor at activation time, a drain-gate path of the output transistor is coupled and the output transistor tends to turn on by itself. A simplified power supply circuit operates in response to current conduction of a drain-source path of the output transistor. The simplified power supply circuit is activated at earlier time than activation of a power supply voltage Vcc of a logic power supply circuit, when the simplified power supply circuit operates with a main power supply voltage. The malfunction prevention circuit thus sets a gate voltage of the output transistor to a ground voltage by using an output generated by the simplified power supply circuit. As a result, malfunction of the output transistor is prevented at earlier time in comparison to malfunction prevention by initialization. |
| US09660630B1 |
Clock grid for integrated circuit
Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one ore more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size. |
| US09660629B2 |
Duty cycle detector and semiconductor integrated circuit apparatus including the same
A duty cycle detector may include a rising clock detection unit enabled in response to a first control signal; a falling clock detection unit enabled in response to a second control signal with a different activation timing from the first control signal; and a comparison unit configured to compare an output signal of the rising clock detection unit to an output signal of the falling clock detection unit in response to a comparison enable signal, and output a duty cycle detection signal. |
| US09660618B2 |
Voltage level shifter, and embedded nonvolatile memory and system using the same
A voltage level shifter may include a first input unit, a second input unit, a first mirror unit, a second mirror unit, and a clamping block. The first and second input units may receive a first input signal and a second input signal, respectively, and form current paths of a negative output node and a positive output node. The first and second mirror units may provide a first voltage to the negative output node and the positive output node. The clamping block may receive a second voltage, and couple the positive output node and the negative output node with the first and second mirror units, respectively. |
| US09660616B2 |
Power managers for an integrated circuit
Systems and methods for managing power in an integrated circuit using power islands are disclosed. The integrated circuit includes a plurality of power islands where power consumption is independently controlled within each of the power islands. A power manager determines a target power level for one of the power islands. The power manager then determines an action to change a consumption power level of the one of the power islands to the target power level. The power manager performs the action to change the consumption power level of the one of the power islands to the target power level. |
| US09660615B2 |
Flip-flop devices with clock sharing
A flip-flop device is provided. The flip-flop device includes a first flip-flop and a clock controller. The first flip-flop receives a first clock signal and a second clock signal for operation. The clock controller receives a clock source signal and generates the first clock signal and the second clock signal according to the clock source signal. Each of the first clock signal and the second clock signal switches between a first voltage level and a second voltage level. For each of the first clock signal and the second clock signal, a period of the first voltage level is shorter than a period of the second voltage level. The period of the first voltage level of the first clock signal and the period of the first voltage level of the second clock signal are non-overlapping. |
| US09660613B2 |
Impedance-matching network using BJT switches in variable-reactance circuits
This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology. |
| US09660612B2 |
Phase shifted resonator
Methods and apparatus, including computer program products, are provided for a tunable filter. In some example embodiments, there may be provided an apparatus. In some example embodiments, there is provided an apparatus. The apparatus may include a tunable radio frequency filter including a tunable phase shifter coupled to a resonator, wherein the tunable phase shifter tunes a center frequency of the tunable radio frequency filter by at least varying a phase of a radio frequency signal provided to the resonator. Related apparatus, systems, methods, and articles are also described. |
| US09660608B2 |
Low passive inter-modulation capacitor
A high power, low passive inter-modulation capacitor is presented, which is formed using metal clad substrates, which are broad-side coupled through a thin air gap. Each substrate may include metal layers affixed on both sides which are electrical coupled together to form a single capacitor plate, or each substrate may have only a single metal layer on the surface adjacent to the air gap. The capacitor has particular application in low cost RF and microwave filters, which may be used in communication equipment and communication test equipment such a diplexers, for low PIM applications. |
| US09660607B2 |
Solid state impedance tuners
A solid state impedance tuner or impedance tuner system includes a control element array with a plurality of solid state control elements configured to be turned on simultaneously to achieve a desired impedance state. The control element array comprises N solid state control elements arranged along an RF transmission line. A controller selectively turns on or off each control element by application of a control signal to vary an impedance presented by the control element array, Another aspect is an impedance tuner module card configured in a standardized system architecture, with a chassis board, and at least one solid state tuner module integrated on the card A chassis electrical connector connected to the tuner module is configured for connection to a corresponding backplane connector. Methods for calibrating a solid state impedance tuner that includes at least two solid state tuner modules combined in one package are disclosed. |
| US09660605B2 |
Variable delay line using variable capacitors in a maximally flat time delay filter
Systems and methods for a variable delay line using variable capacitors in a time delay filter are provided. In at least one embodiment, a delay line is configured to apply an adjustable time delay to an electromagnetic signal travelling through the delay line. The delay line comprises a filter that includes a first variable capacitor. Further, a capacitance of the first variable capacitor is configured to adjust the delay applied to the electromagnetic signal travelling through the delay line when varied. |
| US09660601B2 |
Amplifier with compensation of gain in low frequencies
An amplifier includes a differential amplifier and a compensator. A differential amplifier includes a current source and paired transistors. The paired transistors generate an output signal by dividing a source current supplied by the current source into emitter currents of the paired transistors in response to a difference between an input signal and a reference signal. A compensator includes an amplifying transistor and a feedback circuit that feeds a collector current output from a collector of the amplifying transistor back to a base of the amplifying transistor therethrough. The compensator generates the reference signal at a base of the amplifying transistor. The compensator decreases power consumption of the amplifying transistor when the collector current increases, and increases the power consumption of the amplifying transistor when the collector current decreases. The compensator suppresses a peaking of gain in a low frequency band. |
| US09660599B2 |
Radio frequency power amplifier including a pulse generator and matching network circuit
A system and method are provided for controlling a radio frequency (RF) power amplifier. A magnitude input and a phase input are received for transmission of a RF signal by the RF power amplifier. A digital pulse, having a center position relative to an edge of a reference clock based on the phase input and having a width based on the magnitude input, is generated. The digital pulse is filtered with a resonant matching network to produce the RF signal corresponding to the magnitude input and the phase input. |
| US09660594B2 |
Resonating filter and method thereof
In general the embodiments described herein can provide alternating-current (AC) resonating filters. These resonating filters comprise a transmission line, a first resonator, and a second resonator. The first resonator is configured to block AC signals in a first frequency range, while the second resonator is configured to block AC signals in a second frequency range, where the second frequency range is higher than the first frequency range. The transmission line has a first node coupled to an AC source, and the first resonator is coupled to the transmission line a first distance from the first node, and the second resonator is coupled to the transmission line a second distance from the first node, where the second distance is greater than the first distance. When so configured the resonating filter can effectively block signals in multiple selected frequency bandwidths. |
| US09660587B2 |
Power amplifier
A power amplifier (PA) has been disclosed for linearity improvement. The PA comprises at least an amplifying transistor and at least an auxiliary transistor. Each amplifying transistor of the at least an amplifying transistor includes a first terminal for receiving an input signal of the PA, a second terminal for delivering an output signal of the PA, and a third terminal. Each auxiliary transistor of the at least an auxiliary transistor includes a first terminal, a second terminal coupled to the second terminal of the at least an amplifying transistor, and a third terminal electrically connected to the first terminal of the at least an amplifying transistor. |
| US09660586B2 |
Class D switching amplifier and method of controlling a loudspeaker
A switching amplifier includes a first half-bridge PWM modulator, a second half-bridge PWM modulator, and at least one amplifier stage configured to receive input signals. The switching amplifier also includes a PWM control stage configured to control switching of the first PWM modulator and of the second PWM modulator as a function of the input signals, by respective first PWM control signals and second PWM control signals. The amplifier stage and the PWM control stage have a fully differential structure. |
| US09660584B2 |
Power amplifier modules including wire bond pad and related systems, devices, and methods
One aspect of this disclosure is a power amplifier module that includes a power amplifier; a wire bond pad electrically connected to the power amplifier, the wire bond pad including a nickel layer having a thickness that is less than 0.5 um, a palladium layer over the nickel layer, and a gold layer over the palladium layer; and a conductive trace having a top surface with a plated portion and an unplated portion surrounding the plated portion, the wire bond pad being disposed over the plated portion. Other embodiments of the module are provided along with related methods and components thereof. |
| US09660582B2 |
Spin current generation with nano-oscillator
A device including a spin channel to transport a spin current, a nano-oscillator, and a magnetoresistive device that receives the spin current from the nano-oscillator. The nano-oscillator includes a magnetization state that oscillates between a first state and a second state in response to an input voltage or current. The oscillation of the nano-oscillator may induce the spin current within the spin channel. The magnetoresistive device includes a magnetization state that is set based at least in part on the received spin current. |
| US09660578B2 |
Electronic device with capacitor bank linearization and a linearization method
An electronic device comprises a controllable capacitor bank and a capacitive divider arranged in parallel with the capacitor bank and configured to linearize the capacitor bank in a linearization frequency range of a frequency characteristic of the electronic device. The capacitive divider comprises a series arrangement of a first series capacitance, and a main capacitor bank. A control circuit coupled to one or more control inputs of the capacitive divider and controllable capacitor bank is configured to modify the equivalent capacitance of the capacitive divider and the controllable capacitor bank for providing capacitance steps, each capacitance step being variable over frequency such that for each step a frequency change Δf of the frequency characteristic is maintained constant in the linearization frequency range. |
| US09660576B2 |
Predicting production of photovoltaic systems
The present invention is directed to methods, systems, and devices for predicting production of a photovoltaic (PV) system. A method may include establishing a reference performance model for a reference PV system at a reference site. Further, the method may include establishing a performance factor for an installed PV system based on configuration parameters of the installed PV system, measurements of the installed PV system, weather data at an installation site of the installed PV system and a comparison of the measurements of the installed PV system to the reference performance model. The method may also include predicting production of the installed PV system based on the performance factor, cumulative weather data and a time dependent performance ratio. |
| US09660569B2 |
Solar array support structure, mounting rail and method of installation thereof
Disclosed herein is a mounting rail for a solar array support structure that includes a main body having a top and a bottom, the main body extending from a first end to a second end. The mounting rail further includes a solar panel mounting portion extending along the top of the main body, the solar panel mounting portion configured to secure the solar panel to the mounting rail. The mounting rail further includes a first flange extending from the bottom of the first vertical element, the first flange including a first pair of holes configured to receive two ends of a U-bolt, the first pair of holes spaced apart substantially equal to a width of the horizontal rail. A method of installing a solar array support structure using the mounting rail is further disclosed. |
| US09660567B2 |
System for mounting and supporting photovoltaic modules
A system for mounting and supporting photovoltaic (PV) modules includes a frame rail that is formed with a longitudinally extending channel for retaining a plurality of mounting clips, and mounting clamps for anchoring the frame rail to a support base or support structure. Each mounting clamp includes a pair of jaws for engaging along a base portion of the fame rail. The mounting clips are arranged along the length of the frame rail, and are used to support the PV modules adjacent to the frame rails. Module clamps are used to hold the PV modules in place, the module clamps being secured to the mounting clips using elongated fasteners having an engaging end for engaging the mounting clip. The mounting clamps allow the frame rail position to be adjusted in two directions, and the mounting clips facilitate rapid mounting of the PV modules to the frame rail structure. |
| US09660561B2 |
Motor drive device
A motor drive device having drive controller to control a motor for driving an electric vehicle wheel depending on position of magnetic poles using angle detection value sensed by a motor angle sensor; motor angle estimator to estimate an angle of a motor rotor without a rotation sensor; sensor malfunction determiner to determine malfunction of the sensor; sensor switcher to cause the controller to control using an estimation value of the rotor angle estimated by the estimator instead of the angle detection value sensed by the sensor once the determiner determines that the sensor malfunctions; and start-up rotor angle calculator to calculate an angle of the rotor from a counter electromotive voltage of the motor and to cause the controller to control using the calculated angle, when the motor is started up after stop of the motor in a state where the sensor is determined as malfunctioning by the determiner. |
| US09660560B2 |
Motor drive circuit and method of driving a motor
A drive system for a brushless DC motor having a rotor includes at least one permanent magnet and a stator including at least one phase winding. The system has a drive circuit including a switch associated with the winding for varying the current passing through the winding; a rotor position sensor arranged to sense the position of the rotor; and a controller arranged to provide drive signals to control the switch. The drive system is further arranged to receive a temperature signal that has a value dependent upon the temperature of the at least one magnet of the rotor. The controller is arranged to vary the phase of the current passing through the winding relative to the rotor position dependent upon the temperature of the rotor magnet. |
| US09660553B2 |
Switching stage, energy conversion circuit, and conversion stage for wind turbines comprising the energy conversion circuit
The present invention relates to an energy conversion circuit comprising a switching stage with a positive DC voltage terminal (1), a negative DC voltage terminal (3), m−1 intermediate DC voltage terminals (2) m DC bus capacitors (5); and p linked cells consisting of m+1 switches (9) and at least one capacitor (10), connecting cell 1 to the positive DC voltage terminal (1), negative DC voltage terminals (3) and intermediate DC voltage terminals (2); and a multilevel converter, the output of which is connected to the AC voltage terminal (4), with a positive voltage terminal (12) and a negative voltage terminal (14) of the multilevel converter and m−1 intermediate voltage terminals of the multilevel converter (13), which are connected to the positive output terminal of the switching stage (6), to the negative output terminal of the switching stage (8), and to the m−1 intermediate output terminals of the switching stage (7), respectively. |
| US09660538B2 |
Digital closed-loop control for DC/DC switch-mode power converters with multiple outputs
Apparatus and method for providing closed loop feedback control for switch-mode DC/DC power converter with multiple outputs using digital filter feedback, in contrast to analog error feedback. In the apparatus and method, multiple outputs for a switch-mode DC/DC power converter are regulated by digital means, including the allocating or partitioning of digital control resources among each of the multiple outputs. The partitioning of control resources may be in response to operating conditions. |
| US09660537B1 |
Fault tolerant power converter
A power converter provides a low-voltage output using a full-bridge fault-tolerant rectification circuit. The output circuit uses controlled switches as rectifiers. A fault detection circuit monitors circuit conditions. Upon detection of a fault, the switches are disabled decoupling the power converter from the system.A common-source dual MOSFET device includes a plurality of elements arranged in alternating patterns on a semiconductor die. A common-source dual synchronous rectifier includes control circuitry powered from the drain to source voltage of the complementary switch.A DC-to-DC transformer converts power from an input source to a load using a fixed voltage transformation ratio. A clamp phase may be used to reduce power losses in the converter at light loads, control the effective output resistance of the converter, effectively regulate the voltage transformation ratio, provide narrow band output regulation, and control the rate of change of output voltage for example during start up. One or more of the transformer windings may be clamped. The converter may use the sine amplitude converter topology. The converter may use common-source dual MOSFET devices and fault detection.The density of point of load power conversion may be increased and the associated power dissipation reduced by removing the input driver circuitry from the point of load where it is not necessary. An output circuit may be located at the point of load providing fault tolerant rectification of the AC power from the secondary winding of a power transformer which may be located nearby the output circuit. The resonant voltage and current waveforms on the primary side of the transformer are readily communicated via an AC bus between the driver circuit and the primary winding of the power transformer. The driver circuit may drive a plurality of transformer-output circuit pairs. The transformer and output circuit may be combined in a single module at the point of load. Alternatively, the output circuit may be integrated into point of load circuitry such as a processor core. The transformer may be deployed near the output circuit. |
| US09660535B2 |
Method and system to dynamically position a switch mode power supply output voltage
A switch mode power supply (SMPS) converter is periodically run backwards by using a synchronous switch instead of the normally used commutating diode. By running the SMPS converter backwards the SMPS output capacitor can be discharged very quickly to provide a fast turn off of (no current through) the LED's, thereby solving the color shift problem. This enables positioning the output voltage of the SMPS up or down by actively charging or discharging the bulk output capacitor. Having the capability of actively charging or discharging the bulk output capacitor allows generation of a current source comprising substantially square, e.g., substantially full current when on and substantially no current when off, current pulses that are preferable for driving LED lighting applications. |
| US09660530B2 |
Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time
A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise. |
| US09660528B2 |
Adaptive controller for a voltage converter
A DC-to-DC converter includes an input voltage node, an inductor, and a switch coupled to the inductor and the input voltage node. More specifically, the switch has an on state and off state, wherein during the on state, current flowing through the inductor increases and the off state results in a decrease of the current flowing through the inductor via a driver coupled to the switch. The driver comprises a plurality of transistors and an adaptive voltage node, wherein a voltage level at the adaptive voltage node is to vary in accordance with the current flowing through the inductor so as to decrease a variation of the amount of time to turn off the switch. |
| US09660527B2 |
Zero voltage switching
A method for providing non-resonant zero-voltage switching in a switching power converter. The switching power converter converts power from input power to output power during multiple periodic switching cycles. The switching power converter includes a main switch and an auxiliary capacitor adapted for connecting to the main switch, and an inductor connectable to the auxiliary capacitor. When the main switch is on, a previously charged (or previously discharged) auxiliary capacitor is connected to the main switch with auxiliary switches. The main switch is switched off with zero voltage while discharging non-resonantly (charging) the auxiliary capacitor by providing a current path to the inductor. The auxiliary capacitor is disconnected from the main switch. The voltage of the auxiliary capacitor is charged and discharged alternatively during subsequent switching cycles. The voltage of the auxiliary capacitor stays substantially the same until the subsequent turn off of the main switch during the next switching cycle with substantially no energy loss in the auxiliary capacitor. |
| US09660522B2 |
DC-DC converter circuit arrangement
A DC-DC converter circuit arrangement consisting of at least one multiphase DC-DC converter for transporting energy between two electrical systems. The arrangement may include several converter circuits whereby each features at least one first control element that can be regulated. A controller can produce several drive signals that have different phases. One switched mode operation of a converter circuit of the multiphase DC-DC converter can be controlled with each drive signal. The switched mode operation of each converter circuit of each subsequent multiphase DC-DC converter can be controlled by means of a drive signal, which can be produced by the controller. The controller is designed and equipped in such a way that it can enable or disable the energy transport by means of one of the multiphase DC-DC converter. |
| US09660521B2 |
Power conversion circuit
A power conversion circuit includes first to fourth switching elements connected in series between ground and high voltage electrical paths, a first reactor, a main battery, a second reactor, a sub battery, a high voltage sensor for detecting a high voltage VH between the ground and high voltage electrical paths, and a controller. Upon issuance of an instruction for turning off all of the first to fourth switching elements, the controller determines that the third switching element is experiencing an ON failure when the high voltage VH is equal to the sum of a battery voltage VB1 of the main battery and a battery voltage VB2 of the sub battery, to thereby allow electrical power to be transferred between the batteries and a load even in the event of occurrence of the ON failure in the switching element. |
| US09660520B2 |
Method and apparatus to provide power conversion with high power factor
A power converter circuit rectifies a line voltage and applies the rectified voltage to a stack of capacitors. Voltages on the capacitors are coupled to a plurality of regulating converters to be converted to regulated output signals. The regulated output signals are combined and converted to a desired DC output voltage of the power converter. Input currents of the regulating converters are modulated in a manner that enhances the power factor of the power converter. |
| US09660519B2 |
Switching power supply circuit and power factor correction circuit
A switching power supply circuit including a phase angle detector circuit detecting a phase angle specified in advance based on a peak hold signal, a continuous conduction control setting circuit holding a voltage value corresponding to a peak current value of an inductor current detection voltage in every switching cycle and during a one-shot pulse when the peak is held and outputting a signal at the point of detection to determine to enable or disable a second set pulse set by the continuous conduction control setting circuit. When the second set pulse is disabled, a selector circuit carries out control using critical conduction control to turn on a switching element using a ZCD comparator detecting that the inductor current has reached zero, because of which the peak current does not increase. |
| US09660513B2 |
Switching device
A control circuit is driven by a driving voltage (VOC) generated by a generator circuit, and outputs a control signal. A drive circuit is driven by a driving voltage (VOD) generated by another generator circuit, and turns a switching element inside a switching circuit on or off by supplying, to the switching circuit, a drive signal based on the control signal. During activation of a switching device, a voltage generation controller detects a voltage value of the output voltage (VOC) of the generator circuit, and allows activation of the other generator circuit after verifying that the detected voltage value is at or above a designated threshold. |
| US09660511B2 |
Gate driver circuit and power conversion apparatus using same
A gate driver circuit capable of quickly driving a semiconductor device without erroneous ignitions. It has a positive power supply for forward bias, a negative power supply for backward bias, a first bias circuit that outputs the positive- or negative-power-supply voltage according to gate driver signal S, a capacitor that is charged by the negative-power-supply voltage when the first bias circuit outputs the negative-power-supply voltage, and a second bias circuit that supplies the gate of the semiconductor device with the positive- or negative-power-supply voltage according to gate driver signal S. Only in an early stage of a transition period during which the semiconductor device is turned on, the second bias circuit supplies the gate of the semiconductor device, instead of the positive-power-supply voltage, with a voltage boosted by adding the charged voltage of the capacitor onto the positive-power-supply voltage outputted from the first bias circuit. |
| US09660509B2 |
Linear vibration actuator
Embodiments of the invention provide a motor assembly including a terminal provided at a stator of a motor and electrically connected to a coil wound around the stator, and a controller formed with a coupling hole to which the terminal is coupled and electrically connected and controlling electric input and output to the terminal. |
| US09660501B2 |
Electric actuator with a manual drive means
An actuator including a frame, an electric motor fastened to the frame and to a rotor that is constrained to rotate with an outlet shaft, and a connector electrically connected to the motor and secured to the frame to be connected to a complementary connector. The actuator includes a secondary drive device having a secondary shaft having a first end that extends outside the frame and is arranged to be coupled to rotate with a rotary drive tool, a second end of the secondary shaft in rotation coupled with the outlet shaft, and an activation rod opening out into the connector is secured to the frame and arranged to prevent the secondary shaft from being coupled in rotation with the outlet shaft only when the complementary connector is connected to the connector secured to the frame. |
| US09660500B2 |
Hub motor arrangement or vehicle with hub motor arrangement
A ride-on vehicle, such as for a child, includes a vehicle body and one or more wheels that support the vehicle body relative to a surface. At least one of the wheels includes a hub motor arrangement that provides a drive torque for propelling the vehicle. The hub motor arrangement includes a housing defining an interior space. An axle or other mounting element(s) define an axis of rotation of the housing. Preferably, the axle or other mounting element(s) do not pass completely through the housing. A motor drives the housing through a transmission. Preferably, the motor is a standard, compact motor that is positioned on the axis of rotation and can be laterally offset from a central plane of the housing. In some embodiments, a traction element is carried directly by the housing. |
| US09660494B2 |
Joint and jointing method in a permanent magnet synchronous machine
The invention relates to a joint between a copper short-circuiting ring (1) and a copper bar (2) of the damper winding in a permanent magnet synchronous machine, wherein the end of the bar is jointed to a hole (9) disposed in the short-circuiting ring by welding them together at the mating surfaces. Further, the invention relates to a corresponding method. According to the invention the short-circuiting ring (1) includes a blocking structure for limiting the heat flux from being conducted further into the short-circuiting ring from the weld between the short-circuiting ring and the bar. |
| US09660492B2 |
Outer rotor construction
An outer rotor construction for a wind turbine generator which outer rotor construction comprises a plurality of rotor housing segments, wherein a rotor housing segment is realized to hold a number of magnet poles, and wherein a rotor housing segment comprises a lateral connecting interface of a lateral connection for detachably connecting that rotor housing segment along its longitudinal length to a number of adjacent rotor housing segments. The invention further describes a wind turbine including a generator, which generator includes an inner stator and such an outer rotor is provided. A method of performing a maintenance procedure on such an outer rotor construction is also provided. |
| US09660491B2 |
Rotor for rotating electric machine
A rotor includes a rotor core having a plurality of pairs of magnet-receiving holes and a plurality of magnets respectively received in the magnet-receiving holes. Each pair of the magnet-receiving holes is arranged in a substantially V-shape that opens toward a stator side. The rotor core also has a plurality of q-axis core portions through which q-axis magnetic flux flows, a plurality of first magnetic flux barriers and a plurality of second magnetic flux barriers. Further, in the rotor core, the following dimensional relationships are satisfied: W2≧W1; and W3≧W1, where W1 is a width between centerlines L1 of the q-axis core portions and the corresponding first magnetic flux barriers, W2 is a width between the centerlines L1 and the corresponding second magnetic flux barriers, and W3 is a radial width between a radially inner surface of the rotor core and the second magnetic flux barriers. |
| US09660487B1 |
Intelligent wireless power transferring system with automatic positioning
An automatic-positioning wireless power transfer system to wirelessly charge power to an object and is also capable of wirelessly harvesting power from an object. The power transfer system consists of a mobile housing configured to autonomously move about the object, and has a tiltable transceiver. The mobile housing can be tethered to a base station via a cable, or not physically tethered to a base station when it travels. |
| US09660486B2 |
Wireless power transfer device and wireless charging system having same
The present specification provides a wireless power transfer device formed to transmit power to a wireless power reception device, and a power transfer unit in the wireless power transfer device comprises: a first coil formed to generate a magnetic field so as to transmit power in an induction scheme; and a second coil wound around the first coil and formed to generate a magnetic field vibrating at a resonance frequency so as to transmit power in a resonance scheme. |
| US09660483B2 |
Power supply control apparatus and power supply control system having the same
A power supply control apparatus is connected to an electric device to control supply of power to the electric device. The apparatus includes a main power switch to apply or interrupt main power to the electric device, the main power being external input commercial AC power, an auxiliary power storage unit supplied and charged with the main power as auxiliary power, a charging/discharging unit including a charging circuit to convert the main power into DC power and charge the converted DC power in the auxiliary power storage unit, and a discharging circuit to convert the DC power in the auxiliary power storage unit into AC power and discharge the converted AC power to the electric device, and a controller to control the main power switch, and control the charging/discharging unit to selectively drive the charging circuit or the discharging circuit. |
| US09660479B2 |
Device and method for wirelessly transmitting power
There is provided a wireless power transmitting device capable of simply being carried by a user and wirelessly transmitting a power to a power receiving device with a high transmission efficiency regardless of time and space. The wireless power transmitting device includes a power storage unit configured to store a direct current power, and a power transmitting unit configured to be operated by the direct current power stored in the power storage unit and to wirelessly transmit the power to a power receiving device. |
| US09660478B2 |
System and method for facilitating avoidance of wireless charging cross connection
A system and method for charging a chargeable device is provided. The system can include a wireless charger including a wireless power antenna and a wireless power transmitter coupled to the wireless power antenna and configured to generate a wireless charging field in at least one charging region. The wireless charging field includes a plurality of power signals. The wireless charger further includes a communication antenna and a transceiver coupled to the communication antenna and configured to communicate with the chargeable device via the communication antenna. The wireless charger further includes a controller configured to facilitate avoidance of cross connection of the chargeable device with the wireless charger and at least one other wireless charger in which the chargeable device receives power from the wireless power transmitter of the wireless charger while communicating with at least one other wireless charger. The system can include a chargeable device including a controller configured to generate a load pulse configured to be received by the wireless charger. |
| US09660477B2 |
Mobile charging unit for input devices
Devices, methods, and systems for charging input devices. A charging unit includes a sleeve for receiving a stylus and a base. The charging unit receives electrical power from an external power source via an interface and transfers the power to the stylus via a connection between the base's charging contacts and conductive charging zones on a portion of the input device in the base. A method detects insertion of a stylus into a charging unit having an internal battery and an interface capable of receiving power from an external power source. The method determines if the unit is connected to a power source. If so, the stylus is charged by transferring the received energy via a connection between the unit's charging contacts and conductive charging zones of the stylus. If energy is not being received from the external power source, the method charges the stylus using the unit's internal battery. |
| US09660476B2 |
Circuit arrangement for discharging an electrical energy store and power converter comprising such a circuit arrangement
A circuit assembly for discharging an electrical energy store includes a first discharge current path for uncontrolled, passive discharging of the energy store and for keeping a defined charge voltage of the energy store, and a second discharge current path for controlled, active discharging of the energy store. A semiconductor switch electrically connects to a positive current connection of the energy store and to a negative current connection of the energy store. A voltage limiter includes a first current connection for electrically connecting to the positive current connection of the energy store and a second current connection for electrically connecting to the negative current connection of the energy store. The circuit assembly further includes a first control path for providing a first control signal from the first current connection of the voltage limiter to the control connection of the semiconductor switch in order to control the semiconductor switch. |
| US09660468B2 |
Rechargeable flameless candle systems and methods
According to an embodiment of the present invention, a recharging device includes a recharging port that receives a flameless candle and recharges a battery in the candle. The recharging device includes a first stacking structure that has a top portion and a bottom portion. There is a top stacking contact on the top portion. An electrical power bus is connected with the top stacking contact. The electrical power bus is also configured to provide electrical power to the flameless candle through the recharging port. The top portion of the first stacking structure is configured to mate with a bottom portion of a first stacking structure of another recharging device. |
| US09660465B2 |
Uninterruptible power supply, battery assembly thereof and charging-discharging method thereof
A battery assembly includes a power module, a receptacle connector, a driving switch and a movable stop arm. The power module includes a battery control unit and a cell electrically connected to the battery control unit. The receptacle connector is disposed at the power module and electrically connected to the cell via the battery control unit. The receptacle connector includes an insertion opening. The driving switch is disposed corresponding to the receptacle connector and electrically connected to the battery control unit. A default setting of the driving switch is “switched off”. One end of the movable stop arm is outside of the insertion opening and blocks the same. The movable stop arm is movable toward the driving switch to touch and switch on the same. |
| US09660457B2 |
Feed line switching apparatus, optical submarine branching apparatus, submarine cable system, and feed line switching method
In a feed line switching apparatus, a situation in which the feed line switching apparatus cannot work when feed lines have a predetermined connection relationship is prevented. The feed line switching apparatus includes a command acquisition unit which acquires a feed line switching command which designates a connection relationship of feed lines, a switching execution unit which switches the connection relationship of the feed lines in accordance with the feed line switching command acquired by the command acquisition unit, and a switching control unit which suppresses switching of the connection relationship of the feed lines in the switching execution unit for a predetermined feed line switching command. |
| US09660456B2 |
Switching of conductor pair in power over ethernet system
Technique for providing power to a powered device (PD) over a cable having first and second sets of twisted pairs, such as signal pairs and spare pairs. Power Sourcing Equipment (PSE) circuitry is coupled via a first switch to the second set, e.g. to the spare pairs. A switch control circuit turns the first switch off to enable the PSE circuitry to perform a prescribed operation in connection with the PD over only the first set, e.g. over the signal pairs, and turns the first switch on to enable the PSE circuitry to perform the prescribed operation in connection with the PD over the first and second sets. |
| US09660455B2 |
System and method for increasing efficiency of gensets in micro-grid systems
A system and method for running a plurality of gensets in parallel in a micro-grid system is disclosed. The system and method may include at least one genset configured to run at a load factor of greater than sixty percent, the number of the at least one genset supplying power at any given time including a minimum or less than minimum number of gensets capable of meeting a demand imposed by a load. The system and method may also include a turbo compounding system associated with at least one of the at least one genset, each of the electric turbo compounding systems configured to increase fuel efficiency of the at least one genset. |
| US09660453B2 |
Control of a microgrid
A method of controlling a microgrid including at least one distributed generator (DG) and arranged for being connected to a power grid, by means of a converter via which the DG is connected in said microgrid. The method includes running the converter in a current control mode for controlling at least one current output of the DG in the microgrid; obtaining an indication that the converter should change from the current control mode towards a voltage control mode for controlling a voltage output of the DG in the microgrid; and entering the converter in an interstate mode, in response to the obtained indication, in which interstate mode the converter is configured for controlling both the current output and the voltage output. |
| US09660451B1 |
Islanded operation of distributed power sources
A method for synchronizing distributed generation power sources during an islanding event may include synchronizing a first one of the islanded local power sources to a master local reference, and synchronizing a second one of the islanded local power sources to the master local reference. In-rush current may be controlled by energizing the local load sequentially in stages when a utility grid is connected to the point of common connection. The local loads may also be selectively energized in response to the amount of available local power generating capacity in an islanding situation. A method for controlling a system having local loads and local power sources may include evaluating the power available from local power sources, adaptively controlling the local loads in response to the power available from the local power sources, and operating the local loads and local power sources as an independent system during an islanding event. |
| US09660447B2 |
Connector having wireless control capabilities
A connector for connecting a source of AC power to a powered device includes a line-side interface arranged for releasably and electrically coupling the connector to the source of power, a load-side power interface arranged for electrically coupling the connector to the powered device, a load-side control interface for controlling the power supplied to the powered device, a controller electrically coupled to the line-side interface, the load-side power interface, and the load-side control interface and operable to control a bringing of power to the load-side power interface from the line-side interface and for bringing a control signal to the load-side control interface, and a receiver electrically coupled to the controller for receiving a first signal from a device external to the connector and for generating, in response thereto, a second signal for controlling operations of the controller. |
| US09660443B1 |
Control circuits with energy recycling for envelope elimination and restoration and related methods
Control circuits with energy recycling for envelope elimination and restoration and related methods are disclosed. A control circuit includes a filter module configured to condition an input power signal to provide an output power signal. An energy recapture module is electrically coupled to the filter module and is configured to capture a portion of residual energy from the filter module and return the portion of the residual energy to the input power signal. A control module is electrically coupled to the filter module and the energy recapture module and is configured to control the filter module to provide the output power signal and is further configured to control the energy recapture module to capture and return the portion of the residual energy to the input power signal. |
| US09660439B2 |
Direct current power distribution and protection system
A direct current power (DC) distribution system includes a plurality of DC power sources, a ring bus, a plurality of switch assemblies, and a plurality of passive protection assemblies. Each DC power source is coupled to the ring bus by a respective switch assembly and a respective passive protection assembly. |
| US09660438B2 |
Secure and dependable differential protection for electric power generators
Secure and dependable differential protection for electric power generators is described herein. An internal fault is declared if the operating current exceeds a function of the restraining current, and the operating current exceeds and adjusted pickup value. The adjusted pickup value is selected as a minimum of a compensated first pickup value and a second pickup value. The compensated first pickup value may be calculated by adding the absolute value of a compensation addend with a first pickup value. The compensation addend may be calculated by filtering, compensating, and summing current values from the neutral side and the power system side of the electrical generator. The absolute value of the compensation addend may be further adjusted using a security compensation factor. |
| US09660436B2 |
Detection of interconnected outputs
Systems and methods for detection of interconnected outputs of a power supply are provided. A first channel of a power supply is activated, such that power is supplied to a first load connected to the first channel. A first load voltage is measured for the first load. A second load voltage is measured for a second load connected to a second channel of the power supply. The second load voltage is compared to the first load voltage to generate an interconnection result. The power supply is shut down when the interconnection result indicates that the second load voltage matches the first load voltage, such that all channels of the power supply do not supply power to any load connected thereto. |
| US09660431B2 |
Vibration resistant cable
Vibration resistant cables containing a first conductor and a second conductor, each having a diameter d, are disclosed. The second conductor is twisted around the first conductor at a lay length between 3 feet and 6 feet to eliminate bagging of the vibration resistant cable during installation. |
| US09660428B2 |
Fireproof wall lead-through for an electrically insulated conductor and method for producing a fireproof wall lead-through
A fireproof wall lead-through for an electrically insulated conductor, having a wall, a wall pipe leading through the wall, an outer sleeve extending through the wall pipe, and a conductor led through the outer sleeve, which conductor is spaced apart from the outer sleeve in an electrically insulating manner, wherein an intumescent material is applied to the outer sleeve and the conductor in the conductor segment of the wall pipe, which intumescent material swells and closes the wall lead-through under the influence of heat. |
| US09660427B1 |
Power transfer unit
A power transfer unit is disclosed. In a first implementation of the disclosed power transfer unit, a tubular assembly of the power transfer unit includes an encapsulated elbow hinge design with a reduced profile that permits substantially off-center installation of the housings of the power transfer unit. In a second implementation of the disclosed power transfer unit, the tubular assembly includes an inverted, telescoping tubing design that does not come apart during installation and use, and in some implementations may act as a stop for a closable member. |
| US09660426B1 |
Attachments for compact tractor for pulling wire through underground conduits
A compact tractor equipped for pulling wire through underground conduits having a boom and dipper on the rear of the compact tractor and a rotatable witch's hat spool assembly on the front of the compact tractor, wherein the spool assembly is mounted onto the loader lifter arms such that it can be easily tilted to dump a roll of cable onto the back of a trailer. |
| US09660425B1 |
Ion generator device support
The present disclosure is directed to ion generator device supports. An ion generator device support is configured to retain an ion generator device, the ion generator device having a first portion containing exposed electrodes and a second portion, the support includes a first wall, a second wall extending orthogonally from the first wall, a third wall extending orthogonally from the first wall opposed to the second wall, wherein the third wall extends a smaller distance from the first wall than the second wall and a fourth wall extending orthogonally from the second wall, wherein a substantially open cavity is defined by the fourth wall, the second wall and an edge of the third wall, and a substantially closed cavity is defined by the second wall, the first wall and the third wall, and wherein the first portion of the ion generator device is retained within the substantially open cavity. |
| US09660424B2 |
Spark plug
A spark plug 1 has a center electrode 4 and a ground electrode 5 opposed to each other and causes a spark discharge to occur through application of a voltage between the center electrode 4 and the ground electrode 5 . Moreover, the center electrode 4 has a columnar main chip 10 provided at a distal end thereof by welding via a fusion portion 12 and an annular auxiliary chip 11 surrounding the fusion portion 12. Consequently, when a spark discharge occurring from the center electrode 4 is blown to the downstream side by the influence of a gas flow in a cylinder of an internal combustion engine, it is possible to suppress a cathode point from being formed in the fusion portion 12 since the fusion portion 12 is surrounded and thus protected by the auxiliary chip 11. As a result, it is possible to suppress wear of the center electrode 4, thereby extending the service life of the spark plug 1. |
| US09660419B2 |
High reliability etched-facet photonic devices
Semiconductor photonic device surfaces are covered with a dielectric or a metal protective layer. The protective layer covers the entire device, including regions near facets at active regions, to prevent bare or unprotected semiconductor regions, thereby to form a very high reliability etched facet photonic device. |
| US09660418B2 |
VCSEL based low coherence emitter for confocal 3D scanner
Methods and apparatus for measuring objects comprise a plurality of light sources to generate a plurality of light beams directed toward a spot generator array comprising a plurality of spot generating lenses. The plurality of light sources is separated from the spot generator array with a separation distance sufficient to overlap the plurality of light beams at each of the spot generating lenses. The overlap of each of the beams at each of the spot generating lenses provides smoothing of the energy profile of the light energy incident on the spot generating lenses. The spot generator array generates focused spots comprising overlapping focused beams. The overlapping beams may comprise overlapping beams of a vertical cavity surface emitting laser (VCSEL) array, and the overlapping focused beams can decrease optical artifacts. |
| US09660414B2 |
Heat dissipation system for optical module
A heat dissipation system for an optical module, related to communication fittings technologies, is provided to improve heat dissipation efficiency of the optical module. The heat dissipation system for an optical module includes a circuit card on which at least one optical module is mounted, where the optical module includes a housing and a laser disposed inside the housing. A first heat dissipation apparatus is fixedly disposed on the circuit card. A heat dissipation window is provided in an area that is above the laser and on the housing of the optical module. The first heat dissipation apparatus performs heat dissipation on the heat dissipation window. |
| US09660413B2 |
Nitride semiconductor light emitting device
A nitride semiconductor light emitting device includes a first coat film of aluminum nitride or aluminum oxynitride formed at a light emitting portion and a second coat film of aluminum oxide formed on the first coat film. The thickness of the second coat film is at least 80 nm and at most 1000 nm. Here, the thickness of the first coat film is preferably at least 6 nm and at most 200 nm. |
| US09660412B2 |
Femtosecond ultraviolet laser
A method and system for generating femtosecond (fs) ultraviolet (UV) laser pulses enables stabile, robust, and optically efficient generation of third harmonic fs laser pulses using periodically-poled quasi-phase-matched crystals. The crystals have different numbers of periodically poled crystalline layers that enable a long conversion length without back-conversion and without a special phase-matching direction. The fs UV laser may have a high conversion efficiency and may be suitable for high power operation. |
| US09660409B2 |
Low noise, high stability, deep ultra-violet, continuous wave laser
A laser for generating deep ultra-violet (DUV) continuous wave (CW) light includes a second-harmonic generator and a fourth-harmonic generator. The fourth-harmonic generator includes a plurality of mirrors as well as a first non-linear optical (NLO) crystal and a pair of tilted plates. The first NLO crystal generates the light having the fourth harmonic wavelength and a first astigmatism, and is placed in operative relation to the plurality of mirrors. The pair of tilted plates is placed in operative relation to the first NLO crystal such that the light having the second harmonic wavelength passes through both of the tilted plates. Notably, the pair of tilted plates are disposed at substantially equal and opposite angles about respective parallel axes such that they introduce a second astigmatism that corrects for the first astigmatism while minimizing displacement of the circulated light. |
| US09660406B2 |
Push-in wire connector with collar
A wire connector having a collar surrounding a set of wire ports in a wire connector with the collar providing a collective shield between an environment external to the collar the collar but not between the set of wires within the collar. |
| US09660404B2 |
Terminal connection structure for resistor
Provided is a connection structure for a detection terminal of shunt resistor that allows a lead wire, that is to be connected to an electrode of the shunt resistor and is for detecting electrical current, to be easily and compactly connected to the electrode within a narrow and small module. A terminal connection structure for a resistor, which connects a detection terminal to an electrode, comprises a shunt resistor (13) that has a pair of electrodes (12) at both ends of a resistor body (11); a connector base (14) formed of insulating material; and an electrically conductive section (15a) formed on the connector base (14); wherein the connector base (14) is fit onto the shunt resistor (13) such that the electrically conductive section (15a) is electrically connected to the electrodes (12). The connector base (14) is provided with a joint section (C) that can be fit onto the resistor body (11). The resistor body (11) and the electrode (12) is provided with a level difference and the connector base (14) is fit into between the electrodes (12,12). |
| US09660400B2 |
Flippable electrical connector
A plug connector includes a connector body defining a rear cable supporting platform with opposite first and second surfaces, a plurality of terminals and a cable. The terminal includes a pair of USB 2.0 signal soldering legs, a grounding and power soldering legs exposed to the first surface of the supporting platform and a detecting soldering leg, an additional power and grounding soldering legs exposed to the second surface. Wires of the cable consist of a pair of USB 2.0 signal wires, a power wire, a grounding wire welded with corresponding soldering legs on the first surface. The second surface of the supporting platform is further located with a SMT type resistor with a first leg and a second leg, the first leg is connected with the detecting soldering leg, the second leg is connected with the additional power soldering leg or the additional grounding soldering leg. |
| US09660399B2 |
Electrical connector with two insertion orientations
An electrical connector comprises an insulating housing, several first and second conductive terminals, an inner grounding unit, and an outer grounding unit, which are disposed on the insulating housing. The insulating housing has a first surface, an opposite second surface, and two side surfaces arranged between the first and second surfaces. The inner grounding unit has a plate embedded in the insulating housing and two protruding sheets extended from the plate and respectively protruding from the side surfaces of the insulating housing. The plate is arranged to separate the first conductive terminals from the second conductive terminals. The outer grounding unit clips the insulating housing and engages the protruding sheets. A portion of the outer grounding unit engaged with one of the protruding sheets includes two stacked engaging portions, and at least one of the two stacked engaging portions has a thru-hole for engaging with the corresponding protruding sheet. |
| US09660398B2 |
Coaxial cable connector having electrical continuity member
A coaxial cable connector comprising a connector body; a post engageable with the connector body, wherein the post includes a flange; a nut, axially rotatable with respect to the post and the connector body, the nut having a first end and an opposing second end, wherein the nut includes an internal lip, and wherein a second end portion of the nut corresponds to the portion of the nut extending from the second end of the nut to the side of the lip of the nut facing the first end of the nut at a point nearest the second end of the nut, and a first end portion of the nut corresponds to the portion of the nut extending from the first end of the nut to the same point nearest the second end of the nut of the same side of the lip facing the first end of the nut; and a continuity member disposed within the second end portion of the nut and contacting the post and the nut, so that the continuity member extends electrical grounding continuity through the post and the nut is provided. |
| US09660396B2 |
Cable connector assembly with improved indication effect
A cable connector assembly (100) includes: a cable (30) having a number of inner wires; a first connector (10) including a main body (120), plural contacts (121) retained in the main body, a first circuit board (130), a luminous element (152), and a cover; and a second circuit board (180) assembled on a rear end of the first circuit board and getting power and grounding source from the first circuit board. The second circuit board includes a detection contact (182) electrically connected to an inner wire of the cable, and a chip (181) electrically connected respectively to the luminous element and the detection contact. The chip detects a voltage difference between the power source and the first connector. A light is emitted by the luminous element passing through the cover to indicate a charging status of the charging device. |
| US09660392B2 |
Electrical plug and energy transmission arrangement
The invention relates to an electrical plug (24) having a connection unit (36) which can be coupled to an electrical line (26) in order to transmit electrical energy, having at least one electrical contact pin (30) which has a plug section (32) and a coupling section (34), wherein the coupling section (34) is electrically coupled to the connection unit (36), and wherein the plug section (32) is designed to provide a releasable plug connection to an associated contact socket (18) in order to electrically couple the contact pin (30) to the contact socket (18), and having a detection unit (38) which is designed to) detect a tensile force which is exerted on the contact pin (30) and/or a movement of the contact pin (30) relative to the contact socket (18), and to provide a disconnection signal for interrupting the energy transmission process. |
| US09660391B1 |
Adapter having a rotating member with a connector pin connected to a printed circuit board
An adapter having a rotatable plug is provided. The adapter includes a case having an installation hole which provides access to an interior of the case; a rotation member installed within the installation hole of the case, the rotation member being rotatable within the installation hole relative to the case; at least one connection pin installed in the rotation member and protruding from the case; and a guide member provided adjacent to installation hole in the interior of the case and configured to guide rotation of the rotation member. |
| US09660390B2 |
Cable connector assembly having an insulative housing constructed of two main bodies
A cable connector assembly includes: an insulative housing; a number of contacts retained in the insulative housing; a cable including a plurality of wires electrically connected with the contacts and an insulative outer coating enclosing the wires; and a shielding case enclosing the insulative housing; wherein the insulative housing includes a first main body extending along a docking direction and a second main body extending along a direction perpendicular to the docking direction, an end of the second main body is exposed to the first main body along the docking direction, and the insulative outer coating of the cable extends along a direction away from the docking direction to form an angle relative to the extending direction of the second main body. |
| US09660382B2 |
Electrical extension cord with a unitary and convertible two or three prong plug end
What is presented is an extension cord with a convertible electrical plug end that can be connected to grounded and ungrounded power supply outlets. The extension cord comprises an extension cord and a plug end and is configured to transmit electrical power. The plug end is connected to the extension cord. The plug end itself comprises a plug body, plurality of prongs, flap, and ground contact. The protruding prongs are connected to the plug body and configured to couple to the outlet. The flap is movably attached to the plug body such that the flap can rotate relative to the plug body. When the flap is in the closed position, the plug end can connect to a grounded outlet. The ground contact is configured to releasably and electrically connect the extension cord to a ground potential on the outlet. |
| US09660378B2 |
Magnetic electrical connector
An electrical connector that includes a first part housing for supporting contacting elements each configured to conductively couple with an electrical power source. First part coupling elements are configured to move between a connected and an unconnected configuration. In the connected configuration, each first part coupling element conductively couples with contacting elements, and in the unconnected configuration the first part coupling elements are not conductively coupled with contacting elements. At least one biasing element is configured to maintain the first part coupling elements in the unconnected configuration. A second part housing supports second part coupling elements each configured to conductively couple with one of the first part coupling elements. At least one magnetic element is configured to move and maintain the first part coupling elements into the connected configuration, wherein in the connected configuration electrical current can flow from the contacting elements to the second coupling elements. |
| US09660376B2 |
Connector insert having a cable crimp portion with protrusions and a receptacle having a label in the front
A magnetic connector system having a durable and reliable construction and a reduced height while maintaining sufficient holding strength. A connector insert may utilize a crimping piece to crimp a braiding of a cable. The crimping piece may be fixed to an attraction plate and a board in the insert for mechanical reliability. Retention clips may be used to fix a shell to the attraction plate. A connector receptacle may employ a magnetically conductive label to improve holding strength. |
| US09660375B2 |
Anti-corrosive material, wire with terminal, and wire harness
An anti-corrosive material includes: an ultraviolet curable resin including a polymerizable compound as a main component, the polymerizable compound composed of at least one of a photopolymerizable (meth)acrylate monomer and a photopolymerizable (meth)acrylate oligomer. The polymerizable compound is composed of a combination of a monofunctional (meth)acrylate monomer and a bifunctional (meth)acrylate monomer, or a combination of at least one of a monofunctional (meth)acrylate monomer and a bifunctional (meth)acrylate monomer and at least one of a trifunctional (meth)acrylate monomer and a polyfunctional (meth)acrylate monomer having four or more functional groups. The anti-corrosive material has a viscosity at 25° C. of 18900 mPa·s or less measured according to JIS Z8803. |
| US09660368B2 |
High performance surface mount electrical interconnect
An interconnect assembly including a substrate with a plurality of through holes extending from a first surface to a second surface. A plurality of discrete contact member are located in the plurality of through holes. The contact members include proximal ends that are accessible from the second surface, distal ends extending above the first surface, and intermediate portions engaged with an engagement region of the substrate located between the first surface and the recesses. Retention members are coupled with at least a portion of the proximal ends to retain the contact members in the through holes. The retention members can be made from a variety of materials with different levels of conductivity, ranging from highly conductive to non-conductive. |
| US09660366B2 |
Device for connecting a radiofrequency circuit or component printed on a flexible support to a coaxial cable
The invention concerns a device (4) for connecting a radio frequency circuit (3) or component printed on a flexible support (2) to a coaxial cable, comprising: —a first part (14) suitable for being disposed against a first face (5) of the support (2) on which the circuit or the component (3) is printed, the first part (14) comprising a recess capable of housing a coaxial cable connector (13), —a second part (15) capable of being disposed against a second face (6) of the support (2), opposite the first face, and in which the first part (14) and/or the second part (15) comprises attachment means for attaching the first part (14) and the second part (15) to each other, the flexible support (2) being clamped between the first part (14) and the second part (15), in such a way as to maintain an electrical contact between the connector (13) and the circuit or component (3). |
| US09660361B2 |
Connector with secure wafer retention
A connector includes a connector body, a plurality of wafers arranged within the connector body, and a weld tab defined by a unitary member that includes a plurality of weld tab legs and a plurality of weld tab arms. The plurality of weld tab arms are arranged to engage with corresponding weld tab arm holes included in the connector body, and the plurality of weld tab legs are arranged to engage with a circuit board when the connector is mounted to the circuit board. The weld tab prevents the plurality of wafers from withdrawing from the connector body when the plurality of weld tab arms are engaged with the corresponding weld tab arm holes. |
| US09660360B2 |
Connector producing a biasing force
A connector includes, in one embodiment, a first component, a coupling element configured to engage the first component, and a second component configured to engage the first component. The second component, in one embodiment, is configured to produce a spring, pushing or biasing force. |
| US09660358B2 |
Contact element for an electrical plug connector device
A contact element for an electrical plug connecting device, having a molded first end section and a molded elongated receiving section which defines a longitudinal axis for mechanical and electrical coupling and/or receiving a mating contact element designed to be complementary to the contact element of a plug connecting device to be paired with the electrical plug connecting device, both of which are manufactured of an electrically conductive material. The elongated receiving section extends essentially cylindrically from the first end section. This end section as well as the elongated cylindrical receiving section are molded to be free of seams and butt joints by shaping the electrically conducting material by means of a force acting at least predominantly parallel to the longitudinal axis, and at least the receiving section molded by shaping the electrically conducting material forms a cylindrical interior sheathed by the molded electrically conducting material along the longitudinal axis. |
| US09660353B2 |
Small-sized elastic inner conductor right-angled elbow conductor connector
A small-sized elastic inner conductor right-angled elbow conductor connector includes: a first conductor capable of deforming elastically, the first conductor having a first axis, the first conductor deforms elastically and springs back in a longitudinal direction perpendicular to the first axis under the action of a second conductor, thereby elastically contacting the second conductor arranged perpendicular to the first axis and retaining the second conductor, when the second conductor is connected with the first conductor, such that the first conductor and the second conductor are able to be connected to each other at a right angle. |
| US09660352B2 |
Antenna system for broadband satellite communication in the GHz frequency range, comprising horn antennas with geometrical constrictions
An antenna system for wireless communication of data includes at least four horn antennas. Each horn antenna is configured to support communications at two mutually orthogonal linear polarizations. Each horn antenna includes an inner wall enclosing a space and geometric constrictions each protruding inwardly from the inner wall into the space along a corresponding polarization plane of one of the two linear polarizations. At least one of the inner wall or the geometric constrictions has a stepped structure. |
| US09660344B2 |
Optically transparent antenna for wireless communication and energy transfer
Embodiments of an optically transparent antenna are generally described herein. In some embodiments, the optically transparent antenna may comprise a plurality of electrically-isolated conductive patches arranged on a non-conductive surface. A combination of a size of the conductive patches and a spacing between the conductive patches is less than a human visual acuity for a predetermined viewing distance so that the patches are not be visible or perceptible to a human. In some embodiments, optically transparent antenna may serve as one or more antennas on a mobile platform. |
| US09660335B2 |
Antenna system and a communication device
An antenna system includes a monopole antenna with a first end connected to a feed point on a printed circuit board (PCB) and a second end being electrically floating; and a matching conductive stub with a first end connected to a ground point on the PCB and a second end being electrically floating. |
| US09660327B2 |
Combination antenna
A combination antenna includes a conductive block having at least one electrical component mounted on the surface. A metallic housing is connected to the conductive block via at least one electronic element having a front surface and a rear surface. The front surface includes one or more plates separated by gaps of a predetermined width. The rear surface includes a continuous plate separated from the front surface by a gap of a second predetermined width. One or more antenna feeds are disposed between the front surface and the rear surface of the metallic housing and are connected to the metallic housing directly or via the at least one electronic element. A grounding plane includes one or more grounding points connected to the front surface and the rear surface directly or via the at least one electronic element. |
| US09660323B2 |
Independent adjustable azimuth multi-band antenna fixture
A combination antenna fixture is configured to accommodate adjustment of independent azimuths for each frequency band of operation of antennas of a mobile telephone network. The antennas may be mounted within a single radome or housing used to protect the antennas from environmental conditions. Each of the antennas may be coupled to a different movable mounting device within a radome, which may enable directing the azimuth for each antenna independently. By directing the azimuth independently for each antenna, the signal coverage area for each antenna may be customized to optimize coverage over a geographic area. |
| US09660320B2 |
High efficiency mounting assembly for satellite dish reflector
A reflector dish assembly including a support structure, a reflector dish, and a reflector bracket configured for mounting the reflector dish. A support arm supports an electronic device and an elbow bracket is configured for coupling with an end of the support arm. A seat section of the elbow bracket is configured for engaging with the reflector bracket for securing the support arm in relation to the reflector dish. The reflector bracket includes a seat to receive the elbow bracket seat section, with the seat having bosses and support tabs spaced linearly from the bosses. The elbow bracket seat section includes guide slots configured for sliding over the bosses when the seat receives the seat section. The elbow bracket seat section includes support slots for receiving the support tabs of the reflector bracket seat and securing the guide slots with the bosses. |
| US09660316B2 |
Millimeter wave dual-mode diplexer and method
An embodiment millimeter wave diplexer includes a substrate integrated waveguide (SIW) high pass filter (HPF), a microstrip line low pass filter (LPF), and a T-junction. The SIW HPF is coupled to a first port, and the microstrip line LPF is coupled to a second port. The SIW HPF is operable in a first frequency band, and the microstrip line LPF is operable in a second frequency band. The T-junction is coupled between the SIW HPF and the microstrip line LPF. The T-junction is also coupled to a common port. |
| US09660315B2 |
Ground structures between resonators for distributed electromagnetic wave filters
A distributed electromagnetic (EM) wave filter includes: a cavity; upper and lower ground planes on top and bottom surfaces of the cavity, wherein the upper and lower ground planes are in electrical contact; a plurality of electromagnetically coupled resonators in said cavity between the upper and lower ground planes that define respective transmission lines, wherein the plurality of resonators are not connected to each other by a conductive connection; an input port coupled to a first one of the plurality of resonators to receive an EM wave; an output port coupled to a last one of the plurality of resonators to output a filtered EM wave; and a plurality of conductive structures between adjacent resonators, respectively and connected to one or more of the upper and lower ground planes. |
| US09660314B1 |
High efficiency plasma tunable antenna and plasma tuned delay line phaser shifter
A tunable antenna includes a patch antenna including a substrate, a metallic patch mounted on a first side of the substrate, a signal line connected through the substrate to the metallic patch, and a ground plane on a second side of the substrate opposite the first side. The tunable antenna includes an ionizable gas adjacent to the patch antenna. |
| US09660309B2 |
Device and method for raising temperature of battery module in eco-friendly vehicle
A device for raising a temperature of a battery module for an eco-friendly vehicle, the battery module including a plurality of battery cells disposed at intervals in a housing thereof, the device blowing air introduced by a blowing fan to the battery cells to raise a temperature of each the battery cell, the device may include a temperature sensor provided on each battery cell for measuring a temperature of corresponding battery cell, a flow passage for guiding air flowed from a blowing fan to each battery cell, and an air flow rate control means provided at a region connecting the flow passage and each battery cell to control the flow rate of air introduced to each battery cell. |
| US09660294B2 |
Electrolyte materials for batteries and methods for use
An electrolyte solution comprising an additive wherein the additive is not substantially consumed during charge and discharge cycles of the electrochemical cell. Additives include Lewis acids, electron-rich transition metal complexes, and electron deficient pi-conjugated systems. |
| US09660290B2 |
Oxidation resistant separator for a battery
A lithium ion rechargeable battery comprises: a negative electrode adapted to give up electrons during discharge, a positive electrode adapted to gain electrons during discharge, a microporous separator sandwiched between said positive electrode and said negative electrode, an organic electrolyte being contained within said separator and being in electrochemical communication with said positive electrode and said negative electrode, and an oxidative barrier interposed between said separator and said positive electrode, and thereby preventing oxidation of said separator. |
| US09660288B2 |
Battery subunit having multiple battery modules that are connected to one another in a parallel and/or series manner, battery system and method for producing a battery subunit
A battery subunit includes multiple battery modules that are connected to one another in a parallel and/or series manner, and a thermal management system that contacts each of the multiple battery modules. Each of the multiple battery modules has respective multiple battery cells. The thermal management system is configured to dissipate heat that occurs during operation of the multiple battery modules. The battery subunit further includes a carrier unit that comprises at least one carrier plate positioned on a side of the thermal management system that is remote from the battery modules. The thermal management system is configured to at least partially receive, and on at least two opposite lying edges comprises, in each case, one or multiple grooves configured to collect and/or drain off at least one of fluids that are situated in the at least one carrier plate, and condensation water and/or leakage from the thermal management system. |
| US09660286B1 |
Method for assembly of a microbial fuel cell
An anode/cathode system is disclosed for use in a Benthic microbial fuel cell. Carbon cloth forms at least a portion of the anode and is disposed on one side of a water oxygen impermeable layer, which can be weighted around a periphery thereof to hold the anode against a water-sediment interface. Carbon cloth flaps or strands can be attached to the other side of the impermeable layer to form the cathode. The anode and cathode can be divided into sections with each section having an electrical lead coupled thereto. The system is deployed onto the seafloor with the anode side in contact with the water-sediment interface. |
| US09660282B2 |
Fuel cell system and method of controlling the fuel cell system
A control device of a fuel cell system includes an electric conductivity comparing unit for comparing the electric conductivity of the water inside the ion exchanger which is measured by the electric conductivity measuring unit with a predetermined electric conductivity range, and an ion exchange environment determining unit for arbitrarily determining whether or not air has been mixed into an ion exchanger and whether or not the ion exchange efficiency of the ion exchanger has been degraded, based on a comparison result by the electric conductivity comparing unit. |
| US09660279B2 |
Fuel unit for hydrogen generator
Disclosed are a fuel unit for a hydrogen generator and methods for producing the fuel unit and the hydrogen generator. A fuel sheet (50) is made by disposing a plurality of fuel pellets (50A-50J) containing a hydrogen-containing material on a substrate (52), and one or more fuel sheets are formed into a non-cylindrical fuel sheet assembly my moving (e.g., bending) a portion of the fuel sheet (50) to position pellets adjacent to each other such that adjacent sides of the adjacent pellets lie in essentially parallel planes. A non-cylindrical fuel unit is produced from one or more of the fuel sheet assemblies. Fuel units can be replaceably disposed in a hydrogen generator, and fuel pellets can be selectively heated to produce hydrogen gas as needed. |
| US09660277B2 |
Methods for inhibiting corrosion in brazed metal surfaces and coolants and additives for use therein
Disclosed are coolants comprising brazed metal corrosion inhibitors. |
| US09660274B2 |
Iron coated chromium powder and SOFC IC made therefrom
A component, such as a SOFC interconnect, and methods of making the component are provided using various chromium powders, including powder particles with a chromium core covered with an iron shell, a pre-alloyed Cr—Fe powder or a chromium powder produced by hydrogen reduction with hydrogen. |
| US09660270B2 |
Method for producing garnet-type compound, garnet-type compound, and all-solid lithium secondary cell containing said garnet-type compound
The present invention provides a production method that can produce a garnet-type compound containing zirconium and lithium, the compound being in the form of fine particles, with high productivity. The method produces a garnet-type compound containing Zr, Li, and element M1 (wherein M1 is at least one element selected from the group consisting of La, Sc, Y, and Ce) as constituent elements. The method includes a first step of (1) mixing a first raw material and a second raw material to obtain a precipitate, the first raw material being a solution containing a zirconium carbonate complex and having a pH of at least 7.0 and not more than 9.5, and the second raw material containing a compound containing the above element M1 as a constituent element; and (2) a second step of mixing the precipitate and a third raw material containing Li as a constituent element to obtain a mixture, and then firing the mixture at a temperature of less than 1,000° C. to obtain a fired product. The first raw material is prepared by mixing, at a prescribed molar ratio, at least a compound that contains a carbonate species and a compound that contains a zirconium species. |
| US09660269B2 |
Electrode for lithium secondary battery and lithium secondary battery
The present invention provides positive and negative electrodes, for a lithium secondary battery, allowing a battery to be quickly and fully charged in a very short period of time, for example, within one minute and allowing the battery to be used for vehicles at low temperatures. An organic electrolytic solution is permeated into an electrode group formed by winding positive and negative electrodes or by laminating the positive and negative electrodes one upon another with a separator being interposed therebetween to repeatingly occlude and release lithium ions. The positive electrode active substance and the negative electrode active substance have at least one phase selected from among a graphene phase and an amorphous phase as a surface layer thereof. An activated carbon layer is formed on a surface of the positive electrode active substance and that of the negative electrode active substance. |
| US09660266B2 |
Lithium secondary battery
Disclosed is a lithium secondary battery including (i) a cathode active material including a lithium metal phosphate according to Formula 1 below, (ii) an anode active material including amorphous carbon, and (iii) an electrolyte for lithium secondary batteries including a lithium salt and an ether-based solvent, Li1+aM(PO4-b)Xb (1) wherein M is at least one selected from the group consisting of Group II to XII metals, X is at least one selected from F, S, and N, −0.5≦a≦+0.5, and 0≦b≦0.1. |
| US09660265B2 |
Lithium sulfur batteries and electrolytes and sulfur cathodes thereof
Lithium sulfur battery cells that use water as an electrolyte solvent provide significant cost reductions. Electrolytes for the battery cells may include water solvent for maintaining electroactive sulfur species in solution during cell discharge and a sufficient amount of a cycle life-enhancing compound that facilitates charging at the cathode. The combination of these two components enhances one or more of the following cell attributes: energy density, power density and cycle life. For instance, in applications where cost per Watt-Hour (Wh) is paramount, such as grid storage and traction applications, the use of an aqueous electrolyte in combination with inexpensive sulfur as the cathode active material can be a key enabler for the utility and automotive industries, for example, providing a cost effective and compact solution for load leveling, electric vehicles and renewable energy storage. Sulfur cathodes, and methods of fabricating lithium sulfur cells, in particular for loading lithium sulfide into the cathode structures, provide further advantages. |
| US09660262B2 |
Nonaqueous electrolyte secondary battery
A positive electrode for a nonaqueous electrolyte secondary battery according to the present invention includes particles A of a lamellar type lithium transition metal oxide and particles B of a spinel type lithium transition metal oxide, as a positive active material, at a ratio within the range of A:B=20:80 to 80:20 (weight ratio), in which a particle size distribution of the positive active material has a peak based on the particles A and a peak based on the particles B within the range of 1 to 50 μm. In the integrated distribution curve of the particle diameter, a particle diameter A(D50) at a degree of accumulation of the particles A of 50% and a particle diameter B(D50) at a degree of accumulation of the particles B of 50% satisfy the following expression (1), and a particle diameter A(D95) at a degree of accumulation of the particles A of 95% and a particle diameter B(D5) at a degree of accumulation of the particles B of 5% satisfy the following expression (2): B(D50)−A(D50)≧5 μm Expression (1) B(D5)>A(D95) Expression (2). |
| US09660259B2 |
Positive electrode active material with improved output and lithium secondary battery comprising the same
A mixed positive electrode active material comprising a lithium manganese oxide represented by following [Chemical Formula 1] and a second positive electrode active material represented by following [Chemical Formula 2], and a lithium secondary battery comprising the same are disclosed. aLi2MnO3.(1−a)LixMO2 [Chemical Formula 1] In [Chemical Formula 1], 0 |
| US09660256B2 |
Storage element for a solid electrolyte battery
A storage element for a solid electrolyte battery is provided, having a main member including a porous ceramic matrix in which particles that are made of a first metal and/or a metal oxide and jointly form a redox couple are embedded. The storage element further includes particles made of another metal and/or an associated metal oxide, the other metal being electrochemically more noble than the first metal. |
| US09660254B2 |
Method for producing silicon-based negative electrode active material, negative electrode active material for lithium secondary battery, and lithium secondary battery comprising same
The present invention relates to a method for preparing a silicon-based negative electrode active material, a negative electrode active material for a lithium secondary battery, and a lithium secondary battery comprising the same. More particularly, the method for preparing the silicon-based negative electrode active material comprises: preparing a porous silica (SiO2) and a thin metal film; coating the porous silica onto the thin metal film; reducing the porous silica to a porous silicon by performing heat-treatment of the thin metal film and the porous silica; and obtaining the porous silicon. |
| US09660252B2 |
Method for the production of electrodes for fully solid batteries
The invention relates to a process for fabrication of an electrode film in an all-solid-state battery comprising successive steps to: a) Procure a substrate, preferably a conducting substrate, b) Deposit an electrode film on said substrate by electrophoresis, from a suspension containing particles of electrode materials, c) Dry the film obtained in the previous step, d) Thermal consolidation of the electrode film obtained in the previous step by sintering, sintering being done at a temperature TR that preferably does not exceed 0.7 times the melting temperature (expressed in ° C.), even more preferably does not exceed 0.5 times the melting temperature (expressed in ° C.), and much more preferably does not exceed 0.3 times the melting temperature (expressed in ° C.) of the electrode material that melts at the lowest temperature. |
| US09660251B2 |
Electric storage device and manufacturing method thereof
Provided is an electric storage device including: a first electrode plate; a second electrode plate having a polarity opposite to that of the first electrode plate; and a separator interposed between the first electrode plate and the second electrode plate, wherein the first electrode plate includes a current collector and a mixture layer laminated onto the current collector, the mixture layer contains at least one of the binder and the conductive additive, primary particles of an active material, and secondary particles each having a hollow region formed therein by aggregation of a plurality of the primary particles, and the at least one of the binder and the conductive additive is partially distributed in the hollow region. |
| US09660250B2 |
Secondary battery, and electrode sheet cutting apparatus
A secondary battery 100 comprises a positive electrode current collector 221 and a positive electrode active material layer 223 applied on the positive electrode current collector 221 and containing at least a positive electrode active material. The lithium-ion secondary battery 100 further comprises a negative electrode current collector 241 provided so as to oppose the positive electrode current collector 221 and a negative electrode active material layer 243 applied on the negative electrode current collector 241 and containing at least a negative electrode active material. The lithium-ion secondary battery 100 is also formed with a porous insulating layer 245 which contains stacked resin particles having insulating properties and is formed so as to cover at least one of the positive electrode active material layer 223 and the negative electrode active material layer 243 (in this case, negative electrode active material layer 243). The lithium-ion secondary battery 100 further comprises, on the edge of the insulating layer 245, a molten part 246 where the resin particles are melted. |
| US09660247B2 |
Secondary battery manufacturing method and secondary battery
A secondary battery includes, in a battery case, an electrode body having an electrode sheet, a current collecting member including a weld part ultrasonic welded to a current collecting foil of the electrode sheet, and a pressure-type current interrupt mechanism electrically connected to the current collecting member. The current interrupt mechanism has a first valve element integrated with the current collecting member and a second element body, both joined at a joint portion. Of the current collecting member, the first valve element, and the second valve element, at least a part between the weld part and the joint portion is made of damping metal. A method of manufacturing this secondary battery includes: a step of forming a structure in which the first and second valve elements are joined at the joint portion; and a step of thereafter ultrasonic welding the current collecting foil and the weld part. |
| US09660246B2 |
Battery terminal
A battery terminal includes a terminal body and a component terminal. The terminal body is connected to a rod-like electrode which projects from a terminal mounting surface of a battery and extends toward an outer periphery of the terminal mounting surface. An external fuse (electrical component) is connected to the component terminal. The terminal body and the component terminal are formed by being cut integrally from a single plate made of a conductive metal. |
| US09660245B2 |
Battery cell
Provided is a battery cell including: an electrode assembly including a first electrode part, a second electrode part, and a separation membrane; a first terminal and a second terminal extending in a first direction or a fourth direction which is an opposite direction to the first direction from the first electrode part and the second electrode part, respectively; a first lead tap and a second lead tap connected to the first terminal and the second terminal, respectively; and a case in which the electrode assembly, the first terminal, and the second terminal are accommodated, which is sealed to expose the first lead tap and the second lead tap to the outside, and in which a sealing part sealed by coating a sealing member on circumferential sides joined with each other is formed. |
| US09660241B2 |
NASICON-polymer electrolyte structure
A method is provided for forming a sodium-containing particle electrolyte structure. The method provides sodium-containing particles (e.g., NASICON), dispersed in a liquid phase polymer, to form a polymer film with sodium-containing particles distributed in the polymer film. The liquid phase polymer is a result of dissolving the polymer in a solvent or melting the polymer in an extrusion process. In one aspect, the method forms a plurality of polymer film layers, where each polymer film layer includes sodium-containing particles. For example, the plurality of polymer film layers may form a stack having a top layer and a bottom layer, where with percentage of sodium-containing particles in the polymer film layers increasing from the bottom layer to the top layer. In another aspect, the sodium-containing particles are coated with a dopant. A sodium-containing particle electrolyte structure and a battery made using the sodium-containing particle electrolyte structure are also presented. |
| US09660239B2 |
Positive active material layer for rechargeable lithium battery, separator for rechargeable lithium battery, and rechargeable lithium battery including at least one of same
A positive active material layer for a rechargeable lithium battery including a positive active material and a protection film-forming material is disclosed. A separator for a rechargeable lithium battery including a substrate and a porous layer positioned at least one side of the substrate and including a protection film-forming material is also disclosed. A rechargeable lithium battery can include at least one of the positive active material layer and the separator. |
| US09660235B2 |
Assembly with a first and a second component and method for producing such an assembly
The present invention relates to an assembly (10) with a first and a second component (1, 2) which are fixed relative to each other by at least one fixation element (3), characterized by a fixation element (3) extending into or through a space (9) between the first and the second component (1, 2), wherein the fixation element (3) is filled with a hardenable filling material (61), wherein the fixation element (3) is a hollow deformable and at least in a radial direction expandable element if internally pressurized, at least before the filling material (61) hardens. The present invention also relates to a method for producing an assembly with a first and a second component. |
| US09660233B2 |
Base plate of battery module assembly with novel structure
Disclosed herein is a base plate of a battery module assembly, wherein the base plate is made of a metal sheet having module receiving parts, on which one or more battery modules each including battery cells are loaded, formed at a top thereof, the sheet is provided at at least a portion of an outer edge thereof with upwardly bent side walls, and the module receiving parts are provided with reinforcement beads protruding toward the battery modules. |
| US09660232B2 |
Button cell terminal
A button cell terminal to electrically connect to a button cell and a circuit board includes: a spring contact terminal; a board joint; and a pressing force absorbing spring portion. The spring contact terminal is arranged into a spring shape deforming elastically in response to pressing force from the button cell in the X-axis direction and the Z-axis direction. The board joint is joined to the circuit board. The pressing force absorbing spring portion includes a bent arm for absorbing pressing force from the button cell through elastic deformation in response to pressing force from the button cell in the X-axis direction and the Y-axis direction. |
| US09660226B2 |
Packaging material for lithium-ion battery
A packaging material for lithium-ion battery comprises a substrate layer made of a plastic film, and a first adhesive layer, a metal foil layer, an anti-corrosion layer, a second adhesive layer and a sealant layer successively laminated on one surface of the substrate layer. The plastic film has a water absorption rate of not less than about 01% to not larger than about 3% when determined by a method described in JIS K 7209:2000 and when the plastic film is subjected to a tensile test (wherein the sample of the plastic film is stored for 24 hours in an environment of 23° C. and 40% R.H., and subjected to a tensile test in the same environment as indicated above under conditions of a sample width of 6 mm, a gauge length of 35 mm and a tensile speed of 300 mm/minute), stress values in an MD direction of the sample and in a TD direction of the sample after stretching by about 10% relative to a length of the sample prior to the tensile test are both from not larger than about 110 MPa and at least one of the stress values in the MD direction of the sample and in the TD direction of the sample is not less than about 70 MPa. |
| US09660225B2 |
Secondary battery, electronic device, and vehicle
Provided is a secondary battery suitable for a portable information terminal or a wearable device, or an electronic device having a novel structure with a variety of forms and a secondary battery that fits the form of the electronic device. The secondary battery is sealed using a film having projections that can reduce stress on the film caused when external force is applied. The film has a pattern of projections formed by pressing (e.g., embossing). A top portion of each of the projections has a region thicker than a bottom portion of each of the projections. The thickness of the top portion of each of the projections is 1.5 or more times, preferably 2 or more times, as large as that of the bottom portion of each of the projections, and is a thickness such that each of the projections has a convex space. |
| US09660218B2 |
Package of environmental sensitive element
In one embodiment, a package of an environmental sensitive element including a flexible substrate, an environmental sensitive element and an encapsulation is provided. The environmental sensitive element is disposed on the flexible substrate. The encapsulation covers the environmental sensitive element, wherein the Young's mudulus of the encapsulation ranges from about 5 GPa to about 15 GPa, hardness of the encapsulation ranges from about 0.4 GPa to about 1.0 GPa, and water vapor transmittance rate (WVTR) of the encapsulation is less than 10−2 g/cm2 day. |
| US09660215B2 |
Display panel and encapsulation method thereof
Embodiments of the present invention disclose a display panel and an encapsulation method thereof, and relate to the field of display technology. The display panel comprises a first substrate and a second substrate which are disposed in opposition to each other. The first substrate and the second substrate are encapsulated by a sealant. In a non-display area of the display panel, a first adsorption layer is disposed on one of the first substrate and the second substrate, and a second adsorption layer is disposed on the other of the first substrate and the second substrate. The first adsorption layer and the second adsorption layer may be attracted to each other by magnetic force. Embodiments of the present invention can effectively avoid the separation of the first substrate and the second substrate due to the stress released during the process of melting the sealant, thereby improving the problem of poor encapsulation caused thereby. |
| US09660213B2 |
Organic EL element and manufacturing method thereof, and metal oxide film forming method
An organic EL element including: an anode and a cathode disposed to face each other with a gap therebetween; a functional layer that contains an organic material and is disposed between the anode and the cathode; and an electron injection layer that has a function to inject electrons into the functional layer and is disposed between the anode and the cathode. The electron injection layer contains a metal oxide with d0 electron configuration, and a Fermi level of the electron injection layer is located in a vicinity of a lower end of a conduction band of the electron injection layer. |
| US09660211B2 |
Light-emitting element, light-emitting device, display device, electronic appliance, and lighting device
A multicolor light-emitting element using fluorescence and phosphorescence, which has a small number of manufacturing steps owing to a relatively small number of layers to be formed and is advantageous for practical application can be provided. In addition, a multicolor light-emitting element using fluorescence and phosphorescence, which has favorable emission efficiency is provided. A light-emitting element which includes a light-emitting layer having a stacked-layer structure of a first light-emitting layer exhibiting light emission from a first exciplex and a second light-emitting layer exhibiting phosphorescence is provided. |
| US09660210B2 |
Method for manufacturing OLED device and OLED device manufactured therewith
The present invention provides a method for manufacturing an OLED device and an OLED device manufactured therewith. The method for manufacturing an OLED device includes: (1) providing a substrate and forming, in sequence, an anode and a hole transporting layer on the substrate; (2) forming an emissive layer on the hole transporting layer through a solution film casting process, wherein the emissive layer comprises a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, of which at least one sub-pixel is formed of a quantum dot and at least one sub-pixel is formed of an organic light-emitting material; (3) forming, in sequence, an electron transporting layer and a cathode on the emissive layer; and (4) providing a package cover plate, which is set above the cathode, wherein the substrate and the package cover plate are bonded together by sealing enclosing resin to complete packaging of the OLED device. Since each sub-pixel of the emissive layer is formed through a solution film casting process, the manufacture of the OLED device requires no use of a fine metal mask so that the manufacturing cost is low, the utilization rate of material is high, and the yield rate is good. |
| US09660209B2 |
Method for manufacturing OLED device and OLED device manufactured therewith
The present invention provides a method for manufacturing an OLED device and an OLED device manufactured therewith. The method for manufacturing an OLED device includes: (1) providing a substrate and forming, in sequence, an anode and a hole transporting layer on the substrate; (2) forming an emissive layer on the hole transporting layer through a solution film casting process, wherein the emissive layer comprises a red sub-pixel, a green sub-pixel, and a blue sub-pixel, of which at least one sub-pixel is formed of a quantum dot and at least one sub-pixel is formed of an organic light-emitting material; (3) forming, in sequence, an electron transporting layer and a cathode on the emissive layer; and (4) providing a package cover plate, which is set above the cathode, wherein the substrate and the package cover plate are bonded together by sealing enclosing resin to complete packaging of the OLED device. Since each sub-pixel of the emissive layer is formed through a solution film casting process, the manufacture of the OLED device requires no use of a fine metal mask so that the manufacturing cost is low, the utilization rate of material is high, and the yield rate is good. |
| US09660206B2 |
Vertical organic transistor and production method
The invention relates to a vertical organic transistor on a substrate having an electrode, a counter electrode and a layer arrangement which is arranged between the electrode and the counter electrode, wherein the layer arrangement is formed with the following layers: a central electrode, an organic layer made up of organic semiconductor material which is arranged between the central electrode and the electrode, a further organic layer made up of organic semiconductor material, which is arranged between the central electrode and the counter electrode, and a doping layer which is arranged between the central electrode and the electrode. Furthermore, the invention relates to a method for producing a vertical organic transistor. |
| US09660204B2 |
Silane-based compound and organic light-emitting device including the same
A silane-based compound and an organic light-emitting device including the same, the compound being represented by Formula 1: |
| US09660195B2 |
Anthracene derivative having a phenanthryl group
Anthracene derivatives each having a structure including an anthracene skeleton, a phenanthrene skeleton selected from among various phenanthrene skeletons different in bonding site which is bonded to the 9-position of the anthracene skeleton and a group selected from among various aryl groups and so on which is bonded to the 10-position of the anthracene skeleton. Organic EL devices made by using the derivatives exhibit high light emission efficiency and a long life. |
| US09660194B2 |
Copolymer and organic solar cell comprising same
The present specification provides a copolymer and an organic solar cell including the same. |
| US09660187B1 |
Methods of forming a layer and methods of manufacturing magnetic memory devices using the same
A method of forming a layer includes providing a first insulator and a second insulator over a lower structure, generating a first ion source and a second ion source from the first insulator and the second insulator, respectively, and forming an insulating layer on the lower structure using the first ion source and the second ion source. The first and second insulators are vertically spaced apart from the lower structure and are laterally spaced apart from each other. The first insulator and the second insulator include the same material. |
| US09660180B2 |
Current constriction for spin torque MRAM
Magnetoresistive random access memory (MRAM) devices include a first magnetic layer. A tunnel barrier layer is formed on the first magnetic layer. The tunnel barrier includes first regions having a first thickness and second regions having a second thickness that is greater than the first thickness. A second magnetic layer is formed on the tunnel barrier layer. |
| US09660176B2 |
Method of manufacturing electronic device, electronic apparatus, and mobile apparatus
A method of manufacturing an electronic device including an electronic element, a base substrate, and a lid member, includes joining the lid member to the sealing part by application of an energy beam so that a plate thickness of the lid member may be larger in a part joined to the sealing part than in a part located inside of the part in a plan view along the thickness direction. |
| US09660175B2 |
Piezoelectric ceramic, method for manufacturing piezoelectric ceramic, piezoelectric element, and electronic device
A piezoelectric ceramic contains a main component, Mn as a first auxiliary component, and a second auxiliary component containing at least one element selected from the group consisting of Cu, B, and Si. The main component contains a perovskite metal oxide having the following general formula (1): (Ba1-xCax)a(Ti1-yZry)O3(0.100≦x≦0.145,0.010≦y≦0.039) (1) The amount b (mol) of Mn per mole of the metal oxide is in the range of 0.0048≦b≦0.0400, the second auxiliary component content on a metal basis is 0.001 parts by weight or more and 4.000 parts by weight or less per 100 parts by weight of the metal oxide, and the value a of the general formula (1) is in the range of 0.9925+b≦a≦1.0025+b. |
| US09660170B2 |
Micromachined ultrasonic transducer arrays with multiple harmonic modes
Micromachined ultrasonic transducer (MUT) arrays capable of multiple resonant modes and techniques for operating them are described, for example to achieve both high frequency and low frequency operation in a same device. In embodiments, various sizes of piezoelectric membranes are fabricated for tuning resonance frequency across the membranes. The variously sized piezoelectric membranes are gradually transitioned across a length of the substrate to mitigate destructive interference between membranes oscillating in different modes and frequencies. |
| US09660155B2 |
Light emitting diode
Provided are a light emitting diode, a method of manufacturing the same, and a use thereof. The light emitting diode having excellent initial light flux and excellent color uniformity and dispersion, the method of manufacturing the same, and the use thereof may be provided. |
| US09660153B2 |
Gap engineering for flip-chip mounted horizontal LEDs
A horizontal LED die is flip-chip mounted on a mounting substrate to define a gap that extends between the closely spaced apart anode and cathode contacts of the LED die, and between the closely spaced apart anode and cathode pads of the substrate. An encapsulant is provided on the light emitting diode die and the mounting substrate. The gap is configured to prevent sufficient encapsulant from entering the gap that would degrade operation of the LED. |
| US09660151B2 |
Method for manufacturing light emitting device
A method for manufacturing a light emitting device has: forming a first phosphor layer including a first phosphor that is based on KSF or quantum dots on a light emitting element by a method other than spraying, and forming a second phosphor layer including a second phosphor that is different from the first phosphor on the first phosphor layer by spraying. |
| US09660147B2 |
Method for providing a reflective coating to a substrate for a light emitting device
The present invention relates to a method for providing a reflective coating (114) to a substrate (104) for a light-emitting device (112), comprising the steps of: providing (201) a substrate (104) having a first surface portion (116) with a first surface material and a second surface portion (106, 108) with a second surface material different from the first surface material; applying (202) a reflective compound (401) configured to attach to said first surface material to form a bond with the substrate (104) in the first surface portion (116) that is stronger than a bond between the reflective compound (401) and the substrate (104) in the second surface portion (106, 108); curing (203) said reflective compound (401) to form a reflective coating (114) having said bond between the reflective coating (114) and the substrate (104) in the first surface portion (116); and subjecting said substrate (104) to a mechanical treatment with such an intensity as to remove (205) said reflective coating (114) from said second surface portion (106, 108) while said reflective coating (114) remains on said first surface portion (116). |
| US09660135B2 |
Enhanced performance active pixel array and epitaxial growth method for achieving the same
Methods are described to utilize relatively low cost substrates and processing methods to achieve enhanced emissive imager pixel performance via selective epitaxial growth. An emissive imaging array is coupled with one or more patterned compound semiconductor light emitting structures grown on a second patterned and selectively grown compound semiconductor template article. The proper design and execution of the patterning and epitaxial growth steps, coupled with alignment of the epitaxial structures with the imaging array, results in enhanced performance of the emissive imager. The increased luminous flux achieved enables use of such images for high brightness display and illumination applications. |
| US09660134B1 |
Nitride semiconductor polarization controlled device
A polarization controlled device has a first layer comprising a group III-nitride semiconductor substrate or template; a second group III-nitride semiconductor layer disposed over the group III-nitride semiconductor substrate or template; a third group III-nitride semiconductor layer disposed over the second group III-nitride semiconductor layer; and a fourth group III-nitride semiconductor layer disposed over the third group III-nitride semiconductor layer. A pn junction is formed at an interface between the third and fourth group III-nitride semiconductor layers. A polarization heterojunction is formed between the second group III-nitride semiconductor layer and the third group III-nitride semiconductor layer. The polarization junction has fixed charges of a polarity on one side of the polarization junction and fixed charges of an opposite polarity on an opposite side of the polarization junction. When unbiased, the pn junction comprises a first electric field that opposes the flow of carriers across the pn junction and the polarization junction comprises a second electric field that opposes the flow of oppositely charged carriers across the polarization junction. |
| US09660130B2 |
Passivation stack on a crystalline silicon solar cell
A method for manufacturing a passivation stack on a crystalline silicon solar cell device. The method includes providing a substrate comprising a crystalline silicone layer such as a crystalline silicon wafer or chip, cleaning a surface of the crystalline silicon layer by removing an oxide layer at least from a portion of one side of the crystalline silicon layer, depositing, on at least a part of the cleaned surface, a layer of silicon oxynitride, and depositing a capping layer comprising a hydrogenated dielectric material on top of the layer of silicon oxynitride, wherein the layer of silicon oxynitride is deposited at a temperature from 100° C. to 200° C., and the step of depositing the layer of silicon oxynitride includes using N2O and SiH4 as precursor gasses in an N2 ambient atmosphere and depositing silicon oxynitride with a gas flow ratio of N2O to SiH4 below 2. |
| US09660128B2 |
Paste for preparing mask patterns and manufacturing method of solar cell using the same
Provided are a paste for preparing etching mask patterns and a manufacturing method of a silicon solar cell using the same. The paste composition for preparing mask patterns is used to form a selective emitter of a silicon solar cell, and includes inorganic powder, an organic solvent, a binder resin, and a plasticizer. The mask patterns prepared from the paste composition have good adhesion with a substrate, thereby preventing edge curling, and have good etching resistant characteristic in an etch-back process for forming a selective emitter, enabling formation of a stable emitter. |
| US09660123B2 |
Fresnel lens solar concentrator configured to focus sunlight at large longitudinal incidence angles onto an articulating energy receiver
This invention includes a Fresnel lens assembly positioned relative to an energy receiver, onto which the lens assembly focuses sunlight for collection and conversion. The Fresnel lens assembly includes a thin polymeric film with prisms molded into or attached to the film. This invention also includes an articulating energy receiver which can move closer to or farther away from the lens depending on the longitudinal angle of incidence of the sunlight relative to the lens, to maintain the best focus of sunlight on the energy receiver. The prisms in the present lens are specified to provide acceptable optical performance in the presence of relatively large longitudinal solar incidence angles, relatively smaller lateral solar incidence angles, in combination with the articulating energy receiver. The new lens assembly can further be deployed and supported as a thin flexible stretched membrane with tension maintaining the lens in proper position on orbit. |
| US09660121B2 |
Method for fabricating a solar module of rear contact solar cells using linear ribbon-type connector strips and respective solar module
A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells (1) are provided with a large size of e.g. 156×156 mm2. Soldering pad arrangements (13, 15) applied on emitter contacts (5) and base contacts (7) are provided with one or more soldering pads (9, 11) arranged linearly. The soldering pad arrangements (13, 15) are arranged asymmetrically with respect to a longitudinal axis (17). Each solar cell (1) is then separated into first and second cell portions (19, 21) along a line (23) perpendicular to the longitudinal axis (17). Due to such cell separation and the asymmetrical design of the soldering pad arrangements (13, 15), the first and second cell portions (19, 21) may then be arranged alternately along a line with each second cell portion (21) arranged in a 180°-orientation with respect to the first cell portions (19) and such that emitter soldering pad arrangements (13) of a first cell portion (19) are aligned with base soldering pad arrangements (15) of neighboring second cell portions (21), and vice versa. Simple linear ribbon-type connector strips (25) may be used for interconnecting the cell portions (19, 21) by soldering onto the underlying aligned emitter and base soldering pad arrangements (13, 15). The interconnection approach enables using standard ribbon-type connector strips (25) while reducing any bow as well as reducing series resistance losses. |
| US09660113B2 |
Solar cell apparatus and method of fabricating the same
A solar cell apparatus according to the embodiment includes a support substrate including a plurality of patterns; a back electrode layer on the support substrate; a light absorbing layer on the back electrode layer; a buffer layer on the light absorbing layer; and a front electrode layer on the buffer layer, wherein the patterns are formed in an undercut structure including a first inner side surface, a second inner side surface and a bottom surface. |
| US09660111B2 |
Luminescent materials that emit light in the visible range or the near infrared range and methods of forming thereof
Luminescent materials and methods of forming such materials are described herein. A method of forming a luminescent material includes: (1) providing a source of A and X, wherein A is selected from at least one of elements of Group 1, and X is selected from at least one of elements of Group 17; (2) providing a source of B, wherein B is selected from at least one of elements of Group 14; (3) subjecting the source of A and X and the source of B to vacuum deposition to form a precursor layer over a substrate; (4) forming an encapsulation layer over the precursor layer to form an assembly of layers; and (5) heating the assembly of layers to a temperature Theat to form a luminescent material within the precursor layer. |
| US09660109B2 |
Semiconductor device
A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source terminal, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second source electrically connected to the first drain, a second drain electrically connected to a voltage terminal, and a second gate electrically connected to the first source, a coil component provided between the voltage terminal and the second drain, and a first diode having a first anode electrically connected to the first drain and the second source, and a first cathode electrically connected to the coil component and the voltage terminal. |
| US09660106B2 |
Flash memory and method of manufacturing the same
A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion. |
| US09660103B2 |
Thin film transistor and method for manufacturing same
This thin film transistor comprises, on a substrate, at least a gate electrode, a gate insulating film, an oxide semiconductor layer, a source-drain electrode, and two or more protective films. The oxide semiconductor layer comprises Sn, O and one or more elements selected from the group consisting of In, Ga and Zn. In addition, the two or more protective films are composed of at least a first protective film that is in contact with the oxide semiconductor film, and one or more second protective films other than the first protective film. The first protective film is a SiOx film having a hydrogen concentration of 3.5 atomic % or lower. |
| US09660101B2 |
Semiconductor device comprising an oxide semiconductor layer
Oxide layers which contain at least one metal element that is the same as that contained in an oxide semiconductor layer including a channel are formed in contact with the top surface and the bottom surface of the oxide semiconductor layer, whereby an interface state is not likely to be generated at each of an upper interface and a lower interface of the oxide semiconductor layer. Further, it is preferable that an oxide layer, which is formed using a material and a method similar to those of the oxide layers be formed over the oxide layers Accordingly, the interface state hardly influences the movement of electrons. |
| US09660098B2 |
Semiconductor device and method for manufacturing the same
Stable electrical characteristics and high reliability are provided for a miniaturized semiconductor device including an oxide semiconductor, and the semiconductor device is manufactured. The semiconductor device includes a base insulating layer; an oxide stack which is over the base insulating layer and includes an oxide semiconductor layer; a source electrode layer and a drain electrode layer over the oxide stack; a gate insulating layer over the oxide stack, the source electrode layer, and the drain electrode layer; a gate electrode layer over the gate insulating layer; and an interlayer insulating layer over the gate electrode layer. In the semiconductor device, the defect density in the oxide semiconductor layer is reduced. |
| US09660096B2 |
Semiconductor device
A transistor is provided in which the bottom surface portion of an oxide semiconductor film is provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film, and an insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. In addition, the oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) through heat treatment in which impurities such as hydrogen, moisture, hydroxyl, and hydride are removed from the oxide semiconductor and oxygen which is one of main component materials of the oxide semiconductor is supplied and is also reduced in a step of removing impurities. |
| US09660089B2 |
Thin film transistor substrate and method of manufacturing the same
A thin film transistor substrate includes a substrate, a data line disposed on the substrate and which extends substantially in a predetermined direction, a light blocking layer disposed on the substrate and including a metal oxide including zinc manganese oxide, zinc cadmium oxide, zinc phosphorus oxide or zinc tin oxide, a gate electrode disposed on the light blocking layer, a signal electrode including a source electrode and a drain electrode spaced apart from the source electrode, where the source electrode is connected to the data line, and a semiconductor pattern disposed between the source electrode and the drain electrode. |
| US09660086B2 |
Fin-shaped field effect transistor
The present invention provides a fin-shaped field effect transistor (FinFET), comprises: a substrate having a fin structure; a plurality trenches formed on the fin structure with an alloy grown in the trenches; a gate structure on the fin structure perpendicular to an extending direction of the fin structure in-between the plurality of trenches; and an amorphous layer on a surface of the fin structure exposed by the gate structure and disposed in-between the gate structure and the alloy. The invention also provides a manufacturing method of a fin-shaped field effect transistor (FinFET). |
| US09660085B2 |
Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof
Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form. |
| US09660084B2 |
Semiconductor device structure and method for forming the same
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess. |
| US09660081B2 |
Method to form localized relaxed substrate by using condensation
Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs. |
| US09660078B2 |
Enhanced dislocation stress transistor
A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation. |
| US09660073B1 |
High-voltage semiconductor device and method for manufacturing the same
A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a well region of a first conductivity type and an isolation structure in the well region. First and second regions are respectively defined on both sides of the isolation structure. First and second gate structures are respectively disposed on the first and second regions. First and second implant regions of a second conductivity type that is different from the first conductivity type are respectively in the first and second regions and adjacent to the isolation structure. A counter implant region is in the well region under the isolation structure and laterally extends under the first and second implant regions. The counter implant region has the first conductivity type and has a doping concentration that is greater than that of the well region. A method for fabricating the high-voltage semiconductor device is also disclosed. |
| US09660071B2 |
Semiconductor device
A semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a conductive layer, a gate electrode, and a first electrode. The conductive layer includes a first portion, a second portion, and a third portion. The first portion is surrounded by the first semiconductor region via a first insulating portion. The second portion extends in a second direction, is provided on the first semiconductor region, and is provided on the second region. The third portion is connected between the first portion and the second portion and extends in a third direction. The first electrode is electrically connected to the third semiconductor region and the conductive layer. The second portion electrically connects the first electrode to the third portion. |
| US09660069B2 |
Group III nitride integration with CMOS technology
A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer. |
| US09660068B2 |
Nitride semiconductor
According to this GaN-based HFET, resistivity ρ of a semi-insulating film forming a gate insulating film is 3.9×109Ωcm. The value of this resistivity ρ is a value derived when the current density is 6.25×10−4 (A/cm2). By inclusion of the gate insulating film by a semi-insulating film having a resistivity ρ=3.9×109Ωcm, a withstand voltage of 1000 V can be obtained. Meanwhile, the withstand voltage abruptly drops as the resistivity of the gate insulating film exceeds 1 ×1011Ωcm, and the gate leak current increases when the resistivity of the gate insulating film drops below 1 ×107Ωcm. |
| US09660064B2 |
Low sheet resistance GaN channel on Si substrates using InAlN and AlGaN bi-layer capping stack
Transistors or transistor layers include an InAlN and AlGaN bi-layer capping stack on a 2DEG GaN channel, such as for GaN MOS structures on Si substrates. The GaN channel may be formed in a GaN buffer layer or stack, to compensate for the high crystal structure lattice size and coefficient of thermal expansion mismatch between GaN and Si. The bi-layer capping stack an upper InAlN layer on a lower AlGaN layer to induce charge polarization in the channel, compensate for poor composition uniformity (e.g., of Al), and compensate for rough surface morphology of the bottom surface of the InAlN material. It may lead to a sheet resistance between 250 and 350 ohms/sqr. It may also reduce bowing of the GaN on Si wafers during growth of the layer of InAlN material, and provide a AlGaN setback layer for etching the InAlN layer in the gate region. |
| US09660062B2 |
Bidirectional HEMT and an electronic package including the bidirectional HEMT
An electronic device can include a bidirectional HEMT. In an aspect, a packaged electronic device can include the bidirectional HEMT can be part of a die having a die substrate connection that is configured to be at a fixed voltage, electrically connected to drain/source or source/drain depending on current flow through the bidirectional HEMT, or electrically float. In another aspect, the electronic device can include Kelvin connections on both the drain/source and source/drain side of the circuit. In a further embodiment, a circuit can include the bidirectional HEMT, switch transistors, and diodes with breakdown voltages to limit voltage swings at the drain/source and source/drain of the switch transistors. |
| US09660061B2 |
Semiconductor device
A p-type well is formed in a semiconductor substrate, and an n+-type semiconductor region and a p+-type semiconductor region are formed in the p-type well to be spaced apart from each other. The n+-type semiconductor region is an emitter semiconductor region of a bipolar transistor, and the p-type well and the p+-type semiconductor region are base semiconductor regions of the bipolar transistor. An electrode is formed on an element isolation region between the n+-type semiconductor region and the p+-type semiconductor region, and at least a part of the electrode is buried in a trench which is formed in the element isolation region. The electrode is electrically connected to the n+-type semiconductor region. |
| US09660058B2 |
Method of FinFET formation
A method of fabricating a fin for a FinFET device includes providing a semiconductor substrate, forming a patterned silicon germanium layer on the semiconductor substrate, epitaxially growing a silicon layer on a top surface and sidewalls of the patterned silicon germanium layer, forming a sacrificial layer covering the patterned silicon germanium layer, and removing the sacrificial layer and a portion of the silicon layer disposed on the top surface of the patterned silicon germanium layer until a top surface of the sacrificial layer is co-planar with the top surface of the patterned silicon germanium layer. The method further includes removing the patterned silicon germanium layer and removing the sacrificial layer to form the fin. The epitaxially formed fin does not have the issues of line width roughness and edge roughness to improve the performance of the FinFET device. |
| US09660057B2 |
Method of forming a reduced resistance fin structure
Methods and structures for forming a reduced resistance region of a finFET are described. According to some aspects, a dummy gate and first gate spacer may be formed above a fin comprising a first semiconductor composition. At least a portion of source and drain regions of the fin may be removed, and a second semiconductor composition may be formed in the source and drain regions in contact with the first semiconductor composition. A second gate spacer may be formed covering the first gate spacer. The methods may be used to form finFETs having reduced resistance at source and drain junctions. |
| US09660054B2 |
Tunneling field effect transistor (TFET) with ultra shallow pockets formed by asymmetric ion implantation and method of making same
An embodiment integrated circuit device and a method of making the same. The embodiment integrated circuit includes a substrate supporting a source with a first doping type and a drain with a second doping type on opposing sides of a channel region in the substrate, and a pocket disposed in the channel region, the pocket having the second doping type and spaced apart from the drain between about 2 nm and about 15 nm. In an embodiment, the pocket has a depth of between about 1 nanometer to about 30 nanometers. |
| US09660053B2 |
High-voltage field-effect transistor having multiple implanted layers
A method for fabricating a high-voltage field-effect transistor includes forming a body region, a source region, and a drain region in a semiconductor substrate. The drain region is separated from the source region by the body region. Forming the drain region includes forming an oxide layer on a surface of the semiconductor substrate over the drain region and performing a plurality of ion implantation operations through the oxide layer while tilting the semiconductor substrate such that ion beams impinge on the oxide layer at an angle that is offset from perpendicular. The plurality of ion implantation operations form a corresponding plurality of separate implanted layers within the drain region. Each of the implanted layers is formed at a different depth within the drain region. |
| US09660048B2 |
High electron mobility transistors exhibiting dual depletion and methods of manufacturing the same
High electron mobility transistors (HEMT) exhibiting dual depletion and methods of manufacturing the same. The HEMT includes a source electrode, a gate electrode and a drain electrode disposed on a plurality of semiconductor layers having different polarities. A dual depletion region exists between the source electrode and the drain electrode. The plurality of semiconductor layers includes an upper material layer, an intermediate material layer and a lower material layer, and a polarity of the intermediate material layer is different from polarities of the upper material layer and the lower material layer. |
| US09660039B2 |
Display device
According to one embodiment, a thin-film transistor includes a semiconductor layer SC including a channel region, and a source region and a drain region on both sides of the channel region, a gate electrode GE, a first electrode SE connected to the source region via a first contact hole CH1, a second electrode DE connected to the drain region via a second contact hole CH2, a source line connected to the first electrode, and a drain line connected to the second electrode. A distance from the first and second contact holes to an end of the respective regions in a direction of a channel width is greater than or equal to 5 μm and less than or equal to 30 μm. The source line and the drain line extend in directions different from each other. |
| US09660038B2 |
Lateral/vertical semiconductor device
A lateral semiconductor device and/or design including a space-charge generating layer and an electrode or a set of electrodes located on an opposite side of a device channel as contacts to the device channel is provided. The space-charge generating layer is configured to form a space-charge region to at least partially deplete the device channel in response to an operating voltage being applied to the contacts to the device channel. |
| US09660036B2 |
Graphene layer, method of forming the same, device including graphene layer and method of manufacturing the device
A graphene layer, a method of forming the graphene layer, a device including the graphene layer, and a method of manufacturing the device are provided. The method of forming the graphene layer may include forming a first graphene at a first temperature using a first source gas and forming a second graphene at a second temperature using a second source gas. One of the first and second graphenes may be a P-type graphene, and the other one of the first and second graphenes may be an N-type graphene. The first graphene and the second graphene together form a P—N junction. |
| US09660029B2 |
Semiconductor device having a positive temperature coefficient structure
A semiconductor device includes a first load terminal at a first surface of a semiconductor body and a second load terminal at the opposing surface. An active device area is surrounded by an edge termination area. Load terminal contacts are absent in the edge termination area and are electrically connected to the semiconductor body in the active device area at the first surface. A positive temperature coefficient structure is between at least one of the first and second load terminals and a corresponding one of the first and second surfaces. Above a maximum operation temperature specified for the semiconductor device, a specific resistance of the positive temperature coefficient structure increases by at least two orders of magnitude within a temperature range of at most 50 K. A degree of area coverage of the positive temperature coefficient structure is greater in the edge termination area than in the active device area. |
| US09660026B1 |
Method of making a silicon nanowire device
There is provided an electronic device and a method for its manufacture. The device comprises an elongate silicon nanowire less than 0.5 μm in cross-sectional dimensions and having a hexagonal cross-sectional shape due to annealing-induced energy relaxation. The method, in examples, includes thinning the nanowire through iterative oxidation and etching of the oxidized portion. |
| US09660023B2 |
Semiconductor film with adhesion layer and method for forming the same
Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a semiconductor oxide, the semiconductor oxide including a compound of a semiconductor element and oxygen. A semiconductor film layer is over the adhesion layer, the semiconductor film layer being a material including the semiconductor element, the semiconductor film layer having a different composition than the adhesion layer. Bonds at an interface between the insulator layer and the adhesion layer comprise oxygen-hydrogen bonds and oxygen-semiconductor element bonds. |
| US09660020B2 |
Integrated circuits with laterally diffused metal oxide semiconductor structures and methods for fabricating the same
Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes a p-type semiconductor substrate, an n-type epitaxial layer disposed over and in contact with the p-type semiconductor substrate, and a p-type implant layer disposed within the n-type epitaxial layer, wherein the p-type implant layer is not in contact with the p-type semiconductor substrate. It further includes an n-type reduced surface field region disposed over and in contact with the p-type implant layer, a p-type body well disposed on a lateral side of the p-type implant layer and the n-type reduced surface field region, and a shallow trench isolation (STI) structure disposed within the n-type reduced surface field region. Still further, it includes a gate structure disposed partially over the p-type body well, partially over the n-type surface field region, and partially over the STI structure. |
| US09660015B2 |
Method for making semiconductor device with stacked analog components in back end of line (BEOL) regions
A method for making a semiconductor device may include forming a first dielectric layer above a semiconductor substrate, forming a first trench in the first dielectric layer, filling the first trench with electrically conductive material, removing upper portions of the electrically conductive material to define a lower conductive member with a recess thereabove, forming a filler dielectric material in the recess to define a second trench. The method may further include filling the second trench with electrically conductive material to define an upper conductive member, forming a second dielectric layer over the first dielectric layer and upper conductive member, forming a first via through the second dielectric layer and underlying filler dielectric material to the lower conductive member, and forming a second via through the second dielectric layer to the upper conductive member. |
| US09660013B2 |
Chip inductor
Disclosed herein is a chip inductor. The chip inductor according to the present invention includes a substrate on which a trough-hole is formed, a conductive coil that is formed on the substrate, an upper resin composite magnetic layer that is filled to surround the conductive coil so that a core is formed on a center portion of the substrate, a lower resin composite magnetic layer that is formed on a bottom portion of the substrate, and an external electrode that is formed on both sides of the upper and lower resin composite magnetic layers. |
| US09660009B2 |
Organic light emitting diode display
An organic light emitting diode display includes a scan line, a data line, and a driving voltage line connected to a pixel. The pixel includes a switching transistor connected to the scan line and the data line, a driving transistor connected to the switching transistor, and a compensation transistor to compensate a threshold voltage of the driving transistor. The pixel also includes a first data connector to connect the compensation transistor to the driving transistor, a first storage electrode corresponding to the driving gate electrode and connected to the driving voltage line, and a second storage electrode overlapping a first storage electrode. An extended portion of the second storage electrode is in an overlapped portion between the first data connector and the scan line. |
| US09660006B2 |
Method for manufacturing display device and method for manufacturing electronic device
A method for manufacturing a display device, which does not easily damage an electrode, is provided. In the first step, a terminal electrode, a wiring, and a functional layer are provided over a first substrate; the terminal electrode, the wiring, and the functional layer are electrically connected to one another; an insulating layer is provided over the terminal electrode; a first layer is provided over the terminal electrode and the insulating layer; an adhesive layer is sandwiched between the first substrate and a second substrate; the second substrate and the adhesive layer include a first opening overlapping with part of the first layer; and the insulating layer includes a second opening inside the first opening in a top view. In the second step, part of the first layer is removed by emitting particles having a high sublimation property to the first layer, so that the terminal electrode is exposed. |
| US09660000B2 |
Organic light emitting diode (OLED) array substrate and fabricating method thereof, display device
An OLED array substrate, comprising a plurality of pixel units, the pixel unit at least comprising a first sub-pixel, a second sub-pixel and a third sub-pixel, further comprising: a substrate, a TFT array and a pixel electrode formed on the substrate, and at least two organic luminescent material layers that display different colors formed on the pixel electrode, wherein the first sub-pixel comprises a first pixel electrode, the second sub-pixel comprises a second pixel electrode, the third sub-pixel comprises a third pixel electrode, an organic luminescent material layer of a first color covers the adjacent first pixel electrode and second pixel electrode in the pixel unit, an organic luminescent material layer of a second color covers the adjacent second pixel electrode and third pixel electrode in the pixel unit. |
| US09659998B1 |
Memory having an interlayer insulating structure with different thermal resistance
An integrated circuit memory comprises an intermediate layer disposed between a plurality of bit lines in a bit line conductor layer and a plurality of word lines in a word line conductor layer. The intermediate layer includes a plurality of memory posts through an interlayer insulating structure. Each memory post has a memory element and an access element. The interlayer insulating structure includes higher thermal resistance at the level of the memory element than at the level of the access element. |
| US09659993B2 |
Vertical integration of CMOS electronics with photonic devices
A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure. |
| US09659988B2 |
Image pickup apparatus
In an image pickup apparatus, during a period from a start of an accumulation period of electric carriers to an end of a reading period for a first photoelectric conversion unit and a second photoelectric conversion unit, the number of times an on-state voltage is supplied to a gate electrode of a first transfer transistor is larger than the number of times an on-state voltage is supplied to a gate electrode of a second transfer transistor. Additionally, among a plurality of pixels, in a pixel having a shortest distance from the gate electrode of the second transfer transistor to a contact plug, a distance from the gate electrode of the second transfer transistor to the contact plug is shorter than a distance from the gate electrode of the first transfer transistor to the contact plug. |
| US09659983B2 |
Semiconductor device and method for driving the same
An image sensor is provided which is capable of holding data for one frame period or longer and conducting a difference operation with a small number of elements. A photosensor is provided in each of a plurality of pixels arranged in a matrix, each pixel accumulates electric charge in a data holding portion for one frame period or longer, and an output of the photosensor changes in accordance with the electric charge accumulated in the data holding portion. As a writing switch element for the data holding portion, a transistor with small leakage current (sufficiently smaller than 1×10−14 A) is used. As an example of the transistor with small leakage current, there is a transistor having a channel formed in an oxide semiconductor layer. |
| US09659982B2 |
Image sensor pixel structure with optimized uniformity
An image sensor includes at least a first row and a second row of photodiodes, each photodiode being coupled with an associated transistor, each associated transistor including a gate, the first and second row of photodiodes forming a series of 2×2 Bayer-pattern units. In each Bayer-pattern unit, a first photodiode and a second photodiode in the first row are designated respectively as a first green pixel and a blue pixel, and a third photodiode and a fourth photodiode in the second row are designated respectively as a red pixel and a second green pixel, wherein a position of the gate of the transistor associated with the first photodiode relative to the first photodiode and a position of the gate of the transistor associated with the fourth photodiode relative to the fourth photodiode are the same. |
| US09659979B2 |
Sensors including complementary lateral bipolar junction transistors
An integrated radiation sensor for detecting the presence of an environmental material and/or condition includes a sensing structure and first and second lateral bipolar junction transistors (BJTs) having opposite polarities. The first lateral BJT has a base that is electrically coupled to the sensing structure and is configured to generate an output signal indicative of a change in stored charge in the sensing structure. The second lateral BJT is configured to amplify the output signal of the first bipolar junction transistor. The first and second lateral BJTs, the sensing structure, and the substrate on which they are formed comprise a monolithic structure. |
| US09659976B2 |
Electro-optic device and electronic equipment
Deterioration of display quality due to a difference of leak current in each pixel is suppressed.A pixel 30G includes a pixel capacitor 36 and a switching element 14 which controls supplying and blocking of voltage with respect to the pixel capacitor 36, and modulates irradiation light of a first wavelength (530 nm) according to the voltage of the pixel capacitor 36. A pixel 30R includes the pixel capacitor 36 and the switching element 14 that controls supplying and blocking of voltage with respect to the pixel capacitor 36, and modulates irradiation light of a second wavelength (620 nm) which is longer than the first wavelength according to the voltage of the pixel capacitor 36. A capacitance value of the pixel capacitor 36 of the pixel 30G is larger than a capacitance value of the pixel capacitor 36 of the pixel 30R. |
| US09659975B2 |
Fabrication methods of transparent conductive electrode and array substrate
Fabrication methods of a transparent conductive electrode (301) and an array substrate are provided. The fabrication method of the transparent conductive electrode (301) comprises: forming a sacrificial layer pattern (201) on a substrate (10) having a first region (A1) and a second region (A2) adjacent to each other, wherein the sacrificial layer pattern (201) is located in the second region (A2), and has an upper sharp corner profile formed on a side adjacent to the first region (A1); forming a transparent conductive thin-film (30) in the first region (A1) and the second region (A2) of the substrate (10) with the sacrificial layer pattern (201) formed thereon, wherein a thickness ratio of the transparent conductive thin-film (30) to the sacrificial layer pattern (201) is less than or equal to 1:1.5, and the transparent conductive thin-film (30) is disconnected at the upper sharp corner profile of the sacrificial layer pattern (201), such that at least a part of a side surface of the sacrificial layer pattern (201) facing the first region (A1) is exposed; and removing the sacrificial layer pattern (201) so as to reserve the transparent conductive thin-film (30) in the first region as the transparent conductive electrode (301). |
| US09659974B2 |
Pixel structure, manufacturing method of pixel structure, array substrate, and display panel
The disclosure provides a pixel structure, a manufacturing method of a pixel structure, an array substrate, a display panel, and a display device. The pixel structure includes a plurality of data lines and a plurality of scan lines, and a plurality of pixel units formed by intersecting the plurality of data lines with the plurality of scan lines. A pixel unit corresponds to one of the plurality of data lines and one of the plurality of scan lines. The pixel unit includes a pixel electrode and a TFT. The pixel electrode of the pixel unit in a row is electrically connected to a TFT of a pixel unit in a preceding adjacent row of the pixel electrode of the pixel unit. |
| US09659969B2 |
Display device
With an increase in the definition of a display device, the number of pixels is increased, and thus the numbers of gate lines and signal lines are increased. Due to the increase in the numbers of gate lines and signal lines, it is difficult to mount an IC chip having a driver circuit for driving the gate and signal lines by bonding or the like, which causes an increase in manufacturing costs. A pixel portion and a driver circuit for driving the pixel portion are formed over one substrate. At least a part of the driver circuit is formed using an inverted staggered thin film transistor in which an oxide semiconductor is used. The driver circuit as well as the pixel portion is provided over the same substrate, whereby manufacturing costs are reduced. |
| US09659968B2 |
Display device comprising a metal oxide semiconductor channel and a specified insulating layer arrangement
Variation in the electrical characteristics of transistors is minimized and reliability of the transistors is improved. A display device includes a pixel portion 104 and a driver circuit portion 106 outside the pixel portion. The pixel portion includes a pixel transistor, a first insulating layer 122 which covers the pixel transistor and includes an inorganic material, a second insulating layer 124 which is over the first insulating layer and includes an organic material, and a third insulating layer 128 which is over the second insulating layer and includes an inorganic material. The driver circuit portion includes a driving transistor for supplying a signal to the pixel transistor, and the first insulating layer covering the driving transistor. The second insulating layer is not formed in the driver circuit portion. |
| US09659967B2 |
Thin-film transistor and display device having the same
A thin-film transistor includes a substrate, a gate electrode formed over the substrate, a gate insulating layer formed over the gate electrode and the substrate, an oxide semiconductor layer formed over the gate insulating layer and comprising a source section and a drain section, a first electrode formed over the substrate and electrically connected to the source section, and a second electrode formed over the substrate and electrically connected to the drain section. The thin-film transistor further includes a first barrier layer disposed between the oxide semiconductor layer and the first electrode, a second barrier layer disposed between the first barrier layer and the first electrode, and the first electrode being electrically connected to the oxide semiconductor layer via the first barrier layer and the second barrier layer. |
| US09659961B2 |
Semiconductor structure with integrated passive structures
A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure. |
| US09659958B2 |
Three-dimensional semiconductor memory device
A semiconductor device includes lower and upper selection lines, a cell gate structure, a lower dummy structure and an upper dummy structure. The cell gate structure is between the lower and upper selection lines and includes cell gate electrodes stacked in a first direction. The lower dummy structure is between the lower selection line and the cell gate structure and includes a lower dummy gate line spaced from a lowermost one of the cell gate electrodes by a first distance. The upper dummy structure is between the upper selection line and the cell gate structure and includes an upper dummy gate line spaced from an uppermost one of the cell gate electrodes by a second distance. The cell gate electrodes are spaced by a third distance less than each of the first and second distances. |
| US09659956B1 |
Three-dimensional memory device containing source select gate electrodes with enhanced electrical isolation
A method of manufacturing a three-dimensional memory device includes forming, a bottom dielectric layer, a bottom sacrificial material layer, and an alternating stack of insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening, forming an epitaxial channel portion and a memory stack structure in the memory opening, forming a backside contact trench, forming a first backside recess by selectively removing the bottom sacrificial material layer, forming a semiconductor oxide layer underneath the bottom dielectric layer and around a material of the epitaxial channel portion, forming second backside recesses by selectively removing the spacer material layers, and forming electrically conductive layers in the first and second backside recesses. |
| US09659945B2 |
Semiconductor device
A first transistor including a channel formation region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode; a second transistor including an oxide semiconductor layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode; and a capacitor including one of the second source electrode and the second drain electrode, the second gate insulating layer, and an electrode provided to overlap with one of the second source electrode and the second drain electrode over the second gate insulating layer are provided. The first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other. |
| US09659943B1 |
Programmable integrated circuits and methods of forming the same
Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate having a central shallow trench isolation (STI) region. A pair of select transistors have drain regions in contact with opposite portions of the central STI region. A central gate structure overlies the central STI region and includes a central gate dielectric layer. The central gate dielectric layer has a medial dielectric region overlying the central STI region, a first lateral dielectric region overlying the first drain region, and a second lateral dielectric region overlying the second drain region. The first lateral dielectric region defines a first programmable element and the second lateral dielectric region defines a second programmable element. |
| US09659941B2 |
Integrated circuit structure with methods of electrically connecting same
Embodiments of the present disclosure provide an integrated circuit (IC) structure and methods of electrically connecting multiple IC structures. An IC structure according to embodiments of the present disclosure can include: a first conductive region; a second conductive region laterally separated from the first conductive region; a first vertically-oriented semiconductor fin formed over and contacting the first conductive region; a second vertically-oriented semiconductor fin formed over and contacting the second conductive region; and a first gate contacting each of the first vertically-oriented semiconductor fin and the second conductive region, wherein the first gate includes: a substantially horizontal section contacting the first vertically-oriented semiconductor fin, and a substantially vertical section contacting the second conductive region. |
| US09659940B2 |
Semiconductor device and method of manufacturing the same
A method of manufacturing a semiconductor device includes: preparing a wafer in which a first cell area and a second cell area are defined; forming a bottom electrode structure in the first cell area and a dummy structure located in the second cell area; and sequentially forming a dielectric layer and a top electrode on the bottom electrode structure and the dummy structure, wherein the bottom electrode structure includes a plurality of bottom electrodes extending in a first direction in the first cell area and first and second supporters to support the plurality of bottom electrodes, wherein the dummy structure includes a first mold film, a first supporter film, a second mold film, and a second supporter film that are sequentially formed to cover the second cell area, and the second supporter and the second supporter film are at a same level relative to the wafer. |
| US09659932B2 |
Semiconductor device having a plurality of fins and method for fabricating the same
A semiconductor device having a plurality of fins including at least one first fin and at least one second fin formed on a semiconductor substrate is provided. Each of the first fin and second fin has a first portion and a second portion. A gate electrode structure overlies the first portion of the plurality of fins. The gate electrode structure includes a gate electrode, and a gate dielectric layer between the gate electrode and the plurality of fins, A first electrode overlies the second portion of the plurality of fins and the first electrode is in electrical contact with the second portion of the plurality of fins. The gate electrode structure is in direct physical contact with the first portion of the first fin and the gate electrode structure is spaced apart from the first portion of the second fin. |
| US09659930B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view. |
| US09659923B2 |
Electrostatic discharge (ESD) protection circuits, integrated circuits, systems, and methods for forming the ESD protection circuits
An electrostatic discharge (ESD) protection circuit includes a field oxide device in a substrate, wherein the field oxide device is coupled between an input/output (I/O) pad and a first terminal. The field oxide device includes a drain end and a source end having a first type of dopant. The field oxide device includes a field oxide structure between the drain end and the source end. The field oxide structure has a top surface co-planar with a top surface of a substrate. A first doped region having a second type of dopant is adjacent to the drain end. A second doped region having the second type of dopant is adjacent to the source end. The field oxide structure is in a well and the source end and the drain end are separate from the well. The substrate has the second type of dopant and is around the field oxide structure. |
| US09659921B2 |
Power switch device
A power switch device includes a transistor and an ESD protection circuit. The transistor includes a source, a drain, and a gate, wherein a well region is disposed between the source and the drain. One end of the ESD protection circuit is coupled to the gate and another end thereof is coupled to the well region so as to form a protection circuit between the gate and the source and between the gate and the drain simultaneously. |
| US09659918B2 |
POP structures with dams encircling air gaps and methods for forming the same
A device includes a bottom package component that includes a bottom die, and a dam over a top surface of the bottom die. The dam has a plurality of sides forming a partial ring, with an air gap surrounded by the plurality of side portions. The air gap overlaps the bottom die. A top package component is bonded to the bottom package component, wherein the air gap separates a bottom surface of the top package component from the bottom die. |
| US09659916B2 |
Light emitting device package
A light emitting device package is provided. The light emitting device package may include a main body having a cavity including side surfaces and a bottom, and a first reflective cup and a second reflective cup provided in the bottom of the cavity of the main body and separated from each other. A first light emitting device may be provided in the first reflective cup, and a second light emitting device may be provided in the second reflective cup. |
| US09659913B2 |
LED module and LED module packaging structure
An LED module includes: a substrate including main, rear, and bottom surfaces; a first light emitting element disposed on the main surface; a conductive layer formed on the substrate and electrically coupled with the first light emitting element; a first conductive bonding layer interposed between the first light emitting element and the conductive layer; a main surface insulating film formed on the main surface and covering a portion of the conductive layer; and a first wire, wherein the main surface and the rear surface face opposite directions, the bottom surface connects long sides of the main and rear surfaces, the conductive layer includes a first wire bonding portion where the first wire is bonded, and the main surface insulating film includes a first insulating portion including a portion interposed between the first light emitting element and the first wire bonding portion when viewed in a thickness direction of the substrate. |
| US09659912B2 |
Low-inductance circuit arrangement comprising load current collecting conductor track
A circuit arrangement includes at least two semiconductor chip having first and second load terminals that are each connected to one another, a first load current collecting conductor track, and also an external terminal electrically conductively connected thereto. For each of the semiconductor chips there is at least one electrical connection conductor electrically conductively connected to the first load terminal of the relevant semiconductor chip and also to the first load current collecting conductor track. The total inductance of all the connection conductors with which the first load terminal of the second of the semiconductor chips is connected to the first load current collecting conductor track has at least twice the inductance of that section of the first load current collecting conductor track which is formed between the second connection location of the first of the semiconductor chips and the second connection location of the second of the semiconductor chips. |
| US09659911B1 |
Package structure and manufacturing method thereof
A package structure and a manufacturing method thereof are provided. The package structure includes a redistribution layer (RDL), at least one first die, a plurality of conductive terminals and solder balls, a first encapsulant, a plurality of second dies, and a second encapsulant. The RDL has a first surface and a second surface opposite to the first surface. The first die and the conductive terminals are electrically connected to the RDL and are located on the first surface of the RDL. The first encapsulant encapsulates the first die and the conductive terminals. The first encapsulant exposes part of the conductive terminals. The solder balls are electrically connected to the conductive terminals and are located over the conductive terminals exposed by the first encapsulant. The second dies are electrically connected to the RDL and are located on the second surface of the RDL. The second encapsulant encapsulates the second dies. |
| US09659908B1 |
Systems and methods for package on package through mold interconnects
Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package. |
| US09659905B2 |
Semiconductor package and semiconductor system including the same
A semiconductor package may include a first die, a second die disposed adjacent to the first die, and configured to share an address with the first die. The semiconductor package may include a first address pin included with the first die, and configured for receiving the address. The semiconductor package may include a second address pin included with the second die, and configured for receiving the address. The first die and the second die may output data corresponding to the address. Timings of the address in the first die and the second die may be aligned according to delay signals applied from a controller. |
| US09659902B2 |
Thermocompression bonding systems and methods of operating the same
A thermocompression bonding system for bonding semiconductor elements is provided. The thermocompression bonding system includes (1) a bond head assembly including a heater for heating an semiconductor element to be bonded, the bond head assembly including a fluid path configured to receive a cooling fluid; (2) a pressurized cooling fluid source; (3) a booster pump for receiving a pressurized cooling fluid from the pressurized cooling fluid source, and for increasing a pressure of the received pressurized cooling fluid; (4) a pressurized fluid reservoir for receiving pressurized cooling fluid from the booster pump; and (5) a control valve for controlling a supply of pressurized cooling fluid from the pressurized fluid reservoir to the fluid path. |
| US09659894B2 |
Chip mounting
A device comprising a chip including a substrate defining one or more electronic devices and a printed circuit board electrically connected to the chip via one or more solder elements sandwiched between the chip and the printed circuit board, and the solder elements, and buffer layers having a Young's Modulus of 2.5 GPa or less. |
| US09659893B2 |
Semiconductor package
The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A first conductive trace disposed on the substrate. A semiconductor die is disposed over the first conductive trace. A solder resist layer that extends across an edge of the semiconductor die is also included. Finally, a molding compound is provided that is formed over the substrate and covers the first conductive trace and the semiconductor die. |
| US09659892B2 |
Semiconductor device and method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes: arranging a solder material containing at least tin, between a semiconductor element and a joined member provided with a nickel layer and a copper layer, such that the solder material is in contact with the copper layer, the nickel layer being provided on a surface of the joined member, and the copper layer being provided on at least a portion of a surface of the nickel layer; and melting and solidifying the solder material to form Cu6Sn5 on the surface of the nickel layer using tin of the solder material and the copper layer. |
| US09659887B2 |
Semiconductor device
A semiconductor device includes a pad group including pads provided on a semiconductor substrate and arranged in a row to form a pad row as a whole. The pad group includes at least one first pad provided with a first via-connection part electrically connected therewith and extending in a first direction perpendicular to a row direction of the pad row, and at least one second pad provided with a second via-connection part electrically connected therewith and extending in a second direction opposite to the first direction. The at least one second pad is formed at a position moved in the first direction from the row direction of the pad row passing through a center of the at least one first pad. |
| US09659885B2 |
Semiconductor device with pre-molding chip bonding
This disclosure relates generally to a semiconductor device and method of making the semiconductor device by pressing an electrical contact of a chip into a bonding layer on a carrier. The bonding layer is cured and coupled, at least in part, to the electrical contact. A molding layer is applied in contact with the chip and a first major surface of the bonding layer. Distribution circuitry is coupled to the electrical contact. |
| US09659879B1 |
Semiconductor device having a guard ring
A semiconductor device includes a semiconductor die having a guard ring disposed in a periphery of the semiconductor die. The semiconductor device also includes a conductive pad over the guard ring. the semiconductor device further has a passivation partially covering the conductive pad, and including a recess to expose a portion of the conductive pad and a post passivation interconnect (PPI) over the passivation. In the semiconductor device, a conductor is extended upwardly from the recess and connected to a portion of the PPI. |
| US09659878B2 |
Wafer level shielding in multi-stacked fan out packages and methods of forming same
An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die. |
| US09659876B1 |
Wafer-scale marking systems and related methods
A method of wafer-scale marking includes coupling a first marking mask over a semiconductor wafer having unsingulated semiconductor devices thereon. The first marking mask has a plurality of first stencils therethrough and a surface of the wafer is plasma etched through the first stencils to form first markings in the surface. A second marking mask is coupled over the surface and includes a plurality of second stencils therethrough. The surface is plasma etched through the second stencils to form second markings in the surface. In implementations the first marking mask and second marking mask are simultaneously coupled over the surface and the first markings and second markings are simultaneously formed. In implementations a plurality of first windows of the first marking mask are aligned with the plurality of second stencils while a plurality of second windows of the second marking mask are aligned with the plurality of first stencils. |
| US09659871B2 |
Semiconductor device
Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction. |
| US09659868B2 |
Semiconductor apparatus
A semiconductor apparatus has a configuration in which multiple copper wiring layers and multiple insulating layers are alternately layered. A low-impedance wiring is formed occupying a predetermined region. A first wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a first copper wiring layer, each of which has a rectangular shape extending in a first direction. A second wiring pattern includes multiple copper wiring members arranged in parallel with predetermined intervals in a second copper wiring layer adjacent to the first copper wiring layer, each of which has a rectangular shape extending in a second direction orthogonal to the first direction. The region occupied by the first wiring pattern and that occupied by the second wiring pattern are arranged such that they at least overlap. The first wiring pattern and the second wiring pattern are electrically connected so as to have the same electric potential. |
| US09659867B2 |
Semiconductor device and manufacturing method thereof
The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed. |
| US09659864B2 |
Method and apparatus for forming self-aligned via with selectively deposited etching stop layer
A layer of an interconnect structure is formed over a substrate. The layer contains an interlayer dielectric (ILD) material and a metal line disposed in the ILD. A first etching stop layer is formed on the ILD but not on the metal line. The first etching stop layer is formed through a selective atomic layer deposition (ALD) process. A second etching stop layer is formed over the first etching stop layer. A high etching selectivity exists between the first and second etching stop layers. A via is formed to be at least partially aligned with, and electrically coupled to, the metal line. The first etching stop layer prevents the ILD from being etched through during the formation of the via. |
| US09659863B2 |
Semiconductor devices, multi-die packages, and methods of manufacture thereof
Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars. |
| US09659862B1 |
Method, apparatus, and system for e-fuse in advanced CMOS technologies
Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an e-fuse comprising a first region comprising a conductive oxide of a first metal; and a second region comprising a second metal, wherein an oxide of the second metal is resistive; wherein the e-fuse is electrically connected to both the first conductive element and the second conductive element. |
| US09659861B2 |
Semiconductor device and fabrication method thereof
A semiconductor device includes a lower wiring layer made of a conductive material; an upper wiring layer formed in an upper layer than the lower wiring layer; and a fuse film, at least a portion of the fuse film being formed in a plug formation layer in which a plug for connecting the lower wiring layer and the upper wiring layer is formed, and made of a conductive material including a metallic material other than copper. |
| US09659857B2 |
Semiconductor structure and method making the same
The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer. |
| US09659855B2 |
Cavity package with pre-molded substrate
A cavity package is set forth along with a method of manufacturing thereof. The method comprises applying a selective plating resist to a metallic substrate in a pattern to expose portions for a ring, tie bars, die attach pad and input/output wire bonding pads; elective depositing of metal plating using the selective plating resist; removing the selective metal plating resist; applying a selective etching resist to the substrate; selectively etching portions of the substrate not covered by the selective etching resist; stripping away the selective etching resist; pre-molding a leadframe to the substrate so as to surround the die attach pad portion; etching the tie bars away from the bottom surface of the substrate; attaching a semiconductor device die to the die attach pad; wire bonding the semiconductor device to the input/output wire bonding pads; and attaching a cap to the ring portion of the substrate and the die attach pad to protect the wire bonded semiconductor device die and permit electrical grounding. |
| US09659841B2 |
Semiconductor device and method of producing semiconductor device
A method of producing a semiconductor device, comprising the steps of forming a through hole in a semiconductor substrate having a first main surface, a second main surface opposite to the first main surface, and a first conductive layer disposed on the second main surface so that the through hole passes through the semiconductor substrate from the first main surface to the second main surface; forming an insulation film to extend from a bottom portion of the through hole to the first main surface through a side surface of the through hole; coating an organic member on the insulation film on the side surface of the through hole and the first main surface; removing an air bubble in the organic member and between the organic member and the insulation film; and forming a first opening portion in the organic member. |
| US09659839B2 |
Barrier structures between external electrical connectors
A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad. |
| US09659837B2 |
Direct bonded copper semiconductor packages and related methods
A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package. |
| US09659835B1 |
Techniques for integrating thermal via structures in integrated circuits
A technique for designing an integrated circuit includes placing standard cells across a first surface of a substrate of an integrated circuit (IC) design. At least two unoccupied regions are located across the first surface that do not include standard cells. Aspect ratios for one or more micro fill vias that can be placed in the at least two unoccupied regions are determined. The one or more micro fill vias are placed in the at least two unoccupied regions. Finally, one or more partial thermal vias are placed from a second surface of the integrated circuit, opposite the first surface, to thermally couple the one or more partial thermal vias to the one or more micro fill vias to create thermal paths from the first surface to the second surface. |
| US09659829B1 |
Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS
A method of CMOS construction may include stacked III-V nanowires and stacked Ge nanowires. The CMOS construction may include a hybrid orientation with surface SOI and a standard substrate. |
| US09659828B2 |
Semiconductor device with metal gate and high-k dielectric layer, CMOS integrated circuit, and method for fabricating the same
A semiconductor device includes a gate dielectric layer over a substrate, a metal layer over the gate dielectric layer, a capping layer over the metal layer, wherein the capping layer includes a plurality of dipole forming elements concentrated at the interface between the metal layer and the capping layer. |
| US09659825B2 |
Method of CMOS manufacturing utilizing multi-layer epitaxial hardmask films for improved epi profile
An integrated circuit containing PMOS transistors may be formed by forming a dual layer hard mask. A first layer of the hard mask is halogen-containing silicon nitride formed using a halogenated silane reagent. A second layer of the hard mask is silicon nitride formed on the first layer using halogen-free reagents. After source/drain cavities are etched in the PMOS transistors, a pre-epitaxial bake with hydrogen is performed. After SiGe epitaxial source/drain regions are formed, the hard mask is removed. |
| US09659824B2 |
Graphoepitaxy directed self-assembly process for semiconductor fin formation
Guiding pattern portions are formed on a surface of a lithographic material stack that is disposed on a surface of a semiconductor substrate. A copolymer layer is then formed between each neighboring pair of guiding pattern portions and thereafter a directed self-assembly process is performed that causes phase separation of the various polymeric domains of the copolymer layer. Each guiding pattern portion is selectively removed, followed by the removal of each first phase separated polymeric domain. Each second phase separated polymeric domain remains and is used as an etch mask in forming semiconductor fins in an upper semiconductor material portion of the semiconductor substrate. |
| US09659822B2 |
Providing a chip die with electrically conductive elements
A method for providing position control information for controlling an impingement position of a laser beam for treatment of a chip die in a chip manufacturing process, comprises the steps of a) receiving a specification of positions (x,y) of a electrically conductive elements in the chip die, the positions having a first coordinate along a first direction (x) and a second coordinate (y) along a second direction in a plane defined by the chip die, said first and second direction being mutually transverse to each other, b) selecting a cluster of positions that is within a predetermined two-dimensional spatial range, wherein each pair of positions in the cluster at least has a first minimum difference in their first coordinates or a second minimum difference in their second coordinates and removing the next position from the ordered set, c) update the positions of the set of positions in accordance with an expected time needed to carry out the treatment for said cluster and a speed of a wafer comprising the chip die, d) repeating steps b-d until each of the positions in said set is assigned to a cluster. |
| US09659821B1 |
Method of forming interconnect structures by self-aligned approach
A method includes forming a dielectric layer over a conductive feature. A first mask having a first opening is formed over the dielectric layer. A second mask is formed over the first mask. A third mask having a second opening is formed over the second mask. A fourth mask having a third opening is formed over the third mask, a portion of the third opening overlapping with the second opening. The portion of the third opening is transferred to the second mask to form a fourth opening, a portion of the fourth opening overlapping with the first opening. The portion of the fourth opening is transferred to the dielectric layer to form a fifth opening. The fifth opening is extended into the dielectric layer to form an extended fifth opening, the extended fifth opening exposing the conductive feature. The extended fifth opening is filled with a conductive material. |
| US09659820B2 |
Interconnect structure having large self-aligned vias
A method of forming a wavy line interconnect structure that accommodates small metal lines and enlarged diameter vias is disclosed. The enlarged diameter vias can be formed using a self-aligned dual damascene process without the need for a separate via lithography mask. The enlarged diameter vias make direct contact with at least three sides of the underlying metal lines, and can be aligned asymmetrically with respect to the metal line to increase the packing density of the metal pattern. The resulting vias have an aspect ratio that is relatively easy to fill, while the larger via footprint provides low via resistance. By allowing the via footprint to exceed the minimum size of the metal line width, a path is cleared for further process generations to continue shrinking metal lines to dimensions below 10 nm. |
| US09659812B2 |
Microelectronic elements with post-assembly planarization
A microelectronic unit can include a carrier structure having a front surface, a rear surface remote from the front surface, and a recess having an opening at the front surface and an inner surface located below the front surface of the carrier structure. The microelectronic unit can also include a microelectronic element having a top surface adjacent the inner surface, a bottom surface remote from the top surface, and a plurality of contacts at the top surface. The microelectronic unit can also include terminals electrically connected with the contacts of the microelectronic element. The terminals can be electrically insulated from the carrier structure. The microelectronic unit can also include a dielectric region contacting at least the bottom surface of the microelectronic element. The dielectric region can define a planar surface located coplanar with or above the front surface of the carrier structure. |
| US09659810B2 |
Method of making a FinFET device
The present disclosure provides many different embodiments of fabricating a FinFET device that provide one or more improvements over the prior art. In one embodiment, a method of fabricating a FinFET includes providing a semiconductor substrate and a plurality of dummy fins and active fins on the semiconductor substrate. A predetermined group of dummy fins is removed. |
| US09659808B2 |
Semiconductor-element manufacturing method and wafer mounting device using a vacuum end-effector
According to the present invention, a semiconductor-element manufacturing method including the steps of cutting out a ring portion of a wafer with laser light to form a flat wafer, the ring portion being formed on a periphery of the wafer and thicker than a central portion of the wafer, the wafer having a first surface and a second surface opposite to the first surface, with the first surface of the wafer being held on a vacuum stage by suction, attaching the first surface to dicing tape after detaching the flat wafer from the vacuum stage with the second surface of the flat wafer being held by a vacuum end-effector by suction, and dicing the flat wafer attached to the dicing tape. |
| US09659806B2 |
Semiconductor package having conductive pillars
A semiconductor package and a method for fabricating the semiconductor package are provided. The semiconductor package includes a base layer, a plurality of conductive pillars, a semiconductor element, and an encapsulation. The base layer has opposing first and second surfaces and a receiving part. The conductive pillars are formed on the second surface. Each of the conductive pillars has first and second terminals, and the second terminal is distant from the second surface of the base layer. The semiconductor element is received in the receiving part, and has opposing active and passive surfaces, and the active surface is exposed from the first surface. The encapsulation is formed on the second surface, encapsulates the conductive pillars and the semiconductor element, and has opposing third and fourth surfaces, and the second terminals of the conductive pillars are exposed from the fourth surface. The semiconductor package is provided with the conductive pillars having fine pitches. |
| US09659805B2 |
Fan-out interconnect structure and methods forming the same
A method includes forming an adhesive layer over a carrier, forming a sacrificial layer over the adhesive layer, forming through-vias over the sacrificial layer, and placing a device die over the sacrificial layer. The Method further includes molding and planarizing the device die and the through-vias, de-bonding the carrier by removing the adhesive layer, and removing the sacrificial layer. |
| US09659803B2 |
Electrostatic chuck with concentric cooling base
Embodiments of the present disclosure generally provide apparatus and method for cooling a substrate support in a uniform manner. One embodiment of the present disclosure provides a cooling assembly for a substrate support. The cooling assembly includes a cooling base having a first side for contacting the substrate support and providing cooling to the substrate support, a diffuser disposed on a second side of the cooling base, wherein the diffuser defines a plurality of cooling paths for delivering a cooling fluid towards the cooling base in a parallel manner, and an inlet/outlet plate disposed under the diffuser, wherein the inlet/outlet plate is provides an interface between the diffuser and an inlet and outlet of a cooling fluid. |
| US09659801B2 |
High efficiency buffer stocker
A high-efficiency buffer stocker is disclosed. The buffer stocker includes an overhead transport track for supporting overhead transport vehicles carrying wafer containers and at least one conveyor system or conveyor belt provided beneath the overhead transport track for receiving the wafer containers from the overhead transport vehicles on the overhead transport track. The buffer stocker is capable of absorbing the excessive flow of wafer containers between a processing tool and a stocker, for example, to facilitate the orderly and efficient flow of wafers between sequential process tools in a semiconductor fabrication facility, for example. |
| US09659799B2 |
Systems and methods for dynamic semiconductor process scheduling
Embodiments of the present disclosure can help increase throughput and reduce resource conflicts and delays in semiconductor processing tools. An exemplary method according to various aspects of the present disclosure includes analyzing, by a computer program operating on a computer system, a plurality of expected times to complete each of a respective plurality of actions to be performed by a semiconductor processing tool, the semiconductor processing tool including a first process module and a second process module. |
| US09659796B2 |
Rinsing wafers using composition-tunable rinse water in chemical mechanical polish
An apparatus for manufacturing integrated circuits on a wafer includes a polish pad; a rinse arm movable over the polish pad; and a post-polish cleaner. The post-polish cleaner includes a brush for brushing the wafer; and a nozzle aiming at the wafer. The apparatus further includes a mixer configured to mix an additive and de-ionized water; and a pipe connecting the mixer to at least one of the rinse arm and the nozzle. |
| US09659788B2 |
Nitrogen-containing compounds for etching semiconductor structures
A method for etching silicon-containing films is disclosed. The method includes the steps of introducing a vapor of a nitrogen containing etching compound into a reaction chamber containing a silicon-containing film on a substrate, wherein the nitrogen containing etching compound is an organofluorine compound containing at least one C≡N or C═N functional group; introducing an inert gas into the reaction chamber; and activating a plasma to produce an activated nitrogen containing etching compound capable of etching the silicon-containing film from the substrate. |
| US09659785B2 |
Fin cut for taper device
A method of making a semiconductor device includes patterning a fin in a substrate; performing a first etching process to remove a portion of the fin to cut the fin into a first cut fin and a second cut fin, the first cut fin having a first fin end and a second fin end and the second cut fin having a first fin end and a second fin end; forming an oxide layer along an endwall of the first fin end and an endwall of the second fin end of the first cut fin, and an endwall of the first fin end and an endwall of the second fin end of the second cut fin; disposing a liner onto the oxide layer disposed onto the endwall of the first fin end of the first cut fin to form a bilayer liner; and performing a second etching process to remove a portion of the second cut fin. |
| US09659783B2 |
High aspect ratio etch with combination mask
A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask. |
| US09659779B2 |
Method and structure for enabling high aspect ratio sacrificial gates
Sacrificial gate structures having an aspect ratio of greater than 5:1 are formed on a substrate. In some embodiments, each sacrificial gate structure straddles a portion of a semiconductor fin that is present on the substrate. An anchoring element is formed orthogonal to each sacrificial gate structure rendering the sacrificial gate structures mechanically stable. After formation of a planarization dielectric layer, each anchoring element can be removed and thereafter each sacrificial gate structure can be replaced with a functional gate structure. |
| US09659777B2 |
Process for stabilizing a bonding interface, located within a structure which comprises an oxide layer and structure obtained
The invention relates to a process for stabilizing a bonding interface, located within a structure for applications in the fields of electronics, optics and/or optoelectronics and that comprises an oxide layer buried between an active layer and a receiver substrate, the bonding interface having been obtained by molecular adhesion. In accordance with the invention, the process further comprises irradiating this structure with a light energy flux provided by a laser, so that the flux, directed toward the structure, is absorbed by the energy conversion layer and converted to heat in this layer, and in that this heat diffuses into the structure toward the bonding interface, so as to thus stabilize the bonding interface. |
| US09659775B2 |
Method for doping impurities, method for manufacturing semiconductor device
Impurity elements are doped at a high concentration exceeding a thermodynamic equilibrium concentration into a solid material having an extremely small diffusion coefficient of the impurity element. A method for doping impurities includes steps for depositing source film made of material containing impurity elements with a film thickness on a surface of a solid target object (semiconductor substrate) made from the solid material. The film thickness is determined in consideration of irradiation time per light pulse and the energy density of the light pulse. The method also includes a step for irradiating the source film by the light pulse with the irradiation time and the energy density so as to dope the impurity elements into the target object at a concentration exceeding a thermodynamic equilibrium concentration. |
| US09659773B2 |
Method for manufacturing silicon carbide semiconductor device by selectively removing silicon from silicon carbide substrate to form protective carbon layer on silicon carbide substrate for activating dopants
A method for manufacturing a SiC semiconductor device includes the steps of: forming an impurity region in a SiC layer; forming a first carbon layer on a surface of the SiC layer having the impurity region formed therein, by selectively removing silicon from the surface; forming a second carbon layer on the first carbon layer; and heating the SiC layer having the first carbon layer and the second carbon layer formed therein. |
| US09659767B2 |
Substrate processing apparatus and method of manufacturing semiconductor device
Generation of adhered materials in a space over a gas guide of a shower head is inhibited. A substrate processing apparatus includes a process chamber; a buffer chamber including a dispersion unit; a process gas supply hole installed in a ceiling portion of the buffer chamber; an inert gas supply hole installed in the ceiling portion; a gas guide disposed in a gap between the dispersion unit and the ceiling portion, the gas guide including a base end portion disposed at a side of the process gas supply hole, a leading end portion disposed closer to the inert gas supply hole than to the process gas supply hole, and a plate portion connecting the base end portion and the leading end portion; a process chamber exhaust unit; and a control unit. |
| US09659766B2 |
Method for forming semiconductor structure with etched fin structure
Methods for forming semiconductor structures are provided. The method includes forming a first fin structure and a second fin structure over a substrate and forming a first sidewall layer to cover the first fin structure and the second fin structure over the substrate. The method for manufacturing a semiconductor structure further includes forming a second sidewall layer over the first sidewall layer and etching a top portion of the first fin structure and the first sidewall layer and the second sidewall layer formed over the top portion of the first fin structure to expose a portion of the first fin structure. The method for manufacturing a semiconductor structure further includes oxidizing the exposed portion of the first fin structure to transform the exposed portion of the first fin structure into an oxide structure formed over the first fin structure. |
| US09659757B2 |
Measuring and controlling wafer potential in pulsed RF bias processing
Apparatus and methods are provided for monitoring a pulsed RF bias signal applied to a chuck in a processing chamber. One method includes operations for detecting voltage values of individual pulses of the pulsed RF bias voltage, and for determining the time for sampling the value of each individual detected pulse. At the sampling time for each pulse, a particular voltage value of the respective individual detected pulse is sampled and the particular voltage value is held. Each particular voltage value represents a characteristic peak-to-peak voltage value of each individual detected pulse. A feedback signal representing the characteristic peak-to-peak voltage value for a voltage envelope of one of the individual detected pulses is generated, and the voltage of the pulsed RF bias voltage signal applied to the chuck is adjusted according to a difference between the feedback signal and a desired voltage value of the pulsed RF bias voltage signal. |
| US09659755B2 |
Plasma generator and thermal electron emitter
A plasma generator includes: an arc chamber having a plasma generation region in which plasma is generated in the inside thereof; a magnetic field generator configured to apply a magnetic field to the plasma generation region; and a cathode configured to extend in an axial direction along an applying direction of the magnetic field applied to the plasma generation region and provided with a cathode cap that emits thermal electrons at a front end thereof. The cathode cap protrudes toward the inside of the arc chamber in the axial direction and has a shape of which a width in the radial direction perpendicular to the axial direction becomes smaller toward the inside of the arc chamber. |
| US09659754B2 |
Plasma processing apparatus and plasma processing method
The present disclosure provides a plasma processing apparatus, including: a processing chamber; an oscillator configured to output high-frequency power; a power supply unit configured to supply the high-frequency power from a specific plasma generating location into the processing chamber; a magnetic field forming unit provided outside the processing chamber and configured to forming a magnetic field at least at the specific plasma generating location; and a control unit configured to control the magnetic field formed by the magnetic field forming unit such that a relationship between an electron collision frequency fe of plasma generated in the processing chamber and a cyclotron frequency fc is fc>fe. |
| US09659753B2 |
Grooved insulator to reduce leakage current
A plasma source includes a first electrode and a second electrode having respective surfaces, and an insulator that is between and in contact with the electrodes. The electrode surfaces and the insulator surface substantially define a plasma cavity. The insulator surface defines one or more grooves configured to prevent deposition of material in a contiguous form on the insulator surface. A method of generating a plasma includes introducing one or more gases into a plasma cavity defined by a first electrode, a surface of an insulator that is in contact with the first electrode, and a second electrode that faces the first electrode. The insulator surface defines one or more grooves where portions of the insulator surface are not exposed to a central region of the cavity. The method further includes providing RF energy across the first and second electrodes to generate the plasma within the cavity. |
| US09659752B2 |
Method for presetting tuner of plasma processing apparatus and plasma processing apparatus
Disclosed is a method for presetting a tuner that matches a power required for plasma emission in a plasma processing apparatus. The method includes: obtaining a relationship of a time lapse from power supply, an emission intensity of plasma, and a setting position of the tuner by emitting plasma; differentiating the emission intensity by time to calculate a time when an increase rate of the emission intensity becomes maximum; and setting the setting position of the tuner at a time, which is obtained by subtracting a time required from the setting of the tuner until the setting is reflected on the emission intensity from the time when the increase rate of the emission intensity becomes maximum, as a preset position. |
| US09659751B2 |
System and method for selective coil excitation in inductively coupled plasma processing reactors
Spatial distribution of RF power delivered to plasma in a processing chamber is controlled using an arrangement of primary and secondary inductors, wherein the current through the secondary inductors affects the spatial distribution of the plasma. The secondary inductors are configured to resonate at respectively different frequencies. A first secondary inductor is selectively excited to resonance, during a first time period within a duty cycle, by delivering power to a primary inductor at the resonant frequency of the first secondary inductor. A second secondary inductor is selectively excited to resonance, during a second time period within a duty cycle, by delivering power to a primary inductor at the resonant frequency of the second secondary inductor. The secondary inductors are isolated from one another and terminated such that substantially all current that passes through them and into the plasma results from mutual inductance with a primary inductor. |
| US09659749B2 |
Beam extraction slit structure and ion source
A beam extraction slit structure includes a plasma chamber interior surface that is, in operation, in contact with a plasma; a plasma chamber exterior surface that faces an extraction electrode; and a slit surface part that forms a beam extraction slit between the plasma chamber interior surface and the plasma chamber exterior surface in the beam extraction direction. The slit surface part includes a plasma meniscus fixing part formed in an area of relatively higher plasma density in the slit longitudinal direction to fixingly maintain a plasma meniscus of the plasma and a plasma meniscus non-fixing part formed in an area of relatively lower plasma density in the slit longitudinal direction to movably maintain the plasma meniscus of the plasma in the beam extraction direction. |
| US09659745B2 |
Charged particle beam drawing apparatus, information processing apparatus and pattern inspection apparatus
A charged particle beam drawing apparatus of an embodiment includes: a graphic information file for storing graphic information for each of elements (for example, patterns) at a level underlying an element (for example, a cell) at a particular level in hierarchically-structured drawing data which has elements at each level; and an attribute information file for storing attribute information to be given to each of the elements at the underlying level in association with information (for example, an index number) on the element at the particular level. |
| US09659743B2 |
Image creating method and imaging system for performing the same
A spatial image having 2D spatial information is obtained from a surface of a sample by an image creating method. The surface of the sample is milled to obtain an elemental image having material information from the milled surface. The spatial image and the elemental image are composed to form a 2D spatial/elemental image. |
| US09659740B2 |
Radiation generator adjusting beam focusing based upon a diagnostic electrode
A radiation generator is provided that includes a target, a cathode to emit electrons in a downstream direction toward the target, a first conductive member downstream of the cathode, and a second conductive member downstream of the cathode. The first and second conductive members have a potential difference with the cathode such that a resultant electric field accelerates the electrons toward the target. A diagnostic current in the second conductive member and a target current in the target may be measured, and an electrical property of the first conductive member may be adjusted based upon the diagnostic current and the target current. |
| US09659736B2 |
Particle beam isotope generator apparatus, system and method
An isotope generation apparatus is disclosed including: an ion beam source of any of the types described herein; an extractor for extracting the ion beam from the confinement region, where the beam includes a portion of multiply ionized ions in a selected final ionization state; a target including a target material; and an accelerator for accelerating the ion beam and directing the ion beam to the target. The ion beam directed to the target transmutes at least a portion of the target material to a radio-isotope in response to a nuclear reaction between ions in the selected final ion state and atoms of the target material. |
| US09659735B2 |
Applications of graphene grids in vacuum electronics
Graphene grids are configured for applications in vacuum electronic devices. A multilayer graphene grid is configured as a filter for electrons in a specific energy range, in a field emission device or other vacuum electronic device. A graphene grid can be deformable responsive to an input to vary electric fields proximate to the grid. A mesh can be configured to support a graphene grid. |
| US09659733B2 |
Method for preparing a molybdenum disulfide film used in a field emission device
Method for preparing a molybdenum disulfide film used in a field emission device, including: providing a sulfur vapor; blowing the sulfur vapor into a reaction chamber having a substrate and MoO3 powder to generate a gaseous MoOx; feeding the sulfur vapor into the reaction chamber sequentially, heating the reaction chamber to a predetermined reaction temperature and maintaining for a predetermined reaction time, and then cooling the reaction chamber to a room temperature and maintaining for a second reaction time to form a molybdenum disulfide film on the surface of the substrate, in which the molybdenum disulfide film grows horizontally and then grows vertically. The method according to the present disclosure is simple and easy, and the field emission property of the MoS2 film obtained is good. |
| US09659729B2 |
Electrical switch
An electrical switch includes a gas-insulated tube, a contact system in the tube having fixed and movable contacts, a contact operating element passed out of the tube and movable along an actuation direction for opening and closing the system, and a contact pressure spring movable along the direction, connected to the operating element and an external drive element and disposed in a stationary guide part. The guide part guides the operating element. If the drive element shifts along the direction toward the fixed contact, the spring, operating element and movable contact move toward the fixed contact, closing the system and compressing the spring providing contact pressure force. The spring is in a housing connected to the operating element and movable relative to the guide part. A guide element is attached outside the housing, bears against the guide part, guides the housing and guides the operating element along the direction. |
| US09659728B2 |
Solid-dielectric switch including a molded viewing window
A solid-dielectric switch includes a visible disconnect assembly having an open state and a closed state. A molded housing at least partially encases the visible disconnect assembly. At least a portion of the molded housing forms a molded one-piece wall having an inner surface and an outer surface. An aperture in the molded one-piece wall extends between the inner surface and the outer surface of the wall. A viewing window is disposed in the aperture and molded into the molded wall. The viewing window includes a lens, wherein the viewing window has an outer edge that is embedded within the molded one-piece wall with the outer edge extending into the molded one-piece wall between the inner surface and the outer surface of the molded one-piece wall. |
| US09659721B1 |
Circuit breakers with integrated safety, control, monitoring, and protection features
Methods, systems, and apparatus for circuit breakers with integrated safety, control, monitoring, and protection features. In one aspect, a circuit breaker includes, an input and an output, a switch coupled between the input and the output, a sensor configured to measure the current flowing from the input to the output, and a control system coupled to the sensor and the switch, wherein the control system is configured to perform operations including comparing a rate of change of the current measured by the sensor to a threshold rate of change of current, determining that the rate of change of the current measured by the sensor exceeds the threshold rate of change of current for at least a predetermined period of time, and as a consequence of determining that the rate of change of current exceeds the threshold rate of change, opening the switch, thereby disconnecting the input from the output. |
| US09659717B2 |
MEMS device with constant capacitance
A MEMS apparatus has a substrate, an input node, an output node, and a MEMS switch between the input node and the output node. The switch selectively connects the input node and the output node, which are electrically isolated when the switch is open. The apparatus also has an input doped region in the substrate and an output doped region in the substrate. The input doped region and output doped region are electrically isolated through the substrate—i.e., the resistance between them inhibits non-negligible current flows between the two doped regions. The input doped region forms an input capacitance with the input node, while the output doped region forms an output capacitance with the output node. |
| US09659709B2 |
Common mode filter and manufacturing method thereof
A common mode filter and a manufacturing method thereof are disclosed. A common mode filter in accordance with an aspect of the present invention includes: a substrate: a filter layer disposed on the substrate and configured to remove a signal noise; an electrode column formed to be bent along a perimetric portion of the filter layer and electrically connected with the filter layer; an electrode pad formed to have a larger longitudinal cross-sectional area than the electrode column and integrally coupled on the electrode column; and a magnetic layer formed on a layer on which the electrode column and the electrode pad are formed. |
| US09659708B2 |
Method for manufacturing an inductor
A method for manufacturing an inductor including preparing an insulating layer; forming a polymer layer including a coil pattern on the insulating layer; forming a stacked structure by heat treating the insulating layer and the polymer layer; and forming an external electrode to electrically connect the coil pattern for the stacked structure. |
| US09659701B2 |
Common mode filter
A common mode filter includes first and second wires wound around a winding core portion by the same number of turns. Each of the first and second wires is wound by a number m1 of turns in a first winding area and wound by a number m2 of turns in a second winding area. A distance D1 between an n1th turn (1≦n1≦m1−1) of the second wire and an n1+1th turn of the first wire is shorter than a distance D2 between an n1th turn of the first wire and an n1+1th turn of the second wire in the winding area. A distance D3 between an n2th (m1+1≦n2≦m1+m2−1) turn of the first wire and an n2+1th turn of the second wire is shorter than a distance D4 between an n2th turn of the second wire and an n2+1th turn of the first wire in the winding area. |
| US09659700B2 |
Neutralizing external magnetic forces on an OIS module
A device is disclosed, comprising a camera comprising an optical image stabilization module, at least one magnetic component, at least one ferromagnetic component, wherein the at least one ferromagnetic component is disposed at a position so as to develop a magnetic force between the optical image stabilization module of the camera and the ferromagnetic component which acts in a direction opposite to a magnetic force exerted on the optical image stabilization module by the at least one magnetic component. |
| US09659699B2 |
Magnetic substance holding device minimalizing residual magnetism
Disclosed herein is a magnetic substance holding device that minimizes residual magnetism by way of employing structures for minimizing reluctance to magnetic flux flow. |
| US09659695B2 |
Dipole ring magnetic field generator
Provided is a dipole ring magnetic field generator capable of generating a substantially unidirectional magnetic field in the internal space of a ring without using permanent magnet pieces having fan-shaped or trapezoidal sections, and as a result, a smaller skew angle therein is achieved. The sections of the permanent magnet pieces are shaped to be rectangular, and a plurality of the rectangular permanent magnet pieces are circularly placed at predetermined positions. Each of first, second, third and fourth permanent magnet units, which are main permanent magnet units, comprises five or more permanent magnet pieces. The first and third permanent magnet units, as well as the second and fourth permanent magnet units, are positioned oppositely from each other with respect to a central axis of the magnetic field generator and have hollow shapes or E-shapes facing against each other in a section perpendicular to the central axis. |
| US09659694B2 |
Non-oriented electrical steel plate and manufacturing process therefor
Disclosed are a non-oriented electrical steel plate with low iron loss and high magnetic conductivity and a manufacturing process therefor. The casting blank of the steel plate comprises the following components: Si: 0.1-2.0 wt %, Al: 0.1-1.0 wt %, Mn: 0.10-1.0 wt %, C: ≦0.005 wt %, P: ≦0.2 wt %, S: ≦0.005 wt %, N: ≦0.005 wt %, the balance being Fe and unavoidable impurities. The magnetic conductivity of the steel plate meets the following relationship formula: μ10+μ13+μ15≧13982−586.5P15/50; μ10+μ13+μ15≧10000, wherein P15/50 is the iron loss at a magnetic induction intensity of 1.5 T at 50 Hz; μ10, μ13, and μ15 are relative magnetic conductivities at induction intensities of 1.0 T, 1.3 T, and 1.5 T at 50 Hz, respectively. The steel plate can be used for manufacturing highly effective and ultra-highly effective electric motors. |
| US09659693B2 |
Grain-oriented electrical steel sheet and manufacturing method thereof
A silicon steel sheet (1) containing Si is cold-rolled. Next, a decarburization annealing (3) of the silicon steel sheet (1) is performed so as to cause a primary recrystallization. Next, the silicon steel sheet (1) is coiled so as to obtain a steel sheet coil (31). Next, an annealing (6) of the steel sheet coil (31) is performed through batch processing so as to cause a secondary recrystallization. Next, the steel sheet coil (31) is uncoiled and flattened. Between the cold-rolling and the obtaining the steel sheet coil (31), a laser beam is irradiated a plurality of times at predetermined intervals on a surface of the silicon steel sheet (1) from one end to the other end of the silicon steel sheet (1) along a sheet width direction (2). When the secondary recrystallization is caused, grain boundaries passing from a front surface to a rear surface of the silicon steel sheet (1) along paths of the laser beams are generated. |
| US09659692B2 |
Preparation method and application of magnetic iron oxide and desulfurizer containing the magnetic iron oxide as active component
A method of preparing magnetic iron oxide Fe21.333O32, which includes the steps of preparing a solid green rust and calcining the solid green rust to obtain the magnetic iron oxide Fe21.333O32. Also provided is the application of magnetic iron oxide Fe21.333O32 as an active material in desulfurization at a medium temperature. Also provided is a desulfurizer which uses magnetic iron oxide Fe21.333O32 and the application thereof. The present preparation method has simple steps and a short production period. |
| US09659690B2 |
Method for manufacturing a surface mount device
A method of manufacturing a surface mount device includes providing at least one core device and at least one lead frame. The core device is attached to the lead frame. The core device and the lead frame are encapsulated within an encapsulant. The encapsulant comprises a liquid epoxy that when cured has an oxygen permeability of less than approximately 0.4 cm3·mm/m2·atm·day. |
| US09659687B2 |
Noise reduction cable
A noise reduction cable includes an insulated wire including an insulator and a wire conductor, an outer circumference of which is coated with the insulator, a magnetic-material layer including a magnetic-material-containing member wound around an outer circumference of the insulated wire, a shield layer with which an outer circumference of the magnetic-material layer is coated, a magnetic-material-fixing-and-insulating tape layer that is disposed between the magnetic-material layer and the shield layer. The magnetic-material-fixing-and-insulating tape layer fixes the magnetic-material layer and insulates the magnetic-material layer and the shield layer from each other. |
| US09659681B2 |
Transparent conductive thin film
Disclosed is a transparent conductive thin film and an electronic device including the same. The transparent conductive thin film may include a perovskite vanadium oxide represented by Chemical Formula 1, A1-xVO3±δ [Chemical Formula 1] wherein A is a Group II element, 0≦x<1, and δ is a number necessary for charge balance in the oxide. |
| US09659680B2 |
Composite core for electrical transmission cables
A composite core for use in electrical cables, such as high voltage transmission cables is provided. The composite core contains at least one rod that includes a continuous fiber component surrounded by a capping layer. The continuous fiber component is formed from a plurality of unidirectionally aligned fiber rovings embedded within a thermoplastic polymer matrix. The present inventors have discovered that the degree to which the rovings are impregnated with the thermoplastic polymer matrix can be significantly improved through selective control over the impregnation process, and also through control over the degree of compression imparted to the rovings during formation and shaping of the rod, as well as the calibration of the final rod geometry. Such a well impregnated rod has a very small void fraction, which leads to excellent strength properties. Notably, the desired strength properties may be achieved without the need for different fiber types in the rod. |
| US09659679B2 |
Composite filar for implantable medical device
A composite filar has a conductive core, an outer fatigue-resistant metallic layer and a diffusion barrier between the core and the fatigue-resistant layer to prevent intermetallic diffusion between the core and the fatigue-resistant layer. |
| US09659675B2 |
Fuel rod auto-loading apparatus for nuclear fuel assembly
Disclosed is a fuel rod auto-loading apparatus for a nuclear fuel assembly, which disposes fuel rods in a fuel rod case in a bundle to assemble the fuel rods into the nuclear fuel assembly. The fuel rod auto-loading apparatus includes a fuel rod storage unit having a plurality of stacked racks for fuel rods, a fuel rod loading unit raised/lowered to the racks and transferring the fuel rods, a feeding unit placing the fuel rods in rows and loading the fuel rods into the fuel rod case, a fuel rod unloading unit selectively unloading some of the fuel rods stored in the fuel rod storage unit and transferring the fuel rods to the feeding unit, a fuel rod assembly lifter which is disposed parallel to the feeding unit, and a controller controlling driving of the fuel rod loading unit, the feeding unit, and the fuel rod unloading unit. |
| US09659674B2 |
Instrumentation and control penetration flange for pressurized water reactor
A nuclear reactor having a penetration seal ring interposed between the reactor vessel flange and a mating flange on the reactor vessel head. Radial ports through the flange provide passage into the interior of the reactor vessel for utility conduits that can be used to convey signal cables, power cables or hydraulic lines to the components within the interior of the pressure vessel. A double o-ring seal is provided on both sides of the penetration flange and partial J-welds on the inside diameter of the flange between the flange and the utility conduits secure the pressure boundary. |
| US09659672B2 |
Memory device includes efuse, and methods for reading and operating the same
The present disclosure provides a memory. The memory includes an array of memory cells arranged as a plurality of rows by a plurality of columns. A memory cell is connected to at least one redundant memory cell in series in a same row for storing same data as the memory cell; and a column of memory cells correspond to at least one redundant column of redundant memory cells wherein each redundant memory cell in the at least one redundant column stores same data as the memory cell in a same row. |
| US09659668B2 |
Via stack fault detection
A method and apparatus are disclosed. One such method includes selecting a die of a plurality of dies that are coupled together through a via stack. A via on the selected die can be coupled to ground. A supply voltage is coupled to an end of the via stack and a resulting current measured. A calculated resistance is compared to an expected resistance to determine if a fault exists in the via stack. |
| US09659664B1 |
Dynamically adjusting read voltage in a NAND flash memory
A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and Program-Read-Immediate (PM), and provides a way to dynamically adjust read voltage to account for CVDDEs. A read command includes extended addressing bits that are used when a CVDDE has occurred to access registers that indicate an adjustment to read voltage that is needed to accommodate the CVDDE. The read voltage is then dynamically adjusted to accommodate the CVDDE. When the CVDDE is no longer an issue, the read voltage is adjusted to its previous value before the CVDDE. |
| US09659662B2 |
Nonvolatile memory device and method of erasing nonvolatile memory device
A method is provided for erasing a nonvolatile memory device, including multiple memory blocks formed in a direction perpendicular to a substrate, each memory block having multiple strings connected to a bit line. The method includes selecting a memory block to be erased using a power supply voltage; unselecting a remaining memory block, other than the selected memory block, using a negative voltage; setting a bias condition to reduce leakage currents of the unselected memory block; and performing an erase operation on the selected memory block. |
| US09659661B2 |
EEPROM backup method and device
An electrically erasable programmable read-only memory (EEPROM) device includes a plurality of data areas in the EEPROM associated with a corresponding plurality of memory addresses, respectively, a data status indicator associated with each of the plurality of data areas. The data status indicator is configured to indicate that a data area is in an erase state, an uncertain state, or a valid state. The EEPROM device also includes a controller. A first data area and a second data area are configured to be a backup storage area for each other. In an erase and program cycle, at least one of the first or second memory areas is in a valid state throughout the erase and program cycle. Further, in an erase and program cycle, an erase operation is performed in one of the first or second memory areas, and a program operation is performed in the other data areas. |
| US09659655B1 |
Memory arrays using common floating gate series devices
Semiconductor devices and methods of writing information to a memory cell include an n-type transistor connected to a first terminal. The n-type transistor is formed with a low injection-barrier material gate dielectric. A p-type transistor is connected in serial between the n-type transistor and a second terminal. The p-type transistor is formed with a low injection-barrier material gate dielectric. The first and second transistor share a common floating gate and a common output node. |
| US09659653B2 |
Semiconductor device
An object is to provide a semiconductor device capable of accurate data retention even with a memory element including a depletion mode transistor. A gate terminal of a transistor for controlling input of a signal to a signal holding portion is negatively charged in advance. The connection to a power supply is physically broken, whereby negative charge is held at the gate terminal. Further, a capacitor having terminals one of which is electrically connected to the gate terminal of the transistor is provided, and thus switching operation of the transistor is controlled with the capacitor. |
| US09659652B2 |
Semiconductor storage device and control method thereof
According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal. |
| US09659651B1 |
Quantum memory systems and quantum repeater systems comprising chalcogenide optical fiber links and methods of storing and releasing photons using the same
A quantum memory system includes a chalcogenide optical fiber link, a magnetic field generation unit and a pump laser. The chalcogenide optical fiber link includes a photon receiving end opposite a photon output end and is positioned within a magnetic field of the magnetic field generation unit when the magnetic field generation unit generates the magnetic field. The pump laser is optically coupled to the photon receiving end of the chalcogenide optical fiber link. The chalcogenide optical fiber link includes a core doped with a rare-earth element dopant. The rare-earth element dopant is configured to absorb a storage photon traversing the chalcogenide optical fiber link upon receipt of a first pump pulse output by the pump laser. Further, the rare-earth element dopant is configured to release the storage photon upon receipt of a second pump pulse output by the pump laser. |
| US09659649B2 |
Semiconductor storage device and driving method thereof
A memory includes first signal-lines, second signal-lines and resistance-change memory cells. First and second drivers can supply power to the first and second signal-lines, respectively. The second driver increases a voltage of a selected second signal-line in a write-loop higher than that in a previous write-loop. The write-loop includes a write operation and a verify operation. A voltage increase width of the selected second signal-line at a time of transition from a first write-loop to a second write-loop is larger than a voltage increase width of the selected second signal-line at a time of transition from the second write-loop to a third write-loop. A voltage increase width of the selected second signal-line at a time of transition from the second write-loop to the third write-loop is smaller than a voltage increase width of the selected second signal-line at a time of transition from the third write-loop to a forth write-loop. |
| US09659648B2 |
Semiconductor memory device including switches for selectively turning on bit lines
A semiconductor memory device includes a plurality of first memory cells included in a first memory cell group and coupled to a plurality of first bit lines, respectively, a plurality of first switches coupled to the first bit lines, respectively, and coupled to a voltage node, a driver configured to supply a constant voltage to the voltage node for a write operation, and a switch control unit configured to selectively turn on one or more of the first switches when the write operation is performed. |
| US09659646B1 |
Programmable logic applications for an array of high on/off ratio and high speed non-volatile memory cells
A non-volatile programmable circuit configurable to perform logic functions, is provided. The programmable circuit can employ two-terminal non-volatile memory devices to store information, thereby mitigating or avoiding disturbance of programmed data in the absence of external power. Two-terminal resistive switching memory devices having high current on/off ratios and fast switching times can also be employed for high performance, and facilitating a high density array. For look-up table applications, input/output response times can be several nanoseconds or less, facilitating much faster response times than a memory array access for retrieving stored data. |
| US09659643B2 |
Operation method for RRAM
The present invention provides an operation method for RRAM. The operation method includes providing a reset voltage pulse to a RRAM, providing a dummy voltage pulse to the RRAM, and providing a verification voltage pulse to the RRAM. The reset current of the RRAM is read when the verification voltage pulse is provided. The voltage level of the verification voltage pulse is higher than the voltage level of the read voltage pulse for reading the RRAM. |
| US09659640B2 |
Semiconductor memory apparatus comprising a plurality of current sink units
A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages. |
| US09659639B2 |
Threshold voltage analysis
Apparatuses and methods for threshold voltage analysis are described. One or more methods for threshold voltage analysis include storing expected state indicators corresponding to a group of memory cells, applying a first sensing voltage to a selected access line to which the group of memory cells is coupled, sensing whether at least one of the memory cells of the group conducts responsive to the first sensing voltage, determining whether a discharge indicator for the at least one of the memory cells has changed responsive to application of the first sensing voltage, and determining that the first sensing voltage is the threshold voltage for a particular program state of the at least one of the memory cells. |
| US09659631B2 |
Current sense amplifiers, memory devices and methods
A current sense amplifier may include one or more clamping circuits coupled between differential output nodes of the amplifier. The clamping circuits may be enabled during at least a portion of the time that the sense amplifier is sensing the state of a memory cell coupled to a differential input of the sense amplifier. The clamping circuits may be disabled during the time that the sense amplifier is sensing the state of a memory cell at different times in a staggered manner. The clamping circuits may be effecting in making the current sense amplifier less sensitive to noise signals. |
| US09659630B2 |
Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes
Memory device systems, systems and methods are disclosed, such as those involving a plurality of stacked memory device dice and a logic die connected to each other through a plurality of conductors. The logic die serves, for example, as a memory interface device to a memory access device, such as a processor. The logic die can include a command register that allows selective operation in either of two modes. In a direct mode, conventional command signals as well as row and column address signals are applied to the logic die, and the logic die can essentially couple these signals directly to the memory device dice. In an indirect mode, a packet containing a command and a composite address are applied to the logic die, and the logic die can decode the command and composite address to apply conventional command signals as well as row and column address signals to the memory device dice. |
| US09659628B2 |
Signal timing alignment based on a common data strobe in memory devices configured for stacked arrangements
Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal. |
| US09659627B2 |
Semiconductor apparatus capable of preventing refresh error and memory system using the same
A semiconductor apparatus includes a plurality of memory banks configured to perform a refresh operation in response to an address count value and row active signals; a refresh control block configured to update refresh bank informations which define a bank designated to perform the refresh operation in response to a refresh command and bank addresses, and activate a count control signal in response to the refresh bank informations; and a counter configured to change the address count value in response to activation of the count control signal. |
| US09659624B1 |
Method for sense reference generation for MTJ based memories
In some aspects, the disclosure is directed to methods and systems for sense reference generation. A first array and a second array of MTJ based cells are configured as a magnetoresistive random access memory block. The first array is matched to the second array, the first array and the second array each including rows of MTJ based cells for storing data bits. Responsive to a first row of MTJ based cells in the first array being selected for at least a first stored data bit to be read, a reference row of MTJ based cells in the second array is connected to at least a first comparator of a plurality of comparators via reference lines, to provide sense reference for determining a value of the first stored data bit. The reference lines are shorted together prior to connecting to a first input of the first comparator. |
| US09659621B2 |
Semiconductor memory and memory system including the semiconductor memory
A memory system is provided which includes multiple semiconductor memories having arrays of memory cells and a memory controller configured to provide an address in common to the multiple memories. First and second addresses corresponding to first and second rows of memory cells in first and second memories are selected according to the address in common. The first row and its adjacent rows in the first memory can all be different from the second row and its adjacent rows in the second semiconductor memory. Different conversion schemes can provide scramble information used to convert the address in common into the first and second addresses. |
| US09659619B2 |
System and method for memory integrated circuit chip write abort indication
Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred. |
| US09659613B1 |
Methods and apparatus to read memory cells based on clock pulse counts
A disclosed example accesses a binary value latched by a sense amplifier in circuit with a memory cell, the binary value latched by the sense amplifier in response to a counter reaching a trigger count value, the trigger count value selected from a plurality of different trigger count values based on a characteristic of the memory cell; determines a programmed state of the memory cell based on the binary value; and performs a memory operation based on the programmed state of the memory cell. |
| US09659612B1 |
Semiconductor memory apparatus
A semiconductor memory apparatus may include a data storage region, a pipe register group, and an output driver. The data storage region may store data and output stored data as pipe input data. The pipe register group may include a plurality of pipe registers. In response to a plurality of coupling enable signals, a plurality of pipe input signals and a plurality of pipe output signals, the pipe register group may determine a number of pipe registers receiving the pipe input data and outputting pipe output data. The output driver may drive the pipe output data and transmit output data. |
| US09659611B1 |
Semiconductor devices and semiconductor systems including the same
A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command and a mask command. The second semiconductor device drives a first local line according to data on a first global line if a first mask write operation is performed in response to the command and the mask command. In addition, the second semiconductor device senses and amplifies data on a second local line if the first mask write operation is performed in response to the command and the mask command. |
| US09659600B2 |
Filter customization for search facilitation
A classifier may be used to receive, via a website, user input associated with a product search of a user, and may be further used to identify a plurality of filters associated with the product search and predict a user-specific subset of the plurality of filters. Then, a filter manager may be used to provide a webpage of the website to the user, based on the user-specific filter subset. |
| US09659588B2 |
Thermally-assisted magnetic recording head including a main pole and a plasmon generator
A main pole has a front end face including a first end face portion and a second end face portion. A plasmon generator has a near-field light generating surface. A surrounding layer has a first surrounding layer end face and a second surrounding layer end face located on opposite sides of the first end face portion in the track width direction. A gap film has a first gap film end face and a second gap film end face located on opposite sides of the near-field light generating surface in the track width direction. Each of the first and second gap film end faces includes a portion located between the first and second surrounding layer end faces, but does not include any portion interposed between the first surrounding layer end face and the first end face portion or between the second surrounding layer end face and the first end face portion. |
| US09659584B2 |
Dynamic flying height read/write head with off-track contact capability at touch down in hard disk drives
Dynamic fly height (DFH) control is obtained for a read/write head by use of a heating element having two laterally separated heat sources symmetrically spaced around the track center line of the head. The two heating sources create a protrusion profile relative to the undistorted ABS that recesses the read element and main write pole at the track center line relative to off-track positions. The resulting DFH control also protects the head from HDI (head-disk interference) events that are either the result of calibration procedures or normal HDD (hard disk drive) operation. |
| US09659581B2 |
Module with coating for abrasion testing
A module according to one embodiment includes a body having a tape bearing surface, and a coating on the tape bearing surface. The coating includes a bulk material and one or more sections of a second material at predetermined positions relative to the bulk material. The second material is constructed of a material selected from a group consisting of AlFeSil and Sendust. |
| US09659579B2 |
Method of and apparatus for evaluating intelligibility of a degraded speech signal, through selecting a difference function for compensating for a disturbance type, and providing an output signal indicative of a derived quality parameter
The present invention relates to a method of evaluating intelligibility of a degraded speech signal received from an audio transmission system conveying a reference signal. The method comprises sampling said reference and degraded signal into frames, and forming frame pairs. For each pair one or more difference functions representing a difference between the degraded and reference signal are provided. A difference function is selected and compensated for different disturbance types, such as to provide a disturbance density function adapted to human auditory perception. An overall quality parameter is determined indicative of the intelligibility of the degraded signal. The method comprises determining a switching parameter indicative of audio power level of said degraded signal, for performing said selecting. |
| US09659578B2 |
Computer implemented system and method for identifying significant speech frames within speech signals
The present disclosure envisages a computer implemented system for identifying significant speech frames within speech signals for facilitating speech recognition. The system receives an input speech signal having a plurality of feature vectors which is passed through a spectrum analyzer. The spectrum analyzer divides the input speech signal into a plurality of speech frames and computes a spectral magnitude of each of the speech frames. There is provided a suitability engine which is enabled to compute a suitability measure for each of the speech frames corresponding to spectral flatness measure (SFM), energy normalized variance (ENV), entropy, signal-to-noise ratio (SNR) and similarity measure. The suitability engine further computes a weighted suitability measure for each of the speech frames. |
| US09659574B2 |
Signal noise attenuation
A noise attenuation apparatus receives a first signal comprising a desired and a noise signal component. Two codebooks (109, 111) comprise respectively desired signal candidates and noise signal candidates representing possible desired and noise signal components respectively. A noise attenuator (105) generates estimated signal candidates by for each pair of desired and noise signal candidates generating an estimated signal candidate as a combination of the desired signal candidate and the noise signal candidate. A signal candidate is then determined from the estimated signal candidates and the first signal is noise compensated based on this signal candidate. A sensor signal representing a measurement of the desired source or the noise in the environment is used to reduce the number of candidates searched thereby substantially reducing complexity and computational resource usage. The noise attenuation may specifically be audio noise attenuation. |
| US09659570B2 |
Audiovisual information processing in videoconferencing
Embodiments of the present invention relate to audiovisual stream processing in videoconferences. For each audiovisual stream in a videoconference, a sound level of the audiovisual stream is detected. If the sound level exceeds a predefined threshold level, the audiovisual stream is processed with a first configuration. If the sound level is below the predefined threshold level, the audiovisual stream is processed with a second configuration. The second configuration is more resource-effective than the first configuration. |
| US09659566B2 |
Device and method for generating and decoding a side channel signal transmitted with a main channel signal
For generating a signal to be transmitted original information is encoded into a main channel and a side channel, wherein the side channel is more robust against channel influences than the main channel. On the receiver side, when the receive quality is above a threshold, which is necessitated to execute a successful decoding of the main channel, the main channel is reproduced. If the receive quality falls below this threshold, however, the side channel is reproduced which may have less bits than the main channel and which is a correspondingly lower quality representation of the original information than the main channel. |
| US09659563B1 |
System and method for sharing region specific pronunciations of phrases
Systems and methods include transmitting from a server to a client device a list of common phrases of a language and voice recordings associated with each of the phrase, wherein voice recordings provide region-specific pronunciations of the phrases. Users at the client device can search over communication network for common phrases and listen to how certain phrases of a language are spoken in different regions of the world. The users at the client device can also upload to the server their own voice recordings of phrases in their own region-specific pronunciations. Using the present systems and methods, the users can familiarize themselves with how a particular language, such as English, is spoken in different regions of the world prior to their international travel or business meeting. |
| US09659561B2 |
Recording support electronic device and method
A recording support method includes: receiving audio data; acquiring voice data from the audio data; receiving or generating text data corresponding to the voice data; storing at least part of the voice data and at least part of the text data corresponding to the at least part of the voice data; and output the received or generated text data, and wherein the stored at least part of the voice data and the stored at least part of the text data are associated each other, and wherein the at least part of voice data comprises one or more units. |
| US09659559B2 |
Phonetic distance measurement system and related methods
Phonetic distances are empirically measured as a function of speech recognition engine recognition error rates. The error rates are determined by comparing a recognized speech file with a reference file. The phonetic distances can be normalized to earlier measurements. The phonetic distances/error rates can also be used to improve speech recognition engine grammar selection, as an aid in language training and evaluation, and in other applications. |
| US09659557B2 |
Active control of membrane-type acoustic metamaterial
Sound attenuation is performed using a sound attenuation panel using an electromagnetic or electrostatic response unit to modify resonance. The sound attenuation panel has an acoustically transparent planar, rigid frame divided into a plurality of individual cells configured for attenuating sound. In one configuration, each cell has a weight fixed to the membrane. The planar geometry of each said individual cell, the flexibility of the membrane, and the weight establish a base resonant frequency for sound attenuation. The electromagnetic or electrostatic response unit is configured to modify the resonant frequency of the cell. |
| US09659555B1 |
Multichannel acoustic echo cancellation
An echo cancellation system performs audio beamforming to separate audio input into multiple directions (e.g., target signals) and generates multiple audio outputs using two acoustic echo cancellation (AEC) circuits. A first AEC removes a playback reference signal (generated from a signal sent a loudspeaker) to isolate speech included in the target signals. A second AEC removes an adaptive reference signal (generated from microphone inputs corresponding to audio received from the loudspeaker) to isolate speech included in the target signals. A beam selector receives the multiple audio outputs and selects the first AEC or the second AEC based on a linearity of the system. When linear (e.g., no distortion or variable delay between microphone input and playback signal), the beam selector selects an output from the first AEC based on signal to noise (SNR) ratios. When nonlinear, the beam selector selects an output from the second AEC. |
| US09659549B2 |
Support assembly and keyboard apparatus
A support assembly of a keyboard apparatus activated in accordance with pressing of a key to rotate a hammer provided at one end of a hammer shank, the support assembly includes a support rotatably disposed with respect to a frame, a jack having one side rotatably connected to the support and another side including a contact surface which makes contact with a hammer shank roller provided to the hammer shank, and a rib provided to the other side of the jack and projecting to a hammer shank roller side of the contact surface. |
| US09659547B2 |
Method and device for displaying images and text in accordance with a selected pattern
An electronic device and method for displaying a display item is disclosed. A first pattern comprises an image at a first image size and a character string at a first character string size. A second pattern comprises the image at a second image size and the character string at a second character string size, the character string not overlapping the image at the second image size. The second image size is larger than the first image size, and the second character string size is larger than the first character string size. A selected size comprises at least a first size and a second size. The first pattern is displayed for the display item if the selected size is the first size, and the second pattern is displayed for the display item if the selected size is the second size. |
| US09659543B2 |
Method of driving liquid crystal display device during write period
There are provided a method of driving a liquid crystal display device, a liquid crystal display device, and a portable device including the liquid crystal display device that can display an image where the occurrence of flicker is restrained when pause driving is performed. In a positive polarity pixel, a voltage of a counter electrode applied during a write period T1 is set to be higher than a counter voltage applied during a pause period T2 and is brought back to its original reference value immediately before starting the pause period T2. In this case, in the positive polarity pixel, the voltage applied to the liquid crystal layer decreases by an amount corresponding to the increase in the voltage of the counter electrode during the write period T1, compared to a negative polarity pixel, and thus, the change in luminance over time decreases. |
| US09659542B2 |
Gate driving unit and display device having the same
A gate driver includes multiple stages. Each stage has a circuit portion and a wiring portion. The wiring portion delivers first and second clock signals to the circuit portion. Further, the wiring portion includes first and second clock wirings receiving the first and second clock signal, respectively, first connecting wirings electrically connecting the first clock wiring with a first every other stage, and second connecting wirings electrically connecting the second clock wiring with the odd-numbered stages. Further, the wiring portion includes third connecting wirings electrically connecting the first connecting wiring with a second every other stage and fourth connecting wirings electrically connecting the second connecting wiring with the even-numbered stages. This configuration may prevent the gate driver from operating erroneously and reduce power consumed by the gate driver. |
| US09659539B2 |
Gate driver circuit, display apparatus having the same, and gate driving method
A gate driver, a display apparatus having the same, and a gate driving method are provided. The display apparatus includes a plurality of pixels, a data driver circuit, and a gate driver circuit. The gate driver circuit includes M groups of gate channels. Each of the M groups of gate channels includes a control circuit and an output buffer. The control circuit receives a power supply voltage from a power supply circuit and generates a modulated supply voltage. The output buffer is connected to the control circuit, the output buffer is powered by the modulated supply voltage to output a gate signal to a gate line of the display panel, wherein a driving pulse of the gate signal is shaped during a charge period according to the modulated supply voltage, and the shape of the driving pulse of the gate signal is maintained during a pre-charge period. |
| US09659536B2 |
Liquid crystal display
A liquid crystal display device includes a plurality of pixels disposed on an insulation substrate in a horizontal direction, and including a thin film transistor region and a display area; and a reference voltage line extended along a center of the display area in a direction perpendicular to the horizontal direction. The display area includes a plurality of domains disposed in two rows, a domain in one of the two rows includes a high-gray subpixel area including a high-gray pixel electrode, and a domain in the other of the two rows includes a low-gray subpixel area including a low-gray pixel electrode. The high-gray pixel electrode and the low-gray pixel electrode each include a plurality of unit pixel electrodes, and each unit pixel electrode includes a center electrode having a planar structure and a plurality of minute branches that extend from a side of the center electrode. |
| US09659535B2 |
Display device
A display device includes a timing controller configured to generate an image signal including a pre-emphasis voltage, a data driver configured to generate a plurality of data signals based on the image signal, and provide information about whether the image signal is normally received or not to the timing controller, and a display panel configured to receive the plurality of data signals and display images corresponding to the received data signals, where when the data driver fails to normally receive the image signal, the timing controller increases a level of the pre-emphasis voltage. |
| US09659533B2 |
Display apparatus and control method thereof
Provided is a display apparatus including: a light emitting unit having a light source; a display unit configured to display an image by controlling a transmittance of light from the light emitting unit; first and second sensors provided in the light emitting unit to detect a brightness of the light source; and a control unit configured to control a transmittance of the display unit on the basis of detection values from the first and second sensors. A distance from the light source to the second sensor is longer than a distance from the light source to the first sensor. The control unit controls the transmittance of the display unit on the basis of a change degree of the detection value from the first sensor during a given period and a change degree of the detection value from the second sensor during the period. |
| US09659524B2 |
Light-emitting device including substrate having cavity, and method for fabricating the light-emitting device
An EL display device capable of performing clear multi-gradation color display and electronic equipment provided with the EL display device are provided, wherein gradation display is performed according to a time-division driving method in which the luminescence and non-luminescence of an EL element (109) disposed in a pixel (104) are controlled by time, and the influence by the characteristic variability of a current controlling TFT (108) is prevented. When this method is used, a data signal side driving circuit (102) and a gate signal side driving circuit (103) are formed with TFTs that use a silicon film having a peculiar crystal structure and exhibit an extremely high operation speed. |
| US09659522B2 |
Display driver, method for driving display driver, and image display system
A display driver includes a memory, a receiver, an image output unit, a controller, and an image mode selection unit. The memory stores a video signal. The receiver receives the video signal and a first control signal from a host processor, where the first control signal corresponds to the video signal. The image output unit processes the video signal stored in the memory and outputs the processed video signal to a display unit. The controller controls the image output unit based on an image mode to display an image corresponding to the video signal. The image mode selection unit detects the first control signal and a second control signal from the controller, and changes the image mode based on the first control signal and second control signal. |
| US09659507B2 |
Process for clearing a tooth and illustrating the internal structure
A process for clearing an extracted tooth comprising the steps of drying the extracted tooth by exposure to air to produce a dried tooth, exposing the dried tooth to a decalcifying solution to produce a decalcified tooth, exposing the decalcified tooth to a non-alcohol dehydrant to produce a dehydrated tooth, exposing the dehydrated tooth to a clearing agent in a container until a desired amount clearing occurs, whereby the tooth is rendered translucent revealing its internal anatomy. |
| US09659494B2 |
Technologies for reporting and predicting emergency vehicle routes
Technologies for reporting and predicting emergency vehicle routes include a cloud server to receive emergency vehicle route data from an emergency vehicle, the emergency vehicle route data indicating a travel route of the emergency vehicle. The cloud server determines a scope of disclosure of the travel route to other vehicles based on the emergency vehicle route data and which other vehicles different from the emergency vehicle to which to convey the travel route of the emergency vehicle. The cloud server transmits a portion of the travel route of the emergency vehicle to the other vehicles based on the scope of disclosure. |
| US09659493B2 |
Traffic beacon
A flashing beacon may include a signal unit, a control unit associated with the signal unit, a solar panel or collector, and an activation device that may all be mounted or otherwise positioned on a post of a roadway sign. Light units associated with the signal unit may be programmed to flash on and off in a unique wig-wag pattern. Further, a light bar may also be used with the beacon to generate an intense flash of light soon after activation of the beacon as an additional means of grabbing the attention of the operator of a vehicle. |
| US09659484B1 |
Method and system for situational awareness for emergency response
Disclosed are systems and methods for sending emergency alerts. In some embodiments, sensors and wearable devices may trigger and send the emergency alerts and/or warning signals via available communication devices. Multi-media emergency alerts are also disclosed that include situational awareness information for effective and efficient emergency response. |
| US09659481B2 |
Data collection and monitoring system and method
A data collection and monitoring system for at least one defined space within a public or commercial facility includes: a plurality of sensors each monitoring a predetermined parameter; and a data collecting unit arranged for communicating with said sensors within a range of communication which corresponds to the extent of said defined space, with at least one mobile device for a user and with a central server which is associated with a storage medium. The storage medium is adapted for storing and monitoring data related to said sensors. Said data collecting unit is arranged for forwarding data relating to the sensors to the mobile device when the mobile device enters said space. |
| US09659480B2 |
Reminders based on virtual locations
One embodiment provides a method, including: obtaining, using a processor, a reminder, the reminder being triggered by a later access to a virtual location; thereafter determining, using a processor, a user is accessing the virtual location; and providing, using a processor, the reminder to the user. Other embodiments are described and claimed. |
| US09659474B1 |
Automatically learning signal strengths at places of interest for wireless signal strength based physical intruder detection
A method for intruder detection is provided. The method includes determining received signal strength of a first wireless device, while the first wireless device is moved at random within a region and generating a profile of the received signal strength of the first wireless device. The method includes determining received signal strength of a second wireless device and issuing an alert, responsive to received signal strength of the second wireless device meeting the profile. An intruder detection system is also provided. |
| US09659471B2 |
Anti-theft apparatus for mobile device
Provided is an anti-theft apparatus for a mobile device that does not disturb a customer when he or she observes and tests a mobile device in a shop and which can be efficiently used with various types of mobile devices. The anti-theft apparatus for a mobile device includes: a base attached to a back surface of a mobile device; a connecting terminal provided in a rear side of the base and connected to an access port of the mobile device; a separation sensor sensing separation of the mobile device from the base; and a distance control unit controlling the distance between the base and the connecting terminal. |
| US09659470B2 |
Door/window contact system
A window or door position detector includes an RFID tag attachable to a window or a door and a transceiver. The transceiver emits an activating signal to the tag. The tag, in turn, responds with an identifying RF signal indicative of a predetermined position of the window or the door. The detector includes a transceiver that can communicate with both the tag and a displaced monitoring system control panel. |
| US09659468B2 |
Haptic feedback in a haptically noisy environment
A method for providing haptic feedback is provided for a device that produces haptic noise, such as a power tool with an electric motor that produces noises and vibrations while in operation. An environmental condition of the device can be sensed while the device is being operated and generating haptic noise. A haptic noise characteristic of the device can be determined. A haptic drive signal based on the environmental condition and haptic noise characteristic can be generated. The haptic drive signal can be applied to a haptic output device associated with the device. |
| US09659467B1 |
Cash drawer
A cash drawer for use in mobile POS and other retail environments includes a plurality of coin bins that are positioned uniformly around the geometric center of the cash drawer. This unique arrangement eliminates the need for counterweights to prevent the drawer from tipping when opened. Bins for storing paper currency are disposed laterally outward from the coin bins and are canted outward so that the paper currency lies at an angle relative to the floor of the cash drawer rather than lying flat as in a conventional cash drawer. This enables the width of the drawer also to be reduced significantly. |
| US09659466B1 |
POS apparatus and display device
A display device includes a chassis, an electronic module, and a waterproof breathable member. The chassis has a front frame and a rear cover installed on the front frame. The rear cover has a plurality of heat-dissipating holes and an intake port, and the chassis is configured to allow a heat-dissipating airflow to pass through the accommodating space via the heat-dissipating holes and the intake port. The electronic module arranged in the chassis has a circuit board, and the heat-dissipating holes are arranged above the circuit board. The waterproof breathable member is disposed on an inner surface of the rear cover and entirely shields the heat-dissipating holes, so the heat-dissipating airflow only passes through the waterproof breathable member when the heat-dissipating airflow flows out of the chassis via the heat-dissipating holes. The waterproof breathable member is configured to avoid any liquid flowing into the chassis via the heat-dissipating holes. |
| US09659462B2 |
Gaming system and method providing simultaneous gaming with linked paytable events
The gaming device disclosed herein includes a plurality of simultaneously, substantially simultaneously or sequentially played primary games, wherein a designated triggering event in at least one of the games causes the gaming device to change, modify, supplement, add to, activate or otherwise influence the paytable of at least another game. |
| US09659460B2 |
Methods for multiple legal game providers and multiple jurisdictions with a single platform
A method is provided for playing lottery games with a single platform. A computer system is run on a single platform of a computer system to play a plurality of different lottery games for different jurisdictions. The single platform is accessible by a plurality of client device lottery game clients. Different types of lottery game packets are processed from a plurality of different jurisdictions using a workflow module at the single platform that includes sets of workflow instruction. A received lottery game packet is inspected and information about the lottery game packet is provided to the workflow module at the single platform. The processing of received lottery game packets is coordinated using selected ones of selectable communication function modules at the single platform based on the information about the lottery game packet provided by a deep lottery game packet inspection module at the single platform. |
| US09659459B2 |
Game server, gaming system and a gaming method
In a first aspect, the invention provides a game server configured to communicate during use with at least one player terminal, each of which is configured to facilitate play of a centrally drawn game, the game server configured to: determine that a win rule of the centrally drawn game has been satisfied; determine a prize corresponding to satisfaction of the win rule; and find a probabilistic game instance having a prize outcome corresponding to the prize, at least in part, by executing one or more probabilistic game instances to attempt to find a probabilistic game instance having a prize outcome corresponding to the prize. |
| US09659447B2 |
System and method for augmented wagering
Disclosed is a method and system involving augmented wagering. In one contemplated approach, context-sensitive betting options are conveniently presented to a player. Promotion of time sensitive propositions are presented to both simplify the wagering experience and provide a better targeted experience. |
| US09659446B2 |
Real money gambling payouts that depend on online social activity
Software on a server and/or client device causes a view in a graphical user interface (GUI) for a game to be displayed to a user. The game is an online gambling game for real money. The software receives input from the user. The input includes a wager and play according to game mechanics for the game. The software calculates a payout from the play. The payout includes a promotional payout that depends at least in part on a measure of social activity associated with the user or a measure of social influence associated with the user. And the software broadcasts the payout to at least one other person who is a social relation of the user. |
| US09659445B2 |
Slot machine with variable suspense factor
A slot machine which can be adjusted to alter the suspense level without changing the mathematics of the gameplay. By evaluating the final outcome before the reels stop spinning, the order in which the reels stop may be adjusted to either increase or decrease the level of suspense for the player, when compared with the standard left-to-right order. |
| US09659443B2 |
Triggering in-application currency transfer
Systems and methods are disclosed for electronically transferring currency from a source user account to a target user account in relation to a game application. A payment service provider may receive a request to transfer an amount of currency from the source user account to the target user account to be used for the game application. |
| US09659440B2 |
Gaming system, gaming device, and method providing multiple hand card game
A gaming device provides a single player poker game including one or more opportunities for forming player hands. In one embodiment, for a play of the poker game, a player places a wager on each of a plurality of player hands. The gaming device provides the player with one or more opportunities to fold one or more of the player hands and withdraw the wager associated with the folded hand. A number of community cards are dealt. The gaming device determines and provides any awards associated with a ranking of each of the remaining player hands according to a paytable. |
| US09659439B1 |
Method, device, and computer-readable medium for wagering on a skills-based digital gaming competition with an out-of-game peer wagering module
A method for wagering on a skills-based digital gaming competition, the method executing on a computing device including storage storing a peer-wagering module that is external and distinct from at least one game stored on the storage device or another storage device, the method including: receiving potential game and competitor player data; receiving game competition selection information from the player that includes at least one selected game instance and at least one wager amount; receiving game instance match ID data generated by the transactional server, wherein the game instance match ID data includes at least one of: credential data associated with the player, player wager amount or a board, level, or difficulty setting associated with the selected game instance; and transmitting the game instance match ID data and game initiation data to the game, thereby activating the at least one selected game instance on the computing device. |
| US09659437B2 |
System and method for cross platform persistent gaming sessions using a mobile device
Disclosed is a method for enabling cross platform persistent gaming sessions using a mobile device in a system that includes a game server, a network, one or more gaming machines, and one or more mobile devices. The method includes: associating a player's mobile device with one of the one or more gaming machines at which the player has a gaming session; presenting a player with an option to move their gaming experience to their mobile device when the player leaves the associated gaming machine if a gaming session is in progress; enabling the player to use its mobile device to continue playing a game after the player has left a proximity of the associated gaming machine by transferring the game from the associated gaming machine to the player's mobile device; and enabling transfer of funds between the associated gaming machine and the players' mobile device. |
| US09659434B2 |
Modular wagering game machine signage
Modular wagering game machine signage is described herein. In some embodiments, a modular wagering game machine sign can include a center module including a plurality of support members, at least one outer panel covering the frame, and a lighted faceplate including lighting units. The lighting units can include light emitting diodes (LEDs) and globes. The sign can also includes at least one side module connected to the center module via hand-spinning latches configured to press against one or more of the center module s support members. |
| US09659433B2 |
System and method for providing remote wagering games in a live table game system
Systems and methods for conducting multiple remote wagering games in a live table game system or similar system wherein the gaming symbols which are randomly generated as a result of a live table game are used to resolve the live table game and simulate play and resolve wagering outcomes of one or more remote wagering games which differ from the live table game. |
| US09659425B2 |
Electronic key for authentication
An electronic key supports a plurality of authentication methods and effectively prevents bidding-down attacks. For this purpose, security information is additionally provided by the electronic key, based on which a card reading device recognizes which authentication methods are supported by the electronic key. When the reading device recognizes based on said information that the electronic key supports a stronger second authentication method, but the authentication method was not recognized by the card reading device, the electronic key is, for example, rejected. |
| US09659423B2 |
Personal authentication apparatus system and method
A target authentication device includes an electrode to detect an electrical signal associated with a user of the device. The electrical signal represents an authentication code for the device. An authentication receiver module is coupled to the electrode. The module receives the electrical signal from the electrode and determines whether the electrical signal matches a predetermined criterion to authenticate the identity of the user based on the electrical signal. An authentication module is also disclosed. The authentication module includes one electrode to couple an electrical signal associated with a user to a user of a target authentication device, the electrical signal represents an authentication code for the device. An authentication transmission module is coupled to the electrode. The authentication transmission module transmits the electrical signal from the electrode. A method of authenticating the identity of a user of a target authentication device also is disclosed. |
| US09659421B2 |
Virtual security guard
Systems and methods are provided for remotely controlling access of vehicles into and out of a secured area. At a kiosk located at the point of entry into the secured area, information for identifying a vehicle and/or its driver are obtained via input devices at the kiosk and stored at a remote operations center. While a vehicle is inside the secured area, the stored information may be viewed, modified, and/or supplemented. Once a vehicle is authorized to exit the secured area, an electronic indication is received at the operations center. At a kiosk located at the point of exit from the secured area, identifying information pertaining to the vehicle and/or driver is again obtained. The information is verified at the operations center to ensure a sufficient match with identifying information for the vehicle and/or driver previously stored, before the operation center transmits a signal allowing the vehicle to exit. |
| US09659415B2 |
Apparatus for warning of occurrence of error of device
Proposed is a warning system which includes: a warning device; a display device; an IC CPU for controlling the operation of the display device and the warning device; and a master ECU for, connected to the IC CPU through a communication channel and connected to one or more warning devices through a hardware channel, controlling the operation of the warning device through the IC CPU. The master ECU includes an error detection module to monitor regularly the data validity of the communication channel, the warning device and the response of the IC CPU, and an on/off module to operate the warning device. When the error detection module detects an error in the data validity of the communication channel, the warning device and the response of the IC CPU, the master ECU controls the on/off module to operate directly the warning device using the hardware channel. |
| US09659414B2 |
Control methodology for wireless fluid level sensor
A control methodology for a wireless oil level sensor includes mounting a wireless oil pressure sensor to the oil plug of an engine. The oil pressure sensor detects a pressure which is used to determine a volume or level of oil in the oil pan. The oil level sensor can include an accelerometer sensor that can be excited by the vibration caused by the starting of the engine to “wake up” the sensor. The sensor can take an initial pressure reading at start up and associate the pressure reading with an oil level that can then be transmitted to a vehicle control unit. The sensor can remain idle until the accelerometer sensor no longer detects engine vibrations. The sensor is activated to take pressure readings at predetermined time intervals and to transmit an associated oil level to the vehicle central processor unit until a predetermined time period has expired. |
| US09659410B2 |
Low latency augmented reality display
An augmented reality system is provided and a method for controlling an augmented reality system are provided. The augmented reality system, for example, may include, but is not limited to a display, a memory, and at least one processor communicatively coupled to the display and memory, the at least one processor configured to generate image data having a first resolution at a first rate, store the generated image data in the memory, and transfer a portion of the generated image data having a second resolution to the display from the memory at a second rate, wherein the second rate is faster than the first rate and the second resolution is smaller than the first resolution. This dual rate system then enables a head-tracked augmented reality system to be updated at the high rate, reducing latency based artifacts. |
| US09659406B2 |
Procedural authoring
A three dimensional (3D) model of an object or environment may be created from images and other information of the object or environment. The 3D model may be created by aligning the images. The 3D model may include surfaces that are based on surfaces of the object or environment. The 3D model may be displayed, extorted, modified and so on. |
| US09659404B2 |
Normalized diffusion profile for subsurface scattering rendering
The disclosure provides an approach for rendering images which include subsurface scattering effects. In one aspect, a shader computes subsurface scattering effects via a ray-tracing or point-based technique using a normalized diffusion profile. The shader may use the inverse of a cumulative density function associated with the normalized diffusion profile to determine, for each ray intersecting the surface, points on the surface at which to evaluate the normalized diffusion profile. To determine the lit surface of a pixel due to subsurface scattering, the shader may multiply the result of the integral of the normalized diffusion profile for each of the R, G, and B color components by corresponding components of a diffuse color constant. Further, the shader may scale the integral of the normalized diffusion profile based on a scaling function which accounts for a forward-scattering nature of a medium and compensates for out-of-plane scattering. |
| US09659403B1 |
Initializing orientation in space for predictive information for free space gesture control and communication
The technology disclosed relates to initializing orientation of a three-dimensional (3D) model of an object. In particular, it relates to accessing at least one three-dimensional (3D) model of an object and observed information of the object movable in space and determining a primary orientation parameter of the model from the observed information. The method further includes detecting contours of the object in the observed information and calculating a representative normal to the detected contours, accessing a vector representing a 3D angle from the object to a point of observation, calculating a primary orientation of the object as a cross-product of the representative normal and the vector, and using the calculated primary orientation parameter to initialize the model. |
| US09659402B2 |
Filtering multi-sample surfaces
In accordance with some embodiments, multi-sampling may be used together with texture filtering and particularly texture filtering that generally uses rectangular grids of samples. This is accomplished by performing the texture filtering before doing the resolve, while conventionally the resolve is done and then the texture filtering is done. In addition, each sample is filtered as if it were the only sample. |
| US09659400B2 |
Efficiently implementing and displaying independent 3-dimensional interactive viewports of a virtual world on multiple client devices
Methods, apparatuses and systems directed to efficiently circumventing the limitations of client side rendering of virtual worlds. In a particular implementation, a proposed system renders each client viewport remotely, removing the burden of rendering a 3D scene from the local client device. 3D viewports, rather than being rasterized on the local client, are instead generated on a remote render device which then transmits a visual representation of the viewport to the client device in a format (including, but not limited to a video stream) which the client can use to display the scene without requiring complex 3D rasterization. This process eliminates the need for the client to have any specialized 3D rendering software or hardware, or to install or download any persistent render assets on the local system. The hardware requirements for the client are therefore roughly equivalent to those needed to play a continuous video stream. |
| US09659399B2 |
System, method, and computer program product for passing attribute structures between shader stages in a graphics pipeline
A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit also stores the first set of the attributes in a first portion of a memory system that can be read by the downstream shader unit and any shader units that are downstream in the processing pipeline relative to the upstream shader unit. In one embodiment, the processing unit is coupled between the upstream shader unit and the downstream shader unit. |
| US09659396B1 |
Clothwarp rigging cloth
Simulating cloth garments can be a large challenge that requires both directability as well as stability. In various embodiments, cloth garments can be animated using a technique called “Clothwarp.” Clothwarp assists garment animation through methods of cloth articulation and simulation targeting. In one aspect, Clothwarp grants another level of directable control on simulation, allowing the artist to modify the influence of the warp, both as a target input into the simulation and as a cleanup tool on simulation results. |
| US09659395B2 |
Systems, methods, and computer-readable media for generating and displaying visual images
System, methods, and computer-readable media are provided that include receiving an input including data items for creating an account for a member on a website, where the data items include category and/or attribute selections, determining whether one or more category selections have been received, designating an image corresponding thereto, if the one or more category selections have been received, assigning an outer portion shape, based on a number of received category selections, determining whether attribute selections have been received, associating a visual indicator with each attribute selection, designating segments of the outer portion shape with the visual indicators associated with each of the attribute selections, generating an icon, based on the designated image and the assigned outer portion shape, wherein the one or more segments of the outer portion shape are designated visual indicators associated with each of the attribute selections, and displaying the icon. |
| US09659394B2 |
Cinematization of output in compound device environment
Synthesizing of information and application user interface elements into a continuous stream form. This is done by adjusting a level of cinematicity to be applied to a session of information as the session is presented. Higher level cinematicity use higher degrees of movement in presenting user interface elements representing the information. In contrast, lower levels of cinematicity use lower or no movement of user interface elements representing the information. |
| US09659393B2 |
Selective rasterization
According to one embodiment, a given tile, made up of pixels or samples, may be of any shape, including a square shape. These pixels may contain colors, depths, stencil values, and other values. Each tile may be further augmented with a single bit, referred to herein as a render bit. In one embodiment, if the render bit is one, then everything is rendered as usual within the tile. However, if the render bit is zero, then nothing is rasterized to this tile and, correspondingly, depth tests, pixel shading, frame buffer accesses, and multi-sampled anti-aliasing (MSAA) resolves are not done for this tile. In other embodiments, some operations may be done nevertheless, but at least one operation is avoided based on the render bit. Of course, the render bits may be switched such that the bit zero indicates that everything should be rendered and the bit one indicates more limited rendering. |
| US09659390B2 |
Tomosynthesis reconstruction with rib suppression
A method for rib suppression in a volume chest x-ray image, executed at least in part by a computer captures a first set of unsegmented projection images, each at a corresponding angle, and forms a second set of segmented projection images by detecting rib features in a first projection image to form a first segmented projection image and generating a base model according to the detected rib features for the first projection image. Each of one or more additional projection images from the first set is processed to add members to the second set by a repeated sequence of generating a predictive model; detecting rib features using the predictive model; adjusting the base model according to detected rib features; and correcting rib detection in one or more members of the second set. The volume chest x-ray image is reconstructed according to the segmented projection images and is displayed. |
| US09659389B2 |
Fast scatter estimation in pet reconstruction
An image processing apparatus includes a scatter simulation processor which processes measured sinograms generated from imaging data acquired for an imaging subject by an imaging apparatus to produce a scatter sinogram that represents a shape of scatter contribution. A scatter scaling processor utilizes a Monte Carlo simulation to determine a scatter fraction and scales the scatter sinogram to generate a scaled scatter sinogram that matches the scatter contribution in the measured sinogram. A reconstruction processor reconstructs the imaging data into an image representation using the scaled scatter sinogram for scatter correction. |
| US09659388B1 |
White point calibration and gamut mapping for a display
In an example, a method of gamut mapping may include generating a first second-order or higher response-surface regression model that maps color values corresponding to the second color space to color values corresponding to the first color space. The method may include generating predicted color values for measured color values by inputting measured color values into the first second-order or higher response-surface regression model. The method may include generating, based on predicted color values and a plurality of color values, a second second-order or higher response-surface regression model that maps predicted color values output by the first second-order or higher response-surface regression model corresponding to the first color space to color values corresponding to the first color space. |
| US09659387B2 |
Graphics primitive and color channels
Graphics primitive and color channel techniques are described. In one or more implementations, image data is processed by a computing device to form a plurality of pixels and corresponding one or more color channels usable to define a color for a respective said pixel. A graphics primitive type is identified by the computing device associated with one or more of the pixels in the processed image data. The graphics primitive type is assigned by the computing device to the one or more pixels using at least one color channel. |
| US09659385B2 |
Method and apparatus for producing and reproducing augmented reality contents in mobile terminal
A method and an apparatus produce and reproduce Augmented Reality (AR) contents in a mobile terminal. In the method, contents are produced. An image including an object corresponding to the contents is recognized. Recognition information for the object corresponding to the contents is obtained based on a recognition result. AR contents including the contents and the recognition information are generated. Therefore, AR contents for an input image may be easily produced and reproduced, and the AR contents may be used as independent multimedia contents, not an auxiliary means of other contents. |
| US09659381B2 |
Real time texture mapping for augmented reality system
A system and method for real-time texture mapping for an augmented reality system are described. A viewing device includes an optical sensor to capture an image of a real-world object. A texture extraction module extracts a texture of the image of the real-world object. A recognition module identifies the real-world object based on the captured image. A texture mapping module retrieves a virtual object corresponding to the identified real-world object, maps the texture to the virtual object, dynamically updates the texture to the virtual object in real time, and generates a visualization of the virtual object in a display of the viewing device. |
| US09659380B1 |
Object position tracking using motion estimation
A method includes tracking positions of object(s) in video frames, including: processing an initial frame of a set of frames of the video frames using feature extraction to identify locations of features of the object(s), obtaining a next frame of the set and applying a motion estimation algorithm as between the next frame and a prior frame to identify updated locations of the features in the next frame, where locations of the features as identified based on the prior frame are used as input to the motion estimation algorithm to identify the updated locations of the features in the next frame based one searching less than an entirety of the next frame. The tracking further includes recognizing occurrence of an event, halting the iteratively performing, and repeating, for at least one subsequent set of frames, the processing an initial frame and the using motion estimation. |
| US09659376B2 |
Filtering device
When a positional relationship between reference blocks differs from a positional relationship between comparison blocks, a filtering device replaces the corresponding comparison blocks to update positional relationship information (order of correlations and the positional relationship thereof) into a state where the information should be and, thus, appropriately derives a difference value of an object so that the positional relationship between the reference blocks become identical to the positional relationship between the comparison blocks. |
| US09659370B2 |
Cortical bone segmentation from MR Dixon data
The present invention relates to a method for segmenting MR Dixon image data. A processor and a computer program product are also disclosed for use in connection with the method. The invention finds application in the MR imaging field in general and more specifically may be used in the generation of an attenuation map to correct for attenuation by cortical bone during the reconstruction of PET images. In the method, a surface mesh is adapted to a region of interest by: for each mesh element in the surface mesh: selecting a water target position based on a water image feature response in the MR Dixon water image; selecting a fat target position based on a fat image feature response in the MR Dixon fat image; and displacing each mesh element from its current position to a new position based on both its water target position and its corresponding fat target position. |
| US09659369B2 |
Radiological image radiographing display method and system thereof
Targeting of a lesion which is performed by a stereoscopic biopsy device or the like is performed simply and highly accurately. Designation of a predetermined position in the stereoscopic image is received to acquire position information when a stereoscopic image is displayed, radiological images of radiographing directions are displayed as two-dimensional images, a mark based on the position information, which is designated in the stereoscopic image, is displayed in the two-dimensional images, designation of a predetermined position in the two-dimensional images is further received to acquire the position information after the mark is displayed. |
| US09659367B2 |
Head mounted video and touch detection for healthcare facility hygiene
A system and method tracks touches in a healthcare environment in order to analyze paths of transmission and contamination for the purpose of eliminating and containing transmission of colonizing, drug-resistant pathogens. Touches are identified and tracked with the use of recording devices. Each touch is logged and a touch graph is generated to identify transmission paths. |
| US09659365B2 |
Image analysing
A flow pattern in a tube system is calculated from acquired image data. From the flow pattern virtual image data are generated and compared with the acquired data in order to determine a quality measure for the usability of the generated flow pattern at characteristic locations. |
| US09659364B2 |
Probabilistic refinement of model-based segmentation
A system for segmenting current diagnostic images includes a workstation (30) which segments a volume of interest in previously generated diagnostic images of a selected volume of interest generated from a plurality of patients. One or more processors (32) are programmed to register the segmented previously generated images and merge the segmented previously generated images into a probability map that depicts a probability that each voxel represents the volume of interest (24) or background (26) and a mean segmentation boundary (40). A segmentation processor (50) registers the probability map with a current diagnostic image (14) to generate a transformed probability map (62). A previously-trained classifier (70) classifies voxels of the diagnostic image with a probability that each voxel depicts the volume of interest or the background. A merge processor (80) merges the probabilities from the classifier and the transformed probability map. A segmentation boundary processor (84) determines the segmentation boundary for the volume of interest based on the current image based on the merge probabilities. |
| US09659363B2 |
Workpiece positioning apparatus using imaging unit
A positioning apparatus includes: a calculation unit that calculates an amount of deviation between a position of a feature point of a reference workpiece and a feature point of a workpiece by comparing a relative position of an imaging unit with respect to a table when the workpiece is imaged by the imaging unit with a reference relative position, and comparing a position of a feature point of the workpiece in the image of the workpiece imaged by the imaging unit with a reference point image position; and a program changing unit that generates a correction amount such that the amount of deviation calculated by the calculation unit becomes zero, and thereby changes a program of the machine tool. |
| US09659362B2 |
Methods and systems for generating a fingerprint for verification of a reference object
Disclosed herein are methods and systems for generating a fingerprint for verification of a reference object, such as a layer or ply during a composite laminate layup procedure. An exemplary method includes the steps of generating at least one reference image of a reference object; removing lighting effects from the at least one reference image to create at least one processed image; generating a reference fingerprint for the reference object based on the at least one processed image; generating at least one candidate image of a candidate object; generating a candidate fingerprint for the candidate object based on the at least one candidate image; and comparing the candidate fingerprint and the reference fingerprint to determine a correlation. An alert is generated based on the comparison. The alert is indicative that the correlation between the candidate fingerprint and the reference fingerprint exists. |
| US09659359B1 |
Method of and device for quality control process optimization
Methods of and Devices for quality control that can be used with automated optical inspection (AOI), solder paste inspection (SPI), and automated x-ray inspection (AXI) are disclosed. Plurality of threshold settings are entered in a testing process. Multiple testing results are obtained from the testing process. A graphic presentation is generated showing the numerical relationship among the data points, such that a quality control person is able to fine-tune the testing process to have a predetermined ratio of Defect Escaped % to False Call ppm. |
| US09659357B2 |
Device for correcting image processing data, and method for correcting image processing data
A mounting control device including an error detection device which detects an error based on image processing data and a component image taken of the component; and a data creation device which creates image processing data based on a component image, is provided. Processing of creating image processing data is performed automatically at a component mounting machine. Accordingly, because an operator does not need to perform work of creating image processing data, the work load on the operator may be reduced, and it is possible to improve work efficiency and productivity. |
| US09659353B2 |
Object speed weighted motion compensated interpolation
In one embodiment of the present invention, a method is provided for performing motion compensated interpolation using a previous frame and a current frame of a displayable output, the method comprising: detecting the speed of an object in the displayable output relative to the speed of a background in the displayable output; and blending results from a halo reducing interpolator and a median interpolator, wherein the results of each of the interpolators are weighted based on the speed of the object, to arrive at an interpolated frame using the previous frame and the current frame. |
| US09659351B2 |
Displaying personalized imagery for improving visual acuity
A method to generate an output image that improves observation of a target image viewed on a medium by an optical system is disclosed. The method includes receiving at least one target image by a processing system, receiving at least one parameter by the processing system, defining an error signal associated with the difference between calculated optical system observation of intermediate images and the at least one target image, minimizing the error signal, and generating an output image associated with the intermediate image having the minimized error. |
| US09659349B2 |
Color filter array scaler
A system identifies a scaling position in a captured image, and identifies red subpixels adjacent to the scaling position. The system computes a scaled red subpixel for the scaling position based on the identified red subpixels according to constraints. The system further computes a scaled blue subpixel based on identified adjacent blue subpixels, according to constraints, and computes a scaled green subpixel position based on Gr and Gb subpixels adjacent to the scaling position according to certain constraints. The system then generates a scaled image representative of the captured image, the scaled image including at least the scaled red subpixel value, the scaled blue subpixel value, and the scaled green subpixel value. |
| US09659348B1 |
Methods and systems for high definition scaling with low hardware complexity
Methods and systems are discussed for high definition scaling. The method may include identifying values for each of a first plurality of points in a first grid. The method may include interpolating values for each of a second plurality of points in a second grid based on a location of a point and the first plurality of points, wherein the second grid is in a first grid. The method may include interpolating a value for the point based on values for each of a subset of the second plurality of points. Interpolating by using the first plurality of points may reduce storage requirements. Directional filters may be used to preserve edge sharpness during interpolation. Iterative interpolation may ensure that a limited number of directional filters are used, thereby further reducing storage requirements. |
| US09659346B2 |
Image processing apparatus, image processing method, solid-state imaging device, and electronic apparatus configured to calculate a pixel value of a target position in accordance with a weighted value of each pixel on a candidate line of a plurality of candidate lines
An image processing apparatus includes: a target position selecting unit to select a pixel position on an input image, as a target position; a candidate line setting unit to set two or more sets of candidate lines including a pixel with a value, in the vicinity of the target position; a weighted-value calculating unit to calculate a weighted value that corresponds to a degree of expectation that the target position and the pixel position on the candidate line are on the same pattern; a direction classifying unit to selectively determine a set of candidate lines that are close to a direction of a pattern of the target position in accordance with the weighted value of each pixel on the candidate lines; and a first interpolated-value calculating unit to calculate a pixel value of the target position in accordance with the weighted value of each pixel on the candidate lines. |
| US09659334B2 |
Systems and methods for facilitating real estate transactions with purchase offer processing feature
A system and method for facilitating real estate transactions that is configured for receiving property information from a listing service or data feed, presenting a property information display on data communication devices for each property; generating a unique transaction actuator in each property information display, and responsive to selecting a unique transaction actuator, generating an offer form with an offer transmittal actuator, wherein the offer form includes a plurality of data fields relating to an offer to purchase property that are populated with the property information for the specific property associated with the selected unique transaction actuator. |
| US09659330B2 |
Distribution of market data
Systems and methods are provided for communicating and processing market data. The market data may comprise quotes, orders, trades and/or statistics. A messaging structure allows for adding, re-ordering and/or expanding data, within the printable character set of any language. One or more delimiters are defined and used to delimit data elements within the message structure. The data is interpreted based on templates which may be disseminated prior to the sending of messages and used as an abstraction so that the meaning of data need not be conveyed in the message. |
| US09659329B2 |
Foreign exchange trading system
Computer-implemented trading of financial products can include using a first communication channel to stream offering data for a plurality of different financial products from a server to a trading terminal. A second communication channel can be used to receive request for offers about ones of the financial products from the trading terminal. Such request can include user-specified parameters that modify or further specify characteristics of the desired products. Offers may then be determined for the product in accordance with the user-specified parameters and transmitted (over the second communication channel) back to the trading terminal. Each communication channel can be allocated a different priority and/or different level of system processing resources to optimize the allocation of system resources based on the criticality of data on each channel. |
| US09659327B2 |
Expense report system with receipt image processing
A system and method for generating expense data for an expense report is disclosed. The method includes receiving receipt data that includes one or more data items pertaining to a transaction, where the one or more data items are obtained from characters optically recognized in receipt image data for the transaction, and the receipt data includes data indicating whether the transaction is a credit card transaction or a cash transaction. The method further includes, if the receipt data indicates the transaction is a credit card transaction, creating expense data for the expense report, where the expense data includes the receipt data and the receipt image data associated with the receipt data for the transaction, and the receipt data includes credit card data. If the transaction indicates the transaction is a personal credit card transaction, then the credit card data is personal credit card data. |
| US09659312B1 |
System and method for a mobile wallet
A computer system includes a processor configured to receive one or more offers from one or more merchants, determine an offer from the one or more offers to present on a mobile device based on a characteristic of a user of the mobile device, receive a request for a code to provide to a merchant associated with the offer, the code being generated for the mobile device that belongs to the user, receive, from the mobile device, an indication from the user to use the offer that provides the user a discount from a price of a product or service, send to the mobile device, by an offer computer system, an offer code to be displayed on the mobile device and to be received by the merchant, aggregate a total amount of funds that the user has saved using a plurality of offers in the past, generate the code, including embedding in the code a transaction identification number, a geographic location of the mobile device, a date and a time, send the code to the mobile device for the merchant to scan and send to a financial institution to request funds from an account held by the user, receive a request for funds from the merchant that includes an address for the merchant and an amount of the transaction, and send the requested funds to the merchant upon verifying the offer was accepted by the user of the mobile device. |
| US09659311B2 |
Geographically-aware electronic traveling advertisements
Implementations disclose geographically-aware electronic traveling advertisements. A method includes providing, by a mobile advertising unit, advertisements for display on an electronic display of the mobile advertising unit, wherein the advertisements are stored in a data store of the mobile advertising unit, receiving a priority advertisement and rules corresponding to the priority advertisement, wherein the rules comprise a range of locations that trigger display of the priority advertisement and a time range to trigger display of the priority advertisement, identifying a current location of the mobile advertising unit from a location unit of the mobile advertising unit and a current time, determining that at least one of the current location is within the range of locations of the rules for the priority advertisement or the current time is within the time range of the rules for the priority advertisement, and providing the priority advertisement for display on the electronic display. |
| US09659310B1 |
Consumption based subscription frequency recommendations
Disclosed herein are systems, methods, and non-transitory computer-readable storage media for consumption based subscription frequency recommendations. A system configured to practice the example method first evaluates purchase statistics for an item to determine a consumption frequency. The system receives from a user a request for the item, and presents to the user a subscription recommendation based on the consumption frequency. The system can also provide recommendations for accessories by evaluating purchase statistics for an item to determine an accessory for the item, wherein a number of times the accessory is purchased with the item exceeds a threshold, receiving from a user a request for a subscription for recurring purchases of the item, and presenting to the user a recommendation to include the accessory as part of the subscription. |
| US09659308B2 |
Determining influence in a social networking system
An influence metric describing the influence of a social networking system object on social networking system users is determined based on affinities between the users and the object. For example, affinities between the associated users and the object are combined to determine the influence metric. Content may be selected for presentation to users based in part on influence metrics of the content. Additionally, influence metrics of objects associated with a user may be combined to determine the relevance of objects associated with the user, which may also be used to select content for presentation to the user. |
| US09659306B1 |
Method and system for linking social media systems and financial management systems to provide social group-based marketing programs
Marketing program data associated with a social group-based marketing program offered by a merchant is obtained. Access to social group identification data identifying two or more socially connected consumers and their respective financial data is obtained and analyzed to identify two or more spending and socially connected consumers. Two or more marketing program eligible spending and socially connected consumers who meet defined marketing program eligibility criteria are then identified and registered with the marketing program. Spending data associated with the registered spending and socially connected consumers is then monitored and when the spending data associated with the registered spending and socially connected consumers indicates the marketing program requirements of the social group-based marketing program have been met, the registered spending and socially connected consumers are provided the benefits of the social group-based marketing program. |
| US09659304B1 |
Methods, systems, and computer program products for associating a shopper loyalty program with a mobile payments account
A method includes performing operations as follows on at least one processor: receiving credentials from a shopper, the credentials being associated with a purchase from a merchant, determining that the shopper is registered for a loyalty program with the merchant based on the credentials, determining that the shopper has a mobile payments account with a mobile payments processor associated with the loyalty program, the mobile payments account having a mobile phone number associated therewith, sending a payment request for the purchase to the mobile payments processor with the mobile phone number, and receiving an approval for advancing funds for the purchase from the mobile payments processor responsive to the shopper sending a payment request from a mobile device having the mobile phone number. |
| US09659303B2 |
System and method for handling gamification fraud
Some embodiments of the present invention include determining if updates performed by a second user include a systematic change such as a reversal of an update previously performed by a first user within a time window. The reversal is associated with a record of data used by a gamification application executing in a computer system. A time delay is introduced between the update performed by the second user and rewarding the second user if the update performed by the second user includes the reversal within the time window. An update history of the first user and the second user is evaluated to identify pattern of reversals associated with similar records within the time window. The second user is prevented from being rewarded based on identifying that there are patterns of reversals from the update history occurring within the time window. |
| US09659302B2 |
Recommendation system, method and non-transitory computer readable storage medium for storing thereof
A recommendation method includes providing an ontology database, in which the ontology database includes a plurality of entities, and the entities are arranged in an ontology hierarchy structure with N hierarchy levels; storing a plurality of jth level user data respectively corresponding to a plurality of users; generating a plurality of kth level user data according to the jth level user data respectively; clustering the kth level user data; and recommending the entities in the ontology database to the users according to a clustering result. |
| US09659297B2 |
Biometric identification device
The invention is directed towards methods, systems and apparatuses, see FIG. 1, (100) for providing secure and private interactions. The invention provides capability for verifying the identity of a party initiating an electronic interaction with another party through data input module (140) which is verified by the identity verification module (150), which further includes a self-destruct mechanism (153). Embodiments of the invention include secure methods for conducting transactions and for limiting the transfer and distribution of personal data to only those data that are absolutely necessary for the completion of the transactions. The invention facilitates the transfer of additional personal data contingent upon an agreement that appropriately compensates the provider of the personal data. |
| US09659295B2 |
Personal digital identity device with near field and non near field radios for access control
A personal digital ID device provides a digital identifier to a service for a predetermined duration in response to user interaction. The user interaction may include a button press. The personal digital ID device may be in the form of a bracelet, a key fob, or other form factor. The service may be provided by a mobile device, in the cloud, or elsewhere. |
| US09659294B2 |
Mobile phone ATM processing methods and systems
Embodiments provide systems, methods, processes, computer program code and means for using mobile devices to conduct transactions with ATM devices. |
| US09659293B2 |
Money transfer smart phone methods and systems
A method includes establishing a first funds transfer account associated with a first device and a second funds transfer account with a second device, funding at least the first fund account, and selecting the second device as the recipient of a funds transfer from the first device. The method further includes sending a communications link request from the first device to the second device and receiving acceptance of the communications link request from the second device. The method then establishes a communications link between the first device and the second device, initiates a funds transfer from the first device to the second device, wherein the amount is designated at the first device, and verifies the funds transfer amount, the first funds transfer account, and the second funds transfer account. Then, the method transfers the amount to the second funds transfer account associated with second device. |
| US09659289B2 |
Customer touch point for real time sharing of transaction data between different customer interaction channels
Techniques and equipment for enabling a cross-channel real time awareness framework for capturing and sharing transaction data in real time for a user via an interface of a channel of an enterprise are disclosed. The captured transaction data are made accessible to other channels of the enterprise for processing transactions initiated by the user via an interface of the one of the other channels. |
| US09659286B2 |
Point-of-sale terminal having a scanner shared by full and scan-only checkout modules
Disclosed herein are methods and systems for executing a first transaction at a checkout system at substantially the same time that a second transaction is started at the checkout system. For example, a cashier can scan one or more items, adding the items to a first transaction. When all items have been added to the first transaction and a first customer is making a payment in the first transaction, the cashier can begin to add items to a second transaction, such that execution of the first transaction occurs at substantially the same time that items are added to the second transaction. |
| US09659283B1 |
Generating a model and estimating a cost using a controllable inspection aircraft
Disclosed systems and methods estimate a financial cost to remedy estimated damage to a building. A controllable inspection vehicle, such as an aircraft, may capture one or more images of the building. The one or more images may be utilized to generate a model of the building, which can be analyzed to estimate the damage to the building. |
| US09659282B2 |
Generating a visitation schedule
The method includes identifying a location of an individual and an amount of time the individual will be in the location. The method further includes identifying one or more contacts of the individual that are within a threshold distance of the identified location of the individual during the identified amount time the individual will be in the location. The method further includes generating a first visitation schedule and corresponding visitation route for the individual based upon the identified status for the one or more contacts of the individual based upon social media activity, the identified frequency of interaction between the individual and the identified one or more contacts of the individual, and the determined distances from the individual to the identified one or more contacts and between each of the identified one or more contacts. |
| US09659281B2 |
System for managing scheduling conflicts
A system that incorporates teachings of the present disclosure may include, for example, a proactive scheduler having a controller element to determine a scheduling conflict between a called party and a calling party according to calendar information of the called party and presence information of the called party. Additional embodiments are disclosed. |
| US09659275B2 |
Consumer demand-based inventory management system
In some embodiments, methods and systems of managing products at a retail sales facility include scanning a product in a stocking cart at the retail sales facility using a hand-held electronic device including a processor. At least two of the following three functions may be performed based on the scanning of the product. First, the stocking cart may be audited by comparing scanned data to data contained in an inventory management database. Second, a determination of whether the item is on a pick list may be made, which may include determining a demand for the scanned product to arrive at a decision whether to store the product in the stock room or place it on a shelf on the sales floor. Third, if the item is to be stored in the stock room, a determination of whether identical items are stored in bins in the stock room may be made. |
| US09659265B2 |
Methods and systems for collecting and analyzing enterprise activities
Various systems and methods are described for gathering events and analyzing the events and nodes associated with the events. Various arrangements may include receiving events from one or more applications. An event may include two nodes and an action. These events may be stored and processed to determine relations between nodes. These relations may then be processed to determine the similarity between nodes. Further, the nodes may be ranked according to the importance of the nodes as compared with each other. |
| US09659262B2 |
Sharing quantity takeoff data between computer aided design projects
Embodiments of the present invention include methods for semi-automatic quantity takeoff from computer aided design (CAD) drawings. For each drawing object a corresponding takeoff object is created. A takeoff object may include the dimension of geometry (e.g., numerical, lineal, area) to quantify, the object parameter to be quantified for all instances of the object, and the takeoff calculations to be performed. After a takeoff object is defined, the corresponding instances are automatically identified and quantified. The cost of each instance is then calculated and added to the project cost. Using automated methods, instead of manual techniques, reduces errors and increases the accuracy of the generated cost estimate. Advantageously, the takeoff objects may be saved in the system database and reused for different projects, thereby ensuring consistency between projects. Furthermore, reusing takeoff information, both between instances of an object and between projects, reduces the time required to perform cost estimates. |
| US09659257B2 |
Predictive cueing
A method and system that provide for decision support and/or training support in crisis decision-making situations are provided. In one implementation, a method identifies patterns from known cases based on information from a crisis event. Each of the known cases includes attributes and at least one outcome. The method also identifies a first subset of the known cases that relate to the identified patterns from the known cases. The method also analyzes the identified patterns to determine a cue that, if answered, will provide a second subset of the known cases including a more converged range of decision outcomes than the first subset. |
| US09659250B2 |
Facility state monitoring method and device for same
In case-based anomaly indication detection in a facility, there are problems such as error generation due to insufficient learning data or execution difficulty due to increased memory capacity and calculation time when the learning data period has been increased to obtain the learning data sufficiently. Provided is a method for monitoring facility state on the basis of a time series signal outputted from the facility, wherein an operation pattern label for each fixed interval is assigned on the basis of the time series signal, learning data is selected on the basis of the operation pattern label for each fixed interval, a normal model is created on the basis of the selected learning data, an anomaly measure is calculated on the basis of the time series signal and the normal model, and the facility state is determined to be anomaly or normal on the basis of the calculated anomaly measure. |
| US09659243B2 |
Image forming apparatus and method for driving light source
An image forming apparatus includes: an image processor configured to perform first image processing on image data having a first resolution and to add tag data to a target pixel where second image processing is to be performed; a resolution converter configured to convert the image data into image data having a second resolution higher than the first resolution, and to perform the second image processing based on arrangement of the image data having the first resolution and the tag data; a pulse generator configured to generate an on-off modulation signal and an application-current switching signal in accordance with the image data having undergone the second image processing; and a light source driver configured to drive the light source in accordance with a current setting value output from an application current setter depending on the application-current switching signal and the on-off modulation signal. |
| US09659241B1 |
Method for printing on a stationary flat media using a portable large format printer
A method for operating a portable large format inkjet printer includes determining an output image size of an output image to be printed on a stationary flat media; selecting a source image to serve as the output image; displaying a preview of the output image superposed with an output image grid defining a plurality of output image area portions; selecting a serial order of printing each of the output image area portions; selecting a next output image area portion based on the serial order; printing the selected next output image area portion at a media print area of the stationary flat media; and repeating the acts of selecting the next output image area portion and printing, for each of the plurality of output image area portions, until an entirety of the output image area has been printed at the media print area of the stationary flat media. |
| US09659240B2 |
Card reader
A card reader may include a card insertion port; a card conveying passage; and a card lock mechanism. The card lock mechanism may include a motor; a lock member comprising a prevention pawl; and a power transmission mechanism structured to transmit power of the motor to the lock member. The power transmission mechanism may include a worm gear having a screw gear and a helical gear engaged with the screw gear. The screw gear may be disposed on a motor side relative to the helical gear in a transmitting direction of power from the motor to the lock member. The lock member may further include a teeth part in a fan shape. The teeth part may be driven through engagement of gears including the worm gear to move the prevention pawl. |
| US09659237B2 |
Imaging through aerosol obscurants
A method for determining a level of haze within a field of view of an image sensor adapted for detecting a plurality of color components includes collecting a first image of the field of view at a first point in time, defining regions of the first image as a reference and determining reference intensities for each color component. At least one second image is collected at different points in time and intensities for each color component are determined and compared against the reference intensities. If the intensities of second image differ from the reference intensities by more than a predetermined threshold, all or a portion of the second image is designated as being obscured by haze and requiring correction. |
| US09659233B2 |
Method and apparatus for detecting salient region of image
The present invention provides a method and an apparatus for detecting a salient region of an image. Classification processing is obtained by means of pre-training, so as to obtain a classification label, where the classification label is used to indicate a salience detection algorithm for detecting a salient region of the test image. Salience detection is performed on the test image by using the salience detection algorithm indicated by the classification label, so as to obtain the salient region of the test image. Because a salience detection algorithm with the best detection effect is acquired by using the image feature vector of the test image, to detect the salient region of the test image, accuracy of salience detection is improved. |
| US09659229B2 |
Method and system for signal analysis
An image of a human, animal or machine subject, is analysed to detect regions which include strong periodic intensity variations, such as a photoplethysmogram (PPG) signal in a human or animal, or some periodic vibration in a machine. The image is divided into plural regions of fixed order is fitted to a representative intensity signal for that region. The poles of the fitted autoregressive model are thresholded by magnitude to select only the pole or poles with a magnitude greater than the threshold. The pole magnitude therefore acts as a signal quality index. The dominant pole is representative of the strongest periodic information and the frequency of that spectral component can be derived from the phase angle of the pole. The image may be redisplayed with image attributes, e.g. color-coding, according to the pole magnitude in each region of interest and/or the dominant pole phase angle in each region of interest. In the case of a PPG image signal this can give maps of heart rate and breathing rate. |
| US09659226B2 |
Image processing apparatus, image processing method, and computer-readable recording medium storing image processing program
An image processing apparatus is configured to extract contour information of a medium area from readout image data, and correct distortion of the medium area based on the contour information. The medium area is an area for image data corresponding to a medium serving as a reading target. The image processing apparatus includes an acquiring unit that acquires the readout image data, an extracting unit that extracts the contour information of the medium area from the readout image data, a displaying unit that displays the contour information so as to superpose the contour information on the readout image data, a detecting unit that detects an instruction of changing a position of the contour information. The extracting unit extracts again the contour information by reflecting the instruction of changing, and the displaying unit redisplays the contour information extracted again by the extracting unit. |
| US09659223B2 |
Driving assistance apparatus and driving assistance method
A driving assistance apparatus captures with a camera a video image showing an area, which surrounds a vehicle and includes a target on a road surface; generates a positioning video image for positioning the vehicle; and displays the generated positioning video image on a display monitor. The driving assistance apparatus also acquires a relative location of the target with respect to the vehicle. Further, based on the relative location of the target, the driving assistance apparatus switches the display mode of the positioning video image displayed on the display monitor between a first display mode (in which the target moves with respect to the vehicle) and a second display mode (in which the vehicle moves with respect to the target). |
| US09659219B2 |
Computer-aided video production triggered by media availability
A method includes receiving multiple visual media items from one or more media databases, and associating the visual media items with one or more story topics. In response to deciding that a given story topic is associated with sufficient suitable visual media items, computer-aided creation of a video clip relating to the given story topic is initiated using the associated visual media items. |
| US09659217B2 |
Systems and methods for scale invariant 3D object detection leveraging processor architecture
An example method includes receiving a plurality of templates of a plurality of objects, where a template comprises feature values sampled at corresponding points of a two-dimensional grid of points positioned over a particular view of an object and scaled based on a depth of the object at the particular view. The method may further include receiving an image of an environment and determining a matrix representative of the image, where a row of the matrix comprises feature values sampled at a particular point of the two-dimensional grid positioned over one or more locations within the image and scaled based on depths of the one or more locations. The method may additionally include determining at least one similarity vector corresponding to at least one template and using the at least one similarity vector to identify at least one matching template for at least one object located within the image. |
| US09659205B2 |
Multimodal imaging system and method for non-contact identification of multiple biometric traits
Systems and methods are disclosed for obtaining at least a pair of biometric traits of a person and without contact with the person. In one embodiment a system is disclosed which makes use of a plurality of illumination modules and an imaging module, where a single image is acquired with a color encoded imaging sensor. Parallel and orthogonally polarized images are obtained by at least one sensor of the imaging module from illuminations produced by the illumination modules. A processing subsystem uses mathematical applied operations between the acquired images to selectively produce at least one image of at least one specific biometric trait, such as a finger print, a palm print, a finger-vein, a palm vein, or hand geometry. The biometric trait can be subsequently used for biometric verification and identification. |
| US09659197B2 |
Memorabilia provenance authentication
Embodiments of the invention for the track, categorize, or authenticate the provenance of historical artifacts. The invention couples an artifact to at least one unique identifier. Unique identifiers may be attached to or be contained within an artifact. Unique identifiers are coupled to a data storage archive where historical information relating to the artifact are stored. In certain embodiments the data storage archive is a database or relational database. Artifacts incorporated into the invention, may be objects used in sports, be objects used in politics, or may be personal objects. The invention tracks the use of artifacts and records historical information corresponding to the artifact in the data storage archive. Historical information recorded may include the time, or place where an artifact was used. The invention, in certain embodiments also tracks the use of the movement of an artifact, tracks who interacted with the artifact, and provides a mechanism for collectors to review historical information corresponding to one or more particular artifacts. |