最新美国发明专利第2017-05-23期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09660691B2	Antenna interface circuits with quadplexers Techniques for supporting data transmission and reception on multiple bands for carrier aggregation are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes first and second antenna interface circuits coupled to first and second antennas, respectively. The first antenna interface circuit includes a first quadplexer for first and second bands. The second antenna interface circuit includes a second quadplexer for the first and second bands. The first quadplexer may be a duplicate of the second quadplexer, which may simplify implementation. Each antenna interface circuit may further include a diplexer, a duplexer, a triplexer, another quadplexer, switches, etc. The first and second quadplexers may support data transmission and reception on two bands in a first band group. Other circuits in the first and second antenna interface circuits may support data transmission and/or reception on additional bands, possibly in one or more other band groups.
US09660689B2	Multiple radio frequency (RF) systems using a common radio frequency port without an RF switch Methods and systems are disclosed for changing between multiple radio frequency (RF) systems. The method comprising transmitting, by a first radio frequency (RF) transmitter of a first RF system, a first RF signal from an antenna, receiving, by a first RF receiver of the first RF system, a second RF signal from the antenna, and receiving, by a second RF receiver of a second RF system, the second RF signal from the antenna, wherein a first RF port of the first RF system and a second RF port of the second RF system are both connected to a common RF port of the antenna, and wherein the first and second RF systems operate with overlapping frequency bands.
US09660688B2	Apparatus and methods for power amplifier output matching Apparatus and methods for power amplifier output matching is provided. In certain configurations, an output matching circuit includes a supply voltage biasing circuit electrically connected between an input node and a power high supply voltage, a second-order harmonic series resonant circuit electrically connected between the input node and a power low supply voltage, a third-order harmonic parallel resonant circuit electrically connected between the input node and a harmonic frequency grounding node, a third-order harmonic series resonant circuit electrically connected between the harmonic frequency grounding node and the power low supply voltage, and a DC blocking capacitor electrically connected between the harmonic frequency grounding node and an output node.
US09660680B1	Apparatus and method for communication over power lines An apparatus and method are provided for communicating over power lines. The apparatus includes a coupling modem that is situated between a power line and a device. The coupling modem is configured to demodulate a signal received from the power line into a sine signal and a cosine signal. The coupling modem is also configured to modulate a communicated bit stream received from the device into a transmitted signal in order to impose the transmitted signal onto the power line.
US09660679B2	Method, system and apparatus for automatic gain control in direct-conversion receiver A wireless receiver automatic gain control system includes: a coarse amplification subsystem that receives and amplifies a carrier-modulated signal; a demodulator that generates a baseband signal from the amplified carrier-modulated signal; a fine amplification subsystem that amplifies the baseband signal; and a controller connected to the amplification subsystems. The controller: obtains a unified gain value for the amplification subsystems; based on the unified gain value, selects (i) one of a plurality of coarse gain values defining a set of coarse gain steps each spanning a plurality of unified gain steps, and (ii) one of a plurality of fine gain values defining a set of fine gain steps each spanning a single unified gain step; and sets (i) the gain of the coarse amplification subsystem to the selected coarse gain value, and (ii) the gain of the fine amplification subsystem to the selected fine gain value.
US09660678B2	Adaptive radio frequency local oscillator tuning Methods, systems, and devices are described for adaptively or dynamically tuning a radio frequency (RF) local oscillator (LO) for wireless communications. In one example, a radio may receive an RF signal and the LO of a radio may be tuned to a frequency that is an offset from its reception (RX) center frequency to deal with interference from another signal, such as one being transmitted using a different radio access technology (RAT) than that of the radio. The offset may be determined based upon an effect of the tuning on an attribute of the RF signal. In addition, the offset may be determined based on interference caused by the other signal.
US09660676B2	Methods and apparatus for reducing interference effect on data transmitted over a communication channel In one example embodiment, a method for reducing an effect of an interference signal on data being transmitted over a communication channel includes determining, by a processor, a code word based on at least an information vector and an interference vector, the information vector representing the data, the interference vector representing the interference signal. The method further includes determining, by the processor, a code vector based on the determined code word. The method further includes generating, by the processor, a transmit vector based on the code vector and the interference vector.
US09660674B2	Self-interference cancellation antenna systems and methods The present application describes systems and methods of performing self-interference cancellation. Such systems may include generating a transmit signal along a transmit path of a transceiver, where the transmit signal can be sent through a circulator to isolate the transmit signal from a receiver. The transmit signal may be transmitted from an antenna, and a signal may be reflected from the antenna, where the reflected signal may be at less power than an incident power to the antenna, and where the reflected signal may include a transmitter carrier signal and a transmitter noise. A received signal may be routed from the antenna to the receiver, the reflected signal may be routed through a filter and a phase shifter, and the signal may be combined with the received signal in the receive path to cancel the portion of the transmit signal that entered the receive path towards the receiver from the circulator.
US09660670B1	System, device, and method for combining software defined radios A device includes circuitry configured to assess a broadband spectrum environment including signal and blocker characteristics via one or more receiver paths, determine operational parameters for the device based on the signal and blocker characteristics, and align one or more radio components from one or more radios for operation based on the operational parameters of the device.
US09660665B2	Delta sigma modulator with dynamic error cancellation The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.
US09660664B1	Generating asynchronous clock signals for successive approximation register (SAR) analog to digital converters (ADCs) Aspects of generating asynchronous clock signals for successive approximation register (SAR) analog to digital converters (ADCs) are disclosed. In one aspect, an asynchronous clock generator circuit is provided that is configured to receive a voltage generated by a comparator in a SAR ADC, and generate an outside-window signal in response to the voltage being outside of a voltage threshold window. The asynchronous clock generator circuit is configured to generate a trigger signal in response to the outside-window signal coinciding with the asynchronous clock signal being in an inactive state. In response to the trigger signal being in an active state for a minimum time, the asynchronous clock generator circuit is configured to generate an edge signal, and generate the asynchronous clock signal having a pulse width in response to the edge signal. The asynchronous clock generator circuit adaptively generates the asynchronous clock signal according to timing of each comparison.
US09660661B2	High bandwidth oscilloscope A method for improving bandwidth of an oscilloscope involves, in preferred embodiments, the use of frequency up-conversion and down-conversion techniques. In an illustrative embodiment the technique involves separating an input signal into a high frequency content and a low frequency content, down-converting the high frequency content in the analog domain so that it may be processed by the oscilloscope's analog front end, digitizing the low frequency content and the down-converted high frequency content, and forming a digital representation of the received analog signal from the digitized low frequency content and high frequency content.
US09660660B1	Analog to digital converter with high precision offset calibrated integrating comparators An analog-to-digital converter includes a plurality of slave sampler multiplexers responsive to outputs of a master sampler that receives analog signals and whose output ports connect to integrating threshold comparators having capacitive digital-to-analog conversion offset adjustments for forming an analog-to-thermometer code conversion. A calibration state machine receives outputs of each of the integrating threshold comparators to control the capacitive digital-to-analog conversion offset adjustment of every integrating threshold comparator and to control a calibration digital-to analog converter. A thermometer code to binary code logic decoder receives outputs of each of the integrating threshold comparators and outputs digital samples.
US09660658B2	Analog-to-digital conversion At least one asymmetry element is configured to receive an input signal and is coupled to a first branch of a bi-stable flip-flop comprising the first branch and a second branch. An asymmetry between the first branch and the second branch depends on the input signal. A value indicative of the input signal is determined based on received output signals of a plurality of readout events.
US09660656B2	Delay compensation Methods and circuits for delay compensation are provided. A data clock may be generated from a peripheral clock. Sample data may be provided in a data signal on a bus in response to an edge of the data clock, where the edge of the data clock is triggered by an initial edge of the peripheral clock. A delay of the data clock relative to the peripheral clock may be selected based on a time difference between the initial edge of the peripheral clock and a time at which the sample data is detected on the bus. A delayed data clock having the selected delay relative to the peripheral clock may be generated. Requested data may be provided on the bus in response to an edge of the delayed data clock.
US09660653B1	Techniques for reducing skew between clock signals A skew reduction circuit includes a first delay circuit that delays a first clock signal to generate a second clock signal and a second delay circuit that delays a third clock signal to generate a fourth clock signal. The skew reduction circuit also includes a time-to-digital converter circuit that measures a skew between the second and fourth clock signals to generate a measurement of the skew between the second and fourth clock signals. The skew reduction circuit adjusts a delay of one of the first or second delay circuits to reduce the skew between the second and fourth clock signals based on the measurement of the skew.
US09660651B2	Level shift circuit An input part is supplied with a low voltage from a low voltage power supply line. A level shift part and an output part are supplied with a high voltage from a high voltage power supply line. An input terminal is pulled up by a resistor and connected to the level shift part through a buffer circuit and an inverter circuit. The level shift part is connected in series with an NMOS and turned on when the input terminal changes to a low level. The output terminal is pulled up by a resistor through the buffer circuit. Even when the level shift part operates unstably because of long delay time from rising of a potential of the high voltage power supply line to rising of a potential of the low voltage power supply line, the output voltage is maintained at a high level.
US09660650B1	Integrated circuits with improved register circuitry Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions include register circuitry that may be controlled by register control signals. A clock enable feedback loop circuit controlled by a clock enable control signal may couple the register output to the register input. The clock enable feedback loop circuit may facilitate adjustment of register locations within a design while ensuring correct clock enable functionality. A group of programmable logic regions may have shared input selection circuitry that selects register control signals and produces delayed versions of the signals that are shared by the group. If desired, each programmable logic region may be provided with adjustable delay circuitry that individually adjusts control signal delay for registers of that programmable logic region.
US09660649B2	Voltage scaling for holistic energy management A method for scaling voltages provided to different modules of a system-on-chip (SOC) includes receiving, at an energy-performance engine of the SOC, a first indication of usage history for a first module of the SOC and a second indication of usage history for a second module of the SOC. The method includes receiving a battery life indication that indicates a remaining battery life for a battery of the SOC. The method also includes adjusting a first supply voltage provided to the first module of the SOC based on the first indication, the second indication, and the battery life indication. The method further includes adjusting a second supply voltage provided to the second module of the SOC based on the first indication, the second indication, and the battery life indication.
US09660644B2	Proximity switch assembly and activation method A proximity switch assembly and method for detecting activation of a proximity switch assembly is provided. The assembly includes a plurality of proximity switches each having a proximity sensor providing a sense activation field and control circuitry processing the activation field of each proximity switch to sense activation. The control circuitry monitors the signal responsive to the activation field and determines a differential change in generated signal, and further generates an activation output when the differential signal exceeds a threshold. The control circuitry further distinguishes an activation from an exploration of the plurality of switches and may determine activation upon detection of a stable signal.
US09660638B1	One wire parasite power switch control circuit A power switch control circuit is provided for power management in one-wire application. The circuit comprises a controllable switch coupled between an input node and an internal power node. A comparator is utilized for power loss sensing to close the switch when necessary to minimize the power loss while the input is low or floating. A watchdog circuit is incorporated within the control circuit to pull down the input node periodically to detect small leakage current when the input node is floating.
US09660637B1	Driving circuit and driving method A driving circuit configured to control at least one switch element is disclosed in the present disclosure. The driving circuit includes a first voltage generating circuit, a second voltage generating circuit and a driving voltage generating circuit. The first voltage generating circuit is configured to generate a first voltage signal. The second voltage generating circuit is configured to generate a second voltage signal. The driving voltage generating circuit is electrically coupled with the first voltage generating circuit and the second voltage generating circuit. The driving voltage generating circuit outputs at least one driving voltage signal according to the first voltage signal and the second voltage signal. The at least one driving voltage signal comprises three levels. At least one level of the levels is lower than zero level.
US09660636B2	Drive device A drive device includes: an on-side circuit turning on a power switching element; an off-side circuit turning off the power switching element; and a protection circuit controlling a gate current of the power switching element. The protection circuit includes: a constant-current circuit that defines a constant current for drawing a gate charge of the power switching element; a protection switch that controls electrical connection between the constant-current circuit and the gate of the power switching element; and a collector current detector. The collector current detector turns off the on-side circuit to disconnect the power switching element from the main power supply, and turns on the protection switch after a predetermined time has elapsed from when the current value of the collector current of the power switching element exceeds a first threshold.
US09660632B1	Adjustable time duration for driving pulse-width modulation (PWM) output to reduce thermal noise Noise introduced in an output signal of a pulse-width modulator (PWM) may be reduced by changing the time duration that a switch is driving the output node. Because the power supplies coupled to the switches are the source of noise in the output signal of the PWM, the time duration that the power supplies are driving the output may be reduced to obtain a subsequent reduction in noise in the output signal. For example, when a small signal is desired to be output by the PWM, the switches may be operated for shorter time durations. Thus, the switches couple the noise sources to ground for a duration of a cycle to reduce contribution of noise to the output. But, when a larger signal is desired to be output by the PWM, the switches may be operated for longer time durations or the conventional time durations described above.
US09660631B2	Duty cycle detection circuit and method A duty cycle detection circuit may include: a timing signal generation unit to generate a plurality of timing signal groups by selectively combining multi-phase clock signals according to an enable signal; and a detection unit to generate a duty detection signal by selectively combining signals of the plurality of timing signal groups according to the enable signal.
US09660627B1	System and techniques for repeating differential signals Techniques and devices for differential signal repeating are described. A differential signal repeating method may include receiving an input differential signal pair including first and second input signals received at first and second input terminals, respectively, and generating an output signal at an output terminal. Generating the output signal may include: based on a determination, at a first time, that the first and second input signals represent complementary values, setting a level of the output signal to represent an inverse of the value represented by the first input signal, and based on a determination, at a second time, that the first and second input signals do not represent complementary values, placing the output terminal in a high-impedance state.
US09660626B2	Implantable medical device having clock tree network with reduced power consumption An integrated circuit includes a clock tree network that distributes a clock signal to a plurality of clocked components of the integrated circuit. The clock tree network includes clock lines, each of which includes a clock tree delay element that provides a modified clock signal that is provided to an individual one the clocked components. Among the plurality of clocked components, one or more of the clocked components provides a data signal to another one or more of the clocked components. The one or more clocked components are configured having a transmission duration for the data signal that is longer relative to a transmission duration of the modified clock signal of the receiving clocked component.
US09660625B1	Continuously tunable delay line An apparatus includes a first conductive path comprising a first set of inductive elements connected in series, a second conductive path comprising a second set of inductive elements connected in series, each inductive element of the second set of inductive elements inductively coupled to, and having a mutual capacitance with, a corresponding inductive element of the first set of inductive elements. In some embodiments, the apparatus further includes a first amplifier having an amplifier input and an amplifier output, the amplifier output electrically connected to a proximal end of the first conductive path or the second conductive path. The described apparatus delays a signal according to the gain of the input amplifier. A method that uses the described apparatus is also disclosed herein.
US09660623B1	Analog correlator based on one bit digital correlator A two input time domain correlator may perform analog correlation. In order to achieve high throughput rates with reduced or minimal computational overhead, the input data streams may be hard limited through adaptive thresholding to yield two binary bit streams. Correlation may be achieved through the use of a Hamming distance calculation, where the distance between the two bit streams approximates the time delay that separates them. The resulting Hamming distance approximates the correlation time delay with high accuracy.
US09660621B1	Large dynamic range analog signal conditioning method and device with active accuracy enhancement An analog signal conditioning device and method employing a multi-path feedback mechanism to actively minimize the error of the overall desired signal conditioning transfer function to produce a corrected output signal, initially and over temperature, by exploiting characteristics of resistances manufactured simultaneously on a common thermally conductive substrate.
US09660620B1	Dual-edge trigger clock gater Techniques are disclosed relating to dual-edge triggered clock gater circuitry. In some embodiments, an apparatus includes dual-edge triggered clock gater circuitry configured to generate an output signal based on an input clock signal and a control signal that indicates whether to gate the input clock signal. In some embodiments, the clock gater circuitry includes first and second storage elements. In some embodiments, the clock gater circuitry includes multiplexer circuitry that selects between outputs of the first and second storage elements to generate the output signal. In some embodiments, the clock gater circuitry includes a third storage element configured to store an indication of which of the first and second storage elements stores a first digital value and which stores an inverse of the first digital value when not gating. In some embodiments, the clock gater circuitry includes a buffering element configured, when gating, to copy data stored in one of the first and second storage elements to the other of the first and second storage elements.
US09660619B2	High voltage pulse generator The present invention relates to a high voltage pulse generator which can operate for a long time and has high pulse frequency. In the preferred embodiment of the invention, the air stored in the air container is transmitted to the air duct by means of a hose over the regulator that adjusts the pressure and flow rate of the air. The air given into the air duct blows into the chamber through the nozzles. Then, this air is taken into this air duct by means of the nozzles placed on the other air duct and is transferred to the outer environment over an exhaust valve placed under the air duct. The air coming from the air container takes the place of the removed air.
US09660617B2	Semiconductor apparatus A semiconductor apparatus includes a pipe input/output signal generation block configured to generate a plurality of pipe input signals and a plurality of pipe output signals according to a pipe enable signal, and be initialized according to an error detection signal; a pipe latch group including a plurality of pipe latches, each of the plurality of pipe latches being configured to receive and store an input signal according to a corresponding pipe input signal and output a stored signal as an output signal according to a corresponding pipe output signal; and an error detection block configured to generate the error detection signal according to a pipe end signal, the pipe enable signal, the plurality of pipe input signals and the plurality of pipe output signals.
US09660610B2	Crystal device and mounting arrangement A crystal device has a crystal blank, a first excitation electrode part which is provided on an upper surface of the crystal blank, a first wiring part which extends from the first excitation electrode part to an edge part of the upper surface, a first lead-out terminal which is provided at the edge part of the upper surface of the crystal blank, a first mounting terminal which is provided at a position facing the first lead-out terminal, a first connection part which is provided so that one end is superimposed on the first lead-out terminal and the other end is superimposed on the first mounting terminal, a substrate having a mounting pad which is provided on its upper surface, a conductive adhesive which is provided between the mounting pad and the first mounting terminal, and a lid which is bonded to the upper surface of the substrate.
US09660609B2	Devices and methods related to stacked duplexers Devices and method related to stacked duplexers. In some embodiments, an assembly may include a first wafer-level packaging (WLP) device having a radio-frequency (RF) shield. The assembly may also include a second WLP device having an RF shield, the second WLP device positioned over the first WLP device such that the RF shield of the second WLP device is electrically connected to the RF shield of the first WLP device.
US09660604B2	Efficient passive broadband gyrator A gyrator for AC signals comprises a Hall effect material, means for coupling an alternating current (I1; I4) into the Hall effect material, means for permeating a Hall effect material with a magnetic field that is perpendicular to the plane or surface of the material, and means far converting a current (I3; I2), which was generated by the current I1 perpendicularly to the electric field generated by I1 in the Hall effect material, into an output voltage (U4; U1). A transformer is provided between at least one conductor loop (1a; 2a) made of a normal-conducting or semi-conducting material and at least one conductor loop (1; 2) made of the Hall effect material for coupling the current (I1; I4) into the Hall effect material and/or for converting the current (I3; I2) in the Hall effect material into the output voltage (U4; U1). It was found that eliminating an inefficient galvanic coupling of the Hall effect material to metallic or semi-conducting conductors minimizes the dissipative losses that occur during the conversion of the input current (I1; I4) into the output voltage (U4; U1). The gyrator can thus also be used for highly sensitive experiments in quantum information processing at low temperatures.
US09660603B2	Sloped termination in molybdenum layers and method of fabricating A method of fabricating a sloped termination of a molybdenum layer includes providing the molybdenum layer and applying a photo resist material to the molybdenum layer. The photo resist material is exposed under a defocus condition to generate a resist mask having an edge portion. The molybdenum layer is etched at least at the edge portion of the resist mask to result in a sloped termination of the molybdenum layer.
US09660597B2	Voltage supply for electrical focusing of electron beams A rapidly regulable high-voltage supply for the electrical focusing of an electron beam using a high-voltage final stage is provided. The high-voltage final stage includes a plurality of amplification elements that are interconnected in a series configuration with a first high-voltage connection, and a potential dividing chain including a series of potential dividing elements. The potential dividing chain is interconnected with the first high-voltage connection and has a signal interconnection with the plurality of amplification elements, so that when a voltage is applied across the potential dividing chain, a difference in voltages between a signal input to any amplification element of the plurality of amplification elements and a signal input to a next amplification element of the plurality of amplification elements has a same sign.
US09660596B2	Audio transducer stabilization system and method System and method for audio transducer stabilization comprising providing a sound generation panel for transmission of audio sound waves in response to a plurality of force inputs received from three or more audio transducers, providing a mounting frame for coupling to the sound generation panel, the mounting frame having three or more predefined locations for receiving audio transducers, placing the three or more audio transducers in the predefined locations, the predefined locations optimized to reduce a plurality of force moments when the audio transducers are driven using an input drive signal, connecting a coupler ring on each of the audio transducers placed in the predefined locations on the mounting frame to an outer surface of the sound generation panel, and driving each of the audio transducers using the input drive signal from an audio amplifier.
US09660595B2	Linear amplifier using nonlinear amplifying stage Disclosed herein is a linear amplifier using a nonlinear amplifying stage which includes a first amplifier and a second amplifier connected in cascade, including: a bias voltage generator in which a first bias voltage is applied to a gate terminal of the first amplifier, and a second bias voltage higher than the first bias voltage is applied to a gate terminal of the second amplifier, wherein the first amplifier and the second amplifier have a nonlinear gain characteristic in a region of arbitrary output power, and as the output power increases in the region of arbitrary output power, a gain of the first amplifier increases, while a gain of the second amplifier decreases.
US09660581B2	Oscillation circuit, electronic apparatus, moving object, and method of adjusting oscillation circuit An oscillation circuit includes a circuit for oscillation, a first frequency adjustment circuit for adjusting a frequency, and a first terminal. The oscillation circuit has a first mode in which the circuit for oscillation and the first frequency adjustment circuit are electrically connected to each other and the first frequency adjustment circuit and the first terminal are not electrically connected to each other, and a second mode in which the circuit for oscillation and the first frequency adjustment circuit operate and a terminal on a side where a signal of the first frequency adjustment circuit is output and the first terminal are electrically connected to each other.
US09660580B2	Synchronous buck inverter A power inverter, such as a synchronous buck power inverter, that is configured with a high frequency switching control having a (PWM) controller and sensing circuit. Controller provides a low frequency oscillating wave to effect switching control on a synchronous-buck circuit portion that includes a plurality of switches to invert every half cycle of the frequency provided by controller. The inverting process thus creates a positive and negative transition of the oscillating wave signal. A low frequency switching stage includes a further plurality of switches configured to operate as zero voltage switching (ZVS) and zero current switching (ZCS) drives Charge on an output capacitor is discharged to zero on every zero crossing of low frequency switching stage and advantageously discharges energy every half cycle. During this discharge of energy, the zero crossing distortion in the low frequency sine wave is greatly reduced.
US09660579B2	Voltage controlled oscillator with a large frequency range and a low gain A circuit includes a voltage controlled oscillator (“VCO”) having a VCO cell. The VCO cell includes a first transistor and a second transistor. The first transistor has a gate terminal coupled to a first node that also is coupled to a low-pass filter from which the gate terminal receives a first control voltage signal. A second terminal of the first transistor is connected to a first voltage source. The second transistor has a gate terminal coupled to a second node that is disposed between a capacitor and a resistor of the low pass filter. The second transistor has a second terminal connected to the first voltage source. The second transistor is larger than the first transistor, and the VCO has an output terminal for providing an output frequency signal.
US09660574B2	System and method for adjusting notifications for solar monitoring systems The invention includes a system and method for characterizing and monitoring photovoltaic power systems, and more particularly, to solar monitoring systems that provide notification of fault and performance conditions. Mistaken fault conditions causing false alarms are corrected by use of current weather conditions and performance data to adjust fault detection algorithms and control features.
US09660570B2	Clamps for securing solar energy panels Clamp assemblies for mounting solar panels and accessories. Clamp assemblies can have geometric features, shaped apertures for fasteners, and measured protrusions for allowing clamp rotation, lateral adjustment, self-alignment, and angled surfaces for facilitating installation of a solar panel.
US09660568B2	Solar array column cap Disclosed herein is a solar array column cap that includes a body having an opening extending along a center axis from a bottom to a top, the opening configured to receive the vertical column such that the body surrounds the vertical column. The solar array column cap further includes an upper support surface configured to receive a horizontal beam, the upper support surface being located in a plane that is visibly non-perpendicular with the center axis.
US09660566B2	Motor control method and motor control device A system has an acceleration region SU and a deceleration region SD between operation start and end positions of a wiper arm. In the acceleration region and the deceleration region, an addition amount and a subtraction amount are calculated, respectively, based on a difference between a maximum rotation speed and a current rotation speed to update a target rotation speed. The addition amount is larger than the subtraction amount, and a constant speed region CV is between the acceleration region SU and the deceleration region SD. When a change amount of an operation angle of the wiper arm does not exceed the constant speed region CV, the operation angle change amount is subtracted from the constant speed region. Further, when the operation angle change amount exceeds the constant speed region CV, the target rotation speed is updated by the same change amount.
US09660565B2	Controller for controlling a motor A controller in an electric power steering system controls motor that assists a steering operation of a steering wheel by a driver by generating an assist torque. The controller includes an instruction calculator calculating a base assist instruction value and at least one of correction instruction values, a distributor distributing the instruction values a plurality of winding wire groups, and calculating a torque instruction value for each of the plurality of winding wire groups. Thus, the base assist instruction value and the correction instruction values are appropriately distributed to each of the plurality of winding wire groups, for an appropriate distribution of the instruction values among the plurality of winding wire groups for generating the assist torque.
US09660564B2	Optimized control for synchronous motors Representative implementations of devices and techniques provide optimized control of a three-phase AC motor. A field oriented control (FOC) arrangement uses optimization components and techniques to improve power efficiency of the motor, with fast control response over a full range of motor speeds.
US09660559B2	Brushless motor and wiper apparatus A brushless motor comprises: a stator 21 having armature coils 21a, 21b, and 21c; a rotor 22 which is rotated by a revolving magnetic field; and a switching element 30a, wherein the brushless motor has a rotation number control unit 33 which switches between low-speed and high-speed mode, wherein in the low-speed mode, the rotation number control unit 33 supplies current to the armature coils 21a, 21b, and 21c at predetermined energization timing and controls a duty ratio to control the rotation number of the rotor 22, and in the high-speed mode, the rotation number control unit 33 supplies current to the armature coils 21a, 21b, and 21c at energization timing advanced from the energization timing for the low-speed mode, thereby performing field weakening control of weakening the revolving magnetic field from that of the low-speed mode to control the rotation number of the rotor 22.
US09660557B2	Electrostatic chuck and method for manufacturing the electrostatic chuck An electrostatic chuck includes a pedestal part formed of metal and including a gas passage, an insulation substrate mounted on the pedestal part and including a first surface facing the pedestal part and a second surface on an opposite side of the first surface, the first surface including a first hole part communicating with the gas passage, the second surface including a second hole part having a bore diameter less than that of the first hole part and communicating with the first hole part, and an insulation flow part formed of an insulating material and including a first end provided in the first hole part and a second end provided in the gas passage. The insulation flow part is configured to allow a gas supplied from the gas passage to flow into the second hole part.
US09660554B2	Method for making a capacitive micromachined ultrasonic transducer A method as disclosed makes a capacitive micromachined ultrasonic transducer (cMUT). The method forms a pattern of standing features on a substrate to serve as support walls in the cMUT being made, and further makes a patterned trench from the front side into the substrate at selected locations where separation boundaries of neighboring elements of the cMUT are located. In the process of completing the transducer elements of the cMUT, the method forms a covering layer over the patterned trench to at least temporarily cover the patterned trench. The covering layer seals the patterned trench to prevent other materials from entering during at least a part of the fabrication process.
US09660551B2	Operating point optimization with double-base-contact bidirectional bipolar junction transistor circuits, methods, and systems The present application teaches, inter alia, methods and circuits for operating B-TRANs (double-base bidirectional bipolar junction transistors). Base drive circuits provide high-impedance drive to the base contact region on whichever side of the device is (instantaneously) operating as the collector. (B-TRANs, unlike other bipolar junction transistors, are controlled by applied voltage, not applied current.) Control signals operate preferred drive circuits, providing diode-mode turn-on and pre-turnoff operation, and a hard ON state with a low voltage drop (the “transistor-ON” state). In some (not necessarily all) preferred embodiments, a self-synchronizing rectifier circuit provides an adjustable low voltage for the gate drive circuit. Also, in some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while monitoring the base current at that terminal, so that no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in B-TRANs.
US09660550B2	Generator device for the voltage supply of a motor vehicle A generator device for the voltage supply of a motor vehicle is equipped with at least one rectifying element for rectifying an alternating voltage provided by a generator. The rectifying element has an n-channel MOS field-effect transistor in which the gate, the body area, and the source area are electrically fixedly connected to one another and in which the drain area is used as a cathode.
US09660548B2	Rectification device for improved short-circuit protection A rectification device equipped with: a rectification circuit wherein switch elements are on the two sides adjacent to the side of an AC power source on which a feedback current flows, and the other two sides are rectification elements; an input voltage detector; an input current detector; and a control circuit that modulates the pulse width to control the switch elements in response to the difference between the input current and an input current target value generated on the basis of a synchronized sine wave synchronized with the input voltage. When the polarity of the input voltage, the input current, or the synchronized sine wave differs from the polarity of the other two, the two switch elements are switched simultaneously. Thus, it is possible to prevent circuit damage in the rectification device and to reduce the power factor even when there is a possibility of short-circuiting in the AC power.
US09660546B2	Coil structure and power converter A coil structure includes: a magnetic core that defines a closed loop magnetic path in which a magnetic flux flows, the magnetic core including a core leg; a coil that is wound around the core leg about a coil axis extending in a first direction, the coil generating the magnetic flux; a detour member that is separate from the magnetic core, the detour member defining a detour magnetic path that detours around the closed loop magnetic path between first and second points, the detour member including a first piece that defines the first point and a second piece that defines the second point; and a fixing portion that includes an adjoining member adjoining the core leg and a connecting portion connecting at least one of the first piece and the second piece to the adjoining member and fixes positional relations among the core leg and the first and second points.
US09660543B2	Electric power conversion circuit system An electric power conversion circuit system for reducing core loss in a transformer particularly during light loading and improving conversion efficiency during light loading comprising an electric power conversion circuit composed of a primary side conversion circuit having a left arm and a right arm and a secondary side conversion circuit having a left arm and a right arm, and a control circuit for controlling switching of switching transistors of the first side conversion circuit and the secondary side conversion circuit. When the output voltage is at a relatively light load, the control circuit controls to change the duty of the transmitting side among the primary side conversion circuit and the secondary side conversion circuit and controls to change the half-bridge phase differences of the left arm and the right arm of the primary side conversion circuit and the secondary side conversion circuit, respectively.
US09660541B2	Switching power supply device A switching power supply device includes a switching control circuit that generates a switching control signal such that a desired output voltage is generated from an input voltage, a drive circuit that turns on/off an output transistor in accordance with the switching control signal, and an on-pulse stop circuit that generates a pulse stop signal such that the number of ON pulses of the switching control signal is reduced in a state where a load is heavier than a first threshold but is lighter than a second threshold.
US09660540B2	Digital error signal comparator A digital error feedback system, method and device adjusts the output voltage of a power converter. The digital error feedback system uses a digital comparator and one or more digital signal generators to generate and compare a digital signal corresponding to the output voltage to a reference digital signal in order to determine the current amount of error in the output voltage. The error is then able to be compensated for using a control signal generated based on the determined error.
US09660539B2	Switching power supplies, and switch controllers for switching power supplies A switching power supply includes a power converter which includes a transformer and a switch, a current sensor, a switch controller and a compensation resistor. The current sensor is operable for generating a current monitoring signal indicating a current through a primary winding of the transformer. The switch controller is operable for receiving a feedback signal indicating an output voltage of the power converter, generating a driving signal based on the feedback signal to control an input power and an output power of the transformer, receiving a line voltage signal indicating an input voltage of the power converter, and generating a compensation current corresponding to a peak value of the line voltage signal. The compensation resistor is coupled between the current sensor and the switch controller. A voltage of the current monitoring signal is inversely proportional to the input voltage under control of the compensation current and the compensation resistor.
US09660534B2	Control circuit for multiphase switching converter to reduce overshoot and associated control method A multiphase switching converter having a plurality of switching circuits and a control circuit, the plurality of switching circuits provide an output voltage, the control circuit provides a plurality of switching control signals to turn ON the plurality of switching circuits successively based on the output voltage and a reference signal, when the output voltage is detected overshooting, the control circuit turns OFF a current switching circuit, and when the output voltage is detected recovering from overshooting, the control circuit turns ON the current switching circuit again for a first time period until a sum of the first time period and a second time period achieves a predetermined value, wherein the second time period is a time period the current switching circuit maintains ON uninterruptedly before the output voltage is detected overshooting.
US09660533B2	Buck-boost converter with smooth transition circuits and methods A buck-boost converter with smooth transitions is disclosed. A buck-boost converter controller is disclosed including a first high side driver switch gate control signal output for controlling a first high side driver device; a first low side driver switch gate control signal output for controlling a first low side driver device; a second high side driver switch gate control signal output for controlling a second high side driver device; a second low side driver switch gate control signal output for controlling a second low side driver device; a state machine having four states comprising a buck state, a boost state, a transition buck state, and a transition boost state; a hysteresis timer indicating a pulse width greater than a predetermined threshold coupled to the state machine; and a minimum timer indicating a pulse width less than a predetermined threshold coupled to the state machine. Methods are also disclosed.
US09660532B2	Package systems including passive electrical components A converter includes a plurality of active circuitry elements over a substrate. The converter further includes a passivation structure over the plurality of active circuitry elements, the passivation structure having at least one opening that is configured to expose at least one electrical pad of each active circuitry element. The converter further includes a plurality of passive electrical components over the passivation structure, wherein each passive electrical component is selectively connectable with at least one other passive electrical component, and a first side of each passive electrical component is electrically coupled to an electrical pad of each of at least two active circuitry elements. The converter further includes a plurality of electrical connection structures, wherein a first electrical connection structure electrically couples an electrical pad of a first active circuitry element to a corresponding passive electrical component, and the first electrical connection structure is completely within the passivation structure.
US09660531B1	System and method for improving efficiency for quasi-square wave power converters A power converter includes a power stage having a switch-node of a switched-mode power supply that is coupled to an input voltage node by a power field-effect transistor (FET) to energize an inductive circuit and is coupled to a ground node by a synchronous rectifier in parallel with the inductive circuit. The power converter also includes a controller coupled to the power stage. The controller controls switching of the power FET and synchronous rectifier in a complimentary manner. The controller switches on the power FET during a first switching cycle. Subsequently, the controller switches on the synchronous rectifier and, in response to a current through the inductive circuit being approximately zero, switches off the synchronous rectifier. Subsequently, the controller switches on the synchronous rectifier again to generate a negative current through the inductive circuit prior to entering a second switching cycle.
US09660526B2	Voltage converter having adjustable driving signal frequency Systems, circuits, devices and methods related to voltage converters. In some embodiments, a control system for a voltage converter can include a driving unit configured to generate a driving signal having a pulse width and a frequency. The driving signal is provided to a voltage conversion circuit to control conversion of an input voltage into an output voltage. The control system can further include a modulation unit configured to modulate the pulse width of the driving signal based on the output voltage to thereby allow adjustment of the output voltage. The control system can further include a control circuit configured to adjust the frequency of the driving signal based on the modulated pulse width. Such a control system can be useful in situations such as when the output voltage is close to the input voltage, or when a load being driven by the output voltage is relatively low.
US09660525B2	Three-D power converter in three distinct strata A switching power supply in an integrated circuit, an integrated circuit comprising a switching power supply, and a method of assembling a switching power supply in an integrated circuit are disclosed. In one embodiment, the invention provides a three-dimensional switching power supply in an integrated circuit comprising a device layer. The switching power supply comprises three distinct strata arranged in series with the device layer, the three distinct strata including a switching layer including switching circuits, a capacitor layer including banks of capacitors, and an inductor layer including inductors. This switching power supply further comprises a multitude of connectors electrically and mechanically connecting together the device layer, the switching layer, the capacitor layer, and the inductor layer. The switching circuits, the capacitors and the inductors form a switching power supply for supplying power to the device layer.
US09660524B2	System and method for estimating output current of DC-DC converter A DC-DC converter and a method for estimating output current of a DC-DC converter are provided. The method includes measuring, by a controller, input voltage and output voltage of the DC-DC converter and measuring output voltage of a current transformer (CT) included in the DC-DC converter. In addition, the method includes compensating, by the controller, for the output voltage based on the relationship between the measured output voltage and CT output voltage and compensating for the input voltage by measuring the input current of the DC-DC converter based on the output current of the DC-DC converter into the CT output voltage converted through the current transformer and using an output current map composed of the output voltage and the measured CT voltage. In addition, the output current is estimated using the compensated output voltage and input voltage.
US09660518B2	Switching converter A switching converter in which deterioration and breakage can be suppressed is provided. A switching converter whose area can be reduced is provided. The switching converter includes a switch connected to a power supply portion; a transformer connected to the power supply portion; a first rectifying and smoothing circuit and a second rectifying and smoothing circuit each connected to at least the transformer; and a switching control circuit which is connected to the first rectifying and smoothing circuit and the second rectifying and smoothing circuit and which controls operation of the switch. The switching control circuit includes a control circuit controlling on/off of the switch and operation of a starter circuit; and the starter circuit controlling startup of the control circuit. The starter circuit includes a transistor and a resistor each including a wide-gap semiconductor.
US09660517B2	DC-AC conversion device, control circuit controlling operation of DC-AC conversion device, and control method for controlling operation of DC-AC conversion device Provided is a DC-AC conversion device capable of reducing ripple current output from a battery.A DC-AC conversion device, including a DC-DC conversion circuit having a full bridge circuit, a DC-AC conversion circuit converting DC voltage output from the DC-DC conversion circuit into AC voltage, a coil with one end connected to one DC terminal of the DC-DC conversion circuit, and a capacitor connected between the other end of the coil and the other DC terminal, comprises: a short-circuit control part controlling switching so that a leg of the full bridge circuit is temporarily short-circuited; a phase reverse control part controlling switching of the full bridge circuit so that a phase of AC voltage output from the full bridge circuit is reversed, after the leg of the full bridge circuit is temporarily short-circuited; and a short-circuit duration variation part varying a duration for which the leg of the full bridge circuit is short-circuited at a specific cycle according to a cycle of AC voltage output from the DC-AC conversion circuit.
US09660515B1	Control method and control device for reducing second-order ripple A control method for reducing second-order ripple is adapted to reduce second-order ripple on an input side of a DC-DC conversion device, wherein the input side of the DC-DC conversion device is coupled to a preceding voltage supply device, and an output side of the DC-DC conversion device is coupled to a DC-AC transforming device, characterized in that a voltage control device for controlling the preceding voltage supply device is designed according to a transfer function, and the transfer function is adjusted and controlled with an output voltage of the DC-DC conversion device and an amplitude voltage of pulse width modulation to reduce second-order ripple of an input voltage input to the input side of the DC-DC conversion device, thereby dispensing the need to increase circuits or increase capacitance of components and cutting costs.
US09660512B2	Electronic device for acquiring specific information of respective switching elements There is provided an electronic device comprising: a plurality of switching elements connected to a power supply; a plurality of specific information storage units provided for the corresponding switching elements and configured to store specific information of respective corresponding switching elements; a processing unit configured to control the switching elements; and a communication line disposed between the specific information storage units and the processing unit, through which the specific information of the respective switching elements is sent from the specific information storage units to the processing unit.
US09660510B2	Voltage converter for a motor vehicle The invention relates to a voltage converter (1) for a motor vehicle. Said voltage converter (1) comprises a transformer (10) and a power output stage (7). The power output stage (7) comprises at least two semiconductor switches (20, 22, 24, 26) that are connected to the transformer (10), in particular to a primary winding (12) of said transformer (10). The voltage converter (1) has a driver stage (31) which is connected, on the output side, to a control connection of the semiconductor switch (20, 22, 24, 26) and which is designed to actuate said semiconductor switch (20, 22, 24, 26) using a control signal (93, 94), for the purpose of generating an alternating voltage. According to the invention, the driver stage (31) is connected, on the input side, to a pulse signal generator (35) and an input capacitor (60, 62). The pulse signal generator (35) is designed to generate a pulse signal (37, 38) and to actuate the driver stage (31) using the pulse signal (37, 38) in order to generate the control signal (93, 94). For at least one incipient half-wave of the alternating voltage, the pulse signal (37, 38) has at least one prepulse and one main pulse that generates the half-wave, the prepulse being designed to preload the input capacitor (60, 62) of the driver stage (31) such that complete switching of the semiconductor switch (20, 22, 24, 26) can occur more quickly than it could without a prepulse.
US09660503B2	Rotating electric machine including a cooling device for cooling a fluid in the rotating electric machine A cooling device mounted in the interior of a frame of a rotating electric machine is configured in such a manner that at least one of the end-face portions between a first end-face portion through which a cooling fluid flows into the cooling device and a second end-face portion from which the cooling fluid flows out thereof is placed tilting with respect to a minimum-width's direction of a frame's internal flow-path in vicinity to the cooling device, or with respect to at least one of an inflow direction and outflow direction of the cooling fluid.
US09660502B2	Cooling system for electric motor with internal shaft passage and cooling medium reservoir A motor includes: a shaft to which a rotor is attached and having an internal cooling medium passage in an inside of the shaft, a cooling medium passing through the internal cooling medium passage; a housing including the shaft disposed therein and configured to rotatably support the shaft; and a cooling medium reservoir provided in the housing and provided on an upstream side of an inlet of the internal cooling medium passage in a flowing direction of the cooling medium, the cooling medium reservoir being configured to store the cooling medium and then flow the cooling medium to the internal cooling medium passage.
US09660499B2	Compressor having biased controlled magnetic bearings A stator is provided which exerts a combined electromagnetic force of a plurality of electromagnets on a drive shaft having a fluctuating load. A controller is provided which controls a current difference between a first coil current passed through a coil of the electromagnet generating an electromagnetic force in a direction opposite to that of the load and a second coil current passed through a coil of the electromagnet generating an electromagnetic force in the same direction as that of the load to perform a position control on the drive shaft. The controller adjusts the second coil current to reduce an average value of the second coil current.
US09660490B2	Permanent magnet type motor and method for manufacturing permanent magnet type motor Provided is a permanent magnet type motor capable of improving a demagnetization proof stress almost without lowering a generated torque, and reducing a torque ripple and a cogging torque by improving a gap magnetic flux density distribution. Portions having a low demagnetization proof stress of a plurality of permanent magnets incorporated into a rotor core are partially and equally demagnetized.
US09660485B2	Methods and apparatus for electronic device power Improved mechanisms for automated control of harvested energy delivery are described. A device harvests and stores energy and activates a controller when a sufficient level of stored energy is achieved. The controller retrieves previous power-off state information determines status information, and activates and powers a powered device. Just before insufficient energy remains to power the powered device, the controller stores shutdown status information and enters a power-off state.
US09660484B2	Power distribution unit inrush current monitor and method for protecting an uninterruptible power supply from inrush current A power distribution unit (PDU) inrush current monitor (PICM) may be used to protect an uninterruptible power supply (UPS) from an inrush current from a PDU. In general, the PICM senses a power condition of the PDU (e.g., energized or de-energized) and places the UPS in the appropriate operational state or mode (e.g., a stop mode or a run mode) to avoid an inrush current to the UPS when the PDU is powered on and energized. The PICM thus protects the UPS while allowing the UPS to operate when needed. In one embodiment, the PICM provides a stop signal to the UPS to place the UPS into a stop mode while the PDU is de-energized and provides a run signal to the UPS to place the UPS into a run mode after the PDU is energized.
US09660481B2	Wireless charger assembly mountable on different desks A wireless charger assembly is used for transferring power to an electronic device through inductive charging. The wireless charger assembly includes a bottom case releasably mounted to an exterior flatbed, a transmitter coil, and a top case. The transmitter coil transmits power to a receiver coil of the electronic device through inductive charging. The top case has a working platform mounted around the working surface of the flatbed, a neck portion extending downwardly from the working platform, and a slot defined by the working platform and the neck portion. The neck portion releasably retained to the closed loop wall.
US09660475B2	Control circuit for reducing charging time and method thereof A control circuit for reducing a charging time and a method thereof are provided. The charging device includes an input unit configured to receive a control signal indicating that applied power is process power, and a switch configured to cut off a path between a terminal set and a battery while the process power is applied, when the applied power is the process power.
US09660474B2	Energy storage system with green maintenance discharge cycle An energy storage system with an energy storage cell coupled to a battery management system provided with a charge control circuit, a discharge control circuit and a maintenance discharge control circuit. The maintenance discharge control circuit including a voltage booster coupled to a constant current/constant voltage (CC/CV) regulator. Each of the charge control circuit, the discharge control circuit and the maintenance discharge control circuit are coupled between the battery management system and a host power rail. The voltage booster is operable to raise a voltage from the energy storage cell to a CC/CV regulator input voltage greater than a voltage of the host power rail, enabling the CC/CV regulator to provide a selected maximum voltage and corresponding maximum current to the host power rail during a maintenance discharge cycle of the energy storage cell.
US09660471B2	Arrangement for and method of dynamically managing electrical power between an electrical power source and an electrical load Electrical power is dynamically managed among one or more power sources and one or more loads. A plurality of monitor nodes is connected to an input terminal connected to each source, and to an output terminal connected to each load. A plurality of electrical power storage cells is connected among the input and output terminals, each cell being capable of storing power from at least one of the sources and being capable of discharging stored power to at least one of the loads. A plurality of controllable switches is connected to the cells. Master and slave controllers dynamically monitor operating conditions at the monitor nodes during operation of each source and each load, and selectively dynamically control the switches to interconnect the cells in different circuit topologies in response to the monitored operating conditions.
US09660467B2	Portable powerbank with integrated promotional-video capabilities and methods of use The inventive disclosures contained herein are generally directed to an improved portable powerbank (or battery bank) that is integrated with video storage and playback/display capabilities for use as a promotional product and/or related services. Effectively, the improved device is an electronic billboard and/or video player that can keep a user engaged because of a user's motivation to use the powerbank functionality. The combination of the improved powerbank's high user utility with the integrated video/audio player's strong capability in communicating promotional messages, the VIP significantly elevates the promotional effectiveness of each VIP device, as compared with the individual parts of the sum. The VIP incorporates control logic that implements strategic algorithms that are designed to enable or disable certain functional capabilities of the VIP in order to encourage end-users to actually watch/listen to promotional video and/or audio media for a predetermined minimum number of VIP operational cycles.
US09660466B2	Tablet and monitor support systems Support systems and related methods for supporting tablets and monitors. A stand that includes a monitor support portion configured to support a monitor and a tablet support portion configured to support a tablet.
US09660464B2	Battery pack, electrical hardware, and communication control method A battery pack has a communicator storing various communication protocols. When new hardware is connected thereto, the battery pack sequentially transmits a respective communication request signal to request communication with the hardware using a stored communication protocol, and establishes communication. The battery pack transmits the communication request signal using a standard such as a compatibility priority among communication protocols, a frequency priority for communication protocols used according to a history record, a communication speed priority for communication protocols, and so on, thereby achieving quick establishment of communication.
US09660463B2	Apparatus comprising power strip and battery An exemplary aspect comprises an apparatus, comprising: a cord component connected to a plug component at a first end; a power strip component connected to the cord component at a second end of the cord component; the power strip component comprising one or more USB dedicated charge ports and one or more AC outlets; a charging cavity within the power strip component suitable to receive a removable battery having a battery electrical contact; and a power strip electrical contact located in the charging cavity that connects with the battery electrical contact and charges the battery when the battery is inserted into the charging cavity of the power strip component.
US09660461B2	Charging assembly and charging control method A charging assembly and a charging control method are provided for charging a battery pack in a fast charging voltage value which is greater than the rated charging voltage value. The charging assembly includes a battery pack, a charger and a control system configured to control the charger to charge the battery pack with a constant charging current. The method includes: detecting the open-circuit voltage of each battery cell and screening out a maximum open-circuit voltage value, calculating a maximum charging duration and controlling the charger to charge the battery cell assembly with a constant current when the charging voltage is equal to the fast charging voltage value or reaches the maximum charging duration.
US09660460B2	Hybrid battery control A hybrid battery controller controls charging of a hybrid battery comprising at least two types of rechargeable cell and includes battery characteristic logic operable to determine at least two optimized charge profiles corresponding to the at least two types of rechargeable cell; power source characteristic logic that assesses operational characteristics of a charging power source; and adaptation circuitry that adapts the operational characteristics of said charging power source to perform optimized charging of the at least two types of rechargeable cell according to said at least two determined optimized charge profiles.
US09660458B2	Electrical load management Methods, systems, and apparatus, including computer programs encoded on computer storage media, for electrical load management. One of the systems includes a first electrical grid, one or more power sources coupled to the first electrical grid, a second electrical grid coupled to the first electrical grid by a power conversion system, one or more loads coupled to the second electrical grid, and one or more load control systems coupled to the one or more loads. A grid control system is configured to receive source information from the first electrical grid and send load instructions to the load control systems based on the source information.
US09660454B2	Apparatus and method for managing and conditioning photovoltaic power harvesting systems The efficiency of a PV power generation system (10) is maximized by an apparatus providing series of electronic units (20) connected to the PV modules (12) and comprising microprocessor controlled DC converters/power supply units. A managing unit (60) communicates with the electronic units (20) of a string (11) in order to carry out a synergic optimization of the efficiency both of the single PV modules (12) and of the entire string (11). The apparatus also provides PV module (12) by PV module (12) diagnostic features and it is able to communicate with external devices for a full system control.
US09660449B2	Power system sub-synchronous oscillation damper A control circuit for power system sub-synchronous oscillation dampening is described. The control circuit is configured to provide low impedance at sub-synchronous frequencies and high impedance at the fundamental frequency. The control circuit includes an input configured to receive a direct voltage value and a quadrature voltage value. Both the direct voltage value and the quadrature voltage value are based on a three-phase voltage. At least one controller configured to determine a direct current value and a quadrature current value based at least in part on the direct voltage value and the quadrature voltage value is included. The control circuit also includes an output configured to send the direct current value and the quadrature current value as feed forward signals to a control loop for the three-phase voltage.
US09660446B2	Power distribution system for an aircraft An aircraft power distribution system includes a first DC power distribution bus, a second DC power distribution bus, and a DC power source coupled with at least one of the first or second DC power distribution buses, wherein the DC power distribution buses are electrically coupled by a plurality of electrical couplings.
US09660441B2	Overvoltage protection for power systems Electrical protection devices, such as for use with power systems for overvoltage protection, are disclosed. One electrical protection device includes a first electrical connection, a second electrical connection, a first electrical discharge device, and a second electrical discharge device. The first electrical discharge device includes a first conductive bus connected to the first electrical connection and a second conductive bus connected to the second electrical connection. The first electrical discharge device has a first breakdown voltage. The second electrical discharge device includes a third conductive bus connected to the first electrical connection and a fourth conductive bus connected to the second electrical connection. The second electrical discharge device has a second breakdown voltage.
US09660437B2	Arrangement for forming a thermal isolation point The invention relates to an arrangement for forming a thermal isolation point, consisting of an isolation strip to which a prestressing force can be applied, an electrical means which produces thermal energy and has a contact surface, in particular in the form of an overvoltage protection element or a component of such an element, as well as an integral connection means, which changes when heated in a defined manner in the aggregate state, in particular a solder. According to the invention, an adapter part is provided between the isolation strip and the contact surface of the electrical means, wherein the adapter part can on the one hand be connected to the contact surface in a purely interlocking and/or force-fitting manner, and on the other hand is connected in a manner which can provide thermal isolation integrally to the isolation strip.
US09660435B2	Multi-directional electrical power protection system A multidirectional electrical power protection system, includes a first power supply and at least a second power supply with each supply being configured for supplying power to a main bus circuit; a first load bus electrically connected to the first power supply and at least the second power supply, at least a second load bus electrically coupled with each of the first power supply and at least the second power supply, the first load bus and the second load bus configured for energizing devices connected to the respective first and second load bus; and at least one smart contactor in coupled with the main bus circuit, the at least one smart contactor being configured for sensing a first current flowing in a first direction through the main bus circuit and for sensing a second current flowing in a second direction through the main bus circuit.
US09660433B2	Active lightning arrester The present invention relates to an arrester, comprising: a rod member coupled to a ground means at one end in the longitudinal direction and charged with charges of the ground; a plurality of insulators provided to be spaced from each other in the longitudinal direction of the rod member; an charging plates provided between the neighboring insulators separately from the rod member so as to be electrically insulated and charged with a polarity opposite to that of the charges of the ground; a charging tube provided between the charging plates and the insulators, electrically connected to the charging plates, and charged with charges having a polarity opposite to that of the charges of the ground; a needle electrode member provided to the upper end of the rod member and having a needle-shaped part; and a discharge induction conductor electrode electrically connected to the charging plates between the insulators and the charging plates so as to induce discharge between the needle electrode member and the discharge induction conductor electrode and emit ion charges through the discharge, thereby forming a discharge path between a thundercloud and the needle electrode.
US09660430B2	Configurable enclosure A configurable enclosure including a cover portion operably attached to a base portion, the base portion including a wall disposed along a perimeter of a bottom surface, and a removable portion of the bottom surface configured to be peeled away from the base portion to create an opening on the bottom surface is provided. Moreover, an enclosure having a cover portion operably attached to a base portion, the base portion including a wall disposed around a perimeter of a bottom surface, a thin section of the bottom surface located proximate an outer edge of a removable portion of the bottom surface, an actuator operably attached to the removable portion, wherein through actuation of the actuator, the removable portion peels away from the bottom surface to create an opening on the base portion is also provided. Furthermore, an associated method is also provided.
US09660423B2	Spark plug having an electrode structure that effectively suppresses flashover It is an object to reduce eccentricity between a terminal nut and an insulator. A spark plug includes an insulator, a terminal nut, and a metallic shell. The outside diameter of the insulator at a rear end of the metallic shell is smaller than or equal to 8 mm, and the contact area between a flat portion of the insulator and a contact surface of the terminal nut is smaller than 10 mm2.
US09660421B2	Dynamically-distributable multiple-output pump for fiber optic amplifier A multiple-output laser component is described with a plurality of diode lasers in a common package, each of the diode lasers having distinct electrical control and optically coupled to a distinct output fiber, the component configured such that up to a maximum total output power can be selectively and dynamically partitioned among said diode lasers. The dynamic allocation can be based on demand for laser power in a fiber optic coupled to each diode laser. The multi-output laser component can be used to drive amplifiers associated with a multicast switch in some embodiments.
US09660420B2	Laser diode A laser diode with an improved kink level in the L-I characteristic and capable of obtaining a stable high output in a horizontal transverse mode is provided. The laser diode includes an active layer made of nitride III-V compound semiconductor containing at least gallium (Ga) in 3B-group elements and at least nitrogen (N) in 5B-group elements, an n-type compound semiconductor layer provided on one of faces of the active layer, and a p-type compound semiconductor layer provided on the other face of the active layer. A region closest to the active layer, in the n-type compound semiconductor layer is a high-concentration region whose impurity concentration is higher than that of the other n-type regions.
US09660411B2	Tunable SOI laser A wavelength tunable silicon-on-insulator (SOI) laser comprising: a laser cavity including: a semiconductor gain medium having a front end and a back end, wherein a mirror of the laser cavity is located at the back end of the semiconductor gain medium; and a phase-tunable waveguide platform coupled to the front end of the semiconductor gain medium, the phase-tunable waveguide platform comprising: a first resonator and a second resonator; at least one resonator being a phase-tunable resonator; wherein the first resonator is any one of: an MMI device including a pair of reflective surfaces defining a resonator cavity therebetween such that the device is configured to act as a Fabry-Perot filter; a ring resonator; or a waveguide Fabry-Perot filter; and wherein the second resonator is any one of: an MMI device including a pair of reflective surfaces defining a resonator cavity therebetween such that the device is configured to act as a Fabry-Perot filter; a ring resonator; or a waveguide Fabry-Perot filter.
US09660405B2	Electrical device with low friction contact parts An electrical device including an electrode arrangement having a magnet, and an electrode, an electrically conducting movable device, movable relative to the electrode arrangement and spaced apart from the electrode arrangement, whereby a gap (G) is formed therebetween, and a suspension including a liquid, a plurality of magnetic particles dispersed in the liquid and a plurality of non-magnetic electrically conducting particles dispersed in the liquid, which non-magnetic electrically conducting particles have higher electric conductivity than the magnetic particles, wherein the suspension) extends between the electrically movable device and the electrode arrangement in the gap (G), and wherein the magnet is arranged to provide a magnetic field through the suspension to thereby align the non-magnetic electrically conducting particles between the electrode arrangement and the electrically conducting movable device to obtain an electrical connection between the electrode arrangement and the electrically conducting movable device.
US09660403B2	Connector for devices for creating mosaicked display systems, and display mosaic systems comprising same Discrete electronic modules, such as display tiles, designed and configured to be mosaicked and operatively connected with one another and/or to one or more differing types of discrete electronic modules. In some embodiments, the electronic modules include one or more recessed receptacles along their edges that receive corresponding connector biscuits that operatively connect abutting or confronting electronic modules with one another and/or to a controller. In some embodiments, the sizes of the recessed receptacles and connector biscuits are precisely matched so that the biscuits participate in aligning the abutting or confronting display tiles with one another. In some embodiments, the recessed receptacles are provided in recesses in the backsides of the display tiles, which allows each tile to be easily installed and removed from a display mosaic of which the tile is part.
US09660397B2	Plate for cable connector attachments A mounting system for facilitating ordered mating of plural connectors includes a bracket having at least one feature for securing to a pole or wall. A plate is connected to the bracket and includes plural mounting positions. Optional grounding and/or surge arrestors may be included. In a keying embodiment, each mounting position has an inner perimeter shape different than the inner perimeter shapes of the other mounting positions. Each connector of plural first connectors includes a threaded portion holding a first nut with an outer perimeter having a shape unique as compared to the first nuts of other first connectors. The outer perimeter of the first nut seats into one, and only one, of the plural mounting positions of the plate. Optionally, a second plate may be mounted to and spaced from the first plate. The second plate includes plural keyholes which are aligned to the plural mounting positions. Each keyhole has an inner perimeter shape matching the inner perimeter shape of the mounting position to which the keyhole is aligned. The keyholes only permit a second connector, with a matching key nut, to pass therethrough and mate into the first connector in the aligned mounting position.
US09660395B2	Terminal connection device having light source module Provided is a terminal connection device having a light source module that is installed at a front panel terminal for a vehicle and is capable of emitting light around the terminal, the terminal connection device including: a housing having an inner space and an opening part; a terminal part having a printed circuit board located at an inner side of the housing, and a terminal mounted to the printed circuit board; a housing cover sealing the opening part of the housing and protecting the terminal part; an LED light source mounted to the printed circuit board and adopted to radiate light to the housing cover; and a border lighting part located at the housing cover and arranged to face an edge of one end of the terminal, the border light part protruding from one surface of the housing cover.
US09660386B2	High frequency RJ45 plug with non-continuous ground planes for cross talk control There is provided a communication connector including a housing and a plurality of electrical contacts received by the housing. A printed circuit board (PCB) is provided and includes first and second pairs of electrically conductive signal traces on different layers of the PCB, each pair of the first and second pairs of traces being connected to a corresponding pair of the plurality of pairs of contacts; and at least one split ground plane including first and second sections being substantially electrically isolated from one another, wherein at least a portion of the first section is adjacent to at least a portion of the first pair of traces and at least a portion of the second section is adjacent to at least a portion of the second pair of traces.
US09660383B2	Connector with tuned terminal beam A connector assembly includes a housing with a card slot and includes terminals positioned in the card slot where the terminals are tuned to improve performance. The terminals include a contact, a tail and a body extending therebetween. The contacts can include a deflecting portion and a pad interface portion. The deflecting portion includes a dual beam portion and a single beam portion. The connector can be configured to provide a row of contacts positioned on both sides of a card slot.
US09660379B1	Vehicle electrical connector assembly and connection method An exemplary vehicle connector assembly includes, among other things, a first housing, and a second housing configured to selectively engage the first housing in a first position to accommodate a first take-out location. The first housing is further configured to engage the second housing in a second position to accommodate a second take-out location different than the first take-out location. An exemplary electrical connection method includes, among other things, securing a first housing of a connector to a second housing in a first position to accommodate a first take-out location. The first housing is securable to the second housing in a second position to accommodate a second take-out location instead of the first take-out location. The first position circumferentially offset from the second position.
US09660374B2	Sealed electrical connector for magnetic bearings An electrical connector providing a sealed electrical link between an inside environment subjected to corrosive gases or liquids under pressure and an outside environment of different pressure. The connector includes a connector body, conductor cables, a thermoplastic insulator, and a sealing element. The connector body is secured to a structure and includes insulating feed-throughs for receiving electrical contacts connecting an outside environment to an inside environment. The conductor cables, comprising an outer insulating layer made of a fusible thermoplastic material, are connected to said electrical contacts inside said inside environment. The thermoplastic insulator is secured to said connector body and surrounds the conductor cables. The thermoplastic insulator and cable outer insulating layers are made of a same type of fusible thermoplastic material making it possible, by localized fusion, to form a thermoplastic weld therebetween. The sealing element is mounted between the connector body and the thermoplastic insulator.
US09660372B2	Waterproof cable connector A waterproof cable connector includes a first cable terminal for transmitting or receiving electrical signals of a first cable to or from a second cable, a waterproof member combined with the first cable to perform a waterproof function of the first cable terminal, and a first fastener wrapping the first cable terminal and the waterproof member.
US09660365B2	Printed circuit board A printed circuit board includes at least two rigid printed circuit board parts which are connected to one another by at least one flexible connecting part which is thinner than the rigid printed circuit board parts. The at least two rigid printed circuit board parts can be moved toward one another by bending the flexible connecting part. A groove, which is produced by the different thickness of the rigid printed circuit board parts relative to the flexible connecting part, is filled with an elastic material.
US09660364B2	System interconnect for integrated circuits An electronic device for transmitting data is described herein. In some examples, the electronic device includes a package substrate, and a plurality of integrated circuits to be coupled to the package substrate, at least one integrated circuit comprising a topside connector or an edge connector to be coupled to a cable that is to couple to a cable receptacle.
US09660359B2	Automatic cable splice A cable splice includes a casing, a jaw assembly, a biasing member, a guide, and a bullet cup. The casing has an opening and an interior cavity. The jaw assembly is positioned in the interior cavity and moveable between a loading position and a terminated position. The biasing member biases the jaw assembly towards the terminated position. The guide includes a receiving end and a shaft extending at least partially into the interior cavity.
US09660355B2	Connection structure of external conductor terminal of electric cable A connection structure of an external conductor terminal for connection with an external conductor of an electric cable including the external conductor made up of twined cables enclosing an outer periphery of an insulating coating of one or more internal conductors and a protective coating covering the external conductor, wherein the external conductor terminal has a cylindrical connector portion connected to the external conductor and a terminal portion provided at one end of the connector portion; and the connector portion is fitted around a location on an outer periphery of the insulating coating where the external conductor is laid bare, the twined cables of the external conductor are provided in contact with an outer periphery of the connector portion, a ring member is fitted around outer peripheries of the twined cables and the twined cables are crimped.
US09660354B2	Aluminum electric wire connecting structure A connector includes a crimping portion (12) provided at an inner surface with projections (13) having inclined sides (19), the crimping portion (12) being provided with a combination of a base portion (14) and first and a second protruding portions (15) and (16) protruding from the base portion (14), the first protruding portion (15) having a distal end part (15a) located at an inside of a distal end part (16a) of the second protruding portion (16), the crimping portion (12) having a ring-shaped section perpendicular to a length direction of the aluminum electric wire (21), the projections (13) being projected into surface areas of the aluminum electric wire (21), with distorted regions formed along the inclined sides (19) in a surface part of the aluminum electric wire (21).
US09660351B2	Deployable antenna frame A multi-faceted deployable antenna frame including a six-bar linkage structure in a lateral facet of the antenna frame, the six-bar linkage structure being convertible from a folded state into a deployed state and having two first bars and four second bars, each bar being coupled to two others by a hinge to form a closed loop, where in the deployed state, the six-bar linkage structure has a quadrilateral shape. The antenna frame also includes a deployment means for deploying the antenna frame by moving the six-bar linkage structures from the folded state into the deployed state, the deployment means including: a flexible, elongated member of a substantially inextensible material; a first guiding means provided at an end portion of one of the first bars and coupled to the elongated member; a storage means provided at the first bar that includes the first guiding means for storing a part of the elongated member; a driving means that is coupled to the elongated member to pull the elongated member to the storing means when deploying the antenna frame; and a second guiding means between two adjacent second bars, the elongated member being coupled to the second guiding means. A first end of the elongated member is attached to the storing means and a second end of the elongated member is coupled to another first bar, and wherein the elongated member is extending between said first end and said second end along a plurality of second bars.
US09660348B2	Multi-function array for access point and mobile wireless systems A multi-function array is described where several communication system functions are realized using the same antenna architecture. An array of antenna elements where each antenna element can generate multiple radiation patterns is described; the multiple radiation patterns from each antenna element provides increased capability and flexibility in generating a phased array, a MIMO antenna system, a receive diversity antenna system, as well as direction finding feature by way of an interferometer function provided by one or multiple elements. The small volume attributes of the antenna elements populating the array lend this technique to mobile wireless devices as well as access points.
US09660347B2	Printed coupled-fed multi-band antenna and electronic system The disclosure is related to a printed coupled-fed multi-band antenna, and a related electronic system. The antenna includes a first antenna member structurally with a mushroom-shaped radiation portion and an antenna connection portion being electrically connected with a ground plane. The mushroom-shaped radiation portion is employed to activate first band electromagnetic wave. The antenna includes a second antenna member, which may be shaped as a U-shaped radiation portion. The second antenna member is floating within a region surrounded by the mushroom-shaped radiation portion, the antenna connection portion and the ground plane. The U-shaped radiation portion is coupled with both the ground plane and the mushroom-shaped radiation portion. The coupling effect allows the second antenna member to activate a second band electromagnetic wave. The multiple band signaling paths are formed over the printed antenna for application of a multi-band antenna.
US09660346B2	Antenna structure An antenna structure and an electronic device are provided. The antenna structure includes a connecting part, a grounding part, a first extending part and a second extending part. An angle is larger than zero between a first vector from the connecting point to the first open terminal and a second vector from the connecting point to the second open terminal. Also, a difference between the path length of a first path length and the path length of a second path length would be a quarter of the wave length of the radio frequency signal or a positive integer times thereof, so that the antenna is capable of receiving the radio frequency signal with circular polarizing.
US09660345B1	Millimeter-wave communications on a multifunction platform A millimeter-wave (MMW) communication system may include an antenna array structure operating within a MMW band, having both a first antenna coupling point and a second antenna coupling point, whereby the first and the second location of the antenna coupling points are within a coplanar surface on which the antenna array structure is formed. The system may further include a single MMW transmitter device having a power splitter that splits a data modulated MMW signal into a first MMW data modulated signal and a second MMW data modulated signal identical to the first MMW data modulated signal, such that the first data modulated MMW signal is coupled to the first antenna coupling point for radio propagation at a first direction, and the second data modulated MMW signal is coupled to the second antenna coupling point for radio propagation at a second direction.
US09660339B2	Beam steering and manipulating apparatus and method An apparatus and method for electromagnetic beam steering and manipulating employ narrow beams in close proximity. The beam width and distance between neighboring beams are arranged around or smaller than the wavelength. In an aspect, a strong beam is steered by a much weaker beam. In another aspect, a strong beam is focused by a small group of much weaker beams.
US09660334B2	Collapsible ground plane for satcom antenna A collapsible ground plane for a mobile UHF satcom antenna mounted on a riser comprises a hub and a plurality of conductive members, some of which extend radially from the hub with additional conductive members that extend peripherally between adjacent distal ends of the radially extending conductive members. Each conductive member is flexible so as to yield upon an impact, and return to its original shape when the impact is relieved.
US09660333B2	Radiator, solderless interconnect thereof and grounding element thereof A radiator includes an aperture plate defining multiple slots in first and second transverse directions, spring probes disposed within each of the multiple slots, printed circuit boards (PCBs) each having major and minor surfaces and being recessed on either side of multiple portions of one of the minor surfaces to define multiple pads plated with conductive pad material electrically interconnected with a PCB circuit and a grounding element. Each of the PCBs is disposed with the corresponding one of the minor surfaces inserted into a slot such that the PCBs form a crisscrossing pattern and the pads form horizontal blind-mate contacts with the spring probes that are in-plane with corresponding PCB planes. The grounding element is interposed between crisscrossing PCB pairs at complementary notches thereof.
US09660332B2	Antenna apparatus and feeding structure thereof Disclosed are an antenna apparatus and a feeding structure thereof. The feeding structure includes at least one feeding unit; at least one ground unit connected to the feeding unit; and a ground member connected to the ground unit, and the antenna apparatus includes the feeding structure. Thus, a plurality of signal transferring paths is formed in the antenna apparatus so that the operation efficiency of the antenna apparatus is improved.
US09660330B2	Quasi-fractal antenna The present invention provides to an antenna. The antenna includes a piezoelectric-substrate layer; and a quasi-fractal radiating layer disposed on the piezoelectric-substrate layer and having a quadrangle sub-structure and a similar structure that is formed by a nth-order self-similar iteration process including a trimming step, a scaling step and a combining step on the basis of the quadrangle sub-structure, where n is an integer greater than zero.
US09660326B2	Conductive loop antennas A antenna for a wireless device is provided. The antenna may include a dielectric substrate, a counterpoise disposed on the dielectric substrate, a first conductive element electrically connected to the counterpoise, and a second conductive element electrically connected to a feed point. The first conductive element may form at least a portion of a radiating loop resonant at a first frequency, and the second conductive element may form at least a portion of a radiating spur resonant at a second frequency higher than the first frequency. The antenna may further include a conductive frame constituting at least a portion of the radiating loop or the radiating spur.
US09660325B2	Sensor and measuring arrangement A sensor for liquid and/or gas analysis comprising a measuring transducer for producing a measurement signal, and, connected with the measuring transducer, especially separably, a compact transmitter, which is embodied for receiving and further processing the measurement signal. The compact transmitter includes: a transmitter housing; a transmitter circuit arranged in the transmitter housing; arranged in the transmitter housing, a first interface, via which the transmitter circuit is connectable by means of a connection cable with a first superordinated data processing system, especially one embodied as a superordinated control system; and arranged in the transmitter housing, a second interface, which connects the transmitter circuit with an antenna and which is embodied to supply the antenna with, or to receive by means of the antenna, a radio signal, whose center frequency has a wavelength λ. The antenna includes a radiating element and at least one metal mirror element, and wherein the radiating element has a length of λ/8 up to 3λ/8, especially of, for instance, λ/4.
US09660324B2	Hybrid piezoelectric device / radio frequency antenna A hybrid antenna including a piezoelectric device and an RF radiator. The hybrid antenna is capable of providing both RF and piezoelectric device functionality, e.g., radio frequency transmission/reception capabilities for radio frequency devices as well as sound-producing and/or energy-scavenging functionality via the piezoelectric device. The piezoelectric device may be in conductive contact with the RF radiator or may not be in conductive contact with the RF radiator.
US09660319B1	Signal distribution utilizing directional couplers connected in a chain topology The present disclosure is directed to combiners/splitters that reduce packaging and circuit board complexities. More specifically, an apparatus including a chain of directional couplers is used to distribute radio frequency power. The apparatus may also include a set of gain controllers. Each particular gain controller of the set of gain controllers is associated with a particular directional coupler of the chain of directional couplers, and each particular gain controller is configured to adjust a radio frequency power for the associated particular directional coupler.
US09660318B2	Differential signaling cable, transmission cable assembly using same, and production method for differential signaling cable A differential signaling cable includes a pair of signal conductors provided in parallel, longitudinally within the differential signaling cable, an insulator covering a periphery of the pair of signal conductors as a whole, wherein only the insulator is between the pair of signal conductors, and a shield conductor provided on an outer periphery of the insulator. An interval between the pair of signal conductors is set so that an even-mode impedance of the pair of signal conductors having the interval fixed by embedment within the insulator and covered by the shield conductor, is in a range from 1.5 to 1.9 times an odd-mode impedance for improved skew and differential mode insertion loss experienced during a transmission of high-speed signals of at least 10 Gbps.
US09660317B2	High-frequency signal transmission line A flexible high-frequency signal transmission line includes a dielectric body including laminated flexible dielectric layers. A signal line is provided in the dielectric body. A grounding conductor is arranged in the dielectric body to be opposed to the signal line via one of the dielectric layers. The grounding conductor is of a ladder structure including a plurality of openings and a plurality of bridges arranged alternately along the signal line. A characteristic impedance of the signal line changes between two adjacent ones of the plurality of bridges such that the characteristic impedance of the signal line rises from a minimum value to an intermediate value and to a maximum value and falls from the maximum value to the intermediate value and to the minimum value in this order.
US09660312B2	Metal/air battery with gas separation nanostructure A metal/air battery electrochemical cell in one embodiment includes a negative electrode, a positive electrode, an oxygen supply, and a closed oxygen conducting membrane less than about 50 microns thick located between the oxygen supply and the positive electrode.
US09660310B2	Electrode materials for metal-air batteries, fuel cells and supercapacitors The present invention refers to an electrode comprised of a first layer which comprises a mesoporous nanostructured hydrophobic material; and a second layer which comprises a mesoporous nanostructured hydrophilic material arranged on the first layer. In a further aspect, the present invention refers to an electrode comprised of a single layer which comprises a mixture of a mesoporous nanostructured hydrophobic material and a mesoporous nanostructured hydrophilic material; or a single layer comprised of a porous nanostructured material wherein the porous nanostructured material comprises metallic nanostructures which are bound to the surface of the porous nanostructured material. The present invention further refers to the manufacture of these electrodes and their use in metal-air batteries, supercapacitors and fuel cells.
US09660307B2	Battery temperature adjustment device A structure for effectively heating a battery. A battery is housed in a battery container. A condenser is formed such that a heating medium is in direct contact with a surface of the battery container, and condenses the heating medium to heat the battery via the battery container. The heating medium condensed by the condenser is supplied to an evaporator that heats and vaporizes the heating medium. The heating medium vaporized by the evaporator which is in vapor is circulated to the condenser.
US09660306B2	Systems and methods for selectively separating and separately processing portions of lead-acid batteries The present disclosure relates generally to systems and methods for recycling lead-acid batteries, and more specifically, relates to systems and methods for selectively separating and separately processing portions of lead-acid batteries to improve efficiency and reduce costs. A lead-acid battery processing system includes an imaging system configured to perform imaging of a lead-acid battery and perform image analysis to determine a break point that divides top lead from a remainder of the lead content of the lead-acid battery. The system also includes a battery breaking device configured to break the lead-acid battery at the determined break point and separate the lead-acid battery into a first portion, which includes the top lead, from a second portion, which includes the remainder of the lead content, for separate processing of the first and second portions of the lead-acid battery.
US09660304B2	Battery pack of novel air cooling structure Disclosed herein is a battery pack including a plurality of battery modules, each having a battery cell or a unit module (unit cell) that can be charged and discharged, mounted in a pack case, wherein two or more unit cells constitute one battery module, two or more battery modules are arranged in a length direction of the battery pack to constitute one battery module group, two battery module groups are arranged in a width direction of the battery pack in a state in which the batter module groups are spaced apart from each other such that a coolant discharge part is defined between the battery module groups, a coolant inlet port is independently formed at a region of the pack case corresponding to each of the battery modules located at a position opposite to the coolant discharge part, and a coolant outlet port is formed at a front or a rear of the pack case in the length direction of the battery pack such that coolant introduced through the respective coolant inlet ports cools the unit cells of the respective battery modules while passing through the respective battery modules and is then discharged out of the pack case.
US09660302B2	Secondary battery pack having non-protruded connector Disclosed herein is a secondary battery pack including a battery cell having a cathode terminal and an anode terminal formed on one surface including a sealed portion to seal the battery cell and a protection circuit module (PCM) including a protection circuit board (PCB) having a protection circuit formed thereon, an external input and output terminal electrically connected to the protection circuit, a connector electrically connected to the external input and output terminal, and an electrically insulative PCM case in which the PCB is mounted, wherein the PCM is loaded on the sealed portion in a state in which the PCM is electrically connected to the battery cell and the connector is formed on the PCM such that the connector does not protrude outward from the secondary battery pack.
US09660301B2	Methods and devices for battery protection An electronic apparatus is provided. The electronic apparatus includes: a battery; at least one pressure sensor provided on a surface of the battery; and a controller electrically connected with the at least one pressure sensor. The at least one pressure sensor samples a pressure parameter on the surface of the battery. The controller acquires the pressure parameter, detects a magnitude relation between the pressure parameter and a predefined threshold value, and generates a control instruction for protecting the battery based on the detected magnitude relation.
US09660298B2	Power storage element, manufacturing method thereof, and power storage device Disclosed is a power storage element including a positive electrode current collector layer and a negative electrode current collector layer which are arranged on the same plane and can be formed through a simple process. The power storage element further includes a positive electrode active material layer on the positive electrode current collector layer; a negative electrode active material layer on the negative electrode current collector layer; and a solid electrolyte layer in contact with at least the positive electrode active material layer and the negative electrode active material layer. The positive electrode active material layer and the negative electrode active material layer are formed by oxidation treatment.
US09660291B2	Positive active material for lithium secondary battery, method of preparing the same, and lithium secondary battery including positive active material A positive active material for a lithium secondary battery, a method of preparing the same, and a lithium secondary battery including the positive active material. The positive active material includes a core part and a shell part that include a nickel-based composite oxide, and a content of nickel in the core part is larger than that in the shell part.
US09660289B2	Electrode for secondary battery, preparation thereof, and secondary battery and cable-type secondary battery comprising the same A sheet-form electrode for a secondary battery includes a current collector, an electrode active material layer formed on one surface of the current collector, a porous polymer layer formed on the electrode active material layer, and a first porous supporting layer formed on the porous polymer layer. The sheet-form electrode can have supporting layers on at least one of the surfaces thereof to exhibit surprisingly improved flexibility and prevent the release of the electrode active material layer from a current collector even if intense external forces are applied to the electrode, thereby preventing the decrease of battery capacity and improving the cycle life characteristic of the battery.
US09660281B2	Method for controlling startup of fuel cell system A method for controlling a startup of a fuel cell system is provided. The method includes comparing a voltage generated in a fuel cell stack when hydrogen is supplied to a fuel electrode of the fuel cell stack for a set period of time with a first reference voltage. A voltage of a unit cell of the fuel cell stack is compared with a second reference voltage for load connection when the voltage generated in the fuel cell stack is higher than the first reference voltage. A load is connected to the fuel cell stack when the voltage of the unit cell of the fuel cell stack is higher than the second reference voltage for load connection.
US09660278B2	Method for detecting orifice flow phase transition in a pressure-controlled anode A fuel cell system that determines the phase transition from water to gas through a bleed/drain valve in a water separation device. The fuel cell system includes a fuel cell stack having an anode side and a cathode side. An injector injects hydrogen gas into the anode side of the fuel cell stack. The water separation device receives an anode exhaust gas from the anode side of the fuel cell stack, where the water separation device includes a water holding reservoir. A controller controls the injector and the bleed/drain valve and determines when the bleed/drain valve transitions from draining water to bleeding the anode exhaust gas by comparing the flow rate through the water separation device and the flow rate through the injector.
US09660276B2	Fuel cell including separator with outer ends placed inward of fluid passages formed in frame A cell unit constituting a fuel cell is provided with a first electrolyte membrane/electrode structure, a first separator, a second electrolyte membrane/electrode structure, and a second separator. The first and second electrolyte membrane/electrode structures respectively have a frame section on the outer periphery, and the frame sections are formed with a fluid communicating hole extending in the stacking direction. The first and second separators are disposed towards the inside of the fluid communication hole and are respectively provided with two metal plates which have the same shape and which are stacked on one another.
US09660273B2	Liquid phase modification of solid oxide fuel cells A solid oxide fuel cell comprising an electrolyte, an anode and a cathode. In this fuel cell at least one electrode has been modified with a promoter using liquid phase infiltration.
US09660272B2	Oxygen reduction catalyst and use thereof An oxygen reduction catalyst which includes composite particles including a portion including an inorganic metal compound and a portion containing carbon. The composite particles include a metal element M1, carbon, and oxygen as constituent elements; the amount of carbon atoms is 1 to 10 mol, and the amount of oxygen atoms is 1 to 3 mol, assuming that the total amount of atoms in the metal element M1 is 1 mol; a G-band and a D-band are present in a Raman spectrum, and a V/G ratio defined in an expression described below is 0.10 to 0.35: V/G ratio=(minimum value of spectral intensity in region V which is a region between G-band and D-band)/(peak intensity in G-band).
US09660267B2	High power electrode materials An LFP electrode material is provided which has improved impedance, power during cold cranking, rate capacity retention, charge transfer resistance over the current LFP based cathode materials. The electrode material comprises crystalline primary particles and secondary particles, where the primary particle is formed from a plate-shaped single-phase spheniscidite precursor and a lithium source. The LFP includes an LFP phase behavior where the LFP phase behavior includes an extended solid-solution range.
US09660264B2	Lithium secondary battery A lithium secondary battery includes: a positive electrode including a positive-electrode active material layer; a negative electrode including a negative-electrode active material layer; and an ion conductor being lithium ion conductive and interposed between the positive electrode and the negative electrode. The positive-electrode active material layer is composed of lithium cobaltate, and has an α-NaFeO2 type crystal structure. The positive-electrode active material layer is composed only of first regions oriented in the (110) plane and second regions oriented in the (018) plane, the first regions and the second regions being mixedly present in the xy plane of the positive-electrode active material layer, where x and y axes are defined as two axes that are parallel to the principal face of the positive-electrode active material layer, and a z axis is defined as an axis perpendicular to the principal face.
US09660261B2	Positive electrode active material, method for producing the same, and electrochemical device The invention provides a high-capacity positive electrode active material capable of sufficiently exploiting the excellent characteristics of magnesium metal or the like as a negative electrode active material, such as high energy capacity; a method for producing the same; and an electrochemical device using the positive electrode active material. A positive electrode 11 includes a positive electrode can 1, a positive pole pellet 2 having a positive electrode active material and the like, and a metal mesh support 3. A negative electrode 12 includes a negative electrode cap 4 and a negative electrode active material 5 such as magnesium metal. The positive electrode pellet 2 and the negative electrode active material 5 are disposed so as to sandwich a separator 6, and an electrolyte 7 is injected into the separator 6. The positive electrode active material, which provides the feature of the invention, is synthesized by a step of reacting a permanganate, such as potassium permanganate, with hydrochloric acid preferably having a concentration of 3 to 4 mol/l to produce a precipitate, and a step of filtering the precipitate, thoroughly washing the filtered precipitate with water, and then subjecting the washed precipitate to heat treatment preferably at a temperature of 300 to 400° C. for not less than 2 hours, thereby giving a manganese oxide.
US09660255B2	Wrapping electrode assembly and method for manufacturing the same A wrapping electrode assembly for use in a secondary battery manufactured by an electrode-stacking method includes: an electrode plate which has a coating layer of an electrode active material and a non-coated protruding portion, the electrode active material being capable of reversibly inserting and extracting lithium ions; first and second separator films which cover both surfaces of the electrode plate while exposing only the non-coated protruding portion; and an insulating polymer film which is positioned between the first separator film and the second separator film at least on a portion of a circumference of the electrode plate to be bonded to the first separator film and the second separator film, wherein the insulating polymer film is formed as being divided into at least two parts.
US09660244B2	System and method for establishing connections of a battery module A battery module includes a housing and battery cells disposed in the housing, each of the battery cells including two terminals. The battery module also includes bus bar cell interconnects including a first material, where each bus bar cell interconnect is configured to electrically couple two adjacent battery cells via an electrical coupling with a first terminal of one of the adjacent battery cells and a second terminal of the other adjacent battery cell, where at least one of the first and second terminals includes the first material. The battery module includes welds, each weld being disposed at a corresponding welding point to directly couple one of the bus bar cell interconnects with the corresponding at least one terminal including the first material. Each welding point is accessible for welding from a position above the battery cells when the interconnects are disposed over the battery cells.
US09660242B2	Electrode board having security device and power battery system using same A power battery system includes a number of parallel groups that being connected in series and a number of improved electrode boards. Each of the parallel groups comprising a number of single batteries connected in parallel. Each of the improved electrode boards being connected between two neighbored parallel groups. Each of the improved electrode boards includes a number of electrode contact plate, a conductive substrate, and a number of security devices. Each electrode contact plate connects two neighbored single batteries of two neighbored parallel groups in series. Each of the security devices corresponds to an electrode connection plate and electrically connects an electrode connection plate to the conductive substrate. Each of the security devices fuses when one of the single batteries of a parallel group occurs short circuit.
US09660231B2	Battery pack There is provided a battery pack capable of improving the safety thereof. The battery pack includes a battery array, side plates, a top cover and end plates. The battery array includes a plurality of battery cells aligned in a first direction. The battery array is formed as a hexahedron having (1-1)th, (1-2)th, (2-1)th (2-2)th, (3-1)th and (3-2)th planes. The top cover is provided to the (1-1)th plane of the battery array, and has reinforcing frames respectively formed at both sides based on the first direction. The reinforcing frame includes vertical and horizontal frames. The end plates are provided to the (3-1)th and (3-2)th planes, respectively. The end plates are fixed to the top cover. A holding part pressing both sides of the top cover on the (1-1)th plane are provided to the side plates, respectively.
US09660228B2	Secondary battery A secondary battery includes an electrode assembly, a case and a safety member. The electrode assembly has a first electrode plate, a second electrode plate and a separator interposed between the first and second electrode plates. The case accommodates the electrode assembly, and has an opened top. The safety member is inserted into an upper inside portion of the case, and seals the case. In the secondary battery, the safety member comprises an outer member contacting an inner surface of the case and having a center passing therethrough, an inner member spaced apart from the outer member at a predetermined interval and positioned at the center of the outer member, and a connection member connecting the outer and inner members. Accordingly, it is possible to increase the capacity of the battery.
US09660224B2	Mobile electronic device capable of uninterrupted power supply during battery replacement A mobile electronic device comprising an internal circuit and a battery compartment having an entrance and an exit. The battery compartment comprises a first conductor and a second conduct at the inner side of the battery compartment. The first conductor comprises at least two conductive contacts electrically connected to the internal circuit and having a distance from each other in the direction from the battery entrance to the battery exit so that, while a backup battery is sliding into the battery compartment from the battery entrance and pushing out a current battery through the battery exit, the first conductor may maintain electrical connection with conductive belt of the current battery and/or the backup battery. The structure of the second conductor is similar that of the first conductor and may maintain electrical connection with conductive belt of the current battery and/or the backup battery.
US09660223B2	Printing apparatus A printing apparatus includes a printing mask, which is disposed between a substrate having a display area and a non-display area surrounding the display area. The apparatus further includes a nozzle discharging an organic light emitting liquid onto the substrate. The printing mask includes a mask open part and a mask cover part. The mask open part exposes the display area, and the mask cover part surrounds the mask open part and covers the non-display area. The apparatus can be used to form an organic emitting layer on the substrate.
US09660222B2	Light-emitting device and method for manufacturing the same A light-emitting device with high reliability is provided. A light-emitting device includes a substrate 101, an organic EL element 110 formed over the substrate, a counter substrate 102 which is disposed so as to face the substrate, a plurality of projection structures 102a which are formed on the counter substrate and face the organic EL element, and a thermal conductor 135a of a liquid, a solid, or the like, which is disposed between the substrate and the counter substrate. The plurality of projection structures and the organic EL element are each in contact with the thermal conductor.
US09660220B2	Multiple light-emitting element device To provide a novel light-emitting element or a novel light-emitting device with high emission efficiency and low power consumption, a light-emitting element having a plurality of light-emitting layers between a pair of electrodes includes a lower electrode, a first light-emitting layer over the lower electrode, a charge-generation layer over the first light-emitting layer, a second light-emitting layer over the charge-generation layer, and an upper electrode over the second light-emitting layer. An emission spectrum of the first light-emitting layer peaks at a longer wavelength than an emission spectrum of the second light-emitting layer. A distance of between a bottom surface of the upper electrode and a bottom surface of the first light-emitting layer is less than or equal to 130 nm.
US09660219B2	Methods of manufacturing display devices A display device includes a first optical resonance layer on a substrate, a switching structure on the first optical resonance layer, a first electrode on the switching structure, a light emitting structure on the first electrode, and a second electrode on the emitting structure. The switching structure may include a switching device and an optical distance controlling insulation layer covering the switching device. A first optical resonance distance for an optical resonance of the light may be provided between an upper face of the first optical resonance layer and a bottom face of the second electrode.
US09660214B2	Organic light emitting diode and organic light emitting display device including the same An organic light emitting diode and an organic light emitting display device, the organic light emitting diode including a first electrode and a second electrode facing each other; an emission layer between the first electrode and the second electrode; and a hole transport layer between the first electrode and the emission layer, wherein the hole transport layer includes an organic material and a dipole material, the dipole material including a first component and a second component, the first component having a polarity different from that of the second component and the first component and the second component being combined with each other.
US09660212B2	Optical device comprising a charge transport layer of insoluble organic material and method for the production thereof A method of forming an organic light emitting diode comprising the steps of: providing a substrate comprising a first electrode for injection of charge carriers of a first type; forming a charge transporting layer by depositing over the substrate a charge transporting material for transporting charge carriers of the first type, the charge transporting material being soluble in a solvent; treating the charge transporting layer to render it insoluble in the solvent; forming an electroluminescent layer by depositing onto the charge transporting layer a composition comprising the solvent, a phosphorescent material, and a host material; and depositing over the electroluminescent layer a second electrode for injection of charge carriers of a second type.
US09660207B2	Organic solar cell An organic solar cell includes a first sub-cell including a first active layer and a second sub-cell including a second active layer, wherein at least one of the first active layer and the second active layer includes at least two types of electron acceptors having different light absorbance from each other.
US09660202B2	Organic electroluminescence device An organic electroluminescence (EL) device, including an anode; a cathode; and an emission layer between the anode and the cathode, the emission layer emitting a light via a singlet excited state, a stacking structure of at least three layers having different components being provided between the anode and the emission layer, wherein the stacking structure includes: a first layer including an electron accepting compound having a lowest unoccupied molecular orbital (LUMO) level of about −9.0 eV to about −4.0 eV; a second layer including a compound represented by the following Formula (1), the second layer being closer to the emission layer than the first layer; and a third layer including a compound represented by the following Formula (2), the third layer being closer to the emission layer than the second layer, wherein the emission layer includes a compound represented by the following Formula (3).
US09660201B2	Organic light emitting device A compound for an organic light emitting device is represented by Chemical Formula 1. An organic light emitting device includes a first electrode, a second electrode facing the first electrode and an organic layer between the first electrode and the second electrode, and the organic layer includes a compound represented by Chemical Formula 1. In the above Chemical Formula 1, Ar and L are the same as defined in the specification.
US09660200B2	Organic light-emitting device An organic light-emitting device includes a first electrode, a second electrode disposed opposite to the first electrode, and an organic layer disposed between the first electrode and the second electrode and including an emission layer. The emission layer includes at least one first light-emitting material represented by Formula 1 and at least one second light-emitting material represented by Formula 2: and X1 to X12, Ar1, M, X21 to X24, A, B, R1 to R12, R21, R22, a1, a2, n, L, M in Formulae 1 and 2 are defined as in the specification.
US09660199B2	Compound, light-emitting material, and organic light-emitting device A compound represented by the general formula (1) is useful as a light-emitting material. In the general formula (1), Ar1 to Ar3 represent an aryl group, provided that at least one thereof represents an aryl group substituted by a group represented by the general formula (2). In the general formula (2), R1 to R8 represent a hydrogen atom or a substituent; Z represents O, S, O═C or Ar4—N; and Ar4 represents an aryl group.
US09660197B2	Condensed cyclic compound and organic light-emitting device comprising the same A condensed cyclic compound represented by Formula 1: Also disclosed is an organic light-emitting device including a first electrode; a second electrode; and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer and the condensed cyclic compound of Formula 1. An organic light-emitting device including the condensed cyclic compound of Formula 1 may have low driving voltage, high efficiency, a high luminance, and long lifetime.
US09660196B2	Organic dye for a dye-sensitized solar cell Organic dye for a Dye Sensitized Solar Cell (DSSC) comprising at least one electron donor group and at least two electron acceptor groups, each of said electron acceptor groups being bound to said electron donor group through a π-conjugated unit.Said organic dye is particularly useful in a dye sensitized photoelectric transformation element, which, in its turn, can be used in a Dye Sensitized Solar Cell (DSSC).
US09660192B2	Organic electroluminescent display device with metal reflective layer Disclosed is an organic electroluminescent display device, a method for manufacturing the same and a display apparatus. The organic electroluminescent display device comprises: a substrate; a thin film transistor disposed on the substrate and including a gate electrode and an active layer insulated with each other, and a source electrode and a drain electrode connected with the active layer; and an organic electroluminescent structure disposed on the substrate and including an anode, a luminescent layer and a cathode stacked sequentially, the anode and the drain electrode being electrically connected with each other. The anode and the active layer are disposed in the same layer. The active layer is made of a transparent oxide semiconductor material. The anode is made of the transparent oxide semiconductor material undergone a plasma treatment. When producing the OLED device, the active layer and the anode may be simultaneously produced only by changing the pattern of the corresponding mask without additional patterning processes for producing the anodes, thereby simplifying process steps and saving production costs.
US09660191B2	Thin film deposition apparatus and method of manufacturing organic light-emitting display device by using the same A thin film deposition apparatus including a deposition source having a crucible to contain a deposition material and a heater to heat and vaporize the deposition material; a nozzle unit disposed at a side of the deposition source along a first direction and having a plurality of nozzle slits to discharge the deposition material that was vaporized; a plurality of emission coefficient increasing units disposed toward the nozzle unit within the deposition source and increasing a quantity of motion of the deposition material that is discharged toward the nozzle unit; a patterning slit sheet disposed opposite to the nozzle unit and having a plurality of patterning slits arranged along the first direction; and a barrier plate assembly disposed between the nozzle unit and the patterning slit sheet along the first direction, and having a plurality of barrier plates that partition a space between the nozzle unit and the patterning slit sheet into a plurality of sub-deposition spaces.
US09660190B2	Metal-insulator transition (MIT) device molded by clear compound epoxy The inventive concept provides MIT devices molded by clear compound epoxy and fire detecting devices including the MIT device. The fire detecting device is supplied with a power source from a power control device. The fire detecting device includes a MIT device including a MIT chip molded by a clear compound epoxy, a diode bridge circuit supplied with the power source from the power control device for providing a non-polar power source, a notice circuit supplied with the non-polar power source from the diode bridge circuit for warning of a fire alarm in response to a detecting signal from the MIT device, and a stabilization circuit for maintaining the detecting signal for a certain period.
US09660188B2	Phase change memory structure to reduce leakage from the heating element to the surrounding material A phase change memory (PCM) cell with a heating element electrically isolated from laterally surrounding regions of the PCM cell by a cavity is provided. A dielectric region is arranged between first and second conductors. A heating plug is arranged within a hole extending through the dielectric region to the first conductor. The heating plug includes a heating element running along sidewalls of the hole, and includes a sidewall structure including a cavity arranged between the heating element and the sidewalls. A phase change element is in thermal communication with the heating plug and arranged between the heating plug and the second conductor. Also provide is a method for manufacturing the PCM cell.
US09660186B2	Method of inspecting by-products and method of manufacturing semiconductor device using the same Provided is a method of manufacturing a semiconductor device. The method of manufacturing the semiconductor device includes forming magneto tunnel layers, forming a hard mask on the magneto tunnel layers, etching the magneto tunnel layers to form a magneto tunnel junction, wherein etching by-products are formed on sidewalls of the magneto tunnel junction, performing chemical treatment on the etching by-products to convert the etching by-products into a chemical reactant; and inspecting the chemical reactant.
US09660185B2	Pattern fortification for HDD bit patterned media pattern transfer A method and apparatus for forming a magnetic layer having a pattern of magnetic properties on a substrate is described. The method includes using a metal nitride hardmask layer to pattern the magnetic layer by plasma exposure. The metal nitride layer is patterned using a nanoimprint patterning process with a silicon oxide pattern negative material. The pattern is developed in the metal nitride using a halogen and oxygen containing remote plasma, and is removed after plasma exposure using a caustic wet strip process. All processing is done at low temperatures to avoid thermal damage to magnetic materials.
US09660184B2	Spin transfer torque memory cells Spin transfer torque memory cells and methods of forming the same are described herein. As an example, spin transfer torque memory cells may include an amorphous material, a storage material formed on the amorphous material, wherein the storage material is substantially boron free, an interfacial perpendicular magnetic anisotropy material formed on the storage material, a reference material formed on the interfacial perpendicular magnetic anisotropy material, wherein the reference material is substantially boron free, a buffer material formed on the reference material and a pinning material formed on the buffer material.
US09660183B2	Integration of spintronic devices with memory device A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer. The upper ILD layer includes a plurality of ILD levels. A plurality of magnetic tunneling junction (MTJ) stacks is formed in between adjacent ILD levels of the upper ILD layer. The plurality of MTJ stacks include a first MTJ stack having a first free layer, a first tunneling barrier layer and a first fixed layer. The first free layer is perpendicular to the first tunneling layer and fixed layer in the plane of the substrate surface. The plurality of MTJ stacks also include a second MTJ stack having a second free layer, a second tunneling barrier layer and a second fixed layer.
US09660182B2	Plasma processing method and plasma processing apparatus A plasma processing method of etching a multilayered material having a structure where a first magnetic layer 105 and a second magnetic layer 103 are stacked with an insulating layer 104 therebetween is performed by a plasma processing apparatus 10 including a processing chamber 12 where a processing space S is formed; and a gas supply unit 44 of supplying a processing gas into the processing space, and includes a first etching process where the first magnetic layer is etched by supplying a first processing gas and generating plasma, and the first etching process is stopped on a surface of the insulating layer; and a second etching process where a residue Z is removed by supplying a second processing gas and generating plasma. The first magnetic layer and the second magnetic layer contain CoFeB, the first processing gas contains Cl2, and the second processing gas contains H2.
US09660181B2	Logic chip including embedded magnetic tunnel junctions An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.
US09660173B2	Vibration generating apparatus There is provided a vibration generating apparatus including: a housing having an internal space; a vibrating plate fixedly installed in the housing and having a disc shape; a piezoelectric element fixed to the vibrating plate and having a hollow disc shape; and a vibration element vibrating together with the vibrating plate when the piezoelectric element is deformed.
US09660168B2	Heat exchanger for thermoelectric power generation with the thermoelectric modules in direct contact with the heat source A thermoelectric power generator for converting thermal energy into electrical energy. The thermoelectric power generator includes a heat exchanger configured to extract thermal energy from an exhaust gas stream. The heat exchanger includes fins in contact with a boundary of the heat exchanger, where the fins are directly connected to a first set of thermoelectric modules. A second set of thermoelectric modules are directly connected to the boundary of the heat exchanger. The first and second sets of thermoelectric modules are configured to convert the thermal energy to electrical energy. By eliminating the metal wall that previously existed between the thermoelectric modules and the fins, the thermoelectric power generator improves the heat transfer between the exhaust gas and the thermoelectric modules, eliminates the thermal fatigue failures at the bond between the metal wall and the thermoelectric modules as well as allows for a higher density of thermoelectric modules.
US09660161B2	Light emitting diode (LED) components including contact expansion frame A Light Emitting Diode (LED) component includes an LED die and a contact expansion frame having an expanded anode contact and/or an expanded cathode contact. A patterned solder mask is provided on the contact expansion frame that exposes a portion of the outer face of the expanded anode contact and/or a portion of the outer face of the expanded cathode contact. A solder layer is provided on the portion of the outer face of the expanded anode contact and on the portion of the outer face of the expanded cathode contact. Multiple die components and related fabrication methods are also described.
US09660160B2	Light emitting device A light emitting device package, and a lighting system includes a light emitting device. The light emitting device includes a substrate, a first conductive semiconductor layer on the substrate, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. A first via electrode contacts the first conductive semiconductor layer through a via hole formed through the substrate, and a second via electrode contacts the second conductive semiconductor layer through a second via hole formed through the substrate, the first conductive semiconductor layer, and the active layer.
US09660157B2	Addition-curable silicone resin composition and die attach material for optical semiconductor device An addition-curable silicone resin composition includes (A-1) a linear organopolysiloxane having at least two alkenyl groups per molecule, (A-2) a terminal alkenyl group-containing branched organopolysiloxane having at least two alkenyl groups per molecule, (B) an organohydrogenpolysiloxane with a content of low-molecular-weight siloxane having a degree of polymerization of up to 10 and one or more terminal SiH group per molecule of 5 wt % or less, and (C) an addition reaction catalyst. The composition can be cured to form a product which, when used as a die attach material for optical semiconductor devices, minimizes contamination of the gold electrode pads on LED chips and imparts a good wire bondability.
US09660156B2	Optical semiconductor element mounting package, and optical semiconductor device using the same An optical semiconductor element mounting package that has good adhesion between the resin molding and the lead electrodes and has excellent reliability is provided, as well as an optical semiconductor device using the package is also provided. The optical semiconductor element mounting package having a recessed part that serves as an optical semiconductor element mounting region, wherein the package is formed by integrating: a resin molding composed of a thermosetting light-reflecting resin composition, which forms at least the side faces of the recessed part; and at least a pair of positive and negative lead electrodes disposed opposite each other so as to form part of the bottom face of the recessed part, and there is no gap at a joint face between the resin molding and the lead electrodes.
US09660154B2	Chip scale light emitting device package with dome Light Emitting Devices (LEDs) are fabricated on a wafer substrate with one or more thick metal layers that provide structural support to each LED. The streets, or lanes, between individual LEDs do not include this metal, and the wafer can be easily sliced/diced into singulated self-supporting LEDs. Because these devices are self-supporting, a separate support submount is not required. Before singulation, further processes may be applied at the wafer-level; after singulation, these self-supporting LEDs may be picked and placed upon an intermediate substrate for further processing as required. In an embodiment of this invention, protective optical domes are formed over the light emitting devices at the wafer-level or while the light emitting devices are situated on the intermediate substrate.
US09660148B2	Method for manufacturing light emitting device, and light emitting device A method for manufacturing a light emitting device comprises a package preparation step of preparing a package having a recess in which a light emitting element is locatable, wherein the package includes a projection extending from an upper surface of the package, the projection at least partially surrounding the recess, a sealing resin forming step of filling said recess in which said light emitting element is located with a sealing resin, and providing said sealing resin higher than the height of said package, and a sealing resin cutting step of cutting the sealing resin such that an upper surface of the sealing resin is at a height that is substantially the same as a height of the upper surface of the package.
US09660146B2	Light-emitting element A light-emitting element comprises a light-emitting stack comprising an active layer for emitting a light; a window layer on the light-emitting stack; and a first insulative layer having a first refractive index on the window layer; wherein the first insulative layer has a first refractive index, and the window layer has a second refractive index, and a difference between the first refractive index and the second refractive index is larger than 1.5.
US09660144B2	LED package and LED die The present disclosure provides a light emitting diode die which includes a substrate; an N type semiconductor layer, an active layer, and a P type semiconductor layer formed on the substrate in sequence; at least one recess, and a pair of electrodes. The recess extends to the N type semiconductor layer. The insulating layer covers the all of side surfaces of the N type semiconductor layer, the active layer, the P type semiconductor layer, and covers top of the P type semiconductor layer except an opening on the P semiconductor layer. One of the electrodes is filled in the recess and electrically connected to the N type semiconductor layer, and the other one of the electrodes is connected to the P type semiconductor layer in the opening. The present disclosure further provides an LED package having the LED die and a method for manufacturing the same.
US09660139B2	Nanostructure semiconductor light emitting device A nanostructure semiconductor light emitting device includes a base layer, an insulating layer, a plurality of light emitting nanostructures, and a contact electrode. The base layer is formed of a first conductivity-type semiconductor material. The insulating layer is disposed on the base layer. Each light emitting nanostructure is disposed in a respective opening of a plurality of openings in the base layer, and includes a nanocore formed of the first conductivity-type semiconductor material, and an active layer and a second conductivity-type semiconductor layer sequentially disposed on a surface of the nanocore. The contact electrode is spaced apart from the insulating layer and is disposed on a portion of the second conductivity-type semiconductor layer. A tip portion of the light emitting nanostructure has crystal planes different from those on side surfaces of the light emitting nanostructure.
US09660138B2	Light emitting device and method for manufacturing light emitting device A method for manufacturing a light emitting device includes a) forming a first light confinement layer having a plurality of openings on or above one main surface of an oriented polycrystalline substrate, said oriented polycrystalline substrate including a plurality of oriented crystal grains; b) stacking an n-type layer, an active layer, and a p-type layer; c) forming a second light confinement layer on said first light confinement layer so that said second light confinement layer covers said plurality of first columnar structures and said second columnar structure; d) forming a transparent conductive film on said second light confinement layer; e) forming a pad electrode on said transparent conductive film; and f) forming a cathode electrode electrically connected to ends of said plurality of first columnar structures closer to said oriented polycrystalline substrate.
US09660137B2	Method for producing a nitride compound semiconductor device A method is provided for producing a nitride compound semiconductor device. A growth substrate has a silicon surface. A buffer layer, which comprises AlxInyGa1-x-yN with 0≦x≦1, 0≦y≦1 and x+y≦1, is grown onto the silicon surface of the substrate. A semiconductor layer sequence is grown onto the buffer layer. The buffer layer includes a material composition that varies in such a way that a lateral lattice constant of the buffer layer increases stepwise or continuously in a first region and decreases stepwise or continuously in a second region, which follows the first region in the growth direction. At an interface with the semiconductor layer sequence, the buffer layer includes a smaller lateral lattice constant than a semiconductor layer of the semiconductor layer sequence adjoining the buffer layer.
US09660131B2	Method for connecting conductor, member for connecting conductor, connecting structure and solar cell module The electric conductor connection method of the invention is a method for electrical connection between a mutually separated first electric conductor and second electric conductor, comprising a step of hot pressing a metal foil, a first adhesive layer formed on one side of the metal foil and a first electric conductor, arranged in that order, to electrically connect and bond the metal foil and first electric conductor, and hot pressing the metal foil, the first adhesive layer or second adhesive layer formed on the other side of the metal foil, and the second electric conductor, arranged in that order, to electrically connect and bond the metal foil and the second electric conductor.
US09660127B2	Sputtering target and method for producing same Provided are a sputtering target that is capable of forming a Cu—Ga film, which has an added Ga concentration of 1 to 40 at % and into which Na is well added, by a sputtering method and a method for producing the sputtering target. The sputtering target has a component composition that contains 1 to 40 at % of Ga, 0.05 to 2 at % of Na as metal element components other than F, S and Se, and the balance composed of Cu and unavoidable impurities. The sputtering target contains Na in at least one form selected from among sodium fluoride, sodium sulfide, and sodium selenide, and has a content of oxygen of from 100 to 1,000 ppm.
US09660126B2	Photovoltaic device with three dimensional charge separation and collection A photovoltaic device having three dimensional (3D) charge separation and collection, where charge separation occurs in 3D depletion regions formed between a p-type doped group III-nitride material in the photovoltaic device and intrinsic structural imperfections extending through the material. The p-type group III-nitride alloy is compositionally graded to straddle the Fermi level pinning by the intrinsic structural imperfections in the material at different locations in the group III-nitride alloy. A field close to the surfaces of the intrinsic defects separates photoexcited electron-hole pairs and drives the separated electrons to accumulate at the surfaces of the intrinsic defects. The intrinsic defects function as n-type conductors and transport the accumulated electrons to the material surface for collection. The compositional grading also creates a potential that drives the accumulated separated electrons toward an n-type group III-nitride layer for collection. The p-type group III-nitride alloy may comprise an alloy of InGaN, InAlN or InGaAlN.
US09660124B2	Concentrator photovoltaic unit, concentrator photovoltaic module, concentrator photovoltaic panel, and concentrator photovoltaic apparatus A concentrator photovoltaic unit being an optical system base unit includes: a concentrating portion configured to converge sunlight; a cell configured to receive light converged by the concentrating portion to generate power; a package including a frame portion, the frame portion having insulating property and surrounding the cell, the package being in integrated relation with the cell; a shield plate provided between the concentrating portion and the cell, and including an opening allowing light converged by the concentrating portion to selectively pass therethrough; and a protection plate being a heat-resistant member provided on the frame portion to make the cell expose to the light and to shield the package, the protection plate being in contact with nothing but the frame portion, and securing a predetermined insulation distance from a live portion of the cell.
US09660120B2	Solar cell module and solar cell module manufacturing method A solar battery module is provided with a plurality of solar battery cells which are connected to each other by connecting bus bar electrodes (21) formed on the surfaces of the adjacent solar battery cells with wiring material (41a, 41b). The bus bar electrode (21) is embedded in the wiring material (41b), and the solar battery cell (1) and the wiring material (41b) are bonded with a resin.
US09660119B2	Polyester film, method for producing the same, back sheet for solar cell, and solar cell module A polyester film has excellent resistance to hydrolysis, excellent heat resistance in high temperatures and low humidity, and mechanical strength. The polyester film satisfies a stress heat resistant coefficient f(125)≧3 and a wet thermo retention (=100×S(120)/S(0)) of 30% or more. f(125) is a value obtained by substituting t=125° C. in an approximation represented by f(t); t represents a temperature (° C.) at thermo processing; f(t) represents a stress heat resistant coefficient f at the thermo temperature t and represents an approximation to a straight line obtained by linear approximation by a least squares method of values plotted from a relationship between the thermo temperature t and a logarithm (log T(t)) of time T at which a rupture stress is 50% when t is 150° C., 160° C., 170° C., or 180° C.; T(t) is a time (hr) at which the maximum stress in a tensile test after thermo processing at t° C. and 0% RH is 50% of the maximum stress in a tensile test before thermo processing; S(120) is breaking elongation (%) after aging for 100 hours at 120° C. and 100% RH, and S(0) represents a breaking elongation (%) before aging.
US09660117B1	Energy selective photodetector A semiconductor device has a layered structure. The semiconductor device includes a metallic layer of thickness 1-100 nm, with a thickness optimized to absorb light in a wavelength range of operation. The device further includes an adjacent semiconductor layer additionally adjacent to an ohmic electrical contact, wherein the interface between the metallic layer and the semiconductor layer is electrically rectifying and energy selective. The device further includes a reflective back surface positioned opposite to the semiconductor layer relative to incident light providing broadband reflection in the wavelength range of operation. The semiconductor layer includes a quantum well adjacent to the metallic layer, wherein the energy selectivity is provided by the quantum well allowing charge carrier tunneling from the metallic layer. The device further may include an additional anti-reflection dielectric layer deposited on the metallic layer that is configured to minimize reflection of light in the wavelength range of operation.
US09660116B2	Nanowires formed by employing solder nanodots A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
US09660115B2	Nano-electrode multi-well high-gain avalanche rushing photoconductor Provided is a detector that includes a scintillator, a common electrode, a pixel electrode, and a plurality of insulating layers, with a plurality of nano-pillars formed in the plurality of insulating layers, a nano-scale well structure between adjacent nano-pillars, with a-Se separating the adjacent nano-pillars, and a method for operation thereof.
US09660114B2	Temperature stabilization of an on-chip temperature-sensitive element Disclosed is an integrated circuit (IC) chip incorporating a temperature-sensitive element and temperature stabilization circuitry for ensuring that the temperature of the temperature-sensitive element (TSE) remains essentially constant. The IC chip comprises a temperature-sensitive element and, within at least one region adjacent to the temperature-sensitive element, a first circuit that radiates a first heat amount to the TSE and a second circuit that radiates a second heat amount to the TSE. The second circuit senses changes in a first current amount in the first circuit and, thereby changes in the first heat amount. In response to those changes, the second circuit also automatically adjusts a second current amount in the second circuit and, thereby the second heat amount in order to ensure that the total heat amount radiated by the first circuit and the second circuit, in combination, to the TSE remains constant. Also disclosed is an associated method.
US09660112B2	Semiconductor light trap devices Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.
US09660110B2	Varactor device with backside contact An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.
US09660107B1	3D cross-bar nonvolatile memory Semiconductor structures and methods for crystalline junctionless transistors used in nonvolatile memory arrays are introduced. Various embodiments in accordance with this disclosure provide a method of fabricating a monolithic 3D cross-bar nonvolatile memory array with low thermal budget. The method incorporates crystalline junctionless transistors into nonvolatile memory structures by transferring a layer of doped crystalline semiconductor material from a seed wafer to form the source, drain, and connecting channel of the junctionless transistor.
US09660105B2	Finfet crosspoint flash memory A flash memory device in a dual fin single floating gate configuration is provided. Semiconductor fins are formed on a stack of a back gate conductor layer and a back gate dielectric layer. Pairs of semiconductor fins are formed in an array environment such that shallow trench isolation structures can be formed along the lengthwise direction of the semiconductor fins within the array. After formation of tunneling dielectrics on the sidewalls of the semiconductor fins, a floating gate electrode is formed between each pair of proximally located semiconductor fins by deposition of a conformal conductive material layer and an isotropic etch. A control gate dielectric and a control gate electrode are formed by deposition and patterning of a dielectric layer and a conductive material layer.
US09660104B2	Semiconductor device and manufacturing method thereof A transistor having a multi-layer structure of oxide semiconductor layers is provided in which a second oxide semiconductor layer having a crystalline structure including indium zinc oxide is formed over a first oxide semiconductor layer having an amorphous structure, and at least a third oxide semiconductor layer is formed stacked over the second oxide semiconductor layer. The second oxide semiconductor layer mainly serves as a carrier path for the transistor. The first oxide semiconductor layer and the third oxide semiconductor layer each serve as a barrier layer for suppressing entrance of impurity states of an insulating layer in contact with the multi-layer structure to the carrier path.
US09660102B2	Semiconductor device and manufacturing method thereof An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
US09660097B2	Semiconductor device A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.
US09660094B2	Thin film transistor and method of manufacturing the same A thin film transistor includes a gate electrode on a substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, the semiconductor layer overlapping at least a portion of the gate electrode, a plurality of etch stoppers on the semiconductor layer, and a source electrode and a drain electrode spaced apart from each other and disposed on the etch stoppers and the semiconductor layer, wherein a plurality of channel regions are defined in the semiconductor layer by the etch stoppers on the semiconductor layer.
US09660090B2	Array substrate An array substrate having a thin film transistor with an oxide semiconductor layer, wherein the thin film transistor is in a device area of a pixel region; the substrate comprising a light-shielding pattern on the array substrate in the device area; an auxiliary line connected to a light-shielding pattern and supplying a constant voltage to the light-shielding pattern, wherein the auxiliary line is parallel to and spaced apart from one of the gate and data lines; a buffer layer on the light-shielding pattern and a surface of the array substrate, wherein the oxide semiconductor layer is on the buffer layer and the light-shielding pattern; an inter-insulating layer on the buffer layer, wherein the oxide semiconductor layer includes an active portion located entirely on the light-shielding pattern and having a channel formed thereon, and conductive portions located on sides of the active portion.
US09660080B2	Multi-layer strained channel FinFET Methods and structures for forming a localized, strained region of a substrate are described. Trenches may be formed at boundaries of a localized region of a substrate. An upper portion of sidewalls at the localized region may be covered with a covering layer, and a lower portion of the sidewalls at the localized region may not be covered. A converting material may be formed in contact with the lower portion of the localized region, and the substrate heated. The heating may introduce a chemical species from the converting material into the lower portion, which creates stress in the localized region. The methods may be used to form strained-channel finFETs.
US09660079B2	Semiconductor device and method of manufacturing the same To improve performance of a semiconductor device. Over a semiconductor substrate, a gate electrode is formed via a first insulating film for a gate insulating film, and a second insulating film extends from over a side wall of the gate electrode to over the semiconductor substrate. Over the semiconductor substrate in a part exposed from the second insulating film, a semiconductor layer, which is an epitaxial layer for source/drain, is formed. The second insulating film has a part extending over the side wall of the gate electrode and a part extending over the semiconductor substrate, and a part of the semiconductor layer lies over the second insulating film in the part extending over the semiconductor substrate.
US09660077B2	Stress memorization technique for strain coupling enhancement in bulk finFET device A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the dielectric fill into the trenches to form shallow trench isolation regions. The fins are etched above the shallow trench isolation regions to form a staircase fin structure with narrow top portions of the fins. Gate structures are formed over the top portions of the fins. Raised source ad drain regions are epitaxially grown on opposite sides of the gate structure. A pre-morphization implant is performed to generate defects in the substrate to couple strain into the top portions of the fins.
US09660075B2	Integrated circuits with dual silicide contacts and methods for fabricating same Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.
US09660072B2	Laterally diffused metal oxide semiconductor and field drift metal oxide semiconductor A laterally diffused metal oxide semiconductor (LDMOS) is provided. A substrate has a deep well with a second conductive type therein. A gate is disposed on the substrate. A first doped region of a second conductive type and a second doped region of a first conductive type are located in the deep well and at the corresponding two sides of the gate. A drain region of a second conductive type is located in the first doped region. A drain contact is disposed on the drain region. A doped region of a first conductive type is located in the first doped region and under the drain region but not directly below the drain contact. A source region is located in the second doped region. A field drift metal oxide semiconductor (FDMOS) which is similar to the laterally diffused metal oxide semiconductor (LDMOS) is also provided.
US09660065B2	Semiconductor device and method for producing same having multilayer wiring structure with contact hole having hydrophobic film formed on side surface of the contact hole A method of producing a semiconductor device includes forming an insulating film on a substrate on which a semiconductor layer is formed; removing a part of the insulating film by etching to form an opening in the insulating film; supplying steam with a temperature greater than or equal to 200° C. and less than or equal to 600° C. to the opening formed in the insulating film; after supplying the steam, applying a solution including a silicon compound to a side surface or the insulating film defining the opening; and forming a hydrophobic film on the side surface of the insulating film defining the opening by polymerizing the silicon compound.
US09660063B2	Semiconductor structure having sets of III-V compound layers and method of forming the same A semiconductor structure includes a substrate; and a graded III-V layer over the substrate. The semiconductor structure further includes a p-doped gallium nitride (GaN) layer over the graded III-V layer. The semiconductor structure further includes one or more sets of GaN layers over the p-doped GaN layer. Each set of the one or more sets of GaN layers includes a lower GaN layer, wherein the lower GaN layer is undoped, unintentionally doped having N-type doping, or N-type doped. Each set of the one or more sets of GaN layers includes an upper GaN layer on the lower GaN layer, wherein the upper GaN layer is P-type doped. The semiconductor structure includes a second GaN layer over the one or more sets of GaN layers, the second GaN layer being either undoped or unintentionally doped having the N-type doping. The semiconductor structure includes an active layer over the second GaN layer.
US09660060B2	Thin film transistor and fabricating method thereof A thin film transistor and a fabricating method thereof are provided. The thin film transistor includes a semiconductor stacked layer, an insulating layer, a gate, a dielectric layer, a source and a drain. The semiconductor stacked layer includes a first metal oxide semiconductor layer and a second metal oxide semiconductor layer disposed on the first metal oxide semiconductor layer. A resistance value of the first metal oxide semiconductor layer is less than a resistance value of the second metal oxide semiconductor layer. The insulating layer is disposed on the semiconductor stacked layer. The gate is disposed on the insulating layer. The dielectric layer covers the gate, wherein the dielectric layer has a plurality of contact openings. The source and the drain are disposed on the dielectric layer, and filled into the contact openings to electrically connect with the semiconductor stacked layer.
US09660055B2	Method of manufacturing a semiconductor device with lateral FET cells and field plates A method of manufacturing a semiconductor device includes providing dielectric stripe structures extending from a first surface into a semiconductor substrate between semiconductor fins. A first mask is provided that covers a first area including first stripe sections of the dielectric stripe structures and first fin sections of the semiconductor fins. The first mask exposes a second area including second stripe and second fin sections. A channel/body zone is formed in the second fin sections by introducing impurities, wherein the first mask is used as an implant mask. Using an etch mask that is based on the first mask, recess grooves are formed at least in the second stripe sections.
US09660052B2	Strained source and drain (SSD) structure and method for forming the same Mechanisms of forming a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a gate stack structure formed on the substrate. The semiconductor device structure also includes gate spacers formed on sidewalls of the gate stacks. The semiconductor device structure includes doped regions formed in the substrate. The semiconductor device structure also includes a strained source and drain (SSD) structure adjacent to the gate spacers, and the doped regions are adjacent to the SSD structure. The semiconductor device structure includes SSD structure has a tip which is closest to the doped region, and the tip is substantially aligned with an inner side of gate spacers.
US09660049B2	Semiconductor transistor device with dopant profile A transistor and a method for forming the transistor are provided. The method includes performing at least one implantation operation in the transistor channel area, then forming a silicon carbide/silicon composite film over the implanted area prior to introducing further dopant impurities. A halo implantation operation with a low tilt angle is used to form areas of high dopant concentration at edges of the transistor channel to alleviate short channel effects. The transistor structure includes a reduced dopant impurity concentration at the substrate interface with the gate dielectric and a peak concentration about 10-50 nm below the surface. The dopant profile has high dopant impurity concentration areas at opposed ends of the transistor channel.
US09660045B2	Semiconductor device and a method for manufacturing a semiconductor device The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.
US09660041B2	Electronic device comprising a semiconductor memory unit Devices and methods based on disclosed technology include, among others, an electronic device capable of improving a signal transfer characteristic and a method for fabricating the same. Specifically, an electronic device in one implementation includes a plurality of buried gates formed in a substrate, open parts formed in the substrate on both sides of the buried gate, isolation layers each formed between a sidewall of the open part and a sidewall of the buried gate, source/drain regions formed in the substrate under the respective open parts, and contact plugs buried in the respective open parts.
US09660035B2	Semiconductor device including superlattice SiGe/Si fin structure A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (SiGe) fin having a superlattice structure. The SiGe fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one silicon germanium fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a silicon germanium gate channel beneath the gate stack.
US09660034B1	Electronic chip comprising transistors with front and back gates An integrated circuit includes SOI-type MOS transistors on insulator, with a first well capable of being biased located under the insulator. The first wells are doped with a first conductivity type. Each first well includes, under the insulator of each transistor, a back gate region that is more heavily doped than the first well. The first wells are separated from each other by inclusion in in a second well that is also capable of being biased. The second well is doped with a second conductivity type.
US09660032B2	Method and apparatus providing improved thermal conductivity of strain relaxed buffer A structure includes a substrate and a strain relaxed buffer (SRB) that has a bottom surface disposed on the substrate and an opposite top surface. The SRB is formed to have a plurality of pairs of layers, where a given pair of layers is composed of a layer of Si1-xGex and a layer of Si. The structure further includes a plurality of transistor devices formed above the top surface of the SRB and at least one contact disposed vertically through the top surface of the SRB and partially through a thickness of the SRB. The at least one contact is thermally coupled to at least one of the plurality of the Si layers for conducting heat out of the SRB via the at least one of the plurality of Si layers. A method to form the structure is also disclosed.
US09660031B2	Integrated circuit device having III-V compound semiconductor region comprising magnesium and N-type impurity and overlying III-V compound semiconductor layer formed without Cp2Mg precursor A method includes epitaxially growing a first III-V compound semiconductor, wherein the first III-V compound semiconductor is of p-type. The first III-V compound semiconductor is grown using precursors including a first precursor comprising Cp2Mg, and a second precursor comprising a donor impurity. A second III-V compound semiconductor is grown overlying and contacting the first III-V compound semiconductor. The second III-V compound semiconductor is of n-type.
US09660025B2	Structure and formation method of semiconductor device structure Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The fin structure includes a first surface and a second surface. The first surface is inclined to the second surface. The semiconductor device structure also includes a passivation layer covering the first surface and the second surface of the fin structure. The thickness of a first portion of the passivation layer covering the first surface is substantially the same as that of a second portion of the passivation layer covering the second surface.
US09660022B2	Semiconductive device with a single diffusion break and method of fabricating the same A method of fabricating a single diffusion break includes providing a fin with two gate structures crossing the fin and a middle dummy gate structure crossing the fin, wherein the middle dummy gate structure is sandwiched by the gate structures. Later, numerous spacers are formed and each spacer respectively surrounds the gate structures and the middle dummy gate structure. Then, the middle dummy gate structure, and part of the fin directly under the middle dummy gate structure are removed to form a recess. Finally, an isolating layer in the recess is formed to close an entrance of the recess so as to form a void embedded within the recess.
US09660021B1	Trench gate trench field plate vertical MOSFET A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
US09660019B2	Concentric capacitor structure A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.
US09660017B2	Microelectronic package with surface mounted passive element A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.
US09660005B2	Display device A display device includes a first substrate, a first light emitting structure, a first transistor, a second transistor, a second light emitting structure, and a second substrate. The first light emitting structure is disposed on the first substrate. The first transistor is disposed on the first light emitting structure, and electrically connected to the first light emitting structure. The second transistor is disposed on the same level with the first transistor. The second light emitting structure is disposed on the first and second transistors, and electrically connected to the second transistor. The second substrate is disposed on the second light emitting structure, and opposite to the first substrate.
US09660001B2	Organic light emitting diode display An organic light emitting diode display includes a plurality of transmission window areas arranged in a matrix form, a plurality of green pixels arranged in a plurality of horizontal line areas among the plurality of transmission window areas, and a plurality of red pixels and a plurality of blue pixels arranged in a plurality of vertical line areas among the plurality of transmission window areas.
US09659999B2	3-dimensional stack memory device A 3-dimensional stack memory device includes a semiconductor substrate, a stacked active pattern configured so that a plurality of stripe shape active regions and insulation layers are stacked alternatively over the semiconductor substrate, a gate electrode formed in the stacked active pattern, a source and drain formed at both sides of the gate electrode in each of the plurality of active regions, a bit line formed on one side of the drain to be connected to the drain, a resistive device layer formed on one side of the source to be connected to the source, and a source line connected to the resistive device layer. The source is configured of an impurity region having a first conductivity type, and the drain is configured of an impurity region having a second conductivity type different from the first conductivity type.
US09659996B2	Magnetic memory element and magnetic memory According to one embodiment, a magnetic memory element comprises a first magnetic unit, a second magnetic unit, a first insulating unit, a first electrode, a second electrode, and a third electrode. The first magnetic unit includes a plurality of magnetic domains. The second magnetic unit includes a first region and a second region. The first region includes a conductive material. The second region includes an insulating material. At least one of the first region or the second region is magnetic. The first insulating unit is provided between the first magnetic unit and the second magnetic unit. The first electrode and the second electrode are connected to the first magnetic unit. A part of the second magnetic unit and a part of the first insulating unit are provided between the third electrode and a part of the first magnetic unit.
US09659994B2	Imaging device and electronic apparatus An imaging device includes: a photoelectric conversion region that generates photovoltaic power for each pixel depending on irradiation light; and a first element isolation region that is provided between adjacent photoelectric conversion regions in a state of surrounding the photoelectric conversion region.
US09659992B2	Method of manufacturing an imager and imager device Embodiments related to a method of manufacturing of an imager and an imager device are shown and depicted.
US09659991B2	Image capturing apparatus, manufacturing method thereof, and camera A back-side illumination image capturing apparatus includes a semiconductor substrate having a first surface for receiving incident light and a second surface located on the opposite side as the first surface, and including a photoelectric conversion portion, and a gate electrode disposed above the second surface. The apparatus further includes a first insulating layer disposed above the second surface of the semiconductor substrate, an interlayer insulation film disposed on the first insulating layer, a contact plug connected to the gate electrode, and a light-cutting portion for cutting light, of the incident light, that has passed through the photoelectric conversion portion. The light-cutting portion passes through at least part of the interlayer insulation film. The first insulating layer is located between the light-cutting portion and the semiconductor substrate.
US09659984B2	Solid-state image sensor including a photoelectric conversion element, a charge conversion element, and a light shielding element, method for producing the same solid-state image sensor, and electronic apparatus including the same solid-state image sensor A solid-state image sensor includes a semiconductor substrate having a photoelectric conversion element converting incident light into a charge and a charge retaining section temporarily retaining the charge photoelectrically converted by the photoelectric conversion element and a light shielding section having an embedded section extending in at least a region between the photoelectric conversion element and the charge retaining section of the semiconductor substrate.
US09659981B2	Backside illuminated image sensor with negatively charged layer A semiconductor image sensor device having a negatively-charged layer includes a semiconductor substrate having a p-type region, a plurality of radiation-sensing regions in the p-type region proximate a front side of the semiconductor substrate, and a negatively-charged layer adjoining the p-type region proximate the plurality of radiation-sensing regions. The negatively-charged layer may be an oxygen-rich silicon oxide, a high-k metal oxide, or a silicon nitride formed as a liner in a shallow trench isolation feature, a sidewall spacer or an offset spacer of a transistor gate, a salicide-block layer, a buffer layer under a salicide-block layer, a backside surface layer, or a combination of these.
US09659977B2	Semiconductor device A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled.
US09659973B2	Display device The present disclosure provides a display device, including: a display region, a driving element, and the display region electrically connected to the driving element through a plurality of signal line pairs. In particular, at least one of the signal line pairs includes a first conductive line and a second conductive line, and the first conductive line is electrically isolated from the second conductive line. In the signal line pair, at least a part of the first conductive line overlaps the second conductive line.
US09659971B2	Array substrate and liquid crystal display device The present invention relates to the field of liquid crystal display technology and provides an array substrate and a liquid crystal display device which can solve the problem of low transmissivity of existing liquid crystal display devices. The array substrate of the present invention comprises a plurality of pixel units, each pixel unit is provided with a plate electrode and a slit electrode arranged above the plate electrode, an insulation layer is provided between the plate electrode and the slit electrode, and the plate electrode extends to the periphery region of the pixel unit, the slit electrode extends to the periphery region of the pixel unit; the slit electrode and the plate electrode are both provided in at least part of the peripheral region of the pixel unit. the present invention is applicable to liquid crystal display devices, especially the liquid crystal display devices taking a “dual gate lines” design.
US09659966B2	Flexible display substrate, flexible organic light emitting display device and method of manufacturing the same A flexible display substrate, a flexible organic light emitting display device, and a method of manufacturing the same are provided. The flexible display substrate comprises a flexible substrate including a display area and a non-display area extending from the display area, and a wire formed on the flexible substrate. At least a part of the non-display area of the flexible substrate is formed in a crooked shape in a bending direction, and the wire positioned on at least a part of the non-display area of the flexible substrate includes a plurality of first wire patterns, and a second wire pattern formed on the plurality of first wire patterns and electrically connected with the plurality of first wire patterns.
US09659965B2	Liquid crystal display device and method of manufacturing the same A liquid crystal display (LCD) device comprises a first substrate, a second substrate disposed to face the first substrate, a liquid crystal layer which is disposed between the first substrate and the second substrate and which includes multiple liquid crystal molecules, and a self-alignment layer formed between the first substrate and the liquid crystal layer, the self-alignment layer comprising a vertical alignment additive having a molecular structure having a hydrophilic group and a polymerized group formed in both ends of a core molecule, wherein a major axis of the vertical alignment additive is at an angle less than about 90° with respect to a surface of the first substrate.
US09659962B2	Semiconductor devices and methods of manufacture thereof Semiconductor devices and methods of manufacture thereof are disclosed. A complimentary metal oxide semiconductor (CMOS) device includes a PMOS transistor having at least two first gate electrodes comprising a first parameter, and an NMOS transistor having at least two second gate electrodes comprising a second parameter, wherein the second parameter is different than the first parameter. The first parameter and the second parameter may comprise the thickness or the dopant profile of the gate electrode materials of the PMOS and NMOS transistors. The first and second parameter of the at least two first gate electrodes and the at least two second gate electrodes establish the work function of the PMOS and NMOS transistors, respectively.
US09659960B1	Extremely thin silicon-on-insulator silicon germanium device without edge strain relaxation A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.
US09659959B2	Semiconductor devices A semiconductor device includes a lower insulation layer, a plurality of base layer patterns separated from each other on the lower insulation layer, a separation layer pattern between the base layer patterns, a plurality of channels extending in a vertical direction with respect to top surfaces of the base layer patterns, and a plurality of gate lines surrounding outer sidewalls of the channels, being stacked in the vertical direction and spaced apart from each other.
US09659954B2	Non-volatile memory devices with vertically integrated capacitor electrodes Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area occupied by the capacitor in the entire device can be reduced as compared with a planar capacitor. Thus, a non-volatile memory device may be highly integrated and have a high capacity. The device includes a substrate having a cell region and a peripheral circuit region, a memory cell string including a plurality of vertical memory cells formed in the cell region and channel holes formed to penetrate the vertical memory cells in a first direction vertical to the substrate, an insulating layer formed in the peripheral circuit region on the substrates at substantially the same level as an upper surface of the memory cell string, and a plurality of capacitor electrodes formed on the peripheral circuit region to penetrate at least a portion of the insulating layer in the first direction, the plurality of capacitor electrodes extending parallel to the channel holes. The plurality of capacitor electrodes are spaced apart from one another in a second direction parallel to the substrate, and the insulating layer is interposed between a pair of adjacent capacitor electrodes from among the plurality of capacitor electrodes.
US09659953B2	HKMG high voltage CMOS for embedded non-volatile memory The present disclosure relates to a structure and method for embedding a non-volatile memory (NVM) in a HKMG (high-κ metal gate) integrated circuit which includes a high voltage (HV) HKMG transistor. NVM devices (e.g., flash memory) are operated at high voltages for its read and write operations and hence a HV device is necessary for integrated circuits involving non-volatile embedded memory and HKMG logic circuits. Forming a HV HKMG circuit along with the HKMG periphery circuit reduces the need for additional boundaries between the HV transistor and rest of the periphery circuit. This method further helps reduce divot issue and reduce cell size.
US09659948B2	Semiconductor device and method of fabricating semiconductor device A semiconductor device includes a substrate with a memory region and a logic region, a logic gate stack, and a non-volatile gate stack. The substrate has a recess disposed in the memory region. The logic gate stack is disposed in the logic region and has a first top surface. The non-volatile gate stack is disposed in the recess and has a second top surface. The second top surface is lower than the first top surface by a step height.
US09659939B1	Integrated circuit having MIM capacitor with refractory metal silicided strap and method to fabricate same A method includes forming a trench in a Silicon substrate; depositing metal on sidewalls and a bottom of the trench; annealing to react the metal with underlying Si and form metal silicide adjacent to sidewalls and bottom of the trench; removing unreacted metal and depositing a dielectric layer on the metal silicide, a metal layer over the dielectric layer and polysilicon to fill a remainder of the trench thereby forming top plate electrode of a MIM capacitor. The method further forms a transistor adjacent to a top of the trench, where the transistor is connected to the top plate electrode of the MIM capacitor via a strap interface that comprises a portion of the metal silicide layer at the top of the trench. The portion of the metal silicide layer can be disposed in an SOI layer, and silicide in the Si substrate forms a bottom plate of the capacitor.
US09659937B2	Semiconductor process of forming metal gates with different threshold voltages and semiconductor structure thereof A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.
US09659936B2	Layout construction for addressing electromigration A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.
US09659935B2	Dielectric liner added after contact etch before silicide formation A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.
US09659934B2	Methods and apparatus for quantum point contacts in CMOS processes Methods and apparatus for quantum point contacts. In an arrangement, a quantum point contact device includes at least one well region in a portion of a semiconductor substrate and doped to a first conductivity type; a gate structure disposed on a surface of the semiconductor substrate; the gate structure further comprising a quantum point contact formed in a constricted area, the constricted area having a width and a length arranged so that a maximum dimension is less than a predetermined distance equal to about 35 nanometers; a drain/source region in the well region doped to a second conductivity type opposite the first conductivity type; a source/drain region in the well region doped to the second conductivity type; a first and second lightly doped drain region in the at least one well region. Additional methods and apparatus are disclosed.
US09659931B2	Fin cut on sit level A method of forming semiconductor fins with variable pitches of arbitrary values in a sidewall image transfer (SIT) process is provided. After forming an array of first mandrel structures with a constant pitch and removing at least one first mandrel structure form the array, a set of second mandrel structures are formed overlapping the first mandrel structures. The combination of the first mandrel structures and the second mandrel structures defines pitches of sidewall spacer patterns to be subsequently formed.
US09659929B2	Semiconductor device with enhancement and depletion FinFET cells A semiconductor device includes enhancement FinFET cells and depletion FinFET cells. The enhancement FinFET cells include first gate structures separating first semiconductor fins. The depletion FinFET cells include second gate structures separating second semiconductor fins. Between the first and second gate structures a connection structure separates the first semiconductor fins from the second semiconductor fins. The connection structure has a specific conductance which is higher than a specific conductance in the second semiconductor fins.
US09659927B2	Junction barrier Schottky rectifier A junction barrier Schottky rectifier with first and second drift layer sections, wherein a peak net doping concentration of the first section is at least two times lower than a minimum net doping concentration of the second section. For each emitter region the first section includes a layer which is in contact with the respective emitter region to form a pn-junction between the first section and the respective emitter region, wherein the thickness of this layer in a direction perpendicular to the interface between the first section and the respective emitter region is at least 0.1 μm. The JBS rectifier has a transition from unipolar to bipolar conduction mode at a lower forward bias due to lowering of electrostatic forces otherwise impairing the transport of electrons toward the emitter regions under forward bias conditions, and with reduced snap-back phenomenon.
US09659925B2	Display panel A display panel includes a substrate, a first stacking unit, and a second stacking unit. The first stacking unit is disposed on the substrate and connected to a scan line. The first stacking unit includes a first conducting layer, a second conducting layer, at least one first through hole, and a first protruding portion. The first conducting layer is interposed between the second conducting layer and the substrate. The first through hole connects the first conducting layer and the second conducting layer. The position of the first protruding portion is relative to the position of the second protruding portion.
US09659915B2	Lighting module with semiconductor light sources and carrier plate Various embodiments may relate to a lighting module which is equipped with several semiconductor light sources, in particular LED-chips and includes a metallic carrier plate. Several metallic carrier substrates are arranged on the carrier plate and are electrically insulated therefrom. At least one semiconductor light source is arranged on the carrier substrates and the carrier substrates are electrically connected in series.
US09659910B1	Manufacturing methods semiconductor packages including through mold connectors A semiconductor package structure and a method for manufacturing the same are provided. According to the method, a first mold layer is formed to cover a first semiconductor chip and a first bumps. A portion of the first mold layer is removed to expose top portions of the first bumps and second bumps are disposed to be connected to each of the first bumps. A second mold layer is formed, and the second mold layer is recessed to form through mold connectors that substantially penetrate the second mold layer with the second bumps disposed on the first bumps.
US09659907B2	Double side mounting memory integration in thin low warpage fanout package Packages and methods of formation are described. In an embodiment, a package includes a redistribution layer (RDL) formed directly on a top die, and a bottom die mounted on a back surface of the RDL.
US09659900B2	Semiconductor device having a die and through-substrate via Semiconductor devices are described that have a through-substrate via formed therein. In one or more implementations, the semiconductor devices include a semiconductor wafer and an integrated circuit die bonded together with an adhesive material. The semiconductor wafer and the integrated circuit die include one or more integrated circuits formed therein. The integrated circuits are connected to one or more conductive layers deployed over the surfaces of the semiconductor wafer and an integrated circuit die. A via is formed through the semiconductor wafer and the patterned adhesive material so that an electrical interconnection can be formed between the integrated circuits formed in the semiconductor wafer and the integrated circuits formed in the integrated circuit die. The via includes a conductive material that furnishes the electrical interconnection between the semiconductor wafer and the integrated circuit die.
US09659898B1	Apparatuses, systems, and methods for die attach coatings for semiconductor packages Embodiments of the present disclosure are directed towards apparatuses, systems, and methods for die attach coatings for semiconductor packages. In one embodiment, a die may be coupled with a substrate by a die attach and a coating may be applied to an edge of the die attach.
US09659896B2	Interconnect structures for wafer level package and methods of forming same A method for forming a device package includes forming a molding compound around a plurality of dies and laminating a polymer layer over the dies. A top surface of the dies is covered by a film layer while the molding compound is formed, and the polymer layer extends laterally past edge portions of the dies. The method further includes forming a conductive via in the polymer layer, wherein the conductive via is electrically connected to a contact pad at a top surface of one of the dies.
US09659891B2	Semiconductor device having a boundary structure, a package on package structure, and a method of making A semiconductor device includes a substrate and a first conductive pad on a top surface of the substrate. The semiconductor device further includes a boundary structure on the top surface of the substrate around the conductive pad.
US09659883B2	Thermally curable resin sheet for sealing semiconductor chip, and method for manufacturing semiconductor package The present invention provides a thermally curable resin sheet for sealing a semiconductor chip having excellent reliability and storability while being reduced in warpage deformation due to the volume shrinkage of the thermally curable resin sheet, and a method for manufacturing a semiconductor package. The present invention relates to a thermally curable resin sheet for sealing a semiconductor chip, wherein an activation energy (Ea) satisfies the following formula (1), a glass transition temperature of a product thermally cured at 150° C. for 1 hour is 125° C. or higher, and a thermal expansion coefficient α [ppm/K] of the thermally cured product at the glass transition temperature or lower and a storage modulus E′ [GPa] at 25° C. of the thermally cured product satisfy the following formula (2): 30≦Ea≦120 [kJ/mol] (1); and 10,000≦α×E′≦300,000 [Pa/K] (2).
US09659882B2	System, method and apparatus to relieve stresses in a semiconductor die caused by uneven internal metallization layers A system, method and apparatus for making a semiconductor die includes forming multiple semiconductor devices in a respective portion of a semiconductor wafer. An electrical interconnect structure is formed over the semiconductor devices and provide electrical connections to the semiconductor devices. The electrical interconnect structure including one or more metallization layers. Each of the metallization layers includes conductive lines. At least one portion of at least one of the metallization layers includes a density of the conductive lines that varies as compared to the other portions of the metallization layers. At least one support structure is formed in the electrical interconnect structure. The semiconductor wafer can be a thinned semiconductor wafer.
US09659881B2	Semiconductor structure including a substrate and a semiconductor chip with matching coefficients of thermal expansion A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate comprising a recess portion filled with a conductive material; a conductive trace overlying and contacting the conductive material; a conductive pillar disposed on the conductive trace and over the recess portion of the substrate; and a semiconductor chip disposed on the conductive pillar, wherein the elastic modulus of the substrate is of about 3 to about 10 GPa at about 20 to about 30° C. and of about 1 to about 5 GPa at about 250 to about 270° C.
US09659880B2	Semiconductor device A semiconductor device includes a wiring substrate, a semiconductor element mounted on an upper surface of a wiring substrate, and a magnetic shield arranged above the upper surface of the wiring substrate to cover an upper side of the semiconductor element. The magnetic shield is formed from a soft magnetic material and includes inclined faces that are inclined straight with respect to the upper surface of the wiring substrate at a portion overlapped with the semiconductor element in a plan view.
US09659877B2	Shielding device One aspect of the invention relates to a shielding device for shielding from electromagnetic radiation, including a shielding base element, a shielding cover element and a shielding lateral element for electrically connecting the base element to the cover element in such that a circuit part to be shielded is arranged within the shielding elements. Since at least one partial section of the shielding elements includes a semiconductor material, a shielding device can be realized completely and cost-effectively in an integrated circuit.
US09659874B2	Method of forming deep trench and deep trench isolation structure A method of forming a deep trench in a semiconductor substrate includes: forming a first mask pattern over the semiconductor substrate, in which the first mask pattern has a first opening exposing a portion of the semiconductor substrate; forming a second mask pattern over the first mask pattern, in which the second mask pattern has a second opening substantially aligned with the first opening to expose the portion of the semiconductor substrate, and the second opening has a width greater than a width of the first opening to further expose a portion of the first mask pattern; and removing the portion of the semiconductor substrate, the portion of first mask pattern and another portion of the semiconductor substrate beneath the portion of the first mask pattern to form the deep trench.
US09659872B2	Manufacturing method for semiconductor device and semiconductor device A step of forming a connecting member configured to electrically connect a first conductive line and a second conductive line includes a phase of perforating a laminate from a first semiconductor wafer to form a plurality of connection holes that reach the second conductive line and a phase of filling the plurality of penetrating connection holes with a conductive material to form conductive sections in contact with the second conductive line.
US09659865B2	Field-effect transistor, method of manufacturing the same, and radio-frequency device There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.
US09659860B2	Method and structure to contact tight pitch conductive layers with guided vias An apparatus including a circuit substrate; a first interconnect layer in a first plane on the substrate and a second interconnect layer in a different second plane on the substrate; and a hardmask layer separating the first interconnect layer and the second interconnect layer, wherein the hardmask layer comprises alternating guide sections comprising different hard mask materials, and a via guide. A method including forming a dielectric layer on an integrated circuit structure; forming a first interconnect layer having interconnect lines in the dielectric layer; forming a hardmask layer on a surface of the dielectric layer, the hardmask layer comprising alternating hardmask materials which form guide sections over the interconnect lines; forming a via guide in one of the guide sections; and forming a second interconnect layer over the hardmask guide layer which is electrically connected to one of the interconnect lines through the via guide.
US09659858B2	Low-stress vias A component can include a substrate having a front surface and a rear surface remote therefrom, an opening extending from the rear surface towards the front surface, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The opening can define an inner surface between the front and rear surfaces. The conductive via can include a first metal layer overlying the inner surface and a second metal region overlying the first metal layer and electrically coupled to the first metal layer. The second metal region can have a CTE greater than a CTE of the first metal layer. The conductive via can have an effective CTE across a diameter of the conductive via that is less than 80% of the CTE of the second metal region.
US09659848B1	Stiffened wires for offset BVA A component can include a generally planar element, a reinforcing dielectric layer overlying the generally planar element, an encapsulation overlying the reinforcing dielectric layer, and a plurality of wire bonds. Each wire bond can have a tip at a major surface of the encapsulation. The wire bonds can have first portions extending within the reinforcing dielectric layer. The first portions of at least some of the wire bonds can have bends that change an extension direction of the respective wire bond. The reinforcing dielectric layer can have protruding regions surrounding respective ones of the wire bonds, the protruding regions extending to greater peak heights from the first surface of the generally planar element than portions of the reinforcing dielectric layer between adjacent ones of the protruding regions. The peak heights of the protruding regions can coincide with points of contact between the reinforcing dielectric layer and individual wire bonds.
US09659845B2	Power quad flat no-lead (PQFN) package in a single shunt inverter circuit A power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC.
US09659844B2	Semiconductor die substrate with integral heat sink An integrated circuit device includes a semiconductor substrate with a top surface, a bottom surface opposite the top surface and an intermediate portion positioned between the top and bottom surfaces. The device also includes interior substrate surfaces defined by at least one void extending from the bottom surface to the intermediate portion.
US09659843B2	Lead frame strip with molding compound channels A lead frame strip has a plurality of unit lead frames. Each of the unit lead frames has a periphery structure connecting adjacent ones of the unit lead frames, a die paddle inside of the periphery structure, a plurality of leads connected to the periphery structure and extending towards the die paddle, and a molding compound channel in the periphery structure configured to guide liquefied molding material. The lead frame strip is processed by attaching a semiconductor die to each of the die paddles, electrically connecting each of the semiconductor dies to the leads, and forming a liquefied molding compound on each of the unit lead frames. The liquefied molding compound is formed such that the liquefied molding compound encapsulates the semiconductor dies and flows into the molding compound channels thereby forming molding extensions that extend onto the periphery structures.
US09659840B2	Process flow for a combined CA and TSV oxide deposition A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed. Embodiments include providing a gate stack, with source/drain regions at opposite sides thereof, and an STI layer on a silicon substrate; forming a TSV trench, laterally separated from the gate stack, through the STI layer and the silicon substrate; forming an isolation layer on sidewalls and a bottom surface of the TSV trench and over the gate stack, the STI layer, and the silicon substrate; forming a TSV in the TSV trench; forming a dielectric cap over the isolation layer and the TSV; and forming a source/drain contact through the dielectric cap and the isolation layer down to the source/drain contract regions.
US09659838B1	Integration of chip level micro-fluidic cooling in chip packages for heat flux removal An electronic chip package including a base defining a fluid inlet opening for receiving pressurized fluid from a fluid source and a fluid outlet opening. A dielectric body is arranged on the base and configured to support an electronic device. The dielectric body comprises a coolant flow chamber formed in a first surface thereof, and a plurality of impingement openings formed within the coolant flow chamber. The plurality of impingement openings are in communication with the fluid inlet opening of the base for generating a plurality of fluid streams to be expelled into the coolant flow chamber. The body further comprises a coolant return port formed within the coolant flow chamber and in communication with the fluid outlet opening of the base.
US09659836B2	Heat dissipation structure, fabricating method, and electronic apparatus Disclosed is a heat dissipation structure that includes a plurality of linear structures made of carbon, each of the linear structures having at least one of a first end and a second end being bent, and a coating layer formed on a surface of each of the linear structures, the coating layer having a part covering the other one of the first ends and the second ends of the linear structures, a thickness of the part allowing the corresponding linear structures to be plastically deformable.
US09659833B2	Semiconductor packages, methods of manufacturing the same, electronic systems including the same, and memory cards including the same A semiconductor package includes an adhesive member disposed on a package substrate to have a trapezoid cross-section view, and a semiconductor chip disposed on the adhesive member and attached to the package substrate by the adhesive member. The semiconductor chip has a first surface and a second surface facing the first surface, and the second surface of the semiconductor chip contacts the adhesive member. The semiconductor chip includes a tension supplement pattern attached to the second surface and spaced apart from the package substrate.
US09659832B2	Reactive hot-melt adhesive for use on electronics The disclosure relates to a method of making an electronic assembly with a reactive hot-melt adhesive composition that include an atmospheric curing prepolymer and optionally a thermoplastic component with a softening point of at least about 120° C., and the electronic assembly made therewith.
US09659831B2	Methods and structures for detecting low strength in an interlayer dielectric structure A method for manufacturing a semiconductor device is disclosed. The method includes generating a thermo-mechanical stress within a plurality of layers of a wafer, and after generating the thermo-mechanical stress, testing an interfacial strength level associated with one or more of the plurality of layers.
US09659819B2	Interconnects for stacked non-volatile memory device and method A method of forming a memory device includes providing a substrate having a surface region, defining a cell region and first and second peripheral regions, sequentially forming a first dielectric material, a first wiring structure for a first array of devices, and a second dielectric material over the surface region, forming an opening region in the first peripheral region, the opening region extending in a portion of at least the first and second dielectric materials to expose portions of the first wiring structure and the substrate, forming a second wiring material that is overlying the second dielectric material and fills the opening region to form a vertical interconnect structure in the first peripheral region, and forming a second wiring structure from the second wiring material for a second array of devices, the first and second wiring structures being separated from each other and electrically connected by the vertical interconnect structure.
US09659816B2	Pattern forming method A pattern forming method in an embodiment includes forming, on or above a substrate, a block copolymer layer containing a first polymer and a second polymer having lower surface energy than the first polymer, heat treating the block copolymer layer to separate the block copolymer layer into a first phase containing the first polymer and a second phase containing the second polymer, and using an atomic layer deposition process, selectively forming a metal layer on the first phase and selectively removing the second phase.
US09659814B2	Doping control of metal nitride films Described are methods for controlling the doping of metal nitride films such as TaN, TiN and MnN. The temperature during deposition of the metal nitride film may be controlled to provide a film density that permits a desired amount of doping. Dopants may include Ru, Cu, Co, Mn, Mo, Al, Mg, Cr, Nb, Ta, Ti and V. The metal nitride film may optionally be exposed to plasma treatment after doping.
US09659811B1	Manufacturing method of semiconductor device A method of forming a semiconductor device includes forming a low-k dielectric layer over a substrate and forming a first dielectric layer on the low-k dielectric layer. A first metal hard mask layer is formed on the first dielectric layer, and a second dielectric layer is formed on the first metal hard mask layer. A second metal hard mask layer is formed on the second dielectric layer, and a first trench opening is formed in the second metal hard mask layer and the second dielectric layer exposing the first metal hard mask layer. A first via opening is formed in the exposed first metal hard mask layer in the first trench opening, and the first trench opening and first via opening are extended into the low-k dielectric layer to form a first trench and a first via.
US09659800B2	Substrate storage container and substrate storage container mounting table In accordance with an embodiment, a substrate storage container includes first and second cases, a lid and a moving unit. The first case is provided with an opening to take in or out a substrate. The lid closes the opening. The second case can move in a first direction crossing a surface of the first case. The opening is provided on the surface. The moving unit moves the second case in the first direction in response to the opening of the lid.
US09659795B2	Foreign matter removal device and foreign matter removal method A device includes a jig having a plate with through-holes formed therein and also having a frame formed on the plate so as to be able to accommodate a plurality of semiconductor chips in spaced relationship, a foreign matter capture member having a first charge section with a first flat surface and a second charge section with a second flat surface, the second charge section being insulated from the first charge section, charging means for positively charging the first flat surface and negatively charging the second flat surface, and sliding means for causing either the jig or the foreign matter capture member to slide relative to the other in such a manner that the through-holes of the jig are spaced a predetermined distance from the first and second flat surfaces. The through-holes are formed in different regions defined and surrounded by the frame.
US09659792B2	Processing systems and methods for halide scavenging Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
US09659790B2	Method of forming pattern and method of manufacturing integrated circuit device by using the same A method of forming a pattern, the method including forming a mask layer on a feature layer on a substrate; forming guides regularly arranged with a first pitch on the mask layer in a first region and dummy guides regularly arranged with the first pitch on the mask layer in a second region spaced apart from the first region with a separation region therebetween, the separation region having a width greater than the first pitch; forming a block copolymer layer on the mask layer; phase-separating the block copolymer layer to form a self-assembled layer; forming a mask pattern by etching the mask layer using the self-assembled layer; and patterning the feature layer by transferring a shape of the mask pattern to the feature layer in the first region while blocking the shape of the mask pattern from being transferred to the feature layer in the second region.
US09659787B2	High-purity 2-fluorobutane The present invention is a high-purity 2-fluorobutane having a purity of 99.9 vol % or more and a butene content of 1,000 ppm by volume or less, and a method for using the high-purity 2-fluorobutane as a dry etching gas. According to the present invention, a high-purity 2-fluorobutane that is suitable as a plasma reaction gas for semiconductors is provided.
US09659786B2	Gate cut with high selectivity to preserve interlevel dielectric layer A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
US09659778B2	Methods of fabricating semiconductor devices and structures thereof Methods of fabricating semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a gate material stack over a substrate having a first region and a second region. The gate material stack includes a semiconductive gate material. A thickness is altered or a substance is introduced to the semiconductive gate material in the first region or the second region of the substrate. The gate material stack is patterned in the first region and the second region resulting in a first transistor in the first region of the substrate comprising an NMOS FET of a CMOS device and a second transistor in the second region of the substrate comprising an NMOS FET of the CMOS device. The first transistor has a first threshold voltage and the second transistor has a second threshold voltage different than the first threshold voltage.
US09659769B1	Tensile dielectric films using UV curing A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. UV curing of as-deposited PECVD silicon nitride films, for example, has been shown to produce films with stresses of at least 1.65 E10 dynes/cm2. Other dielectric capping layer film materials show similar results. In transistor implementations, the stress from a source/drain region capping layer composed of such a film is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in the NMOS channel.
US09659768B2	Focused radiation beam induced thin film deposition A method of depositing a material on a surface is disclosed. The method includes focusing a radiation beam on the surface and introducing a precursor gas near the surface wherein the precursor gas forms the material on the surface upon radiation by the radiation beam. The method further includes introducing an assistant gas near the surface wherein the assistant gas produces nitric oxide radicals upon radiation by the radiation beam. The nitric oxide radicals facilitate the dissociation process of the precursor gas and reduce contaminants in the deposited material.
US09659765B2	Enhancement of modulus and hardness for UV-cured ultra low-k dielectric films Embodiments described herein generally relate to methods for processing a dielectric film on a substrate with UV energy. In one embodiment, a precursor film is deposited on the substrate, and the precursor film includes a plurality of porogen molecules. The precursor film is first exposed to UV energy at a first temperature to initiate a cross-linking process. After a first predetermined time, the temperature of the precursor film is increased to a second temperature for a second predetermined time to remove porogen molecules and to continue the cross-linking process. The resulting film is a porous low-k dielectric film having improved elastic modulus and hardness.
US09659764B2	Method of controlled crack propagation for material cleavage using electromagnetic forces To address the needs in the art, a method of cleaving substrate material that includes forming an initial crack in a bulk substrate material, where the crack is aligned along a cleaving plane of the bulk substrate material, aligning the cleaving plane between two parallel electrodes in a controlled environment, wherein the parallel electrodes include a top electrode and a bottom electrode, where the cleaving plane is parallel with the two parallel electrodes, where a bottom portion of the bulk substrate material is physically and electrically connected to the bottom electrode, and applying a voltage across the two parallel electrodes, where the voltage is at least 50 kV and establishes a uniform electromagnetic force on the top surface of the bulk substrate material, where the electromagnetic force is capable of inducing crack propagation along the cleaving plane and separating a cleaved substrate material from the bulk substrate material.
US09659762B2	Amalgam balls having an alloy coating Energy-saving lamps contain a gas filling of mercury vapor and argon in a gas discharge bulb. Amalgam balls are used for filling the gas discharge bulb with mercury. Novel coated balls whose operating life in the case of automatic metered introduction is increased by coating of the balls with an alloy powder and conglutination of the amalgam balls during storage and processing is prevented are proposed.
US09659759B2	Quantitation of structural isomers using MALDI MS/MS The present invention relates to a quantitative determination of structural isomers implicated in diseases, the said process is completely independent of chromatographic separation, internal standard, and labeled isotopic references. Further, the present invention provides a diagnostic kit for quantitative determination of structural isomers.
US09659758B2	Coils utilized in vapor deposition applications and methods of production A coil assembly for utilization in a vapor deposition system is described herein that includes at least one subject coil having a length, a height, an inside edge, an outside edge and a thickness, wherein the thickness of the subject coil is measured as the distance between the inside edge and the outside edge and wherein at least part of the thickness of the subject coil is reduced by at least 20% as compared to a reference coil. A coil assembly is also described herein for utilization in a vapor deposition system that includes at least one subject coil having a length, a height, an inside edge, an outside edge, and a thickness, wherein the thickness of the subject coil is measured as the distance between the inside edge and the outside edge and wherein at least part of the height of at least part of the subject coil is reduced by at least 20% as compared to the height of a reference coil.
US09659756B2	Plasma etching apparatus and plasma cleaning method A plasma etching apparatus includes an electrostatic chuck and an etching gas supply unit for supplying an etching gas to a processing space between a first and a second electrode to perform a dry etching process on the target object. The apparatus further includes a cleaning gas supply unit for supplying a cleaning gas to a processing space; a first high frequency power supply unit for supplying a first high frequency power to the first electrode; and a controller for controlling the first high frequency power supply unit such that a first period during which the first high frequency power has a first amplitude that generates the plasma and a second period during which the first high frequency power has a second amplitude that generates substantially no plasma are alternately repeated at a specific cycle when the plasma cleaning is performed in the processing chamber without the target object.
US09659748B2	Treating biomass Methods and systems are described for processing cellulosic and lignocellulosic materials and useful intermediates and products, such as energy and fuels. For example, irradiating methods and systems are described to aid in the processing of the cellulosic and lignocellulosic materials. The electron beam accelerator has multiple windows foils and these foils are cooled with cooling gas. In one configuration a secondary foil is integral to the electron beam accelerator and in another configuration the secondary foil is part of the enclosure for the biomass conveying system.
US09659744B2	Charged particle beam apparatus and inspection method using the same A charged particle beam apparatus makes it possible to acquire information in the cross-sectional direction (depth direction) of a sample having an internal structure in a nondestructive manner with reduced damage. Further, the apparatus makes it possible to analyze the depth and/or dimensions in the depth direction of the internal structure. The charged particle beam apparatus includes: a means for providing a time base for control signals; a means for applying a charged particle beam to a sample in synchronization with the time base and controlling an irradiation position; a means for analyzing the emission characteristics of an emission electron from the sample from a detection signal of the emission electron; and a means for analyzing the electrical characteristics or cross-sectional morphological characteristics of the sample based on the emission characteristics.
US09659742B2	X-ray tube and method of manufacturing the same According to one embodiment, an X-ray tube includes an envelope with an opening, an X-ray transmission assembly mounted on the envelope and vacuum-tightly blocking the opening, a cathode and an anode target. The X-ray transmission assembly includes a window frame, an X-ray transmission window, an X-ray-resistive resin film, a sealing member and a dry gas. The X-ray transmission window is formed of a beryllium thin plate, accommodated in the window frame, and configured to maintain, along with the window frame, a vacuum-tight state inside the envelope. The X-ray-resistive resin film forms a space inside along with the window frame and the X-ray transmission window. The dry gas fills the space.
US09659739B2	Blanking of electron beam during dynamic focal spot jumping in circumferential direction of a rotating anode disk of an X-ray tube An apparatus (210) and method for total or partial blanking of an electron beam (e) during a jump between the 2 or more positions of a dynamic focal spot (FP) movement in circumferential direction of the electron beam impinging on the focal track (FPTR) of a rotating target disk (230) of a X-ray tube (110). Alternatively the focal spot size can be increased during this short time interval. Overheating of the anode at the focal spot can be prevented.
US09659738B2	X-ray source and the use thereof and method for producing X-rays An x-ray source comprising a housing, in which a target in the form of an ionized cloud based on metal vapor is provided. The ionized cloud can be excited by means of an electron beam for emitting monochromatic x-rays. The low atom density advantageously produces only a little braking radiation. The robustness of the plasma with respect to the inevitable thermal energy input is also advantageous with respect to the solid target materials. The cloud can be filled at any time with target material which can be vaporized by means of an electric arc. A method for producing x-rays with the above-mentioned x-ray source is also provided. The use of an x-ray source for emitting monochromatic x-rays for x-raying a body is further provided.
US09659737B2	Phosphor coating for irregular surfaces and method for creating phosphor coatings Microstructured, irregular surfaces pose special challenges but coatings of the invention can uniformly coat irregular and microstructured surfaces with one or more thin layers of phosphor. Preferred embodiment coatings are used in microcavity plasma devices and the substrate is, for example, a device electrode with a patterned and microstructured dielectric surface. A method for forming a thin encapsulated phosphor coating of the invention applies a uniform paste of metal or polymer layer to the substrate. In another embodiment, a low temperature melting point metal is deposited on the substrate. Polymer particles are deposited on a metal layer, or a mixture of a phosphor particles and a solvent are deposited onto the uniform glass, metal or polymer layer. Sequential soft and hard baking with temperatures controlled to drive off the solvent will then soften or melt the lowest melting point constituents of the glass, metal or polymer layer, partially or fully embed the phosphor particles into glass, polymer, or metal layers, which partially or fully encapsulate the phosphor particles and/or serve to anchor the particles to a surface.
US09659734B2	Electronic device multi-layer graphene grid A vacuum electronic device includes a multi-layer graphene grid that includes at least two layers of graphene, where the transmission of electrons through the multi-layer graphene grid can be tuned by varying the parameters of the vacuum electronic device such as the number of graphene layers, relative positions of the electrodes, voltage biases applied to the electrodes, and other device parameters.
US09659732B2	Partially insulated cathode A partially-insulated cathode for exciting plasma in a plasma chamber is provided. The partially-insulated cathode includes a conductive structure enclosing a cavity having a cavity surface and an insulating material contiguously covering a portion of the cavity surface from the cavity opening up to an insulation height that is less than a cavity height. Cross-sections of the cavity in X-Y planes have at least one respective cavity-width. A cavity opening has a diameter less than a minimum cavity-width of the at least one cavity-width.
US09659730B2	Apparatus and method for sectioning the phase conductors of an electric power distribution network The invention relates to an apparatus (50) for sectioning the phase conductors (L1, L2, L3) of a multi-phase electric power distribution network (NET) comprising a plurality of disconnectors (1, 2, 3), each disconnector being operatively associated to a related said phase conductor and comprising switching means (S) for sectioning a related phase conductor and a control unit (CU) that is capable of controlling said switching means and is capable of wireless communicating with remote devices. The control units of said disconnectors (1, 2, 3) execute different managing procedure depending on the operating status of said electric power distribution network. In a further aspect, the invention relates to a control system for executing the above described method.
US09659727B2	Switch A switch capable of easily accomplishing current cutoff roles required for a high-voltage switch, and which has a short breaking time. The switch includes pressure housings filled with an insulative medium, a plurality of contactors each including a contact, a plurality of operation units actuating the contacts, an insulative spacer dividing the interiors of the pressure housings into the same number of internal spaces as the number of contacts, and an electrode passing completely through the insulative spacer and fastened to the insulative spacer. The contactor is provided one by one for each internal space, and all contacts are electrically connected in series via the electrode, and the operation units actuate the corresponding contacts, respectively.
US09659724B2	Key apparatus for electronic appliances A key apparatus of an electronic device is provided. The key apparatus includes a housing having a cylindrical portion, the cylindrical portion including an upper portion and a lower portion, the upper portion and the lower portion being open, a knob including a circular-plate portion, the circular plate portion having a concavo-convex portion, the concavo-convex portion including a concave portion and a convex portion arranged alternately in a circular shape and an extension portion extended from the circular-plate portion in a downward direction and inserted into a hollow of the cylindrical portion, and the knob moves on the circular-plate portion, an anti-deviation unit configured to prevent the knob from being deviated from the cylindrical portion, an elastic configured to elastically press the concavo-convex portion at a lower side of the circular-plate portion, and a switch connected to the extension portion and switches over movement of the extension portion is delivered.
US09659723B2	Accessory controller with switch module An accessory may be provided with a button controller having a microphone and switches. Plastic structures for the accessory may be formed by injection molding. Plastic structures may be molded around switch terminals. Switches may be formed using dome switch members and the switch terminals. A printed circuit with components may be mounted in the plastic structures. Recesses in the structures may be configured to receive the dome switch members, components on the printed circuit board, and wires in a cable. A backplate may be used to cover the printed circuit. A layer of plastic may be molded over the backplate to seal an interface created by the backplate. Cable strain relief structures may be molded into the layer of plastic. A lip on the strain relief structures may prevent particles from entering the controller.
US09659722B2	Switching device and related switchgear An exemplary switching device connects and disconnects a power line to and from, respectively, at least an associated electrical load. The switching device includes at least one phase of the switching device having a housing that includes a movable contact configured to be coupled to and separated from a corresponding fixed contact, wherein the at least one phase of the switching device includes an electrically semiconducting assembly having an insulating support operatively associated with a plurality of semiconductor devices, wherein the plurality of semiconductor devices are connected in series and are electrically connected to said fixed contact and to said movable contact, and wherein the semiconducting assembly is configured to be installed into the housing to surround at least a portion of at least one of said fixed contact the movable contact when it is coupled to the fixed contact.
US09659719B2	Display switch A display switch includes a holding portion that formed by a light guide member and adapted to hold a held portion, and a display portion that is integrally formed with the holding portion by the light guide member, is embedded in a light shielding portion, and emits light by guiding a light irradiated to the holding portion.
US09659718B2	High load switch for vehicle A high load switch for a vehicle includes a case having an opening formed at an upper side of the case; a first contact unit disposed at a lower side in the case; a second contact unit disposed at a lower side in the case and disposed directly above the first contact unit; and a contactor having one end fixed to one side in the case, and the other end disposed between the first contact unit and the second contact unit, in which a portion of the contactor between the one end and the other end is continuously formed, and the contactor includes a pusher unit formed by being bent upward so that an intermediate portion thereof penetrates the opening and protrudes, and a reinforcement bead formed on a surface of the contactor, thereby preventing deformation in the contactor and enhancing durability.
US09659716B2	Collector and electrode structure, non-aqueous electrolyte cell, electrical double layer capacitor, lithium ion capacitor, or electrical storage device using same Provided is a technique to confirm the performance of the conductive resin layer of a current collector without actually preparing an electrode structure, a non-aqueous electrolyte battery, an electrical double layer capacitor, a lithium ion capacitor, or an electrical storage device, and to confirm the performance of the conductive resin layer easily with high accuracy by a non-destructive test. A current collector includes a conductive substrate and a resin layer possessing conductivity, the resin layer being formed on at least one side of the conductive substrate. The resin layer possessing conductivity contains a resin and a conductive material containing carbon as a main component. When the color tone of the surface of the resin layer possessing conductivity is specified with Lab* color system, L* is 60 or lower, a* is −1.0 to 1.0, and b* is −1.0 to 3.0.
US09659715B2	Electricity storing/discharging device having multiple input/output electric conductive interface covered by electrode plate pair with multiple-sided electric conductive terminals with a single layer means The present invention provides an electricity storing/discharging device having multiple input/output electric conductive interface covered by electrode plate pair with multiple-sided electric conductive terminals with a single layer means, which is applied in a specific multiple-sided package structure having electrode plate pair with multiple-sided electric conductive terminals and a multiple-directional input/output electric conductive interfaces, so the electrode plate pair is able to be installed on at least one multiple-sided electric conductive terminal and/or at least one side for forming an electric conductive interface so as to transfer electric energy to the exterior.
US09659713B2	Electronic component An electronic component comprises an element body, an external electrode, and an insulating resin coating layer. The element body has a pair of end faces opposed to each other, a pair of principal faces extending so as to connect the pair of end faces and opposed to each other, and a pair of side faces extending so as to connect the pair of principal faces and opposed to each other. The external electrode is formed so as to cover at least a partial region of the principal face and/or a partial region of the side face and has a plating layer comprised of Sn or an Sn alloy. The insulating resin coating layer covers at least the portion of the external electrode formed so as to cover the side face.
US09659712B2	Multilayer ceramic capacitor A multilayer ceramic capacitor includes a body and at least two outer electrodes. The body includes first and second main surfaces, an inner layer portion and first and second outer layer portions. In the inner layer portion, dielectric layers and conductive layers are alternately stacked on each other. The second outer layer portion includes an outer portion and an inner portion. A boundary region adjacent to the inner portion in the outer portion inclines toward the first main surface.
US09659711B2	Capacitor films, methods of manufacture, and articles manufactured therefrom A uniaxially-stretched, high yield extruded film comprising a polyetherimide comprising units derived from polymerization of an aromatic dianhydride with a diamine selected from a meta-phenylene diamine, a para-phenylene diamine, and a combination thereof, wherein the polyetherimide is endcapped with an a substituted or unsubstituted aromatic primary monoamine; and wherein the high yield extruded film comprises at least 90 weight % of the polyetherimide before extrusion.
US09659710B2	Multilayer ceramic component and board having the same A multilayer ceramic component includes a multilayer ceramic capacitor including a ceramic body including a plurality of first and second internal electrodes, and first and second external electrodes, first and second insulation frames respectively including first and second horizontal insulation portions and first and second vertical insulation portions, first and second external conductive electrodes including first and second horizontal conductive portions and first and second vertical conductive portions, first and second internal conductive electrodes disposed on internal surfaces of the first and second vertical insulation portions and connected to the first and second external electrodes, and electrical connection portions.
US09659707B2	Manufacturing device for field-pole magnet and manufacturing method for same A one-piece field-pole magnet is manufactured by filling a gap formed between magnetic pieces placed on a plane with an adhesive or resin. During the process, a pushing member applies a pushing force onto each of the magnet pieces in a thickness direction thereof. The pushing member comprises pushing parts each of which pushes each of the magnet pieces, thereby equalizing the pushing forces applied to the respective magnet pieces.
US09659706B2	Methods for making radially anisotropic thin-film magnetic torroidal cores A method of forming a radially anisotropic toroidal magnetic core includes providing apparatus having a first magnet for providing a radial magnetic field extending across a cavity from an axial spindle to a surrounding second magnetic element, placing a substrate in the cavity, the substrate having a hole fitting around the head of the spindle; and sputter-depositing a film of ferromagnetic material onto the substrate. In an embodiment, the spindle is magnetically coupled to a first pole of the first magnet, the second magnetic element is coupled to a second pole of the first magnet, and a thermally conductive, nonmagnetic, insert separates the spindle and the second magnetic element.
US09659705B2	Method of producing surface-mount inductor A method of producing a surface-mount inductor including an external electrode having high fixing strength with respect to an element body even in a high-humidity environment. The method includes the steps of: winding an electrically-conductive wire to form a coil; forming a core using a sealant primarily containing a metal magnetic powder and a resin in such a manner as to encapsulate the coil in the sealant while allowing each of opposite ends of the coil to be at least partially exposed on a surface of the core; reducing smoothness of a surface of at least a part of a portion of the core on which an external electrode is formed as compared to a surface therearound; and forming the external electrode on the core in such a manner as to be electrically conducted with the coil.
US09659689B2	Monolithic ceramic electronic component A monolithic ceramic electronic component includes a ceramic body including a stack of ceramic layers. Inner electrodes are disposed within the ceramic body and include exposed portions at the end surfaces of the ceramic body. A pair of outer electrodes is arranged on the end surfaces of the ceramic body so as to extend from the end surfaces to the main surfaces and side surfaces of the ceramic body. Each of the outer electrodes includes a lower electrode layer provided on the ceramic body, an intermediate electrode layer located on the lower electrode layer and defined by a plated Ni layer, and an upper electrode layer located on the intermediate electrode layer and defined by a plated Pd layer. A thickness of the intermediate electrode layer on the main surfaces and the side surfaces of the ceramic body is larger than a thickness of the intermediate electrode layer on the end surfaces of the ceramic body.
US09659686B1	Communication cables incorporating twisted pair separators that function as shields Cables incorporating twisted pair separators that function as shields are describes. A cable may include one or more twisted pairs of individually insulated conductors. A respective separator may be associated with at least one of the twisted pairs. The separator may include a dielectric portion positioned between the conductors of the twisted pair and at least one shielding portion that includes electrically conductive material. The shielding portion may extending from the dielectric portion to form a shield around an outer circumference of the twisted pair. Additionally, the cable may include a jacket formed around the twisted pair and the separator.
US09659683B2	Coaxial cable and medical cable using the same A coaxial cable includes a center conductor, and an insulation formed surrounding the center conductor. The insulation includes an insulating tape that includes a mesh layer including a plurality of threads woven and a reinforcement layer attached to the mesh layer. The insulating tape is wound, with an overlap, around the center conductor such that the mesh layer is arranged as an outer peripheral surface.
US09659678B2	Method for removing cesium ions from water The present invention provides a method for efficiently separating cesium ions in a short time from an aqueous solution with the number of human working steps being reduced as much as possible and recovering the cesium ions, and an apparatus therefor.Cesium ions in an aqueous solution are removed by preparing a cesium ion-containing magnetic particle in a cesium-containing aqueous solution and filtering or magnetically separating the magnetic particle.
US09659677B2	Shielding device for substrate edge protection and method of using same A shielding device for shielding an edge of a semiconductor substrate can include a multisided frame defining a perimeter of an enclosed area, and a shield coupled to the frame. The shield may be configured to move between a first position where the shield is retracted to the perimeter and a second position where shield advanced into the enclosed area. A method for processing a semiconductor substrate includes placing a semiconductor substrate in position in an implantation chamber, covering edges of the semiconductor substrate by pushing shields into engagement with the edges, performing an ion implantation procedure, and retracting the shields from the edges.
US09659676B2	Jet pump diffuser stack repair A method of repairing a slip joint on a jet pump assembly between an inlet mixer and a diffuser, with the diffuser having an opening that receives the inlet mixer with a given spacing between an outside diameter of the inlet mixer and an inside diameter of the opening in the diffuser forming an annulus whose spacing is a product of manufacture and vibration wear. The method comprises the steps of remotely accessing the annulus and narrowing a radial dimension of the annulus.
US09659671B2	Controller to detect malfunctioning address of memory device A controller includes an internal memory to store an address and a memory control unit operatively coupled with the internal memory. The memory control unit includes logic to identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device being another semiconductor device separate from the controller, store the malfunctioning address in the internal memory, and transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data storage elements and an indication of an address associated with the malfunctioning address.
US09659669B2	Device and method for repairing memory cell and memory system including the device Provided are a method and an apparatus for repairing a memory cell in a memory test system. A test device detects a fail address by testing a memory device according to a test command, and temporarily stores the fail address in a fail address memory (FAM). The fail address is transmitted to the memory device according to a fail address transmission mode, is temporarily stored in a temporary fail address storage of the memory device, and is then stored in an anti-fuse array, which is a non-volatile storage device. To secure the reliability of data, stored data can be read to verify the data and a verification result can be transmitted in series or in parallel to the test device.
US09659667B2	Circuit for reading one time programmable memory A circuit for reading a one time programmable (OTP) memory includes a controller that receives a read input signal and generates a read delay signal, a read voltage signal, and a read latch signal; a read voltage generator that generates a read voltage based on the read voltage signal and outputs the read voltage to a detecting node; an OTP memory unit cell including a first electrode connected to the detecting node; a first detecting unit that determines a voltage at the detecting node; a determining unit that delays an output signal from the first detecting unit based on the read delay signal; and a latch unit that latches an output signal from the determining unit during a first delay time at a falling edge of the read input signal based on the read latch signal.
US09659666B2	Dynamic memory recovery at the sub-block level A non-volatile flash memory has bit lines spanning multiple blocks grouped into columns, where each block is connected along multiple regular columns and one or more redundancy columns. When there is a local column defect, so that the defect is not at the level of the whole block or global column, the portions of a column at an individual block can be remapped to a portion of the same block along a redundant column. Sections of multiple columns from different blocks can be remapped to the same redundancy column. Then a memory block includes a number of independently accessible sub-blocks, the process can also be implemented at the sub-block level. A dynamic, system level implementation is presented.
US09659665B1	Sensing control signal generation circuit and semiconductor memory device including the same The present invention relates to a sensing control signal generation circuit and a semiconductor memory device including the same. In an embodiment, a semiconductor memory device may include a memory block suitable for including a plurality of memory cells coupled in series and a plurality of cell strings respectively coupled to a plurality of bit lines, page buffers suitable for being coupled to the respective bit lines in response to a sensing control signal and each suitable for sensing a voltage of each of the bit lines transferred to a sensing node and storing data corresponding to the results of the sensing or temporarily storing data to be programmed into a selected memory cell, and a sensing control signal generation unit suitable for generating the sensing control signal having a form of a ramping signal rising at a constant slope during the program operation.
US09659659B2	Semiconductor memory apparatus and data scrambling method using the same A semiconductor memory apparatus and a data processing method are provided. The semiconductor memory apparatus gives consideration to partial page programming and data scrambling, and improves the reliability. In the flash memory of the present invention, when data is programmed to a page n times consecutively, identification information and program information are generated. A scrambled data, the location information and the flag information are programmed to a selected page in a memory array. The location information indicates a storage location for a data scrambling in the page selected based on an input address information. The flag information is used to identify a storage region specified by the location information is programmed.
US09659657B2	Reuse of electrical charge at a semiconductor memory device A semiconductor memory device having a plurality of decoders, wherein each decoder is assigned to a select line, wherein no other decoder is assigned to the select line, each decoder has an output configured to charge the select line to when the decoder is activated and to discharge the select line when said decoder is deactivated. Also, each decoder is configured such that, in case that a first decoder gets deactivated after being activated and a second decoder of the decoders gets activated after being deactivated, the output of the first decoder and the output of the second decoder get connected to a common node for a predefined time interval, so that an electrical charge may be transferred from the select line, to the first decoder is assigned to, to the select line, to which the second decoder is assigned to, before the output of the first decoder gets connected to a reference voltage and the output of the second decoder gets connected to a supply voltage.
US09659654B2	Method to prevent loss of data of a transistor-based memory unit A method to prevent loss of data of transistor-based memory unit including bulk, source and drain formed on bulk and first tunnel oxide, floating gate, second tunnel oxide and control gate stacked up on channel between source and drain is disclosed to include steps of: erasing the floating gate, using weak electric field inject small amount of electrons into floating gate, enabling small amount of electrons to remain in floating gate to keep channel between source and drain electrically conducted, enabling small amount of electrons in floating gate to repel against electrons in first tunnel oxide and second tunnel oxide so as avoid electron accumulation in first tunnel oxide and second tunnel oxide and allow normal data access floating gate, and using electric field of normal write to inject electrons in floating gate so as to prevent channel conduction between source and drain and allow writing data into floating gate.
US09659645B2	Resistive memory device and method of writing data A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.
US09659644B2	Driving method of nonvolatile memory device using variable resistive element Provided is a driving method of a nonvolatile memory device for performing a write operation using a plurality of consecutive write loops. The driving method includes writing data to a plurality of nonvolatile memory cells during a first write loop, and after the first write loop, writing the data to the plurality of nonvolatile memory cells during a second write loop. A first maximum parallel bit size of the first write loop is n bits. A second maximum parallel bit size of the second write loop is m bits. m is greater than n.
US09659642B1	State change detection for two-terminal memory during application of a state-changing stimulus A detection circuit that can detect a two-terminal memory cell changing state. For example, in response to electrical stimuli, a memory cell will change state (e.g., to a highest resistance state), but existing techniques do not detect this state change until after the stimuli is completed and a subsequent sensing operation (e.g., read pulse) is performed. The detection circuit can detect the state change during application of the electrical stimuli that causes the state change.
US09659638B1	Data storage device and the operating method thereof A data storage device includes a nonvolatile memory device including a first plane and a second plane; and a controller configured to provide a read command for reading simultaneously the first plane and the second plane, a first address for accessing the first plane and a second address for accessing the second plane, to the nonvolatile memory device, wherein the nonvolatile memory device reads all page types that should be read from the first plane and the second plane, from each of the first plane and the second plane, according to the read command, the first address and the second address.
US09659637B2	Correlating physical page addresses for soft decision decoding A storage device may include a processor and a memory device including a multilevel memory cell. The processor may correlate a first physical page address and a second physical page address, each address being associated with the multilevel memory cell. The processor also may apply a first read operation to the memory cell to determine a value of a first bit associated with the first physical page address. The processor additionally may apply at least a second read operation to the multilevel memory cell to determine a value of a second bit associated with the second physical page address. The processor may determine, based at least in part on the value of the first bit and the value of the second bit, a soft decision value associated with the second bit. The processor may verify the value of the second bit based at least in part on the soft decision value.
US09659636B2	NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations A YUKAI NAND array comprising multiple strings associated with hierarchical global/local bit lines (GBL/LBL) and each string being associated with one LBL and having adjacent LBL as a dedicated local source line (LSL) without a common source line to connect all strings. Each of the LBLs is interleavingly associated with either an Odd or Even string selected via one pair of dummy cells inserted in each string and is used as one on-chip PCACHE register with full BL-shielding without wasting extra silicon area to allow batch-based multiple concurrent MLC All-BL, All-Vtn-Program and Alternative-WL program, Odd/Even read and verify operations with options of providing individual and common VSL-based Vt-compensation and VLBL compensations to mitigate high WL-WL and BL-BL coupling effects. Bias conditions in each string are provided to correctly sense highly-negative erase-verify voltage, multiple negative program-verify voltages and without VDS punch-through, breakdown and body-effect in both boundary and non-boundary WLs cells.
US09659635B1	Memory array with bit-lines connected to different sub-arrays through jumper structures An integrated circuit structure includes an SRAM array including a first sub-array having a first plurality of rows and a plurality of columns of SRAM cells, and a second sub-array having a second plurality of rows and the plurality of columns of SRAM cells. A first bit-line and a first complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in a column in the first sub-array. A second bit-line and a second complementary bit-line are connected to the first and the second pass-gate MOS devices of SRAM cells in the column in the second sub-array. The first bit-line and the first complementary bit-line are disconnected from the second bit-line and the second complementary bit-line. A sense amplifier circuit is electrically coupled to, and configured to sense, the first bit-line, the first complementary bit-line, the second bit-line, and the second complementary bit-line.
US09659634B2	Methods for operating a FinFET SRAM array A method of operating an SRAM array may include: providing a plurality of bit cells, each of the plurality of bit cells comprising a cross coupled inverter pair; a first pass gate; and a second pass gate. A word line voltage may be applied to the first pass gate and the second pass gate, while a first cell positive voltage supply CVdd may be applied to terminals of the cross coupled inverter pair. The first cell positive voltage supply CVdd may be varied relative to the word line voltage during a selected operation of the plurality of bit cells.
US09659629B2	Sense amplifier driving device A sense amplifier driving device, and more particularly, a technology for improving the post overdriving operation characteristic of a semiconductor device. A sense amplifier driving device includes a driving signal generation block configured to compare a reference voltage set by a voltage trimming signal and a level of a power supply voltage, and generate a pull-up driving signal for controlling an operation of a sense amplifier; and a sense amplifier driving block configured to supply a driving voltage to a pull-up power line of the sense amplifier for an active operation period in correspondence to the pull-up driving signal, the driving signal generation block including a voltage divider configured to divide the power supply voltage, and output a divided voltage; and a voltage comparison section configured to compare the reference voltage and the divided voltage, and output a control signal for controlling an overdriving operation of the sense amplifier.
US09659626B1	Memory refresh operation with page open Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.
US09659623B1	Memory having a plurality of resistive non-volatile memory cells A resistive non-volatile memory (NVMN) cell has three select transistors connected together in series. A first resistive element has a first terminal connected between first and second select transistors and a second terminal. A second resistive element has a first terminal connected between second and third transistors. In a first embodiment, the second terminals of the first and second resistive elements are connected to bit lines. In a second embodiment, the second terminals of the first and second resistive elements are connected to source lines. In the first embodiment, when the center select transistor is conductive, the first and second resistive elements become a resistor-divider. Each of the first and second resistive elements include a magnetic tunnel junction (MTJ).
US09659617B2	Clock control device A clock control device is disclosed, which relates to a technology for changing a rising or falling edge trigger. The clock control device includes: a flip-flop configured to latch data in response to a delay clock signal; and a clock controller configured to output the delay clock signal by delaying a clock signal, and control the data to be triggered at a falling edge of the clock signal when the clock signal is input at a time earlier than the data.
US09659615B1	Semiconductor device comprising pipe latch circuit and auto-precharge signal generation circuit A semiconductor device may include an input/output control signal generation circuit configured to generate at least one input control signal and at least one output control signal from a first control clock in response to a shifting control signal, a bank address latch circuit configured to generate a latch bank address signal by latching at least one bank address in response to the at least one input control signal and the at least one output control signal, a pipe latch circuit configured to generate an auto-precharge latch signal by latching an auto-precharge flag signal in response to the at least one input control signal and the at least one output control signal, and an auto-precharge signal generation circuit configured to generate at least one auto-precharge signal from the auto-precharge latch signal.
US09659609B2	Semiconductor memory apparatus and system using the same A semiconductor memory apparatus includes a command input unit configured to generate an internal command in response to an external command and a selective input unit configured to transmit selection signals to one of a first internal circuit. The selective input unit transmits the selection signals to the first internal circuit when the internal command is not a predetermined command and transmits the selection signals to the second internal circuit when the internal command is the predetermined command.
US09659605B1	Apparatuses and methods for performing corner turn operations using sensing circuitry The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a first group of memory cells coupled to an access line and a plurality of sense lines and a second group of memory cells coupled to a plurality of access lines and a sense line. The example apparatus comprises a controller configured to cause a corner turn operation using sensing circuitry on an element stored in the first group of memory cells resulting in the element being stored in the second group of memory cells.
US09659604B1	Dual-bit 3-T high density MTPROM array A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor having a first common connection, and said second FET transistor and a third FET transistor having a second common connection, said first and second connected FET transistors programmable to store a first bit value, and said second FET and said third connected FET transistors programmable to store a second bit value, wherein said first FET transistor exhibits a low threshold voltage value (LVT), said second FET transistor exhibits an elevated threshold voltage value HVT and said third FET transistor exhibits a threshold value LVT lower than HVT. The MTPM cell enables two bits of information to be stored as default bit values like an electrical fuse. To store opposite bit values, the LVT transistors are programmed such that their threshold voltage is higher than that of HVT.
US09659603B2	Power management circuit for an electronic device A power management circuit for an electronic device sequentially activates and/or deactivates electronic circuits of the electronic device. The power management circuit provides a first group of one or more circuit power management signals to activate and/or deactivate a first electronic circuit from among the electronic circuits. Thereafter, the power management circuit provides a corresponding power management signal from among a second group of the one or more circuit power management signals that corresponds to a portion of the first electronic circuit that has been activated and/or deactivated by the first group of the one or more circuit power management signals to activate and/or deactivate a portion of a second electronic circuit from among the electronic circuits. The power management circuit continues to sequentially provide each of the one or more circuit power management signals in a similar manner until the electronic circuits of the electronic device have been activated and/or deactivated.
US09659602B2	Voltage control integrated circuit devices Voltage control in integrated circuits include a first voltage divider coupled to receive a reference voltage and having an output providing an adjusted reference voltage; an operational amplifier having a first input coupled to receive the output of the first voltage divider, a second input coupled to receive a feedback voltage, and an output; a voltage generation circuit responsive to the output of the operational amplifier and having an output providing an output voltage; and a second voltage divider coupled to receive the output voltage and having an output providing the feedback voltage. The first voltage divider is responsive to first control signals to adjust a voltage level of the adjusted reference voltage. The second voltage divider is responsive to second control signals to adjust a voltage level of the feedback voltage.
US09659601B2	Memory module with packages of stacked memory chips An apparatus is provided that includes a plurality of array dies and at least two die interconnects. The first die interconnect is in electrical communication with a data port of a first array die and a data port of a second array die and not in electrical communication with data ports of a third array die. The second die interconnect is in electrical communication with a data port of the third array die and not in electrical communication with data ports of the first array die and the second array die. The apparatus includes a control die that includes a first data conduit configured to transmit a data signal to the first die interconnect and not to the second die interconnect, and at least a second data conduit configured to transmit the data signal to the second die interconnect and not to the first die interconnect.
US09659594B2	Integrated recording head with selective movement In one example, a head is provided that may include a slider body, a transducer body, a transducer connected to the transducer body, and an interleaver assembly interconnecting the slider body and the transducer body. The interleaver assembly may include an interleaver body to which the transducer body is attached, the interleaver body having a plurality of geometric features that enable temporary deformation of the interleaver body in response to exertion of a force on the interleaver body, and the interleaver body may further include piezoelectric elements positioned in the interleaver body, the piezoelectric elements operable such that, when selectively actuated, the piezoelectric elements exert a force on the interleaver body so as to effect selective movement of the transducer with respect to a surface of a medium.
US09659593B2	Dynamic gain control for use with adaptive equalizers According to one embodiment, a method for processing data includes directing first data through a first FIR gain module in response to a determination that the first data is being read from a magnetic tape medium in an asynchronous mode to control FIR gain of the first data. The method also includes directing second data through a second FIR gain module in response to a determination that the second data is being read from the magnetic tape medium in a synchronous mode to control FIR gain of the second data. Other systems and methods for processing data using dynamic gain control with adaptive equalizers are presented according to more embodiments.
US09659591B1	Polynomial spiral waveguide that facilitates coupling light to a near-field transducer at an oblique angle A recording head includes a near-field transducer located an oblique angle to a media-facing surface. The near-field transducer includes an enlarged portion and a peg extending from the enlarged portion towards the media-facing surface at a normal angle. An input waveguide of the recording head receives energy from an energy source, and an output waveguide delivers the energy to near-field transducer at the oblique angle. The output waveguide is oriented at the oblique angle. A bent waveguide with a polynomial spiral shape joins the input waveguide and the output waveguide.
US09659587B1	Magnetic head having a reader overcoat with DLC and a recessed writer overcoat without DLC A magnetic head includes a slider defining an air bearing surface (ABS) and having a trailing face approximately orthogonal to the ABS. A transducer is disposed on the trailing face and includes a reader and a writer. The writer comprises a non-ferromagnetic writer encapsulate material, and includes a ferromagnetic write pole embedded in the non-ferromagnetic writer encapsulate material. The reader comprises a non-ferromagnetic reader encapsulate material, and includes a magnetoresistive sensor stack embedded in the non-ferromagnetic reader encapsulate material. The magnetic head further includes a novel dual overcoat having a writer overcoat material disposed on the writer, and a reader overcoat material disposed on the reader. The reader overcoat material comprises diamond-like carbon (DLC), and the writer overcoat material does not comprise DLC. An example method for fabricating the novel dual overcoat is also disclosed.
US09659586B1	Reader with free layer experiencing opposite phase-shifted media torques A read sensor that includes an unbalanced synthetic antiferromagnetic (SAF) free layer structure. The unbalanced SAF free layer structure includes a first magnetic layer having a first magnetic moment value and a second magnetic layer having a second magnetic moment value that is different from the first magnetic moment value. A separation layer is included between the first magnetic layer and the second magnetic layer. The first magnetic layer and the second magnetic layer are antiferromagnetically coupled.
US09659583B2	Magnetic recording head having protected reader sensors and near zero recession writer poles An apparatus according to one embodiment includes a module having first and second transducers of different transducer types positioned towards a media facing side of the module. The apparatus also includes a first protection structure for protecting the first transducer. The first protection structure includes a recessed portion of the media facing side adjacent the first transducer. The second transducer is protected by a second protection structure that is different than the first protection structure. The second protection structure includes a recessed portion of the media facing side adjacent the second transducer. An extent of recession of the recessed portion of the media facing side adjacent the second transducer is not as great as an extent of recession of the recessed portion of the media facing side adjacent the first transducer.
US09659582B2	Method of manufacturing an electronic device A method of manufacturing an electronic device includes a positioning step of positioning a first member supporting a laser diode with respect to a second member having a waveguide, a bonding step of bonding the first member and the second member together, and a checking step of checking the accuracy of positioning of the first member with respect to the second member. In the positioning step, the laser diode is energized to allow laser light to be emitted, and the laser light is allowed to be incident on the incidence end of the waveguide. In the bonding step, a bonding material is melted by irradiating the first member with heating light while the laser diode is not energized. In the checking step, the laser diode is energized again.
US09659572B2	Apparatus, process, and program for combining speech and audio data There is provided a speech processing apparatus including: a data obtaining unit which obtains music progression data defining a property of one or more time points or one or more time periods along progression of music; a determining unit which determines an output time point at which a speech is to be output during reproducing the music by utilizing the music progression data obtained by the data obtaining unit; and an audio output unit which outputs the speech at the output time point determined by the determining unit during reproducing the music.
US09659569B2	Audio signal encoder An apparatus comprising: a channel analyzer configured to determine for a first frame of at least one audio signal a set of first frame audio signal multi-channel parameters; a multichannel difference selector configured to select for the first frame groups of elements of the set of first frame audio signal multi-channel parameters based on a value associated with the first frame; and a multichannel parameter encoder configured to generate an encoded first frame audio signal multi-channel parameter based on the selected groups of elements of the set of first frame audio signal multi-channel parameters.
US09659568B2	Method and an apparatus for processing an audio signal A method of decoding an audio signal, and which includes extracting spectral data and a loss signal compensation parameter from an audio signal bitstream; detecting a loss signal based on the spectral data; generating first compensation data corresponding to the loss signal using a random signal based on the loss signal compensation parameter; generating a scale factor by adding a scale factor difference value to a scale factor reference value if the scale factor corresponds to a band quantized to zero, and the scale factor reference value is included in the loss signal compensation parameter; and generating second compensation data by applying the scale factor to the first compensation data.
US09659552B1	Automatic tuning floating bridge for electric stringed instruments A method, computer program product, and system for automatically tuning a stringed instrument. An initial height of a first string of an instrument having a plurality of strings and a floating bridge is determined. The height of the plurality of strings is determined using a bridge sensor. The floating bridge is locked. A frequency of the first string is analyzed. In response to determining the frequency of the first string does not match a predetermined frequency, a tuning peg servo motor to adjust a tuning peg, thereby adjusting a string tension of the first string. The one or more bridge servo motors adjusts a spring tension until the spring tension of the one or more springs equals the string tension of the first string. In response to determining the first string is tuned, the floating bridge is unlocked.
US09659551B1	End blown woodwind harness A woodwind harness that provides support a woodwind musical instrument to relieve fatigue from a musician's arms and shoulders is described. The woodwind harness generally comprises a sternum plate adapted to press against a human sternum with a pair of rigid members extending from the sternum plate and terminating in a hook shaped bend that is arranged and configured to hook over a human shoulder. Between the sternum plate and the hook shaped bend is an elastic cord attached to each of the rigid members. An end-blown woodwind instrument is attached to the elastic cord by way of an attaching means.
US09659550B2	Cymbal sizzle sound enhancer and method A sizzle enhancer device is provided for complimentary use with a cymbal instrument to modify the sound the cymbal produces. The device reversibly fastens to the stand post above the cymbal element and includes an adjustable sizzle element which contacts and vibrates with the cymbal element to product a sizzle sound upon impact of the cymbal element with an object.
US09659546B2	Control apparatus and control method to control external device depending on motion of human body A display apparatus includes a detector configured to detect an infrared ray emitted from a human body; a state signal generator configured to generate a state signal including at least one of a first state signal component indicating that the human body is approaching the detector and a second state signal component indicating that the human body is leaving from the detector in response to an intensity variance of the infrared ray detected with the detector; and a controller configured to start controlling an external device upon detecting the first state signal component from the state signal generated by the state signal generator but to stop controlling the external device upon detecting the second state signal component from the state signal.
US09659545B2	Display apparatus and method of driving the same A display apparatus includes a display panel and a light source part. The display panel includes a first subpixel having a first color, a second subpixel having a second color and a transparent subpixel. The light source part provides a light to the display panel. The light source part includes a first light source generating a first light having a mixed color of the first primary color and the second primary color and a second light source generating a second light having a third primary color. At least one of the first and second light sources are repeatedly turned on and off.
US09659544B2	Luminance suppression power conservation Described herein are systems and methods that reduce power consumption for an electronics device including a display. The systems and methods alter video information in a display area and reduce power for a display device when a graphics item is enlarged and the enlargement threatens to increase perceived luminance for the graphics item or increase aggregate luminance for the display area. Altering the video information reduces the luminance of video information in at least the graphics item when enlarged. This may offset perceived luminance gained by human visual processing when an item increases in size. If the graphics item is smaller than the display area after enlargement, then other video information in the display area may also be altered to conserve power.
US09659541B2	Display panel, display device, and driving method of display device A display panel, a display device and a driving method of the display device, where the display panel includes a pixel structure that includes: in one of two adjacent rows of pixel units, a thin film transistor of a pixel unit in a row electrically connected to a pixel electrode of a pixel unit in the same row adjacently disposed at a first side of the pixel unit; and in the other one of the two adjacent rows of pixel units, a thin film transistor of a pixel unit electrically connected to a pixel electrode of the pixel unit, or electrically connected to a pixel electrode of a pixel unit in the same row adjacently disposed at a second side of the pixel unit; the first side of the thin film transistor being arranged opposite to the second side of the thin film transistor.
US09659537B2	Liquid crystal display device and driving method thereof The disclosure is related to a liquid crystal display device, including a liquid crystal display panel and a gamma generator including a first storage unit storing a group of positive or negative gamma voltage values and a second storage unit storing a group of negative or positive gamma voltage values. The gamma generator periodically obtains the group of the positive or negative gamma voltage values, or the group of the positive or negative gamma voltage values according to a control of a polarity inversion signal. The liquid crystal display panel displays an image according to the group of the positive and/or the group of the negative gamma voltage values. The difference between the disclosure and the current technique is that the cost is decreased effectively; meanwhile, the driving structure is simplified, a wiring area is decreased and it is favorable for a narrow frame design.
US09659534B2	Reducing visual artifacts and reducing power consumption in electrowetting displays Subject matter disclosed herein relates to addressing schemes that reduce visual artifacts and power consumption in electrowetting display devices. The electrowetting display comprises a first substrate and a second substrate opposite to the first substrate, wherein a plurality of pixel regions are defined between the first substrate and the second substrate. The electrowetting display further comprises a first fluid within the pixel regions and a second fluid on the first fluid, wherein the second fluid is immiscible with the first fluid. The electrowetting display also comprises a timing controller that includes a memory. The timing controller is configured to drive the plurality of pixel regions with one or more addressing schemes that control rates of driving the plurality of pixel regions.
US09659531B2	Display device and display device drive method for controlling luminance of RGBW subpixels and a lighting unit In a display device, pixels each including first to fourth subpixels that respectively display first to third primary colors and fourth color are arranged on an image display panel. A lighting unit emits light to the panel from the rear thereof. A control unit calculates a required luminance value for each block of the display surface of the panel based on an input image signal, determines a light source lighting amount of the lighting unit based on luminance distribution information on the lighting unit so as to satisfy the required luminance value, generates luminance information on each pixel based on the luminance distribution information and light source lighting amount, generates an output image signal that drives the subpixels based on the luminance information and input image signal, controls the lighting unit by the light source lighting amount, and controls the panel by the output image signal.
US09659528B2	Organic light emitting display device and method for driving the same A method of compensating driving TFTs in an organic light emitting display device is discussed. According to an embodiment, the method includes applying a varied drain voltage to a drain of a specific driving TFT in one of a plurality of pixels; and compensating the specific driving TFT by the varied drain voltage, so as to maintain a constant drain-source voltage at the specific driving TFT.
US09659520B2	Gamma correction method based on a gamma curve obtained from single or multiple primary-color frames A gamma correction method adapted for a liquid crystal display panel is provided. The gamma correction method includes the following steps. A reference gamma curve is provided. The LCD panel is lighted up with at least one of primary-color frames. Gamma voltages of the primary-color frame are set for the LCD panel based on the reference gamma curve to obtain at least one primary-color gamma curve. The gamma correction is performed on the LCD panel based on the at least one primary-color gamma curve or a linear combination curve of the at least one primary-color gamma curve. By using the gamma correction method, the LCD panel could be allowed to provide good image quality.
US09659519B2	Video-display control device for correcting a video signal and controlling a backlight In a video display control device, a control data generating section allocates a part of a dynamic range of a high gradation region of a video signal to a low gradation region, and a backlight controlling section controls a light emission luminance of a backlight so as to cancel an increase or decrease of a mean luminance of a video displayed on a screen in accordance with an increase or decrease of the mean luminance of a video signal after correction with respect to a mean luminance of the video signal.
US09659518B2	Display panel and display apparatus having interlace and progressive driving methods A method of driving a display panel, the method including analyzing input image data, determining a driving method of the display panel as one of a progressive driving method and an interlace driving method, and rearranging the input image data according to the determined one of the progressive driving method and the interlace driving method.
US09659516B2	Drive device of display panel, display device including the same, and drive method of display panel A drive device of a display panel includes a controller that controls operations of a scanning-control signal output circuit and a common-electrode voltage control circuit, wherein when the controller receives a changeover command that indicates changeover of a scanning order of a plurality of scanning signal lines, the controller controls an operation of the scanning-control signal output circuit so that a scanning order of the plurality of scanning signal lines is changed over between a normal order and a reverse order and controls an operation of the common-electrode voltage control circuit so that a voltage of the common electrode is changed over between a voltage determined in advance for normal-order scan and a voltage determined in advance for reverse-order scan, during a scanning order changeover period as a predetermined period after ending last scanning of a scanning signal line during a frame period in which the changeover command is received.
US09659512B2	Rollable display device A rollable display device includes a flexible display panel that displays an image, a first housing, inside which a first portion of the flexible display panel is storable, a second housing, inside which a second portion of the flexible display panel is storable, a first rotation member inside the first housing, the first portion of the flexible display panel being windable and unwindable on the first rotation member, a second rotation member inside the second housing, the second portion of the flexible display panel being windable and unwindable on the second rotation member, a first rail at one end of the first rotation member, the first rail being defined in the first rotation member to have a spiral shape having two ends, and a first guide part penetrating through the first housing and being inserted in the first rail.
US09659508B2	Microfluidic platform and methods for using the same The present invention provides a microfluidic device which includes at least 3 chambers, a chamber inlet, at least 2 dichotomously branching generations of channels, a channel inlet, and a channel outlet, wherein the channels and the chambers are separated by deformable walls, wherein each wall is lined with at least one cavity, and wherein the cavity is fluidly connected to the channel.
US09659500B2	Safety monitoring in systems of mobile assets Systems and methods for safety monitoring are described. Mobile assets may receive safety monitoring notifications responsive to one or more safety criteria being met. A driver or other user of the mobile asset may be prompted to acknowledge the safety monitoring notification. If the user requests assistance or does not acknowledge the safety monitoring notification, notifications may be communicated to other individuals, e.g. supervisors. In this manner, the safety of, e.g. drivers in a fleet of vehicles may be monitored.
US09659498B2	Exterior mirror assembly with blind zone indicator A mirror reflective element sub-assembly for a vehicular exterior rearview mirror assembly includes a mirror reflective element, a mirror back plate, and a blind zone indication module. The module includes a first portion disposed at an aperture through the back plate and an internal structure that has reflective surfaces and at least one aperture. A circuit board is disposed at a second portion of the housing such that at least one light emitting diode is disposed at a respective aperture of the internal structure. The reflective surfaces are configured so that light emitted by the light emitting diode is generally directed towards the side of the vehicle. The circuit board is disposed at the second portion such that electrically conductive terminals of the circuit board are disposed in a connector portion that is configured to connect to a connector of a wire harness of the exterior rearview mirror assembly.
US09659497B2	Lane departure warning system and lane departure warning method A lane departure warning system includes an image photographing unit attached to a front of a vehicle to photograph an object in a forward direction of the vehicle; a driving unit receiving image data from the image photographing unit, filtering the image data to search for a lane pair, converting an image coordinate of the image data into a real coordinate to calculate a lateral distance between the lane pair and the vehicle and to calculate a lateral speed of the vehicle, and generating a warning generating signal as a time of lane change elapses by obtaining the time of lane change; and a warning unit receiving the warning generating signal to generate a lane departure warning signal.
US09659496B2	Proximity awareness system for motor vehicles Various embodiments provide enhanced warnings of potential future adverse events (e.g., automobile crashes) by tracking the location and motion of multiple vehicles, and providing alerts or warnings to the drivers of such vehicles in the event that a risk of an adverse event is identified.
US09659492B2	Real-time vehicle spacing control In an embodiment, a system detects when vehicle bunching is about to occur or is already occurring within a given transit system. The system resolves the bunching using an event and tone based system which regulates the arrival and departure times of vehicles at vehicle stops. Also, an embodiment includes a method for receiving location information for a plurality of vehicles along a route, determining a relative distance between a first vehicle of the plurality of vehicles and at least a second vehicle of the plurality of vehicles as a function of the received location information, and generating an action signal for at least one of the plurality of vehicles located on the route, wherein the action signal is in response to the determined relative distance.
US09659489B2	Display apparatus A display apparatus is disclosed, which includes a display unit, an opening member, a light source, a light transmission member, and a buffer having a buffer main portion and a light block portion. The buffer main portion is held between the display unit and the light transmission member. The light block portion protrudes from the buffer main portion along an opposing surface of the light transmission member opposing the display unit, and covers a reached region of the opposing surface to which a direct light from the light source toward an opening of the opening member reaches.
US09659485B2	Self-testing smoke detector with integrated smoke source A device and method for self-testing fire detection devices that includes a smoke source housed within the fire detection device. The smoke source is typically a pressurized canister or cartridge, which stores or generates smoke or a smoke equivalent. In response to a signal from a controller, the smoke source releases the smoke or smoke equivalent in or near a sampling volume of the fire detection device to test the operation of the fire detection device. If the device is operating properly, it will be triggered in response to the smoke or a smoke equivalent.
US09659482B2	Context-based alerts for an electronic device Embodiments of the present disclosure provide a system and method for providing an output for an electronic device. In certain embodiments, an alert is output in accordance with a current alert mode, which are selected based on one or more environmental conditions. The environmental conditions may be detected using one or more environmental sensors. The alert can optionally include one or more of: an audio component, a haptic component and a visual component. One or more of alert components correspond to an aspect of the environmental condition detected by the one or more environmental sensors.
US09659478B1	Wearable electronic stress and strain indicator A stress and/or strain indicator comprises a wearable body, one or more flexible sections, one or more rigid sections and one or more strain gauges. The one or more strain gauges detect a level of stress and/or strain applied to the wearable body in order to indicate when the product is in danger of failing. A warning is activated based upon the level of stress and/or strain applied to the wearable body. For example, the stress and/or strain indicator is able to display a visual and/or an audible warning that a high level of stress and/or strain has been applied to the wearable body and the product is in danger of failing. In some embodiments, the stress and/or strain incident is recorded and downloadable. Consequently, a user is better informed as to when the electronic product is in danger of failing because of damage or misuse.
US09659473B2	Fiber optic security systems including a local control node and a remote control unit, and methods of using the same A fiber optic security system is provided. The fiber optic security system includes at least one length of fiber optic cable affixed to at least one item to be monitored using the fiber optic security system. The fiber optic security system also includes at least one local control node, the at least one local control node including at least one light source for generating and transmitting light through the at least one length of fiber optic cable, and the at least one local control node monitoring a status of the light. The fiber optic security system also includes a remote control unit for receiving information from the at least one local control node regarding the status of the light.
US09659472B2	Programmable security system and method for protecting merchandise A programmable security system and method for protecting an item of merchandise includes a programming station, a programmable key and a security system. The programming station generates a security code and communicates the security code to a memory of the programmable key. The programmable key initially communicates the security code to a memory of the security device and subsequently operates the security device upon a matching of the security code in the memory of the security device with the security code in the memory of the programmable key. The programmable key may also transfer power via electrical contacts or inductive transfer from an internal battery to the security device to operate a lock mechanism. The security code may be communicated by wireless infrared (IR) systems, electrical contacts or inductive transfer. A timer inactivates the programmable key and/or the security device after a predetermined period of time. A counter inactivates the programmable key after a predetermined maximum number of activations.
US09659469B2	Explicit real-time fire disaster alarming device and method An explicit real-time fire disaster alarming device includes a fire disaster detector, human body detector, controller and outdoor light displaying portion. If the fire disaster detector detects any fire inside a space or room, it will send out a fire signal. The human body detector detects whether there is any human inside the space and send out a YES signal or a NO signal accordingly. When the controller receives the fire signal, the outdoor light displaying portion changes from a storing form to an extending form. When the controller receives the YES signal, the outdoor light displaying portion turns on a light for showing there is a human inside the space. When it receives the NO signal, the outdoor light displaying portion turns on another light for showing there is no human inside. Hence, fire fighters and rescuers are provided with a priority reference for life rescue.
US09659465B2	Problem resolution validation A method of validating resolution of a problem at a media terminal is described. The method comprises accessing a file including a task; identifying a plurality of specific actions to be taken to perform the task; and ascertaining each event that would be triggered by the media terminal when each identified specific action is performed correctly. The method further comprises: displaying the identified specific actions to a service engineer; and transmitting a validation message to a remote management system when all ascertained events have been triggered in response to the service engineer performing the identified specific actions correctly.
US09659458B2	Guild-dependent variation of player capabilities in a computer-implemented game A system and method provide automated guild-dependent variation of in-game capabilities available to player in an computer-implemented game. An in-game capability is made available to the player in inter-guild competitive gameplay, for example comprising an object-specific ability associated with the game object, such as a collectible card. A value for a variable attribute of the in-game capability is dynamically adjusted based at least in part on one or more guild metrics for an associated guild of which the player is a member. The one or more guild metrics may include guild size and activity levels of guild members.
US09659454B2	Electronic gaming device with auto-play functionality Examples disclosed herein relate to systems and methods, which may receive wagers on one or more paylines. The systems and methods may utilize one or more auto-play game functionality. The systems and methods may determine one or more payouts based on the one or more auto-play game functionality. The systems and methods may display one or more presentations based on the one or more auto-play game functionality.
US09659452B2	Method of gaming, a gaming system and a game controller A method of gaming comprising: (a) determining a minimum prize value to be awarded for a current game outcome based on a previous game outcome; (b) generating the current game outcome; (c) determining a provisional prize value based on the current game outcome; (d) comparing the provisional prize value with the minimum prize value; and (e) setting a current prize value at the minimum prize value upon the provisional prize value being less than the minimum prize value or at the provisional prize value upon the provisional prize value being greater than or equal to the minimum prize value.
US09659451B2	Linked progressive jackpot system A gaming machine 10 has a display 14 and a game controller arranged to control images of symbols displayed on the display 14. The game controller is arranged to play a game 16 in which at least one random event is caused to be displayed on the display 14. If a predefined winning event occurs, the machine 10 awards a prize to a player. When a trigger condition occurs in a base game of the game 16, a bonus game feature is awarded comprising a series of bonus games. If a particular special symbol outcome occurs during any of the bonus games, the particular special symbol outcome is collected towards a jackpot prize awarding event.
US09659449B2	Methods and systems for providing accessory devices usable to facilitate remotely viewable wagering game outcomes In accordance with some embodiments, a plurality of outcomes are generated and used to create a video presentation of representative outcomes. The video presentation is recorded onto a tangible medium (e.g., DVD or CD-ROM) or otherwise provided to a player (e.g., player may access the video presentation online). This allows a player to purchase a video presentation of (e.g., predetermined) outcomes in a jurisdiction in which gambling is legal yet view the presentation at the player's convenience (e.g., from any jurisdiction and at any time). The outcomes on the DVD or CD ROM may be viewed on a video display generated by a primary output device (e.g., a personal computer or a DVD player). In addition, the player may purchase or otherwise obtain an accessory device that interacts (e.g., augments the outcomes) with the game play recorded on the tangible medium.
US09659448B1	System and method for monetizing winnings from virtual gaming The present invention provides methods and systems for monetizing virtual poker winnings that include selecting a first plurality of contestants for participation in a virtual poker tournament; conducting the virtual poker tournament, wherein each one of the first plurality of contestants play in the virtual poker tournament using a device operatively coupled to the computer system via an internet connection, and wherein no prizes are awarded in relation to the conducting of the virtual poker tournament; selecting a subset of the first plurality of contestants to form a second plurality of contestants, wherein the second plurality of contestants qualifies for entry to a live poker tournament, and wherein the selecting of the subset of the first plurality of contestants is based at least in part on performance in the virtual poker tournament; conducting the live poker tournament; and awarding prizes to a subset of the second plurality of contestants.
US09659441B2	Opt-in proximity alert A method for alerting a player about a wagering game machine is described herein. In some embodiments, the method can include receiving, via a communications network from a handheld computing device, player preferences for an opt-in proximity alert. The method can further include creating the opt-in proximity alert based, at least in part, on the player preferences. The method can further include determining, via one or more processors, that the handheld computing device is in proximity to a wagering game machine matching the player preferences. The method can further include causing the handheld computing device to present an alert about the wagering game machine matching the player preferences.
US09659438B2	Delayed wagering interleaved wagering system A delayed wager interleaved wagering system is disclosed including an interactive processing device constructed to: provide an interactive application display; receive wager actuator data; automatically configure the display to provide a wager actuator; communicate wager actuator activation data; receive wagering telemetry data and application resource data; responsive to receiving the wagering telemetry data, automatically configure the display; a wager server constructed to: receive wager request data; automatically determine and communicate a wager outcome; and the process controller operatively connecting the interactive processing device and the wager server, and constructed to: receive the application telemetry data; determine to provide the wager actuator; communicate the wager actuator data; receive the wager actuator activation data; generate wager request data; communicate the wager request data; receive the wager outcome data; automatically determine and communicate the wagering telemetry data and the application resource data.
US09659430B2	Gaming system and method providing game with multiple award displays A gaming system and method which provides multiple individually and independently activated un-weighted award displays, wherein a plurality of designated awards have the same probability of being won regardless of how many of the award displays are activated. In various embodiments, the designated awards are different, and in various embodiments, the designated awards are progressive awards. In various embodiments, the un-weighted award displays include a plurality of award wheels.
US09659428B2	Gaming system and a method of gaming A gaming system comprising a display, an object selector arranged to select at least one object to be placed in each container of a set of a plurality of containers displayed on the display and an outcome generator arranged to determine a game outcome based on at least one characteristic of the object or objects placed in at least part of each container of the set of containers.
US09659426B2	Dispenser for rolling product and dispenser cartridges A serpentine dispenser and cartridge system provides simplified stocking and restocking, as well as jam-free dispenser feeding. A cartridge priming flap allows a cartridge be inverted and inserted into a dispenser while products in the cartridge are prevented from falling out. Cartridge opening is completed by holding an priming flap while pushing the cartridge into the dispenser. In other embodiments, a dispenser wedge applies pressure on rolling products, forcing a retaining flap open, as the cartridge is pushed into the dispenser. The wedge can also constrain rolling products to exit the cartridge in an order that prevents jamming.
US09659424B2	Technologies and methods for security access Embodiments herein are directed security access. Embodiments include an electronic lock that executes a time-based cryptographic algorithm to compute a time-based access code. The electronic lock compares the time-based access code with a received access code, and grants access to one or more lock features when the time-based access code matches the received access code. Embodiments also include providing an unlock code, including receiving a lock identifier and a user identifier. The lock identifier and the user identifier are sent to a remote computer system, and an access code for the lock is received from the remote computer system. Embodiments also include an electronic lock that receives and verifies an access code that includes a validity start time and a validity end time. When the current time is within the validity start time and the validity end time, the electronic lock grants access to one or more lock features.
US09659418B2	Locking systems A locking system is disclosed. The locking system may move a lockable device included in the locking system between a locked and unlocked state. The lockable device may comprise a laser.
US09659416B2	Abnormality determination apparatus for vehicle There is provided a heat flux sensor with first and second interlayer connection members composed of different metals from each other of which metal atoms maintain a predetermined crystal structure embedded in first and second via holes of a thermoplastic resin made insulating substrate, the first and the second interlayer connection members are connected in series alternately, and a control unit that performs abnormality determination of a heating element disposed in a vehicle. The heat flux sensor is provided to the heating element and outputs a sensor signal corresponding to heat flux between the heating element and an outside air, and the control unit determines based on the sensor signal that there is abnormality in the heating element when the heat flux between the heating element and the outside air is out of a predetermined range.
US09659413B2	Method, system and device for navigating in a virtual reality environment A method, a system, and a device for navigating in a virtual reality scene, using body parts gesturing and posturing are provided herein. The method may include: projecting a synthetic 3D scene, into both eyes of a user, via a near eye display, so as to provide a virtual reality view to the user; identifying at least one gesture or posture carried out by at least one body part of said user; measuring at least one metric of a vector associated with the detected gesture or posture; applying a movement or action of said user in virtual reality environment, based on the measured metrics; and modifying the virtual reality view so as to reflect the movement or action of said user in the virtual reality environment.
US09659412B2	Methods and systems for displaying information on a heads-up display Methods and systems are provided for displaying information on a heads up display (HUD). A background image is captured with a camera. A plurality of regions of the background image are analyzed to determine a region-wise image attribute for each of the plurality of regions. A symbology having a symbology attribute is generated and overlaid on an overlay region of the background image to generate a heads up display image. The overlay region is one of the plurality of regions of the background image. The symbology attribute is adjusted based on the region-wise image attribute of the overlay region to generate an adjusted heads up display image. The adjusted heads up display image is displayed on the HUD.
US09659408B2	Mesh reconstruction from heterogeneous sources of data A system, apparatus, method, computer program product, and computer readable storage medium provide the ability to reconstruct a surface mesh. Photo image data is obtained from a set of overlapping photographic images. Scan data is obtained from a scanner. A point cloud is generated from a combination of the photo image data and the scan data. An initial rough mesh is estimated from the point cloud data. The initial rough mesh is iteratively refined into a refined mesh.
US09659407B2	Preemptive flushing of spatial selective bins for deferred graphics processing A graphics processing unit (GPU) is provided to preemptively flush one or more bins. The GPU generates bin data of a display area according to an association of primitive data with the bins that correspond to the display area. Upon detecting an adaptive condition, a signal is generated to indicate that one or more bins of a first frame are to be flushed in a first order before the first frame is fully binned. The signal interrupts bin flush of a second frame in a second order in order to flush the one or more bins of the first frame in the first order. After the one or more bins of the first frame are flushed, the bin flush of the second frame is resumed in the second order.
US09659405B2	Image processing method and apparatus An image processing apparatus comprises data receiving circuitry for receiving a volumetric imaging data set which is representative of a volume, the volume comprising a region of interest and lighting circuitry configured to place a virtual light source outside the region of interest and to apply a lighting simulation process to simulate light from the virtual light source. The applying of the lighting simulation process is at least partially different for a first lighting region than for a second lighting region, the first lighting region comprising at least part of the volume outside the region of interest and the second lighting region comprising at least part of the region of interest.
US09659398B2	Multiple visual representations of lighting effects in a computer animation scene Computer animation tools for viewing, in multiple contexts, the effect of changes to a computer animation are disclosed. An artist configures multiple visual displays in the user interface of a computer animation system. A visual display shows one or more frames of computer animation. An artist configures a visual display to reflect a specific context. For example, the artist may assign a particular virtual viewpoint of a scene to a particular visual display. Once visual displays are configured, the artist changes a configuration of the computer animation. For example, the artist may change the lighting parameters of a scene. In response, the visual displays show the visual effects of the configuration (e.g., lighting parameters) change under corresponding contexts (e.g., different virtual camera viewpoints). Using multiple visual displays, which may be displayed side-by-side, an artist can view the effects of her configuration changes in the various contexts.
US09659392B2	Method and system for utilizing transformation matrices to process rasterized image data A method and system render rasterized data by receiving non-rasterized page description language data and a corresponding transformation matrix representing transformation operations to be performed. The non-rasterized page description language data is rasterizing to create rasterized data. The corresponding transformation matrix is decomposed into a plurality of individual transformation operation matrices and a discrete transformation operation value, from each corresponding individual transformation operation matrix, is generated for each transformation operation to be performed upon the rasterized data. The transformation operations are performed upon the rasterized data based upon the generated discrete transformation operation values.
US09659386B2	Method for operating a camera assembly, camera assembly and driver assistance system The invention relates to a method for operating a camera assembly, in which a first camera and a second camera capture images (36, 42). Respective fields of view of the two cameras overlap at least in a partial region (24). At least in an image (36) captured by the first camera, at least one contamination region (38) including a plurality of pixels is detected within the partial region (24). Thereupon, data values specifying the respective transparency of the pixels in the at least one contamination region (38) are varied with respect to respective reference values of the transparency, wherein these reference values increase in the partial region (24) towards an edge (28) of the respective image upon superimposition of the images. Furthermore, the invention relates to a camera assembly.
US09659384B2	Systems, methods, and computer program products for searching and sorting images by aesthetic quality A system, method, and computer program product for assigning an aesthetic score to an image. A method of the present invention includes receiving an image. The method further includes executing a neural network on the image to generate learned features. The method further includes applying a machine-learned model to assign an aesthetic score to the image, where a more aesthetically-pleasing image is given a higher aesthetic score and a less aesthetically-pleasing image is given a lower aesthetic score. The learned features are inputs to the machine-learned model.
US09659382B2	System and method for depth extraction of images with forward and backward depth prediction A system and method for spatiotemporal depth extraction of images with forward and backward depth prediction are provided. The system and method of the present disclosure provide for acquiring a plurality of frames, generating a first depth map of a current frame in the plurality of frames based on a depth map of a previous frame in the plurality of frames, generating a second depth map of the current frame in the plurality of frames based on a depth map of a subsequent frame in the plurality of frames, and processing the first depth map and the second depth map to produce a third depth map for the current frame.
US09659379B2	Information processing system and information processing method An information processing system comprises: a light emitting unit that irradiates pattern light having a specific pattern to a subject to form a texture on the subject; an imaging unit that captures the subject on which the texture is formed; a deriving unit that derives distance information to the subject based on an image captured by the imaging unit; an analyzing unit that analyzes whether or not an image abnormality is present in either one of the captured image and an image based on the distance information; and a dimming unit that performs dimming control when the analyzing unit analyzes that the image abnormality is present.
US09659374B2	Feature-based registration method Methods for registering a three-dimensional model of a body volume to a real-time indication of a sensor position that involve analyzing scanned and sensed voxels and using parameters or thresholds to identify said voxels as being either tissue or intraluminal fluid. Those voxels identified as fluid are then used to construct a real-time sensed three-dimensional model of the lumen which is then compared to a similarly constructed, but previously scanned model to establish and update registration.
US09659372B2	Video disparity estimate space-time refinement method and codec A method for disparity estimation of stereo video data receives a sequence of frames of stereo video data. Image-based disparity estimation is initially conducted on a frame-by-frame basis to produce initial disparity estimates. A plurality of initial disparity estimates is grouped into a space-time volume. Disparity error is reduced in the space-time volume to refine the initial disparity estimates.
US09659371B2	System and method for online projector-camera calibration from one or more images A system and method for online projector-camera calibration from one or more images is provided. The system comprises: a projector, a camera, and a calibration device configured to: determine a map between pixels of each of a projector image and a camera image in fewer than one hundred percent of pixels of the projector image using feature extraction; determine an initial estimate of a fundamental matrix from the map; determine an initial guess of intrinsic properties of the projector and camera using one or more closed-form solutions; iteratively determine an error-function based on the map using the fundamental matrix while adding constraints on the intrinsic properties using the one or more closed-form solutions, and the initial estimate and guess as initial input; and, when the error-function reaches an acceptance value, determine intrinsic and extrinsic properties of the projector and the camera from current values of iterative estimates.
US09659368B2	System and method for enhancing functional medical images Systems and methods for generating a medical image of a subject that includes functional information. First, two medical images are acquired. One is weighted based on functional information reflecting physiological functions of the subject and the other weighted based on anatomic information of the subject. A difference image between the two images are generated. By subjecting the difference image and the second image to a localized kernel, a local similarity image is generated. Using the local similarity image, an improved difference image is generated. Lastly, by subtracting the improved difference image from the first image, an enhanced medical image that retains the functional information reflecting physiological functions of the subject is generated.
US09659361B2	Measuring apparatus that generates positional deviation distribution of a pattern on a target object A measuring apparatus includes an optical image input unit to input optical image data of a figure pattern obtained by a pattern inspection apparatus, which inspects defects of a pattern on a target object to be inspected by scanning an inspection region of the target object, from the pattern inspection apparatus, a design data input unit to input design data of the pattern on the target object, a reference image generation unit to generate reference image data to be compared with the optical image data, by performing image development of the design data, a positional deviation distribution generation unit to generate positional deviation distribution by measuring a positional deviation amount of the pattern on the target object, by using the optical image data obtained from the pattern inspection apparatus and the reference image data having been generated, and an output unit to output generated positional deviation distribution of the pattern.
US09659360B2	Identifying an original object in a forgery-proof way For identifying an original object comprising a surface essentially made of a first substance in a forgery-proof way, atoms of a second substance not soluble in the first substance are deposited on the surface. The surface is subjected to a beam of energized atoms providing movability to the atoms of the second substance in the surface to allow for a nucleation of a phase separation of a phase, in which the atoms of the second substance are concentrated. Then, an image of a surface pattern originating from the nucleation of the phase separation is taken and stored as a identifier for the original object. When a comparison image of a surface pattern of some object supposed to be the original object is compared to the identifier, the object is confirmed as being the original object, if the surface patterns in the identifier and the comparison image are identical.
US09659358B2	Apparatus for checking adherence state of fiber reinforced plastic tape An apparatus for checking an adherence state of fiber reinforced plastic tape includes an illuminating section having first and second illuminating groups. The main optical axes of illumination light beams of light emitting sections of the first illuminating group are set at a designated inclination angle with respect to a surface of an imaging region and distances on the main optical axes between a surface of a structural object and each of the light emitting sections are set to be the same. The main optical axes of illumination light beams of light emitting sections of the second illuminating group are set at an inclination angle different from the first illuminating group with respect to the surface of the imaging region and distances on the main optical axes between the surface of the structural object and each of the light emitting sections are set to be the same.
US09659352B2	Image denoising system and method A method, computer program product, and computer system for identifying a first portion of a facial image in a first image, wherein the first portion includes noise. A corresponding portion of the facial image is identified in a second image, wherein the corresponding portion includes less noise than the first portion. One or more filter parameters of the first portion are determined based upon, at least in part, the first portion and the corresponding portion. At least a portion of the noise from the first portion is smoothed based upon, at least in part, the one or more filter parameters. At least a portion of face specific details from the corresponding portion is added to the first portion.
US09659347B2	Method and device for image zoom out processing A method for image zoom out processing includes: determining whether a predetermined zoom out ratio is smaller than a first predetermined threshold; when the predetermined zoom out ratio is smaller than the first predetermined threshold, performing a zoom out process on an image according to the first predetermined threshold by a bilinear interpolation algorithm to obtain a zoomed out image; determining whether a product of a resolution of the zoomed out image and the first predetermined threshold is greater than or equal to a target resolution; when the product is greater than the target resolution, repeating the step of performing the zoom out process; when the product is smaller than the target resolution, performing the zoom out process on the image according to a second predetermined threshold by the bilinear interpolation algorithm so that the resolution of the zoomed out image reaches the target resolution.
US09659342B2	Mid command buffer preemption for graphics workloads Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.
US09659341B2	Texture pipe as an image processing engine A texture pipe of a graphics processing unit (GPU) may receive a texture data. The texture pipe may perform a block-based operation on the texture data, wherein the texture data comprises one or more blocks of texels. Shader processors of the GPU may process graphics data concurrently with the texture pipe performing the block-based operation. The texture pipe may output a result of performing the block-based operation on the one or more texture data.
US09659336B2	Mobile baggage dispatch system and method The disclosure relates to an apparatus, method and system for dispatching baggage. The apparatus includes a processor configured to receive baggage information associated with a passenger; associate the baggage information with a delivery person, where the delivery person is associated with delivery person information; and transmit at least apportion of the baggage information and the delivery person information to a passenger computing device associated with the passenger.
US09659335B2	Sample management for a sales call Systems and methods are provided that record details of product samples given to a customer. A request to add one or more product sample records is received, and in response, user interface showing product sample information for available product samples is presented. The user interface may include a field for entering a quantity of each product sample given to the customer. One or more product sample records is recorded corresponding to each product sample for which a quantity was entered in the user interface.
US09659331B1	Insurance claim capitation and predictive payment modeling A claim-based capitation model is proposed for handling vehicle repair insurance claims. Rather than determining a detailed estimate of the expected actual cost of repair, the estimate may be determined using a simpler model. For example, the insurance company and a repair facility may agree to following a predictive payment model in which the insurance company pays a fixed predicted capitated amount of money for each repair claim, regardless of the amount of repair work that will be needed. Alternatively, the insurance company may pre-pay a fixed capitated amount for a predicted number of future insurance claims.
US09659325B2	Bidding to receive data after a consumer is in a zone An announcement distributor distributes, or auctions an opportunity to distribute, an announcement to an announcement recipient such as a consumer, issuer, merchant, or acquirer within a payment processing system. The announcement when there has been a satisfaction of an announcement condition, such as the consumer being determined to be located within a predetermined spatial zone. The content of the announcement may, in turn, facilitate a subsequent cashless transaction for resources of merchants. Implementations describe various permutations of the content of the announcement, the announcement condition, and the announcement recipient.
US09659324B1	System, method, and computer program for aggregating fallouts in an ordering system A system, method, and computer program product are provided for aggregating fallouts in an ordering system. In use, a repository of fallout errors associated with an ordering system is maintained. Further, one or more fallout events associated with the ordering system are automatically detected. Additionally, it is determined that the one or more detected fallout events are associated with at least one fallout error associated with processing an order in the ordering system. Furthermore, it may be determined whether the at least one fallout error corresponds to one of a plurality of stored fallout errors stored in the repository of fallout errors, in response to determining that the one or more detected fallout events are associated with the at least one fallout error from processing an order in the ordering system.
US09659323B2	System for making financial gifts A computer-implemented method for electronic gift giving. An exemplary embodiment includes providing an internet site for access by a giver, prompting the giver to enter giver identification information, prompting the giver to enter recipient information, prompting the giver to enter a value of a monetary gift, providing a plurality of possible recommended gifts or transfers of funds, prompting the giver to recommend at least one gift or transfer of funds to be effectuated using the monetary gift, prompting the giver to select a presentation template from a plurality of recommended presentation templates, prompting the giver to transfer the value of the monetary gift to a gift account, and storing the value of the monetary gift and the at least one recommended gift or transfer in association with the presentation template for delivery to a recipient.
US09659322B2	Graphical display for recommending sleep comfort and support systems A pressure sensor measures the surface pressure distribution of a body supported by a surface, for example a person lying on a mattress. In one approach, a pressure mapping system acquires a customer's pressure map using a reference mattress and presents this pressure data in the form of a pressure map. The pressure map measurement data is then analyzed to determine body characterizing parameters such as body mass index, contact area and average peak pressure. The pressure map measurements are then located on a mattress category grid that has been referenced and aligned to a large population sample of measurements taken with a reference mattress. Alternatively, the pressure map measurements are matched to a physical profile category within a database. Each category provides ranked mattress recommendations based on selection and ranking criteria derived from pressure map data obtained from a large sample of test subjects. In this way, a customer's pressure map can be translated to a recommendation of specific mattresses or mattress categories that are offered by a mattress retailer or manufacturer.
US09659320B2	System and method to enable a customer to select a wine based upon available inventory A method is disclosed for providing services to a patron of an establishment by providing to the patron a handheld device upon entering the establishment. The patron is identified such that the patron is associated with the handheld device provided thereto and the operation thereof. The patron is presented with available services of the establishment and, in association with the available services, parameterized information from a database is presented to the patron relating to prior actual experiences with at least one of the services as rated by the patron, which rating defines how the patron viewed the services at the time of such providing. The patron selects from the provided information one or more of the available services. As part of the parameterized information, prior selected and not yet rated services are also presented. The patron rates the prior selected and not yet rated services and the database is updated.
US09659319B2	Method, medium, and system for processing resource returns The present disclosure provides a method and an apparatus for processing resource returning. According to the method, as a first user requests for a return of a resource associated with a prior online trade, a trading server determines if the first user has a user rating greater or equal to a preset user rating threshold, and if yes, returns the requested online trading resource to the first user without waiting until a second user has received the corresponding returned goods or services from the first user. The method can expedite the process of returning resources in online trading, and lightens the system burden caused by the user's frequently refreshing the account to check the resource return status.
US09659317B2	Individual online price adjustments in real time A method, system and computer program product for adjusting prices for goods and services offered using a computer network. In one embodiment, data relating to goods and services offered over the computer network by a number of entities using the computer network are stored in a database, communications are monitored, using the computer network, to identify an interest of a user, and this interest of the user and the data in the database are used to identify one of the entities to offer a specified product or service to the user. Information is obtained relating to a price for the specified product or service, and this information and the data in the database are used to determine an adjusted price for the specified product or service. In one embodiment, the information the user has about a price for the specified product or service is used to determine the adjusted price.
US09659315B2	Directing internet shopping traffic and tracking revenues generated as a result thereof A system having a client, a host server, a sponsor server, and a video server, which are all interconnected via the Internet and which operate seamlessly together in order to provide video content to an end user at the client and allow the end user at the client to purchase products and/or services from the sponsor that are featured in the video content provided by the video server. As the user views video content on his or her computer, images associated with segments of the content are periodically provided in conjunction with the video content. Each image contains an image map, which defines areas in the image. Each defined area is associated with a product which is displayed in that area of the image. Each defined area is also associated with an anchored hyperlink which links to web content from a sponsor server.
US09659314B2	Method and apparatus for tagging network traffic using extensible fields in message headers Embodiments within describe a system and method of tagging network traffic with relevant user information for facilitating the delivery of directed media. In an embodiment, a user identifier is generated from user information. Network traffic from the user and bound for a destination site is tagged within a network routing device. The tagged traffic is tagged with a request identifier that has the user identifier encrypted in an alphanumeric string. The tagged network traffic is transmitted to the destination site. A request is received from the destination site to decode the tagged network traffic, retrieve stored user information, and transmit the stored user information to the destination site.
US09659313B2	Systems and methods for managing interactive features associated with multimedia content Methods and systems for managing interactive features associated with multimedia content are disclosed. One method includes applying a container to multimedia content using one or more computing systems, the container defining an interface through which metadata external to the multimedia content is linked with one or more portions of the multimedia content. The method further includes receiving a request for the multimedia content from a content consumer. The method also includes associating a set of metadata describing one or more interactive features with the multimedia content, the set of metadata linked to at least a portion of the multimedia content via the container and selected from a database including metadata defining interactive features capable of being associated with the multimedia content. The method also includes, upon receiving a request for playback of the multimedia content, providing the multimedia content and the one or more interactive features to the content consumer.
US09659309B2	Suggesting and/or providing ad serving constraint information Targeting information (also referred to as ad “serving constraints”) or candidate targeting information for an advertisement is identified. Targeting information may be identified by extracting topics or concepts from, and/or generating topics or concepts based on, ad information, such as information from a Web page to which an ad is linked (or some other Web page of interest to the ad or advertiser). The topics or concepts may be relevant queries associated with the Web page of interest, clusters, etc.
US09659305B2	Click quality classification and delivery In one embodiment, a method includes receiving a packet flow associated with a click-through from an end user node destined for an advertiser server; extracting information from the packet flow; analyzing the extracted information to determine one or more characteristics of the packet flow; and classifying the packet flow based on the determined one or more characteristics; modifying the packet flow to include classification information to provide classification information indicating a quality level of the click-through. The packet flow may include a hypertext transfer protocol GET request. Modifying the packet flow may include adding a tag with classification information that indicates a likelihood of fraudulent click behavior associated with the packet flow.
US09659301B1	Roadside assistance A mobile computerized apparatus configured to provide membership status in a roadside assistance program after occurrence of a roadside event is disclosed. The apparatus executes instructions that cause/allow the apparatus to receive input related to an electronic membership card, retrieve from a data store membership information associated with the vehicle, and dynamically update the electronic membership card for display on the apparatus.
US09659298B2	Systems and methods for informing virtual agent recommendation Systems, methods, and apparatus for use in connection with at least one virtual agent. In some embodiments, at least one virtual agent is programmed to: identify a relationship between at least two persons; and make a recommendation for the at least two persons based at least in part on the relationship between the at least two persons.
US09659292B1	Storage-based replication of e-commerce transactions in real time The back-end data storage system of an e-commerce system receives a replicated transaction from the data storage system of another e-commerce system and makes a determination or decision whether to commit the replicated transaction based upon a comparison of information parsed from the transaction with predetermined commit criteria.
US09659291B2	Method for processing a payment In a method for processing a payment, an electronic device receives transaction information related to a transaction and to a payment for the transaction, accesses a payment card via a portable payment device, cooperates with the payment card to generate a payment command to include at least the transaction information, establishes a session with a banking server, and transmits the payment command to the banking server under the session. The banking server identifies validity of the payment card based on the payment command, and processes the payment according to the transaction information afterward. The electronic device then receives a payment result generated by the banking server after completing the payment.
US09659290B2	Financial transaction system A system and method for conducting a financial transaction is disclosed. The system includes a first memory location embedded in a personal portable device. The first memory location stores a plurality of personal financial data files associated with a user. The system also includes a second memory location to store biometric information and a first input interface to receive authentication information after initiation of a purchase transaction session. The system also includes a security module including an input coupled to the first interface to authenticate the authentication information based on the biometric information and an output interface comprising an input coupled to the first memory location and an output to provide personal financial data file information to a host device.
US09659288B1	System and method for providing measurement tool at point of sale The present invention is generally a system and method for providing a measurement device with a point of sale (POS) receipt. In exemplary embodiments, a store such as a building supply store or hardware store, may implement POS devices configured to generate printed media that may be used by customers as a measuring tool. The measuring tool may comprise a printed sheet with measurement markings printed along a longitudinal border of the printed sheet adjacent to transactional information of a registered purchase, and or promotional information that may be relevant to the customer.
US09659287B2	Online purchase processing system and method A system and method to use quick response (QR) codes encoded with merchant website identification codes and session GUID to register a user or code scanner with a merchant server, login the user or code scanner with the merchant server, and complete a purchase of an item or service within a virtual shopping cart of the merchant server. A code scanner can scan a QR code displayed on a device connected to the internet. An application server can receive an identification code from the code scanner and then transmit data indicating form fields to be filled in on a merchant webpage. A user profile can include data regarding the user and a payment instrument. The user profile data can prepopulate the form fields and the form field data can be transmitted to the merchant server to use for logging in the user and completing the purchase.
US09659285B2	Music distribution systems Music is blanket transmitted (for example, via satellite downlink transmission) to each customer's user station where selected music files are recorded. Customers preselect from a list of available music in advance using an interactive screen selector, and pay only for music that they choose to playback for their enjoyment. An antipiracy WID tag” is woven into the recorded music so that any illegal copies therefrom may be traced to the purchase transaction. Music is transmitted on a fixed schedule or through an active scheduling process that monitors music requests from all or a subset of satellite receivers and adjust scheduling according to demand for various CD's. Receivers store selections that are likely to be preferred by a specific customer. In those instances where weather conditions, motion of atmospheric layers or dish obstructions result in data loss, the system downloads the next transmission of the requested CD and uses both transmissions to produce a “good copy”. In conjunction 20 with the blanket transmission of more popular music, an automated CD manufacturing facility may be provided to manufacture CD's that are not frequently requested and distribute them by ground transportation.
US09659284B1	Systems and devices controlled responsive to data bearing records A device (12, 312, 494) operates to cause financial transfers responsive to data read from data bearing records. The device includes a reader (20, 314) that is usable to read check data from financial checks. The reader is also usable to read record document data associated with goods provided to a purchaser. At least one circuit (54, 332) of the device is operative to cause a determination to be made that check data and/or record document data corresponds to stored data. Responsive to the determination, check data and record data is made available to a payee terminal (346).
US09659280B2	Information sharing democratization for co-located group meetings Information sharing between meeting attendees during a co-located group meeting in a meeting space is democratized using a computer that is operating cooperatively with one or more object sensing devices in the meeting space to identify postures formed by the meeting attendees.
US09659278B2	Methods, systems, and computer program products for displaying tag words for selection by users engaged in social tagging of content Methods, systems and computer program products for displaying tag words for selection by users engaged in social tagging of content accessible via a communications network, are provided. A tag cloud, tag word inventory curve and slider control are displayed within a graphical user interface. The tag cloud is a visual representation of an inventory of tag words. The tag word inventory curve is a graphical representation of the words in the inventory by frequency of usage by others. The slider control is responsive to user movement, and is movable within a range that spans the length of the tag word inventory curve. Movement of the slider control changes the number of tag words from the inventory displayed in the tag cloud according to frequency of usage by others.
US09659274B2	Inventory tracking and management A method of inventory tracking and management is described. The method may include receiving a location request for an item and determining, using three or more base stations, the location of the item. The method may also include generating, by a processing device, a map of the item's location and item information and sending the map to a user, and sending the location request to the item, where the location request causes the item or the item's container to indicate its presence.
US09659271B2	Protection of privacy in connection with shipment of products Disclosed are various embodiments for enhancing protection of privacy of purchaser contact details in connection with shipment of parcels. A shipping label can be generated that includes at least one contact detail that hides an actual contact detail associated with a purchaser. A carrier tasked to ship and/or deliver the product to an address designated by the purchaser can use the at least one contact detail to contact the purchaser. The attempts to contact the purchaser can be logged, and the contact details are expired when no longer needed.
US09659269B2	System and method for increasing employee productivity An exemplary embodiment of the computerized system and method for increasing employee productivity provides a database for storing data, a data inputting device for inputting expected output parameters into the database and a data acquiring device for acquiring actual output data during performance of any workplace duties, preferably in real-time. The data acquiring device may be linked by an interface that transfers the acquired data to the database, where a processor may evaluate the inputted data versus the acquired data. The processor is connected to a data displaying device that may display the inputted, acquired and evaluated data, preferably in real-time.
US09659266B2	Enterprise intelligence (‘EI’) management in an EI framework Enterprise Intelligence (‘EI’) management in an EI framework including: analyzing, by an assembly analysis engine, a plurality of EI assemblies, each EI assembly configured to carry out a business capability upon execution; choreographing, by an assembly engine, execution of one or more of the EI assemblies; and reporting, by the assembly engine to an EI administrator, information related to execution of the one or more of the EI assemblies.
US09659264B2	Enablement of licensed features at a logical volume level of granularity A licensing application implemented in a computational device receives a request to enable a feature for a logical volume of a plurality of logical volumes controlled by the computational device, wherein each feature of a plurality of features is configurable to be enabled or disabled for one or more logical volumes of the plurality of logical volumes. The licensing application determines, whether enabling the feature for the logical volume causes a licensed capacity limit for the feature to be exceeded. Enabling the feature for the logical volume is avoided, in response to determining that enabling the feature for the logical volume causes the licensed capacity limit for the feature to be exceeded.
US09659260B2	Calendar based task and time management systems and methods A software solution for managing, sorting and ranking lists of tasks and integrating task and time management, such that tasks can be automatically or manually assigned to specified time blocks. Users can monitor the relationship between volume of tasks and available time in which to complete them. The solution and method can be applied to individual task lists as well as to the management of time across multiple projects and can be employed either by individuals or by collaborative groups. The solution and method employ multiple filters, sorts and handling rules to embody users' personal planning preferences. It can be used to manage task lists both with and without employing a scheduling component. The solution can interoperate with existing computer- and web-based calendar software and can use third-party calendar clients to display its output and to accept input from users.
US09659256B2	Network service recommendation method and apparatus The present disclosure discloses a network service recommendation method and apparatus, which belong to a network data analysis technology. The method includes: retrieving, according to a historical browsing record of a user during use of a network service, a label corresponding to each network service used by the user; determining, according to a preset label-topic correspondence, and by using the label corresponding to each network service used by the user, first n topics corresponding to the user; acquiring, according to a preset topic-network service correspondence, respective corresponding recommended network service lists of the first n topics, the recommended network service list of each topic including at least one network service; and recommending a network service to the user according to the respective corresponding recommended network service lists of the first n topics.
US09659254B2	Systems and techniques for predictive data analytics Systems and techniques for predictive data analytics are described. In a method for selecting a predictive model for a prediction problem, the suitabilities of predictive modeling procedures for the prediction problem may be determined based on characteristics of the prediction problem and/or on attributes of the respective modeling procedures. A subset of the predictive modeling procedures may be selected based on the determined suitabilities of the selected modeling procedures for the prediction problem. A resource allocation schedule allocating computational resources for execution of the selected modeling procedures may be generated, based on the determined suitabilities of the selected modeling procedures for the prediction problem. Results of the execution of the selected modeling procedures in accordance with the resource allocation schedule may be obtained. A predictive model for the prediction problem may be selected based on those results.
US09659253B1	Solving an optimization model using automatically generated formulations in a parallel and collaborative method A method, apparatus and computer program product for solving an optimization model by automatically creating alternative formulations, and solving those with parallel solution approaches communicating with each other. The method: automatically generates alternative formulations for a given optimization model; executes parallel communicating solution approaches in a parallel computing infrastructure in order to solve a given set of alternative model formulations; utilizes a mechanism to automatically detect the model structure and a mechanism to automatically detect the appropriate solution approach(es) for a given model structure, and to launch multiple parallel solution approaches at existing optimization solvers. The system and methods enable communication between parallel solution approaches in order to improve performance. The system communicates information between the parallel solution approaches during a solve process, in order to improve performance. The communicated information includes information on upper and lower bounds of running algorithms and information on decision variables values for feasible intermediate solutions.
US09659251B2	Systems and methods of autonomic virtual network management The disclosed invention involves a method and systems of autonomic virtual network, which relates to three basic inventions in the area of autonomic computing: (1) systems and methods of multi-loop autonomic manager, preemptive contact point, i.e. sensors and effectors, and software-defined hardware resource, or abstraction and virtualization of the hardware functions; (2) service-delivery virtual network in the area of distributed network, and application assurance systems and methods; and (3) integration of these two fields of inventions, namely autonomic managed virtual network, such that the management of virtual networks which provide service delivery, is able to achieve n-tier architecture system and method ACRA.
US09659246B1	Dynamic magnetic stripe communications device with beveled magnetic material for magnetic cards and devices A flexible card may include a dynamic magnetic stripe communications device having multiple layers, such as an electromagnetic generator, a magnet, and a shield. A shield may form a non-flexible layer within the stack and may bend, but the shield may not be able to stretch or compress. Flexible layers may surround and adhere to the shield such that when the card is flexed, the flexible layers may stretch and compress with the movement of the shield. The dynamic magnetic stripe communications device may include one or more coils. Each coil may contain a material that may be beveled, such that a width at an end portion of the material may be smaller than a width at a middle portion of the material.
US09659242B2	Apparatus that performs calibration for maintaining image quality To add an arbitrary recording medium as a recording medium that can be used for calibration to maintain the quality of an image to be formed, an image forming unit forms a pattern image on each of a specific recording medium that can be used for the calibration and the arbitrary recording medium. A creating unit creates second conversion setting information applied to the arbitrary recording medium to convert luminance information into density information, using first luminance information obtained from the pattern image formed on the specific recording medium, second luminance information obtained from the pattern image formed on the arbitrary recording medium, and first conversion setting information applied to the specific recording medium for converting luminance information into density information. A determining unit determines a common image formation condition applied to the specific recording medium and the arbitrary recording medium based on the second conversion setting information.
US09659235B2	Low-dimensional structure from high-dimensional data Low-dimensional structure from high-dimensional data is described for example, in the context of video foreground/background segmentation, speech signal background identification, document clustering and other applications where distortions in the observed data may exist. In various embodiments a first convex optimization process is used to find low dimensional structure from observations such as video frames in a manner which is robust to distortions in the observations; a second convex optimization process is used for incremental observations so bringing computational efficiency whilst retaining robustness. In various embodiments error checks are made to decide when to move between the first and second optimization processes. In various examples, the second convex optimization process encourages similarity between the solution it produces and the solution of the first convex optimization process, for example, by using an objective function which is suitable for convex optimization.
US09659232B2	Position determination of an object by sensing a position pattern by an optical sensor An apparatus for determining a position of an object relative to a representation of an image to be represented includes a position pattern generator for generating a position pattern subdivided into a plurality of pattern portions, each of the pattern portions having an unambiguous bit pattern of a plurality of bit patterns, and the bit patterns being Gray-coded in a generalized manner; a combination unit for combining the position pattern with the at least one image to be represented and for providing a corresponding combined image; an optical sensor for optically sensing an image section of the combined image, being correlated with the object position; a filter for extracting at least one bit pattern corresponding to a pattern portion of the position pattern, from the image section and for providing at least one corresponding extracted pattern portion; and a determiner for determining the object position based on the extracted bit pattern. A method for determining the position of an object is also disclosed.
US09659231B2	Image analysis device, method for creating image feature information database, and design similarity determination apparatus and method Provided is an image analysis device for specifying an image region of an object being the basis for design similarity determination. An image analysis device 100 includes units 112, 113. The unit 112 moves original images Im1 and Im2 including a designated image region H with a rotationally symmetry on a first point P relative to a reference image Im2(j), calculates a correlation value cim(j) at each relative position, and detects the position of the point P in the images Im1, Im2, according to a geometric model, based on the amount of rotation θ(j) at which the cim(j) is the maximum and a vector v(j). The unit 113 specifies the range of the region H in the images Im1, Im2 based on the position of the point P and the distribution of the brightness values of pixels in the images Im1, Im2.
US09659230B2	Methods and systems for estimating skew angle of an image The disclosed embodiments illustrate methods and systems for estimating a skew angle of an image. The method includes identifying a set of measurable blocks from one or more blocks in said image. The method further includes dilating each measurable block, in said set of measurable blocks, with a predetermined regular structure to create a set of modified measurable blocks. The method further includes selecting a second set of measurable blocks from said set of modified measurable blocks based on a size of each modified measurable block in said set of modified measurable blocks. Thereafter, the method includes determining a slope of each measurable block in said second set of measurable blocks. Further, the slope is utilizable to estimate said skew angle of said image. The method is performed by one or more microprocessors.
US09659227B2	Detecting object from image data using feature quantities Object detecting apparatus and method enable to easily and accurately generate a feature quantity for detecting an object at low cost. To achieve this, in the object detecting apparatus and method, a value is assigned in consideration of relations of rotation and reversal in uniform patterns by using a small-sized conversion table, and, an ULBP feature quantity after rotation and reversal is generated from a previous ULBP feature quantity by simple calculation without using a conversion table indicating a correspondence relation between previous values and values after rotation and reversal.
US09659222B2	Vehicle event data recorder and operation method thereof A vehicle event data recorder and an operation method thereof are provided. The vehicle event data recorder includes a photography module, a database, a first image-processing circuit and a second image-processing circuit. The photography module is configured to capture the scene and output an original video frame. The first image-processing circuit generates a first video frame according to part or all of the original video frame, and records the first video frame into a database. The second image-processing circuit generates a second video frame according to part or all of the original video frame, and records the second video frame into the database. Wherein, the view angle of the second video frame is different from the view angle of the first video frame.
US09659220B2	Method and apparatus for updating scene model and video surveillance The present invention relates to the method for updating scene model and video surveillance. A method is provided for updating a scene model in a video which is composed of a plurality of visual elements, comprising: a classifying step for classifying the visual elements in a scene into stationary visual elements and moving visual elements according to their appearance change rates; a border determining step for determining borders from the scene according to a spatial distribution information of the stationary visual elements and the moving visual elements; and an updating step for updating the scene model according to the determined borders in said scene.
US09659216B2	Method, computer program, and system for automated real-time signal analysis for detection, quanitification, and prediction of signal changes A method, computer program, and system for real-time signal analysis providing characterization of temporally-evolving densities and distributions of signal features of arbitrary-type signals in a moving time window by tracking output of order statistic filters (also known as percentile, quantile, or rank-order filters). Given a raw input signal of arbitrary type, origin, or scale, the present invention enables automated quantification and detection of changes in the distribution of any set of quantifiable features of that signal as they occur in time. Furthermore, the present invention's ability to rapidly and accurately detect changes in certain features of an input signal can also enable prediction in cases where the detected changes associated with an increased likelihood of future signal changes.
US09659214B1	Locally optimized feature space encoding of digital data and retrieval using such encoding A digital document is represented as a set of codes comprising indices into a feature space comprising a number of subspaces, each code corresponds to one subspace and identifying a cell within the subspace. Each digital document can be represented by a code set, and the code set can be used as selection criteria for identifying a number of digital documents using each digital document's corresponding code set. By way of some non-limiting examples, digital document code sets can be used to identify similar or different digital images, used to identify duplicate or nearly-duplicate digital images, used to identify similar and/or different digital images for inclusion in a recommendation, used to identify and rank digital images in a set of search results.
US09659213B2	System and method for efficient recognition of handwritten characters in documents A system and computer-implemented method for efficient recognition of one or more handwritten characters in one or more documents is provided. The system comprises an image input module configured to receive the one or more documents as one or more images. The system further comprises a snippet extraction module to extract one or more fields of information from the one or more received images. Furthermore, the system comprises a segmentation module to segment the one or more extracted fields of information into one or more segments. Also, the system comprises a feature extraction module configured to extract one or more handwritten characters from each of the one or more segments. In addition, the system comprises a character recognition module configured to recognize the one or more extracted handwritten characters. The system further comprises a language processing module configured to detect and correct errors in the one or more recognized characters.
US09659207B1	Vehicle fingerprint bookmark Provided in the present disclosure is a fingerprint bookmark system which may be implemented in a vehicle with one or more configurable interior settings. The fingerprint bookmark system may contain a scanner which may be configured to record a fingerprint from a vehicle occupant such that a fingerprint image showing the fingerprint and a duration data for the fingerprint image are recorded by the scanner. The system may contain one or more processors which may be configured to compare the duration data associated with the fingerprint image with a duration threshold. The one or more processors may be configured to initiate a search to obtain a bookmark for the fingerprint shown in the fingerprint image when the duration data is less than the duration threshold. The one or more processors may be further configured to create a new bookmark when the duration data exceeds the duration threshold.
US09659206B2	Station for acquiring biometric and biographic data A system allowing the acquisition of biometric and biographical data of an individual includes a station into which at least one of the following elements are integrated: a sensor of biometric prints, a camera for taking a picture of said individual, a feedback screen and a gantry including lighting means adapted for ensuring lighting complying with given conditions of acquisition of the biometric data. The lighting means include a curved metallic reflector fixed to the rear and to the apex of the framework of a first upper light tube placed substantially horizontally, furnished with a protection which is lowered and oriented toward said reflector, and a second light tube disposed substantially horizontally in the lower part of the framework, where the power P2 of the second lighting tube being lower than that the power P1 of the first tube.
US09659204B2	Image processing methods and systems for barcode and/or product label recognition This disclosure provides an image processing method and system for recognizing barcodes and/or product labels. According to an exemplary embodiment, the method uses a multifaceted detection process that includes both image enhancement of a candidate barcode region and other product label information associated with a candidate barcode region to identify a product label, where the candidate barcode region includes a nonreadable barcode. According to one exemplary application, a store profile is generated based on the identifications of the product labels which are associated with a location of a product within a store.
US09659203B2	Low power multi-core decoder system and method A portable data terminal including a multi-core processor having at least a first core and a second core, at least one illumination assembly and at least one imaging assembly and data storage means configured to store a plurality of program instructions, the program instructions including at least one one-dimensional decoder and at least one two-dimensional decoder.
US09659202B2	Printing and extraction of 2D barcode on 3D objects A method for printing and extracting of a barcode for an object includes dividing a barcode into disjointed regions and assigning the disjointed regions to different locations on an object. The disjointed regions are printed on the object at the different locations wherein the disjointed regions are printed visibly or invisibly.
US09659201B2	Information code, information code producing method, information code reader, and system which uses information code An information code producing apparatus produces a free space inside the code region of an information code arranged on a medium such as sheets of paper. The free space is arranged at a position other than specification pattern regions. Data being interpreted, which are expressed by cells, are not recorded in the free space. The free space has a preset size which is larger than that of a single cell. The information code producing apparatus detects the size of this free space by, at least, either selection from a plurality of candidate shapes prepared in advance or input of shape designating information provided from the outside.
US09659200B2	Indicia reading system employing digital gain control A scanning code symbol reading system includes an analog scan data signal processor for producing digitized data signals, wherein during each laser beam scanning cycle, a light collection and photo-detection module generates an analog scan data signal corresponding to a laser scanned code symbol, an analog scan data signal processor/digitizer processes the analog scan data signal to generate digital data signals corresponding thereto, and a synchronized digital gain control module automatically processes the digitized data signals in response to start of scan (SOS) signals generated by a SOS detector. The synchronized digital gain control module generates digital control data which is transmitted to the analog scan data signal processor for use in controlling the gain of a signal processing stage in the light collection and photo-detection module and/or analog scan data signal processor, during the corresponding laser beam scanning cycle.
US09659199B2	Terminal with flicker-corrected aimer and alternating illumination An indicia reading terminal is disclosed that eliminates unwanted flickering effects in an illuminated screen reading mode, among other advantageous features. The indicia reading terminal, in response to a screen reading signal, is operative to activate a screen reading cycle. In the screen reading cycle, an imaging subsystem is activated at least once at the same time that an illumination subsystem is activated for one of a plurality of active illumination periods, for a first illuminated exposure period. The imaging subsystem is activated at least once while the illumination subsystem is not activated, for a first unilluminated exposure period, which is longer than the first illuminated exposure period. An aimer subsystem is activated for a plurality of active aimer periods when neither the imaging subsystem nor the illumination subsystem is activated, wherein intervals of time between the active aimer periods are equal, within nominal tolerances.
US09659198B2	System and method of determining if a surface is printed or a mobile device screen A system and method of determining if a surface contains print or is a screen of a mobile device is provided. The method is comprised of the steps of: acquiring a spectral wavelength signature of the surface; comparing the spectral wavelength signature of the surface to RGB triple-peak emission spectra; scanning the surface with an image-based scanner in non-illumination mode based upon the spectral wavelength signature of the surface corresponding to the RGB triple-peak emission spectra, and scanning the surface with an image-based scanner in illumination mode based upon the spectral wavelength signature of the surface not corresponding to the RGB triple-peak emission spectra.
US09659195B2	Tone-based wake up circuit for card reader A card reader for a point-of-sale system that is configured to accept both magnetic strip-type and integrated circuit (IC) chip-type payment cards. The card reader is a component of a point-of-sale system including a portable computing device in communication with the card reader that is configured to present a first graphical user interface (GUI) when a magnetic stripe-type card is detected and a second GUI when an IC chip-type card is detected in the card reader. The card reader comprises a slot configured to receive the payment card, a magnetic reading device and an IC chip reading device. The card reader also includes a discriminator contact disposed within the slot that is configured to conduct across a surface of a metal pad of the IC chip-type card prior to the CI chip reading device making contact with the IC chip.
US09659191B2	Encryption key storage and modification in a data storage device Methods, systems, and devices are described for encryption key storage and modification in a data storage device. A portion of an encryption key may be stored in a first storage medium, and one or more bits of the encryption key may be stored in a one-time writable storage location. Data received at the data storage device may be encrypted using the encryption key, and may be stored in a storage medium. In the event that it is no longer desired to allow users to access the encrypted data stored in the storage medium, the one or more bits of the encryption key stored in a one-time writable storage location may be modified. Such modification thereby prevents decryption of the encrypted data and effectively precludes access to the encrypted data.
US09659185B2	Method for detecting spammers and fake profiles in social networks A method for protecting user privacy in an online social network, according to which negative examples of fake profiles and positive examples of legitimate profiles are chosen from the database of existing users of the social network. Then, a predetermined set of features is extracted for each chosen fake and legitimate profile, by dividing the friends or followers of the chosen examples to communities and analyzing the relationships of each node inside and between the communities. Classifiers that can detect other existing fake profiles according to their features are constructed and trained by using supervised learning.

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