| Document | Document Title |
|---|---|
| US09660340B2 |
Multiband antenna
Two high frequency antennas are provided in a multilayer substrate. Each high frequency antenna is configured of a radiation element, a high frequency power supply line, and a high frequency power supply unit. A low frequency antenna is configured of a series radiation element, a low frequency power supply line, and a lower frequency power supply unit. The series radiation element is formed of two radiation elements connected by a radiation element connection line. One end side of the series radiation element is connected to the low frequency power supply unit via the low frequency power supply line. Open stubs to block transmission of a high frequency signal (SH) are connected to the radiation element connection line and the low frequency power supply line. Short stubs to block transmission of a low frequency signal (SL) are connected to the high frequency power supply lines. |
| US09660338B2 |
Method for multi-antenna signal processing at an antenna element arrangement, corresponding transceiver and corresponding antenna element arrangement
The present invention relates to a method for multi-antenna signal processing at an antenna element arrangement belonging to a transceiver of a radio communication network, the antenna element arrangement comprising antenna elements (211, 221, 231, 241) in horizontal and in vertical direction, wherein complex antenna weights are applied to said antenna elements. |
| US09660337B2 |
Multimode antenna structure
One or more embodiments are directed to a multimode antenna structure for transmitting and receiving electromagnetic signals in a communications device. The communications device includes circuitry for processing signals communicated to and from the antenna structure. The antenna structure is configured for optimal operation in a given frequency range. The antenna structure includes a plurality of antenna ports operatively coupled to the circuitry, and a plurality of antenna elements, each operatively coupled to a different one of the antenna ports. Each of the plurality of antenna elements is configured to have an electrical length selected to provide optimal operation within the given frequency range. The antenna structure also includes one or more connecting elements electrically connecting the antenna elements such that electrical currents on one antenna element flow to a connected neighboring antenna element and generally bypass the antenna port coupled to the neighboring antenna element. The electrical currents flowing through the one antenna element and the neighboring antenna element are generally equal in magnitude, such that an antenna mode excited by one antenna port is generally electrically isolated from a mode excited by another antenna port at a given desired signal frequency range without the use of a decoupling network connected to the antenna ports, and the antenna structure generates diverse antenna patterns. |
| US09660336B2 |
Systems, devices and methods for transmitting electrical signals through a faraday cage
Embodiments of the present disclosure provide devices, methods, and systems that support electrical connection, signal delivery, and/or communication between internal and external portions of a Faraday cage. In some embodiments, devices and methods are provided for transmitting electrical signals through a waveguide port of a Faraday cage. In some embodiments, aspects of the present disclosure are employed to adapt a magnetic resonance imaging system for communications between a scanner room and a control room. |
| US09660331B2 |
Radio modem antenna efficiency in on board diagnostic device
An on board diagnostic (OBD) device having a radio modem is provided. An antenna of the radio modem is connected to a printed circuit board (PCB) housed within a plastic housing, where the PCB has a ground plane which is extended by a conductive extension. The conductive extension lengthens an effective length of a counterpoise of the antenna without necessitating an increase in size of the OBD device/plastic housing, resulting in maintaining a small form factor for the OBD device, while increasing antenna efficiency and/or bandwidth. |
| US09660329B2 |
Directional antenna
A directional antenna including a ground plane, a feeding element and a radiating element is provided. The feeding element is adjacent to the ground plane and includes a feeding point. A coupling gap is formed between the radiating element and the feeding element, and the radiating element includes a coupling point. Both the coupling point of the radiating element and the feeding point of the feeding element are at the perpendicular line of a ground plane. Further, a distance between the coupling point and an open end of the radiating element is smaller than 0.16λ of a resonant frequency of the directional antenna. |
| US09660328B2 |
Mounting assembly for an integrated remote radio head and antenna system
A mounting assembly for a remote radio head, in one embodiment, comprising a body configured to hold the remote radio head and a mounting system to detachably couple the body to an antenna housing. The mounting system configured to facilitate alignment of the remote radio head ports with the antenna ports. |
| US09660322B1 |
Using a coarse positioning mechanism for precision pointing applications
Apparatus, systems and methods provide for compensating for pointing errors that may occur when using a coarse positioning mechanism for pointing a payload toward a target. According to aspects of the disclosure, a coarse positioning mechanism is configured to compensate for pointing errors that may occur when pointing a payload toward a target over a large angular FOV. The coarse positioning mechanism may be configured for a variety of applications, such as precision tracking applications and precision pointing applications over a large angular FOV. The coarse positioning mechanism may include adjustment mechanisms for one or more axes that are used to adjust the pointing direction of the target. |
| US09660321B2 |
Method and system for a mobile application (app) that assists with aiming or aligning a satellite dish or antenna
An app running on a communication device determines a current position of an antenna, which is to be aligned with a transmitter. The app determines a direction in which the antenna should be oriented so that the antenna is aligned with the transmitter when the communication device is placed by the antenna. The app may generate, based on the determined direction, one or more cues to enable alignment of the antenna so that the current position or a newly determined current position of the antenna is aligned with the determined position of the transmitter. The cues may include audible, visual and/or vibration cues. The app may acquire information from one or more sensors, which are located within the communication device and/or integrated within the antenna. The acquired information may be utilized to determine the current position and/or a newly determined current position of the antenna. |
| US09660313B2 |
Metal-air fuel cells and methods of removing spent fuel therefrom
This invention is directed to a metal-air electrochemical power sources, specifically zinc-air batteries and fuel cells, and methods for removing solid or semi-solid spent fuel using a thickener-liquefier pair. |
| US09660311B2 |
Aqueous lithium air batteries
Aqueous Li/Air secondary battery cells are configurable to achieve high energy density and prolonged cycle life. The cells include a protected a lithium metal or alloy anode and an aqueous catholyte in a cathode compartment. The aqueous catholyte comprises an evaporative-loss resistant and/or polyprotic active compound or active agent that partakes in the discharge reaction and effectuates cathode capacity for discharge in the acidic region. This leads to improved performance including one or more of increased specific energy, improved stability on open circuit, and prolonged cycle life, as well as various methods, including a method of operating an aqueous Li/Air cell to simultaneously achieve improved energy density and prolonged cycle life. |
| US09660308B2 |
Thermal protection case for a motor vehicle battery
A thermal protection device made from a polymer material, including two separate elements, a cover and a thermal protection case. The thermal protection case includes at least two foldable portions of which the link between the two is articulated about a hinge, the case configured to switch, by folding and unfolding, from a storage position to an operating position configured, by fixing to the battery support base that maintains the shape of same, to cover a motor vehicle battery, which may be in different formats depending on characteristics of the vehicle. |
| US09660305B2 |
Method of controlling storage battery, apparatus for controlling storage battery, and electric power control system
A method of controlling a high-temperature storage battery connected to an electric power system, an apparatus for controlling the storage battery, and an electric power control system reside in that, when the temperature of the storage battery is equal to or lower than a reference temperature, charging and discharging the storage battery with charging and discharging electric power, which is the sum of charging and discharging electric power based on a preset process of operating the storage battery and charging and discharging electric power corresponding to charging and discharging cycles each of a continuous charging time of 1 hour or shorter and a continuous discharging time of 1 hour or shorter, for thereby supplying thermal energy to the storage battery. |
| US09660303B2 |
Battery monitoring system
A battery monitoring device includes a sensor device, which is electrically connectable to an automobile battery and may be placed thereon, and which is arranged to detect an operating variable of the battery. The battery monitoring device further includes a detection circuit, which is connected via a cable connection to the sensor device; and a data processing circuit, which is connected via a potential isolation circuit to the detection circuit. The potential isolation circuit provides isolation of the potential level of the detection circuit from a potential level of the data processing circuit for direct components. |
| US09660300B2 |
Method for manufacturing sealed battery
A method for manufacturing a sealed battery includes: injecting an electrolytic solution into an exterior; introducing a detection gas into the exterior; and detecting a leakage by detecting a leakage of the detection gas introduced into the exterior, the electrolytic solution in an electrolytic solution tank is pressure fed into the exterior by pressurizing the electrolytic solution tank by feeding a gas of a kind the same as the detection gas in the electrolytic solution tank where the electrolytic solution is stored, in order to inject the electrolytic solution into the battery container. |
| US09660299B2 |
Strain measurement based battery testing
A method and system for strain-based estimation of the state of health of a battery, from an initial state to an aged state, is provided. A strain gauge is applied to the battery. A first strain measurement is performed on the battery, using the strain gauge, at a selected charge capacity of the battery and at the initial state of the battery. A second strain measurement is performed on the battery, using the strain gauge, at the selected charge capacity of the battery and at the aged state of the battery. The capacity degradation of the battery is estimated as the difference between the first and second strain measurements divided by the first strain measurement. |
| US09660297B2 |
Methods of producing batteries utilizing anode coatings directly on nanoporous separators
Provided are methods of preparing a separator/anode assembly for use in an electric current producing cell, wherein the assembly comprises an anode current collector layer interposed between a first anode layer and a second anode layer and a porous separator layer on the side of the first anode layer opposite to the anode current collector layer, wherein the first anode layer is coated directly on the separator layer. |
| US09660296B2 |
Electrode assembly having step, battery cell, battery pack and device including the same
There is provide an electrode assembly including an electrode laminate having a plurality of electrode units rolled up to be stacked on one another in at least two rectangularly shaped separation films, the electrode assembly being characterized in that at least one of two rectangularly shaped separation films is disposed on upper and lower surfaces of the respective electrode unit, at least one separation film disposed on one surface being different from a separation film disposed on another surface, and the electrode laminate includes at least one step formed by stacking an electrode unit having a difference in area from an electrode unit adjacent thereto, having one of the rectangularly shaped separation films as a boundary therebetween. |
| US09660295B2 |
Electrolyte and rechargeable lithium battery including the same
An electrolyte for a rechargeable lithium battery and a rechargeable lithium battery, the electrolyte including a lithium salt, a non-aqueous organic solvent, and an additive represented by the following Chemical Formula 1: wherein, in Chemical Formula 1, R1 to R3 are each independently a substituted or unsubstituted C1 to C10 alkylene group, a substituted or unsubstituted C3 to C30 cycloalkylene group, a substituted or unsubstituted C6 to C30 arylene group, or a substituted or unsubstituted C2 to C30 heteroarylene group. |
| US09660293B2 |
Method and system for battery protection
An electrical combination. The combination comprises a hand held power tool, a battery pack and a controller. The battery pack includes a battery pack housing connectable to and supportable by the hand held power tool, a plurality of battery cells supported by the battery pack housing, each of the plurality of battery cells having a lithium-based chemistry, being individually tapped and having an individual state of charge. A communication path is provided by a battery pack sense terminal and a power tool sense terminal. The controller is operable to monitor a state of charge of a number of battery cells less than the plurality of battery cells and to generate a signal based on the monitored state of charge of the number of battery cells less than the plurality of battery cells, the signal being operable to control the operation of the hand held power tool. |
| US09660292B2 |
Electrode structures for three-dimensional batteries
An electrode structure for use in an energy storage device comprising a population of electrodes, a population of counter-electrodes and a microporous separator separating members of the electrode population from members of the counter-electrode population. Each member of the electrode population comprises an electrode active material layer and an electrode current conductor layer, and each member of the electrode population has a bottom, a top, a length LE, a width WE and a height HE, wherein the ratio of LE to each of WE and HE is at least 5:1, the ratio of HE to WE is between 0.4:1 and 1000:1, and the electrode current collector layer of each member of the electrode population has a length LC that is measured in the same direction as and is at least 50% of length LE. |
| US09660287B2 |
Apparatus for preventing deformation of fuel cell stack
An apparatus for preventing deformation of a fuel cell stack is provided. The apparatus includes a support unit, respective ends of which are connected to first endplates of a pair of stacked fuel cell stacks. The apparatus further includes a support protrusion that protrudes from a surface of the support unit and extends through a gap between the pair of fuel cell stacks. |
| US09660285B2 |
Fuel cell and method for manufacturing the same
Disclosed are: a fuel cell which is provided with a membrane electrode assembly (50), an anode-side gas diffusion layer (52) and a cathode-side gas diffusion layer (54); and a method for manufacturing the cell. The degree of processing for suppressing protrusion of carbon fibers in the anode-side gas diffusion layer (52) and the degree of processing for suppressing protrusion of carbon fibers in the cathode-side gas diffusion layer (54) are set to be different from each other. Specifically, protrusion from the anode-side gas diffusion layer (52) is sufficiently suppressed, thereby being prevented from damaging the membrane electrode assembly (50). Meanwhile, the degree of suppression processing of the cathode-side gas diffusion layer (54) is set low, thereby securing drainage of generated water. |
| US09660284B2 |
Power conversion system
Provided is a power conversion system having a solid-oxide fuel cell capable of stably generating electricity from hydrogen generated by an organic hydride. The power conversion system includes a solid-oxide fuel cell, a reactor for producing hydrogen and a dehydrogenation product from an organic hydride by dehydrogenation reaction, and a heat engine for generating motive power. The power conversion system separates the hydrogen produced by the reactor, and supplies the hydrogen as fuel to the solid-oxide fuel cell. Exhaust heat of the heat engine is supplied to both the solid-oxide fuel cell and the reactor. |
| US09660283B2 |
Current measurement device
A current measurement device includes a measurement part that is constituted by including a resistance part having a predetermined electric resistance value and a pair of current collector parts for extracting a potential difference generated by a current that flows the resistance part; a potential difference detector that is connected to the pair of current collector parts and detects a potential difference generated in the resistance part; and a current detector that detects the current that flows through the inside of a fuel cell. The measurement part is disposed to be integrated with one separator of the pair of separators and the pair of current collectors is disposed so as to overlap with the resistance part when seen from a direction orthogonal to the stacking direction of the cells. |
| US09660280B2 |
System and method of controlling fuel cell system using a drain-purge valve
A system and method of controlling fuel cell system is provided that simultaneously drains condensation and purges hydrogen via single valve. In particular, condensate water is drained by opening a drain-purge valve at a point in time at which a production amount of the condensate water exceeds a capacity of a water trap. An opening time of the drain-purge valve is then determined depending on a hydrogen concentration of an anode side and a target hydrogen concentration after the draining the condensate water. Hydrogen is then purged by maintaining the drain-purge valve in a state in which it is opened for the determined opening time. |
| US09660275B2 |
Fuel cell including gas flow path layer
A fuel cell is configured to comprise a power generation layer including an electrolyte membrane, an anode and a cathode, separators and a gas flow path layer provided between the power generation layer and the separator. The gas flow path layer is structured by a plurality of corrugated elements. Each corrugated element has a corrugated cross section where first convexes that are convex toward the separator and second convexes that are convex toward the power generation layer are alternately arranged. The plurality of corrugated elements are arranged, such that a top surface of the first convex in one corrugated element and a bottom surface of the second convex in an adjacent corrugated element cooperatively form an integral surface, and a plurality of through holes are formed between the respective adjacent corrugated elements. The plurality of corrugated elements include a corrugated element having positions of the first convexes and the second convexes shifted in a positive side of the first direction from those of an adjacent corrugated element, and a corrugated element having positions of the first convexes and the second convexes shifted in a negative side of the first direction from those of an adjacent corrugated element. The volume of a first reaction gas flow path, which is formed along the positions of the second convexes on a separator-side of the gas flow path layer, is less than the volume of a second reaction gas flow path, which is formed along the positions of the first convexes on a power generation layer-side of the gas flow path layer. |
| US09660271B2 |
Resin composition
The present invention provides a resin composition for an electrically conductive resin film which is excellent in electric conductivity, tensile elongation, durability to bending and flexibility and is suitable as electrodes or protective coatings on the electrodes in redox flow batteries. A resin composition includes (A) 100 parts by mass of a thermoplastic resin, (B) 1 to 60 parts by mass of carbon nanotubes and (C) 1 to 100 parts by mass of at least one selected from the group consisting of acetylene black and graphite. |
| US09660268B2 |
Alkali-ion battery with enhanced transition metal cyanometallate electrode structure
An alkali-ion battery is provided with a transition metal cyanometallate (TMCM) sheet cathode and a non-alkaline metal anode. The fabrication method mixes TMCM powders, conductive additives, and a polytetrafluoroethylene binder with a solution containing water, forming a wet paste. The wet paste is formed into a free-standing sheet of cathode active material, which is laminated to a cathode current collector, forming a cathode electrode. The free-standing sheet of cathode active material has a thickness typically in the range of 100 microns to 2 millimeters. The cathode electrode is assembled with a non-alkaline metal anode electrode and an ion-permeable membrane interposed between the cathode electrode and anode electrode, forming an assembly. The assembly is dried at a temperature of greater than 100 degrees C. The dried assembly is then inserted into a container (case) and electrolyte is added. Thick anodes made from free-standing sheets of active material can be similarly formed. |
| US09660263B2 |
Layered oxide materials for batteries
Materials are presented of the formula: Ax My Mizi O2−d, where A is sodium or a mixed alkali metal including sodium as a major constituent; x>0; M is a metal or germanium; y>0; Mi, for i=1, 2, 3 . . . n, is a transition metal or an alkali metal; zi≧0 for each i=1, 2, 3 . . . n; 0 |
| US09660260B2 |
Cathode active material coated with fluorine-doped lithium metal manganese oxide and lithium-ion secondary battery comprising the same
Provided are a cathode active material coated with a fluorine-doped spinel-structured lithium metal manganese oxide, a lithium secondary battery including the same, and a method for preparing the same. The cathode active material has improved chemical stability and provides improved charge/discharge characteristics at elevated temperature (55-60° C.) and high rate. The cathode active material allows lithium ions to pass through the coating layer with ease and is chemically stable, and thus may be used effectively as a cathode active material for a high-power lithium secondary battery. |
| US09660258B2 |
Lithium-ion secondary battery
The negative electrode is formed from silicon, an amount of heat generation in a negative electrode, which is measured by a differential scanning calorimeter within a range of 210 to 380° C. during full charge, is 850 J/g or less, and a cyclic carbonate including ethylene carbonate and a chain carbonate which has a chemical formula expressed by R1—O—CO—OR2, and in which R1 and R2 represent an alkyl group having a carbon number of 2 or more are used for an electrolytic solution. |
| US09660257B2 |
Storage element
A storage element for a solid-electrolyte battery is provided, having a main body which is composed of a porous matrix of sintered ceramic particles, and also having a redox system which is composed of a first metal and/or at least one oxide of the first metal, wherein a basic composition of the storage element comprises at least one further oxide from the group comprising Y2O3, MgO, Gd2O3, WO3, ZnO, MnO which is suitable for forming an oxidic mixed phase with the first metal and/or the at least one oxide of the first metal. |
| US09660253B2 |
Positive electrode active material for sodium battery, and method of producing the same
The invention provides a positive electrode active material for sodium batteries which has a high working potential and can be charged and discharged at a high potential. The invention also provides a method of producing such a positive electrode active material, with this positive electrode active material for sodium batteries being represented by general formula (1) below: NaxMy(AO4)z(P2O7)w (1) (wherein M is at least one selected from the group consisting of titanium, vanadium, chromium, manganese, iron, cobalt, nickel, copper and zinc; A is at least one selected from the group consisting of aluminum, silicon, phosphorus, sulfur, titanium, vanadium and tungsten; x satisfies the condition 4≧x≧2; y satisfies the condition 4≧y≧1, z satisfies the condition 4≧z≧0; w satisfies the condition 1≧w≧0; and one or both of z and w is 1 or more). |
| US09660249B2 |
Rechargeable battery having a fuse
A rechargeable battery includes an electrode assembly; a case housing the electrode assembly; and an electrode connection assembly electrically coupled to the electrode assembly, the electrode connection assembly including: a terminal; a current collector electrically coupled to the electrode assembly; an insulating member between the terminal and the current collector, wherein a portion of the insulating member is spaced from the terminal and the current collector; and a connection member electrically coupling the terminal and the current collector, the connection member including a fuse part, wherein the portion of the insulating member overlaps with the connection member. |
| US09660243B2 |
Battery wiring module
A battery wiring module in which connection members are held by a resin protector, the connection members connecting adjacent electrode terminals of a plurality of single batteries, the single batteries having the positive and negative electrode terminals, as well as a battery-side detection terminal for detecting a status of the single battery. The battery wiring module includes a voltage detection terminal, which includes a flat plate-shaped flat plate and a wire connection connected to a terminal end of a wire. The resin protector includes an opening, which enables the battery-side detection terminal to contact the flat plate of the voltage detection terminal. The voltage detection terminal includes an engaged portion extending on a different plane than that of the flat plate. The engaged portion is engaged with a first engagement portion provided to the resin protector. |
| US09660240B2 |
Secondary battery including separator containing electroconductive porous layer sandwiched between electroconductive material-free porous layers
Provided is a very safe secondary battery that can prevent the occurrence of battery abnormalities even when the internal battery temperature increases due to, for example, overcharging. A separator 70 in this secondary battery has a laminated structure that is provided with at least two porous layers 76A, 72, 76B, wherein one of these layers forms a porous electroconductive layer 72 in which an electroconductive material 74 is dispersed in the porous layer. |
| US09660238B2 |
Slurry for secondary battery porous membrane, a secondary battery porous membrane, an electrode for secondary battery, a separator for secondary battery and a secondary battery
A secondary battery porous membrane, manufactured by a slurry for secondary battery porous membrane, which is superior in coating priority and dispersibility of non-conductive organic particles, which improves cycle characteristic of the obtained secondary battery, which has high flexibility and can prevent powder falls, and which has less content of moisture amount; and non-conductive organic particles, which can be suitably used as a secondary battery porous membrane and has less content of metallic foreign particles. The slurry for secondary battery porous membrane comprises; a binder including a polymerized unit of vinyl monomer having a hydrophilic acid group, a non-conductive organic particle having a functional group, cross-linkable with the hydrophilic acid group and a solvent. |
| US09660237B2 |
Manifold vent channel for a battery module
The present disclosure includes a battery module having a housing that includes a lid and a battery cell with a battery cell terminal and a battery cell vent on an end of the battery cell. The battery cell vent is configured to exhaust battery cell effluent. The battery module includes a printed circuit board positioned in an immediate vent direction of the battery cell, a vent shield channel positioned between the battery cell vent and the printed circuit board along the immediate vent direction of battery cell effluent, where the vent shield plate is immediately adjacent to the printed circuit board and configured to block the effluent from contacting the printed circuit board and to redirect the battery cell effluent along a desired vent path, and a module vent fluidly coupled to the desired vent path and configured to direct the battery cell effluent out of the battery module. |
| US09660236B2 |
Battery and saddle-type electric vehicle equipped therewith
A battery includes a controller configured or programmed to manage battery cells disposed inside a housing. The controller is arranged one of forward or rearward of the battery cells. The housing includes right and left housing half bodies which define right and left portions of the housing, respectively, and are assembled together in a lateral direction. The battery prevents an increase in the width of a saddle-type electric vehicle while securing a sufficient capacity of the housing. |
| US09660234B2 |
Battery enclosure with arc-shaped elongated impact absorbing ribs
An enclosure for a traction motor battery of a vehicle is disclosed that includes a plurality of impact absorbing members on the exterior of the enclosure. The impact absorbing members have an arc-shaped or partially cylindrical wall and a flat wall that define a partially cylindrical pocket. In an impact, the arc-shaped wall collapses toward the flat wall to absorb the impact force. |
| US09660230B2 |
Battery pack having end plates
Provided is a battery pack including a pair of end plates facing each other, a plurality of battery cells arrayed between the end plates, and a pair of side plates each extending along a length of the plurality of battery cells, and coupled to the end plates, wherein each of the end plates includes a base plate, bending portions bent from each edge of the base plate in a direction away from the plurality of battery cells, each bending portion having a reinforcing bead unit, and a flange portion connected to the base plate at each bending portion. According to one or more embodiments of the present invention, deformation of the battery pack may be efficiently suppressed and deterioration of a function of a battery cell may be prevented by blocking volume expansion due to recharging and discharging operations of the battery cell. |
| US09660229B2 |
Battery pack release with tactile feedback for cordless power tools
Battery packs include a battery pack housing, at least one battery release member held by the battery housing, a (blind) latch held by the battery pack housing in communication with the battery release member that releaseably locks the battery pack to a device, and a tactile feedback mechanism that is held by the battery pack housing and is in communication with the battery release member. The tactile feedback mechanism generates a tactile feedback that reduces or increases an application force required by a user to manually actuate the at least one release member. The tactile feedback transmitted through the at least one battery release member. The tactile feedback is generated when the at least one release member has been manually actuated by the user a sufficient distance to allow the user to easily remove the battery pack from the device. |
| US09660227B2 |
Sealing plate for prismatic secondary battery and prismatic secondary battery using the sealing plate
A prismatic secondary battery includes a prismatic hollow outer body having a mouth and a bottom; a flat electrode assembly, a positive electrode collector, a negative electrode collector, and an electrolyte, all of which are stored in the prismatic outer body; a sealing plate sealing up the mouth of the prismatic outer body; and a positive electrode terminal attached to the sealing plate in an electrically insulated manner. The sealing plate includes a gas release valve and an electrolyte pour hole and further includes, on the front face, a concaved flat face having an identification code. With the prismatic secondary battery of the invention, a jig for assembly or the like is unlikely to come into contact with the identification code during an assembly process of the prismatic secondary battery, hence the identification code is unlikely to be abraded, and the traceability is unlikely to be lost. |
| US09660221B2 |
Display devices using feedback enhanced light emitting diode
Display devices using feedback-enhanced light emitting diodes are disclosed. The display devices include but are not limited to active and passive matrix displays and projection displays. A light emissive element disposed between feedback elements is used as light emitting element in the display devices. The light emissive element may include organic or non-organic material. The feedback elements coupled to an emissive element allow the emissive element to emit collimated light by stimulated emission. In one aspect, feedback elements that provide this function include, but are not limited to, holographic reflectors with refractive index variations that are continuous. |
| US09660217B2 |
Light emitting element and method for maufacturing light emitting element
A light emitting element includes a base member, a sealing member disposed to face the base member, a concave-convex structure layer, a first electrode, an organic layer, a second electrode, and an adhesive layer. The concave-convex structure layer, the first electrode, the organic layer, and the second electrode are formed on the base member in that order. The adhesive layer is positioned between the base member and the sealing member. An outer periphery of the concave-convex structure layer is positioned between an inner periphery and an outer periphery of the adhesive layer. The light emitting element includes the concave-convex structure layer functioning as a diffracting grating, and thus light extraction efficiency thereof is excellent. Further, a light emitting part is sealed with sufficient sealing performance and deterioration of the light emitting part due to moisture and oxygen is prevented. Thus, the light emitting element has a long service life. |
| US09660216B2 |
Light-transmitting adhesive film and display device comprising the same
A light-transmissive adhesive film includes an adhesive layer in which an elastic modulus in a second area is higher than that in a first area, and also includes release layers on upper and lower portions of the adhesive layer. |
| US09660208B2 |
Transparent gas barrier film, method for producing transparent gas barrier film, organic EL element, solar battery, and thin film battery
A transparent gas barrier film that has excellent gas barrier properties and includes a transparent gas barrier layer having a very low internal stress, and a method for producing the same. The transparent gas barrier film according to the present invention includes: a resin substrate; and a transparent gas barrier layer formed over the resin substrate. The transparent gas barrier layer includes at least one kind selected from the group consisting of metals and metalloids. The transparent gas barrier layer includes a plurality of layers each having a density that changes continuously from high density to low density or from low density to high density and then cycles alternatively from low density to high density or high density to low density, respectively, once or two or more times. |
| US09660205B2 |
Protective coatings for organic electronic devices made using atomic layer deposition and molecular layer deposition techniques
Coatings are applied on a flexible substrate using atomic layer deposition and molecular layer deposition methods. The coatings have thickness of up to 100 nanometers. The coatings include layers of an inorganic material such as alumina, which are separated by flexibilizing layers that are deposited with covalent chemical linkage to the inorganic material and which are one or more of silica deposited by an atomic layer deposition process; an organic polymer that is deposited by a molecular layer deposition process, or a hybrid organic-inorganic polymer that is deposited by an molecular layer deposition process. |
| US09660203B2 |
Material for organic electroluminescence device and organic electroluminescence device using the same
Provided are an organic electroluminescence device, which shows high luminous efficiency, is free of any pixel defect, and has a long lifetime, and a material for an organic electroluminescence device for realizing the device. The material for an organic electroluminescence device is a compound having a π-conjugated heteroacene skeleton crosslinked with a carbon atom, nitrogen atom, oxygen atom, or sulfur atom. The organic electroluminescence device has one or more organic thin film layers including a light emitting layer between a cathode and an anode, and at least one layer of the organic thin film layers contains the material for an organic electroluminescence device. |
| US09660198B2 |
Organic electroluminescence element and compound used therein
An organic electroluminescence element in which a compound represented by the general formula below is used in a light-emitting layer exhibits a high emission efficiency and is inexpensive to provide. At least one of R1 to R8 and R17 represent an electron-donating group and the others represent a hydrogen atom; at least one of R9 to R16 represent an electron-withdrawing group that does not have an unshared electron pair at the α-position thereof and the others represent a hydrogen atom; Z represents a single bond or >C═Y; Y represents O, S, C(CN)2 or C(COOH)2; provided that when Z is a single bond, then at least one of R9 to R16 is an electron-withdrawing group that does not have an unshared electron pair at the α-position thereof. |
| US09660193B2 |
Material composition for organic photoelectric conversion layer, organic photoelectric conversion element, method for producing organic photoelectric conversion element, and solar cell
It is an object of the present invention to provide a material composition for a bulk-heterojunction-type organic photoelectric conversion layer having high photoelectric conversion efficiency and durability through formation of a stable phase-separated structure by drying in a short time with high productivity and to provide an organic photoelectric conversion element, a method of producing the organic photoelectric conversion element, and a solar cell. The material composition for an organic photoelectric conversion layer contains at least a p-type conjugated polymer semiconductor material being a copolymer having a main chain including an electron-donating group and an electron-withdrawing group, an n-type organic semiconductor material having electron acceptability, and a solvent. The solvent is represented by a general formula (1). |
| US09660189B1 |
Barrier layer for correlated electron material
Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to one or more barrier layers having various characteristics formed under and/or over and/or around correlated electron material. |
| US09660179B1 |
Enhanced coercivity in MTJ devices by contact depth control
A magnetic memory device includes a magnetic memory stack including a bottom electrode and having a hard mask formed thereon. An encapsulation layer is formed over sides of the magnetic memory stack and has a thickness adjacent to the sides formed on the bottom electrode. A dielectric material is formed over the encapsulation layer and is removed from over the hard mask and gapped apart from the encapsulation layer on the sides of the magnetic memory stack to form trenches between the dielectric material and the encapsulation layer at the sides of the magnetic memory stack. A top electrode is formed over the hard mask and in the trenches such that the top electrode is spaced apart from the bottom electrode by at least the thickness. |
| US09660178B2 |
Electronic device and method for fabricating the same
Provided is an electronic device. The electronic device according to an implementation of the disclosed technology includes a semiconductor memory, the semiconductor memory including: a substrate; an interlayer insulating layer formed over the substrate; a metal-containing insulating layer formed over the interlayer insulating layer and including a second metal; a contact hole formed through the interlayer insulating layer and the metal-containing insulating layer; a contact plug filling a portion of the contact hole; a contact pad formed over the contact plug so as to fill the remaining portion of the contact hole; and a variable resistance element formed over the contact pad, wherein the contact pad includes a metal-containing material including a first metal, and the second metal has a higher electron affinity than the first metal. |
| US09660177B2 |
Method to minimize MTJ sidewall damage and bottom electrode redeposition using IBE trimming
An improved method for etching a magnetic tunneling junction (MTJ) structure is achieved. A stack of MTJ layers is provided on a bottom electrode. The MTJ stack is patterned to form a MTJ device wherein sidewall damage or sidewall redeposition is formed on sidewalls of the MTJ device. A dielectric layer is deposited on the MTJ device and the bottom electrode. The dielectric layer is etched away using ion beam etching at an angle relative to vertical of greater than 50 degrees wherein the dielectric layer on the sidewalls is etched away and wherein sidewall damage or sidewall redeposition is also removed and wherein some of the dielectric layer remains on horizontal surfaces of the bottom electrode. |
| US09660174B2 |
Piezoelectric material and piezoelectric element using the same, and electronic apparatus using the piezoelectronic element
Provided is a lead-free piezoelectric material having a high Curie temperature, a satisfactory mechanical quality factor, and a satisfactory Young's modulus, and a piezoelectric element and a multilayered piezoelectric element each using the piezoelectric material. The piezoelectric material contains 0.04 mol % or more to 2.00 mol % or less of Cu with respect to 1 mol of a perovskite-type metal oxide represented by the following general formula: (KvBiwBa1-v-w)1-yNax(NbyTi1-y)O3 where relationships of 0 |
| US09660172B2 |
Vibrator
There is provided a vibrator including: an elastic member of which both end portions are fixedly attached to a housing; a piezoelectric element installed on one surface of the elastic member; and a circuit board attached to the elastic member to be connected to the piezoelectric element, wherein an opening portion for a connection between the piezoelectric element and the circuit board is provided in the elastic member, and a step portion insertedly disposed in the opening portion is formed at the circuit board. |
| US09660171B2 |
Electronic component and acoustic wave device
An electronic component has a mounting board, a bump located on a mounting surface of the mounting board, a SAW device located on the bump and connected to the bump. The SAW device has an element substrate, an excitation electrode located on the first primary surface of the element substrate, a pad located on the first primary surface and connected to the excitation electrode, and a cover located above the excitation electrode and formed with a pad exposure portion on the pad. Further, the SAW device makes the top surface of the cover face the mounting surface, makes the bump be located in the pad exposure portion, and makes the pad abut against the bump. |
| US09660169B2 |
Sensors and method of operating sensor
Sensors and methods of operating sensors are described herein. One sensor includes a number of III-nitride strain sensitive devices and a number of passive electrical components that connects each of them to one of the III-nitride strain sensitive devices. |
| US09660167B2 |
Wound and folded thermoelectric systems and method for producing same
A thermoelectric system includes a plurality of thermocouples that are each formed of two thermocouple limbs that include different thermoelectrically active materials. The thermocouple limbs are connected electrically in series and thermally in parallel. The thermodynamic system also includes a flexible and electrically insulating layer formed of a matrix having n rows of thermocouple limbs. The thermocouple limbs form columns having approximately equal widths. Each pair of adjacent thermocouple limbs has a contact region located on a straight fold line above one another in the column direction. The matrix is wound parallel to the rows on top of one another to form a flat strip. The matrix is then folded along the fold lines in the manner of a concertina with elevations and depressions equidistant to one another. |
| US09660166B2 |
Thermoelectric conversion material, thermoelectric conversion element, article for thermoelectric power generation and power supply for sensor
A thermoelectric conversion element (1) having, on a substrate (12), a first electrode (13), a thermoelectric conversion layer (14), and a second electrode 15, wherein a nano conductive material and a low band gap material are contained in the thermoelectric conversion layer (14); an article for thermoelectric power generation and a power supply for a sensor using the thermoelectric conversion element (1); and a thermoelectric conversion material containing the nano conductive material and the low band gap material. |
| US09660165B2 |
Thermoelectric conversion material and producing method thereof, and thermoelectric conversion element using the same
Thermoelectric conversion materials, expressed by the following formula: Bi1-xMxCu1-wOa-yQ1yTeb-zQ2z. Here, M is at least one element selected from the group consisting of Ba, Sr, Ca, Mg, Cs, K, Na, Cd, Hg, Sn, Pb, Mn, Ga, In, Tl, As and Sb; Q1 and Q2 are at least one element selected from the group consisting of S, Se, As and Sb; x, y, z, w, a, and b are 0≦x<1, 0 |
| US09660164B2 |
Light emitting device with reduced epi stress
Elements are added to a light emitting device to reduce the stress within the light emitting device caused by thermal cycling. Alternatively, or additionally, materials are selected for forming contacts within a light emitting device based on their coefficient of thermal expansion and their relative cost, copper alloys being less expensive than gold, and providing a lower coefficient of thermal expansion than copper. Elements of the light emitting device may also be structured to distribute the stress during thermal cycling. |
| US09660163B2 |
Semiconductor light-emitting device and method of manufacturing the same
A semiconductor light-emitting device, and a method of manufacturing the same. The semiconductor light-emitting device includes a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked on a substrate, a first contact that passes through the substrate to be electrically connected to the first electrode layer, and a second contact that passes through the substrate, the first electrode layer, and the insulating layer to communicate with the second electrode layer. The first electrode layer is electrically connected to the first semiconductor layer by filling a contact hole that passes through the second electrode layer, the second semiconductor layer, and the active layer, and the insulating layer surrounds an inner circumferential surface of the contact hole to insulate the first electrode layer from the second electrode layer. |
| US09660162B2 |
Illumination device
Provided is an illumination device that includes a light emitting device having a first electrode and a second electrode and a mounting substrate including a first wiring pattern and a second wiring pattern. The first wiring pattern and the second wiring pattern face and are bonded to the first electrode and the second electrode, respectively, through a bonding material. The second electrode and the second wiring pattern are configured to be at least partially overlapped with each other in a plan view irrespective of an orientation of the light emitting device, under condition that the first electrode and the first wiring pattern are at least partially overlapped with each other in the plan view. |
| US09660159B2 |
Wiring material, semiconductor device provided with a wiring using the wiring material and method of manufacturing thereof
A semiconductor device having good TFT characteristics is realized. By using a high purity target as a target, using a single gas, argon (Ar), as a sputtering gas, setting the substrate temperature equal to or less than 300° C., and setting the sputtering gas pressure from 1.0 Pa to 3.0 Pa, the film stress of a film is made from −1×1010 dyn/cm2 to 1×1010 dyn/cm2. By thus using a conducting film in which the amount of sodium contained within the film is equal to or less than 0.3 ppm, preferably equal to or less than 0.1 ppm, and having a low electrical resistivity (equal to or less than 40 μΩ·cm), as a gate wiring material and a material for other wirings of a TFT, the operating performance and the reliability of a semiconductor device provided with the TFT can be increased. |
| US09660158B2 |
Infrared emitter
The disclosure concerns an infrared emitter is provided comprising a metalized membrane emitting infrared light in operation. The membrane comprises a two dimensional array of infrared wavelength sized through-holes and to each side a thin metal layer comprising also an array of through-holes. The through-holes are arranged as a two-dimensional periodic array and each of said through-holes have a cross section having a maximum and a minimum dimension of less than any wavelength of the emitted infrared light. The peak wavelength of the emitted infrared light is proportional to the periodicity of the through-holes. At least one of the metal layers is connected to an electrical current source that provides an electrical current that heats at least one of the metal layers so that a narrow bandwidth and highly directive light beam of infrared light is emitted. The membrane is arranged on a membrane support and both are made of a material that resists to temperatures higher than 400°. |
| US09660152B2 |
System and method for selected pump LEDs with multiple phosphors
An LED pump light with multiple phosphors is described. LEDs emitting radiation at violet and/or ultraviolet wavelengths are used to pump phosphor materials that emit other colors. The LEDs operating in different wavelength ranges are arranged to reduce light re-absorption and improve light output efficiency. |
| US09660150B2 |
Semiconductor light-emitting device
A semiconductor light-emitting device includes a substrate, an LED chip, a control element, a conductive layer and an insulating layer. The substrate, made of a semiconductor material, has an obverse surface and a reverse surface spaced apart from each other in the thickness direction of the substrate. The control element controls light emission of the LED chip. The conductive layer is electrically connected to the LED chip and the control element. The insulating layer is arranged between at least apart of the conductive layer and the substrate. The substrate has a recess formed in the obverse surface, and the LED chip is housed in the recess. The control element is arranged between the LED chip and the reverse surface in the thickness direction of the substrate. |
| US09660149B2 |
Phosphor and LED light emitting device using the same
An LED light emitting device is provided that has high color rendering properties and is excellent color uniformity and, at the same time, can realize even luminescence unattainable by conventional techniques. A phosphor having a composition represented by formula: (Sr2-X-Y-Z-ωBaXMgYMnZEuω)SiO4 wherein x, y, z, and ω are respectively coefficients satisfying 0.1 |
| US09660145B2 |
Light emitting device, light emitting device package having the same and light system having the same
A light emitting device is provided that may include a substrate, a light emitting structure including a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer provided on the substrate, a first electrode on the first conductive semiconductor layer, and a schottky guide ring configured to surround the first electrode and directly connect with the first conductive semiconductor layer. |
| US09660143B2 |
Substrate and light emitting diode
The present invention relates to a substrate having an upper surface that is not parallel to a reference plane, wherein the substrate may include the upper surface or an upper layer which is inclined or inflexed. In addition, the present invention relates to a light emitting diode comprising an active layer that is not parallel to a reference plane. The light emitting diode of the present invention may be characterized in that the active layer is inflexed. Furthermore, the light emitting diode of the present invention may be characterized in that the side wall of the light emitting diode is inflexed. Moreover, the light emitting diode of the present invention may be characterized in that the side wall of the light emitting diode is inflexed and inclined. Through the configuration, the size of a chip is identically maintained, and the area of the active layer for emitting light is increased. In addition, the area of the exposed active layer at the edge of the chip is increased, and light emitted from the side surface thereof is oriented toward the front side thereof, thereby enhancing a utilization rate of the emitted light. |
| US09660142B2 |
Light emitting diode with nanostructured layer and methods of making and using
A light emitting diode has a plurality of layers including at least two semiconductor layers. A first layer of the plurality of layers has a nanostructured surface which includes a quasi-periodic, anisotropic array of elongated ridge elements having a wave-ordered structure pattern, each ridge element having a wavelike cross-section and oriented substantially in a first direction. |
| US09660141B2 |
Pattern wafer for LEDs, epitaxial wafer for LEDs and method of manufacturing the epitaxial wafer for LEDs
A pattern wafer (10) for LEDs is provided with an uneven structure A (20) having an arrangement with n-fold symmetry substantially on at least a part of the main surface, where in at least a part of the uneven structure A (20), a rotation shift angle Θ meets 0°<Θ≦(180/n)° in which Θ is the rotation shift angle of an arrangement axis A of the uneven structure A (20) with respect to a crystal axis direction in the main surface, and a top of the convex-portion of the uneven structure A (20) is a corner portion with a radius of curvature exceeding “0”. A first semiconductor layer (30), light emitting semiconductor layer (40) and second semiconductor layer (50) are layered on the uneven structure A (20) to constitute an epitaxial wafer (100) for LEDs. It is possible to provide the pattern wafer for LEDs and epitaxial wafer for LEDs with cracks and internal quantum efficiency IQE improved. |
| US09660140B2 |
Ultraviolet light emitting diode and method for producing same
An ultraviolet LED having increased light extraction efficiency includes: a single crystal sapphire substrate on which an array of protruding portions are formed; an AlN crystal buffer layer formed on the sapphire substrate; and an ultraviolet light emitting layer, in contact with the buffer layer, formed into a layered stack including an n-type conductive layer, a recombination layer, and a p-type conductive layer, in order from the buffer layer. The buffer layer includes a pillar array section and an integration section wherein pillars in the array are connected with one another. Each pillar extends from a protruding portion of the sapphire substrate, in a direction normal to one surface thereof. The pillars are separated from one another in the plane of the surface by a gap G. Light emitted from the ultraviolet light emitting layer is extracted to the outside through the pillar array section and the sapphire substrate. |
| US09660136B2 |
Nitride nanowires and method of producing such
The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor. |
| US09660133B2 |
Group III nitride heterostructure for optoelectronic device
Heterostructures for use in optoelectronic devices are described. One or more parameters of the heterostructure can be configured to improve the reliability of the corresponding optoelectronic device. The materials used to create the active structure of the device can be considered in configuring various parameters the n-type and/or p-type sides of the heterostructure. |
| US09660132B2 |
Method of manufacturing solar cell
A solar cell includes a solar cell substrate including a principal surface on which a p-type surface and an n-type surface are exposed, a p-side electrode formed on the p-type surface and including a first linear portion linearly extending in a first direction, and an n-side electrode formed on the n-type surface and including a second linear portion linearly extending in the first direction and arranged next to the first linear portion in a second direction orthogonal to the first direction. Corners of a tip end of at least one of the first and second linear portions are formed in a chamfered shape. |
| US09660129B2 |
Solar cell
A solar cell is discussed, which includes a pair of connecting electrodes having a portion having a width smaller than a width of a plurality of bus bar electrodes, and the pair of connecting electrodes connects a plurality of second finger electrodes to both sides of an end of one of the plurality of bus bar electrodes, respectively, wherein the end of the one of the plurality of bus bar electrodes being positioned in a second direction, wherein an area not including the plurality of second finger electrodes is positioned between the pair of connecting electrodes, and wherein an auxiliary electrode not connected to the plurality of second finger electrodes and having a width smaller than the width of the plurality of bus bar electrodes is disposed in the area not including the plurality of second finger electrodes. |
| US09660125B2 |
Method of making a modular off-axis solar concentrator
A method of making a solar concentrator may include forming a receiving wall having an elongated wall, a first side wall and a second side wall; attaching the first side wall and the second side wall to a reflecting wall to form a housing having an internal volume with an opening; forming a lip on the receiving wall and the reflecting wall; attaching a cover to the receiving wall and the reflecting wall at the lip to seal the opening into the internal volume, thereby creating a rigid structure; and mounting at least one receiver having at least one photovoltaic cell on the elongated wall to receive solar radiation entering the housing and reflected by the receiving wall, the receiver having an axis parallel with a surface normal of the photovoltaic cell, such that the axis is disposed at a non-zero angle relative to the vertical axis of the opening. |
| US09660122B2 |
Compact LCPV solar electric generator
A compact low concentration photovoltaic (LCPV) apparatus totally enclosed in a protective clear dome against harsh environment without active cooling. A conical mirror reflector, a circular lens refractor and a planar circular crystalline silicon photovoltaic solar panel rotate simultaneously inside the dome to concentrate sun rays and instantly produce electricity. The mirror increases electrical current three times and the lens increases one time for total four times using low overall concentration of five to twenty times sun. The lens is offset from the plane parallel to the photovoltaic solar panel, while the panels forming the mirror are angled offset to a center axis perpendicular to the solar panel. The optical assembly and solar panel are mounted in a conical aluminum cage which is pivoted from a rotary turntable for the daily azimuth and altitude rotations. The dual axis movements consist of irregular intermittent increments of less than one second “on time” and less than two minutes “off time” while following the sun path. The electrical power produced is at least two times more than from fixed conventional crystalline silicon solar panel occupying the same planar surface area. LCPV dual tracking systems offer reduced electricity generation costs, reduced installation costs and increased flexibility in deployment. |
| US09660118B2 |
Laminate for solar cell and solar cell module produced using same
Provided are a laminate for solar cells, which facilitates production of solar cell modules, which does not require a crosslinking step and which is excellent in transparency, moisture-proofness, sealability and handleability (rigidity), and a solar cell module produced by the use of the laminate. The laminate for solar cells has a resin layer (I)-1 or a resin layer (I)-2 as at least one outermost layer thereof, and has a resin layer (II) that contains an etylene-based polymer (C) satisfying a specific requirement and a nucleating agent (D). The resin layer (I)-1 is a resin layer containing an ethylene/α-olefin random copolymer (A) satisfying a specific requirement, and an ethylene/α-olefin block copolymer (B) satisfying a specific requirement. The resin layer (I)-2 is a resin layer containing a silane-modified etylene-based resin (X). |
| US09660108B2 |
Bootstrap MOS for high voltage applications
A device includes a p-well region, and a first High-Voltage N-type Well (HVNW) region and a second HVNW region contacting opposite edges of the p-well region. A P-type Buried Layer (PBL) has opposite edges in contact with the first HVNW region and the second HVNW region. An n-type buried well region is underlying the PBL. The p-well region and the n-type buried well region are in contact with a top surface and a bottom surface, respectively, of the PBL. The device further includes a n-well region in a top portion of the p-well region, an n-type source region in the n-well region, a gate stack overlapping a portion of the p-well region and a portion of the second HVNW region, and a channel region under the gate stack. The channel region interconnects the n-well region and the second HVNW region. |
| US09660100B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device is formed in such a manner that a first insulator, a first oxide semiconductor, and a first conductor are formed; the first conductor is processed to form a second conductor; the first oxide semiconductor is processed to form a second oxide semiconductor; a second insulator is formed over the second conductor; a third insulator is formed over the second insulator; a fourth insulator is formed over the third insulator; the fourth insulator, the third insulator, the second insulator, and the second conductor are selectively processed to partly expose the second oxide semiconductor; a fifth insulator is formed over the second oxide semiconductor and the fourth insulator; and a third conductor is formed over the fifth insulator and then chemical mechanical polishing treatment is performed to expose a top surface of the fourth insulator. |
| US09660099B2 |
Thin film transistor substrate and method of manufacturing the same
A thin film transistor substrate includes a gate electrode disposed on a base substrate, an active pattern overlapping the gate electrode, a source metal pattern including both a source electrode disposed on the active pattern and a drain electrode spaced apart from the source electrode, a buffer layer disposed on the source metal pattern and contacting the active pattern, a first passivation layer disposed on the buffer layer and a second passivation layer disposed on the first passivation layer. The density of hydrogen in the buffer layer is greater than the density of hydrogen in the first passivation layer and less than the density of hydrogen in the second passivation layer. |
| US09660095B2 |
Semiconductor device
Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion. |
| US09660093B2 |
Transistor with multilayer film including oxide semiconductor layer and oxide layer
Stable electrical characteristics of a transistor including an oxide semiconductor layer are achieved. A highly reliable semiconductor device including the transistor is provided. The semiconductor device includes a multilayer film formed of an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the oxide layer, and a gate electrode overlapping with the multilayer film with the gate insulating film interposed therebetween. The oxide layer contains a common element to the oxide semiconductor layer and has a large energy gap than the oxide semiconductor layer. The composition between the oxide layer and the oxide semiconductor layer gradually changes. |
| US09660092B2 |
Oxide semiconductor thin film transistor including oxygen release layer
Provided is a semiconductor device including an oxide semiconductor and having stable electrical characteristics. Specifically, a semiconductor device including an oxide semiconductor and including a gate insulating film with favorable characteristics is provided. Further, a method for manufacturing the semiconductor device is provided. The semiconductor device includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, and a source electrode and a drain electrode in contact with the oxide semiconductor film. The gate insulating film includes at least a silicon oxynitride film and an oxygen release type oxide film which is formed over the silicon oxynitride film. The oxide semiconductor film is formed on and in contact with the oxygen release type oxide film. |
| US09660091B2 |
Thin film transistor and method of driving same
A thin film transistor (TFT) and a method of driving the same are disclosed. The TFT includes: an active layer; a bottom gate electrode disposed below the active layer to drive a first region of the active layer; and a top gate electrode disposed on the active layer to drive a second region of the active layer. The TFT controls the conductivity of the active layer by using the bottom gate electrode and the top gate electrode. |
| US09660087B2 |
Semiconductor device, display device including the semiconductor device, display module including the display device, and electronic appliance including the semiconductor device, the display device, or the display module
A semiconductor device including a transistor is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, a second insulating film over the first insulating film, an oxide semiconductor film over the second insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a third insulating film over the source electrode, and a fourth insulating film over the drain electrode. A fifth insulating film including oxygen is provided over the transistor. The third insulating film includes a first portion, the fourth insulating film includes a second portion, and the fifth insulating film includes a third portion. The amount of oxygen molecules released from each of the first portion and the second portion is smaller than the amount of oxygen molecules released from the third portion when the amounts are measured by thermal desorption spectroscopy. |
| US09660083B2 |
LDMOS finFET device and method of manufacture using a trench confined epitaxial growth process
A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material. |
| US09660082B2 |
Integrated circuit transistor structure with high germanium concentration SiGe stressor
An integrated circuit transistor structure includes a semiconductor substrate, a first SiGe layer in at least one of a source area or a drain area on the semiconductor substrate, and a channel between the source area and the drain area. The first SiGe layer has a Ge concentration of 50 percent or more. |
| US09660076B2 |
Semiconductor memory device and method for manufacturing the same
A semiconductor memory device according to an embodiment includes a substrate, a plurality of conductive members containing a metal and provided on the substrate, a stacked body provided in each region between the conductive members, a semiconductor pillar piercing the stacked body, a memory film and internal stress films. The plurality of conductive members extend in a first direction and are separated from each other in a second direction. The internal stress films also extend in the first direction and are separated from each other in the second direction. The first direction and the second direction are parallel to an upper surface of the substrate and intersect each other. The internal stress films contain material having internal stress having the reverse polarity of internal stress of the metal. |
| US09660074B2 |
Methods and apparatus for LDMOS devices with cascaded RESURF implants and double buffers
LDMOS devices are disclosed. An LDMOS device includes at least one drift region disposed in a portion of a semiconductor substrate; at least one isolation structure at a surface of the semiconductor substrate; a D-well region positioned adjacent a portion of the at least one drift region, and an intersection of the drift region and the D-well region forming a junction between first and second conductivity types; a gate structure disposed over the semiconductor substrate; a source contact region disposed on the surface of the D-well region; a drain contact region disposed adjacent the isolation structure; and a double buffer region comprising a first buried layer lying beneath the D-well region and the drift region and doped to the second conductivity type and a second high voltage deep diffusion layer lying beneath the first buried layer and doped to the first conductivity type. Methods are disclosed. |
| US09660070B2 |
Power superjunction MOSFET device with resurf regions
A semiconductor device which solves the following problem of a super junction structure: due to a relatively high concentration in the body cell region (active region), in peripheral areas (peripheral regions or junction end regions), it is difficult to achieve a breakdown voltage equivalent to or higher than in the cell region through a conventional junction edge terminal structure or resurf structure. The semiconductor device includes a power MOSFET having a super junction structure formed in the cell region by a trench fill technique. Also, super junction structures having orientations parallel to the sides of the cell region are provided in a drift region around the cell region. |
| US09660067B2 |
III-N transistors with epitaxial layers providing steep subthreshold swing
III-N transistors with epitaxial semiconductor heterostructures having steep subthreshold slope are described. In embodiments, a III-N HFET employs a gate stack with balanced and opposing III-N polarization materials. Overall effective polarization of the opposing III-N polarization materials may be modulated by an external field, for example associated with an applied gate electrode voltage. In embodiments, polarization strength differences between the III-N materials within the gate stack are tuned by composition and/or film thickness to achieve a desired transistor threshold voltage (Vt). With polarization strengths within the gate stack balanced and opposing each other, both forward and reverse gate voltage sweeps may generate a steep sub-threshold swing in drain current as charge carriers are transferred to and from the III-N polarization layers and the III-N channel semiconductor. |
| US09660066B2 |
High electron mobility transistor
A high electron mobility transistor is provided, which includes a substrate, a superlattice structure formed on the substrate, and a transistor epitaxial structure formed on the superlattice structure such that the superlattice structure is interposed between the substrate and the transistor epitaxial layer. As the high electron mobility transistor has the carbon-doped AlN/GaN superlattice structure between the substrate and the transistor epitaxial layer. Thus, the present invention can effectively reduce vertical leakage current, so as to improve the epitaxial quality and the breakdown voltage of the high electron mobility transistor. |
| US09660059B2 |
Fin replacement in a field-effect transistor
In a method for fabricating a field-effect transistor (FET) structure, forming a fin on a semiconductor substrate. The method further includes forming a gate on a portion of the fin and the semiconductor substrate. The method further includes epitaxially growing a semiconductor material on the fin. The method further includes depositing oxide covering the fin and the epitaxially grown semiconductor material. The method further includes recessing the deposited oxide and the epitaxially grown semiconductor material to expose a top portion of the fin. The method further includes removing the fin. In another embodiment, the method further includes epitaxially growing another fin in a respective trench formed by removing the first set of fins. |
| US09660056B2 |
3D UTB transistor using 2D-material channels
A semiconductor device and a method of manufacture are provided. A substrate has a dielectric layer formed thereon. A three-dimensional feature, such as a trench or a fin, is formed in the dielectric layer. A two-dimensional layer, such as a layer (or multilayer) of graphene, transition metal dichalcogenides (TMDs), or boron nitride (BN), is formed over sidewalls of the feature. The two-dimensional layer may also extend along horizontal surfaces, such as along a bottom of the trench or along horizontal surfaces of the dielectric layer extending away from the three-dimensional feature. A gate dielectric layer is formed over the two-dimensional layer and a gate electrode is formed over the gate dielectric layer. Source/drain contacts are electrically coupled to the two-dimensional layer on opposing sides of the gate electrode. |
| US09660051B1 |
Method for producing semiconductor device
A method for producing a semiconductor device includes forming a first insulating film around a fin-shaped semiconductor layer and forming a pillar-shaped semiconductor layer and forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer. A metal-semiconductor compound is formed on the second diffusion layer. A first metal is deposited to form a gate electrode and a gate line. Second and third metal films are deposited to form a first contact in which the second metal film surrounds a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second contact connects an upper portion of the first contact and an upper portion of the pillar-shaped semiconductor layer. A third contact is formed on the gate line. |
| US09660050B1 |
Replacement low-k spacer
A semiconductor structure formed based on forming a dummy gate stack on a substrate including a sacrificial spacer on the peripheral of the dummy gate stack. The dummy gate stack is partially recessed. The sacrificial spacer is etched down to the partially recessed dummy gate stack. Remaining portions of the sacrificial spacer are etched leaving gaps around and above a remaining portion of the dummy gate stack. A first low-k spacer portion and a second low-k spacer portion are formed to fill gaps around the dummy gate stack and extend vertically along a sidewall of a dummy gate cavity. The first low-k spacer portion and the second low-k spacer portion are etched. A poly pull process is performed on the dummy gate stack. A replacement metal gate (RMG) structure is formed with the first low-k spacer portion and the second low-k spacer portion. |
| US09660047B2 |
Method for forming semiconductor components having self-aligned trench contacts
A method for producing a semiconductor component includes providing a semiconductor body having a first semiconductor material extending to a first surface and at least one trench, the at least one trench extending from the first surface into the semiconductor body, a first insulation layer being arranged in the at least one trench. The method further includes forming a second insulation layer on the first surface having a recess that overlaps in a projection onto the first surface with the at least one trench, forming a mask region in the recess, etching the second insulation layer selectively to the mask region, depositing a third insulation layer over the first surface, and etching the third insulation layer so that a semiconductor mesa of the semiconductor body arranged next to the at least one trench is exposed at the first surface. |
| US09660046B2 |
Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes: forming a first trench in a first area of a drift layer that has a surface including the first area and a second area; growing a crystal of a p-type base layer on a surface of the drift layer after forming the first trench; and growing a crystal of an n-type source layer on a surface of the base layer. Material of the drift layer, the base layer, and the source layer are a wide-gap semiconductor. |
| US09660044B2 |
Power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor
A power field effect transistor, a power field effect transistor device and a method of manufacturing a power field effect transistor are provided. During the manufacturing of the power field effect transistor, a body drive stage to manufacture the body region of the power field effect transistor is shortened to obtain a relatively low on resistance for the power field effect transistor. Before the implanting stage of the dopants of the body region, a pre body drive stage is introduced. During the pre body drive stage and the body drive stage sidewalls of a polysilicon layer of the power field effect transistor are oxidized to obtain a power field effect transistor which has at the sidewalls an oxidized polysilicon layer that is thick enough to prevent a premature current injection from the gate to the source regions of the power field effect transistor. |
| US09660043B2 |
Ohmic contact to semiconductor layer
A perforating ohmic contact to a semiconductor layer in a semiconductor structure is provided. The perforating ohmic contact can include a set of perforating elements, which can include a set of metal protrusions laterally penetrating the semiconductor layer(s). The perforating elements can be separated from one another by a characteristic length scale selected based on a sheet resistance of the semiconductor layer and a contact resistance per unit length of a metal of the perforating ohmic contact contacting the semiconductor layer. The structure can be annealed using a set of conditions configured to ensure formation of the set of metal protrusions. |
| US09660042B1 |
Semiconductor device and manufacturing method thereof
A semiconductor device and manufacturing method thereof are provided in the present invention. A second opening is formed corresponding to a gate structure after a step of forming a first opening corresponding to an epitaxial layer. After the step of forming the second opening, a pre-amorphization implantation process is performed to form an amorphous region in the epitaxial layer, and the influence of the process of forming the second opening on the amorphous region may be avoided. The semiconductor device formed by the manufacturing method of the present invention includes a contact structure and an alloy layer. The contact structure is disposed in the second opening for being electrically connected to a metal gate. The alloy layer is disposed on the metal gate and disposed between the metal gate and the contact structure. The alloy layer includes an alloy of the material of the metal gate. |
| US09660040B2 |
Transistor contacts self-aligned two dimensions
Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them. |
| US09660037B1 |
Semiconductor wafer and method
In an embodiment, a method includes forming an adhesion promotion layer on at least portions of a conductive surface arranged on a Group III nitride-based semiconductor layer, applying a resist layer to the adhesion promotion layer such that regions of the conductive surface are uncovered by the adhesion promotion layer and the resist layer, applying by electroplating a conductive layer to the regions of the conductive surface uncovered by the adhesion promotion layer and the resist layer, and removing the resist layer and removing the adhesion promotion layer. |
| US09660033B1 |
Multi-gate device and method of fabrication thereof
A method of semiconductor device fabrication includes providing a fin extending from a substrate and having a source/drain region and a channel region. The fin includes a first layer, a second layer over the first layer, and a third layer over the second layer. A gap is formed by removing at least a portion of the second layer from the channel region. A first material is formed in the channel region to form first and second interfacial layer portions, each at least partially wrapping around the first and third layers respectively. A second material is deposited in the channel region to form first and second high-k dielectric layer portions, each at least partially wrapping around the first and second interfacial layer portions. A metal layer including a scavenging material is formed along opposing sidewalls of the first and second high-k dielectric layer portions in the channel region. |
| US09660030B2 |
Replacement gate electrode with a self-aligned dielectric spacer
A dielectric disposable gate structure can be formed across a semiconductor material portion, and active semiconductor regions are formed within the semiconductor material portion. Raised active semiconductor regions are grown over the active semiconductor regions while the dielectric disposable gate structure limits the extent of the raised active semiconductor regions. A planarization dielectric layer is formed over the raised active semiconductor regions. In one embodiment, the dielectric disposable gate structure is removed, and a dielectric gate spacer can be formed by conversion of surface portions of the raised active semiconductor regions around a gate cavity. Alternately, an etch mask layer overlying peripheral portions of the disposable gate structure can be formed, and a gate cavity and a dielectric spacer can be formed by anisotropically etching an unmasked portion of the dielectric disposable gate structure. A replacement gate structure can be formed in the gate cavity. |
| US09660028B1 |
Stacked transistors with different channel widths
A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack. |
| US09660027B2 |
Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor
After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type. |
| US09660024B2 |
Semiconductor device with two transistors and a capacitor
A semiconductor device includes a first memory cell including a first transistor and a first capacitor, the first transistor comprising a first gate electrode, a first source, and a first drain; a second memory cell including a second transistor and the first capacitor, the second transistor comprising a second gate electrode, a second source, and a second drain; a first word line coupled to the first gate electrode; and a second word line coupled to the second gate electrode. The first capacitor is electrically connected between the first and second transistors. |
| US09660018B2 |
Semiconductor device fabricating method and semiconductor device
A method of fabricating a semiconductor device, including forming a lower electrode on a substrate; forming a first insulating film covering a periphery of the lower electrode and an upper surface end portion of the lower electrode; forming a second insulating film along an upper surface central portion outside the upper surface end portion of the lower electrode and a side surface and an upper surface of the first insulating film; and forming an upper electrode on the second insulating film. |
| US09660016B2 |
Method of manufacturing a capacitor
A method of forming a device comprises forming a through via extending from a surface of a substrate into the substrate. The method also comprises forming a first insulating layer over the surface of the substrate. The method further comprises forming a first metallization layer in the first insulating layer, the first metallization layer electrically connecting the through via. The method additionally comprises forming a capacitor over the first metallization layer. The capacitor comprises a first capacitor dielectric layer over the first metallization layer and a second capacitor dielectric layer over the first capacitor dielectric layer. The method also comprises forming a second metallization layer over and electrically connecting the capacitor. |
| US09660014B2 |
Semiconductor device
A semiconductor device includes: a semiconductor substrate; and a thin film resistor formed over an upper surface of the semiconductor substrate, the thin film resistor including first thin film resistor units and second thin film resistor units alternately connected in series, each of the first thin film resistor units having an elongated main portion and end portions that are connected to the elongated main portion, the end portions each forming a U-shape together with the elongated main portion in a plan view, and respectively overlapping with two of the second thin film resistor units that are adjacent to and connected to the first thin film resistor unit in series. |
| US09660012B2 |
Organic light emitting diode display
An organic light emitting diode display includes a substrate, a scan line on the substrate for transferring a scan signal, a data line crossing the scan line and for transferring a data signal, a driving voltage line crossing the scan line and for transferring a driving voltage, a switching thin film transistor coupled to the scan line and the data line, a driving thin film transistor coupled to a switching drain electrode of the switching thin film transistor, and an organic light emitting diode (OLED) coupled to a driving drain electrode of the driving thin film transistor, wherein a driving semiconductor layer of the driving thin film transistor is bent and in a plane substantially parallel to the substrate. |
| US09660011B2 |
Organic light emitting diode display device and manufacturing method thereof
Provided is an organic light emitting diode display device, including a pixel substrate including a pixel unit displaying an image and a peripheral unit surrounding the pixel unit; a first insulating layer covering the pixel substrate; a fanout line on the first insulating layer of the peripheral unit; a second insulating layer covering the first insulating layer and the fanout line; an etching prevention member on the second insulating layer of the peripheral unit and preventing overetching of the second insulating layer; a third insulating layer covering the second insulating layer; a peripheral potential voltage line on the third insulating layer of the peripheral unit and transferring a potential voltage; a passivation layer covering the third insulating layer; and an organic light emitting diode on the passivation layer of the pixel unit, in which the etching prevention member overlaps with the fanout line and the peripheral potential voltage line. |
| US09660010B2 |
Organic light emitting display device
An organic light emitting display device includes a substrate, a first insulating layer, a extension of a drain electrode, a second insulating layer, a first electrode, an emission layer, and a second electrode. The substrate has a display region and a transparent region. The first insulating layer is disposed on the substrate. The extension of drain electrode is disposed on the first insulating layer. The second insulating layer is disposed on the extension of a drain electrode such that an edge portion of the extension of a drain electrode is free from overlap with the second insulating layer. The first electrode is disposed on the second insulating layer and in contact with the edge portion of the extension of a drain electrode. The emission layer is disposed on the first electrode. The second electrode is disposed on the emission layer. |
| US09660008B2 |
High-yield fabrication of large-format substrates with distributed, independent control elements
A large-format substrate with distributed control elements is formed by providing a substrate and a wafer, the wafer having a plurality of separate, independent chiplets formed thereon; imaging the wafer and analyzing the wafer image to determine which of the chiplets are defective; removing the defective chiplet(s) from the wafer leaving remaining chiplets in place on the wafer; printing the remaining chiplet(s) onto the substrate forming empty chiplet location(s); and printing additional chiplet(s) from the same or a different wafer into the empty chiplet location(s). |
| US09660007B2 |
Display device and method of manufacturing display device
A display device according to the invention includes: a first substrate that includes a flexible substrate, is segmented into a display area and a non-display area outside the display area, and includes a thin film transistor and an electroluminescent light-emitting element formed on the display area of the flexible substrate; and an IC chip that is bonded on the non-display area of the first substrate via an anisotropic conductive film, wherein the first substrate includes, between the flexible substrate and the anisotropic conductive film, at least one or more support layers whose plan view shape is larger than that of the IC chip and whose hardness is higher than that of the flexible substrate, and the IC chip is located inside the at least one or more support layers in a plan view. |
| US09660004B2 |
Flexible displays with strengthened pad area
An electronic device may have a flexible display with portions that can be bent. The display may include an array of display pixels in an active area. Contact pads may be formed in an inactive area of the display. Display circuitry in the active area may exhibit a given stack height, whereas display circuitry in the inactive area may exhibit a stack height that is less than the given stack height. In particular, the contact pads may be formed directly on a multi-buffer layer that sits directly on a flexible display substrate. Passivation material may be selectively formed only at the edges of the contact pad on the multi-buffer layer. The multi-buffer layer may be formed at a distance from the edge of the flexible display substrate to minimize cracking in the multi-buffer layer. |
| US09660003B2 |
Display device
An organic electroluminescent device with a touch sensor including: a first substrate; a second substrate arranged opposite to the first substrate; an organic EL element layer arranged above the first substrate; a first sealing film arranged toward the second substrate of the organic EL element layer, covering the organic EL element layer, and including a first inorganic layer; plural first detection electrodes extending in one direction, and arranged in parallel toward the second substrate of the first sealing film; a second sealing film arranged toward the second substrate of the first detection electrodes, and including a second inorganic layer; plural second detection electrodes extending in another direction different from the one direction, and arranged in parallel toward the second substrate of the second sealing film; and a touch sensor control unit controlling a potential to detect a touch with a display surface. |
| US09660002B2 |
Display device
A display device includes a pixel area. The plurality of pixels, each includes pixel electrodes; banks; an EL layer; a counter electrode; and a sealing substrate. The plurality of pixels each include a plurality of sub pixels demarcated by the banks; the sealing substrate includes red, blue and green color filters; the plurality of sub pixels each include an effective light emission area and a light-blocked area; the effective light emission area of the blue color filter has an area size larger than that of each of the effective light emission area of the red and green color filter; and an effective light emission area of one sub pixel adjacent to the sub pixel including the blue color filter is located at a position closest, in the one sub pixel, to the light-blocked area of the sub pixel including the blue color filter. |
| US09659997B2 |
Replacement materials processes for forming cross point memory
Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material. |
| US09659995B2 |
Flexible display device
A flexible display device includes a display panel having pliability and a dielectric elastomer unit on the display panel. The dielectric elastomer unit is reversibly deformable by an applied voltage to provide stiffness to the display panel. |
| US09659989B1 |
Image sensor with semiconductor trench isolation
An image sensor pixel includes a photodiode disposed in a semiconductor material, and doped regions surrounding the photodiode, at least in part. The doped regions include a doped portion of the semiconductor material. Deep trench isolation structures are disposed in the doped regions, and surround the photodiode at least in part. The deep trench isolation structures include a SiGe layer disposed on side walls of the deep trench isolation structures, a high-k dielectric disposed on the SiGe layer, and a filler material. |
| US09659987B2 |
Approach for reducing pixel pitch using vertical transfer gates and implant isolation regions
An active pixel sensor (APS) with a vertical transfer gate and a pixel transistor (e.g., a transfer transistor, a source follower transistor, a reset transistor, or a row select transistor) electrically isolated by an implant isolation region is provided. A semiconductor substrate has a photodetector buried therein. The vertical transfer gate extends into the semiconductor substrate with a channel region in electrical communication with the photodetector. The pixel transistor is arranged over the photodetector and configured to facilitate the pixel operation (e.g., reset, signal readout, etc.). The implant isolation region is arranged in the semiconductor substrate and surrounds and electrically isolates the pixel transistor. A method for manufacturing the APS is also provided. |
| US09659986B2 |
Two-dimensional solid-state image capture device with polarization member and color filter for sub-pixel regions and polarization-light data processing method therefor
A two-dimensional solid-state image capture device includes pixel areas arranged in a two-dimensional matrix, each pixel area being constituted by multiple sub-pixel regions, each sub-pixel region having a photoelectric conversion element. A polarization member is disposed at a light incident side of at least one of the sub-pixel regions constituting each pixel area. The polarization member has strip-shaped conductive light-shielding material layers and slit areas, provided between the strip-shaped conductive light-shielding material layers. Each sub-pixel region further has a wiring layer for controlling an operation of the photoelectric conversion element, and the polarization member and the wiring layer are made of the same material and are disposed on the same virtual plane. |
| US09659985B2 |
Integrated circuit and image sensing device having metal shielding layer and related fabricating method
An integrated circuit includes a first semiconductor device, a second semiconductor device, and a metal shielding layer. The first semiconductor device includes a first substrate and a first multi-layer structure, and the first substrate supports the first multi-layer structure. The second semiconductor device includes a second substrate and a second multi-layer structure, and the second substrate supports the second multi-layer structure. The metal shielding layer is disposed between the first multi-layer structure and the second multi-layer structure, wherein the metal shielding layer is electrically connected to the second semiconductor device. |
| US09659980B2 |
Semiconductor photomultiplier
The present disclosure relates to a semiconductor photomultiplier comprising a substrate; an array of photosensitive cells formed on the substrate that are operably coupled between an anode and a cathode. A set of primary bus lines are provided each being associated with a corresponding set of photosensitive cells. A secondary bus line is coupled to the set of primary bus lines. An electrical conductor is provided having a plurality of connection sites coupled to respective connection locations on the secondary bus line for providing conduction paths which have lower impedance than the secondary bus line. |
| US09659978B2 |
Array substrate, method for manufacturing the same, and display device
An array substrate includes a GOA circuit area and a display area, the GOA circuit area includes a TFT area and a lead-wire area, the display area includes a data line and a gate line. The GOA circuit area is provided with at least one first via and at least one second via, a data-line metal layer is disposed at the bottom of the at least one first via, and a gate-line metal layer is disposed at the bottom of the at least one second via. The GOA circuit area further includes a first electrode and a second electrode, the data-line metal layer is electrically connected to one electrode through the at least one first via, the gate-line metal layer is electrically connected to the other electrode through the at least one second via, such that a capacitor is formed between the first electrode and the second electrode. |
| US09659972B2 |
Thin film transistor array panel comprising etch stopper for shaping a channel
A thin film transistor array panel includes: a substrate; gate lines on the substrate, each of the gate lines including a gate electrode; a semiconductor layer on the substrate; an etching stopper on the semiconductor layer; a data wiring layer on the substrate and including a data line, a source electrode connected to the data line, and a drain electrode; and a passivation layer covering the source electrode, the drain electrode, and the etching stopper, where the etching stopper includes an etching prevention portion between the source electrode and the drain electrode, a shortest distance A between an upper side and a lower side of an overlap area where the etching prevention portion and the semiconductor layer overlap one another is represented by a straight line in a plane view, and a width of a channel portion of the semiconductor layer is greater than the shortest distance A. |
| US09659970B2 |
Semiconductor device having auxiliary patterns
A semiconductor device includes a substrate, a first conductive layer on the substrate and including a main pattern, and substantially symmetrical auxiliary patterns extending from two sides of the main pattern, an insulating layer on the substrate and the first conductive layer, and a second conductive layer on the insulating layer and overlapping at least a portion of the main pattern and the auxiliary patterns. |
| US09659964B2 |
Method and structure for preventing epi merging in embedded dynamic random access memory
After forming a plurality of first semiconductor fins having a first spacing in a logic device region and a plurality of second semiconductor fins having a second spacing in a memory device region, sacrificial spacers are formed on sidewalls of the plurality of the first semiconductor fins and the plurality of the second semiconductor fins to completely fill spaces between the plurality of first semiconductor fins, but only partially fill spaces between second semiconductor fins. Next, dielectric barrier layer portions are formed in gaps between the sacrificial spacers. After removal of the sacrificial spacers, an entirety of the plurality of first semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layers, while each of the plurality of second semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layer portions. |
| US09659963B2 |
Contact formation to 3D monolithic stacked FinFETs
A first gate structure straddles one end of a staircase fin stack that contains a first semiconductor material fin, an insulator fin, and a second semiconductor material fin, a second gate structure straddles a portion of the staircase fin stack, a third gate structure straddles another end of the staircase fin stack, and a fourth gate structure straddles a portion of only the first semiconductor fin. A first contact structure is between the first and second gate structures, a second contact structure is between the second and third gate structures, and a third contact structure is between the third and fourth gate structures. The first contact structure has a contact metal that contacts the first and second semiconductor material fins. The second contact structure has a contact metal that contacts only the second semiconductor material fin, and the third contact structure has a contact metal that contacts only the first semiconductor fin. |
| US09659957B2 |
Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a first stacked body including a plurality of first electrode layers and a plurality of first insulating layers, the first electrode layers separately stacked each other, the first insulating layers provided between the first electrode layers; a second stacked body including a plurality of second electrode layers and a plurality of second insulating layers, the second electrode layers separately stacked each other, the second insulating layers provided between the second electrode layers, the second stacked body separated from the first stacked body in a first direction crossing a stacking direction of the first stacked body; and a first insulating portion provided between the first stacked body and the second stacked body, the first insulating portion provided integrally to the first insulating layers and the second insulating layers. |
| US09659955B1 |
Crystalinity-dependent aluminum oxide etching for self-aligned blocking dielectric in a memory structure
A method of forming a device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a memory opening extending through the alternating stack, and forming an aluminum oxide layer on sidewall surfaces of the sacrificial material layers and on sidewall surfaces of the insulating layers around the memory opening. First aluminum oxide portions of the aluminum oxide layer are located on sidewall surfaces of the sacrificial material layers, and second aluminum oxide portions of the aluminum oxide layer are located on sidewalls of the insulating layers. The method also includes removing the second aluminum oxide portions at a greater etch rate than the first aluminum oxide portions employing a selective etch process, such that all or a predominant portion of each first aluminum oxide portion remains after removal of the second aluminum oxide portions. |
| US09659952B2 |
NAND memory array with mismatched cell and bitline pitch
Embodiments of the present disclosure describe methods, apparatus, and system configurations for NAND memory arrays with mismatched cell and bitline pitch. Other embodiments may be described and claimed. |
| US09659951B1 |
Single poly nonvolatile memory cells, arrays thereof, and methods of operating the same
A single poly nonvolatile memory (NVM) cell includes first and second active regions disposed to face each other and third and fourth active regions spaced apart from the first and second active regions. A drain region, a junction region and a source region are disposed in the fourth active region. A floating gate is disposed on the first and second active regions and is disposed to extend onto the third and fourth active regions. A read/selection gate is disposed to cross the fourth active region between the drain region and the junction region. The first active region is coupled to a first array control gate line, and the second active region is coupled to a second array control gate line. The source region, the junction region and the floating gate constitute a floating gate transistor. The drain region, the junction region and the read/selection gate constitute a read/selection transistor. |
| US09659950B2 |
Semiconductor devices including stair step structures, and related methods
Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed. |
| US09659949B2 |
Integrated structures
Some embodiments include a method of forming vertically-stacked memory cells. An opening is formed through a stack of alternating insulative and conductive levels. Cavities are formed to extend into the conductive levels along sidewalls of the opening. At least one of the cavities is formed to be shallower than one or more others of the cavities. Charge-blocking dielectric and charge-storage structures are formed within the cavities. Some embodiments include an integrated structure having a stack of alternating insulative and conductive levels. Cavities extend into the conductive levels. At least one of the cavities is shallower than one or more others of the cavities by at least about 2 nanometers. Charge-blocking dielectric is within the cavities. Charge-storage structures are within the cavities. |
| US09659947B1 |
Low cost high performance EEPROM device
Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by isolation regions. First and second lower sub-gates of first and second transistors are formed in the cell area. A common upper sub-gate of the first and second transistors is formed. The common upper sub-gate and first and second lower sub-gates are separated by an intergate dielectric layer and the common upper sub-gate surrounds the first and second lower sub-gates. |
| US09659946B2 |
Self-aligned source for split-gate non-volatile memory cell
A memory device having a pair of conductive floating gates with inner sidewalls facing each other, and disposed over and insulated from a substrate of first conductivity type. A pair of spaced apart conductive control gates each disposed over and insulated from one of the floating gates, and each including inner sidewalls facing each other. A pair of first spacers of insulation material extending along control gate inner sidewalls and over the floating gates. The floating gate inner sidewalls are aligned with side surfaces of the first spacers. A pair of second spacers of insulation material each extend along one of the first spacers and along one of the floating gate inner sidewalls. A trench formed into the substrate having sidewalls aligned with side surfaces of the second spacers. Silicon carbon disposed in the trench. Material implanted into the silicon carbon forming a first region having a second conductivity type. |
| US09659944B2 |
One time programmable memory with a twin gate structure
A one-time programmable memory (OTP) is provided that includes a combined word line programming line (WL-PL). The OTP includes a programmable transistor having a first threshold voltage and a first breakdown voltage, and a pass transistor having a second threshold voltage and a second breakdown voltage. The combined WL-PL is electrically connected to respective gate electrodes of both the programmable transistor and the pass transistor so that both receive the same control voltage. The second gate electrode has a work function that is greater than that of the first gate electrode, so that the second gate breakdown voltage is greater than the first gate breakdown voltage, which enables the use of the combined WL-PL. |
| US09659942B1 |
Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET)
A method for forming a semiconductor device includes depositing spacer material on a first sidewall and a second sidewall of a fin formed on a substrate. The spacer material is removed from the first sidewall. A selective epitaxy process is performed on the first sidewall of the fin. |
| US09659938B2 |
Single source/drain epitaxy for co-integrating nFET semiconductor fins and pFET semiconductor fins
A plurality of gate structures are formed straddling nFET semiconductor fins and pFET semiconductor fins which extend upwards from a surface of a semiconductor substrate. A boron-doped silicon germanium alloy material is epitaxially grown from exposed surfaces of both the nFET semiconductor fins and the pFET semiconductor fins not protected by the gate structures. An anneal is then performed. During the anneal, silicon and germanium from the boron-doped silicon germanium alloy material diffuse into the nFET semiconductor fins and act as an n-type dopant forming a junction in the nFET semiconductor fins. Since boron is a Group IIIA element it does not have any adverse effect. During the same anneal, boron from the boron-doped silicon germanium alloy material will diffuse into the pFET semiconductor fins to form a junction therein. |
| US09659933B2 |
Body bias multiplexer for stress-free transmission of positive and negative supplies
An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate. |
| US09659928B2 |
Semiconductor device having a high-K gate dielectric above an STI region
By forming a trench isolation structure after providing a high-k dielectric layer stack, direct contact of oxygen-containing insulating material of a top surface of the trench isolation structure with the high-k dielectric material in shared polylines may be avoided. This technique is self-aligned, thereby enabling further device scaling without requiring very tight lithography tolerances. After forming the trench isolation structure, the desired electrical connection across the trench isolation structure may be re-established by providing a further conductive material. |
| US09659926B2 |
Semiconductor device
To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a semiconductor chip in the form of a rectangle that constitutes an LCD driver by devising a layout arrangement in a short-side direction. In a semiconductor chip that constitutes an LCD driver, input protection circuits are arranged in a lower layer of part of a plurality of input bump electrodes and on the other hand, in a lower layer of the other part of the input bump electrodes, the input protection circuits are not arranged but SRAMs (internal circuits) are arranged. |
| US09659924B2 |
Signal receiving circuit and signal transceiving circuit
A signal transceiving circuit comprising an IC including a signal transmitting part. The signal transmitting part comprises: a first I/O pad; a second I/O pad; a first output stage circuit, coupled to the first I/O pad; a second output stage circuit, coupled to the second I/O pad; and a first surge protecting device, comprising a first terminal coupled to the first output stage circuit and the first I/O pad, and comprising a second terminal coupled to the second output stage circuit and the second I/O pad. |
| US09659922B2 |
ESD protection device
An electrostatic discharge protection clamp includes a substrate and a first electrostatic discharge protection device over the substrate. The first electrostatic discharge protection device includes a buried layer over the substrate. The buried layer has a first region having a first doping concentration and a second region having a second doping concentration. The first doping concentration is greater than the second doping concentration. The first electrostatic discharge protection device includes a first transistor over the buried layer. The first transistor has an emitter coupled to a first cathode terminal of the electrostatic discharge protection clamp. The first electrostatic discharge protection device includes a second transistor over the buried layer. The second transistor has an emitter coupled to a first anode terminal of the electrostatic discharge protection clamp. A collector of the first transistor and a collector of the second transistor are over the first region of the buried layer. |
| US09659920B2 |
Performance-driven and gradient-aware dummy insertion for gradient-sensitive array
The present disclosure relates to an arrangement and a method of performance-aware buffer zone placement for a high-density array of unit cells. A first feature density of the array is measured and maximum variation for a parameter within a unit cell is determined. A look-up table of silicon data is consulted to predict a buffer zone width and gradient value that achieves a variation that is less than the maximum variation for the unit cell. The look-up table contains a suite of silicon test cases of various array and buffer zone geometries, wherein variation of the parameter within a respective test structure is measured and cataloged for the various buffer zone geometries, and is also extrapolated from the suite of silicon test cases. A buffer zone is placed at the border of the array with a width that is less than or equal to the buffer zone width. |
| US09659919B2 |
Nearly buffer zone free layout methodology
In some embodiments, an integrated circuit includes a central array region having a first layout feature density. A background region surrounds the central array region and has a second layout feature density, which is different from the first density. A peripheral array region surrounds the central array region and separates the central array region from the background region. The peripheral array region has a third layout feature density between the first and second layout feature densities. |
| US09659917B1 |
Apparatuses and methods for forming die stacks
Apparatuses and methods for forming die stacks are disclosed herein. An example method includes dispensing a temporary adhesive onto a substrate, placing a base die onto the temporary adhesive, curing the temporary adhesive, forming a die stack that includes the base die, activating a release layer disposed on the substrate, wherein the release layer is between the substrate and the temporary adhesive, removing the die stack from the substrate, and removing the temporary adhesive from the die stack. |
| US09659914B2 |
Light-emitting diode chip package
A light-emitting diode chip package is provided. The light-emitting diode chip package includes a substrate; a light-emitting diode chip set (LED chip set) disposed over the substrate, wherein the LED chip set is formed by a plurality of light-emitting diode chips (LED chips) in one piece; and at least two electrodes disposed over the substrate and electrically connected to the LED chip set. |
| US09659909B2 |
Semiconductor packages including flexible wing interconnection substrate
A semiconductor package includes a first semiconductor package, a second semiconductor package disposed on the first semiconductor package, and a flexible wing interconnection substrate disposed between the first and second semiconductor packages. |
| US09659906B2 |
Semiconductor device
A semiconductor device with improved heat radiation characteristics. It includes: a wiring board having a chip mounting surface and a plurality of electrode pads formed over the chip mounting surface; a semiconductor chip located over the chip mounting surface of the wiring board, having a plurality of bonding pads; a plurality of wires for coupling the electrode pads and the bonding pads; a heat slug located over the semiconductor chip; and a sealing member covering the chip mounting surface of the wiring board, the semiconductor chip, the wires, and the heat slug. A spacer lies between the chip mounting surface of the wiring board and the semiconductor chip and the sealing member lies between the semiconductor chip and the heat slug. |
| US09659904B2 |
Distributed on-package millimeter-wave radio
Embodiments described herein generally relate to phased array antenna systems or packages and techniques of making and using the systems and packages. A phased array antenna package may include a distributed phased array antenna comprising (1) a plurality of antenna sub-arrays, which may each include a plurality of antennas, (2) a plurality of Radio Frequency Dies (RFDs), each of the RFDs located proximate and electrically coupled by a trace of a plurality of traces to a corresponding antenna sub-array of the plurality of antenna sub-arrays, and (3) wherein each trace of the plurality of traces configured to electrically couple an antenna of the plurality of antennas to the RFD located proximate the antenna, wherein each trace of the plurality of traces is configured to transmit millimeter wave (mm-wave) radio signals, and wherein the plurality of traces are each of a substantially uniform length. |
| US09659903B2 |
Method of manufacturing connector structures of integrated circuits
A die includes a substrate, a metal pad over the substrate, and a passivation layer covering edge portions of the metal pad. A metal pillar is formed over the metal pad. A portion of the metal pillar overlaps a portion of the metal pad. A center of the metal pillar is misaligned with a center of the metal pad. |
| US09659901B2 |
Semiconductor device including sense insulated-gate bipolar transistor
A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell. |
| US09659899B2 |
Die warpage control for thin die assembly
Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate. |
| US09659897B1 |
Integrated circuit packaging system with interposer structure and method of manufacture thereof
A system and a method of manufacture thereof of integrated circuit packaging system, including: a pillar; a conductive buildup attached to the pillar; and a molded body encapsulating the conductive buildup, the pillar extending out of the molded body. |
| US09659895B2 |
Semi-conductor package structure
Disclosed is a semiconductor package structure comprising a body, a plurality of first-layer, second-layer, third-layer and fourth-layer electrical contacts, wherein the first-layer, the second-layer, the third-layer and the fourth-layer electrical contacts are arranged sequentially from outside to inside on a bottom surface of the body in a matrix manner. Adjacent first-layer electrical contacts have two different spacings therein, and adjacent third-layer electrical contacts have the two different spacings therein. |
| US09659890B2 |
Methods and apparatus of packaging semiconductor devices
Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface. |
| US09659889B2 |
Solder-on-die using water-soluble resist system and method
This disclosure relates generally to generating a solder-on-die using a water-soluble resist, system, and method. Heat may be applied to solder as applied to a hole formed in a water-soluble resist coating, the water-soluble resist coating being on a surface of an initial assembly. The initial assembly may include an electronic component. The surface may be formed, at least in part, by an electrical terminal of the electronic component, the hole being aligned, at least in part, with the electrical terminal. The solder may be reflowed, wherein the solder couples, at least in part, with the electrical terminal. |
| US09659888B2 |
Semiconductor device
Even when a thermal stress is applied to an electrode pad, the electrode pad is prevented from being moved. A substrate of a semiconductor chip has a rectangular planar shape. The semiconductor chip has a plurality of electrode pads. The center of a first electrode pad is positioned closer to the end of a first side in the direction along the first side of the substrate as compared to the center of a first opening. Thus, in a part of the first electrode pad covered with an insulating film, a width of the part closer to the end of the first side in the direction along the first side is larger than another width of the part opposite to the above-mentioned width. |
| US09659886B2 |
Method of fabricating semiconductor device having voids between top metal layers of metal interconnects
The invention provides a semiconductor device including a substrate, a dielectric layer, a dummy bonding pad, a bonding pad, a redistribution layer, and a metal interconnect. The substrate includes a non-device region and a device region. The dielectric layer is on the non-device region and the device region. The dummy bonding pad is on the dielectric layer of the non-device region. The metal interconnect is in the dielectric layer of the non-device region and connected to the dummy bonding pad. The bonding pad is on the dielectric layer of the device region. The buffer layer is between the bonding pad and the dielectric layer. The buffer layer includes metal, metal nitride, or a combination thereof. The redistribution layer is on the dielectric layer and connects the dummy bonding pad and the bonding pad. |
| US09659884B2 |
Carrier substrate
A carrier substrate includes an insulation encapsulation, first conductive patterns, second conductive patterns, at least one first dummy pattern, and at least one second dummy pattern. The carrier substrate has a first layout region and a second layout region. The first conductive patterns and the first dummy pattern are located in the first layout region. The second conductive patterns and the second dummy pattern are located in the second layout region. The first and second conductive patterns and the first and second dummy patterns are embedded in the insulation encapsulation. The insulation encapsulation exposes top surfaces of the first and second conductive patterns and the first and second dummy patterns. The first dummy pattern and the second dummy pattern are insulated from the first conductive patterns and the second conductive patterns. An edge profile of the first dummy pattern facing the second dummy pattern is non-linear. |
| US09659875B2 |
Chip part and method of making the same
A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate. |
| US09659873B2 |
Semiconductor structure with aligning mark and method of forming the same
The present invention provides a semiconductor structure comprising a wafer and an aligning mark. The wafer has a dicing region which comprises a central region, a middle region surrounds the central region, and a peripheral region surrounds the middle region. The aligning mark is disposed in the dicing region, wherein the alignment mark is a mirror symmetrical pattern. The aligning mark comprises a plurality of second patterns in the middle region and a plurality of third patterns disposed in peripheral region, wherein each third pattern comprises a plurality of lines, and a width of the line is 10 times less than a width of the L-shapes. The present invention further provides a method of forming the same. |
| US09659870B2 |
Wiring and method for manufacturing the same
Wiring comprises a multilayer graphene including graphene sheets, an interlayer substance disposed between layers of the multilayer graphene, and an organic compound layer connected to a side surface of the multilayer graphene. The organic compound layer contains a photoisomerizable organic group connected to the multilayer graphene. |
| US09659869B2 |
Forming barrier walls, capping, or alloys /compounds within metal lines
Described herein are techniques structures related to forming barrier walls, capping, or alloys/compounds such as treating copper so that an alloy or compound is formed, to reduce electromigration (EM) and strengthen metal reliability which degrades as the length of the lines increases in integrated circuits. |
| US09659866B1 |
Three-dimensional memory structures with low source line resistance
Dielectric pedestal structures embedded in a sacrificial material layer is formed between a substrate and an alternating stack of insulating layers and spacer material layers. After memory openings are formed through the alternating layer, a cavity is formed by removal of the sacrificial material layer selective to the dielectric pedestal structures. A memory film, a semiconductor channel layer, and a dielectric core are sequentially formed in the volume including the cavity and the memory openings. A backside trench is formed through the alternating stack in an area that straddles the dielectric pedestal structures. By recessing the dielectric pedestal structures selective to the semiconductor channel layer, planar regions and vertical regions of the semiconductor channel layer can be physically exposed, which are converted into source regions. Contact resistance can be lowered due the increased contact area provided by vertical source portions. |
| US09659859B2 |
Metal pad offset for multi-layer metal layout
A semiconductor device includes a first layer including a number of first layer metal pads, a second layer formed on top of the first layer, the second layer including a number of second layer metal pads, and vias connecting the first layer metal pads to the second layer metal pads. A surface area overlap between the first layer metal pads and the second layer metal pads is below a defined threshold. |
| US09659856B2 |
Two step metallization formation
An integrated circuit structure includes a first conductive line, a dielectric layer over the first conductive line, a diffusion barrier layer in the dielectric layer, and a second conductive line in the dielectric layer. The second conductive line includes a first portion of the diffusion barrier layer. A via is underlying the second conductive line and electrically couples the second conductive line to the first conductive line. The via includes a second portion of the diffusion barrier layer, with the second portion of the diffusion barrier layer having a bottom end higher than a bottom surface of the via. |
| US09659854B2 |
Embedded packaging for devices and systems comprising lateral GaN power transistors
Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications. |
| US09659853B2 |
Double side via last method for double embedded patterned substrate
An interposer substrate includes a first circuit pattern embedded at a first surface of a dielectric layer and a second circuit pattern embedded at a second surface of the dielectric layer; a middle patterned conductive layer in the dielectric layer between the first circuit pattern and the second circuit pattern; first conductive vias, where each first conductive via includes a first end adjacent to the first circuit pattern and a second end adjacent to the middle patterned conductive layer, wherein a width of the first end is greater than a width of the second end; second conductive vias, where each second conductive via including a third end adjacent to the second circuit pattern and a fourth end adjacent to the middle patterned conductive layer, wherein a width of the third end is greater than a width of the fourth end. |
| US09659852B2 |
Semiconductor package
A semiconductor package may include a package substrate with a top surface and a bottom surface opposite to the top surface, the top surface of the package substrate configured to have a semiconductor chip mounted thereon, a power block and a ground block in the package substrate, the power block configured as a power pathway penetrating the package substrate, and the ground block configured as a ground pathway penetrating the package substrate, first vias extended from the power block and the ground block, and the first vias electrically connected to the semiconductor chip, second vias extended from the power block and the ground block toward the bottom surface of the package substrate, and block vias to penetrate the power block and the ground block, the block vias electrically connected to the semiconductor chip and electrically separated from the power block and the ground block. |
| US09659851B2 |
Method and apparatus for improving the reliability of a connection to a via in a substrate
Some of the embodiments of the present disclosure provide a semiconductor package interposer comprising a substrate having a first surface and a second surface, a plurality of vias extending between the first surface and the second surface of the substrate, the plurality of vias electrically connecting electrical connectors or circuitry on the first surface of the substrate to electrical connectors or circuitry on the second surface of the substrate, and metal plugs at least partially filling the plurality of vias. At least one of (i) the first surface or (ii) the second surface of the substrate includes depressions at distal ends of the metal plugs. |
| US09659850B2 |
Package substrate comprising capacitor, redistribution layer and discrete coaxial connection
A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects. |
| US09659849B2 |
Method for manufacturing multilayer wiring board
A multilayer wiring board has a high degree of freedom of wiring design and can realize high-density wiring, and a method to simply manufacture the multilayer wiring board. A core substrate with two or more wiring layers provided thereon through an electrical insulating layer. The core substrate has a plurality of throughholes filled with an electroconductive material, and the front side and back side of the core substrate have been electrically conducted to each other by the electroconductive material. The throughholes have an opening diameter in the range of 10 to 100 μm. An insulation layer and an electroconductive material diffusion barrier layer are also provided, and the electroconductive material is filled into the throughholes through the insulation layer. A first wiring layer provided through an electrical insulating layer on the core substrate is connected to the electroconductive material filled into the throughhole through via. |
| US09659847B2 |
Terminal structure for active power device
A semiconductor die comprising a terminal structure for an active power device. The terminal structure comprises a metallic layer arranged to be electrically coupled between the active power device and an external contact of an integrated circuit package, a conductive sub-structure extending in parallel with the metallic layer, and located such that, when mounted within an integrated circuit device, the conductive sub-structure lies between the metallic layer and a reference voltage plane, and interconnecting elements extending between the metallic layer and the conductive sub-structure and electrically coupling the metallic layer to the conductive sub-structure. The plurality of interconnecting elements comprise first and second interconnecting elements extending between first and second lateral end regions of the metallic layer and the conductive sub-structure respectively such that the first and second interconnecting elements are laterally spaced with respect to the direction of travel of the fundamental signal for the active power device. |
| US09659846B2 |
Process for manufacturing a 3D electronic module comprising external interconnection leads
A process for manufacturing at least one 3D electronic module each comprises a stack of electronic packages and/or printed wiring boards, wherein a stack is placed on an electrically interconnecting system comprising metal leads each having two ends. The process comprises the following steps: starting with a lead frame that comprises metal leads, folding by about 180° the leads in order to obtain what is referred to as an internal frame portion including the folded ends, which are intended to be molded, the other portion, which is what is referred to as an external portion, including the unfolded exterior ends, the two ends of each lead being intended to emerge from the 3D module on a given face cut along Z; depositing on the leads a metal coating; placing the external portion of the frame between two, an upper and lower, protective elements while leaving the internal portion free, and placing the frame and the protective elements on a carrier; placing each stack equipped each with exterior interconnection tabs so as to superpose the exterior tabs on the internal portion; molding, in a resin, the stack, the exterior tabs and the internal portion and thereby partially covering the upper protective element; cutting the resin and thereby leaving flush conductive sections of the exterior tabs and of the ends of the leads and removing the resin from the upper protective element; metallizing the cut faces; removing the carrier; and removing the protective elements in order to expose the leads of the external portion. |
| US09659842B2 |
Methods of fabricating QFN semiconductor package and metal plate
A method for fabricating a quad flat non-leaded (QFN) package includes: forming die pads and bump solder pads by pressing a metal plate, wherein each of the die pads and the bump solder pads has at least a cross-sectional area greater than another cross-sectional area located underneath along its vertical thickness dimension, thereby enabling the die pads and the solder pads to be securely embedded in an encapsulant. |
| US09659830B2 |
Dimension detection device and cassette
A dimension detection device includes a first detection unit which is moved to a first predetermined position in a first direction, and configured to detect a current position of the first member, and when the current position of the first member is not a third predetermined position corresponding to the first predetermined position, send a first signal; a second detection unit which is moved to a second predetermined position in the first direction, and configured to detect a current position of the second member, and when the current position of the second member is not a fourth predetermined position corresponding to the second predetermined position, send a second signal; a movement unit which is configured to move the first detection unit and the second detection unit; and an alarm unit configured to send an alarm upon the receipt of the first signal and/or the second signal. |
| US09659827B2 |
Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation
Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth. |
| US09659826B2 |
Asymmetric source/drain depths
A method for fabricating a semiconductor device includes forming a relaxed semiconductor layer on a substrate, the substrate comprising an n-type region and a p-type region. The method further includes forming a tensile strained semiconductor layer on the relaxed semiconductor layer, etching a portion of the tensile strained semiconductor layer in the p-type region, forming a compressive strained semiconductor layer on the tensile strained semiconductor layer in the p-type region, forming a first gate in the n-type region and a second gate in the p-type region, and forming a first set of source/drain features adjacent to the first gate and a second set of source/drain features adjacent to the second gate. The second set of source/drain features are deeper than the first set of source/drain features. |
| US09659823B2 |
Highly scaled tunnel FET with tight pitch and method to fabricate same
A structure includes a substrate and a tunnel field effect transistor (TFET). The TFET includes a source region disposed in the substrate having an overlying source contact, the source region containing first semiconductor material having a first doping type; a drain region disposed in the substrate having an overlying drain contact, the drain region containing second semiconductor material having a second, opposite doping type; and a gate structure that overlies a channel region between the source and the drain. The source region and the drain region are asymmetric with respect to one another such that one contains a larger volume of semiconductor material than the other one. A method is disclosed to fabricate a plurality of the TFETs using a plurality of spaced apart mandrels having spacers. A pair of the mandrels and the associated spacers is processed to form four adjacent TFETs without requiring intervening lithographic processes. |
| US09659818B1 |
Forming self-aligned dual patterning mandrel and non-mandrel interconnects
A method for forming conductive lines on a substrate includes depositing a layer of mandrel material on a substrate and removing portions of the layer of mandrel material to form a first mandrel having a first length, a portion of the first mandrel has sloped sidewalls, a second mandrel having a second length, the second mandrel having an outwardly facing sloped sidewall, and a third mandrel having the second length, the third mandrel having an outwardly facing sloped sidewall, the first length is greater than the second length, the first mandrel is arranged between the second mandrel and the third mandrel. A spacer is formed along non-sloped sidewalls of the first mandrel, the second mandrel, and the third mandrel. The first mandrel, the second mandrel, and the third, mandrel, and exposed portions of the substrate are removed to form cavities. The cavities are filled with a conductive material. |
| US09659817B1 |
Structure and process for W contacts
Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and processes generally includes forming a nitrogen-enriched surface in a deposited metal liner layer or forming a nitrogen-enriched surface in the dielectric material prior to deposition of the metal liner layer. In this manner, nitridization of the metal occurs upon deposition of nitrogen ions into the metal liner layer and/or as a function of additional conventional processing in fabricating the integrated circuit such that the deposited nitrogen ions diffuse into at least a portion of the metal liner layer. As a consequence, only a single metal layer deposition step is needed to form the metal liner layer. |
| US09659815B2 |
System, method, and computer program product for a cavity package-on-package structure
A system, method, and computer program product are provided for producing a cavity bottom package of a package-on-package structure. The method includes the steps of receiving a bottom package comprising a substrate material having a top layer including a first set of pads configured to be electrically coupled to a second set of pads of an integrated circuit die. A layer of non-conductive material is applied to the top layer of the bottom package and a cavity is formed in the layer of non-conductive material to expose the first set of pads, where the cavity is configured to contain the integrated circuit die oriented such that the second set of pads face the first set of pads. |
| US09659813B1 |
Interconnection and manufacturing method thereof
An interconnection includes first and second conductive layers, first and second dielectric layers, a stop layer, and first and second adhesion layers is provided. The first conductive layer is disposed over a semiconductor substrate. The first dielectric layer is over the first conductive layer, and the first dielectric layer includes a via hole. The second dielectric layer is disposed over the first dielectric layer. The stop layer is located between the first dielectric layer and the second dielectric layer, and the second dielectric layer and the stop layer include a trench. The second conductive layer is located in the via hole and the trench to electrically connect with the first conductive layer. The first adhesion layer is located on sidewalls of the trench. The second adhesion layer is located between the second conductive layer and the first adhesion layer and between the second conductive layer and the first dielectric layer. |
| US09659809B2 |
Support cylinder for thermal processing chamber
Embodiments of the disclosure generally relate to a support cylinder used in a thermal process chamber. In one embodiment, the support cylinder includes a hollow cylindrical body comprising an inner peripheral surface, an outer peripheral surface parallel to the inner peripheral surface, wherein the inner peripheral surface and the outer peripheral surface extend along a direction parallel to a longitudinal axis of the support cylinder, and a lateral portion extending radially from the outer peripheral surface to the inner peripheral surface, wherein the lateral portion comprises a first end having a first beveled portion, a first rounded portion, and a first planar portion connecting the first beveled portion and the first rounded portion, and a second end opposing the first end, the second end having a second beveled portion, a second rounded portion, and a second planar portion connecting the second beveled portion and the second rounded portion. |
| US09659807B2 |
Method of forming a flexible semiconductor layer and devices on a flexible carrier
A method for fabricating a semiconductor device comprises providing a preformed spalled structure comprising a stressor layer stack on a first surface of a semiconductor substrate; forming an interfacial release layer on an exposed second surface of the semiconductor substrate; adhesively bonding the interfacial release layer to a rigid handle substrate using an epoxy; removing at least a portion of the stressor layer stack from the first surface of the semiconductor substrate; processing the semiconductor substrate; and removing the semiconductor substrate from the interfacial release layer to impart flexibility to the semiconductor substrate. |
| US09659804B2 |
Orientating and installing jig
An orientating and installing jig for orientating a heat-dissipating unit (or a workpiece) to fix on a heat-generating device (or a target device) above a circuit board (or a supporting baseplate), which includes a carrying board formed with at least one assembling opening, a plurality of fixing posts and a pair of arrest-orientating modules oppositely arranged at two sides of the assembling opening. The assembling opening is shaped correspondingly to the shape of the heat-dissipating unit. The fixing posts are disposed at a bottom surface of the carrying board for fixing the carrying board above the circuit board. Each arrest-orientating module includes an arresting barrier. The arresting barrier is rotatably disposed at a suspending position of suspending the workpiece on the carrying board, and a releasing position of allowing the workpiece to pass through the assembling opening, so that the workpiece is put on the target device. |
| US09659802B2 |
Method for overhead cross-system transportation
A method comprises transferring a wafer carrier to or from an overhead hoist transfer (OHT) system using a conveyor. The method also comprises transferring the wafer carrier between the conveyor and an overhead shuttle (OHS) system using a cross-system transport apparatus. The method further comprises generating control signals using a controller to control at least one of the cross-system transport apparatus, the conveyor, or the loading or unloading of the wafer carrier at the OHT or the OHS. The cross-system transport apparatus comprises a lifting device configured to raise or lower the wafer carrier. The transferring of the wafer carrier between the conveyor and the OHS system comprises one or more of lifting or lowering the wafer carrier. |
| US09659798B2 |
System and method for producing devices including a semiconductor part and a non-semiconductor part
A system produces devices that include a semiconductor part and a non-semiconductor part. A front end is configured to receive a semiconductor part and to process the semiconductor part. A back end is configured to receive the processed semiconductor part and to assemble the processed semiconductor part and a non-semiconductor part into a device. A transfer device is configured to automatically handle the semiconductor part in the front end and to automatically transfer the processed semiconductor part to the back end. |
| US09659797B1 |
Wafer scale oblique angle plasma etching
Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer. |
| US09659794B2 |
Particle improvement for single wafer apparatus
An apparatus includes a susceptor, a first piping, a second piping, a liquid source, a third piping and a gas source. The susceptor is suitable for placing a wafer, and the first piping is configured to dispense a chemical to the wafer on the susceptor. The second piping communicates with the first piping. The liquid source is configured to deliver a cleaning liquid to the first piping through the second piping to wash a portion of the first piping. The third piping communicates with the first piping. The gas source is configured to flow a purge gas to the first piping through the third piping to purge the portion of the first piping. |
| US09659793B2 |
Method for producing a material-bonding connection between a semiconductor chip and a metal layer
A method for producing a material-bonding connection between a semiconductor chip and a metal layer is disclosed. For this purpose, a semiconductor chip, a metal layer, which has a chip mounting portion, and also a bonding medium containing a metal powder are provided. The metal powder is sintered in a sintering process. In this case, throughout a prescribed sintering time, the prescribed requirements are met, that the bonding medium is arranged between the semiconductor chip and the metal layer and extends right through from the semiconductor chip to the metal layer, that the semiconductor chip and the metal layer are pressed against one another in a pressing-pressure range that lies above a minimum pressing pressure, that the bonding medium is kept in a temperature range that lies above a minimum temperature and that a sound signal is introduced into the bonding medium. |
| US09659791B2 |
Metal removal with reduced surface roughness
Methods are described for etching metal layers that are difficult to volatize, such as cobalt, nickel, and platinum to form an etched metal layer with reduced surface roughness. The methods include pretreating the metal layer with a local plasma formed from a hydrogen-containing precursor. The pretreated metal layer is then reacted with a halogen-containing precursor to form a halogenated metal layer having a halogenated etch product. A carbon-and-nitrogen-containing precursor reacts with the halogenated etch product to form a volatile etch product that can be removed in the gas phase from the etched surface of the metal layer. The surface roughness may be reduced by performing one or more plasma treatments on the etching metal layer after a plurality of etching sequences. Surface roughness is also reduced by controlling the temperature and length of time the metal layer is reacting with the etchant precursors. |
| US09659789B2 |
Etching method and etching apparatus
An etching method is provided. In the etching method, a temperature of a chiller configured to cool a pedestal is controlled so as to become −20 degrees C. or lower. Plasma is generated from a hydrogen-containing gas and a fluoride-containing gas supplied from a gas supply source by supplying first high frequency power having a first frequency supplied to the pedestal from a first high frequency power source. A silicon oxide film deposited on a substrate placed on the pedestal is etched by the generated plasma. Second high frequency power having a second frequency lower than the first frequency of the first high frequency power is supplied to the pedestal from a second high frequency power source in a static eliminating process after the step of etching the silicon oxide film. |
| US09659784B1 |
Ion-assisted deposition and implantation of photoresist to improve line edge roughness
Provided herein are approaches for patterning a semiconductor device. Exemplary approaches include providing a set of photoresist patterning features atop a substrate, the set of patterning features having a surface roughness characterized by a set of protrusions and a set of indentations. The approaches further include implanting first ions into a sidewall surface of the set of photoresist patterning features to form a film layer having a non-uniform thickness along the sidewall surface, wherein a thickness of the film layer formed over the indentations is greater than a thickness of the film layer formed over the protrusions. The approaches further include sputtering the sidewall surface of the photoresist patterning features following the formation of the film layer to modify a portion of the film layer and/or the set of protrusions, wherein the sputtering includes directing second ions to photoresist patterning features at an angle with the sidewall surface. |
| US09659782B2 |
Memory device and method for fabricating the same
A method for fabricating memory device is disclosed. The method includes the steps of: providing a substrate having a tunnel oxide layer on the substrate, a first electrode layer on the tunnel oxide layer, an oxide-nitride-oxide (ONO) stack on the first electrode layer, and a second electrode layer on the ONO stack, and then removing part of the second electrode layer, part of the ONO stack, and part of the first electrode layer so that the tunnel oxide layer is not exposed. |
| US09659781B2 |
Method for forming a floating gate in a recess of a shallow trench isolation (STI) region
A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate. |
| US09659780B2 |
Multiple gate field-effect transistors having oxygen-scavenged gate stack
A method includes forming a silicon cap layer on a semiconductor fin, forming an interfacial layer over the silicon cap layer, forming a high-k gate dielectric over the interfacial layer, and forming a scavenging metal layer over the high-k gate dielectric. An anneal is then performed on the silicon cap layer, the interfacial layer, the high-k gate dielectric, and the scavenging metal layer. A filling metal is deposited over the high-k gate dielectric. |
| US09659776B2 |
Doping for FinFET
First and second fins are formed extending from a substrate. A first layer is formed over the first fin. The first layer comprises a first dopant. A portion of the first layer is removed from a tip portion of the first fin. A second layer is formed over the second fin. The second layer comprises a second dopant. One of the first and second dopants is a p-type dopant, and the other of the first and second dopants is an n-type dopant. A portion of the second layer is removed from a tip portion of the second fin. A solid phase diffusion process is performed to diffuse the first dopant into a non-tip portion of the first fin, and to diffuse the second dopant into a non-tip portion of the second fin. |
| US09659774B2 |
Impurity introducing method, impurity introducing apparatus, and method of manufacturing semiconductor element
A method for introducing impurity into a semiconductor substrate includes bringing a solution containing a compound of an impurity element into contact with a primary surface of a semiconductor substrate; and irradiating the primary surface of the semiconductor substrate with a laser beam through the solution to raise a temperature of the primary surface of the semiconductor substrate at a position irradiated by the laser beam so as to dope the impurity element into the semiconductor substrate. The laser beam irradiation is performed such that the raised temperature does not return to room temperature until a prescribed dose of the impurity element is caused to be doped into the semiconductor substrate. |
| US09659772B2 |
Semiconductor devices and methods of manufacturing the same
Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that includes a first main line having a first width and a first subline having a second width, and a second line pattern that includes a second main line having the first width and a second subline having a third width. The first line pattern may include a first width changer whose width increases from the first width to the second width. The second line pattern may include a second width changer whose width increases from the first width to the third width. |
| US09659771B2 |
Conformal strippable carbon film for line-edge-roughness reduction for advanced patterning
Embodiments of the disclosure relate to deposition of a conformal organic material over a feature formed in a photoresist or a hardmask, to decrease the critical dimensions and line edge roughness. In various embodiments, an ultra-conformal carbon-based material is deposited over features formed in a high-resolution photoresist. The conformal organic layer formed over the photoresist thus reduces both the critical dimensions and the line edge roughness of the features. |
| US09659763B2 |
Epoxy-based composition, adhesive film, dicing die-bonding film and semiconductor device
Provided are an epoxy composition, an adhesive film, a dicing die bonding film and a semiconductor device using the same. Specifically, the epoxy composition and a use thereof are provided, wherein the epoxy composition has a gel content of 5˜20%, measured under certain conditions. The epoxy composition according to the present invention, as an adhesive agent, shows excellent elastic properties, when prepared to have a low glass transition temperature, exhibiting good adhesion at high temperature and having minimal occurrence of burrs during processing. According to the present invention, it is therefore possible to prevent defects owing to die cut shift, during a wire bonding or molding process at high temperature, and obtain a highly reliable semiconductor device owing to the excellent adhesiveness and workability of the adhesive agent. |
| US09659761B2 |
Dynamically harmonized FT-ICR cell with specially shaped electrodes for compensation of inhomogeneity of the magnetic field
A method and apparatus of compensating a magnetic field inhomogeneity in a dynamically harmonized FT-ICR cell is presented, based on adding of extra electrodes into the cell, the extra electrodes being shaped in such a way that the averaged electric field created by these electrodes produces a counter force to the forces caused by the inhomogeneous magnetic field on the cycling ions. |
| US09659760B2 |
Automated adjustment of capillary voltage based on the elution conditions to retain optimal ionization conditions
A method of Electrospray ionization is disclosed comprising passing a sample liquid through a liquid chromatography column, monitoring a liquid chromatography back pressure and varying a voltage applied to an Electrospray ionization source electrode in dependence upon said monitored liquid chromatography back pressure. |
| US09659747B2 |
Method of generating write data for energy beam writing apparatus, method of writing with energy beam, and energy beam writing apparatus
In one embodiment, a method is for generating write data for resizing a write pattern to be written with an energy beam. The method includes connecting vertices of the write pattern with a plurality of vectors, extracting a pair of collinear vectors pointing in opposite directions from the vectors, dividing the write pattern into a plurality of figures with a line passing between two adjacent ends of the extracted pair of vectors and extending in a direction orthogonal to the pair of vectors, and generating write data for each of the figures, the write data containing figure data and resizing information, the figure data indicating a shape, a size, and a position of the figure, the resizing information indicating resizing or non-resizing, resizing directions in the resizing, and an amount of resizing in each of the resizing directions. |
| US09659746B2 |
Adjustment method for charged particle beam drawing apparatus and charged particle beam drawing method
According to one embodiment, a method of adjusting a charged particle beam drawing apparatus includes obtaining an offset amount in beam size to be set in the charged particle beam drawing apparatus. The method includes forming a linear evaluation pattern on a substrate by changing number of divisions of a beam with a predetermined size and performing drawing by using divided beams, obtaining a change amount in a line width of the evaluation pattern from a design dimension for each number of divisions, and calculating the offset amount by fitting a model function to the change amount for each number of divisions, the model function being obtained by modeling a pattern line width based on a distribution of energy given by charged particle beams. |
| US09659741B2 |
X-ray tube having planar emitter with tunable emission characteristics
An electron emitter can include: a plurality of elongate rungs connected together end to end from a first emitter end to a second emitter end in a plane so as to form a planar pattern; a plurality of corners, wherein each elongate rung is connected to another elongate rung through a corner having a corner apex and an opposite corner nadir; a first gap between adjacent non-connected elongate rungs, wherein the first gap extends from the first emitter end to a middle rung; a second gap between adjacent non-connected elongate rungs, wherein the second gap extends from the second emitter end to the middle rung, wherein the first gap does not intersect the second gap; and one or more cutouts at one or more of the corners of the plurality of corners between the corner apex and corner nadir or at the corner nadir. |
| US09659731B2 |
Portable actuator assembly
A portable actuator and safety switch assembly wherein the portable actuator includes a housing and an actuator for selectively engaging with a control mechanism of said safety switch. The actuator is at least one of partially located within the housing, forms a part of the housing, or is attached to the housing. The assembly includes a controller that controls a configuration of the actuator assembly, such that the actuator assembly can selectively and controllably attain a first configuration wherein the actuator is able to interact with the control mechanism of the safety switch and a second configuration wherein the actuator is unable to manipulate the control mechanism of said safety switch. |
| US09659726B2 |
Switching device with improved tripping action in the event of a short circuit
A switching device having an arc quenching chamber, a fixed contact element and a movable contact element movable in a sliding contact between untripped and tripped positions within the chamber. A plurality of centering structures are arranged on the walls of the arc quenching chamber for centered guiding movement of the movable contact element as it moves from its untripped position to its tripped position. The centering structures may be fabricated unitarily with the chamber walls, as of plastic, and are arranged in parallel and spaced apart relation to one another. |
| US09659725B2 |
Switch
An inhibiter switch is configured to include a fixed contact point that is connected to and disconnected from a movable contact point. The movable contact point is configured to make pressure contact with the fixed contact point by the movement of a movable board by a shaft member, wherein a press-fit amount of the shaft member to a projecting portion is made smaller toward a connecting portion between the projecting portion and an inner periphery of an insert hole of the movable board. |
| US09659720B2 |
Machine tool switching device
A machine tool switching device, in particular for portable machine tools, includes at least one switching unit that has at least one movably mounted operating element for actuating a mechanical, electrical, and/or electronic switching element. The machine tool switching device further includes at least one blocking device for blocking at least one movement of the operating element. The blocking device includes at least one movably mounted release element provided to lift the blockage of the operating element. The release element is mounted on the operating element so as to be movable in a translatory manner. |
| US09659714B2 |
Solid electrolytic capacitor including insulating substrate having recessed surface
A solid electrolytic capacitor comprises insulating substrate having an upper surface and a lower surface, a capacitor element disposed on the upper surface, a positive electrode lead-out structure, a negative electrode lead-out structure, and an exterior body configured to cover the capacitor element on the upper surface. The capacitor element has a positive electrode member, a negative electrode member, and a dielectric member. The positive electrode lead-out structure has a positive electrode terminal formed on the lower surface of the insulating substrate and is electrically connected to the positive electrode member. The negative electrode lead-out structure has a negative electrode terminal formed on the lower surface of the insulating substrate and is electrically connected to the negative electrode member. The insulating substrate has a step portion made up of a recessed surface formed by recessing the upper surface and a projected surface formed by projecting the lower surface. |
| US09659704B2 |
Chip electronic component
A chip electronic component includes a magnetic body containing magnetic metal powder, internal coil parts embedded in the magnetic body, and an anti-plating layer disposed on at least one of upper and lower surfaces of the magnetic body. The anti-plating layer contains magnetic metal powder having particle sizes within the range of 0.1 μm to 10 μm. |
| US09659703B2 |
Ignition coil for internal combustion engine
An ignition coil for an internal-combustion engine, including an assembly of a primary coil, a secondary coil, and a central core, and a ring-shaped outer core surrounding the assembly. The assembly includes at least one first protrusion protruding from a first end surface of the secondary spool. The at least one first protrusion is in contact with an inside surface of the outer core and offset from the central core toward an opening of the outer core in a penetration direction of the outer core. The assembly further includes at least one second protrusion protruding from a second end surface of the primary spool. The at least one second protrusion protrudes beyond a second axial end surface of the central core so as to be in contact with the inside surface of the outer core and extends substantially the entire length of the outer core in the penetration direction. |
| US09659698B2 |
Electromechanical solenoid having a pole piece alignment member
An electromechanical solenoid has a solenoid assembly including a solenoid coil with a coil aperture formed therein. A pole piece assembly is positioned at least partially within the coil aperture, the pole piece assembly including a first pole piece and a second pole piece positioned at least partially within an hour-glass shaped alignment member. The first pole piece has a first bore and a first outer tapered surface extending away from the first bore, and the second pole piece has a second bore and a second outer tapered surface extending away from the second bore. An armature is moveable within the first bore and the second bore in response to a magnetic field produced by the solenoid coil. |
| US09659697B2 |
Actuator with transmission element
An actuator (1) including at least one electromagnet (121, 122, 13, 14, 16, 17, 181, 182, 19, a magnet housing (11), at least one thrust pin (24) and at least one movable armature (14) with a respective plunger (16) that is movable in an axial direction is provided. When the at least one electromagnet (10) is energized, an axial movement of the at least one armature (14) can be transmitted via the at least one plunger (16) to the at least one thrust pin (24). At least one lever (30) is provided which is pivotably mounted on one side in the magnet housing (11) and with which at least one plunger (16) and the at least one thrust pin (24) are operatively connected such that the axial movement of the at least one plunger (16) can be transmitted to the at least one thrust pin (24). |
| US09659696B2 |
Permanent magnet assemblies for generating concave field lines and process for creating optical effect coating therewith (inverse rolling bar)
The invention relates to the field of the protection of security documents such as for example banknotes and identity documents against counterfeit and illegal reproduction. In particular, the invention relates to magnetic-field-generating devices which produce positively curved magnetic field lines in a concave fashion. The invention also relates to the use of these magnetic-field-generating devices for producing optical effect layers OEL which exhibit the optical impression of a positive rolling bar effect and to processes using these magnetic-field-generating devices, e.g. in the field of document security. |
| US09659691B2 |
Thin-film thermistor element and method of manufacturing the same
Provided is a thin-film thermistor element including a Si substrate 2, a thermistor thin film 5 formed on the Si substrate 2, and an electrode 3 made of platinum, an alloy thereof or the like and formed on, under or inside the thermistor thin film 5. The electrode 3 is formed from a film deposited containing oxygen and nitrogen and then crystallized by heat treatment. |
| US09659688B2 |
Harness protector and wire-harness wiring structure
Provided is a harness protector, wherein a wire harness can easily be formed into a planar shape (with an oblate cross section), and maintained in that state. The harness protector is provided with: a protector body further provided with a roughly tabular-shaped bottom-plate section onto which a wire harness is to be placed, and a holding plate section that is integrally formed on one side of the bottom-plate section in pivotable state, and crushes the wire harness into an oblate cross-section shape, along with the bottom-plate section; and tying bands that anchor the holding plate section onto the bottom-plate section, in a state of having the holding plate section crushing the wire harness into an oblate cross-section shape. |
| US09659685B2 |
Substantially flat fire-resistant safety cables
A fire-resistant safety cable may include: at least two electrical conductors; an insulating layer around each of the at least two electrical conductors in order to obtain at least two separate insulated elements; and/or an outer jacket surrounding the at least two separate insulated elements. The insulating layer may be formed from at least one polymeric material capable of being converted, at least on a surface of the insulating layer, into a ceramic state at high temperatures in a fire. The at least two separate insulated elements may be untwisted and arranged so as to be parallel to each other, side by side, and separated by a space. The outer jacket may at least partially fill the space. A thickness of the outer jacket may be approximately constant over an external surface of the at least two separate insulated elements. |
| US09659684B2 |
Manufacturing a conductor part
A method for manufacturing a conductor part for a connector unit is provided. The conductor part includes a conductive core, an insulating sleeve, and at least a first conductive layer arranged between the conductive core and the insulating sleeve. The method includes equipping at least one section of a radially inner surface of the insulating sleeve with the first conductive layer, and equipping at least one section of a radially outer surface of the insulating sleeve with at least a second conductive layer. The second conductive layer is a metal layer or a conductive plastic layer. The method also includes inserting the conducting core in the insulating sleeve before or after equipping a surface of the insulating sleeve with a conductive layer. |
| US09659682B2 |
Composition and method for forming conductive pattern, and resin structure having conductive pattern thereon
The present invention relates to a composition for forming a conductive pattern capable of forming a fine conductive pattern on a variety of polymer resin products or resin layers by a significantly simple process, a method for forming a conductive pattern using the same, and a resin structure having a conductive pattern. The composition for forming a conductive pattern includes: a polymer resin; and a non-conductive metal compound including at least one of first and second metals as a predetermined non-conductive metal compound including the first and second metals, wherein a metal core including the first or second metal, or an ion thereof is formed from the non-conductive metal compound by electromagnetic irradiation. |
| US09659673B2 |
Nuclear fission reactor fuel assembly and system configured for controlled removal of a volatile fission product and heat released by a burn wave in a traveling wave nuclear fission reactor and method for same
A nuclear fission reactor fuel assembly and system configured for controlled removal of a volatile fission product and heat released by a burn wave in a traveling wave nuclear fission reactor and method for same. The fuel assembly comprises an enclosure adapted to enclose a porous nuclear fuel body having the volatile fission product therein. A fluid control subassembly is coupled to the enclosure and adapted to control removal of at least a portion of the volatile fission product from the porous nuclear fuel body. In addition, the fluid control subassembly is capable of circulating a heat removal fluid through the porous nuclear fuel body in order to remove heat generated by the nuclear fuel body. |
| US09659670B2 |
Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer
Computer-implemented methods, computer-readable media, and systems for classifying defects detected in a memory device area on a wafer are provided. |
| US09659663B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line coupled to the first memory cell; and a second word line coupled to the second memory cell. When data is read from the first memory cell, a first voltage and a second voltage is applied to the first word line. A voltage of the second word line changes a first number of times while the first voltage is applied to the first word line, and the voltage changes a second number of times different from the first number of times while the second voltage is applied to the first word line. |
| US09659660B2 |
Memory system and driving method thereof using at least two zone voltages
A driving method of a nonvolatile memory device includes receiving a program command and an address. The method includes changing a number of adjacent zones of a plurality of zones formed of unselected word lines according to a location of a selected word line corresponding to the received address. The method further includes applying different zone voltages to the number of adjacent zones and remaining zones. The nonvolatile memory device includes a plurality of strings formed to penetrate word lines stacked on a substrate in a plate shape. |
| US09659658B2 |
Nonvolatile memory device, storage device including the nonvolatile memory device, and operating method of the storage device
A storage device includes a nonvolatile memory device and a memory controller is provided. The nonvolatile memory device includes a plurality of blocks. The memory controller is configured to detect, upon receiving a power-on signal, a partial block among the plurality of blocks. The partial block includes a first page incompletely programmed due to sudden power-off occurred to the storage device. The memory controller determines whether or not to perform a dummy program operation on the partial block, and programs a second page of the partial bock with dummy data. The first page is different from the second page. |
| US09659656B2 |
Techniques for programming of select gates in NAND memory
In a non-volatile memory formed according to a NAND-type architecture that has, on one or both ends of the NAND strings, multiple select gates including some with programmable threshold voltages, a structure and corresponding for efficiently programming of such select gates. On the drain side, the end most of multiple drain select transistors is individually controllable and used for biasing purposes while one or more other drain side select gates are collectively programmed to set adjust their threshold voltage. Independently, on the source side, the end most of multiple source select transistors is individually controllable and used for biasing purposes while other source side select gates are collectively programmed to set adjust their threshold voltage. |
| US09659650B2 |
Multistate register having a flip flop and multiple memristive devices
A multistate register, comprising: a flip-flop that comprises a first latch, a second latch and an intermediate gate coupled between the first and second latches; multiple memristive devices; and an interface coupled between the multiple memristive devices and the flip-flop; wherein the multistate register is arranged to operate in a memristive device write mode, in a memristive device read mode and in a flip-flop mode; wherein when operating in the memristive device read mode, the interface is arranged to write to a first selected memristive device of the multiple memristive devices a first logic value stored in the first latch; wherein when operating in the memristive device write mode, the interface is arranged to write to the second latch a second logic value stored in a second selected memristive device of the multiple memristive devices; and wherein when operating on a flip-flop mode logic the interface is prevented from transferring values between the flip flop and the memristive devices. |
| US09659647B1 |
Systems and methods for programming a memory cell having a programmable resistance
A circuit for programming a memory cell having a programmable resistance includes a switch. The circuit is configured to apply a programming voltage to the memory cell when the switch is in a first state. The circuit is configured to apply a programming current to the memory cell when the switch is in a second state. The resistance of the memory cell changes from a first resistance state to a second resistance state based on the application of the programming voltage or the programming current to the memory cell. |
| US09659641B2 |
On-chip resistance measurement circuit and resistive memory device including the same
A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively. |
| US09659632B2 |
SRAM with stacked bit cells
Static random access memories (SRAM) are provided. The SRAM includes a plurality of bit cells. Each bit cell includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass gate transistor coupled between the first inverter and a bit line, and a second pass gate transistor coupled between the second inverter and a complementary bit line. The bit cells are divided into a plurality of top tier cells and a plurality of bottom tier cells, and each of the bottom tier cells is disposed under the individual top tier cell. The first inverter of the top tier cell is disposed on the second inverter of the corresponding bottom tier cell within a substrate, and the second inverter of the top tier cell is disposed on the first inverter of the corresponding bottom tier cell within the substrate. |
| US09659625B2 |
Dynamic random access memory with configurable refresh rate for communications systems
An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit. |
| US09659622B1 |
Sense amplifier
In a non-volatile memory, a method of performing a sensing operation to read a non-volatile (NV) element includes a first and a second phase. During the first phase, the NV element is coupled via a sense path transistor to a first capacitive element at a first input of an amplifier stage and a reference cell is coupled via a reference sense path transistor to a second capacitive element at a second input of the amplifier stage. During the second phase, the NV element is coupled via the sense path transistor to the second capacitive element and the reference cell is coupled via the reference sense path transistor to the first capacitive element. During the first phase, the first and second capacitive elements are initialized to voltages representative of states of the NV element and reference cell, respectively. During the second phase, the voltage differential between the two voltages is amplified. |
| US09659620B2 |
Memory device with self-boosted mechanism
An electronic device is disclosed that includes memory cells, a word line, a selection unit and a self-boosted driver. The memory cells are configured to store data. The word line is coupled to the memory cells. The selection unit is disposed at a first terminal of the word line, and is configured to transmit a selection signal to activate the word line according to one of a read command and a write command. The self-boosted driver is disposed at a second terminal of the word line, and is configured to pull up a voltage level of the word line according to a voltage level of the word line and a control signal. |
| US09659618B1 |
Memory interface, memory control circuit unit, memory storage device and clock generation method
A memory interface, a memory control circuit unit, a memory storage device and a clock generation method are provided. The method includes: receiving a first data strobe signal and a second data strobe signal from a volatile memory, where the first data strobe signal and the second data strobe signal are differential signals corresponding to each other; if a relative relation between a first voltage value of the first data strobe signal and a reference voltage value of a reference voltage signal conforms to a default condition, generating a clock signal in response to the first data strobe signal and the second data strobe signal; and sampling a data signal from the volatile memory based on a raising edge and a falling edge of the clock signal. Thereby, an accuracy for sampling the data signal from the volatile memory can be improved. |
| US09659616B2 |
Configuration fuse data management in a partial power-on state
In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode. |
| US09659614B2 |
Integrated keeper circuit
Various implementations described herein are directed to a keeper circuit coupled to a bitline input path and configured to provide a first voltage source signal to the bitline input path based on a keeper enable signal. The keeper circuit may include an NMOS transistor. Further, a logic device may be coupled to the bitline input path and configured to receive the bitline input signal, receive the first voltage source signal from the keeper circuit, and provide an inverted bitline input signal as an output signal. |
| US09659610B1 |
Apparatuses and methods for shifting data
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage. |
| US09659608B2 |
Semiconductor memory apparatus, and method for training reference voltage
A semiconductor memory apparatus may be configured to, in a data reference voltage training mode, set a reference pad reference voltage by training a first initial data reference voltage for a reference pad being any one of a plurality of input/output pads, and set a data reference voltage for each of remaining input/output pads by training a second initial data reference voltage being the reference pad reference voltage for each of the remaining input/output pads. |
| US09659607B2 |
Sense amplifier circuit and semiconductor memory device
To improve reading accuracy of a sense amplifier circuit and a semiconductor memory device. A sense amplifier circuit includes an N type FET which is a sensing transistor connected between a power supply and a ground via a data line that extends to a memory cell, a resistance element that is connected between a gate of the sensing transistor and the power supply, and a capacitance element that is connected between the gate of the sensing transistor and the ground. |
| US09659606B2 |
Differential sensing circuit with dynamic voltage reference for single-ended bit line memory
The present invention provides a differential sensing circuit with a dynamic voltage reference for a single-ended bit line memory is disclosed. The exemplary differential sensing circuit comprises: a dynamic voltage reference generating unit and a differential sensing amplifying unit. The dynamic voltage reference generating unit is coupled to an input voltage, and utilized for receiving a setting signal to generate the dynamic voltage reference. The differential sensing amplifying unit is coupled to the single-ended bit line memory and the dynamic voltage reference generating unit, and utilized for receiving at least an input signal from the single-ended bit line memory and the dynamic voltage reference from the dynamic voltage reference generating unit, so as to generate at least an output signal accordingly. |
| US09659599B1 |
Multiple port data storage device
The present disclosure outlines front-end-of-line (FEOL) processing, middle-end-of-line (MEOL) processing, and back-end-of-line (BEOL) processing for fabricating a memory cell that can be implemented within a data storage device. The memory cell of the present disclosure represents a multiple port memory cell having at least three ports, such as a write-port, a first read-port, and a second read-port. The disclose FEOL processing is used to form semiconductor devices of the memory cell onto diffusion layers and polysilicon layers of a semiconductor layer stack. The disclosed MEOL processing is used to form interconnections, such as one or more vias and/or one or more contacts to provide some examples, between the semiconductor devices and metallization layers of the semiconductor layer stack. The disclosure BEOL processing is used to form the least three ports onto the metallization layers of the semiconductor layer stack. |
| US09659598B2 |
Timeline synchronization control method for multiple display views
A video surveillance system and methods for operating that sets the timeline for multiple views of video data from different cameras to playback separately from one another or to be linked so as to synchronize their playback. Placement and selection of a playback cursor to a particular point in a timeline of master view will cause linked views to automatically move to and synchronize to the same point in their associated timelines, and when the video data is being transmitted from multiple cameras to cause the cameras displaying the linked views to update so that the video data associated with each camera is updated to the selected point in time from the linked master view. Timeline resolutions for linked views are not affected by linking or unlinking views. |
| US09659597B2 |
Annotating media content for automatic content understanding
A system for annotating frames in a media stream 114 includes a pattern recognition system (PRS) 108 to generate PRS output metadata for a frame; an archive 106 for storing ground truth metadata (GTM); a device to merge the GTM and PRS output metadata and thereby generate proposed annotation data (PAD) 110; and a user interface 109 for use by the human annotator HA 118. The user interface 104 includes an editor 111 and an input device 107 used by the HA 118 to approve GTM for the frame. An optimization system 105 receives the approved GTM and metadata output by the PRS 108, and adjusts input parameters for the PRS to minimize a distance metric corresponding to a difference between the GTM and PRS output metadata. |
| US09659596B2 |
Systems and methods for motion-vector-aided video interpolation using real-time smooth video playback speed variation
Systems and methods for encoding and playing back video at adjustable playback speeds by interpolating frames to achieve smooth playback in accordance with embodiments of the invention are described. One embodiment includes a source encoder that includes a processor, memory including an encoder application, where the encoder application directs the processor to: select a subset of frames from a first video sequence; generate motion vectors describing frames from the first video sequence that are not part of the selected subset of frames, where each motion vector describes movement between a frame in the subset of frames and a frame not included in the subset of frames; store the motion vectors; decimate frames not included in the subset of frames from the first video sequence to generate a second video sequence having a nominal frame rate less than the frame rate of the first video sequence; and encode the second video sequence at the nominal frame rate. |
| US09659595B2 |
Video remixing system
A method and related apparatus for providing content information for a video remix, the method comprising: identifying at least one performer of an event on the basis of image data of a source video; obtaining information about a role of the at least one performer in the event; determining at least some video frames of the source video to contain said at least one performer as a dominant performer in said event; and annotating said video frames of the source video with a description of the role of the at least one performer. |
| US09659592B2 |
Perpendicular magnetic recording medium and method of manufacturing same
A perpendicular magnetic recording medium exhibits reduced noise and improved performance in such measures as SN ratio, and can realize high magnetic recording densities. In the perpendicular magnetic recording medium, at least a first nonmagnetic intermediate layer, second nonmagnetic intermediate layer, and magnetic recording layer are stacked in order on a nonmagnetic substrate. The first nonmagnetic intermediate layer is formed from a CoCrRuW alloy, and the second nonmagnetic intermediate layer is formed from an Ru-base alloy. |
| US09659590B1 |
Angled near-field transducer and waveguide
An apparatus comprises a waveguide having an input end that receives energy in a transverse electric (TE00) mode from an energy source along a substrate-parallel plane. The apparatus also includes a near-field transducer located proximate an output end of the waveguide that receives the energy in the TE00 mode. The output end of the waveguide is at an oblique angle to a cross-track line at an intersection of a media-facing surface and the substrate-parallel plane. The near-field transducer includes an enlarged portion at the oblique angle to the cross-track line. |
| US09659589B2 |
Free-standing reflector usable in heat assisted magnetic recording technology
A heat assisted magnetic recording (HAMR) write apparatus is described. The HAMR write apparatus is coupled with a laser that provides energy. The HAMR writer has a media-facing surface (MFS) and a laser-facing surface. The HAMR write apparatus includes a free-standing reflector and at least one waveguide. The free-standing reflector resides on the laser-facing surface and has a concave reflective surface oriented to receive the energy from the laser. The waveguide(s) are optically coupled with the free-standing reflector and direct energy from the laser toward the MFS. |
| US09659585B2 |
Magnetic sensor seed layer with magnetic and nonmagnetic layers
A magnetic sensor has a bottom shield layer, an upper shield layer, and a sensor stack adjacent the upper shield layer. The sensor includes a seed layer between the bottom shield layer and an antiferromagnetic layer of the sensor stack. The seed layer has a magnetic layer adjacent the sensor stack and a nonmagnetic layer adjacent the bottom shield layer. |
| US09659580B2 |
Moving-magnet type pickup cartridge
A moving-magnet type pickup cartridge is disclosed, which includes a cantilever, a stylus chip attached to a front end part in a longitudinal direction of the cantilever, a damper disposed at a base end part in the longitudinal direction of the cantilever and configured to support the cantilever in a swingable manner, a magnet disposed in the longitudinal direction of the cantilever and immediately above the stylus chip at the front end part of the cantilever, and configured to vibrate with vibration of the stylus chip, and a yoke formed in a U-shape, having generating coils being wound thereon, and having magnetic poles at both leg parts thereof being disposed to face the magnet. With this configuration, there is provided a moving-magnet type pickup cartridge enables not only to ensure a large output signal but also to obtain a faithfully reproduced sound with little distortion. |
| US09659577B1 |
Voice controlled assistant with integrated control knob
A voice controlled assistant has a housing to hold one or more microphones, one or more speakers, and various computing components. The housing has an elongated cylindrical body extending along a center axis between a base end and a top end. The microphone(s) are mounted in the top end and the speaker(s) are mounted proximal to the base end. A control knob is rotatably mounted to the top end of the housing to rotate about the center axis. The control knob has an outer surface that is substantially flush with an outer surface of the housing to provide a smooth, continuous appearance to the voice controlled assistant. |
| US09659576B1 |
Beam forming and acoustic echo cancellation with mutual adaptation control
Audio conferencing systems and methods with mutual adaptation control of adaptive beamforming and adaptive acoustic echo cancellation are disclosed. Mutual adaptation control may be achieved in a system including an adaptive beamforming module, an adaptive acoustic echo cancellation module, and an adaptation control module. The adaptive beamforming module has a controllable beamforming adaptivity and a beamforming adaptation state. The adaptive acoustic echo cancellation module has a controllable AEC adaptivity and an AEC adaptation state. The adaptation control module is configured and/or operates (i) to modify the beamforming adaptivity when the AEC adaptation state is unsettled (adapting to changed conditions), (ii) to modify the AEC adaptivity when the beamforming adaptation state is unsettled (adapting to changed conditions), (iii) to restore the beamforming adaptivity when the AEC adaptation state is settled, and (iv) to restore the AEC adaptivity when the beamforming adaptation state is settled. |
| US09659575B2 |
Signal processor and method therefor
The signal processor suppresses noise components contained in input sound signals by iterative spectral subtraction. The processor derives coherence from first and second directional signals having directivity characteristics on the basis of a pair of input sound signals, and controls the times of iteration of spectral subtraction on the basis of the coherence, thereby suppressing the noise components contained in the input sound signals. |
| US09659573B2 |
Signal processing apparatus and signal processing method, encoder and encoding method, decoder and decoding method, and program
The present invention relates to a signal processing apparatus and a signal processing method, an encoder and an encoding method, a decoder and a decoding method, and a program capable of reproducing music signal having a better sound quality by expansion of frequency band.A high band decoding circuit decodes high band encoded data outputs a coefficient table having coefficients for the respective high band sub-bands, which are specified by a coefficient index obtained as a result of decoding. A decoding high band sub-band power calculation circuit calculates decoded high band sub-band powers for the respective high band sub-bands based on low band signals and the coefficient table, and a decoded high band signal production unit produces decoded high band signals from these decoded high band sub-band powers. At this time, an extension and reduction unit newly produces or deletes coefficients of the coefficient table for the respective sub-bands to correspond to the number of sub-bands of the calculated decoded high band sub-band powers, thereby to extend or reduce the coefficient table. The present invention can be applied to a decoder. |
| US09659571B2 |
System and method for emitting and especially controlling an audio signal in an environment using an objective intelligibility measure
Public address systems or other systems for emitting audio signals, like music, speech or announcements, in different locations like supermarkets, schools, universities, and auditoriums are widely known. In one embodiment, invention proposes a system for emitting an audio signal in an environment. The system includes an audio source for providing the audio signal and at least one loudspeaker for emitting the audio signal. The system also includes at least one microphone for receiving an acoustic signal from the environment. The acoustic signal is based on the audio signal and may comprise disturbing components. The system also includes an analyzing module for analyzing the acoustic signal and for providing an intelligibility measure from an objective intelligibility measure method. The intelligibility measure is used as a feedback signal. |
| US09659567B2 |
Model based prediction in a critically sampled filterbank
The present document relates to audio source coding systems. In particular, the present document relates to audio source coding systems which make use of linear prediction in combination with a filterbank. A method for estimating a first sample (615) of a first subband signal in a first subband of an audio signal is described. The first subband signal of the audio signal is determined using an analysis filterbank (612) comprising a plurality of analysis filters which provide a plurality of subband signals in a plurality of subbands from the audio signal, respectively. The method comprises determining a model parameter (613) of a signal model; determining a prediction coefficient to be applied to a previous sample (614) of a first decoded subband signals derived from the first subband signal, based on the signal model, based on the model parameter (613) and based on the analysis filterbank (612); wherein a time slot of the previous sample (614) is prior to a time slot of the first sample (615); and determining an estimate of the first sample (615) by applying the prediction coefficient to the previous sample (614). |
| US09659565B2 |
Method of and apparatus for evaluating intelligibility of a degraded speech signal, through providing a difference function representing a difference between signal frames and an output signal indicative of a derived quality parameter
The present invention relates to a method of evaluating intelligibility of a degraded speech signal received from an audio transmission system conveying a reference speech signal. The method comprises sampling said reference and degraded signals into reference and degraded signal frames, and forming frame pairs by associating reference and degraded signal frames with each other. For each frame pair a difference function representing disturbance is provided, which is then compensated for specific disturbance types for providing a disturbance density function. Based on the density function of a plurality of frame pairs, an overall quality parameter is determined. The method provides for weighing disturbances in silent periods dependent on the loudness of the reference signal. |
| US09659564B2 |
Speaker verification based on acoustic behavioral characteristics of the speaker
The present invention relates to a non-standard speech detection system and method whereby a speech is analyzed based on models that are trained using personalized speech for each individual. The model is stored in a database and used to analyze a speech in real time to determine the content and behavior of an individual who is a party to a conversation that produces the speech. The results of the analysis can be used to determine if a conversation takes place under normal circumstances or under extraneous circumstances. |
| US09659562B2 |
Environment adjusted speaker identification
A system estimates environment-specific alterations of a user sound received at the system. The system modifies the received user sound to formulate a modified user sound by at least compensating for the audio modifications and/or formulates an expected audio model of a user by modifying a stored user-dependent audio model of the user with the audio modification. The system is also capable of estimating whether the received user sounds is from a particular user by use of a corresponding user-dependent audio model. |
| US09659560B2 |
Semi-supervised learning of word embeddings
Software that trains an artificial neural network for generating vector representations for natural language text, by performing the following steps: (i) receiving, by one or more processors, a set of natural language text; (ii) generating, by one or more processors, a set of first metadata for the set of natural language text, where the first metadata is generated using supervised learning method(s); (iii) generating, by one or more processors, a set of second metadata for the set of natural language text, where the second metadata is generated using unsupervised learning method(s); and (iv) training, by one or more processors, an artificial neural network adapted to generate vector representations for natural language text, where the training is based, at least in part, on the received natural language text, the generated set of first metadata, and the generated set of second metadata. |
| US09659558B2 |
Systems, methods, apparatus, and computer-readable media for adaptive active noise cancellation
An adaptive active noise cancellation apparatus performs a filtering operation in a first digital domain and performs adaptation of the filtering operation in a second digital domain. |
| US09659556B1 |
Methods of repairing an acoustic sandwich panel and acoustic sandwich panel repair kits therefor
A method of repairing an acoustic core cell of an acoustic sandwich panel is provided. The method comprises inserting a core repair splice adjacent to a number of damaged walls of the acoustic core cell of the acoustic sandwich panel, nesting the core repair splice onto the number of damaged walls, and bonding the core repair splice to the number of damaged walls and thereby to repair the acoustic core cell of the acoustic sandwich panel. |
| US09659554B1 |
Whistle/bottle-opener system
An upper plate and a similarly configured lower plate each have a serpentine forward edge, a linear rearward edge, a left edge, a right edge, an upper surface, and a lower surface. The upper and lower plates each have a whistle section and a laterally spaced bottle-opener section. A C-shaped bend couples the upper and lower plates. An upper hole extends through the upper plate in the whistle section. An axially aligned lower hole extends through the lower plate in the whistle section. A J-shaped notch extends through the upper plate and the lower plate and the C-shaped bend at the rearward edge in the bottle-opener section. |
| US09659553B1 |
Guitar effects pedal case
The case of the present invention allows a user to store, transport and use as many as 15 guitar effects pedals, depending on size, and optional, associated accessory components such as a pedal switch controller, a power supply and a power strip, in a small footprint and enables the user to quickly and efficiently set up and play guitar with effects pedals on a plug-and-play basis. The case has a base with a shelf that can accommodate up to six effects pedals. The base also may receive and house a removable or slide-out drawer that can accommodate up to nine pedals. The drawer may have an optional, removable, upper shelf that can accommodate up to five pedals. The drawer may have an optional, articulating shelf that can accommodate mounted thereon a pedal switch controller for the pedals and at least one pedal. |
| US09659548B2 |
Automatic installation method for video wall and related system
An automatic installation method for video wall comprises the following steps. In the step (a), it employs a control system to output a plurality of identifiable images to a plurality of video devices of the video wall. In the step (b), it employs an image capturing device to capture the plurality of identifiable images. In the step (c), based-on the plurality of identifiable images, it employs the image capturing device to determine position data for the video devices, frame dimension of each of the video devices and spacings between adjacent video devices, and calibrate the identifiable images to obtain a setting value thereof. In the step (d), based-on the position data for the video devices, the frame dimension of each of the video devices and spacings between adjacent video devices and the setting value, it employs the control system to install and set-up the video wall automatically. |
| US09659540B1 |
GOA circuit of reducing power consumption
The present invention provides a GOA circuit of reducing power consumption. In the GOA unit circuit of the Nth stage, the twenty-second thin film transistor (T22) of the pull-up module (300) is controlled by the twenty-first thin film transistor (T21) of the second pull-up controlling and transmission module (200) to output the constant high voltage level (VDD) to the scan driving signal (G(N)) for reducing the parasitic capacitance of the clock signal, lowering the voltage level of the clock signal, easing the loading of the clock signal, and thus, to reduce the power consumption of the GOA circuit; the clock signal (CK(m)) is outputted to the stage transfer signal (ST(N)) through the twenty-first thin film transistor (T21), and the stage transfer signal (ST(N)) is employed for the transmission of the signal and the backward feedback to reduce the loading of the scan driving signal, and enhance the propulsive force of the scan driving signal, and the normal function of the GOA circuit can be ensured; and the forty-first thin film transistor (T41) is added in the pull-down holding module (700) to pull down the stage transfer signal (ST(N)) for preventing the electrical leakage of the twenty-second thin film transistor (T22). |
| US09659538B2 |
Power reduction technique for digital display panel with point to point intra panel interface
A system and method are disclosed to control the power consumption of column drivers in a display system. A video input signal is received which has an active video period and a vertical blanking period between frames. A timing controller transmits a first video frame to a column driver. The timing controller transmits a column driver disable command during a vertical blanking period. Prior to the subsequent active video period, the timing controller transmits a column driver enable command. The timing controller proceeds to transmit a second video frame to the column driver. In one embodiment, the timing controller determines whether to disable and enable the column driver based on a refresh rate, the refresh rate calculated by the timing controller from the video input signal. |
| US09659532B2 |
Four-channel transmissive display system
A four-color transmissive display system incorporates a display having independently variable light sources for different colors, and a controller. The controller is configured to receive and process a three-color input image signal, and provide a four-color output image signal to the display. The controller incorporates units respectively configured to (1) calculate a blue reduction factor for each pixel, dependent on luminance differences between blue and other color components, (2) produce respective saturation adjustment factors for red, green, and blue, (3) apply the blue reduction factor to reduce blue luminance, and apply the saturation adjustment factors to reduce saturation of other colors, (4) produce the output image signal. An optional sensor is operable to provide a control signal to the controller, whereby display power can be reduced. An optional estimating unit is configured to estimate current required to display the input image signal, for adjustment of the output image signal. |
| US09659530B2 |
Display
A display is disclosed. The display comprises a panel, a data driver and a scan driver. The panel comprises pixels, data lines and scan lines. The data lines transmit data signals to the pixels, and the scan lines transmit scan signals to the pixels. The data driver provides the data signals, and the scan driver provides the scan signals. The scan driver comprises a shift register circuit. The shift register circuit comprises an i+1th stage carry shift register, an ith stage carry shift register and a jth stage buffer shift register. The ith stage carry shift register generates an i+1th start signal to start the i+1th stage carry shift register, so that the i+1th stage carry shift register generates an i+2th start signal. The i+1th start signal starts the jth stage buffer shift register to generate a jth output signal. |
| US09659529B2 |
Display device that switches light emission states multiple times during one field period
A scan driving circuit includes a shift register unit and a logic circuit unit. The start of a start pulse of an output signal STp+1 of a p+1'th shift register is situated between the start and end of a start pulse of the output signal STp of a p'th shift register, and one each of a first enable signal through a Q'th enable signal exist in sequence between the start of the start pulse of the output signal STp and the start of the start pulse of the output signal STp+1. The operations of a (p′, q)'th NAND circuit are restricted based on period identifying signals, such that the NAND circuit generates scanning signals based only on a portion of the output signal STp corresponding to the first start pulse, the signal obtained by inverting the output signal STp+1, and the q'th enable signal ENq. |
| US09659527B2 |
Pixel circuits for AMOLED displays
The OLED voltage of a selected pixel is extracted from the pixel produced when the pixel is programmed so that the pixel current is a function of the OLED voltage. One method for extracting the OLED voltage is to first program the pixel in a way that the current is not a function of OLED voltage, and then in a way that the current is a function of OLED voltage. During the latter stage, the programming voltage is changed so that the pixel current is the same as the pixel current when the pixel was programmed in a way that the current was not a function of OLED voltage. The difference in the two programming voltages is then used to extract the OLED voltage. |
| US09659526B2 |
Light-emitting device capable of correcting variation in luminance among pixels
A light-emitting device is provided, which is capable of correcting variation in luminance among pixels due to variation in electrical characteristics, such as threshold voltage or mobility, among driving transistors in a period where image display is performed. The light-emitting device includes a pixel; a first circuit configured to generate a signal including information about a value of current extracted from the pixel; and a second circuit configured to correct an image signal in accordance with the signal. The pixel includes a light-emitting element; a transistor whose drain current has a value determined in accordance with the image signal; a first switch configured to control supply of the drain current to the light-emitting element; and a second switch configured to control extraction of the drain current from the pixel and control the supply of the drain current to the light-emitting element. |
| US09659525B2 |
Display device
A display device includes a display panel, a data driver, a scan driver, and a power supply. The display panel includes power voltage lines and pixels coupled to data lines and scan lines. The data driver supplies data voltages to the data lines. The scan driver provides scan signals to the scan lines. The power supply supplies a power voltage to the power voltage lines. The display panel includes a compensation resistance coupled between s pixels and one of the power voltage lines. |
| US09659523B2 |
Display panel and display panel driving method
Display panel includes: a power supply unit that generates first power supply voltage and variable second power supply voltage; and first and second power supply lines that transmit the first and second power supply voltages, respectively, to light emitting elements. The power supply unit (i) includes: first and second input terminals; a switching control unit; an inductor having first terminal connected to the second power supply line; a first switch element that switches conduction/non-conduction between a second terminal of the inductor and the first input terminal; a second switch element that switches conduction/non-conduction between the second terminal and the second input terminal; a capacitor having first electrode to which constant voltage is applied; and a third switch element that switches conduction/non-conduction between the second terminal and a second electrode of the capacitor, and (ii) collects, into the capacitor, and regenerates power from parasitic capacitance of the second power supply line. |
| US09659521B2 |
Color control method
Provided is a color control method that allows for a smooth modification of various display colors without using a huge number of parameters. When a duty ratio is changed from a pre-modified duty ratio (Ds) to a post-modified duty ratio (Df) over a color modification time (Td) from the start to the end of a color modification, the modified duty ratio (Dn) is determined through a calculation using equation for a fade-in process and equation for a fade-out process. Determining the modified duty ratio (Dn) in this manner can modify colors smoothly while reducing emergence of any unnatural colors. |
| US09659517B2 |
Converting system and converting method of three-color data to four-color data
A converting system and a converting method of three-color data to four-color data are provided. The converting system includes: a first calculating part configured to calculate a saturation value and a luminance enhancement coefficient according to inputted RGB values, a second calculating part configured to calculate luminance-enhanced RGB values according to the luminance enhancement coefficient and the inputted RGB values, a white determining part configured to use a minimum value of the luminance-enhanced RGB values as an outputted W value, and a three-color determining part configured to calculate outputted RGB values according to the luminance-enhanced RGB values and the outputted W value. The invention can obtain optimal outputted W values for different inputted RGB values and maximally increase the transmittance of the display apparatus. Accordingly, the display apparatus can increase the saturation of display image while enhance the transmittance. |
| US09659515B2 |
Display driver integrated circuit chip
A display driver integrated circuit chip is provided. The display driver integrated circuit chip may include a source driver circuit configured to process gamma data and generate a driving signal in response to a control signal and a clock signal, a gamma data manager circuit configured to provide the gamma data to the source driver circuit, control logic configured to provide the control signal and the clock signal to the source driver circuit, and a memory configured to store data used to operate the source driver circuit, the gamma data manager circuit and the control logic. A gamma signal line used to transmit the gamma data may include a metal line provided on an area other than an area on which the source driver circuit is disposed. |
| US09659514B2 |
Display device and method with ghost cancellation according to image blocks
Disclosed herein is a display device for determining whether or not ghost exists in a unit of a block to perform ghost cancellation, and a control method of the display device. According to an embodiment, the display device includes: a screen configured to display an image; a calculator configured to partition the screen into a plurality of blocks and determine whether or not ghost exists in at least one block of the blocks; and a controller configured to cancel ghost existing in the at least one block in response to the calculator determining that the ghost exists in the at least one block of the blocks. |
| US09659513B2 |
Method for compensating for a chromaticity shift due to ambient light in an electronic signboard
A method for use with an electronic signboard (e.g., an LED signboard) compensates psychovisual chromaticity shift due to ambient light. The method first measures a color of light reflected from the signboard. Based on the measurement a set of calorimetric equations defining the desired light to be perceived as being displayed by each pixel of the signboard are solved. The calorimetric equations are the additive color mixture of the ambient light and the light to be actually displayed by the pixel in the absence of ambient light. The calorimetric equations may be expressed in units of uniform color space. The solutions of the colorimetric equations are then used to control the light actually displayed by the pixel. |
| US09659511B2 |
LED light assembly having three-part optical elements
An LED lighting assembly includes a circuit board, a number of light emitting diodes (LEDs) overlying the circuit board, and optical element is proximate each LED and separate from other optical elements. Each optical element includes a first portion and a second portion that intersects with the first portion in a region between the first and second portions. The first and second portions are shaped so that at least one surface normal of the first portion intersects with at least one surface normal of the second portion, and the first and second portions are configured so that light from the associated LED exits the associated optical element through the first and the second portions. Each optical element also includes a third portion extending beyond the region between the first portion and the second portion in a direction away from the associated LED. |
| US09659510B2 |
Bag clip with date wheel
A bag clip comprises a pair of opposing jaws configured for resilient movement between an open position in which the jaws are apart from one another and a closed position in which the jaws are adjacent one another. An indicator wheel attached to the clip includes indicators that may correspond to dates on which the bag was opened and the clip was attached. A second indicator wheel may be included, in which the first wheel may correspond to months of the year and the second wheel may correspond to days of the month. |
| US09659509B2 |
Multi-purpose labeling device
A labeling device that can be affixed to articles of different shapes by more than one method and can provide information regarding the contents of the article. |
| US09659506B2 |
Apparatus, system, and method for teaching multiplication
The present invention relates to an apparatus, system, and method for teaching mathematics. Specifically, the present invention relates to a system and method for helping students solve advance multiplication problems and teaching students how to perform the same. Even more specifically, a student may use the present invention to cover up confusing numbers and isolating a single digit for multiplication. The present invention provides students with a space for providing the solution to the single digit multiplication. Further, the present invention allows a student to shift to a different single digit for multiplication without becoming confused with the previously solved multiplications. |
| US09659505B2 |
Dementia therapy method and instrument
A dementia therapy method that involves PWD in playing music, particularly as part of an ensemble “performing in concert”, which provides a rewarding and encouraging result of utilizing abilities that they may not even know they had to produce pleasing music. This method utilizes musical instruments adapted for playing by PWD who can utilize procedural rather than declarative memory in playing. By connecting a plurality of the instruments to a central director's console the combined musical sound can be coordinated to make it pleasing. Then several PWD are trained to play components of songs together as an group. An example of our specially adapted musical instruments is an easily played percussion instrument having an organized layout of one or more tone bars that, when struck (or touched) by a player generate a musical tone. The instrument may be further adapted to ease its use by movement restricted players. |
| US09659504B2 |
Presentation capture with automatically configurable output
A device and method for simultaneously capturing a combination of content video, content audio, presenter video and presenter audio, as well as distributing a combination of content video, content audio, presenter video and presenter audio to a digital sink via a high-definition multimedia interface (HDMI) connection. Video sources are automatically routed to the digital sink depending on the source configuration. |
| US09659503B2 |
Ambulatory route management based on a personal drone
Embodiments include method, systems and computer program products for route planning and management with a drone. Aspects include receiving a destination for an individual and determining multiple routes between a position of the individual and the destination. Aspects further include deploying the drone to determine safety and accessibility risks associated with the multiple routes and determining a preferred route from the multiple routes based on the safety and accessibility risks associated with the multiple routes. |
| US09659502B1 |
Drone range extension via host vehicles
Apparatus, method, computer program product, and system described for an autonomous vehicle (a drone) which uses one or more hosts to transport that drone on its journey. Potential hosts along the envisioned journey can be rated as to their suitability. That rating along with an indication of the value of traveling under its own power or remaining stationary for a particular time can be evaluated at any point along the journey to produce an effective route, time, cost, or whatever other factor is desirable. The drone can chose between these states and communicate with potential hosts and even stationary positions or it can remain in the mode it was just in. The drone can switch between one host and another, be charged by a host or at a stationary location, and can evaluate the different modes differently depending on the needs of the user and the drone itself. |
| US09659501B2 |
Vessel monitoring system and vessel monitoring method thereof
Provided is a vessel monitoring method of a vessel monitoring system, which includes receiving first vessel information from an automatic identification system message output from a vessel, receiving second vessel information on the vessel from a port management information system, selecting a vessel tracking parameter on a basis of the first vessel information and the second vessel information, and tracking the vessel by using a tacking algorithm corresponding to the vessel tracking parameter. |
| US09659499B2 |
Method of communicating vehicle messages using short message system messages
A system and method for communicating reportable vehicle events via SMS messages. The method carried out by the system includes storing a user-provided contact at a vehicle, monitoring a plurality of vehicle conditions, detecting that one of the vehicle conditions has become a reportable vehicle condition, and sending a short-message service (SMS) message to the stored contact based on the determination, wherein the SMS message includes information associated with the reportable vehicle condition. |
| US09659495B2 |
Method and apparatus for automated service schedule derivation and updating
A method, apparatus and computer program products are provided for automatically determining or fine-tuning bus service schedules for bus stops along a route. One example method includes causing reception of GPS data from a plurality of buses or uses from along a transit route, the GPS data comprised of a plurality of location points and associated temporal data, aggregating the location data by route and direction to determine a trip count, causing reception of at least one bus stop location, partitioning the associated temporal data into a number of clusters in accordance with the trip count, calculating a mean arrival time at the at least one bust stop for each cluster, and generating, using a processor, at least one service schedule for the at least one bus stop, wherein the mean arrival time of each cluster represents the service schedule. |
| US09659491B2 |
Dynamic location referencing strands
Systems and methods are described for referencing road strands. Speed data for a set of adjoining road segments is identified. Using at least one of the adjoining road segments, a strand database for is accessed to retrieve a predetermined strand of road segments. An aggregate speed value for the predetermined strand of road segments is calculated based on the speed data for the set of adjoining road segments represented by the predetermined strand of road segments. The aggregate speed value is provided as a representative of traffic on the set of adjoining road segments represented by the predetermined strand of road segments. |
| US09659490B2 |
Self-service crossing aid for pedestrians
A tool for a crossing aid on a mobile device. The tool determines, by a first computer processor, a unique ID associated with a crossing signal. The tool searches, by the first computer processor, for a wireless access point (WAP) having the unique ID. The tool determines, by the first computer processor, whether the WAP having the unique ID is found. Responsive to determining that the WAP having the unique ID is found, the tool determines, by the first computer processor, haptic feedback. The tool initiates, by the first computer processor, the haptic feedback on the mobile device to aid in crossing. |
| US09659488B2 |
Metrology with universal serial bus (USB) connection
Data communication may be accomplished between a utility meter and a peripheral device via a universal serial bus (USB) connection and a USB protocol. The meter may include metrology components arranged to measure utility consumption at a site. The meter may further include components for providing the data communication with the peripheral via the universal serial bus (USB) connection and a USB protocol. In an implementation, the meter provides electrical isolation between the data communication components and the metrology components. |
| US09659487B2 |
Remote control configuration using a remote control profile
Utilizing remote control profile information for configuration of a remote control device. A media processing device may store a remote control profile, locally or on a server accessible via a wide area network, which may include information for configuring a remote control device to utilize one or more wireless remote control commands for controlling the media processing device. The media processing device may also detect one or more wireless remote control commands for controlling one or more other electronic devices and update the remote control profile to include information for configuring a remote control device to utilize those commands. It may be determined to configure a remote control device according to the remote control profile based at least in part on proximity of the remote control device to the media processing device. The remote control device may then be configured according to the remote control profile. |
| US09659486B2 |
Device and system for protecting a person from RF radiation
A radiofrequency (“RF”) transmitter site protection system and an RF radiation protection device are provided. The RF radiation protection device includes a control system and a communication module. The control system includes a processor. The communication module is adapted to communicate with a device operable to sense RF radiation and to receive data representative of a level of the RF radiation proximate the RF safety monitoring device from the RF safety monitoring device. |
| US09659483B2 |
System for leveraging a user's geo-location to arm and disarm network a enabled device
A system includes a security monitoring device in a monitored physical location, a security processing system, and one or more mobile devices. The one or more mobile devices are configured to communicate with the security monitoring device over a network and the security monitoring device is configured to communicate with the security processing system via the network. The security monitoring device and the security processing system device are configured to arm and disarm based on geolocation data associated with at least one of the mobile user devices. |
| US09659479B2 |
System and method to indicate lack of usage for personal items
A method, system and computer-usable medium for performing a usage monitoring operation on an item, comprising: defining a predefined criteria relating to usage of the item; monitoring usage of the item based upon input provided by a sensor associated with the item; and, generating an indication when the predefined criteria is detected. |
| US09659477B1 |
Wireless wearable device platform
Wearable electronic devices configured to connect to cellular network(s) via radio transceiver(s) and methods of using such devices are described herein. These wearable electronic devices receive data from a sensor and transmit the data or a notification regarding the data via the radio transceiver. The wearable electronic devices can also provide feedback to the user regarding the data collected, or regarding indications received via the radio transceiver from a third party provider, including a cloud service. Further, the wearable devices may be customizable such that additional functionality may be added by downloading additional software applications and/or by the addition of physical modules, such as those containing additional sensors. |
| US09659476B2 |
System to monitor the ingestion of medicines
A system for monitoring ingestion of medicine (21) comprises forming a digestible radio frequency identification (RFID) tag (10). The RFID tag is attached to the medicine. The RFID tag and medicine are ingested. A signal from the RFID tag is monitored. |
| US09659475B2 |
System and method for adapting alarms in a wearable medical device
According to another example, a wearable medical device controller is provided. The device controller includes a memory and a processor coupled to the memory. The processor is configured to determine a correlation between a phenomenon identifiable by the wearable medical device controller and at least one response pattern associated with a patient and store, responsive to detecting the correlation, an adaptation path to address the at least one response pattern, the adaptation path specifying an adaptation of at least one characteristic of an alarm. The at least one response pattern may include a plurality of response patterns and the adaptation path may reflect adaptations made to address at least some of the plurality of response patterns. |
| US09659464B2 |
User terminal system and method
A monitoring system for a user terminal, wherein the user terminal comprises at least one application for controlling a user transaction or interaction process of the user terminal, the user transaction or interaction process comprising providing content data to a hardware device of the user terminal and outputting the content data to the user by the hardware device, and the monitoring system comprises monitoring means for monitoring the content data and determining a state of the user transaction or interaction process from the content data. |
| US09659463B2 |
Wagering game with reel-swap feature
A gaming system includes a gaming machine, a random element generator, and game-logic circuitry. An initial outcome is displayed in the form of a plurality of symbols arranged in a primary array and a secondary array, the primary array including a plurality of primary reels and the secondary array including a secondary reel. In response to the plurality of symbols including a trigger symbol, one of the primary reels is substituted with the secondary reel to form a modified primary array. A modified outcome is determined based on the modified primary array. |
| US09659461B2 |
Casino card handling system with game play feed to mobile device
A card game monitor manages play of a game with a video feed of casino table game play. A dealer deals a game using a card-handling device that randomizes and dispenses cards, which may be grouped into sets of hands by the card-handling device. A card recognition system recognizes card information including rank and suit of each card dispensed by the card handling device. A camera captures a video feed of casino table game play, which is transmitted to a mobile computing device operated by a player. A control system receives the card information from the card recognition device and manages control of the game using hand information associated with players. Player action elections from the mobile computing device are displayed to a dealer. The player provides a player action through the mobile computing device, which is used to facilitate play of the casino table game. |
| US09659457B2 |
Gaming machine and method having player electable bonus features
A gaming machine includes a player interface and an electronic controller arranged to control play of a game on the player interface. Prior to commencement of a bonus round, the electronic controller is arranged to display on the player interface a range of bonus features. Then in response to receiving via the player interface a player-selected bonus feature, the electronic controller determines a number of bonus games to be awarded to the player in the bonus round. The determination of the number of bonus games is randomized and is equalized so that a return to player percentage is at least equal to a predetermined return to player. The gaming machine is further arranged such that the player selected bonus feature applies to each and every awarded bonus game in the bonus round. |
| US09659456B2 |
Gaming system with improved wager mechanism
A gaming system comprising presentation means for presenting selected symbols from a first and a second symbol reel with respective first and second sets of symbols in a display area, outcome determination means for determining an outcome from a first win line symbol from the first set and a second win line symbol from the second set, being the symbols from the first and second sets that are positioned along a win line in the display area, outcome replacement means for, upon occurrence of a predetermined event, selecting for the first win line symbol a first replacement symbol, selecting for the second win line symbol a second replacement symbol and causing the output determination means to determine the outcome from the first and second replacement symbols, wherein the first and second replacement symbols are positioned at an equal distance from the first and second win line symbols respectively. |
| US09659455B2 |
Games with persistent effects in player pick rounds
A slot machine game feature provides for several types of persistent indicias in a player selection round. One type of persistent indicia can result not only awards an initial credit value when picked, like a regular pick result, but also have a persistent effect in the bonus round which continues to award another randomly-generated credit value in conjunction with each remaining or subsequent pick that the player makes in the bonus. Some versions include cumulative persistent effects, where multiple picks may uncover persistent prize features. Other persistent indicia cause other effects that persist through the player selection round. |
| US09659444B2 |
Gaming system and method for providing cashable and non-cashable credits upon cash-out
Gaming systems and methods for providing a customer with additional non-cashable credits upon completion of the game are provided herein. The gaming machine includes a game controller that is configured to receive a player input to play a wagering game on the gaming machine. The game controller is also configured to generate results for the wagering game, wherein the results include credits won or lost. The game controller is configured to add or subtract the credits won or lost to the player's total credit balance and provide the player with an amount of additional non-cashable credits upon ending the game, wherein the player must forgo a portion of their remaining credits in order to receive the amount of additional non-cashable credits, and wherein the non-cashable credits cannot be used with the same or another gaming machine without an additional input of currency into the gaming machine by the player. |
| US09659442B2 |
System and method for measuring gaming player behavior
Embodiments of the present invention are directed to analyzing recorded game information to determine information about a player's behavior. This is accomplished by analyzing the player's actions following a positive increase in credits within credit meter data. This analysis can be utilized in automatically altering a game parameter of the gaming device being played by the player or in providing operators trend information that can be used in modifying the game device or designing future gaming devices. An analysis station may be included in a gaming system using this analysis process to allow an operator to view and manipulate a graphical representation of the credit meter data. |
| US09659435B2 |
System and method for providing off-site online based gaming
A system and method for allowing wagers to be made on a game and awarding a payout as a function of an outcome of the game is provided. The game may played by a game server, located at a gaming facility, which is located at a predefined geographic location. A remote device may be provided at a location outside of the predefined geographic location. An agent, in communication with the game server and the remote device, may receive instructions from a patron via the remote device to place a wager on a game and for instructing the server to place the wager in response to receiving the instructions from the patron. |
| US09659432B2 |
Gaming machine having light splitting emotive lighting feature
A gaming system includes at least one light pipe which splits, reflects, and propagates light provided from one or more internal light sources to a plurality of external regions of the gaming system. The light sources may include sets of LEDs which deliver light via multiple light pipes or differing sections of the same light pipe, in varying configurations. Each light pipe may utilize a light splitter-reflector to receive, split, direct, propagate, and emit light from one or more sections of internally positioned light sources, simultaneously projecting decorative lighting to multiple exterior surfaces and regions of the gaming system. Light pipe assemblies may be constructed from modular pieces which include a separate light splitter-reflector, or from a single piece of uniform material which splits, directs, and emits light. Variations of direct light, indirect (reflected) light, and combinations of both enable various lighting patterns on the exterior of gaming machines. |
| US09659431B2 |
Gaming machine with improvements to replay functionality
A gaming machine has a display device; an input device; and a controller comprising a processor and a memory device. The memory device stores a plurality of instructions which when executed by the processor cause the processor to operate with the display device and the input device to display game data in the gaming window on the display device for each of a plurality of plays of a game. The gaming window has sides defining a geometrical shape and defining an enclosed area for presenting the game data on the display device. Upon a replay triggering event, the processor resizes the geometric shape of the gaming window and replays at least one of a plurality of plays of the game in the resized gaming window, wherein the game data displayed in the resized gaming window is accordingly scaled. |
| US09659429B2 |
Gaming device having advance game information analyzer
This concept is directed to methods of operating a gaming device to analyze game information that is part of a gaming event having a player interaction in advance of the player interaction to make a determination about the game play. These methods may be used for a variety of gaming devices such as slot machines, video keno devices, video poker machines, electronic table games, internet gaming terminals, etc. In each type of gaming device, these operation methods evaluate future game information during game play to determine one of multiple manners by which the game play will continue. These continuation manners may include changing the speed of game play, determining display characteristics of the game and outcome, providing tips or information to the player about the future game information, automatically initiating a subsequent game, or otherwise altering an aspect of the game play parameters in response to the evaluated game information. |
| US09659427B2 |
Vending machine and associated methods
A vending machine comprises a robotic arm and a pick mechanism that is coupled to the robotic arm. The pick mechanism is configured to retrieve a vendible product in the vending machine, and the robotic arm is configured to locate the pick mechanism at a location with a x-y coordinate that corresponds to the vendible product. The pick mechanism comprises a first roller, a second roller, and a belt that mechanically links the first and second rollers by forming a loop around the first and second rollers. The belt has a first portion and a second portion on opposing sides of the loop, and the second portion of the belt is coupled to the robotic arm. The pick mechanism further comprises a motor that is configured to rotate the first roller in order to translate the first and second portions of the belt in opposite directions to each other. The pick mechanism further comprises a picker arm extending in the z direction. The picker arm has a proximal portion closest to the first roller and a distal portion furthest from the first roller. The proximal portion is coupled to the first portion of the belt in order to be moved in the z-direction as the first roller is rotated, and the distal portion comprises a product picker for releasably attaching to the vendible product. |
| US09659422B2 |
Using temporary access codes
Managing access by a user includes requesting an access code from an external server, the external server providing the access code to the user only if the user is authorized for access, the access code being provided to an input unit, and the user being granted access by a security component if the access code is valid. The input unit may be a keypad. The access code maybe provided using RF communication, such as NFC, Bluetooth, and/or Bluetooth Smart. The device may request the access code from the external server. The device may be a mobile device. Managing access by a user may also include the user entering a PIN in addition to the access code. The pin may be entered by the user's device. The access may be to a physical area and the user may be granted access by having a door open. |
| US09659420B2 |
Security system of information processing apparatus and security control apparatus
In a security system, a security control apparatus 300 includes an authentication processing unit 31 for perform an authentication on whether the mobile terminal is a permitted terminal, a distance determining unit 32 for determining whether the mobile terminal is located within a predetermined distance from a printer 100, and an unlocking unit 33 for transmitting an unlock instruction signal to the printer 100 when the authentication is successful and it is determined that the mobile terminal is located within the predetermined distance from the printer 100. Therefore, a locking mechanism of the printer 100 cannot be unlocked even if the authentication is successful, and the locking mechanism of the printer 100 can be unlocked when it is further determined the mobile terminal is located within the predetermined distance from the printer 100. |
| US09659419B2 |
Method of controlling mobile terminal based on location information and applying security policy based on priority rules, and system thereof
A method for controlling a mobile terminal that includes receiving, at the mobile terminal, a security level of a defined location. The security level is set based on at least one of gate access information indicating a user of the mobile terminal is entering or exiting a gate, global positioning system (GPS) information of the mobile terminal, or an identifier (ID) of a wireless network apparatus scanned by the mobile terminal. The method further includes obtaining location information of the mobile terminal from a source that is determined according to the security level, identifying location of the mobile terminal based on the obtained location information, and applying a security policy to the mobile terminal based on the security level when the identified location corresponds to the defined location. |
| US09659417B2 |
Systems and methods for extraction and telemetry of vehicle operational data from an internal automotive network
Systems, methods, and related computer programs are provided wherein vehicle operation data is extracted from an internal automotive network. In an embodiment, a method comprises: i) obtaining data available on the internal automotive network via iterative interrogation; ii) analyzing the obtained data to identify a set of candidate data values having at least one common feature within a suitable proximity margin; and iii) heuristically selecting a candidate data value best matching one or more selection criteria to identify a true value. These systems and methods allow data to be extracted from proprietary and non-proprietary busses in the internal automotive network. |
| US09659411B2 |
Passive locators for a virtual reality headset
A virtual reality (VR) headset includes a plurality of marker groups each corresponding to a different location on the VR headset. Each marker group includes one or more passive locators having positions relative to each other. Passive locators included in a marker group are configured to reflect one or more bands of light emitted by a source device. A VR system determines positions of passive locators relative to each other in a marker group and bands of light reflected by the passive locators included in the marker group to determine a location on the VR headset. Based on the location on the VR headset, the VR system determines a position of the VR headset and identifies content to provide to the VR headset. |
| US09659409B2 |
Providing a spatial anatomical model of a body part of a patient
A method for providing a spatial anatomical model of a body part with the aid of at least one imaging examination modality is provided. At least one digital representation of the at least partial body part is provided to a control device by the at least one imaging examination modality. Based on the at least one digital representation, the control device determines a digital model and transmits the digital model to an output device. The output device determines the spatial model and outputs the spatial model as a hologram or workpiece. The spatial model is determined as a function of at least one specifying control parameter that describes a relevant portion of the spatial model and/or a mode of representation of the spatial model and/or of the portion. The control parameter is determined based on an operator control action executed by a user and received by an operator control device. |
| US09659401B2 |
Methods of and apparatus for using textures in graphics processing systems
A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. Each page of a graphics texture has an associated fade factor value that can be set by an application that is to use the texture to control the contribution that the page will be used to make to any texturing result that is generated using the texture page in question. The graphics processing system then controls the contribution of texture data from a texture page to texturing result data to be generated in accordance with the fade factor value associated with the texture page in question. This allows texture paging to be done in a more visually pleasing manner than just a binary “page-is-here”/“page-is-not-here” switch. |
| US09659397B2 |
Rig-based physics simulation
A method is disclosed for applying physics-based simulation to an animator provided rig. The disclosure presents equations of motions for simulations performed in the subspace of deformations defined by an animator's rig. The method receives an input rig with a plurality of deformation parameters, and the dynamics of the character are simulated in the subspace of deformations described by the character's rig. In certain embodiments, the present disclosure provides a method that transforms stiffness values defined on rig parameters to a non-homogeneous distribution of material parameters for the underlying rig. |
| US09659391B1 |
Request resolution shaper in a networked system architecture
An apparatus and related method are provided for generating a graphical display region for display of a plurality of pixels of a display device, comprising generating a timeline axis for display in the graphical display region, receiving requester event data for a plurality of requester events from a requester device relating to a request and storing the requester event data, including a time of occurrence for each requester event, and fulfiller event data for fulfiller events from a fulfiller device and storing the fulfiller event data, calculating a time scale for the timeline axis such that requester events and fulfiller events are displayable at a position along the timeline axis proportional to their respective time of occurrence, and a respective axial position for requester indicia representing the requester events and fulfiller indicia representing the fulfiller events at a position along the timeline axis proportional to their respective time of occurrence. |
| US09659383B2 |
Image compression device, image compression method, and image compression program
A reference image is generated by converting a vector image into a raster image, a temporarily-compressed image is generated by compressing the raster image according to a compression ratio, a comparison image of the same size as the reference image is generated by subjecting the temporarily-compressed image to interpolation enlargement processing, the above processing is repeated while varying the compression ratio if the error ratio between the reference image and the comparison image is greater than a benchmark error ratio, the above processing is repeated while varying the benchmark error ratio if the image volume of the temporarily-compressed image is greater than a predetermined memory capacity when the error ratio is at or under the benchmark error ratio, and the temporarily-compressed image is stored in memory as a compressed image of a vector image if the image volume of the temporarily-compressed image is at or under the memory capacity. |
| US09659378B2 |
Point cloud position data processing device, point cloud position data processing system, point cloud position data processing method, and program therefor
A technique for performing calibration of a laser scanner efficiently is provided. Point cloud position data of a building 131 is obtained by a laser scanner 141 in which exterior orientation parameters are already known. On the other hand, the building 131 is scanned by a laser scanner 115 while a vehicle 100 travels, and point cloud position data of the building 131 measured by the laser scanner 115 is obtained based on a trajectory the vehicle 100 has traveled. Then, exterior orientation parameters of the laser scanner 115 are calculated based on a correspondence relationship between these two point cloud position data. |
| US09659377B2 |
Methods and systems for determining and tracking extremities of a target
An image such as a depth image of a scene may be received, observed, or captured by a device. A grid of voxels may then be generated based on the depth image such that the depth image may be downsampled. A background included in the grid of voxels may also be removed to isolate one or more voxels associated with a foreground object such as a human target. A location or position of one or more extremities of the isolated human target may then be determined. |
| US09659375B2 |
Methods and systems for transforming luminal images
The invention provides methods and systems for correcting translational distortion in a medical image of a lumen of a biological structure. The method facilitates vessel visualization in intravascular images (e.g. IVUS, OCT) used to evaluate the cardiovascular health of a patient. Using the methods and systems described herein it is simpler for a provider to evaluate vascular imaging data, which is typically distorted due to cardiac vessel-catheter motion while the image was acquired. |
| US09659373B2 |
Method and device for ascertaining a blind area of a camera
A method for ascertaining a blind area of a camera includes a step of forming a first signal curve of a plurality of gradients, which have been determined as a function of gray values of adjacent image points of an image section of a first image recorded by the camera, and a second signal curve of a plurality of gradients, which have been determined as a function of gray values of adjacent image points of the image section of a second image recorded by the camera, the second image having been recorded with a time lag relative to the first image, and detecting the blind area, if a comparison of the first signal curve with the second signal curve shows that at least one section of the first signal curve is identical to a corresponding section of the second signal curve. |
| US09659366B2 |
Image processing display device and an image processing display program
An image processing display and an image processing display program that can prevent interference with catheter treatment even when the distal end of a catheter is located behind a treatment apparatus on X-ray fluoroscopic images. The image processing display displays X-ray fluoroscopic images to be obtained by looking through a region including blood vessels using X-rays during treatment, and includes a treatment apparatus image extractor and an image processor. The treatment apparatus image extractor, based on X-ray fluoroscopic images, extracts treatment apparatus images representing the treatment apparatus having the property of absorbing X-rays. The image processor determines the distal end position of the catheter to superimpose and display images representing the determined distal end position of the catheter on the region of the X-ray fluoroscopic images showing the treatment apparatus. |
| US09659356B2 |
Image blur correction apparatus and image blur correction method
An image blur correction apparatus, comprises a blur correction amount calculation unit configured to calculate a blur correction amount based on a shake amount of the apparatus; an estimation calculation unit configured to calculate an estimated value of the blur correction amount using a blur correction amount calculated up until a previous time; a correction unit configured to correct an image blur by cutting out an image using the blur correction amount or the estimated value; and a determination unit configured to determine whether or not to calculate the estimated value in accordance with a frame rate of a moving image. |
| US09659355B1 |
Applying corrections to regions of interest in image data
A method, a system, and computer program product for correcting image artifacts in image data captured by a camera sensor in conjunction with a flash. The method includes extracting, from a buffer, an image data captured by at least one camera sensor. The method then includes determining, from a metadata of the image data, a face in the image data and a position of a first eye and a second eye. The method then includes selecting at least one region of interest around at least one of the first and the second eye based on a size of the face and a distance between the eyes. In response to selecting the at least one region of interest, at least one correction is applied to the at least one region of interest to reduce or eliminate the appearance of at least one image artifact in the image data. |
| US09659354B2 |
Color matching for imaging systems
Techniques related to color matching and color conversion are discussed. Such techniques may include determining operators for converting input pixel values to output pixel values in a color space such that the operators may include a set of color conversion matrix operators, a chroma adaptation operator, and/or a luma adaptation operators determined based on one or more perceptual color space values associated with the input pixel values. |
| US09659350B2 |
Image processing device and image processing method for image correction, and non-transitory computer readable recording medium thereof
The present disclosure is to generate a high-quality image by correcting a predetermined correction target image based on a plurality of input images. In an image processing device 3, an image correcting section 160 detects a user tap gesture on a touch panel 250. When the position of the tap gesture is within foreground candidate areas detected by a foreground candidate area detecting section 140, the image correcting section 160 corrects a base image set by a base image setting section 120 in the areas corresponding to the foreground candidate areas. |
| US09659345B2 |
System and method of providing real-time dynamic imagery of a medical procedure site using multiple modalities
A system and method of providing composite real-time dynamic imagery of a medical procedure site from multiple modalities which continuously and immediately depicts the current state and condition of the medical procedure site synchronously with respect to each modality and without undue latency is disclosed. The composite real-time dynamic imagery may be provided by spatially registering multiple real-time dynamic video streams from the multiple modalities to each other. Spatially registering the multiple real-time dynamic video streams to each other may provide a continuous and immediate depiction of the medical procedure site with an unobstructed and detailed view of a region of interest at the medical procedure site at multiple depths. As such, a surgeon, or other medical practitioner, may view a single, accurate, and current composite real-time dynamic imagery of a region of interest at the medical procedure site as he/she performs a medical procedure, and thereby, may properly and effectively implement the medical procedure. |
| US09659344B2 |
Graphics processing apparatus, display apparatus for an aircraft cockpit, and method for displaying graphical data
Graphics cards normally control the image display of data processing systems.A graphics processing apparatus 1 is proposed which comprises a control device 2 for accepting graphical data relating to first graphic objects from a first application App_1 and for accepting graphical data relating to second graphic objects from a second application App_2; a geometry module 5 for generating the geometry data of the graphic objects from the graphical data; a raster module 7 for rasterizing the graphic objects on the basis of the geometry data and for generating pixels of the graphic objects; the control device 2, the geometry module 5 and the raster module 7 forming a graphics pipeline which is designed to process one of the graphic objects in a serial pass through by generating pixels of the graphic object from the graphical data relating to the graphic object, wherein the graphics pipeline is designed to interrupt the processing of one of the first graphic objects of the first application App_1 in a first serial pass through so that a partially processed graphic object is present, to process at least one of the second graphic objects of the second application App_2 in a second serial pass through, and subsequently to continue the processing of the partially processed graphic object of the first application App_1. |
| US09659343B2 |
Transpose of image data between a linear and a Y-tiled storage format
Systems, apparatus, articles, and methods are described including operations to transpose image data between a linear-type storage format and a Y-tiled-type storage format. |
| US09659340B2 |
Silicon chip of a monolithic construction for use in implementing multiple graphic cores in a graphics processing and display subsystem
A graphics processing chip includes multiple graphics pipeline cores and multi-pipeline core logic circuitry to process graphic data streams received from a processor and to drive multiple GPUs on the multiple graphics pipeline cores. |
| US09659339B2 |
Programmable graphics processor for multithreaded execution of programs
A processing unit includes multiple execution pipelines, each of which is coupled to a first input section for receiving input data for pixel processing and a second input section for receiving input data for vertex processing and to a first output section for storing processed pixel data and a second output section for storing processed vertex data. The processed vertex data is rasterized and scan converted into pixel data that is used as the input data for pixel processing. The processed pixel data is output to a raster analyzer. |
| US09659338B2 |
Method and system for adaptive content protection
Methods, systems, devices and applications for adaptive content protection for image data for use with interactive media display systems are disclosed. Initially, image data is obtained for display. A generated graphical obscuring element is then provided for the image data, the obscuring element generated for display overlaying the image data, wherein the obscuring element is generated to obscure, to a moderate degree, at least a portion of an underlying displayed image. On display of the image and the overlaying obscuring element, and in response to a prompt, the degree to which the obscuring element obscures the underlying displayed image is altered. |
| US09659337B2 |
Unified communication system and unified communication method using multi-login, terminal for controlling operation of unified communication tool, and communication method in terminal
Provided are a unified communication system and a unified communication method using multi-login, a terminal for controlling an operation of a unified communication tool, and a communication method in a terminal. The unified communication system may include a communication tool provider to provide a communication tool for at least one communication server associated with a user; a login manager to manage login information of the user when the user is logged in to two or more terminals simultaneously through respective communication tools on the two or more terminals, respectively, the login manager storing the login information of the user in a storage unit; a terminal determining unit to determine, among the two or more terminals, at least one terminal to which data associated with the user is to be transmitted based on the login information; and a communication unit to transmit the data to the at least one determined terminal. |
| US09659333B2 |
Dining experience management
The present disclosure relates to a system configured to manage a dining experience for guests at a food service establishment. In some implementations, the system may comprise one or more guest identification devices, one or more sensors, one or more host systems, and one or more processors. The system may be configured such that real-time detailed information about the food service establishment, guests of the food service establishment, food orders placed by guests of the food service establishment, table states of the tables in the food service establishment, and tasks performed by staff members is provided to the staff members of the food service establishment. The information may facilitate a unique guest experience for guests of the food service establishment wherein the guests may place a food order remotely, arrive at the food service establishment and self-select a table, and receive delivery of their food order at their selected table. |
| US09659332B2 |
Grid controller for use in smart grid system, smart grid system including the same, and method of controlling smart grid system
A grid controller is communicably connected to controllers of a plurality of power storage units. The grid controller: obtains transmission power transmitted from the smart grid system to an external power system, the transmission power being a sum of electric power generated by power generating units, electric power consumed by loads in the smart grid system, and electric power charged into and discharged from the power storage units; calculates differential power between the transmission power and a smoothing operation output, the smoothing operation output being obtained by performing smoothing operation on the transmission power by using a smoothing filter; and performs control of smoothing the transmission power by performing allocation of the differential power of the transmission power in accordance with a charge-discharge state of each of power storage parts of the plurality of power storage units. |
| US09659328B2 |
System and method for implementing a transaction
A method for executing a trade is provided that includes communicating financial information to a handheld device via a network, the financial information being associated with a trade that can be initiated by the handheld device. The handheld device is connected to the network via a Push to Trade™ protocol. The method also includes executing the trade on behalf of the end user. |
| US09659326B2 |
System and method for debt presentment and resolution
A system and method for debt presentment and resolution through an Intranet or Internet content provider is disclosed. Said system and method include a plurality of “transaction communities” which are electronic forums allowing interaction between a plurality of debtors and creditors through means of electronic mail (e-mail) or other electronic communication means. The Internet/Intranet based software application allows said debtors to access and input information related to a particular debt with any Internet browser software. Said debtors are provided with the URL (Universal Resource Locator) for said content provider along with a unique identification code from the collection agency(s) through mail correspondence or other communication means. Upon said user entering said URL and entering said identification code, said user may then proceed to choose from a variety of settlement options listed on the HTML (HyperText Markup Language) page. |
| US09659321B2 |
Real-time return of local search content based on global search key
In one embodiment, a method includes receiving at a network device, a search key from a global search initiated at a mobile device, the network device in communication with the mobile device via a proxy operable to retrieve the search key from a packet transmitted from the mobile device, performing a search at the network device for local content associated with the search key, and transmitting the local content from the network device for display on the mobile device. An apparatus and logic are also disclosed herein. |
| US09659318B2 |
Purchaser centered, product driven world wide web searching and e-commerce system
Aspects of this invention disclose a system for providing a purchaser specified product search engine, including providing storage circuitry comprising a database of products, storing product data in the database, receiving from a prospective product purchaser, product data of a desired product to purchase, accessing the database of products and comparing the product data to product data in the database, and determining a probability that the product data matches product data stored in the database. Other aspects may include a data processing apparatus providing a purchaser specified product search engine, including storage circuitry comprising a database of product data, processing circuitry configured to receive purchaser specified product search inquiry data, accessing the database of product data, and comparing the purchaser specified product search inquiry data to the product data; and determining a probability that the prospective purchaser product data matches the product data stored in the database. |
| US09659316B2 |
Providing navigation functionality in a retail location using local positioning technology
Methods and systems for providing navigation functionality in a retail location using local positioning technology are presented. In some embodiments, a customer assistance computing platform may receive one or more attributes associated with a beacon signal received by a customer computing device and an identifier associated with the customer computing device. Subsequently, the computing platform may determine an identity of a customer using the customer computing device. The computing platform then may determine a location of the customer using the customer computing device based on the one or more attributes associated with the beacon signal. Thereafter, the computing platform may generate one or more navigation instructions to guide the customer to another location. Then, the computing platform may send the one or more navigation instructions to the customer computing device. |
| US09659307B2 |
Cookie derivatives
Cookie derivatives and methods for generating cookie derivatives are provided. A cookie derivative comprises a transformation of at least one portion of data associated with a cookie (e.g., a name and/or data value). The cookie derivative may comprise a persistent or non-persistent cookie derivative that may be stored on a user's computing device (e.g., within a browser). The cookie derivative may alternatively comprise a virtual cookie derivative that is stored on a server (e.g., in a log file, a cache, or other data storage of the server). |
| US09659300B2 |
System and method for conducting a gift value transaction
A system and method for conducting a gift value transaction is described herein. The method includes receiving a request for payment for a gift, wherein the request includes buyer-imposed conditions on use of the gift; notifying a gift recipient of the gift; and tracking the gift recipient's account balances at the different merchants with the buyer-imposed conditions. |
| US09659299B2 |
Computer system and method for interim transaction diagnosis for selective remediation and customer loyalty enhancement
A customer feedback acquisition and processing system includes a data acquisition processor for receiving first and second customer feedback responses. The first customer feedback response is received by the data acquisition processor after notice of a claim is received and before the claim is resolved. The second customer feedback response is received by the data acquisition processor after it receives the first customer feedback response. The data acquisition processor may operate to classify the first customer feedback response in one of two categories. The two categories may be an attention-needed category and an attention-not-needed category. The system may also include a workflow router in communication with the data acquisition processor. The system may further include a supervisor terminal in communication with the workflow router. |
| US09659296B2 |
Method and system for presenting representations of payment accepting unit events
After sending a request to a payment module, via a first communication capability (e.g., BLE), to initiate a transaction with a payment accepting unit associated with the payment module, a mobile device with one or more processors, memory, one or output devices, and two or more communication capabilities obtains a notification from the payment module via the first communication capability. The notification indicates an event at the payment accepting unit associated with the payment module. In response to obtaining the notification, mobile device provides a representation of the notification to a user of the mobile device via the one or more output devices of the mobile device. For example, a message is displayed on a display of the mobile device, a vibration alert is produced by a vibration mechanism of the mobile device, an aural alert is produced by a speaker of the mobile device, and/or the like. |
| US09659279B2 |
Method and system for enhanced inferred mode user interface operations
A method and system is provided for the input of user interface commands. Particularly, command initiation events including at least one of: (i) a mouse press event on mouse pointer hardware, and (ii) at least one of a pen touch event, a stylus touch event, and a finger touch event on touch pointer hardware, are accepted. Then gesture stroke input events including at least one of: (i) a mouse drag event on the mouse pointer hardware, and (ii) at least one of a pen drag event, a stylus drag event and a finger drag event on the touch pointer hardware, are accepted. Additionally, command termination events including at least one of (i) a mouse release event on the mouse pointer hardware, and (ii) at least one of a pen lift event, a stylus lift event and a finger lift event on the touch pointer hardware, are accepted. The events are then interpreted as at least one of object selection or digital ink input operations without prior selection of a user input mode. |
| US09659277B2 |
Systems and methods for identifying potentially inaccurate data based on patterns in previous submissions of data
According to some embodiments, a system may receive, from a remote insurance submitter, insurance data submitted via an electronic quoting and submission system in connection with behavioral data associated with the submitter. A processor may then automatically analyze the submitted insurance data based at least in part on information stored in a historic underwriting analytics database and the behavioral data associated with the submitter. Potentially inaccurate insurance data submitted by the insurance submitter may then be identified based on the analysis. According to some embodiments, a plurality of potentially inaccurate insurance data values may be used to flag the submitted insurance data, the insurance submitter, one or more input portions of the electronic quoting and submission system, and/or an insurance class of business. |
| US09659276B2 |
Method and system for socializing events
An example of a method includes determining, electronically, a social network associated with a user in response to the user visiting a web page. Further, the method includes determining, electronically, a first buddy of the user on the social network. Furthermore, the method includes identifying, electronically, a first event from events associated with the first buddy which matches an event associated with the web page. In addition, the method includes displaying the first event and information associated with the first buddy on the web page. |
| US09659273B2 |
System to identify and communicate irregular product types and related methods
Some embodiments include a method. The method can include: identifying a first consumer location of a consumer; identifying a first limited irregular product group associated with the first consumer location; and receiving a selected limited irregular product type of one or more first limited irregular product types. The first limited irregular product group can have the first limited irregular product type(s). Further, an irregular product group can have multiple irregular product types, the multiple irregular product types can have the one or more first limited irregular product types, a master product group can have multiple product types, and the multiple product types can have multiple regular product types and the multiple irregular product types. The multiple irregular product types can satisfy at least one irregularity parameter distinguishing the multiple irregular product types from the multiple regular product types. Other embodiments of related methods and systems are also provided. |
| US09659272B2 |
Method and apparatus for managing product placement on store shelf
A method and apparatus for attending to a supply of product at a position on a store shelf involves receiving an electronic image of the position on a store shelf and comparing the electronic image to a previous electronic image of the position on the store shelf. Depending of the difference, if any, between the two images, generating an indication to attend to the supply of product at the position on the store shelf. |
| US09659270B2 |
Supplemental system for business intelligence systems
In various implementations, a supplemental system may be provided. The supplemental system may be coupled to business intelligence environment(s) to facilitate deployment, version control, testing, and/or other processes. |
| US09659268B2 |
Ticket approval system for and method of performing quality control in field service applications
A ticket approval system and method of performing quality control in a field service application. The method includes obtaining a ticket, performing at least one task associated with the ticket, collecting data associated with at least one task, and transmitting the data to a work management server including database and approval applications. Also provided is a method of reviewing the data received by the approval application for quality control purposes. |
| US09659267B2 |
Cohort cost analysis and workload migration
An approach is provided to analyze data center performance. The approach includes analyzing the data centers, with each of the data centers are represented by a plurality of data center records. Available capacity at each of the data centers is identified based on the selected data center's set of data center records. In addition, a current workload currently being performed by each of the data centers is identified. The approach compares the identified current workload of each data center with the identified available capacity at the other data centers. Data centers are added to a consolidation consideration list in response to the comparisons. The consolidation consideration list is further analyzed to select data centers for consolidation or elimination. |
| US09659263B2 |
Project management notification and updates using family tree
A method and apparatus for automated project management notification using an update family tree. The system utilizes a set of subscription service managers and a set of message processing managers to automatically manage the inter-relationship between a set of systems belonging to different entities within the overall family tree of entities working on a project. Each subscription service manager tracks the other entities interested in the updates and events from the host of the subscription service manager. The message processing managers receive the update events from the subscription service manager and apply a set of host defined rules that govern the automated processing of the received messages. In turn, the entity hosting each message processing manager may have its own set of subscribers that are managed by their respective subscription service manager. |
| US09659261B2 |
User interface for portable device
A user interface for a portable electronic device. In an example implementation, a first screen presents selections for launching applications executable by the portable device, the selections being presented in a plurality of horizontal screen regions, and a second screen presents selections related to stored contacts, these selections also being presented in a plurality of horizontal screen regions. Each of the first and second screens is accessible from the other by actuating a respective tab. A selection on the first screen may include an icon representing an application, and a textual description of the application, and the textual description may be prominent in relation to the icon. Actuating a selection on the second screen may access an individual contact screen that presents a chronological history of communications with the corresponding contact. |
| US09659259B2 |
Latency-efficient multi-stage tagging mechanism
Functionality is described herein for analyzing an input linguistic item, such as a query, in a series of stages. The linguistic item includes one or more candidate items. In a first stage, a brand classifier component determines whether the linguistic item specifies at least one brand, to provide a classifier output result. In a second stage, a tagging component generates a set of tags for at least some of the candidate items in the linguistic item, based, in part, on the classifier output result, to generate a tagging output result. An action-taking component then generates at least one result item based on the tagging output result. Functionality is also described herein for producing the brand classifier component and the tagging component using machine-learning training techniques. The training techniques may include provisions to address the later appearance of new brands that do not appear in a brand dictionary. |
| US09659258B2 |
Generating a training model based on feedback
A method and apparatus for generating a training model based on feedback are provided. The method for generating a training model based on feedback, includes calculating an eigenvector of a sample among a plurality of samples; obtaining scores granted by a user for one or more of the plurality of samples in a round, obtaining scores granted by the user for a first number of samples; obtaining scores granted by the user for a second number of samples in response to detecting, based on the eigenvector, an inconsistency between the scores granted by the user for the first number of samples; and generating a training model based on the scores granted by the user for the first and second numbers of samples. A corresponding apparatus is also provided. |
| US09659255B2 |
Systems, methods, and apparatuses for solving stochastic problems using probability distribution samples
Techniques described herein may be used to solve a stochastic problem by dividing the stochastic problem into multiple fragments. In some cases, each fragment may be related to a random variable that forms a part of the problem, such that each fragment may produce samples from a probability distribution for that variable. Each fragment of the stochastic problem may then be assigned to a configurable circuit to solve the stochastic fragment. Configurable circuits may be implemented using any suitable combination of hardware and/or software, including using stochastic circuitry. In some embodiments, stochastic circuitry may include a stochastic tile and/or a stochastic memory. |
| US09659252B2 |
Method to characterize heterogeneous anisotropic media
A computer-implemented method for determining elastic properties for a heterogeneous anisotropic geological formation is described herein. The method includes grouping sonic velocity data from a borehole section (or borehole sections) into a number of clusters (e.g., one or more clusters). The sonic velocity data is grouped into clusters using petrophysical log data from the borehole section. The method also includes inverting the sonic velocity data for the clusters to determine elastic properties for each cluster. In some cases, the elastic properties for the clusters are combined to determine a relationship between the elastic properties and formation heterogeneity. |
| US09659249B1 |
Pre-programmed resistive cross-point array for neural network
Technical solutions are described for forming a semiconductor device for a crosspoint array that implements a pre-programmed neural network. An example method includes sequentially depositing a semiconducting layer, a top insulating layer, and a shunting layer onto a base insulating layer. The method further includes etching selective portions of the top insulating layer corresponding to resistance values associated with weights of the crossbar that implements the neural network. |
| US09659248B1 |
Machine learning and training a computer-implemented neural network to retrieve semantically equivalent questions using hybrid in-memory representations
Determining semantically equivalent text or questions using hybrid representations based on neural network learning. Weighted bag-of-words and convolutional neural networks (CNN) based distributed vector representations of questions or text may be generated to compute the semantic similarity between questions or text. Weighted bag-of-words and CNN based distributed vector representations may be jointly used to compute the semantic similarity. A pair-wise ranking loss function trains neural network. In one embodiment, the parameters of the system are trained by minimizing a pair-wise ranking loss function over a training set using stochastic gradient descent (SGD). |
| US09659247B2 |
System and method for employing the use of neural networks for the purpose of real-time business intelligence and automation control
A system and integration infrastructure to provide a distributed matrix or neural network of connected real-time decision support modules designed to perform business intelligence evaluations in real time. The system and integration infrastructure provide a network of intelligence superimposed upon any company's existing IT data centers, and cloud computing connections. The system is highly customizable to the unique business model deployed by the client company within the best practices of the client company's industry. Whether or not the client company has integrated their diverse enterprise systems, the elements of the matrix are annealed to the various data sources, transaction logs and client software installations currently deployed. These matrix elements or neurons are designed to house critical operational data, determined by the operational model of the client company to be of critical importance. When combined with monitor neurons, they automatically assess the gap between the desired state of a critical element and the current condition in real time. Trigger conditions are pre-established, but modified by an executive controller in real-time, and the system is pre programmed to automatically respond in a prescribed manner to critical conditions having been met even when these conditions come from otherwise stove-piped enterprise applications. |
| US09659245B1 |
Bar code copy prevention method and device therefor
The present invention relates to a bar code copy prevention method and a device therefor. In detail, when a terminal provides a one-time bar code for an electronic payment, the one-time bar code is provided to a user in a state which a bar code scanner cannot recognize by changing the one-time bar code for the electronic payment, and when the bar code scanner exposes a light source in order to recognize the one-time bar code for the electronic payment, a light source recognition module installed in the terminal recognizes the light source of the bar code scanner, a payment may be performed by recovering an original bar code which the bar code scanner can recognize from the changed bar code, and thus an illegal use of the bar code may be prevented since the payment is not performed using the captured bar code. |
| US09659244B2 |
Custom functional patterns for optical barcodes
Systems and methods for custom functional patterns for optical barcodes are provided. In example embodiments, image data of an image is received from a user device. A candidate shape feature of the image is extracted from the image data. A determination is made that the shape feature satisfies a shape feature rule. In response to the candidate shape feature satisfying the shape feature rule, a custom graphic in the image is identified by comparing the candidate shape feature with a reference shape feature of the custom graphic. In response to identifying the custom graphic, data encoded in a portion of the image is decoded. |
| US09659239B2 |
Machine learning device and classification device for accurately classifying into category to which content belongs
An image acquisition unit of a machine learning device acquires n learning images assigned with labels to be used for categorization (n is a natural number larger than or equal to 2). A feature vector acquisition unit acquires a feature vector representing a feature from each of the n learning images. A vector conversion unit converts the feature vector for each of the n learning images to a similarity feature vector based on a similarity degree between the learning images. A classification condition learning unit learns a classification condition for categorizing the n learning images, based on the similarity feature vector converted by the vector conversion unit and the label assigned to each of the n learning images. A classification unit categorizes unlabeled testing images in accordance with the classification condition learned by the classification condition learning unit. |
| US09659238B2 |
Video object classification
A system comprises an input component, a feature extractor, an object classifier, an adaptation component and a calibration tool. The input component is configured to receive one or more images, and the feature extractor is configured to extract features for one or more objects in the one or more images, the extracted features comprising at least one view-independent feature. The object classifier is configured to classify the one or more objects based at least in part on the extracted features and one or more object classification parameters, and the adaptation component is configured to adjust the classification of at least one of the objects based on one or more contextual parameters. The calibration tool is configured to adjust one or more of the object classification parameters based on likelihoods for characteristics associated with one or more object classes. |
| US09659236B2 |
Semi-supervised method for training multiple pattern recognition and registration tool models
A system and method for training multiple pattern recognition and registration models commences with a first pattern model. The model is trained from multiple images. Composite models can be used to improve robustness or model small differences in appearance of a target region. Composite models combine data from noisy training images showing instances of underlying patterns to build a single model. A pattern recognition and registration model is generated that spans the entire range of appearances of the target pattern in the set of training images. The set of pattern models can be implemented as either separate instances of pattern finding models or as a pattern multi-model. The underlying models can be standard pattern finding models or pattern finding composite models, or a combination of both. |
| US09659234B1 |
Adaptive selection of scale invariant image feature keypoints
Techniques are provided for adaptive selection of feature keypoints of an image. An example system may include a contrast statistics calculation circuit configured to generate contrast measurements of regions of the image associated with each of the feature keypoints, and to calculate a mean and variance of the contrast measurements. The system may also include an edge statistics calculation circuit configured to generate ratios of principal curvatures of regions of the image associated with each of the feature keypoints, and to calculate a mean and variance of the ratios of principal curvatures. The system may further include a threshold calculation circuit configured to calculate thresholds based on the mean and variance of the contrast measurements and on the mean and variance of the ratios of principal curvatures; and a keypoint filter circuit configured to filter the set of feature keypoints based on the those thresholds. |
| US09659228B2 |
Image processing apparatus, image processing system, non-transitory computer readable medium, and image processing method
An image processing apparatus includes an image information obtaining unit that obtains image information regarding a process target image on which image processing for adjusting an impression of an image to that of a sample image is performed, and image information regarding the sample image, a feature value extraction unit that extracts feature values of the process target image and those of the sample image, an image adjustment unit that adjusts the feature values of the process target image to those of the sample image, and an image display unit that temporarily displays, on the process target image, an image obtained by adjusting the feature values of the process target image to those of the sample image, within a predetermined area in response to a first operation, and thereafter displays an entire image obtained after image processing in response to a second operation. |
| US09659225B2 |
Restaurant-specific food logging from images
A “Food Logger” provides various approaches for learning or training one or more image-based models (referred to herein as “meal models”) of nutritional content of meals. This training is based on one or more datasets of images of meals in combination with “meal features” that describe various parameters of the meal. Examples of meal features include, but are not limited to, food type, meal contents, portion size, nutritional content (e.g., calories, vitamins, minerals, carbohydrates, protein, salt, etc.), food source (e.g., specific restaurants or restaurant chains, grocery stores, particular pre-packaged foods, school meals, meals prepared at home, etc.). Given the trained models, the Food Logger automatically provides estimates of nutritional information based on automated recognition of new images of meals provided by (or for) the user. This nutritional information is then used to enable a wide range of user-centric interactions relating to food consumed by individual users. |
| US09659224B1 |
Merging optical character recognized text from frames of image data
Disclosed are techniques for merging optical character recognized (OCR'd) text from frames of image data. In some implementations, a device sends frames of image data to a server, where each frame includes at least a portion of a captured textual item. The server performs optical character recognition (OCR) on the image data of each frame. When OCR'd text from respective frames is returned to the device from the server, the device can perform matching operations on the text, for instance, using bounding boxes and/or edit distance processing. The device can merge any identified matches of OCR'd text from different frames. The device can then display the merged text with any corrections. |
| US09659221B2 |
Video stream evaluation
The invention relates to a method for recognizing activities detected in video streams. In this case, it is intended that data relating to frame differences are accumulated for frame sequences in fields, gradients and/or value difference intervals are determined in the accumulator fields, and activity is concluded from the gradients. |
| US09659218B1 |
Predicting video start times for maximizing user engagement
Implementations disclose predicting video start times for maximizing user engagement. A method includes applying a machine-learned model to audio-visual content features of segments of a target content item, the machine-learned model trained based on user interaction signals and audio-visual content features of a training set of content item segments, calculating, based on applying the machine-learned model, a salience score for each of the segments of the target content item, and selecting, based on the calculated salience scores, one of the segments of the target content item as a starting point for playback of the target content item. |
| US09659215B2 |
Raster image processing method
A raster image processing method and a raster image processor validate content objects in a document based on similarity, especially on continuity, to convert the similar objects with one or more same parameters of an image manipulation method to achieve a correct reproduction of the document. |
| US09659212B2 |
Methods, systems, and products for gesture-activation
Methods, systems, and products recognize a gesture in a video signal. A camera generates the video signal as an output. An image comparison is then performed between frames in the video signal to images stored in memory of different gestures. When a frame matches an image, the gesture is determined. A corresponding controller operation may then be selected. |
| US09659210B1 |
System and method for detecting and tracking facial features in images
The present invention relates to a system for detecting and tracking facial features in images and can be used in conjunction with a camera. Given a camera, the system will detect facial landmarks in images. The present invention includes software for real time, accurate facial feature detection and tracking in unconstrained images and videos. The present invention is better, more robust and faster than existing approaches and can be implemented very efficiently allowing real-time processing, even on low-power devices, such as mobile phones. |
| US09659209B2 |
Electronic device including blurred finger image deblurring circuitry and related methods
An electronic device may include a finger biometric sensor that may include an array of electric field sensing pixels and image data output circuitry coupled thereto. The electronic device may also include a dielectric layer over the array of electric field sensing pixels and causing electric field diffusion so that the image data output circuitry generates image data corresponding to a blurred finger image. The electronic device may also include deblurring circuitry coupled to the image data output circuitry and capable of processing the image data to produce processed image data representative of a deblurred finger image. |
| US09659208B2 |
Biometric image sensing
An novel sensor is provided having a plurality of substantially parallel drive lines configured to transmit a signal into a surface of a proximally located object, and also a plurality of substantially parallel pickup lines oriented proximate the drive lines and electrically separated from the pickup lines to form intrinsic electrode pairs that are impedance sensitive at each of the drive and pickup proximal locations. |
| US09659196B2 |
Method, apparatus and system for verifying data
A method for data verification may include: receiving by a radio frequency identification (RFID) tag a write command including data to be written; writing by said RFID tag said data to be written into a local storage; reading by said RFID tag data from said local storage; and carrying out by said RFID tag a data verification according to said data read out. Further, a data verification apparatus may include a receiving module for receiving a write command including data to be written; a writing module for writing said data to be written into a first storage module configured for storing said data to be written; a reading module for reading data from said first storage module; and a verifying module for carrying out verification according to the data read out by said reading module. Such method and apparatus may reduce the time of data verification by an RFID tag. |
| US09659194B2 |
Dividing tagged items into subsets
A method and system for dividing a set of tagged items into subsets. Each tagged item is tagged with a passive RFID tag. A RFID reader is instructed to poll the RFID tags of all tagged items in a specified region having fixed boundaries to generate information including, for each tagged item, a spatial location of each tagged item and a list of all other tagged items in the region which are adjacent to each tagged item. The region is split into non-overlapping subregions. For each subregion, a central tagged item having more adjacent tagged items in each subregion than any other tagged item in each subregion is determined, utilizing the generated information. A virtual boundary is outlined around the central tagged item to enclose the central tagged item and a portion of the tagged items in each subregion which are adjacent to the central tagged item. |
| US09659184B2 |
Multi-identity graphical user interface for secure file sharing
In the approaches described herein, a data file storage service may control access to file system objects using corresponding “personal” or organization-related “work” identity information which may include encryption keys or passwords. To assist the user with identifying respective file system objects, the user is presented with a corresponding graphical user interface (GUI) which displays a corresponding personal or work identity icon next to a visual rendering of the file system objects. Keys that control access to work identity files and folders are purged from a local key store as soon as user authorization changes are detected. In this way, even a user who originated a data file will not be able to decrypt files stored in a folder shared using a work identity once that identity is canceled by the organization, while at the same time, the user's access to their personal files may continue. |
| US09659183B2 |
Pattern for secure store
A computer system, computer product, and method for accessing a secure store, which includes receiving a request to access a secure store, checking the file path of the request to make sure it exists in the secure store, verifying security parameters from the process at the file system filter layer, saving the PID of the process by the file system filter layer, comparing the saved PID to the process's PID, and allowing the process to access the path in the secure store specified in the request. |
| US09659182B1 |
Systems and methods for protecting data files
A method for protecting data files may include (1) identifying a data file to be protected against data loss, (2) identifying a set of software programs permitted to open the data file by (a) identifying a format of the data file and (b) identifying at least one software program capable of opening files of the format of the data file, (3) detecting an attempt to open the data file by a software program not included in the set of software programs, and (4) performing a security action in response to detecting the attempt to open the data file. Various other methods, systems, and computer-readable media are also disclosed. |
| US09659181B2 |
System, apparatus and method for license key permutation
A system and method of dynamically altering the encoding, structure or other attribute of a cryptographic key, typically a license activation key, to render useless keys that have been created by illegal key generation “cracks”. An encoding/decoding engine provides a plurality of key obfuscation algorithms that may alter the structure, encoding or any other attribute of a given key. A changeable combination code is supplied to the encoding/decoding engine that specifies a subset of the algorithms to apply during the encoding or decoding phase. The encoding engine is used during key generation and the decoding engine used during key usage. The same combination code must be used during decoding as was used during encoding to recover the original key or a valid key will not be recovered. Thus, a system can be rapidly re-keyed by selecting a new combination of encoding/decoding algorithms. The selection of algorithms comprises a combination code. The new combination code will result in keys that are incompatible with any existing illegal key generators. |
| US09659180B2 |
Personalized website theme
A personalized website theme for a website is received. The personalized website theme is distinct from a standard theme of the website. Further, a set of data is sent to the computing device. The set of data includes an indicium indicating the personalized website theme so that the computing device displays the website according to the personalized website theme at least prior to a request for identifying data associated with access to an account on the website. |
| US09659178B1 |
Device blanking
A method and apparatus is disclosed for protecting electronic devices from security breaches (e.g., in the form of DPA attacks) by managing input/output (I/O) pin states. The technique is particularly useful in financial applications in which data security related operations, such as those involving cryptography, are performed by payment card readers, and the power supplied to drive the operations are measured and analyzed by attackers to extract sensitive information. The technique prevents any external device from measuring the operation power by disabling the I/O pins. The I/O pins are set to a logic low at any given time a data security related operation is performed. As a result, no communication with the external environment is possible during the data security operation, and external power measurements by DPAs are prevented. |
| US09659174B2 |
Apparatus, system, and method for protecting against keylogging malware and anti-phishing
An apparatus, system, and method is disclosed for protecting against key logger malware. The protection includes protection form grabbing keylogger malware. In response to detecting a form submission event from a browser associated with a user entering data into a form, confidential data is cleared to prevent it being captured by malware. Additional protection of data inputs, entered at a driver level, may be provided as an additional level of protection against hook based malware operating at a virtual keyboard level or operating system level. Data inputs received at a physical driver level may be protected as they pass through a virtual keyboard level and an operating system level. The projection against malware may be provided as a preventive measure that does not require detection of the key logger malware itself. |
| US09659170B2 |
Securing data on untrusted devices
One example method for securing data on untrusted devices includes the steps of identifying, by a first process, a command in a command queue, the command from a second process and comprising an action on secure data; determining whether the command is permitted based on the action and a user credential; and responsive to determining the command is not permitted, removing, by the first process, the command from the command queue. |
| US09659165B2 |
Method and apparatus for accessing corporate data from a mobile device
A computer-implemented communication method performed by a computerized device and a computerized communication apparatus, the method comprising: receiving by a buffer server a first communication request and a device key from a mobile device; verifying the device key and a buffer server key; sending a request with details associated with the device key and the buffer server key, to a corporate server; receiving a response from the corporate server; removing data from the response, and sending a reduced response to the mobile device; receiving a user identification and a second communication request from the mobile device, for the data that has been removed; and sending the data that has been removed to the mobile device, upon verifying the user identification. |
| US09659164B2 |
Method and apparatus for using a multi-factor password or a dynamic password for enhanced security on a device
Techniques for improving security on a device are disclosed. In an aspect, a multi-factor password comprising a plurality of factors may be used to improve security. Each factor may correspond to a different type of information that may be used for authentication and/or other purposes. For example, the plurality of factors may include an alpha-numeric string, a fingerprint of a user, a voice clip, a picture, a video, etc. The device may authenticate the user based on the multi-factor password. In another aspect, a dynamic password that varies with at least one parameter (e.g., time, location, etc.) may be used to improve security. The dynamic password may have a plurality of values for a plurality of scenarios defined by at least one parameter. The device may authenticate a user in a given scenario based on a value of the dynamic password applicable for that scenario. |
| US09659157B2 |
Systems and methods for watermarking software and other media
Systems and methods are disclosed for embedding information in software and/or other electronic content such that the information is difficult for an unauthorized party to detect, remove, insert, forge, and/or corrupt. The embedded information can be used to protect electronic content by identifying the content's source, thus enabling unauthorized copies or derivatives to be reliably traced, and thus facilitating effective legal recourse by the content owner. Systems and methods are also disclosed for protecting, detecting, removing, and decoding information embedded in electronic content, and for using the embedded information to protect software or other media from unauthorized analysis, attack, and/or modification. |
| US09659155B2 |
System and method for software activation and license tracking
System and method for software activation and further tracking of its states on an end-user computing device (computer) was developed to provide software developers a flexible and secure tool for software distribution and gathering statistics of usage of software activation. The method consists of the following logical steps: (a) obtaining an acquisition confirmation; (b) requesting for a license; (c) issuing and delivering the license to End User; (d) verification of license on the User's computer; (e) storing the license on the User's computer; (f) periodic tracking of activation state, (g) another action with the User's license. |
| US09659152B2 |
Computer-implemented technique for defining a bone cut
A technique for generating a data set that geometrically defines a bone cut configuration for transverse maxillary distraction is using a computer-implemented method. An aspect of the technique comprises creating a numeric model of a maxilla based on patient-specific data of the maxilla. The numeric model is representative of mechanical properties of the maxilla. Based on the numeric model thus generated, one or more cut configurations for one or more bone cuts on at least one of a left hand side and a right hand side of the maxilla are determined. Each cut configuration has been determined to compensate for asymmetric mechanical properties of the maxilla. In a further step, a data set indicative of the one or more cut configurations thus determined is generated. The data set may be used to create a surgical template or jig, for computer-assisted surgery or a surgical navigation system. |
| US09659151B2 |
Systems and methods for treatment target deconvolution
Deconvolution systems and methods based on cornea smoothing can be used to obtain an ablation target or treatment shape that does not induce significant high-order aberrations such as spherical aberration. Exemplary ablation targets or treatment shapes can provide a post-operative spherical aberration that is equal to or below a naturally occurring amount of spherical aberration. |
| US09659148B2 |
Caregiver rounding communication system
An information technology system for a healthcare facility is provided. The system includes a first computer device to keep track of rounding intervals for caregivers and to determine whether the caregivers successfully complete their rounds in a timely manner for their assigned patients. The system also has a real time locating system (RTLS) that tracks locations of the plurality of caregivers and that is in communication with the first computer device. The system further has a number of graphical displays in communication with the first computer device. Each graphical display is operable to display a list of patients for whom rounds are due and to display reminder messages to the plurality of caregivers relating to rounding. |
| US09659146B2 |
Method for quantitative analysis of complex proteomic data
This invention is a novel method for analysis of data that is produced by test equipment. The preferred embodiment is data produced by liquid chromatography tandem mass spectrometry (LC-MS/MS) equipment, using industry standard methods to generate the initial data from the test equipment. The invention is a method for processing of the data to promptly produce accurate, reliable, and meaningful data that can be used for critical decisions. The unique benefit of the method is to correct the multiple measurement and calculation errors that are inherent in the operation of laboratory equipment. Prior methods result in errors based on circumstances that are difficult to control, accuracy-related errors in machine measurements, and fundamental mathematical errors in the data processing software that is used with the laboratory equipment. As an added benefit, this novel method allows comprehensive simultaneous measurement and calculation of correlation of any and all peptide pairs in a single measurement, with the capability to support repeated measurements with changed conditions over time. This novel method allows robust, detailed, and comprehensive measurements of peptide activity and function, which results in substantial improvements over prior methods in accuracy, reliability, and efficiency. |
| US09659143B2 |
Method for analyzing the robustness of components within a vehicular mechanical system to calculate out-of-specification robustness
A method for increasing the robustness of a mechanism for a vehicle including the steps of determining a primary function of the mechanism, identifying components of the mechanism used during the primary function, analyzing each component under in-specification conditions, analyzing each component under decreasing out-of-specification conditions during performance of the primary function to determine a lower failure value for each component, analyzing each component during performance of the primary function under increasing out-of-specification conditions to determine an upper failure value for each component, determining a modified robustness value for each component, wherein the modified robustness value is between the lower and upper failure values and modifying each component in the vehicular mechanism to have a robustness that is approximately the modified robustness value of the respective component. |
| US09659141B2 |
EDA tool and method for conflict detection during multi-patterning lithography
A method includes accessing data representing a layout of a layer of an integrated circuit (IC) having a plurality of polygons defining circuit patterns to be divided among a number (N) of photomasks over a single layer of a semiconductor substrate, where N is greater than two. The method further includes inputting a conflict graph having a plurality of vertices, identifying a first and second vertex, each of which is connected to a third and fourth vertex where the third and fourth vertices are connected to a same edge of a conflict graph, and merging the first and second vertices to form a reduced graph. The method further includes detecting at least one or more vertex in the reduced having a conflict. In one aspect, the method resolves the detected conflict by performing one of pattern shifting, stitch inserting, or re-routing. |
| US09659139B2 |
Approach for performing improved timing analysis with improved accuracy
One embodiment of the present invention includes a method for updating timing parameters after a circuit design change. The method includes, prior to the circuit design change, deriving a value for a first timing parameter based on a signoff timing analysis of a timing arc, and a value for a second timing parameter based on a quick timing analysis of the timing arc; and obtaining a first transition time based on the quick timing analysis. The method further includes, after the circuit design change, deriving a value for a third timing parameter based on the quick timing analysis, obtaining a second transition time based on the quick timing analysis, and deriving a fourth value for a fourth parameter based on the quick timing analysis, wherein the fourth parameter is based on the first, second, and third parameters and on the first and second transition times. |
| US09659138B1 |
Methods, systems, and computer program product for a bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic techniques
Disclosed are techniques for implementing parallel fills for bottom-up electronic design implementation flow and track pattern definition for multiple-patterning lithographic processing. These techniques identify a canvas in a layout and design rules for track patterns and multiple-patterning, where the canvas is not yet associated with any base track patterns. A first shape having the first width is inserted along a first track in the canvas based on the design rules. A custom, legal track pattern is generated by arranging multiple tracks in an order and further by associating the first width with the first track in the custom, legal track pattern. The layout may then be further modified by guiding the insertion of one or more additional shapes with the custom, legal track pattern. |
| US09659136B2 |
Suspect logical region synthesis from device design and test information
Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region. |
| US09659135B2 |
Logic structure aware circuit routing
A method, executed by a computer, for routing a circuit includes receiving a logic structure for a circuit, retrieving a logic template, determining whether the logic structure for the circuit matches the logic template, and routing the circuit using a routing recipe corresponding to the logic template in response to determining that the logic structure matches the logic template. A corresponding computer program product and computer system are also disclosed herein. |
| US09659134B2 |
Computing device and method for determining wiring paths on printed circuit board
A printed circuit board (PCB) layout method executed in a computing device obtains pins of a first electronic component that are connected to a second electronic component or third electronic components included in a T topology circuit. A model of the first electronic component is created according to the obtained pins and is modified to form extended nets of the first electronic component. Pin pairs and match groups are set. Wiring paths of the T topology circuit are determined according to the match groups. The wiring paths are output to an output device. |
| US09659132B2 |
Method of generating a target layout on the basis of a source layout
Generating a target layout of an integrated circuit includes providing a source layout comprising one or more source pcells having one or more shapes; providing a set of connectivity constraints for connecting each shape of each source pcell to none, one, or more other components of the integrated circuit; for each shape of each source pcell, determining a corresponding target shape having a contour composed of edges with defined lengths, inserting none, one, or more edges into the contour of the shape, or into the contour of the corresponding target shape, determining a corresponding edge of the corresponding target shape; for each edge, defining an edge length constraint for constraining the edge to have the length of the edge of the corresponding target shape; applying a legalization procedure to the source layout based on the connectivity constraints, the target design constraints, and the edge length constraints. |
| US09659130B2 |
Layout design system for generating layout design of semiconductor device
According to example embodiments, a layout design system includes a processor, a storage module configured to store a standard cell design, and a generation module. The standard cell design includes an active area and a normal gate area on the active area. The generation module is configured to receive the standard cell design, to adjust a width of an active cut design crossing the active area of the standard cell design, and to output a chip design including a design element using the processor. The design element includes the active cut design having the width adjusted. |
| US09659129B2 |
Standard cell having cell height being non-integral multiple of nominal minimum pitch
An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch. |
| US09659128B2 |
Semiconductor overlay production system and method
Disclosed herein is a system and method for producing semiconductor devices using overlays, the method comprising associating one or more patterned overlays with respective ones of reserved regions in a layer template, receiving a layer design based on the layer template, identifying the reserved regions in the layer design, generating a production layer design based on the layer design, the production layer design describing at least one production overlay in one of the reserved regions, and fabricating one or more devices based on the production layer design. |
| US09659127B2 |
Electronic apparatus, method of optimizing de-coupling capacitor and computer-readable recording medium
An electronic apparatus includes a user interface to receive an input selecting a plurality of circuit devices, a storage to store electrical current information and a Scattering parameter regarding input/output ports of the plurality of circuit devices, respectively, a calculator to calculate impedance per number of de-coupling capacitors based on the stared S-parameters and to calculate an accumulated noise value per number of the decoupling capacitors based on the calculated impedance and the electrical current information, and a controller to determine a number of the de-coupling capacitors based on the calculated accumulated noise values and to control the user interface to display the determined number of the de-coupling capacitors. |
| US09659124B2 |
Transport network
Some embodiments provide a method of monitoring the implementation of a user design in a configurable integrated circuit (IC). The method receives a user design for an IC and optimizes the user design to produce a second IC design. The optimization results in the elimination of circuit element(s). The method defines the second IC design for the configurable IC and generates output data for the eliminated circuit element(s) to allow for monitoring the user design. |
| US09659121B1 |
Deterministic and statistical timing modeling for differential circuits
A computer program product for improved modeling of differential circuits is provided. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and executable by a processing circuit to cause the processing circuit to represent a configuration of a differential circuit on a defined space with representations of single-ended inputs and outputs disposed as differential input and output pairs along borders of the defined space, respectively, for each differential input and output pair, introduce an internal input or output differential node to feed from or to feed a corresponding differential input or output pair within the borders, respectively, with the internal input and output differential nodes being connectable and perform timing calculations with respect to input and output differential nodes. |
| US09659116B2 |
Method for designing containers
A method comprises steps of: providing an initial package design, providing an initial package-handling element design, modeling the interaction of the package and the package-handling element, and altering one of the package design or the package-handling element design according to the results of the model. Wherein the initial package-handling element design comprises at least one item selected from the group consisting of: a motion transfer component comprising a combination of discrete geometrically defined elements, package guide rails, package guide rail supports, vacuum conveying components, and combinations thereof. And wherein the interaction reflects the package interaction with the discrete elements of a multi-element motion transfer component or the package guide rails having a flexibility greater than zero, or package guide rail supports having a finite stiffness, or a combination thereof. |
| US09659109B2 |
System and method for query auto-completion using a data structure with trie and ternary query nodes
A method of providing predictive search query recommendations for a search query. The method can be implemented via execution of computer instructions configured to run at one or more processing modules and configured to be stored at one or more non-transitory memory storage modules. The method can include receiving the search query from a user. The method also can include determining the predictive search query recommendations for the search query using a tree data structure. At least one top layer of the tree data structure can include at least one trie query node and bottom layers of the tree data structure can include ternary tree query nodes. The method further can include sending the predictive search query recommendations to the user. Other embodiments of related systems and methods are also disclosed. |
| US09659104B2 |
Link association analysis systems and methods
Link association analysis systems are presented. Disclosed systems are configured to analyze links created by users and to determine possible reasons underpinning why a user would create such a link. The system derives such reasons by analyzing the context within which the link was created and to which the link points, and then presents the reasons as a data object to users for feedback. The system can be made to be self-refining by collecting survey data regarding its accuracy, so that the more users interact with the system, the more accurate the system is at deriving reasons for link creation. |
| US09659102B1 |
Event application
The present invention includes systems and methods for providing event information. A one-time use app is downloaded to a user device when a user elects to purchase the app. The app receives event-related information from an event database. The event database receives information from a plurality of sources. The sources are each associated with an application programming interface. The app provides event-related information to the user through purchased options. The app can filter information based on a user profile before providing the information to the user. |
| US09659096B2 |
Consumable data management
The present invention relates to methods, devices and systems for associating consumable data with an assay consumable used in a biological assay. Provided are assay systems and associated consumables, wherein the assay system adjusts one or more steps of an assay protocol based on consumable data specific for that consumable. Various types of consumable data are described, as well as methods of using such information in the conduct of an assay by an assay system. |
| US09659095B2 |
Managing search-engine-optimization content in web pages
A method for managing the Search Engine Optimization (SEO) content of web pages is disclosed. In one embodiment, such a method includes providing a set of web pages organized in a hierarchical structure. Each web page has an SEO content pattern associated therewith. The method establishes an inheritance scheme for the hierarchical structure such that the SEO content patterns of parent web pages are inherited by children web pages. The method further enables a user to override the inheritance scheme for selected web pages such that the SEO content patterns of the selected web pages override the SEO content patterns of their respective parent web pages. A corresponding apparatus and computer program product are also disclosed. |
| US09659093B1 |
Adaptive recommendations of user-generated mediasets
This disclosure relates to adaptive recommendations for user-generated mediasets. A mediaset component provides for users to generate mediasets. A user-generated mediaset can include a user-generated playlist or a user-generated media channel. A monitoring component monitors consumption of media, e.g., by a consumer. A relatedness component determines a set of the user-generated mediasets that are related to the media consumed by the consumer. A recommendation component recommends a subset of the user-generated mediasets based on a set of criteria. A rights management component determines a set of authorizations of the consumer for respective media content associated with the set of user-generated mediasets, and takes at least one action based on the set of authorizations, e.g., updating one of the mediasets based on the set of authorizations. |
| US09659089B2 |
Prioritizing work and personal items from various data sources using a user profile
A method, system and computer program product for managing work and personal items. Information is received from a user to populate a user profile providing rules to determine a priority for work and personal items to be addressed by the user. Work and personal data sources (e.g., e-mails, social media) are monitored. The content in these monitored data sources are scanned and analyzed for work and personal items to be addressed by the user. These work and personal items are then presented to the user in a prioritized order based on the rules in the user profile. In this manner, the user is able to effectively manage the various work and personal items from various data sources by receiving a prioritized list of work and personal items that need to be addressed based on various factors that the user deems to be important as provided in the user's profile. |
| US09659086B1 |
Foreign organization name matching
Embodiments include a system, method, and computer program product for foreign organization name matching. Aspects include receiving a first entity name from a first database configured in a first language and receiving a second database, wherein the second database includes a plurality of entity names in a second language, wherein the first and second languages are different. Aspects also include performing an Internet search based on the first entity name, wherein a language setting of the Internet search is configured to the second language and identifying a list of candidate names based on a set of results from the Internet search. Another aspect includes filtering the list to obtain a resulting candidate name and determining whether the resulting candidate name matches one of the entity names in the second database. Aspects include associating the first entity name and a matching entity name in the second database based on the determination. |
| US09659084B1 |
System, methods, and user interface for presenting information from unstructured data
A system, methods, and user interface for extracting information from unstructured data sources and presenting such information in a structured or semi-structured format for better information search and utilization, and can be applied to replace the conventional methods of displaying search results. The methods identify terms representing topics and related comments in various types of text contents including documents and Web pages, and extract such terms and present them in a form of a topic-comment or object-properties hierarchy, including a heading+list format and heading+cloud or group format. Methods and interface object are provided to make a file object a non-terminal node in a computer file system, with information extracted from the file content displayed as deeper levels of the file system hierarchy. Methods for displaying information extracted from unstructured document contents in terms of class-members and topic-attributes are also disclosed. |
| US09659081B1 |
Independent data processing environments within a big data cluster system
A cluster system includes an interface and a processor. The interface is to receive a request from a user associated with one of a plurality of shells. The processor is to determine a plurality of tasks to respond to the request; determine a local set of data and a shared set of data for a task of the plurality of tasks, wherein the local set of data is associated with the one of the plurality of shells; and provide the task, a local set indication, and a shared set indication to a worker associated with the task, wherein the local set indication refers to the local set of data and the shared set indication refers to the shared set of data. |
| US09659075B2 |
Providing high availability in an active/active appliance cluster
A method executes a preempt by a standby database appliance in a high-availability active/active appliance cluster. The appliance cluster includes a transaction processing standby group and a persistent storing standby group. The transaction processing standby group includes a primary active appliance and a standby appliance. One or more processors receive a Hello message from the primary DB appliance. The processor(s) examine a priority field in the Hello message, in order to determine a priority of the standby database appliance according to the persistent state to thereby determine whether the standby database appliance requests a preempt, where the persistent state includes a state of an application and a database of the primary DB appliance. The processor(s) implement a failover in response to the preempt request to thereby take over a duty of the primary DB appliance. |
| US09659068B1 |
Methods and systems for providing media recommendations based on implicit user behavior
Methods and systems for providing media recommendations based on implicit user behavior are described herein. In one aspect, a server system provides a first media item for playback based on a request from an application executing on an electronic device. Data associated with a behavior of a first user of the content service is received. The received data and the behavior implicitly correspond to the playback of the first media item and do not correspond to an explicit user input to the application for controlling playback of or providing feedback for the first media item. The server system uses the received data to provide a media recommendation to the electronic device. |
| US09659066B2 |
Dynamic interest-based notifications
Providing dynamic, interest-based change notifications includes detecting an event for an artifact managed by a collaborative system, determining a user subscribed to the artifact, and, responsive to the event, calculating a score for the event using a processor. The score is user-specific and indicates a level of interest of the user for the event. The score is compared with a threshold score. A change notification of the event is sent to the user responsive to determining that the score exceeds the threshold score. |
| US09659065B1 |
Ranking search results based on current or past presences
Systems, methods, and computer-readable media for ranking search results based on current and past presences of a user and a user's contacts from a social graph in accordance with an embodiment of the present invention. A search query is received from a user and search results responsive to the search query are obtained from a search engine. Contacts from a user's social graph are obtained, and presence data for the user and the contacts is obtained. The relevancy scores of the search result entities are modified based on the current presence of a contact at an entity, the past presence of a contact at an entity, and the past presence of the user at an entity. The search results are ranked based on the modified relevancy scores and provided to the user. |
| US09659064B1 |
Obtaining authoritative search results
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for obtaining authoritative search results. One of the methods includes receiving a first search query. First search results responsive to the first search query are obtained. Based on the first search query or the first search results, an authoritative search result that identifies a resource on a site that is authoritative for the first search query is obtained. A ranking of the authoritative search result and the one or more first search results is generated, and the ranking of the authoritative search result and the one or more first search results is provided in response to the first search query. |
| US09659062B1 |
Apparatuses, methods and systems for a global benefits purse facilitator
The APPARATUSES, METHODS AND SYSTEMS FOR A GLOBAL BENEFITS PURSE FACILITATOR (hereinafter “GBPF”) implement efficient and scalable monitoring, regulation, and allocation of computational processing, data, labor, and/or the like resources within an enterprise. The GBPF may facilitate the provision of tailored benefits packages to employees within an enterprise, where employees may be provided with a purse allowance and a selectable list of benefits on which that allowance may be spent. The GBPF may be configured to receive benefits selections, to deduct corresponding costs from the employee purse, and to facilitate the generation of a benefits package based on the employee selections. The GBPF may further be configured to enforce regulations, rules, company policies, and/or the like with regard to benefits. |
| US09659060B2 |
Enhancing performance-cost ratio of a primary storage adaptive data reduction system
Data reduction in a storage system comprises determining attributes of data for storage in the storage system and determining expected data reduction effectiveness for the data based on said attributes. Said effectiveness indicates the benefit that data reduction is expected to provide for the data based on said attributes. The data reduction further comprises applying data reduction to the data based on the expected data reduction effectiveness and performance impact, to improve resource usage efficiency. |
| US09659059B2 |
Matching large sets of words
Word phrases are stored in a phrase structure. Each word is stored as a keyword in a keyword structure. Each keyword is associated with usage attributes identifying use of a word in a word phrase. Any preceding words associated with a keyword, and a mapping from any preceding words to a word phrase, is stored for each word. A word string is input. Match attributes are updated in a match structure if a word in the word string matches any keyword and if any preceding words associated with any matching keyword includes a preceding word which precedes the word in the word string. The match attributes indicate use of the matching word in the word string and in a word phrase. Whether a word phrase is present in the word string is determined based on the usage attributes and the match attributes associated with multiple matching words. |
| US09659055B2 |
Structured searching of dynamic structured document corpuses
A system includes a document corpus containing structured documents, which contain both text and annotations of the text. The system also includes a search engine which is adapted to perform structured searches of the structured documents. As new types of annotations are added to the system, the search engine is updated automatically to become capable of performing structured searches for the new types of annotations. For example, if a new natural language processing (NLP) component, adapted to generate annotations of a new type, is added to the system, then the system automatically updates a query language to include a definition of the new type of annotation. The search engine may then immediately be capable of processing structured queries which refer to the new type of annotation. |
| US09659054B2 |
Database browsing system and method
A computer-implemented system and method for creating a user-defined database interface. An Orbit Form module processes a call comprising an identifier for the database, a target data object (database table), approach filters (table fields), and results lines (table fields). Approach filters may support comparable data types, and results lines may support both comparable and non-comparable data types. The call may optionally include parameters that the Orbit Form module uses to govern retrieval of data from the target database, presentation of filter values, and/or formatting of results pages. After testing the call constructs, the Orbit Form module generates Approach boxes (corresponding to the approach filters) that a user employs to enter target input values to compare to records in the database. Record matches result in retrieval and user-specified display of data corresponding to the results lines (DaPs). A selectable view image field in a DaP extracts and displays image file data. |
| US09659052B1 |
Data object resolver
A system and method to recognize and resolve when a source data object is the same or similar to an existing data object in a database using structured information and facts about each object. The system and method compare relations of the source data object and relations of the existing data object in the database and determine how similar the source data object is to the data object in the database based on scores of the comparisons. The system and method may provide outputs, such as whether the data objects match, the data objects are distinct, the source data object is a strong match to multiple data objects in the database, and the data objects conflict one another. The system and method may then resolve the database entries based on the potential matching outputs. |
| US09659051B2 |
Enforcing referential integrity for object data documents
A metadata framework helps enforce referential integrity in object data documents. In one general aspect, a method includes generating a first data definition language statement, based on a class defined in a metadata framework, that creates a table in a relational database system to store an object data document. The table may include at least one column that corresponds to an identifying attribute in the object data document, at least one column that corresponds to a relationship attribute in the object data document, and a column that stores the object data document. The method may also include generating a second data definition language statement, based on the referential integrity metadata framework, that creates a foreign key constraint on the at least one column that corresponds to the relationship attribute when the relationship is not polymorphic, and issuing the first data definition language statement and the second data definition language statement. |
| US09659050B2 |
Delta store giving row-level versioning semantics to a non-row-level versioning underlying store
A delta store giving row-level versioning semantics to a non-row-level versioning underlying store is described. An example method includes establishing a column-based in-memory database including a main store and a delta store, where the main store does not allow concurrent transactions on a same table and the delta store has a plurality of row-visibility bitmaps implementing a row-level versioning mechanism that allows concurrent transactions on the same table. A transaction associated with the column-based in-memory database is received. For each table read by the transaction, a version of the table in the delta store that represents a transaction-consistent snapshot of the database visible to the transaction is determined. Each table is represented in the main store and the delta store; and each version of the table is represented by one or more bitmaps. Upon execution of a DML as part of the transaction, for each table written by the transaction, the data changes generated by the transaction is recorded in the one or more bitmaps that represent a private version of the table. Upon commit of the transaction, for each table written by the transaction, a new public version of the table is generated based on the private version of the table, and the public version represents a new transaction-consistent snapshot of the database visible to subsequent transactions. |
| US09659048B2 |
Key-Value data storage system
According to an aspect, a key-value store (KVS) system includes a data management unit that stores a data KVS storing a pair of a data KVS key including information on a storage location of application data to be an access target object and the application data; and a key KVS storing a pair of an application key and the data KVS key. The data KVS includes a normal partition in which a size of a record for storing one pair is a predetermined specific size; and a special partition in which the size of the record for storing one pair is a size set according to a data size of the pair to be stored. A data relocation unit relocates a pair of a relocation target object to the special partition having the record size suitable for the data size of the pair. |
| US09659045B2 |
Generic indexing for efficiently supporting ad-hoc query over hierarchically marked-up data
Hierarchical data objects are indexed using an index referred to herein as a hierarchy-value index. A hierarchy-value index has, as index keys, tokens (tag name, a word in node string value) that are extracted from hierarchical data objects. Each token is mapped to the locations that correspond to the data for the token in hierarchical data objects. A token can represent a non-leaf node, such as an XML element or a JSON field. A location can be a region covering and subsuming child nodes. For a token that represents a non-leaf node, a location to which the token is mapped contains the location of any token corresponding to a descendant node of the non-leaf node. Thus, token containment based on the locations of tokens within a hierarchical data object may be used to determine containment relationships between nodes in a hierarchical data object. |
| US09659043B2 |
Data system and method
A system and method for content sharing includes acquiring, by a processing device, a plurality of data objects from data sources, storing the plurality of data objects in a data warehouse, generating a high-level index that is shared by the plurality of data objects, generating a plurality of low-level indices that each provides a respective low-level index for a respective one of the plurality of data objects, and providing the plurality of data objects on the content sharing platform for query or search using the high-level index and the plurality of low-level indices. |
| US09659042B2 |
Data lineage tracking
A data lineage tracking system may include a memory storing a module comprising machine readable instructions to obtain trace log entries representing an interaction with, a manipulation of, and/or a creation of a data value. The data lineage tracking system may further include machine readable instructions to select the trace log entries that are associated with commands performed by an application, cluster similar trace log entries from the selected trace log entries, and analyze mappings between the clustered trace log entries to determine data lineage flow associated with the data value. |
| US09659038B2 |
Efficient snapshot read of a database in a distributed storage system
A computer system issues a batch read operation to a tablet in a first replication group in a distributed database and obtains a most recent version of data items in the tablet that have a timestamp no great than a snapshot timestamp T. For each data item in the one tablet, the computer system determines whether the data item has a move-in timestamp less than or equal to the snapshot timestamp T, which is less than a move-out timestamp, and whether the data item has a creation timestamp less than the snapshot timestamp T, which is less than or equal to a deletion timestamp. If the determination is true, the computer system determines whether the move-out timestamp has an actual associated value and, if so, the computer system determines a second tablet in a second replication group in the database that includes the data item and issues the snapshot read operation to the second table in the second replication group to obtain a most-recent version of the data item that has a timestamp no greater than the snapshot timestamp T; otherwise, the computer system issues the snapshot read to the one tablet to obtain a most recent version of the data item that has a timestamp no greater than the snapshot timestamp T. |
| US09659033B2 |
Metric based recognition, systems and methods
Apparatus, methods and systems of object recognition are disclosed. Embodiments of the inventive subject matter generates map-altered image data according to an object-specific metric map, derives a metric-based descriptor set by executing an image analysis algorithm on the map-altered image data, and retrieves digital content associated with a target object as a function of the metric-based descriptor set. |
| US09659028B2 |
File system implementing write once read many (WORM)
The embodiments deal with files that are already present in a storage when mounting the storage in a file system and files created after the mounting as different groups. (Metadata of) the files is classified. The files are each divided into metadata (index) and a file main body and are recorded on different storage areas, that is, an index partition (IP) and a data partition (DP), associated with each other. This file system is effective in a storage format in which a new file is merely written and an already written file is not updated or deleted (for example, a tape medium used in the LTFS). The embodiments implement a WORM file system by rejecting a request to update or delete a file that is present at mounting as a WORM file and permitting update or deletion of a file that is created after mounting until the storage is unmounted. |
| US09659026B2 |
Unordered idempotent logical replication operations
A method and apparatus for replicating a data container of a source storage server at the logical level in an unordered stream of individual data units are described. In certain embodiments, the replication operations can be performed without regard to the differences in geometry of physical persistent storage of the source and destination storage servers and without regard to the differences in data container format of the source and destination storage servers. An initial replication operation of the source data container is performed by transferring the data objects within the source data container to a replica data container in the destination storage server as an unordered stream of individual data units while preserving data object identifiers of the source data objects. Afterwards, incremental replication operations can be performed to capture modifications to the source data container over time after the initial replication operation. |
| US09659025B1 |
Automation of RSG management for backup and recovery
In one example, a process for recovery management in a server environment includes creating a recovery database on the server, mounting the recovery database to a volume on the server, setting an overwrite flag for the recovery database, dismounting a previously existing recovery database from the volume, and deleting the previously existing recovery database. One, some, or all of the aforementioned processes may be performed automatically without requiring specific user inputs or commands. |
| US09659020B2 |
Serialization for delta encoding
Data can be serialized in such a manner as to facilitate later delta encoding, even when the serialization is performed using a lossy compression algorithm or an algorithm in which portions of the serialized data are encoded relative to other portions which may be modified. This can be achieved by approaches including preserving keyframe information across modified versions of a file, duplicating information from a previously created compressed file when serializing a later version, or adding change information showing differences between versions of a file during the serialization process. |
| US09659016B2 |
Geographic space management
At least one subsystem among the plurality of subsystems includes a managing section operable to manage individual event information for events occurring in a management target region of the at least one subsystem among the plurality of regions and adjacent event information for events occurring in a partial range from a boundary of the management target region among routes in an adjacent region that is adjacent to the management target region, and an event selecting section operable to select events about which the moving object is to be informed, from the individual event information and the adjacent event information managed by the at least one subsystem. Also provided is a method and computer program product. |
| US09659014B1 |
Audio and video matching using a hybrid of fingerprinting and content based classification
Aspects relate to determining whether a probe media content matches one or more reference media content. The reference media content is classified into a content class. The probe media content could also be classified into a content class. Similarities between the probe media content and the reference media content are identified. A matching score given to the probe media content is weighted based on statistics regarding matches and false-positive rates for the content class of the reference media content. Further, classifiers can be trained on computed audio features and video features and/or video metadata and audio metadata of various media content. |
| US09659009B2 |
Selective machine translation with crowdsourcing
A structure and method for crowdsourcing includes evaluating a metric related to a content to be translated, determining a priority for the content based on the metric related to the content, and queuing the content for crowdsourcing based on the priority determined from the metric. |
| US09659008B2 |
Information-sharing system
An information gathering system has a server connected to a network, the server having a processor and a coupled data repository, with software executing on the processor from a non-transitory medium providing system intelligence, and a plurality of computerized communication devices coupled to the network, each having a microphone, a speaker, a GPS capability reporting geographic location, and a display screen, each computerized communication device executing coded instructions providing local intelligence at least presenting interactive interfaces to users of the devices, the users enabled to record an audio or audio-video input to the server. The server receives a report of an event occurring at or near a specific geographic location, determines computerized communication devices reporting geographic location within a predetermined distance from the specific geographic location, and messages users of the second computerized communication devices, eliciting input regarding the event. |
| US09659005B2 |
System for semantic interpretation
A semantic database is generated to provide answers to questions by users. Text processors can receive text from text sources, and can convert the text into intermediate logical statements. The text processors can then convert these statements into unambiguous semantic representations. A semantic database connected to the text processors can store the semantic representations. Query processors connected to the semantic database can receive a question from a computing device operated by a user, and can convert the question into intermediate logical subqueries. The query processors can then use a disambiguation table to generate unambiguous semantic subqueries from these intermediate logical subqueries. Using the semantic database, the query processors can match each semantic subquery to the stored semantic representation, and join results of the matching as appropriate, to determine one or more answers to the question. The query processors can send the one or more answers to the computing device. |
| US09659002B2 |
System and method for inputting text into electronic devices
The present invention provides a system comprising a user interface configured to receive text input by a user, a text prediction engine comprising a plurality of language models and configured to receive the input text from the user interface and to generate concurrently text predictions using the plurality of language models, and wherein the text prediction engine is further configured to provide text predictions to the user interface for display and user selection. An analogous method and an interface for use with the system and method are also provided. |
| US09658998B2 |
Systems and methods for internationalization and localization
Webpage content is sent to a user's web browser in a neutral format. On the user's web browser the webpage content is translated by a transformation application into the appropriate language and locale. A Language template file that contains the internationalization and localization data and processing components is loaded onto a browser and is used by the transformation application to render the final data to the user. The transformation application can render a new language and locale by loading an appropriate language template file. |
| US09658997B2 |
Portable page template
Similarity between a first web document and a second web document based on a similarity threshold is determined. The second web document has a portable page template associated therewith that includes one or more predetermined transformations that were previously applied to the second web document. In addition, one or more objects in the second web document are addressed upon the similarity threshold being met such that a tolerance threshold for one or more modifications to the second web document is met. A user is provided with the portable page template after the addressing of the one or more objects in the web document so that the portable page template automatically applies the one or more transformations, which were previously applied to the second web document, to the first web document. |
| US09658993B2 |
Concurrent preparation of multiple versions of a website
Techniques are disclosed for concurrent preparation of multiple versions of a website. Web page content can be branched in response to a request from a first user to create a working copy of one or more production web pages source documents. Any edits applied to the production version of the documents may be automatically applied to the working copy. Further, the working copy can be edited independently of the production version. The working copy can be promoted to production by replacing the production version with the edited working copy. Any number of separate working copies can be created and edited concurrently with the production version. |
| US09658990B2 |
Reordering text from unstructured sources to intended reading flow
An approach is provided in which a number of sections from a sequence of characters included in a Portable Document Format (PDF) file are identified. Each of the identified sections includes a unique set of coordinate positions. The approach builds links between the sections based on a relative position of each of the sections in relation to the other sections along an axis. The approach repeatedly merges sections based on the links that were built to form increasingly larger sections until a final larger section is generated with the characters appearing in a manner consistent with human reading of the rendered PDF document rather than the placement of the characters found within the original PDF file. |
| US09658988B2 |
Systems and methods to segment text for layout and rendering
A method for segmenting text for layout on a web browser includes receiving a block of text at a client computer and defining a plurality of regular expressions, where a first regular expression in the plurality of regular expressions is used to search for a word or a word boundary. The client computer segments the block of text into a plurality of text segments, where the segmenting includes searching the block of text starting at a defined location for a first text segment that matches any of the plurality of regular expressions, adding the first text segment to the plurality of text segments, and updating the defined location to be located at the end of the first text segment within the block of text. The client computer then constructs a layout of the block of text using the plurality of text segments. |
| US09658981B2 |
Network interface card for a computing node of a parallel computer accelerated by general purpose graphics processing units, and related inter-node communication method
A Network Interface Card (NIC) for a cluster node for parallel calculation on multi-core GPU is described. The NIC has a cluster network including a host and a host memory, a graphics processing unit (GPU) with a GPU memory, a bus and the NIC. The NIC has a transmission network connection block and a reception network connection block. The NIC further includes the following blocks: a transmission block, a reception block, and a GPU memory management block for a direct exchange between the GPU memory and the network through the NIC. An inter-nodal communication method of a nodes cluster, which uses the NIC is also described. |
| US09658977B2 |
High speed, parallel configuration of multiple field programmable gate arrays
Representative embodiments are disclosed for a rapid and highly parallel configuration process for field programmable gate arrays (FPGAs). In a representative method embodiment, using a host processor, a first configuration bit image for an application is stored in a host memory; one of more FPGAs are configured with a communication functionality such as PCIe using a second configuration bit image stored in a nonvolatile memory; a message is transmitted by the host processor to the FPGAs, usually via PCIe lines, with the message comprising a memory address and also a file size of the first configuration bit image in the host memory; using a DMA engine, each FPGA obtains the first configuration bit image from the host memory and is then configured using the first configuration bit image. Primary FPGAs may further transmit the first configuration bit image to additional, secondary FPGAs, such as via JTAG lines, for their configuration. |
| US09658973B2 |
Controlling operations according to another system's architecture
An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt. |
| US09658972B1 |
Universal pull-through receiver
A hybrid mass interconnect system and universal pull-through receiver are shown and described. In one embodiment, a universal receiver for a mass interconnect system includes a frame, a connection assembly and a universal interconnect module. Typically, the receiver supports a variety of testing platforms, including PXI-based platforms, LXI-based platforms, AXIe-based platforms, and a combination thereof. In other examples, a variety of other platform relationships may be used. In particular examples, the universal interconnect module has an upper tier with a pair of spatially separated horizontal rails and a lower tier that is adjacent to the upper tier with at least one pair of spatially separated vertical rails. The result is an interconnect system and receiver for enhancing the organizational and interchangeable electrical engagement between a test adapter and automated testing equipment. |
| US09658968B1 |
Implementing hardware accelerator for storage write cache management
A method and controller for implementing enhanced storage adapter write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The controller manages write cache data and metadata with minimum or no firmware involvement for greatly enhancing performance. |
| US09658967B2 |
Evicting cached stores
A tool for determining eviction of store cache entries based on store pressure. The tool determines, by one or more computer processors, a count value for one or more new store cache entry allocations. The tool determines, by one or more computer processors, whether a new store cache entry allocation limit is exceeded. Responsive to determining the new store cache entry allocation limit is exceeded, the tool determines, by one or more computer processors, an allocation value for one or more existing store cache entries, the allocation value indicating an allocation class for each of the one or more existing store cache entries. The tool determines, by one or more computer processors based, at least in part, on the allocation value for the one or more existing store cache entries, at least one allocation class for eviction. The tool program determines, by one or more computer processors, an eviction request setting for evicting the one or more existing store cache entries. |
| US09658965B2 |
Cache utilization to efficiently manage a storage system
In an approach for managing a storage system, distribution of storage volumes among a plurality of storage controller groups may be adjusted dynamically or adaptively based on the current access hot degrees of respective storage volumes in the storage system. In this way, optimized distribution of storage volumes can be achieved without user interference. Such redistribution eliminates the degradation of performance of the storage system. |
| US09658964B2 |
Tiered data storage system
A storage media comprising a first storage subset with a first value of a storage media characteristic and a second storage subset with a second value of the storage media characteristic, the first value of a storage media characteristic being substantially different than the second value of the storage media characteristic and a storage controller configured to allocate a plurality of logical block addresses (LBAs) between the first storage subset and the second storage subset based on a predetermined criterion in view of the first value of the storage media characteristic and the second value of the storage media characteristic. |
| US09658960B2 |
Subcache affinity
A method and apparatus for controlling affinity of subcaches is disclosed. When a core compute unit evicts a line of victim data, a prioritized search for space allocation on available subcaches is executed, in order of proximity between the subcache and the compute unit. The victim data may be injected into an adjacent subcache if space is available. Otherwise, a line may be evicted from the adjacent subcache to make room for the victim data or the victim data may be sent to the next closest subcache. To retrieve data, a core compute unit sends a Tag Lookup Request message directly to the nearest subcache as well as to a cache controller, which controls routing of messages to all of the subcaches. A Tag Lookup Response message is sent back to the cache controller to indicate if the requested data is located in the nearest sub-cache. |
| US09658957B2 |
Systems and methods for managing data input/output operations
Systems and methods for managing data input/output operations are described. In one aspect, a device driver identifies a data read operation generated by a virtual machine in a virtual environment. The device driver is located in the virtual machine and the data read operation identifies a physical cache address associated with the data requested in the data read operation. A determination is made regarding whether data associated with the data read operation is available in a cache associated with the virtual machine. |
| US09658949B2 |
Test system of system on chip and test method thereof
A test system method for testing software of each of a plurality of system on chips (SoCs) are provided. The test system includes: a plurality of test units configured to test the plurality of SoCs according to a plurality of test cases, respectively; a power supplier configured to supply, to each of the plurality of test units, power of a level corresponding to a corresponding test case, among the plurality of test cases; a temperature controller configured to provide, to each of the plurality of test units, a temperature control signal according to the corresponding test case, and to monitor a measurement temperature, provided from each of the plurality of test units, of each of the plurality of SoCs; and an analyzer configured to analyze at least one of a driving voltage, a driving current, and a driving frequency of each of the plurality of SoCs. |
| US09658948B2 |
Workload mapper for potential problem areas using modules and defect data
Embodiments are directed to methods for improving the efficiency at which problem areas are identified and prioritized for an existing large, multi-module software system. In some embodiments, a workload mapper generates workload maps that identify the intersection between defect risk scores accumulated for various modules and a log of the modules that are accesses by a given workload. A graphical user interface (GUI) provides the ability to sort, search, compare and display the workload maps against various sort, search and/or compare criteria. |
| US09658947B2 |
Method for ranking fault-test pairs based on waveform statistics in a mutation-based test program evaluation system
Ranking of fault-test pairs is performed using first and second multitudes of waveform statistics. The first multitude of waveform statistics includes first value-change information regarding variations in logics HIGH and LOW for each bit of each reference output resulting from a test run of the design code. The second multitude of waveform statistics includes second value-change information regarding variations in logics HIGH and LOW for each bit of each faulty output resulting from a test run of the design code injected with a fault. Relative differences between the first and second multitudes of waveform statistics for each bit of each faulty output with respect to the corresponding reference output are determined. A waveform difference based on the relative differences for each signal of each faulty output is determined. A ranking result of fault-test pairs is determined according to the waveform differences of the faulty outputs. |
| US09658946B2 |
Test machine management
A method includes distributing the plurality of test cases to any available test agents, wherein each test case out of the plurality of test cases does not have any associated preconditions. The method receives event information for a first test case out of the plurality of test cases from a first test agent. Responsive to determining the event information for the first test case includes a satisfied condition for a second test case, the method determines whether the satisfied condition for the second test case relates to a global variable or local variable. The method handles the second test case, wherein handling the second test case includes distributing the second test case to the first test agent subsequent to the first test agent becoming available if the satisfied condition relates to the local variable. |
| US09658944B2 |
Generic test automation for graphical user interface (GUI) applications
A method for generic test automation comprises mapping generic interface commands for objects to be tested to tool-specific interface commands of a test automation tool. An application-specific element map based on an application for test is identified, and the application-specific element map includes label names for the elements of the application-specific element map. Application-specific user actions, which are created based on the generic interface commands and the application-specific element map, are sent to the test automation tool for testing the application. |
| US09658942B2 |
Dynamic tracing framework for debugging in virtualized environments
Embodiments of the present invention provide a system and method for a dynamic tracing framework for debugging in a virtualized environment. Embodiment of the present invention can include selecting a home node and a set of remote nodes to which apply a set of probes. Data collection is performed by a tracing agent of each node and the collection of data is shared across multiple software systems. |
| US09658941B2 |
Methods and systems of function-specific tracing
A system and methods are provided for function-specific tracing of a program. In one embodiment, a method includes generating a trace profile identifying one or more functions of a target program, wherein the trace profile identifies one or more functions to trace and depth of tracing for each function to be traced, loading the trace profile and the target program, identifying traced functions in the target program based on the trace profile, patching the target program to call a trace parameter for one or more functions, wherein traced functions are declared at runtime, and observing function calls for traced functions of the application. In this regard, individual functions are traced and debugged on a function-by-function basis without modifying the code or pre-arranging functions so they are traceable. As such, the scope of tracing may be dynamically limited to yield only information that is desired. |
| US09658938B2 |
Iterative test generation based on data source analysis
A method of testing a software program may include generating a test driver by assigning concrete values to input variables of a software program. The method may also include assigning symbolic source set elements to the input variables of the software program to generate a data structure based on the symbolic source set elements. The method may also include symbolically executing a current instruction of the software program based on the concrete values and symbolic source set elements assigned to the input variables of the software program and performing data source analysis on the current instruction of the software program based on symbolic execution of the current instruction. |
| US09658937B2 |
Optimization of hardware monitoring for computing devices
Various aspects provide systems and methods for optimizing hardware monitoring on a computing device. A computing device may receive a monitoring request to monitor a portion of code or data within a process executing on the computing device. The computing device may generate from the monitoring request a first monitoring configuration parameter for a first hardware monitoring component in the computing device and may identify a non-optimal event pattern that occurs while the first hardware monitoring component monitors the portion of code or data according to the first monitoring configuration parameter. The computing device may apply a transformation to the portion of code or data and reconfigure the first hardware monitoring component by modifying the first monitoring configuration parameter in response to the transformation of the portion of code or data. |
| US09658936B2 |
Optimization analysis using similar frequencies
Periodicity similarity between two different tracer objectives may be used to identify additional input parameters to sample. The tracer objectives may be individual portions of a large tracer operation, and each of the tracer objectives may have separate set of input objects for which data may be collected. After collecting data for a tracer objective, other tracer objectives with similar periodicities may be identified. The input objects from the other tracer objectives may be added to a tracer objective and the tracer objective may be executed to determine a statistical significance of the newly added objective. An iterative process may traverse multiple input objects until exhausting possible input objects and a statistically significant set of input objects are identified. |
| US09658927B1 |
Assisted device recovery
A system for assisted device recovery is provided. The system includes a CMTS connected to a cable modem over a network. The system also includes database including a plurality of cable modem fingerprints and associated recovery actions and an assisted device recovery module. The assisted device recovery module includes one or more processors and a memory. The assisted device recovery module also includes a cable modem identifier configured to identify the make and model of the cable modem using a fingerprint, wherein the fingerprint includes a hardware version and a software version of the cable modem, a recovery determiner configured to query the database with the cable modem fingerprint and determine an associated recovery action, and a recovery performer configured to perform the associated recovery action on the cable modem. |
| US09658922B2 |
Computer-readable recording medium having stored therein program for write inspection, information processing device, and method for write inspection
An information processing device that inputs and outputs data into and from a storage device having a plurality of regions, and includes a processor that: changes a first counter value corresponding to a first region serving as a writing target and being retained in a retainer retaining multiple counter values one representing the number of times of data writing into each of the regions; obtains the first counter value from the retainer; generates block data by attaching the first counter value to data to be written into the first region; writes the block data into the first region; when the first counter value satisfies a predetermined condition, reads the block data from the first region after the writing, and compares the read block data with the block data written into the first region, and when the read block data does not match the written block data, notifies an error. |
| US09658920B1 |
Method for reconfiguring an erroneous memory frame in an integrated circuit
A method of correcting a configuration memory frame may include identifying an erroneous memory frame in a plurality of memory frames in the integrated circuit. The erroneous memory frame may be identified with error detection circuitry on the integrated circuit. A portion of data stored in an off-chip memory module may be read with controller circuitry. The read data portion may correspond to the erroneous memory frame. The erroneous memory frame may thus be corrected by loading the read data portion into the erroneous memory frame during normal operation of the integrated circuit. Every memory bit in the erroneous memory frame may be replaced or overwritten when the read data portion is loaded into the erroneous memory frame. The integrated circuit may be partially reconfigured when the erroneous memory frame is corrected. |
| US09658914B2 |
Troubleshooting system using device snapshots
An information handling system (IHS) troubleshooting system includes a customer IHS including a plurality of components. A customer management system in the customer IHS detects a failure in a managed system and, in response, immediately triggers a device snapshot of the customer IHS. At least one managed system in the customer IHS includes a device snapshot engine that, in response to the customer management system triggering the device snapshot of the customer IHS, immediately create the device snapshot of the customer IHS. A device snapshot storage in the customer IHS stores the device snapshot of the customer IHS. A snapshot communication engine in the customer IHS sends the device snapshot of the customer IHS over the network to a support IHS. The support IHS may load the device snapshot into a virtual IHS and manage the virtual IHS to replicate the failure detected in the managed system for troubleshooting. |
| US09658911B2 |
Selecting a directory of a dispersed storage network
A method begins by a processing module receiving a dispersed storage network (DSN) access request accessing DSN memory regarding a set of encoded data slices, selecting a local DSN directory or a global DSN directory to produce a selected DSN directory, identifying an entry of the selected DSN directory regarding the set of encoded data slices to produce an identified entry, and accessing the DSN memory regarding the set of encoded data slices. The method continues with the processing module determining whether to update one or more of the local DSN directory and the global DSN directory based on the accessing the DSN memory and when the one or more of the local DSN directory and the global DSN directory is to be updated, updating the one or more of the local DSN directory and the global DSN directory in accordance with the accessing the DSN memory. |
| US09658909B2 |
Information processing apparatus, information processing method, and information processing program
An information processing apparatus includes a storage configured to store trace information relating to execution conditions of monitoring subjects, and a determination value, the determination value being a number of the monitoring subjects using a specific resource that can be used by the monitoring subjects, and a processor configured to increase the determination value by a predetermined value when one of the monitoring subjects starts to use the specific resource, reduce the determination value by the predetermined value when one of the monitoring subjects stops using the specific resource, and delete the trace information stored in the storage when the determination value indicates that none of the monitoring subjects are using the specific resource. |
| US09658906B2 |
Routing messages between applications
A system and method for enabling the interchange of enterprise data through an open platform is disclosed. This open platform can be based on a standardized interface that enables parties to easily connect to and use the network. Services operating as senders, recipients, and in-transit parties can therefore leverage a framework that overlays a public network. |