Document | Document Title |
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US09634943B2 |
Transparent provisioning of services over a network
An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the apparatus provides external connectivity to other devices that wish to intercept packets as well. The apparatus applies one or more rules to the intercepted packets which execute one or more functions on a dynamically specified portion of the packet and take one or more actions with the packets. The apparatus is capable of analyzing any portion of the packet including the header and payload. Actions include releasing the packet unmodified, deleting the packet, modifying the packet, logging/storing information about the packet or forwarding the packet to an external device for subsequent processing. Further, the rules may be dynamically modified by the external devices. |
US09634941B2 |
Regional independent tandem telephone switch
Implementations of the present disclosure involve an apparatus and/or method for a regional independent tandem switch of a telecommunications network. The tandem switch processes communications between a long distance carrier and a local exchange carrier through a voice over IP (VOIP) network. By utilizing the VOIP network, the regionally independent tandem may process long distance communications to and from any point in the network, regardless of the physical proximity of the tandem to the originating/destination communication device. The regionally independent nature of the tandem also allows for flexibility in communication routing through the network, load balancing between the network tandem switches and reduction of needed components of the network for proper processing of the long distance communications. |
US09634939B2 |
System and a method for managing wireless networks
A method for reducing load in a cellular communication network, within at least one cell that covers an area which overlaps an area that is at least partially covered by one or more Wi-Fi networks, comprises the steps of: (a) monitoring traffic load within the at least one cell; (b) providing information to a plurality of mobile stations operative in a cellular mode which are currently communicating via their respective at least one cell, to enable one or more of the plurality of mobile stations to switch to their Wi-Fi operating mode, wherein the plurality of mobile stations are capable of operating both in a cellular operating mode and in a Wi-Fi operating mode, and wherein said information indicates to the receiving mobile stations to perform a switch to its Wi-Fi operating mode; (c) for at least some of said plurality of mobile stations, switching their operation mode to Wi-Fi mode. |
US09634935B2 |
Method, name server, and system for directing network traffic utilizing profile records
A server, intermediation server, system and a method for directing network traffic are provided. The name server and intermediation server each include a network interface configured to communicate with a network, a memory configured to store the profile record a processor in communication with the memory and the network interface. The name server is for returning an assigned query result to a originating computing device when a destination identifier is associated with the profile record. The intermediation server is for perform a routing operation based on the request. The system includes an originating computing device a name server and an intermediation server all connected to a network. The method involves receiving a profile record and destination identifier, determining an association of the between the profile record and identifier, and returning with an assigned query result or a default query result. |
US09634934B2 |
Dynamic host configuration protocol relay in a multipod fabric
A packet is generated at a first network connected device for transmission to a destination network device through a network comprising a plurality of pods. At least two of the plurality of pods are within separate management domains, and generating the packet comprises generating the packet with a first identifier and a second identifier. The first identifier indicates a pod of the plurality of pods in which the destination network connected device is located, and the second identifier indicates an identity of the destination network connected device within the pod of the plurality of pods. The packet is transmitted from the first network connected device to the destination network connected device. |
US09634932B2 |
Method and apparatus for forwarding traffic of switching system
Embodiments of the present invention provide a method and an apparatus for forwarding traffic of a switching system. The switching system includes a first LCC, at least one second LCC, and at least one third LCC that are interconnected according to a mesh form topology; and the method includes: receiving, by the first LCC, a packet, and parsing the packet to acquire a destination address of the packet; and when the destination address indicates that the packet is to be sent to the third LCC, if a currently preset configuration mode of the switching system is a first configuration mode, bearing, by the first LCC, the packet on a third link, and forwarding the packet to the third LCC, where the first configuration mode indicates that an N-hop mode is currently applied to the switching system, where N is a natural number greater than or equal to 3. |
US09634924B2 |
Server-layer shared link risk group analysis to identify potential client-layer network connectivity loss
In one embodiment, a particular device within a client-layer network maintains client-layer topology information including server-layer Shared Risk Link Group (SRLG) information of server-layer devices and links in a server-layer network associated with client-layer links and client-layer nodes in the client-layer network. A determination is made to discover if there is an alternative client-layer path to an established client-layer path between a first packet switching device and a second packet switching device if all server-layer resources of any particular server-layer SRLG of a plurality of total server-layer SRLGs associated with the established client-layer path become unavailable. In one embodiment, the plurality of total server-layer SRLGs includes: an SRLG of a same optical node, an SRLG of a same optical fiber, an SRLG of co-located plurality of optical nodes, and/or an SRLG of co-located plurality of optical fibers. |
US09634923B2 |
Method, apparatus and system for disseminating routing information
A method for disseminating routing information includes receiving values of network quality parameters indicating a level of network quality among a set of acceleration nodes and between the set of acceleration nodes and a set of service nodes. The method further includes designating an acceleration node as a source node and designating a service node as a destination node, and then determining, based on the values of network quality parameters and from the set of acceleration nodes, a series of intermediate hop nodes connecting the source node and the destination node. The method includes generating routing information associated with a routing path from the source node to the destination node via the intermediate hop nodes. The routing information is disseminated to the source node and the intermediate hop nodes such that data can be forwarded from the source node to the destination node according to the routing path. |
US09634920B1 |
Trace deduplication and aggregation in distributed systems
Methods and systems for implementing trace deduplication are disclosed. One or more interactions between a plurality of components are determined. The interactions relate to a trace. A fingerprint for the trace is generated. The fingerprint is compared with a plurality of stored fingerprints representing a plurality of stored traces. The trace is stored if the fingerprint does not match any of the plurality of stored fingerprints. The trace is determined to be a duplicate if the fingerprint matches one of the plurality of stored fingerprints. |
US09634916B2 |
Signalling congestion
Methods and apparatus are disclosed for signalling congestion being caused by data items such as packets, received at a network element such as a router, in a communications network such as the Internet, or being caused by items otherwise requiring service or capacity from a shared resource. Preferred embodiments of the method involve identifying whether or not received data items received at a network element are capable of carrying congestion indications such as ECN marks, and for those that are capable, assigning congestion indications to the data items in dependence on a queue length characterization based on a substantially current, instantaneous measurement of the length of the queue, whereas for those that are not capable, a sanction such as dropping may be applied in dependence on a different queue length characterization based on a weighted moving average of current, recent, and less recent measurements of the length of the queue. |
US09634908B2 |
Determining characteristics of a connection traversing a packet switching device
In one embodiment, characteristics of a connection traversing a packet switching device is determined, which includes, but not limited to, determining a network port number and/or address of an established connection based on a signature of the connection. In one embodiment, a packet switching device receives and forwards packets of particular communication between a device and a remote node in a network. The packet switching device maintains information of the particular communication and identification data for use in subsequent identification of said particular communication. In response to receiving a communications information request specifying a signature related to said particular communications, the packet switching device prepares and sends a response, which typically includes matching the signature to said maintained identification data resulting in identification of said information including a characterization of said particular communications, and sending a reply including the characterization of said particular communications. |
US09634906B2 |
Devices and methods supporting content delivery with adaptation services with feedback
A device supporting content delivery is configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include adaptation services with feedback. |
US09634901B2 |
Topology discovery in a computing system
A computer network may comprise a plurality of computing devices. In one example, a method may be provided for discovering topology of the computer network. The method may comprise sending, by a host computing device of the computing network, a neighbor discovery packet to each network interface of the host that has a connection, receiving a reply packet responding to the neighbor discovery packet, building a neighbor map for all neighbor computing devices to the host, sending a connection discovery packet to each network interface of the host that has a connection, receiving reply packets responding to the connection discovery packet, and building a connection map for connections among computing devices based on the information in the reply packets. |
US09634897B2 |
Communication apparatus operable in auto-negotiation mode, method of controlling the communication apparatus, and storage medium
A communication apparatus capable of activating an EEE power saving mode when not activated. The communication apparatus is operable in an auto-negotiation mode. When a CPU of the communication apparatus determines that a power saving mode to be realized in the auto-negotiation mode is to be activated, if an other-party apparatus at the other end of communication has been set to a fixed mode, the CPU causes the other-party apparatus to be set to the auto-negotiation mode. |
US09634896B2 |
Plug-and-play network filter
A method of configuring an appliance to be a plug-and-play network filter includes the steps of configuring an appliance to alter the flow of network traffic when the appliance is connected to a network. The appliance is configured to change the address resolution protocol ARP so that it assumes the role of a router by issuing an ARP packet. The appliance is configured to establish itself between the router and end user terminals. The appliance is configured to respond to any ARP Request on the Gateway IP address. The appliance is configured to monitor Internet traffic, and filter certain predefined types of Internet traffic. The appliance is configured to transparently proxy web packets on TCP with destination port 80. |
US09634890B2 |
Powering off and rebooting method, device and system
Disclosed are a powering off and rebooting method, apparatus and system. Wherein, the method includes: an office-end device monitoring a user-end access device; and when the office-end device monitors that the user-end access device is halted, sending a reboot command to the user-end access device; wherein the reboot command is used for indicating a power supply module in the user-end access device to perform a powering off and rebooting operation on the user-end access device. The abovementioned solution solves the problem in the related art that technical personnel have to go to the site to reboot a device if the software reset is invalid when the device is halted, so that research and development technical personnel can timely and easily power off and reboot the device without going to the site, thus treating a failure timely and reducing maintenance costs, and improving the operability and maintenance efficiency of maintenance personnel. |
US09634883B2 |
Verifying information stored on a managed network device
A method and mechanism for verifying information on a managed device is provided. A request identifying the managed object and also containing a plurality of non-null values comprising proposals for a correct value of the managed object is received from a requester that does not have a correct value for a managed object of a managed device. The requester is unable to read and write the managed object directly, and unable to obtain object specification information. It is determined whether any of the values match the correct value stored in the managed object. Execution of the request is completed by transmitting a notification message indicating whether any of the values match the correct value of the managed object, where the notification message does not provide any indication of which proposed value is the correct value. |
US09634879B2 |
Demodulator apparatus and demodulation method
A demodulator apparatus includes a memory and a processor coupled to the memory. The processor executes a process including: applying lattice reduction to a channel response matrix; applying linear detection to a reception signal in lattice-reduced basis using a lattice-reduced channel response matrix; calculating an expectation of a symbol in the lattice-reduced basis; inversely transforming the expectation of the symbol from the lattice-reduced basis into an original basis; and calculating soft-decision data by performing interference cancellation method in inversely transformed expectation of the symbol in the original basis. |
US09634874B2 |
Bonded OFDM communication system
An orthogonal frequency division multiplexing (OFDM) communication system includes a first interface having a first cable coupler to couple to a first end of a coaxial cable, and a first plurality of signal pathways coupled to the first cable coupler. Each signal pathway of the first plurality includes a physical (PHY) layer component and a radio frequency (RF) front end coupled to the PHY layer component. The system further includes a second interface having a second cable coupler to couple to a second end of a coaxial cable, and a second plurality of signal pathways coupled to the second cable coupler. Each signal pathway of the second plurality corresponds to a signal pathway of the first plurality and includes a PHY layer component and an RF front end coupled to the PHY layer component. |
US09634870B2 |
Optimized receivers for faster than nyquist (FTN) transmission rates in high spectral efficiency satellite systems
An approach is provided for increasing transmission throughput rates for a source signal transmitted over a wireless channel, applying faster-than-Nyquist (FTN) signaling rates combined with tight frequency roll-off to the a source signal. A receiver is provided that compensates for ISI effects induced by the FTN rate and tight frequency roll-off, where the complexity of the receiver grows only linearly with the interference memory. The receiver comprises an equalizer configured to compensate for the ISI effects, and a decoder configured to decode the output of the equalizer to determine and regenerate the source signal. The receiver processes the received signal via a plurality of processing iterations. For one processing iteration, the decoder generates a set of a posteriori soft information based on the output of the equalizer, and the equalizer uses the a posteriori soft information as a priori soft information for a subsequent processing iteration. |
US09634869B2 |
Method and apparatus for channel estimation and detection in MIMO system
The present invention provides a method for performing channel estimation and detection in a Multiple-Input-Multiple-Output (MIMO) system, including: generating a demodulation reference signal, DM-RS, pattern for an extended cyclic prefix (CP); and estimating and detecting channel performance based on the generated DM-RS signal pattern. The DM-RS pattern supports from rank 1 to rank 8 patterns for 8 layer transmission. A transmitter, a receiver and a system thereof are also provided. The solution of the present invention improves channel estimation accuracy, saves channel estimation implementation and implementation complexity at terminals. |
US09634867B2 |
Computing service chain-aware paths
A method implemented by a path computation element (PCE), comprising receiving a path computation request to compute a network path for a source-destination pair in a service chain (SC) network, wherein the path computation request comprises at least one network routing constraint and a service function (SF) input associated with a plurality of SFs, computing a plurality of network paths through the network for the source-destination pair according to the network routing constraint, selecting at least a first of the network paths according to the SF input, and sending a path computation response indicating at least the first network path in response to the received path computation request. |
US09634861B2 |
Calibration of transceiver
Techniques for reducing error in time-of-flight measurement due to transceiver latency are disclosed. A method includes determining a first indicator of a first latency of a first transceiver of a first system using a first loopback configuration of the first transceiver. The method includes receiving a second indicator of a second latency of a second transceiver determined by a second system using a second loopback configuration of the second transceiver. The method includes determining a third indicator of a roundtrip latency of a communication from the first transceiver to the second transceiver and back to the first transceiver. The method includes determining a time-of-flight between the first system and the second system based on the first indicator, the second indicator, and the third indicator. |
US09634857B2 |
Auxiliary channel remote device management, diagnostics, and self-installation
A remote device management, diagnostics, and self-installation architecture employs multiple wireless links, which may include a local wireless link and a remote wireless link. The architecture employs cellular channels for remote management of customer premises equipment (CPE). Within the architecture, test devices may operate on the CPE. As examples, the test devices may include a cellular radio, or the test devices may be in communication with another device that includes the cellular radio. |
US09634854B2 |
Method and apparatus for sharing functions between devices via a network
A method of sharing a function via a network includes selecting a second device having a shared function desired by a first device from among at least one device connected to the network, linking the first device with the second device via the network, transmitting original multimedia content from the first device to the second device via the network, and performing the shared function with respect to the original multimedia content in the second device and transmitting result data of the performing of the shared function to the first device via the network. |
US09634853B2 |
Smart power management apparatus and method leveraging monitoring status of manual switch
A smart power management unit (SPMU) apparatus and method of intelligently switching from a “disconnect mode” to a “connect mode” in regards to power-supplying to a paired downstream load device by programmatically monitoring whether there is change in state of the manual switch of the load device, is provided. The SPMU comprises relay module configured to operate in either operation mode (connect mode) or monitor mode (disconnect mode), and controller module configured to determine the operating mode of relay module. When in monitor mode, relay module is configured to disconnect the power supply from the load device while simultaneously enable a monitoring means configured to monitor a change in state of the manual switch. Upon monitoring a change in state of the manual switch based on a response signal supplied from the monitoring means, the controller module switches the relay module from monitor mode to operation mode. |
US09634852B2 |
Control method for information apparatus and computer-readable recording medium
A control method of the present disclosure causes a computer of the information apparatus to: switch between display of a first display screen and a second display screen displayed on the display, when selection of a region corresponding to a staircase on a floor plan for a first floor or a second floor is sensed; and output to the network a first control command, when selection of an illumination icon representing an illumination device among the one or more target devices in a region corresponding to the staircase included in the first display screen, or an illumination icon representing the illumination device in a region corresponding to the staircase included in the second display screen is sensed, and when selection of the region corresponding to the staircase is sensed, the first control command controlling on/off of power for the illumination device associated with the region corresponding to the staircase. |
US09634849B2 |
System and method for using a packet process proxy to support a flooding mechanism in a middleware machine environment
A system and method can support flooding mechanism using a packet process proxy in a middleware machine environment. The middleware machine environment can comprise a gateway instance that includes an external port for receiving data packets from an external network. The middleware machine environment also comprises one or more host servers, each of which is associated with one or more virtual machines. Furthermore, said host servers can provide virtual interfaces that belong to a virtual hub associated with the gateway instance. At least one said packet is a flooded packet that is specified with an unknown destination address when it is received at the external port. The gateway instance can send the flooded packet to a designated virtual interface on a host server, and a packet process proxy on the host server can forward the flooded packet to a virtual machine on another host server for processing this packet. |
US09634840B2 |
Digital signature technique
A method for signing a digital message, including the following steps: selecting parameters that include first and second primes, a ring of polynomials related to the primes, and at least one range-defining integer; deriving private and public keys respectively related to a random polynomial private key of the ring of polynomials, and to evaluations of roots of unity of the random polynomial to obtain a public key set of integers; storing the private key and publishing the public key; signing the digital message by: (A) generating a noise polynomial, (B) deriving a candidate signature by obtaining a hash of the digital message and the public key evaluated at the noise polynomial, and determining the candidate signature using the private key, a polynomial derived from the hash, and the noise polynomial, (C) determining whether the coefficients of the candidate signature are in a predetermined range dependent on the at least one range-defining integer, and (D) repeating steps (A) through (C) until the criterion of step (C) is satisfied, and outputting the resultant candidate signature as an encoded signed message. |
US09634839B2 |
Systems and methods for preventing transmitted cryptographic parameters from compromising privacy
Techniques, systems, and devices are disclosed for performing secure cryptographic communication. One disclosed technique includes transmitting information that identifies a group key from a first device to a second device. The technique further includes, in the first device, using the group key to encrypt an input vector, transmitting the encrypted input vector, encrypting privacy-sensitive information using a device key, an encryption algorithm, and the input vector, and transmitting the encrypted privacy-sensitive information to the second device. |
US09634838B2 |
Complex format-preserving encryption scheme
Methods, computing systems and computer program products implement embodiments of the present invention that include defining multiple primitives, each primitive including ranking and unranking methods. Two or more of the multiple primitives are selected, and an operation is performed on the selected primitives, thereby defining a complex format. Upon and encryption processor receiving a data record comprising a plaintext, the complex format is applied to the plaintext, thereby generating a ciphertext, and the ciphertext is transmitted to a remote computer. Upon receiving the ciphertext, the remote computer can apply the complex format to the received ciphertext, thereby regenerating the plaintext. |
US09634837B1 |
Method and apparatus for causing a delay in processing requests for internet resources received from client devices
A method and apparatus for causing a delay in processing requests for Internet resources received from client devices is described. A server receives from a client device a request for a resource. The server transmits a response to the first client device indicating that access to the resource is temporarily denied. The response includes a cryptographic token associated with the first request and a predetermined period of time during which the first client device is to wait prior to transmitting another request to access the resource. The server receives a second request for the resource, upon determining that the second request includes a valid cryptographic token, the server causes the second request to be processed. The server receives a third request for the resource, and upon determining that the third request does not include a valid cryptographic token, the server blocks the third request. |
US09634834B1 |
Distributed cryptographic management for computer systems
An administrator installs a key management agent on a previously approved client machine. The agent is started on the client machine, which posts requests for keys to a central key management service. The central key management service logs requests posted to it by clients, and checks for existing pre-approval records. If none are found, a message is typically sent to an approver for the requesting client machine. When a request is verified as approved, the request is flagged for further processing. The supported systems continuously or periodically look for records flagged for processing, use requests to generate keys and other appropriate elements for the requesting client machine, and post keys and other elements to the key management database. The key management agent polls the central key management service periodically until finding the expected key file, which it downloads and installs into a protected file location on the client machine. The key management agent periodically sends status messages to the central key management service, which tracks expected behavior of the client machine and/or key management agent. |
US09634827B2 |
Encrypting data
A method and system. Ciphertext is generated by applying an initialization vector and an encryption key to plaintext. The initialization vector is combined with the ciphertext to generate encrypted data, by using an embedding rule to perform the combining, wherein using the embedding rule includes generating the encrypted data by: dividing the initialization vector into a specified number of bits to obtain an ordered sequence of initialization vector fragments; dividing the ciphertext into a specified number of bits to obtain ciphertext fragments; and distributing the initialization vector fragments between the ciphertext fragments according to the order of the initialization vector fragments in the sequence. |
US09634825B2 |
Apparatus and method for correcting time stamps of transactions performed by multiple servers
A first memory unit stores requester event information pieces each including time information indicating an occurrence time of an event associated with a process executed by a first server. A second memory unit stores request-destination event information pieces each including time information indicating an occurrence time of an event associated with a process executed by a second server in response to a request from the first server. A determining unit determines, for each request-destination event information piece, a correction allowable range of the time information by comparing the time information of the request-destination event information pieces with that of the requester event information pieces. A generating unit generates an information set by extracting, from the request-destination event information pieces arranged in chronological order according to the time information, chronologically consecutive request-destination event information pieces whose correction allowable ranges include a common value. |
US09634823B1 |
Systems for integrated self-interference cancellation
A system for integrated self-interference cancellation, comprising a transmit coupler, coupled to a transmit signal, that samples the transmit signal to create a sampled transmit signal; an analog self-interference canceller, coupled to the transmit coupler, comprising a controller; a signal divider, that splits the sampled transmit signal into a set of signal components; a set of phase shifters, wherein a phase shifter of the set shifts a signal component of the set of signal components by a total phase shift value; a set of scalers, wherein a scaler of the set scales the signal component by a total scale factor; a signal combiner, that combines the set of signal components into a self-interference cancellation signal; and a receive coupler, coupled to a receive signal, that combines the self-interference cancellation signal with the receive signal to remove a portion of self-interference present in the receive signal. |
US09634822B2 |
Information processing device and method for determining path range
An information processing device includes a first storage unit and a processor. The first storage unit is configured to store therein setting information designating a path range. The path range is one of a subset of a plurality of communication paths and a full set of the plurality of communication paths. The processor is configured to perform communication through a communication path included in a first path range designated by first setting information stored in the first storage unit. The processor is configured to acquire performance information of the respective communication paths included in the first path range. The processor is configured to select a second path range between the subset and the full set on basis of the acquired performance information. The processor is configured to store second setting information designating the selected second path range in the first storage unit. |
US09634815B2 |
Method and device for terminal to execute uplink HARQ operation in wireless communication system
Disclosed in the present invention is a method for a terminal to receive an acknowledgement/negative-ACK (ACK/NACK) from a base station in a wireless communication system. More specifically, the method comprises the steps of receiving from the base station, through a first carrier wave, scheduling information on uplink data to be transmitted through a second carrier wave, transmitting the uplink data to the base station through the second carrier wave, and receiving an ACK/NACK signal for the uplink data from the base station, in one specific subframe from the first carrier wave or the second carrier wave. |
US09634813B2 |
Hitless multi-carrier spectrum migration method and apparatus
A hitless multi-carrier spectrum migration method and apparatus are disclosed. The method includes: obtaining a spectrum of a secondary carrier and a to-be-migrated carrier in a target carrier group from a network management system, and generating the secondary carrier according to the spectrum of the secondary carrier; sending a migration notification to a peer network device, and performing answer response to the migration notification from the peer network device, where the answer response is used to determine that network devices at both ends can perform spectrum migration; sending migration signaling to the peer network device; and receiving the migration signaling sent by the peer network device, and migrating, according to the migration signaling, overhead information and a service that are borne on the to-be-migrated carrier in the target carrier group to the secondary carrier. |
US09634811B2 |
Access point and method for communicating with stations in accordance with a multiple-access technique
According to various embodiments, a computer-implemented method is disclosed that allows an AP to efficiently poll various information from STAs belonging to a SDMA group. Each STA may transmit uplink frames using uplink SDMA mechanism. |
US09634810B2 |
Enhancements to wireless networks to support short message service (SMS) communication in the packet switched domain
Technology for communicating a short message service (SMS) communication in a packet switched (PS) domain of a serving general packet radio service (GPRS) support node SGSN in a Universal Terrestrial Radio Access Network (UTRAN). In one embodiment, a PS support module is configured to receive a request message from a mobile station (MS), the request message including an Additional Update Type information element (IE), the Additional Update Type IE including information to indicate that the MS is to support a PS based short messaging service (SMS). |
US09634805B2 |
Packet transmission method
A packet transmission method is provided herein. The packet transmission method is adapted for a wireless distribution system. The packet transmission method includes: generating a packet by an access controller or a wireless access point; determining whether the packet belongs to CAPWAP (Control and Provisioning of Wireless access point s) packet; adding a tag into a packet descriptor corresponding to the packet when the packet belongs to CAPWAP packet; transmitting the packet to the wireless access point or transmitting the packet to the access controller; determining whether an error is occurred during transmitting the packet; determining whether the packet descriptor corresponding to the packet includes the tag when the error is occurred during transmitting the packet; and adding the packet into a queue when the packet descriptor corresponding to the packet includes the tag. |
US09634803B1 |
Optical subcarrier multiplex system with joint forward error correction coding
An optical subcarrier multiplex system. An input data signal is jointly coded with at least one forward error correction (FEC) code before symbol mapping and before subcarrier modulation. Joint FEC coding mitigates non-uniform subcarrier performance. |
US09634802B2 |
Resource mapping to handle bursty interference
Resource mapping and coding schemes to handle bursty interference are disclosed that provide for spreading the modulated symbols for one or more transmission code words over more symbols in the time-frequency transmission stream. Certain aspects allow for the modulated symbols to be based on bits from more than one code word. Other aspects also provide for re-mapping code word transmission sequences for re-transmissions based on the number of re-transmissions requested by the receiver. Additional aspects provide for layered coding that uses a lower fixed-size constellation to encode/decode transmissions in a layered manner in order to achieve a larger-size constellation encoding. The layered encoding process allows the transmitter and receiver to use different coding rates for each coding layer. The layered encoding process also allows interference from neighboring cells to be canceled without knowledge of the actual constellation used to code the interfering neighboring signal. |
US09634799B2 |
Decoding device, information transmission system, and non-transitory computer readable medium
Provided is a decoding device including a reception unit that receives data of which the number of bits is converted and encoded such that a ratio between appearance frequency of a first code and appearance frequency of a second code is a predetermined range, and to which an error correcting code including redundant bits for calculating an error position of the data and a parity check bit of the data is appended, and a detection unit that detects that there are an odd number of bit errors in the data when a value of a syndrome corresponding to an error position is a first predetermined value and an error occurs in the decoding, or when the value of the syndrome is not the first value and a value of the parity check bit is a second predetermined value and an error occurs in the decoding on the data. |
US09634794B2 |
Method and apparatus for transceiving a MIMO packet in a wireless LAN system
A method of transmitting a packet in a wireless local area network system. The method is performed by a transmitting station and includes generating a packet including at least one spatial stream and first control information including a first field and a second field, and transmitting the packet to at least one receiving station. The first field indicates a group ID of the at least one receiving station and whether the packet is generated based on a single user transmission scheme or a multi user transmission scheme. Content of the second field is determined based on whether the packet is generated based on the single user transmission scheme or the multi user transmission scheme, the second field indicates a modulation and coding scheme (MCS) index used for the packet if the packet is generated based on the single user transmission, and the second field indicates an encoding scheme applied to the at least one receiving station if the packet is generated based on the multi user transmission scheme. |
US09634793B2 |
Open-loop link adaption adjusting method and apparatus
Embodiments of the present invention disclosed an open-loop link adaptation adjusting method and apparatus, firstly, classifying, by a base station, states of a user equipment during an information transmission process, and configuring an open-loop link adaptation adjusting OLLA value for each of the classified states respectively; then, determining, by the base station, a current state of the user equipment, and selecting an OLLA value corresponding to the current state of the user equipment from the OLLA values corresponding to each of the states respectively; and finally, after adjusting a modulation and coding scheme MCS value according to the OLLA value corresponding to the current state of the user equipment, modifying, by the base station, the OLLA value corresponding to the current state of the user equipment. The present invention is applicable to the communication system field. |
US09634790B2 |
Burst-mode optical amplification apparatus and method thereof
A burst-mode optical amplification apparatus and method is provided. The burst-mode optical amplification apparatus includes a gain saturation signal generator configured to generate a gain saturation signal for gain stabilization based on an incoming input optical signal; a wavelength multiplexer configured to wavelength multiplex the incoming input optical signal and the gain saturation signal; and an optical amplifier configured to amplify both the wavelength-multiplexed input optical signal and the wavelength-multiplexed gain saturation signal. The apparatus may further include a time delay module configured to synchronize the input optical signal and the gain saturation signal by delaying the transmission time of the input optical signal, taking into consideration the processing time needed by the gain saturation signal generator to generate the gain saturation signal. |
US09634788B2 |
Optical communication system having low latency
Consistent with the present disclosure, an optical communication system is provided in which client data is input to a first node and output from a second node, spaced from the first node, with little delay. In one example, the delay is reduced by including higher order Raman amplifiers that provide a substantially uniform gain along the length of a fiber optic link, thereby reducing the number of EDFAs that may otherwise be installed along the optical fiber link or eliminating such EDFAs entirely. In another example, FEC encoding and decoding are not employed, thereby reducing the delay even further. |
US09634786B2 |
Communication systems with phase-correlated orthogonally-polarized light-stream generator
In one aspect, the present disclosure relates to a communications system which, in one embodiment, includes a phase-correlated, orthogonally-polarized, light-stream generator (POLG) for preparing light into phase coherent light streams having defined states of polarization and spectral composition. In one embodiment, the POLG includes a light source configured to emit light having a predetermined wavelength and a polarization apparatus configured to prepare light from the light source into particular states of polarization. The POLG also includes a phase modulator configured to produce light having a plurality of wavelengths and configured to retard the phase of propagation of light with a first state of linear polarization while not retarding the phase of light with a state of linear polarization orthogonal to the first state of linear polarization when an external electric field is applied. The POLG also includes an electrical oscillator configured to periodically apply an electric field to the phase modulator. |
US09634785B2 |
Interference cancellation method of user equipment in cellular communication system
An interference cancellation method and apparatus of user equipment in a cellular communication system is provided. The method includes receiving signals including a desired signal and an interference signal from one or more base stations; determining a maximum likelihood (ML) decision metric to determine a value “l” of a rank indicator (RI), a value “p” of a precoding matrix indicator (PMI), and a value “q” of a modulation (MOD) level of the interference signal; applying a logarithm to the ML decision metric, and applying a maximum-log approximation to a serving data vector and an interference data vector, which are included in the ML decision metric; determining the values of “l,” “p,” and “q” using the applied ML decision metric; and cancelling the interference signal from the received signals using the determined values of “l,” “p,” and “q.” |
US09634784B2 |
Radio telecommunications system and method of operating the same with polling
An apparatus or method for transmitting data blocks on a communications channel having a radio link between two stations including a user equipment comprises receiving first data blocks from the user equipment, and transmitting second data blocks to the user equipment. A polling interval is dynamically set for the transmission of polling messages to the user equipment after transmission of the second data blocks, the polling interval being set in accordance with at least one of: a size of one or more data blocks received by the apparatus from the user equipment, a size of one or more blocks transmitted from the apparatus to the user equipment, and a service to which the user equipment is subscribed. The apparatus may be used as a PCU in a cellular mobile telephone system. |
US09634781B2 |
Concluding validity of uplink synchronization parameter
Concluding the validity of an uplink synchronization parameter, such as a timing advance, in a packet-switched radio system. The method includes: detecting (802) an uplink synchronization parameter; measuring (804) an interval from the detection of the uplink synchronization parameter; and comparing (806, 808) the measured interval with a predetermined threshold and, if the measured interval is shorter than the predetermined threshold, concluding (810) that the detected uplink synchronization parameter is still valid, or else concluding (812) that the detected uplink synchronization parameter is no more valid. |
US09634777B2 |
Systems and methods for measurement of electrical channel loss
In accordance with embodiments of the present disclosure, a method for characterizing electrical characteristics of a communication channel between a transmitter of a first information handling resource and a receiver of a second information handling resource may include receiving a test signal at the receiver from the transmitter during an in-situ characterization mode of the second information handling resource, converting the test signal into a discrete-time digital signal representing the test signal, generating a discrete-time finite difference function comprising a first derivative of the discrete-time digital signal, transforming the discrete-time finite difference function into a frequency-domain transform of the discrete-time finite difference function. |
US09634773B2 |
Method and device for suppressing harmonic signals
A method for suppressing harmonic signals includes: mixing a first local oscillation signal with an input signal to obtain a first output signal, and mixing a second local oscillation signal with the input signal to obtain a second output signal, the first output signal including an n-order harmonic signal, n being a positive integer greater than 1; and adding the first output signal and the second output signal to suppress the n-order harmonic signal in the first output signal. The first local oscillation signal and the second local oscillation signal have different mark-space ratios but a same oscillation frequency. |
US09634766B2 |
Distributed acoustic sensing using low pulse repetition rates
A distributed acoustic sensing system and a method of obtaining acoustic levels using the distributed acoustic sensing system are described. The distributed acoustic sensing system includes an optical fiber, a light source to inject light into the optical fiber, and a photodetector to sample a DAS signal in each section of one or more sections of the optical fiber resulting from two or more points within the section on the optical fiber over a period of time. The system also includes a processor to process only a low frequency portion of the DAS signal to obtain the acoustic levels at each of the one or more sections on the optical fiber over the period of time, the low frequency portion of the DAS signal being less than 10 Hz. |
US09634765B2 |
Setting up hybrid coded-light—ZigBee lighting system
A lighting system (100) comprising a central lighting device (111), at least one satellite lighting device (121, 131), and a controller (141) for adjusting light settings, is provided. The controller is arranged for transmitting, in response to a user request (140), an association request over a first communication link (142). The central lighting device is arranged for receiving the association request and re-transmitting the association request over a second communication link by means of coded light (112). The satellite lighting device is arranged for transmitting, in response to receiving the association request, its identifier to the central lighting device. The identifier is only transmitted if an association process is enabled. The association process is enabled, in response to a user request, during a limited time period. The central lighting device is further arranged for associating, in response to receiving the identifier, the satellite lighting device with the central lighting device. |
US09634764B2 |
Estimating device and method for estimating
An estimating device includes a detector and an estimator. The detector detects a first parameter representing a ratio of a power of a signal component in received light to a power of a noise component in the received signal, a second parameter representing a sum of the power of the signal component and the power of the noise component, and a third parameter representing a sum of a power of a component being derived from cross phase modulation and being contained in the noise component and a power of a component being derived from spontaneously emitted light and being contained in the noise component. The estimator estimates, based on the first through the third parameters, a fourth parameter representing a ratio of the power of the signal component to a power of a component being derived from self phase modulation and being contained in the noise component. |
US09634760B1 |
System and method for calibration of an optical module
A system and method for calibrating an optical module. The optical module including a microprocessor with non-volatile memory is provided at a calibration station for measuring calibrated value of a device parameter against raw values starting from minimum value in each of multiple zones of a primary parameter with one or more secondary parameters at least being set to a basis calibration point to determine coefficients for generating a N-spline function for the multiple zones and multiple multipliers for each zone corresponding to multiple calibration points. The coefficients and multiple multipliers are stored in the non-volatile memory and reused respectively for calculating a basis calibrated value based on any current raw value of the primary parameter a N-spline function in particular zone and for determining a final multiplier by interpolation of the multiple multipliers associated with the one or more secondary parameters, leading to a calibrated value for any condition. |
US09634757B2 |
Vicinity-based undocking for a wireless docking application
This disclosure describes wireless communication techniques, protocols, methods, and devices applicable to a docking system environment in which aspects of wireless docking may function using vicinity-based undocking techniques. In some examples, the techniques of this disclosure enable a wireless docking center to undock a wireless dockee in a situation where a wireless dockee moves out of the vicinity of a wireless docking center so as to prevent malicious users from using peripheral devices available through the wireless docking center to interact with the wireless dockee without the wireless dockee user's knowledge. In other examples, the wireless dockee may undock itself from a wireless docking center when the wireless dockee moves out of the vicinity of a wireless docking center. |
US09634755B2 |
Method and system for femtocell positioning using low earth orbit satellite signals
Methods and systems for femtocell positioning using low Earth orbit (LEO) satellite signals may comprise receiving LEO RF satellite signals utilizing a LEO satellite signal receiver path when medium Earth orbit (MEO) signals are attenuated below a threshold needed for positioning purposes. A position of said wireless communication device (WCD) may be measured based on the received LEO RF satellite signals. The measured position of the WCD may be compared to a threshold radius defined by a stored initial position. Wireless communication services to the other WCDs may be enabled when the measured position is within the threshold radius. Reentry of the stored initial position may be requested when the measured position is outside of the threshold radius. The WCD may be disabled when the measured position of the WCD falls outside of the threshold radius more than a predetermined number of times. |
US09634754B2 |
Method and system for an internet protocol LNB supporting positioning
An Internet protocol low noise block downconverter (IP LNB), which may be within a satellite reception assembly, may be operable to determine location information and time information of the IP LNB, and may communicate the determined location information and the corresponding time information to a wireless communication device communicatively coupled to the IP LNB. The communicated location information may be configured to enable the wireless communication device to determine its location based on the determined location information and the corresponding time information. The IP LNB may determine the location information and/or the time information of the IP LNB based on global navigation satellite system (GNSS) signals, which may be received via the satellite reception assembly and may be processed via the IP LNB. The IP LNB may provide services based on the determined location information and/or the determined time information of the IP LNB. |
US09634741B2 |
Method and device for performing NIB CoMP transmission in wireless communication system
The present invention relates to a wireless communication system, and more particularly, to a method and device for performing or supporting NIB coordinated multi-point (CoMP) transmission in a wireless communication system. The method and device for performing NIB CoMP transmission in the wireless communication system according to an embodiment of the present invention include: receiving signaling comprising at least one CoMP hypothesis set and at least one benefit metric from a first network node, at a second network node; and performing CoMP transmission based on the at least one CoMP hypothesis set, at the second network node. The at least one CoMP hypothesis set comprises information on hypothetical operation of CoMP network nodes. |
US09634740B2 |
Radio communication system and communication control method
A radio communication system includes: a plurality of cells having different scrambling sequences, respectively, wherein at least two cells communicate with at least two user terminals connected to different serving cells; and a controller which controls the plurality of cells and provides a single scrambling sequence to said at least two cells and said at least two user terminals for control signal transmission and reception. |
US09634739B2 |
Wireless communication system and method thereof
The present invention relates to a wireless communication system and a method thereof. The wireless communication system comprises a signal encoding module for encoding a preset high-frequency audio signal frequency according to a preset encoding rule, and creating an encoding library for storing the code; a signal sampling module for sampling a high-frequency audio signal produced by a high-frequency audio signal generating device; a signal transformation module for performing Fourier transformation on the sampled audio signal firstly to transform the audio signal into frequencies, acquiring a main frequency from the transformed frequencies, and storing the acquired main frequency; a signal decoding module for decoding the main frequency into a preset code according to the code in the library; and an output module for outputting the decoded code. The wireless communication system and the method of the present invention do not need hardware supports, thereby reducing the cost. |
US09634734B2 |
Implantable medical device and power controlling method thereof
An implantable medical device includes a secondary coil for receiving an RF signal from the external terminal by an induced electromotive force excited by an external terminal primary coil. RF signal includes a power signal for energizing the medical device and data signal generated upon modulation of the power signal for use in controlling the medical device. The implantable medical device further comprises: a power processing block for converting the received power signal into DC for use by the implantable medical device; a data communication circuit activated by the DC supplied from the power processing block for demodulating the modulated data signal from the RF signal; a charge unit for charging a battery with the DC supplied from the power processing block; and a control unit to be operative by a power supply from the battery for controlling the implantable medical device according to the demodulated data signal. |
US09634730B2 |
Wireless energy transfer using coupled antennas
A power transmission system produces a magnetic field at a source that is wirelessly coupled to a receiver. Both the source and receiver are capacitively coupled LC circuits, driven at or near resonance. |
US09634727B2 |
NFC architecture
Disclosed is an integrated circuit, system or architecture suitable for NFC functionality and including an NFC companion block connectible to a power source and capable to providing a non-continuous power boost to NFC signals, inter alia, thereby facilitating use of a broader range of antennas, multiple antennas, and thereby providing greater NFC functionality and versatility Further disclosed is a detachable antenna embedded in a potentially detachable shell which closely fits a mobile device and is adapted for use with the above mentioned integrated circuit, system or architecture. |
US09634726B2 |
Seamless tethering setup between phone and laptop using peer-to-peer mechanisms
The subject technology discloses configurations for determining, at a first computing device, if a second computing device is within a predetermined distance of the first computing device. The subject technology then establishes, at the first computing device, a wireless near field communication (NFC) connection with the second computing device. Information for configuring a wireless tethering connection with the second computing device is then transmitted over the wireless NFC connection. Further, the subject technology receives, over the wireless NFC connection, confirmation that the wireless tethering connection has been configured. |
US09634725B2 |
Anticollision mechanism for an NFC device
A device includes near-field communication (NFC) control circuitry and transceiver circuitry. The transceiver circuitry is coupled to the NFC control circuitry. In a reader mode of operation, the NFC circuitry detects reception of NFC polling frames by the transceiver circuitry. When reception of an NFC polling frame is detected, the NFC control circuitry switches from the reader mode of operation to a card mode of operation. |
US09634721B2 |
Method and apparatus for sending SELT measurement signal, and control device
Embodiments of the present invention relate to a method and an apparatus for sending a single-ended loop testing SELT measurement signal, and a control device. The method for sending a SELT measurement signal includes: aligning a synchronization symbol of a digital subscriber line on which a SELT diagnosis needs to be performed with a synchronization symbol of at least one DSL line for data transmission, where the synchronization symbol of the digital subscriber line on which a SELT diagnosis needs to be performed and the synchronization symbol of the at least one digital subscriber line for data transmission are uplink or downlink synchronization symbols; and carrying a SELT measurement signal over the aligned synchronization symbol of the DSL line on which a SELT diagnosis needs to be performed, where the SELT measurement signal is used to detect transmission quality or a line fault of the DSL line. |
US09634714B2 |
HF-band wireless communication device
A HF-band wireless communication device includes a wireless IC configured to process a radio signal, a first substrate including a first inductor pattern coupled to the wireless IC, and a second substrate which includes a coil-shaped second inductor pattern coupled in series to the first inductor pattern. An L value of the first inductor pattern is greater than an L value of the second inductor pattern, and the L value of the first inductor pattern is dominant in a resonant frequency of a resonance circuit including the first and second inductor patterns. A winding diameter of the second inductor pattern is greater than a winding diameter of the first inductor pattern, and the second inductor pattern defines a main radiating element. |
US09634712B1 |
Mobile phone cover
Disclosed is a mobile phone cover, comprising a protective plate, a middle frame body and a flexible rubber bottom cap, wherein the protective plate is sealed above the middle frame body; the middle frame body comprises a hard rubber frame, a flexible rubber frame and a shockproof belt; the flexible rubber frame is disposed on the outer sides of the hard rubber frame; the shockproof belt is disposed on the inner sides of the hard rubber frame and partly penetrates the hard rubber frame to be connected and fixed with flexible rubber frame; the hard rubber frame partly extends outs of the outer sides of the flexible rubber frame and forms an anti-skidding belt; and the flexible rubber bottom cap is provided with a sealing groove matched with the sealing flange. The present invention has waterproof, dust-proof and shockproof functions, and has a feature of high stability. |
US09634708B2 |
Portable communication device with houing sealing member
A portable communication device includes: a housing (101); a substrate (301) disposed within the housing and including a wireless communication circuit (303); and a sealing member (401) configured to prevent entry of water into the substrate from the outside of the housing, wherein the sealing member includes an insulative base body, and an electrically conductive layer (402) covering a portion of a surface of the base body, wherein the electrically conductive layer is connected to an antenna terminal (302) of the wireless communication circuit and serves as an antenna element. |
US09634706B2 |
Receiver and receiving method of receiver
Embodiments of the present disclosure provide a receiver and a receiving method of the receiver, so that monolithic integration of multiple receiving channels can be implemented. The receiver includes: a zero intermediate frequency channel, performing in-phase/quadrature (IQ) down conversion on a radio frequency signal at a first frequency band using a frequency division or frequency multiplication signal of a first oscillation signal; and a superheterodyne channel, performing down conversion on a radio frequency signal at a second frequency band using the frequency division or frequency multiplication signal of the first oscillation signal, where the first frequency band is different from the second frequency band. According to the embodiments of the present disclosure, a zero intermediate frequency channel and a superheterodyne channel use a same oscillation signal or a same frequency division or frequency multiplication signal of the oscillation signal, thereby monolithic integration of multiple receiving channels can be implemented. |
US09634705B2 |
Radio receiver circuit, communication apparatus, and adaptation method
A receiver circuit comprising a transformer arrangement comprising a transformer structure, multiple and distributed receiver units arranged to be connected to one and same antenna via the transformer arrangement and arranged to operate on the same frequency and bandwidth as each other, wherein the transformer arrangement is arranged to input the antenna signal and to output signals at different output ports for the respective receiver unit, and a combiner circuit arranged to combine outputs of the multiple receiver units such that the combiner circuit outputs a combined signal, and corresponding communication apparatus, method and computer program are disclosed. |
US09634697B2 |
Antenna selection and tuning
A systems, methods and apparatus including a plurality of antennas are provided. The antenna system includes a first antenna, a second antenna, and a measurement device. The measurement device is configured to measure at least a first complex value indicative of an impedance matching of the first antenna and a second complex value indicative of an impedance matching of the second antenna. The antenna system includes an antenna selection controller configured to select one of the first antenna and the second antenna. The antenna selection controller making the selection based on the measurement of the first complex value of the first antenna and the measurement of the second complex value of the second antenna. |
US09634696B2 |
Transmitter for supporting multimode and multiband using multiple radio frequency (RF) digital-to-analog converters (DAC) and control method of the transmitter
A transmitter configured to support a multimode and a multiband, using radio frequency (RF) digital-to-analog converters (DACs), includes a first RF DAC configured to transmit a first signal in a first frequency band, and a second RF DAC configured to transmit a second signal in a second frequency band different from the first frequency band. The transmitter further includes an impedance controller configured to adjust impedance of one of the first RF DAC and the second RF DAC operating in an impedance matching mode to adjust a frequency range of another one of the first RF DAC and the second RF DAC operating in a data transmission mode. |
US09634695B1 |
Wireless devices having multiple transmit chains with predistortion circuitry
An electronic device may include wireless communications circuitry that has first and second digital predistortion circuits. The first predistortion circuit receives a first signal at a first frequency while the second predistortion circuit receives a second signal at a second frequency. The first circuit may perform predistortion operations on the first signal using non-unity predistortion coefficients to generate a predistorted signal. The second circuit may apply unity predistortion coefficients to the second signal to generate an undistorted signal. An adder may combine the predistorted and undistorted signals to generate a combined signal that is amplified by amplifier circuitry. An antenna may transmit the amplified signal. By over-distorting the first signal with the first predistortion circuit while the second predistortion circuit does not distort the second signal, the circuitry may mitigate non-linearity in the amplifier while allowing for carrier aggregation operations to be performed with minimal power consumption. |
US09634692B2 |
Transmitting apparatus and interleaving method thereof
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol. |
US09634687B2 |
VCO-based continuous-time sigma delta modulator equipped with truncation circuit and phase-domain excess loop delay compensation
A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed. |
US09634686B2 |
Hybrid digital-to-analog conversion system
A digital-to-analog conversion (DAC) circuit has a resistor ladder circuit controlled by high order bits and a resistor string circuit controlled by low order bits. The resistor ladder circuit includes a stem resistor and a branch resistor. The stem resistor has a stem resistance, and the branch resistor has a branch resistance that is substantially equal to two times of the stem resistance. The resistor string circuit includes a string current source, a string resistor, and a bridge resistor. The string current source is configured to generate a string current that is based on a ratio of a reference voltage divided by a predetermined resistance. The string resistor has a string resistance that corresponds to the predetermined resistance, and it is configured to selectively receive the string current based on a selection signal decoded from the low order bits. |
US09634683B1 |
Low power sigma-delta modulator architecture capable of correcting dynamic range automatically, method for implementing low power circuit thereof, and method for correcting and extending dynamic range of sigma-delta modulator automatically
A low power consumption sigma-delta modulator architecture capable of dynamic detection of output signal strength to change dynamic range, a method for implementing low power consumption circuit thereof, and a method for automatically correcting and extending dynamic range of the sigma-delta modulator are provided. An automatic correction unit is utilized to detect system output signal strength of the sigma-delta modulator, compare system input signal specifications to come out multiple sets of dynamic range curves, and thereby extract an appropriate combination of system order and feed-forward coefficients so as to extend the system dynamic range. The circuit architecture of the automatic correction unit is in a digital circuit form, including a digital signal processor, a counter and register array, a comparator, a digital coefficient controller, a feed-forward gain control unit and a system order control unit. |
US09634682B1 |
Analog-to-digital converting module for related light sensing device
An analog-to-digital module includes a sampling unit, for generating an output voltage between a positive output end and a negative output end according to a positive input voltage of a positive input end and a negative input voltage of a negative input end; a comparing unit, for generating a digital output signal according to magnitude relationship between the output voltage and a reference voltage; a variable current source, for generating a variable current according to the digital output signal at the negative input end in a first period according to a control signal; a measured current source, for generating a measured current at the negative input end; and an adjusting unit, for adjusting the output voltage according to the digital output signal in a second period according to the control signal; wherein the first period does not overlap the second period. |
US09634674B2 |
Semiconductor device
A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader. |
US09634673B2 |
Anti-islanding detection for three-phase distributed generation
Wobbling the operating frequency of a phase-locked loop (PLL), preferably by adding a periodic variation is feedback gain or delay in reference signal phase allows the avoidance of any non-detection zone that might occur due to exact synchronization of the phase locked loop operating frequency with a reference signal. If the change in PLL operating frequency is periodic, it can be made of adequate speed variation to accommodate and time requirement for islanding detection or the like when a reference signal being tracked by the PLL is lost. Such wobbling of the PLL operating frequency is preferably achieved by addition a periodic variable gain in a feedback loop and/or adding a periodically varying phase delay in a reference signal and/or PLL output. |
US09634671B2 |
Device for generating a clock signal by frequency multiplication
A pulse signal generator has an input receiving an initial pulse signal having an initial period, an oscillator generating an oscillator signal, a first stage and a second stage. The first stage is synchronized with the oscillator signal and configured to deliver a secondary pulse signal having a separation between successive pulses that is representative of an integer part of a division of the initial period by an integer N. The first stage further delivers an auxiliary signal representative of a fractional part of the division and containing, for each pulse of the secondary pulse signal, an indication of a time shift to be applied to the pulse taking into account the separation. The second stage is configured to receive the successive pulses and the corresponding time shift indications and generate successive corresponding pulses of an output pulse signal. |
US09634668B2 |
Pipelining of clock guided logic using latches
This application discloses the technique to pipeline the Clock Guided Logic. Latch based storage elements are used in CGL based design such that when first stage CGL elements are in precharge phase the second stage CGL elements are in evaluate phase and vice-versa resulting into higher design throughput. |
US09634664B2 |
Over-current and/or over-voltage protection circuit
A logic inverter with over-current protection, according to one embodiment, includes: a transistor, an input signal line coupled to a gate terminal of the transistor or a base region of the transistor, an output signal line coupled to a drain terminal of the transistor or a collector region of the transistor, a power supply line coupled to the drain terminal of the transistor or a collector region of the transistor, a pull up resistor between a power supply and one of: the drain terminal of the transistor and the collector region of the transistor, and a feedback resistor between ground and one of: a source terminal of the transistor and an emitter region of the transistor. Other systems, methods, and computer program products are described in additional embodiments. |
US09634662B2 |
High-voltage-tolerant pull-up resistor circuit
A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage. |
US09634660B2 |
Touch sensor with reduced anti-touch effects
In an embodiment, a system comprises a touch sensor. The touch sensor comprises an insulating substrate and a plurality of electrodes disposed on the insulating substrate. The plurality of electrodes comprises a drive line having a plurality of drive electrodes and a sense line having a plurality of sense electrodes. At least one of the electrodes comprises a first conductive material having a hole portion substantially free of the first conductive material. |
US09634658B2 |
Apparatus and method for a self-biasing circuit for a FET passive mixer
Embodiments are provided for biasing circuits with compensation of process variation without band-gap referenced current or voltage. In an embodiment, a circuit for biasing a field-effect transistor (FET) passive mixer comprises a series of diode-connected FETs, and a series of first resistors connected to a voltage source and the series of diode-connected FETs. Additionally, one or more second resistors are connected to the series of diode-connected FETs and to ground. In an embodiment method, the total number of the diode-connected FETs and the total number of the resistors, including the first and second series of resistors, are selected. The total number of the second resistors is then determined according to a defined relation between the selected total number of diode-connected FETs and the total number of resistors. |
US09634656B2 |
Current driver circuit
A current driver circuit includes: a current conversion unit including an input side transistor, in which a reference current is input, and multiple output side transistors, which output an output current corresponding to the reference current, and having an digital-analog conversion function for converting a digital control signal to an analog signal and a current amplifying function for amplifying the reference current according to an amplification ratio corresponding to the digital control signal; and an adjustment unit adjusting the digital control signal to be input into the output side transistors. When the adjustment unit adjusts the digital control signal, the current conversion unit changes the amplification ratio to gradually increase or decrease the output current, and controls a slew rate of the output current within a predetermined range. |
US09634654B2 |
Sequenced pulse-width adjustment in a resonant clocking circuit
A clock driver control scheme for a resonant clock distribution network provides robust operation by controlling a pulse width of the output of clock driver circuits that drive the resonant clock distribution network so that changes are sequenced. The clock driver control circuit controls the clock driver circuits in the corresponding sector according to a selected operating mode via a plurality of control signals provided to corresponding clock driver circuits. The pulse widths differ for at least some of the sectors during operation of digital circuits within the integrated circuit having clock inputs coupled to the resonant clock distribution network. The different pulse widths may be a transient difference that is imposed in response to a mode or frequency change of the global clock that provides an input to the clock driver circuits. |
US09634651B1 |
Delay apparatus
A delay apparatus includes a plurality of stage circuits, a first current source, a second current source and a switch. The stage circuits connected in series to each other. The first current source is coupled to the first power terminal of the first stage circuit. In some embodiments, the second current source is coupled to the first power terminal of the second stage circuit, and the first and second terminals of the switch are respectively coupled to the first power terminal of the first stage circuit and the first power terminal of the second stage circuit. In other embodiments, the first and second terminals of the switch are respectively coupled to the first power terminal of the second stage circuit and the second current source, and the first power terminal of the first stage circuit is coupled to the first power terminal of the second stage circuit through a wire. |
US09634649B2 |
Double sampling state retention flip-flop
Embodiments of a device and method are disclosed. In an embodiment, a flip-flop circuit is disclosed. The flip-flop circuit includes a master latch, a slave latch connected to the master latch, and a dual-function circuit connected between the master latch and the slave latch and configured to perform state retention and double sampling. |
US09634648B1 |
Trimming a temperature dependent voltage reference
A circuit includes a divider circuit block configured to generate a trim term signal (VBG_TRIM) that is temperature and process independent. The circuit further includes a processing circuit block configured to multiply a temperature dependent reference voltage signal (TAP_GG) by a factor, and to sum the trim term signal with a result of the multiplication to generate an output reference voltage (VGG). |
US09634647B2 |
Complex-valued synthesis filter bank with phase shift
An apparatus for generating real-valued output audio samples is disclosed. The apparatus includes a memory that stores complex-valued input subband samples, real-valued demodulated samples, and the real-valued output audio samples. The apparatus also incudes a phase shifter that shifts a phase of the complex-valued input subband samples by an amount equal to a previously added phase shift and a complex-valued synthesis filter bank that generates the real-valued output audio samples in response to the complex-valued input subband samples, the real-valued demodulated samples, and prototype filter coefficients. |
US09634643B2 |
Bulk acoustic wave resonator
Disclosed is a bulk acoustic wave resonator (BAWR). The BAWR includes a bulk acoustic wave resonance unit with a first electrode, a second electrode, and a piezoelectric layer. The piezoelectric layer is disposed between the first electrode and the second electrode. An air edge is formed at a distance from a center of the bulk acoustic wave resonance unit. |
US09634640B2 |
Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) and related components and methods
Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used. |
US09634632B2 |
System and method for processing signals to enhance audibility in an MRI environment
A system for processing signals to enhance patient audibility of a plurality of signals in an MRI environment is provided. The system includes an acoustic measuring device for measuring sound power levels generated by the M RI and a principal frequency component identifier for identifying principal frequencies measured by the acoustic measuring device. The system also includes an audio equalizer for controlling the amplitude and frequency of each of the plurality of signals in accordance with the principal frequencies. Further provided by the system is an attenuator for attenuating an overall sound level of the signals being processed and a dynamic range compression processor. |
US09634629B2 |
Semiconductor amplifier circuit
According to one embodiment, a semiconductor amplifier circuit includes: a first amplifier circuit including first and second P-type transistors; a second amplifier circuit including first and second N-type transistors; and first to seventh current mirror circuits. The first and second current mirror circuits are connected to drains of the first and second P-type transistors. The third and fourth current mirror circuits are connected to drains of the first and second N-type transistors. The sixth current mirror circuit is connected to the first, fourth and fifth current mirror circuits. The seventh current mirror circuit is connected to the second, third and fifth current mirror circuits. |
US09634628B2 |
Differential amplifier circuit for a capacitive acoustic transducer and corresponding capacitive acoustic transducer
An amplifier circuit, for a capacitive acoustic transducer defining a sensing capacitor that generates a sensing signal as a function of an acoustic signal, has a first input terminal and a second input terminal, which are coupled to the sensing capacitor and: a dummy capacitor, which has a capacitance corresponding to a capacitance at rest of the sensing capacitor and a first terminal connected to the first input terminal; a first buffer amplifier, which is coupled at input to the second input terminal and defines a first differential output of the circuit; a second buffer amplifier, which is coupled at input to a second terminal of the dummy capacitor and defines a second differential output of the circuit; and a feedback stage, which is coupled between the differential outputs and the first input terminal, for feeding back onto the first input terminal a feedback signal, which has an amplitude that is a function of the sensing signal and is in phase opposition with respect thereto. |
US09634622B2 |
Wireless communication device, method and power amplifier of the same
A wireless communication device that includes a power amplifier and an antenna is provided. The power amplifier includes a first and a second power amplifying paths and a first and a second matching modules. The first and the second power amplifying paths receive a first and a second input signals respectively. The first matching module includes a first input variable load and a first phase-shifting circuit to respectively adjust the magnitude and the phase of the first input signal to generate a first output signal. The second matching module includes a second input variable load and a second phase-shifting circuit to respectively adjust the magnitude and the phase of the second input signal to generate a second output signal. The antenna is coupled to the power amplifier to transmit the first and the second output signals. |
US09634620B2 |
Envelope tracking with reduced circuit area and power consumption
The present disclosure relates to envelope tracking with reduced circuit area and power consumption. In one embodiment, an envelope power converter includes a switching power converter configured to receive a supply voltage and provide an output based on a switching control signal. A holding inductor is coupled between the switching power converter and envelope power supply output node. An offset capacitor is coupled between the envelope power supply output node and control node. In response to a target envelope power supply output voltage, a control circuit is configured to generate the switching control signal and a control voltage to maintain envelope power supply signal at target voltage level. The control circuit is configured to generate switching control signal and control voltage such that supply voltage is provided by switching power converter to holding inductor and offset capacitor is charged to target level without changing voltage of envelope power supply signal. |
US09634618B2 |
Impedance matching arrangement for an amplifier
An impedance matching arrangement for an amplifier includes first and second metallic transmission lines arranged on a ground plane, the first metallic transmission line being connected with a first power amplification stage of the amplifier, the second metallic transmission line being connected with a second power amplification stage of the amplifier; wherein the first and second metallic transmission lines are electrically coupled for transmitting an RF signal amplified by the first power amplification stage to the second power amplification stage. |
US09634617B2 |
Multistage amplifier circuit with improved settling time
Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions. |
US09634612B2 |
Efficiency for linear amplifier of envelope tracking modulator
There is disclosed an envelope tracking power supply arranged to generate a modulated supply voltage in dependence on a reference signal, comprising a first path for tracking low frequency variations in the reference signal and a second path for tracking high frequency variations in the reference signal, the second path including a linear amplifier, wherein the output of the linear amplifier comprises a current source and a current sink connected to the high frequency output, there further being provided a DC offset current at the high frequency output. |
US09634611B1 |
Method for improving stable frequency response of variable gain amplifier
A variable gain amplifier having stabilized frequency response for widened gain control range. A resistor-capacitor compensation network is provided between two differential current input ports and corresponding emitter nodes of cross-coupled four transistors in the variable gain amplifier to desensitize the gain control voltages to the system noise and provide compensation to the VGA frequency response when the differential gain control voltage varies the gain setting, yielding a substantially stabilized frequency response over a −3 dB bandwidth ranging from 1 GHz to 60 GHz with a widened gain control range up to 12 dB without increasing power consumption. |
US09634610B2 |
60 GHz wideband class E/F2 power amplifier
A novel and useful fully integrated switched-mode wideband 60 GHz power amplifier architecture. Using an appropriate second-harmonic termination of its output matching network, the required systematic peak current of the final stage is reduced such that the PA functions as a class-E/F2 switched-mode PA at saturation. In addition, low/moderate magnetic coupling factor transformers in the intermediate stages enable the PA to reach a high power added efficiency (PAE) and bandwidth product. Transformers of low/moderate coupling are also utilized in the preliminary stages of the PA to improve the overall bandwidth. In addition, the PA exploits the different behavior of the output impedance matching network for differential mode (DM) and common mode (CM) excitations. The PA is also stabilized against the combination of DM and CM oscillation modes. The PA also provides a technique to stabilize transformer-based mm-wave amplifiers against various modes of undesired oscillations. |
US09634609B2 |
Switching circuit
There is provided a switching circuit for an active mixer. The switching circuit comprises a first pair of parallel switching devices and a second pair of parallel switching devices. The first and second pairs of parallel switching devices are arranged in a stacked configuration between an input node at which an input current comprising a first input frequency signal is received and a pair of differential output nodes. The first pair of switching devices are controlled by a second input frequency signal. The second pair of switching devices are controlled by a phase-shifted counterpart of the second input frequency signal. A common node between the first switching devices of the first and second pairs of switching devices is electrically coupled to a common node between the second switching devices of the first and second pairs of switching devices. |
US09634603B2 |
Power limiting for motor current controllers
A motor controller a pulse-width modulation (PWM) circuit, a power limit circuit, and an inverter. The PWM circuit is configured to output initial count outputs based on a current command. The power limit circuit includes a peak current detector, a divider, and a dynamic limiter. The power limit circuit is configured to provide updated count outputs based on the initial count outputs, a sensed current, and a power threshold. The inverter is controlled by the updated count outputs and configured to provide output power to a motor. The sensed current is sensed from the output power to the motor. |
US09634600B2 |
Drive performance measurement
A motor drive is provided with integrated frequency response analysis tools for generating drive performance metrics that are independent of motion profile and tuning. The metrics are broadly applicable to a wide range of applications, tunings, and load types, and can be used to fairly compare performance across different drives models and assist in drive selection. The frequency analysis tools include a transformation algorithm that reduces or eliminates spectral leakages, a signal generation component that scales the test input signal as a function of frequency avoid saturation based on defined limits of the controlled system, and a phase unwrapping algorithm that correctly unwraps the phase of open-loop and closed-loop response curves. The frequency response analysis tools yield an open-loop response, a closed-loop response, a tracking error response, and a disturbance rejection response, which are used to derive performance metrics for the drive. |
US09634598B2 |
Motor current mapping
An electric machine combined with an electronic control unit including a set of onboard maps of a same setpoint parameter on the basis of first and second operating variables of the machine, each of the maps being associated with a different level of a third operating parameter of the electric machine. The maps include ranges of authorized values, and at least one range of extrapolated values. The electronic control unit is configured, for values of the third parameter not associated with one of the onboard maps, to use interpolated values between two authorized values, or between one authorized value and one extrapolated value. |
US09634596B2 |
Hybrid power generation with variable voltage flux
The present invention generally relates to power production and energy storage methods requiring high efficiency, particularly relating to a power generator and transmission system utilizing a variable voltage flux actuator that varies the output voltage with substantially lower speed interdependency in addition to varying the power output within a range of speed operation particularly for direct current power consumers. The power generator system is then connected to a set of voltage regulators, with the entire system organized for maximized conversion efficiency. |
US09634594B2 |
Methods and systems for automatic rotation direction determination of electronically commutated motor
A method for determining a direction of rotation for an electronically commutated motor (ECM) is described. The motor is configured to rotate a blower and the method comprises rotating the blower using the ECM and determining if the resulting blower rotation is indicative of the desired direction of rotation for the blower. |
US09634588B2 |
Device and method of 6-step controlling inverter of motor driving system
A device and a method of 6-step controlling of an inverter of a motor driving system are provided. The device and method and apply a voltage to a motor by adopting a 6-step control scheme capable of maximally using an input voltage of the inverter to improve output efficiency of the inverter and the motor and thus improve fuel efficiency of an environmentally friendly vehicle. |
US09634586B2 |
Fail-safe apparatus for inverter
There is provided a fail-safe apparatus for an inverter that can suppress the voltage of a DC power source from rising when the voltage of the DC power source becomes excessive, due to an abnormality caused in an inverter that performs driving and electric-power generation by use of a synchronous motor in which a permanent magnet is utilized as a magnetic-field magnet. The fail-safe apparatus for the inverter includes an excessive voltage detection circuit for detecting a state of excessive voltage while monitoring the voltage of the DC power source of the inverter and a drive switching circuit for switching a driving method for a semiconductor switching device between three-phase PWM driving and three-phase short-circuiting driving in accordance with the state of an excessive voltage detection circuit. |
US09634579B2 |
Systems and methods for controlling inverters
A method of controlling an inverter includes receiving a target waveform for output voltage of an inverter phase, calculating a phase bias for an inverter phase using the target waveform, biasing the target waveform using the phase bias, and generating a switching device command signal by comparing the biased target waveform to a carrier waveform. The switching device command signal has a switching patter that reduces midpoint current in an inverter input lead and common mode voltage in an inverter output lead. |
US09634576B2 |
System and method for unified common mode voltage injection
A power conversion system includes at least one multi-level power converter and a controller coupled to the at least one multi-level power converter. The controller includes a first CMV injection module and a second CMV injection module. The first CMV injection module generates a first CMV signal for modifying at least one voltage command to achieve a first function in association with operation of the power conversion system. The second CMV injection module generates a second CMV signal based at least in part on a local limit either for modifying the at least one voltage command or for further modifying the at least one modified voltage command to achieve a second function in association with operation of the power conversion system. |
US09634573B2 |
Power converter including two converter circuit modules sharing one DC capacitor module
The disclosure provides a power converter including a cabinet, a first converter circuit module, a second converter circuit module, and a DC capacitor module. The first converter circuit module includes at least one first bridge arm. The second converter circuit module includes at least one second bridge arm. The first converter circuit module, the second converter circuit module, and the DC capacitor module are disposed in the cabinet. The second bridge arm and the first bridge arm are arranged side by side in parallel. The DC capacitor module is electrically connected between the first bridge arm and the second bridge arm, so that the first bridge arm and the second bridge arm share the DC capacitor module. |
US09634571B2 |
Driver device and driving method for driving a load
The present invention relates to a driver device (10) for driving a load (18), comprising input terminals (14, 16) for connecting the driver device (10) to a voltage supply (12) and for receiving an input voltage (V10) from the voltage supply (12), at least one output terminal for connecting the driver device (10) to the load (18), an electromagnetic converter unit (24) for converting a drive voltage to an output voltage (V20) for powering the load (18), two controllable switches (20, 22) connected to the input terminals (14, 16) for providing a variable voltage as the drive voltage to the electromagnetic converter unit (24), and a control unit (28) for controlling a first of the controllable switches (20, 22) on the basis of an electrical signal (V12) measured at a member of the electromagnetic converter unit (24) and a threshold level (40, 52) and for controlling a second of the controllable switches (20, 22) on the basis of a control parameter (50, tOFF) set to a value that the on-times of the controllable switches (20, 22) have independent durations. |
US09634566B2 |
Controlling the common mode voltage of a non-isolated buck-boost converter
A switching power stage for producing an output voltage to a load may include a power converter and a controller. The power converter may include a power inductor and plurality of switches arranged to sequentially operate in a plurality of switch configurations. The controller may be configured to, based at least on an input signal to the switching power stage, determine the differential output voltage to be driven at the load, and based on the differential output voltage to be driven at the load, apply a switch configuration from the plurality of switch configurations to selectively activate or deactivate each of the plurality of switches in order to generate the differential output voltage. |
US09634565B2 |
Modulation method, and modulation module and voltage converting device thereof
A modulation method, for a voltage converting device, includes generating a first modulation signal according to an input voltage and a first output voltage; generating a second modulation signal according to the input voltage and a second output voltage; adjusting the first modulation signal and the second modulation signal according to a clock signal for making a first starting time of the first modulation signal be different from a second starting time of the second modulation signal; and generating the first output voltage and the second output voltage according to the input voltage, the first modulation signal and the second modulation signal. |
US09634557B2 |
Voltage boost circuit
A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase. |
US09634556B2 |
Converter, controller, and control method
A control method for a power converter is provided. The power converter includes an inductor, and a switch selectively turned on according to a control signal. The control method includes determining an on-time and a falling time according to a voltage information or a current information of the power converter; determining a switching period of the control signal according to the on-time, the falling time, and a resonant period corresponding to the inductor and a parasitic capacitance of the switch; adjusting the switching period by comparing the switching period with a first threshold period and a second threshold period; generating the control signal having the switching period when the switching period is greater than the first threshold period and less than the second threshold period or when the switching period is greater than the second threshold period and the power converter operates at over 50% of a rated power. |
US09634546B2 |
Multi-shaft linear motor and component transfer apparatus
A multi-shaft linear motor formed by a plurality of linear motors each provided with a magnetic body and an armature and adapted to produce a force causing the magnetic body and the armature to be relatively displaced along a given linear moving direction by interaction of magnetic fluxes generated between the magnetic body and the armature during an operation of supplying electric power to the armature. Each of the single-shaft linear motors includes a base plate. Base plate has a base surface defining the moving direction, wherein the stator is fixed onto the base surface along the moving direction, and the mover is attached onto the base surface in a movable manner reciprocating along the moving direction and in opposed relation to the stator. Single-shaft linear motors are stacked in a stacking direction perpendicular to the base surface such that the single-shaft linear motors are individually detachable as a unit. |
US09634540B2 |
Magnetic suspension planar motor with structure of superconductor excitation
A magnetic suspension planar motor comprises a structure of superconductor excitation. A primary base plate is in a shape of board. Armature windings are fixed on an air gap side of the primary base plate. A secondary base plate in a secondary structure is evenly divided into 2 h*2 h magnet cells. 2 h2 superconducting magnets are respectively fixed in the magnet cells on the secondary base plate, which resembles a checkerboard pattern. The superconducting magnets are adjacent to each other, neither in a horizontal direction nor in a vertical direction. The superconducting magnets are magnetized parallelly, and magnetization directions of the superconducting magnets are perpendicular to a surface on an air gap side of the secondary base plate. The superconducting magnets in a same row or column have same magnetization directions, and the superconducting magnets in adjacent rows columns have contrary magnetization directions. A cooling container shields all of the superconducting magnets. |
US09634539B2 |
Radial magnetic bearing for magnetic support of a rotor
A radial magnetic bearing for magnetic bearing of a rotor has a stator which includes a magnetically conductive stator element, arranged circulating around a rotor. The stator element has recesses running in the axial direction of the stator element in which electrical lines from coils are arranged, wherein magnetic fields can be generated by the coils which hold the rotor suspended in an air gap arranged between the rotor and stator. A softer progression of the components of magnetic flow density in the radial direction is achieved by design measures on the transitions from one magnetic pole to the next magnetic pole, which results in a reduction of the eddy currents induced in the rotor. |
US09634536B2 |
Systems and methods for isolating a conduit enclosure using an adapter plate for an explosion proof motor
An enclosure system includes a stator enclosure defining an enclosure opening, and an adapter having a first entry port, and defines a center cavity having a first volume. Enclosure system includes a conduit enclosure coupled to one or more of stator enclosure and adapter. Conduit enclosure includes a base member having at least one side wall, a rear wall coupled to side wall and defining a second entry port, an interior cavity, and a terminal connection block coupled to base member and having at least one terminal. Enclosure system includes at least one electrical lead extending from the stator enclosure through first enclosure opening, through first entry port, through center cavity, through second entry port, and into the interior cavity. Electrical lead occupies a portion of first volume and leaves a remaining volume. Enclosure system includes sealing compound coupled with adapter such that substantially all of remaining volume is occupied. |
US09634535B2 |
Equipment including epitaxial co-crystallized material
An electric submersible pump motor can include a housing; and a hermetically sealed cavity defined at least in part by the housing that includes at least one material susceptible to hydrolysis, and a polymeric material that includes epitaxial co-crystals of perfluoroalkoxy (PFA) and polytetrafluoroethylene (PTFE). Various other apparatuses, systems, methods, etc., are also disclosed. |
US09634533B2 |
Motor with a stator having four separate corner bobbins/insulators and molded resin insulation around tooth completely enclosing the coil and manufacturing method thereof
A stationary portion of a motor includes resin bodies including an inner resin portion and an outer resin portion. The inner resin portion is between a tooth and a coil and between the tooth and an insulator. The outer resin portion covers circumferentially outer sides and axially outer sides of the coil. The inner and outer resin portions are continuous with each other through a connecting resin portion. The insulator includes an opening portion extending along circumferential side surfaces of the tooth. The inner resin portion is in contact with the circumferential side surfaces of the tooth and a conducting wire in the opening portion. Heat generated in the coil is transferred to the tooth through the resin body. A path along which the heat is transferred from the coil to the tooth is secured, and dissipation of heat out of the motor is promoted. |
US09634531B2 |
Electric motor with embedded permanent magnet, compressor, and refrigeration/air-conditioning device
In an interior permanent magnet motor, at least one magnetic pole center slit and a plurality of side slits are formed between a rotor outer peripheral surface of a rotor and a radially-outer insertion hole contour surface of a magnet insertion hole. The plurality of side slits are formed so that at least one side slit is formed on each of both sides of the magnetic pole center slit in a width direction. The area of the magnetic pole center slit is smaller than the area of each of the plurality of side slits. A width of each of the plurality of side slits is larger than an interval between the adjacent slits. |
US09634526B2 |
Rotor for a rotating electric machine and rotating electric machine
A rotor for a rotating electric machine includes a rotor sheet stack arranged on a rotor shaft, and at least one metallic functional component made of a material comprising iron and also chromium in a proportion of at least 18% and at most 19% by weight and optionally nickel in a proportion of at least 12% and not more than 13% by weight. |
US09634523B2 |
System and method for transferring electric energy to a vehicle using a plurality of segments of a conductor arrangement
A system for transferring electric energy to a vehicle. The system comprises an electric conductor arrangement which produces an alternating electromagnetic field, transfers electromagnetic energy to the vehicle, and includes a plurality of consecutive segments. Each segment extends along the path of travel of the vehicle. The system includes an alternating current supply for conducting electric energy to the segments which are electrically connected in parallel to each other with the alternating current supply. Each segment is coupled to the supply via an associated switching unit adapted to switch on and off the segment by connecting or disconnecting the segment to/from the supply. Each segment is coupled to the associated switching unit via a constant current source adapted to keep the electric current through the segment constant while the segment is switched on independently of the electric power which is transferred to one or more vehicles. |
US09634522B2 |
Power grid data monitoring and control
A method for identifying conditions that correlate with one ore more events related to operation of a power grid. The method includes the determining one or more distinguishing characteristics of a first chunk. The first chunk includes data elements relevant to operating a power grid. The method also includes determining whether a distinguishing characteristic of the first chunk correlates with a distinguishing characteristic of one or more of a plurality of second chunks. Each second chunk includes a plurality of data elements corresponding with the data of the first chunk. The method further includes determining whether a second chunk, having a distinguishing characteristic equivalent to a distinguishing characteristic of the first chunk, is associated with the one or more events. In addition, the method includes determining whether a second chunk, having an association with the one or more events and a distinguishing characteristic equivalent to a distinguishing characteristic of the first chunk, is substantially identical to the first chunk. |
US09634521B2 |
Power control apparatus, power supply control method, and power supply control program
There is provided an apparatus including a power control apparatus for supplying power from an external power source or power from private power supply equipment to a plurality of electrical appliances, the power control apparatus including a power failure detection device for detecting an interruption of power supply from the external power source and for measuring a power supply interruption duration, a storage device for storing power supply information regarding power supply from the private power supply equipment to the electrical appliances, and a power supply control device for controlling the power supply from the private power supply equipment to the electrical appliances based on the power supply information stored in the storage device when the power supply interruption duration measured by the power failure detection device is in excess of a predetermined time period. |
US09634517B2 |
Battery charging mode selection
A device includes a battery connector to couple to a rechargeable battery to provide power, a power manager coupled to the battery connector to charge the battery when connected to the battery connector in a first charging mode and a second charging mode, a power jack to receive a power plug, and a switch coupled to the power jack and the power manager and responsive to user actuation via the power plug to select the second charging mode. |
US09634513B2 |
Methods and systems of a battery charging profile
Embodiments include an electronic device, which contains circuitry configured to acquire charging parameters corresponding to a rechargeable battery of the electronic device. The circuitry is also configured to identify an operation state of one or more signal processing components of the electronic device, and estimate a first temperature profile for the electronic device based on an operation state of the one or more signal processing components. The circuitry is also configured to adjust, in multiple stages, a charging current of the rechargeable battery in response to the estimated first temperature profile and a threshold temperature for the electronic device. |
US09634512B1 |
Battery backup with bi-directional converter
An electronic uninterruptible power supply unit includes one or more battery connections. A bi-directional converter is in electrical communication with the one or more battery connections and arranged to (a) provide power at a first controlled voltage from the one or more battery connections as a boost converter when power is determined to not be available from a power source; and (b) provide charge to the one or more battery connections by providing power at a second controlled voltage that is different from the first controlled voltage when power is determined to be available from the power source. First and second MOSFET switches are connected in series with the one or more battery connections and arranged as a bi-directional switch that controls charging current for the one or more battery connections. |
US09634511B2 |
Charging control method for a rechargeable battery and portable computer
Disclosed are charging control methods for a rechargeable battery and portable computers. The charging control method includes acquiring a control parameter for a charge current of the rechargeable battery; modifying, based on the control parameter, the charge current from a first charge current to a second charge current less than the first charge current; and charging the rechargeable battery with the second charge current. Compared with conventional methods of charging the battery always with the maximal charge current, the present disclosure can improve the battery's lifetime. |
US09634509B2 |
Method for rapid charging and electronic device thereof
A method and an apparatus for rapid charging in an electronic device are provided. In a method for charging a battery of an electronic device, an operation environment of the electronic device is determined. A charging current corresponding to the operation environment of the electronic device is set. Battery charging is started using the set charging current. The battery is charged using a maximum allowed charging current, such that a battery charging time may be reduced. |
US09634508B2 |
Method for balancing frequency instability on an electric grid using networked distributed energy storage systems
Embodiments of the present invention include control methods employed in multiphase distributed energy storage systems that are located behind utility meters typically located at, but not limited to, medium and large commercial and industrial locations. These distributed energy storage systems can operate semi-autonomously, and can be configured to develop energy control solutions for an electric load location based on various data inputs and communicate these energy control solutions to the distributed energy storage systems. In some embodiments, one or more distributed energy storage systems may be used to absorb and/or deliver power to the electric grid in an effort to provide assistance to or correct for power transmission and distribution problems found on the electric grid outside of an electric load location. In some cases, two or more distributed energy storage systems are used to form a controlled and coordinated response to the problems seen on the electric grid. |
US09634507B2 |
Power source supplying device for electronic appliance
A power supply device of an electronic device including: a body formed to wear or to carry in a user body; a support groove formed in an upper portion of the body and that receives the electronic device; an insertion groove formed to insert from the outside to the inside of the body; a battery inserted into the insertion groove and that charges power applied from the outside and that charges the electronic device through charged power; a first through hole punched in the support groove so that the electronic device and the battery contact; and a pressing portion that presses to enclose the electronic device received in the support groove and that is provided to receive in the body regardless of a shape or a size of the electronic device. |
US09634505B2 |
Charging and discharging control device, charging and discharging control system, charging and discharging control method, and program
Within a range of a second limit current (±I_adj_max) set based on the performance of a secondary battery (140), a charging and discharging control device (170) determines an upper limit value (I_adj_limit) or a lower limit value (−I_adj_limit) of a state of charge (SOC) adjustment current (I_adj) in accordance with load power (required power and regeneration power) of a vehicle (100). Using an adjustment logic determined based on these limit values of the SOC adjustment current (I_adj), the charging and discharging control device (170) also determines the SOC adjustment current (I_adj) corresponding to an actually measured SOC value of the secondary battery (140). |
US09634498B2 |
Electrical storage system and equalizing method
An electrical storage system includes electrical storage elements connected in series with each other and being charged or discharged; discharge circuits respectively connected in parallel with the electrical storage elements and discharging the corresponding electrical storage elements; and a controller controlling operations of the discharge circuits. The controller calculates a first SOC difference using a full charge capacity of each electrical storage element. The first SOC difference is a difference in SOC between the electrical storage elements and arises due to a difference in full charge capacity between the electrical storage elements. The controller calculates a second SOC difference that is a difference in SOC between the electrical storage elements at the moment the second SOC difference is calculated. When the second SOC difference is larger than the first SOC difference, the controller brings the second SOC difference close to the first SOC difference through a discharge with the discharge circuits. |
US09634496B2 |
Powering up a wireless power receiving device
Techniques for powering up a wireless power receiving device are described herein. An example computing device includes a power receiving unit to wirelessly receive power from a power transmitting unit. The platform hardware includes a System on a Chip (SoC), a multicomm device, and a power sequence manager. The multicomm device is for wireless communication with two or more communication standards. One of the communication standards is used as a side channel for communicating with the power transmitting unit. The power sequence manager component manages activation of platform components of the platform hardware during a low battery cold boot condition. Upon detecting wireless power, the multicomm device is configured to automatically activate and the power sequence manager component is to suppress activation of other platform components of the platform hardware. |
US09634494B2 |
Power amplifier for wireless power transmission
A power signal source may provide current to a transmit coil to support wireless power transmission. The power signal source may include one or more modulators in parallel that may be phase delayed by an angle with respect to one another. The phase delay angle allows for adjustment of the magnitude of the current. The current provided to the transmit coil may be independent of the load of the transmit coil. |
US09634493B2 |
Resonant frequency control method, electric power transmitting device, electric power receiving device in magnetic resonant type power transmission system
In a resonant frequency control method in a magnetic field resonant coupling type power transmission system transmitting an electric power from a power transmitting coil to a power receiving coil using magnetic field resonance, a high-speed, accurate and real-time adjustment of the resonant frequency of a coil is realized. The phase of a voltage supplied to a power transmitting coil and the phase of a current that flows in the power transmitting coil or a power receiving coil is detected and the resonant frequency of the power transmitting coil or the power receiving coil is varied such that the phase difference between them becomes a target value. |
US09634490B2 |
Dynamic voltage restoration system and method
A system, in one embodiment, includes a voltage fault detection system. The voltage fault detection system may be configured to acquire a reference voltage signal from a power line to determine if a voltage sag condition is present in the power line, determine a correction voltage for correcting the voltage sag condition, use the reference voltage to produce the correction voltage, and apply the correction voltage to the power line. |
US09634488B2 |
Load scheduling optimization in distributed system
A power distribution management system is disclosed for optimal power distribution for a predetermined class of loads and other loads. The power distribution management system include a substation for distributing power supply to a load network, where the load network includes the predetermined class of loads and other loads and the substation includes a plurality of feeders. The power distribution management system includes an optimizer for generating an optimal load schedule for a control period for the predetermined class of loads. The power distribution management system also includes a communication interface for communicating between the plurality of individual loads and/or the optimizer. |
US09634484B2 |
Battery system, vehicle with battery system and method of operating a battery system in a vehicle
A battery system, a vehicle having a battery system, and a method for operating a battery system. The battery system has a plurality of cells, a load circuit, a current sensor to detect current flowing in the load circuit, a pre-charging circuit to limit the current flowing through the load circuit, a disconnecting apparatus in a load circuit section of the load circuit, the load circuit section being bypassed by the pre-charging circuit, a first consumer circuit and a second consumer circuit arranged in parallel with one another and connected to the load circuit, a first fuse assigned to the first consumer circuit, a second fuse assigned to the second consumer circuit and an electronics unit to evaluate signals of the current sensor and which determines whether at least one of the first fuse and the second fuse has blown based on signals of the current sensor. |
US09634483B2 |
Electrostatic discharge (ESD) protection circuit with EOS and latch-up immunity
An electrostatic discharge (ESD) protection circuit with electrical overstress (EOS) and latch-up immunity has a main ESD circuit, a voltage detection circuit and an electrostatic driving circuit. The main ESD circuit is coupled between a first rail and a second rail and has a control end. The main ESD circuit is configured to establish an electrical connection between the first rail and the second rail based on a voltage of the control end. The voltage detection circuit is coupled between the first rail and the second rail for setting the voltage of the control end when a voltage of the first rail is greater than a limiting voltage. The electrostatic driving circuit is used to drive the main ESD circuit when an ESD phenomenon occurs. |
US09634479B2 |
Noise propagation immunity of a multi-string arc fault detection device
Systems and methods of detecting arcing in a DC power system that can provide improved noise propagation immunity. The system includes at least two current sensors for monitoring at least two current outputs, respectively. The current sensors have reverse polarities, and are configured and arranged in parallel to provide a combined current output signal. The current sensors monitor the respective current outputs, which are provided for monitoring by the current sensors over at least two adjacent conductors. If arcing occurs at a location on a first conductor, then arcing (adjacent conductor crosstalk), having an arc current signature like that of the arcing on the first conductor, can occur at a location on the other adjacent conductor. The system can effectively cancel out such adjacent conductor crosstalk within a photovoltaic (PV) system, thereby improving the capability of an arc fault detection device for detecting arcing at the PV string level. |
US09634478B2 |
Electromechanical apparatus and electrical switching apparatus employing electronic circuit to condition motor input power
An electrical switching apparatus includes separable contacts, an operating mechanism structured to open and close the separable contacts, and a motor cooperating with the operating mechanism to open or close the separable contacts. The motor includes an input structured to input power. The electrical switching apparatus also includes an electronic circuit structured to condition the input power to the motor. |
US09634469B2 |
Complex electrically operated ground and test device using vacuum circuit interrupters and methods of operating the same
A grounding and test device includes a chassis configured to be removably installed in a drawout switchgear compartment (e.g., a breaker compartment) having a load conductor and a line conductor therein. The device also includes an interconnection bus supported by the chassis and a ground conductor supported by the chassis. The device further includes a first vacuum circuit interrupter supported by the chassis and configured to selectively couple and decouple the interconnection bus and the line conductor, a second vacuum circuit interrupter supported by the chassis and configured to selectively couple and decouple the interconnection bus and the load conductor and a third vacuum circuit interrupter supported by the chassis and configured to selectively couple and decouple the interconnection bus and the ground conductor. |
US09634468B2 |
Switchgear cabinet including electrical connection clamping device
A switchgear cabinet comprising a cabinet frame, first and second current converter devices, and an electrical connection clamping device. The first current converter device has first DC voltage positive and negative potential connection elements. The second current converter device has second DC voltage positive and negative potential connection elements. The electrical connection clamping device has an electrically conductive first clamping element and an electrically conductive second clamping element which is electrically insulated from the electrically conductive first clamping element, and a pressure-generating device which generates a pressure that pushes the second clamping element towards the first clamping element. The first clamping element is mechanically connected to the cabinet frame by an electrically non-conductive insulation body such that the first clamping element is electrically insulated from the cabinet frame. The invention provides a switchgear cabinet for housing current converter devices, wherein the current converter devices can be replaced quickly and easily. |
US09634465B2 |
Optical device and optical module
An optical device includes an active layer disposed over a semiconductor substrate, a diffraction grating disposed over the active layer, a clad layer partly disposed over the diffraction grating, at least one first burying material layer disposed beside side surfaces of end portions of the clad layer over the diffraction grating, and at least one second burying material layer disposed beside side surfaces of a center portion of the clad layer over the diffraction grating. A refractive index of the at least one first burying material layer is different from a refractive index of the at least are second burying material layer. |
US09634463B2 |
Optical module installing a semiconductor optical amplifier and process of assembling the same
An optical module providing a semiconductor optical amplifier (SOA), and a process to assembly the optical module are disclosed. The optical module provides front and rear coupling units each optically coupled with the SOA and fixed to the housing enclosing the SOA. The housing has a slim wall fixing a lens holder soldered to the slim wall. The front and/or rear coupling unit is fixed to the lens holder by YAG laser welding after the active alignment by using a spontaneous emission of the SOA, and amplified emission of externally provided test beam. |
US09634457B2 |
Extended spectrum supercontinuum pulse source
A source of optical supercontinuum radiation comprises a length of microstructured optical fiber and a pump laser adapted to generate lasing radiation at a pump wavelength. The length of microstructured optical fiber is arranged to receive lasing radiation at the pump wavelength to generate optical supercontinuum radiation and comprises a core region and a cladding region which surrounds the core region. The source of optical supercontinuum radiation is arranged such that at a location along the length of the microstructured optical fiber (a) the microstructured optical fiber comprises a group index (GI) versus wavelength curve having a zero crossing wavelength (ZCW) at which the group velocity dispersion has a zero crossing and such that the GI increases for wavelengths away from the ZCW such that the curve includes group indices that are greater than the GI at the ZCW for wavelengths greater than as well as less than the ZCW; (b) light having a wavelength of greater than 2000 nm propagates along the length of microstructured optical fiber and has a GI that is matched to the GI of light that propagates along the length of microstructured optical fiber and that has a wavelength of less than 400 nm; and (c) the pump wavelength is within 200 nm of the ZCW. |
US09634455B1 |
Gas optimization in a gas discharge light source
One or more operating characteristics of a light source are adjusted by estimating a plurality of extreme values of operating parameters of the light source while operating the light source under a set of extreme test conditions. For each extreme test condition, a group of pulses of energy is supplied to a first gas discharge chamber of the light source while operating the first gas discharge chamber under the extreme test condition to produce a first pulsed amplified light beam; a group of pulses of energy is supplied to a second gas discharge chamber of the light source while operating the second gas discharge chamber under the extreme test condition to produce a second pulsed amplified light beam. An extreme value of an operating parameter for the extreme test condition is measured to thereby estimate the extreme value of the operating parameter. |
US09634453B2 |
Active optical isolators and active optical circulators
An apparatus includes a controllable optical interferometer having first and second external optical ports and a traveling-wave modulation electrode. The apparatus also includes an electrical driver configured and connected to apply a voltage with a periodic modulation to the traveling-wave modulation electrode such that the controllable optical interferometer operates as an optical isolator over a wavelength range. |
US09634451B2 |
Crimping pliers
The invention relates to crimping pliers (1). The crimping pliers comprise a spring element (7) which is located in the force flow between hand levers (3, 5) and dies (12). The spring element (7) builds a force-displacement-compensation element (8) which provides the option to be able to crimp workpieces with different cross-sectional areas with the crimping pliers (1). According to the invention, the spring element (7) which builds the force-displacement-compensation element (8) is built in the region of the pliers head (4) of the crimping pliers (1). Preferably, the spring element (7) is a spring in the shape of an arc of a circle or a spiral spring (44) which extends in circumferential direction around the die axis (13). |
US09634446B2 |
Connector, docking station and connecting assembly with the connector
A connector, configured to extend a plurality of interfaces, includes a housing and a plurality of pins extending out of the housing. The housing is designed to accommodate a plurality of contacts spaced apart in sequentially numbered contact locations including HDMI contact locations designated for a HDMI port, configured to couple to at least one HDMI interface via HDMI pins of the plurality of pins; USB contact locations designated for a USB port; a power contact location designated for a power port; and a detection contact location designated for a detection port, configured to detect the types and quantities of the plurality of interfaces via a detection pin. A docking station and a connecting assembly with the connector are also provided. |
US09634439B2 |
Contactless plug connector and contactless plug connector system
The invention relates to contactless plug connectors and contactless plug connector systems for electromagnetically connecting a corresponding mating plug connector. In order to allow for an electromagnetic connection, the invention suggest providing at least one input terminal for inputting a baseband input signal; an antenna element arranged at the mating end of the contactless plug connector; and a transmitting circuit for modulating the inputted baseband input signal on a predetermined carrier frequency and for transmitting the modulated baseband input signal via the antenna element as a radio wave with the predetermined carrier frequency. In particular, the contactless plug connector and contactless plug connector system include an electromagnetic shielding element arranged to surround the transmitting circuit and the antenna element with a rim portion forming an opening at the mating end of the contactless plug connector. |
US09634437B2 |
Electrical receptacle connector
An electrical receptacle connector includes an insulated housing, upper-row terminals, lower-row terminals, and a grounding sheet. The insulated housing includes a base portion and a tongue portion. The tongue portion is extended from one side of the base portion and has an upper surface and a lower surface. The upper-row terminals are disposed at the base portion and the tongue portion and include a ground terminal located at the upper surface The lower-row terminals are disposed at the base portion and the tongue portion and include a ground terminal located at the lower surface. The grounding sheet is disposed at the insulated housing and located between the ground terminal of the upper-row terminals and the ground terminal of the lower-row terminals. The grounding sheet includes one or more protruded portion in contact with the ground terminal of the upper-row terminals or the ground terminal of the lower-row terminals. |
US09634428B2 |
Electromagnetic connector for electronic device
An electrical plug and receptacle relying on magnetic force from an electromagnet to maintain contact are disclosed. The plug and receptacle can be used as part of a power adapter for connecting an electronic device, such as a laptop computer, to a power supply. The plug includes electrical contacts, which are preferably biased toward corresponding contacts on the receptacle. The plug and receptacle each have a magnetic element. The magnetic element on one of the plug or receptacle can be a magnet or ferromagnetic material. The magnetic element on the other of the plug or receptacle is an electromagnet. When the plug and receptacle are brought into proximity, the magnetic attraction between the electromagnet magnet and its complement, whether another magnet or a ferromagnetic material, maintains the contacts in an electrically conductive relationship. |
US09634425B1 |
Waterproof connector and electronic device including the same
A waterproof connector applied in an electronic device which includes a case body. The waterproof connector includes an insulating housing, a plurality of conductive terminals fastened to the insulating housing, a first shell surrounding the insulating housing together with the conductive terminals, a second shell covering the first shell and a waterproof element. A front edge of the second shell is bent outward to form a blocking portion. The waterproof element includes a first waterproof element, and a second waterproof element which is waterproof adhesive. The first waterproof element tightly loops around an outer surface of the front end of the first shell. The first waterproof element tightly abuts against an inner wall of the case body and the blocking portion. The waterproof adhesive is poured into and seals up a clearance among rear ends of the insulating housing, the conductive terminals and the first shell. |
US09634424B2 |
Integrated connection system
A modular connector system allows a user to configure physical and functional aspects of a sensor or electrical connector assembly to suit the requirements of a particular installation or application. A header module houses an electrical component, such as a photo sensor, a proximity switch, a safety sensor, etc. A variety of field modules and adapter modules are provided that can be selectively added to the header module to accommodate a wide range of applications. These field and adaptor modules can include power modules, communication modules, or other types of signal processing modules. The housings and electronics of the header, field, and adapter modules are designed such that the field and adapter modules can be rotated relative to the header module to suit physical environment of the connector's location. |
US09634423B2 |
Micro plug connector
A micro plug connector has an insulative housing, multiple terminals, an outer casing, a front shell and a circuit board. The outer casing covers the insulative housing and has a vertical positioning slot and two stop portions to vertically and horizontally hold the circuit board. Therefore, the circuit board is firmly fabricated in the micro plug connector without disassembling out of the outer casing due to pull of wires in a transmission cable or a power cable. |
US09634421B2 |
While-in-use deck box
A while-in-use electrical box, such as a deck box, for providing power to an electrical device includes a frame having a door pivotally mounted therein. The frame is adapted to be mounted in a hole formed in a floor or deck. The door includes a bottom surface on which a receptacle housing is coupled. The receptacle housing includes walls which define an opening to receive an electrical socket device, such as an outlet. When in the closed position, the walls of the receptacle housing enclose the electrical socket device and extend beyond a front face of the electrical socket device to protect the socket from the weather. |
US09634418B2 |
Socket for vehicle passenger compartment
An assembly for producing a socket for a vehicle passenger compartment comprises a metal socket body and contact element used to supply current to the metal socket body and includes fixing means and at least one electrical connection element. Each element is adapted to be fixed to the metal socket body so that only some of the fixing means of the socket body are used to fix it. With this structure, the same metal socket body may be used for differently formed connection elements. |
US09634414B1 |
Simple female terminal and a simple LED lamp connector for a drive board and a light board
A simple female terminal includes a mounting base, a weld leg, and an elastic plate. One end of the mounting base bends to form the weld leg. Another end of the mounting base bends to form the elastic plate. A head of the elastic plate bends toward the mounting base to form a contact head. While a male terminal comes into contact with the elastic plate, the contact head is pushed by the male terminal so that the contact head can rest against the mounting base. A connector and an LED lamp adapted to the simple female terminal are also disclosed. The structure of the female terminal is simplified, so the structure of the connector and the LED lamp are also simplified to obtain an easy installation and reduce the cost. |
US09634412B2 |
Connector structures and methods
Electrical contacts comprising a surface with a plurality of cavities therein and their methods of manufacture and use. |
US09634410B2 |
Connector
A first space in which terminals are disposed and that is connected to a first connection and a second space in which ground terminals are disposed and that is connected to a second connection are provided in a housing portion of a flat conductor including a plate. Furthermore, in the thickness direction of the flat conductor including a plate, the second space is formed with a size that is equivalent to or greater than the thickness of a ground plate so as to enable the second connection to the housed therein. |
US09634406B2 |
Switchboard multifunction terminal block for connecting electrical wires
A switchboard multifunction terminal block for connecting electrical wires, comprising a first pair of seats situated more externally in the longitudinal direction, being designed to house a clamp for gripping wires; a first space centered on the vertical central axis for housing a screw-type jumper of the type with a screw; a pair of second spaces respectively arranged symmetrically on opposite sides of the first space relative to the vertical central axis, each second space being bounded in the longitudinal direction by respective second partitions extending in the vertical direction, the size of each space allowing housing of a respective jumper of the type with spring lugs, the top side of the terminal block having an undercut with base provided with three openings forming the external connection, respectively, of the first space and the pair of spaces for inserting the respective jumper. |
US09634404B1 |
Beam steering multiband architecture
An active antenna system developed to beam steer at multiple frequency bands provides improved performance for fixed and mobile communication systems. Methods of altering the current mode on a single radiator are described wherein the radiation pattern of the antenna is varied as the antenna modes are altered. Techniques to restrict or expand the frequency bandwidth of the beam steering technique are described to provide the capability to beam steer at receive frequencies or transmit frequencies only, and techniques are described where beam steering can occur at both transmit and receive frequency bands from a single active antenna system. |
US09634396B2 |
Extremely low-profile antenna
An antenna, including a ground region having a plurality of meandering slots formed therein, a generally conical radiating element supported on the ground region and spaced apart therefrom and a generally flat disk-shaped radiating element disposed between the generally conical radiating element and the ground region, the generally flat disk-shaped radiating element feeding the generally conical radiating element. |
US09634394B2 |
Antenna arrangement
An antenna arrangement 10 comprises a first elongate limb 12 and a second elongate limb 14. The first and second elongate limbs converge towards one another at a first electrical connection point 16 and a spaced anti-phase electrical connection point 18. The first and second limbs collectively forming a closed figure with a first appendage 22, a second appendage 24, a third appendage 26 and a fourth appendage 28 to the closed figure. |
US09634391B2 |
RFID transponder chip modules
The planar antenna (PA) of a transponder chip module (TCM) may have a U-shaped portion so that an outer end (OE) of the antenna may be positioned close to an RFID chip (IC) disposed at a central area of a module tape (MT) for the transponder chip module. A module tape (MT2) may have contact pads (CP) on one side thereof and a connection bridge (CBR) on another side thereof, and may be joined with a module tape (MT1) having a planar antenna (PA). Metal of a conductive layer (CL) within a conductive element such as a coupling frame (CF) or a planar antenna (PA) may be scribed to have many small segments. A metal sheet may be stamped to have contact side metallization, and joined with a module tape (MT) having a planar antenna (PA). |
US09634386B2 |
Apparatus for safely securing radiation-transparent panels covering the antenna service bays of wireless telecommunication towers and methods of installing the same
Improved radio-transparent communication tower panel security devices that can be easily mounted to and strapped around the cover panels of communication towers, including flag-supporting cellular communication towers, so as to band and secure the cover panels thereto and prevent them from falling off in high winds and/or other adverse weather conditions, while preventing wear and tear of flags and their lanyards. |
US09634381B2 |
Inverted E antenna with parallel plate capacitor formed along an arm of the antenna for use with an implantable medical device
The device includes radio frequency (RF) communication components installed within a case of the device and an antenna with an inverted E shape mounted within a header of the device. The antenna has three branches extending from a main arm: a capacitive branch connecting one end of the main arm to the case; an RF signal feed branch connecting a middle portion of the main arm to the internal RF components of the device via a feedthrough; and an inductive branch connecting the opposing (far) end of the main arm to the case to provide a shunt to ground. |
US09634375B2 |
Universal ceiling antenna mount
A universal ceiling antenna mount may include a plate having a first side and a second side. The plate may include at least one antenna adapter hole, at least one mounting post attached to the second side of the plate, and at least one stem having a top open end and a bottom open end. The bottom open end of the stems may attach to the second side of the plate over the antenna adapter holes. A top plate having at least one hole and at least one mounting hole may sandwich a ceiling tile with the second side of the plate and be secured. At least one coaxial antenna cable may be connected to a top side of mount. At least one antenna may be connected to a bottom side of the mount. |
US09634374B2 |
Glazing comprising antennas and a method of manufacturing said glazing
A compact arrangement of antennas in a glazing is disclosed, which allows a plurality of antenna wires to be connected to an external circuit by a single contact. Parallel conductors, in direct current isolation from each other so that alternating current coupling occurs between them, are embedded at different depths in the thickness of a ply of plastic material. In plan view, conductors at different depths may be positioned closer to each other than in the prior art, so antennas connected to them are less obtrusive and may even be hidden completely under an obscuration band. Different widths of parallel conductor may be used. A thin antenna, connected to a thin conductor, may be positioned in a vision area of a glazing without impeding the view. |
US09634371B2 |
Transmission line circuit assemblies and processes for fabrication
A transmission line circuit assembly has a substrate layer having a transmission line trace, further having a functional portion and a transitional portion. An enclosure of the assembly houses the transitional portion of the transmission line trace. A first surface of a dielectric plug is conductively coupled to an inner top surface of the enclosure. A second surface of the plug is aligned and spaced apart from the transitional portion of the transmission line trace to define a gap therebetween. An interfacing portion of a connecting pin is housed within the enclosure and bonded to the transitional portion. A connecting portion of the pin is connectable to an external conductor. The gap may be filled with a dielectric material. The transitional portion, dielectric plug, dielectric filler and connecting pin form an electromagnetic transition providing tuning and matching of the function portion with the external conductor. |
US09634368B2 |
Non-reciprocal circuit element
In a non-reciprocal circuit element, the characteristics variation with respect to temperature is suppressed with a simple configuration without changing a magnetic material or the material of a magnet. A non-reciprocal circuit element includes: a magnetic material (32) to which a DC magnetic field (G) is applied; a plurality of center electrodes (35, 36) disposed on the magnetic material (32) so as to intersect each other in an insulated state; a terminal resistor (R) connected between input and output ports (P1, P2) and in in parallel with one of the center electrodes (35, 36); a variable capacitance element (C11) connected between the input and output ports (P1, P2) and in parallel with the terminal resistor (R); and a thermistor element (S) connected to a control power supply circuit (E) of the variable capacitance element (C11) and in series with the variable capacitance element (C11). |
US09634363B2 |
Electric storage module, electric storage apparatus, and air passage connection member
An electric storage module includes an electric storage device, an air passage formed along the electric storage device, a frame that holds the electric storage device, the frame having an opening that is formed on an outer surface thereof and is in communication with the air passage, and an air passage connection member that encloses the opening of the frame. An electric storage apparatus includes a plurality of electric storage modules, and air passages of adjacent electric storage modules are connected to each other by an air passage connection member. |
US09634361B2 |
Battery system and associated method for determining the internal resistance of battery cells or battery modules of said battery system
A method for determining the internal resistance of battery cells of battery modules of a battery includes measuring a first voltage of at least one battery cell of a first battery module at a first time. The first battery module is decoupled from the battery module string in response to a control signal. The first battery module is connected to the battery module string after the first voltage measurement to enable a change in the first voltage of the at least one battery cell in response to a current flowing through the first battery module. A second voltage is measured at a second time where the first battery module is connected to the battery module string for a predefined time interval. The internal resistance is determined with reference to a difference between the first and the second voltage and the current flowing through the first battery module. |
US09634358B2 |
Method for producing all-solid-state battery, and all-solid-state battery
An objective of the invention is to provide a method for producing an all-solid-state battery with fewer steps for minimizing warping than in the prior art, and an all-solid-state battery with lower warping. This is achieved by a method comprising the steps of: (A) disposing a first electrode active material layer on both sides of a first collector to form a first electrode layer, (B) disposing a solid electrolyte layer on each of the first electrode active material layers, (C) disposing a second electrode active material layer and a second collector on the solid electrolyte layers, in such a manner that the second electrode active material layers contact with the solid electrolyte layers, (D) pressing a stack formed in steps (A) to (C), to form a battery unit, (E) repeating steps (A) to (D) to form a plurality of battery units, and (F) stacking the plurality of battery units. |
US09634350B2 |
Energy storage device
An energy storage device is provided. The energy storage device includes at least an energy-type electrode pair, including a first positive electrode; a first negative electrode disposed opposite to the first positive electrode; and a first electrolyte disposed between the first positive electrode and the first negative electrode; at least a power-type electrode pair, including a second positive electrode; a second negative electrode disposed opposite to the second positive electrode; and a second electrolyte disposed between the second positive electrode and the second negative electrode; and a housing receiving the energy-type electrode pair and the power-type electrode pair. |
US09634335B2 |
Duplex coating for SOFC interconnect
A coated interconnect for a solid oxide fuel cell including an interconnect substrate comprising iron and chromium and a first metal oxide coating formed over an air side of the interconnect substrate. The first metal oxide coating is formed from powder particles, wherein substantially all the powder particles have a particle size less than 22 microns. |
US09634332B2 |
Composite materials
A mixed metal oxide material of tungsten and titanium is provided for use in a fuel cell. The material may comprise less than approximately 30 at. % tungsten. The mixed metal oxide may form the core of a core-shell composite material, used as a catalyst support, in which a catalyst such as platinum forms the shell. The catalyst may be applied as a single monolayer, or up to 20 monolayers. |
US09634328B2 |
Positive electrode
According to one embodiment, a positive electrode includes a positive electrode layer and a positive electrode current collector. The positive electrode layer includes a positive electrode active material including a first oxide represented by the following formula (α) and/or a second oxide represented by the following formula (β). The positive electrode layer has an intensity ratio falling within a range of 0.25 to 0.7. The ratio is represented by the following formula (1) in an X-ray diffraction pattern obtained by using CuKα radiation for a surface of the positive electrode layer. LixNi1-a-bCoaMnbMcO2 (α) LixNi1-a-cCoaMcO2 (β) I2/I1 (1) |
US09634323B2 |
Electrode, metal-air battery, and electrode manufacturing method
A metal-air battery (1) includes a negative electrode (3), a positive electrode (2), and an electrolyte layer (4) disposed between the negative electrode (3) and the positive electrode (2). The negative electrode (3) includes a base member (31) which has a coiled shape and is formed of a conductive material and a deposited metal layer (32) in powder or particle state, which is formed on a surface of the base member (31) by electrolytic deposition. The electrolyte layer (4) contains an alkaline aqueous solution which contains the same metal as the deposited metal layer (32), and the positive electrode (2) has a tubular shape which is concentric with the negative electrode (3) having the coiled shape and surrounds the negative electrode (3). In this metal-air battery (1), it is possible to suppress occurrence of dendrites in the negative electrode (3). |
US09634321B2 |
Oxide shell formation on inorganic substrate via oxidative polyoxoanion salt deposition
The present invention provides a process for depositing an oxide coating on an inorganic substrate, including providing an aqueous composition containing a tetraalkylammonium polyoxoanion and hydrogen peroxide; contacting the aqueous composition with an inorganic substrate for a time sufficient to deposit a hydroxide derived from the polyoxoanion on surfaces of the inorganic substrate to form an initially coated inorganic substrate; and heating the initially coated inorganic substrate for a time sufficient to convert the hydroxide to an oxide to form on the inorganic substrate an oxide coating derived from the polyoxoanion. The inorganic substrate may be a ceramic material or a semiconductor material, a glass or other dielectric material, and the ceramic material may be a lithium ion battery cathode material. |
US09634320B2 |
Active material and lithium ion battery
An active material used for an electrochemical device utilizing Li ion conduction, and capable of improving cycle stability. The object is attained by providing an active material used for an electrochemical device utilizing Li ion conduction, including an active substance capable of absorbing and releasing a Li ion, and an Na ion conductor disposed on the surface of the active substance and having a polyanionic structure. |
US09634316B2 |
Lithium ion secondary battery
A lithium ion secondary battery includes a positive electrode capable of occluding and discharging lithium ions, a negative electrode capable of occluding and discharging the lithium ions, and a nonaqueous electrolyte including a lithium salt, and being reversively charged/discharged. The positive electrode includes a metal plate, a metal film formed on a surface of the metal plate, and a positive electrode active material layer, the metal film includes one or more metals selected from the group consisting of ruthenium, osmium, palladium, and platinum having a orientation, the positive electrode active material layer is a compound expressed by the following expression: LiCoxNi1-xO2, (where 0≦x≦1) and is epitaxially grown and formed on a surface of the metal film, and the positive electrode active material is formed such that a c axis of a crystal structure of the positive electrode active material is perpendicular to the metal film. |
US09634312B2 |
Electrode terminal and battery module having the same
An electrode terminal and battery module having the same are disclosed. In one aspect, the electrode terminal includes a first sub-terminal including a plurality of guide grooves and a second sub-terminal including a plurality of guides configured to be respectively inserted into the guide grooves in a sliding manner. At least one of the guide grooves is formed in an upper surface of the first sub-terminal. |
US09634306B2 |
Battery tray and cover for underground mining equipment
A battery-powered mining machine comprising a battery tray and a plurality of batteries. The battery tray including at least one battery partition, the battery partition made entirely of plastic. The plurality of batteries in the battery tray to provide power to the mining machine, the plurality of batteries held in place by the battery partition. |
US09634305B2 |
Battery module with covering plates
A battery module includes a pair of side plates arranged along two wall faces, opposing to each other in a stacking direction of battery cells, of wall faces of the battery module, a lower plate that swingably supports one end of the pair of side plates by a hinge mechanism and that is arranged along one wall face of the battery module, and an upper plate that is arranged along the wall face of the battery module so as to be opposite to the lower plate, and that connects the other ends of the pair of side plates, wherein the side plates and the upper plate are tightened and fixed by use of a fastening member with pressure being applied in the stacking direction of the battery cells in order to fix the battery module. |
US09634303B2 |
Battery extension and wall mount box for a smoke detector
The invention provides a faux battery for a real battery in a smoke detector, and electrically connects the faux battery to a real battery in a reachable battery housing located within reach of a human, to facilitate battery changing in the smoke detector. |
US09634302B2 |
Secondary battery module
A secondary battery module includes a cell block in which a plurality of square batteries are layered, and includes: a pair of end plates arranged to respectively face one side and another side of the cell block in a layering direction; and a pair of side frames and arranged to respectively face one side and another side in a cell width direction perpendicular to the layering direction of the cell block, and in the one side and another side in the cell width direction, one end portion being engaged with one end plate at the one side in the layering direction, and other end portion being engaged with other end plate at another side in the layering direction. |
US09634301B2 |
Lithium ion battery cell with secondary seal
A lithium ion battery cell includes a prismatic casing enclosing active components of the lithium ion battery cell. The lithium ion battery cell also includes a terminal having a terminal post extending through an opening in the casing and electrically connected to the active components; a primary sealing component configured to seal a first portion of the terminal post against the casing; and a secondary seal disposed around a second portion of the terminal post and against the primary sealing component. The secondary seal is formed from a curable adhesive resin and is configured to resist egress of the electrolyte out of the lithium ion battery cell and is configured to resist ingress of moisture into the lithium ion battery cell. |
US09634299B2 |
Rechargeable battery
A rechargeable battery includes: an electrode assembly including a first electrode having a first polarity and a second electrode having a second polarity, the second polarity being different from the first polarity; a case housing the electrode assembly; a first terminal electrically connected to the first electrode; a cap plate coupled to an opening of the case; a first lower insulating member between the first electrode and the cap plate; and a first short-circuit member between the first terminal and the first lower insulating member, and configured to be deformed to electrically connect the first electrode to the cap plate, wherein the first terminal includes a first fixing portion electrically connected to the first electrode. |
US09634294B2 |
Method of manufacturing organic light emitting display panel
A method of manufacturing an organic light emitting display panel, the method including: providing a pixel defined by an intersection of one of a plurality of data lines and one of a plurality of gate lines, the providing the pixel including: providing a transistor, providing a storage capacitor including: a first electrode, and a second electrode, and providing a semiconductor layer, providing a first plate partially overlapping the semiconductor layer in the pixel, the providing a first plate including: providing a gate portion of the transistor, and providing a capacitor-forming portion including the first electrode of the storage capacitor, and providing a second plate on the first plate in the pixel, the second plate including the second electrode of the storage capacitor, the second plate not overlapping the semiconductor layer. |
US09634293B2 |
Organic light emitting display device having 2 stack structure and a metal oxide
An organic light emitting display (OLED) device can include a substrate on which first to third light emitting portions are defined, first electrodes respectively positioned on the first to third light emitting portions, a first stack formed on the first electrodes and including first, second and third light emitting layers corresponding to the first, second and third light emitting portions, respectively, an N-type charge generation layer (CGL) positioned on the first stack, a transition metal oxide layer positioned on the N-type CGL, a second stack positioned on the transition metal oxide layer and including fourth, fifth and sixth light emitting layers corresponding to the first, second and third light emitting portions, respectively, and a second electrode positioned on the second stack. |
US09634291B2 |
Organic light-emitting transistor
An organic light-emitting transistor (OLET) is provided. The OLET includes: a substrate; at least one first electrode on the substrate; a first semiconductor layer having a first conductive type on the first electrode; a second semiconductor layer having a second conductive type on the first semiconductor layer; a gate electrode disposed on a side surface of the second semiconductor layer; a gate insulating layer disposed between the gate electrode and the second semiconductor layer; an organic emission layer on the second semiconductor layer. |
US09634290B2 |
Laminate for light emitting device and process of preparing same
A laminate for a light emitting device, includes a glass substrate, a random network of reliefs formed on the glass substrate, and a flattening layer formed on the network, wherein the network of reliefs are formed from a glass frit. The laminate for a light emitting device further includes a network inducing the scattering of light for efficiently extracting outward a loss of light at an interface between a glass substrate and an internal light extraction layer. The laminate is suitable for the industrial field of optical devices, such as organic light emitting diodes (OLEDs), backlights, lighting, and the like. |
US09634285B2 |
Electrical device
The invention relates to an electrical device comprising an electrical unit (2) like an organic light emitting diode, a protection element (3) like a thin film encapsulation, which at least partly covers the electrical unit, for protecting the electrical unit against water and/or oxygen, and a detection layer (4) arranged between the protection element and the electrical unit or within the protection element, wherein the detection layer comprises organic material and is adapted such that a property of the detection layer is changed, if the detection layer is in contact with a contact gas usable for detecting a permeability of the protection element. This allows easily integrating a fast detection test for detecting a permeability of the protection element into a production process for producing the electrical device, i.e. a time consuming external permeability test may not be required. |
US09634279B2 |
Light-emitting element
A light-emitting element having high external quantum efficiency is provided. A light-emitting element having low drive voltage is provided. Provided is a light-emitting element which includes a light-emitting layer containing a phosphorescent compound, a first organic compound, and a second organic compound between a pair of electrodes. A combination of the first organic compound and the second organic compound forms an exciplex (excited complex). An emission spectrum of the exciplex overlaps with an absorption band located on the longest wavelength side of an absorption spectrum of the phosphorescent compound. A peak wavelength of the emission spectrum of the exciplex is longer than or equal to a peak wavelength of the absorption band located on the longest wavelength side of the absorption spectrum of the phosphorescent compound. |
US09634274B2 |
Monochrome OLED and method for manufacturing the same, and OLED display panel
The present invention discloses a monochrome OLED and a method for manufacturing the same, and an OLED display panel, which can improve the performance of an OLED. A monochrome OLED according to an embodiment of the invention comprises a luminescent layer, wherein the luminescent layer comprises at least one luminescent sublayer; and at least one carrier control layer that is adjacent to the luminescent sublayer, wherein the carrier control layer is adapted to control the concentration ratio of carriers with different polarities in the luminescent layer. |
US09634273B2 |
Method for producing fully aqueous phase-synthesized nanocrystals/conducting polymer hybrid solar cell
Provided is a method for producing a highly efficient organic/inorganic hybrid solar cell using fully aqueous phase-synthesized semiconductor nanocrystals and conducting polymer. The method mainly includes three steps: synthesizing nanocrystals in an aqueous phase, synthesizing a conjugated polymer precursor in an aqueous phase, and producing a device of solar cell. The nanocrystal material required for producing a solar cell by the method is widely available, diversified and size-controlled, and the used conjugated polymer has regulated molecular structure and molecular weight, which contributes to increase the absorption of sunlight. The processing of cell device can be performed at room temperature in air, and has advantages of no pollution, short processing period, and low cost. A method for producing an organic/inorganic hybrid solar cell is developed, which succeeds in introducing the high quality nanocrystals synthesized in an aqueous phase and is an eco-friendly and pollution-free technology for producing a solar cell. |
US09634272B2 |
Foldable display
A foldable display according to the present disclosure includes: a substrate having a folding portion which is folded; and a plurality of transistors in the substrate each of the transistors including: a gate electrode on the substrate; a channel overlapping the gate electrode; and a source electrode and a drain electrode positioned at respective sides of the channel, wherein the gate electrode is divided into a plurality of sub-gate electrodes by at least one gate cutout. |
US09634268B2 |
Electronic device comprising metal complexes
Electronic devices, in particular organic electroluminescent devices, comprising metal complexes of the formula (1). |
US09634261B2 |
Organic photoelectric conversion element and solar cell using same
Disclosed is an organic photoelectric conversion element which has a reverse layer structure wherein at least a first electrode, a photoelectric conversion layer and a second electrode are arranged on a substrate in this order. The organic photoelectric conversion element is characterized in that: the photoelectric conversion layer is a bulk heterojunction layer that is composed of a p-type organic semiconductor material and an n-type organic semiconductor material; and a compound that has a linear or branched fluorinated alkyl group having 6-20 carbon atoms is contained as the p-type organic semiconductor material. |
US09634257B2 |
Heterocyclic compound and organic light-emitting device including the same
A heterocyclic compound of Formula 1 below and an organic light-emitting device including the same are provided. X1 to X4, L1, L2, n, m, and Ar1 to, Ar4 in Formula 1 are defined as in the specification. |
US09634254B2 |
Organic material and organic light emitting diode display using same
An organic material for an organic light emitting diode (OLED) display, and an OLED display are provided, and the organic material includes an anthracene derivative includes at least deuterium. |
US09634252B2 |
Polymer and solar cell using the same
A polymer of an embodiment includes a repeating unit containing a bivalent group represented by the following formula (1). R is hydrogen, halogen, an alkyl group, an alkanoyl group, an aryl group, a heteroaryl group, or the like. X is oxygen, sulfur, selenium, or the like. Y and Z each is a bivalent group selected from a carbonyl group, a sulfinyl group, and a sulfonyl group. However, a case where Y and Z are both the carbonyl groups is excluded. |
US09634249B2 |
Semiconductor device and method for producing semiconductor device
A device includes a pillar-shaped insulating layer above a first pillar-shaped semiconductor layer. A resistance-changing film is around an upper portion of the pillar-shaped insulating layer and a lower electrode is around a lower portion of the pillar-shaped insulating layer and connected to the resistance-changing film. A reset gate insulating film surrounds the resistance-changing film, and a reset gate surrounds the reset gate insulating film. |
US09634246B2 |
Electronic device and method for fabricating the same
An electronic device includes a semiconductor memory. The semiconductor memory includes a vertical electrode layer formed over a substrate and extending in a vertical direction substantially perpendicular to a surface of the substrate; an interlayer dielectric layer and a structure formed over the substrate and alternately stacked along the vertical electrode layer, wherein the structure includes a horizontal electrode layer and a base layer which is conductive and located over or under the horizontal electrode layer; a variable resistance layer interposed between the vertical electrode layer and the base layer, and including a common element with the base layer; and a groove interposed between the vertical electrode layer and the horizontal electrode layer and insulating the vertical electrode layer and the horizontal electrode layer from each other. |
US09634244B2 |
Magnetic random access memory with perpendicular interfacial anisotropy
The present invention is directed to an MRAM element comprising a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic free layer structure has a variable magnetization direction substantially perpendicular to the layer plane thereof. The magnetic reference layer structure includes a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated from the first magnetic reference layer by a first non-magnetic perpendicular enhancement layer. The first and second magnetic reference layers have a first fixed magnetization direction substantially perpendicular to the layer plane thereof. The second magnetic reference layer has a multilayer structure comprising a first magnetic reference sublayer formed adjacent to the first non-magnetic perpendicular enhancement layer and a second magnetic reference sublayer separated from the first magnetic reference sublayer by an intermediate metallic layer. |
US09634243B1 |
Semiconductor structure and method of forming the same
The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a first Nth metal line of an Nth metal layer, a magnetic tunneling junction (MTJ) over first Nth metal line, and a first (N+1)th metal via of an (N+1)th metal layer, the first (N+1)th metal via being disposed over the MTJ layer. N is an integer greater than or equal to 1. A method of manufacturing the semiconductor structure is also disclosed. |
US09634239B2 |
Magnetic element
A magnetic element is provided. The magnetic element includes a free magnetization layer having a surface area that is approximately 1,600 nm2 or less, the free magnetization layer including a magnetization state that is configured to be changed; an insulation layer coupled to the free magnetization layer, the insulation layer including a non-magnetic material; and a magnetization fixing layer coupled to the insulation layer opposite the free magnetization layer, the magnetization fixing layer including a fixed magnetization so as to be capable of serving as a reference of the free magnetization layer. |
US09634238B2 |
Magnetic structures, methods of forming the same and memory devices including a magnetic structure
Magnetic structures, methods of forming the same, and memory devices including a magnetic structure, include a magnetic layer, and a stress-inducing layer on a first surface of the magnetic layer, a non-magnetic layer on a second surface of the magnetic layer. The stress-inducing layer is configured to induce a compressive stress in the magnetic layer. The magnetic layer has a lattice structure compressively strained due to the stress-inducing layer. |
US09634237B2 |
Ultrathin perpendicular pinned layer structure for magnetic tunneling junction devices
A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer. |
US09634236B2 |
Magnetoelectronic components and measurement method
Magnetoelectronic components comprise at least one oblong working structure made of a ferromagnetic material, along which magnetic domain walls can migrate, means for applying an electric current to this working structure, and at least one magnetic field sensor for the magnetic field generated by the working structure. The working structure is designed so that it is able to form domain walls, the transverse magnetization direction of which in the center has no preferred direction in the plane perpendicular to the migration direction thereof along the working structure, and/or can form massless domain walls. It was found that the kinetic energy of such moving domain walls vanishes. These walls are thus not subject to the Walker limit nor to intrinsic pinning. As a result, the components can read, store or process and finally output information more quickly. The invention also relates to a method for measuring the non-adiabatic spin transfer parameter β of a ferromagnetic material. This method was developed as part of a more in-depth examination of the phenomena that were found. |
US09634233B2 |
Axial loading for magnetostrictive power generation
A device generates electrical energy from mechanical motion in a downhole environment. The device includes a magnetostrictive element and an electrically conductive coil. The magnetostrictive element has a first end and a second end. The first and second ends are coupled between two connectors. The magnetostrictive element is configured to experience axial strain in response to radial movement of at least one of the connectors relative to the other connector. The electrically conductive coil is disposed in proximity to the magnetostrictive element. The coil is configured to generate an electrical current in response to a change in flux density of the magnetostrictive element. |
US09634229B2 |
Piezoelectric device, ultrasound probe, droplet discharge device, and piezoelectric device fabrication method
In a piezoelectric device, an ultrasound probe, and a droplet discharge unit of the present invention, each of a pair of first and second electrodes is placed on a piezoelectric member having a single orientation in a direction perpendicular to a thickness direction thereof to extend in a direction perpendicular to the thickness direction or along the thickness direction and in a direction perpendicular to the direction of the orientation. Therefore, the piezoelectric device of the present invention has excellent piezoelectric properties. Further, the ultrasound probe and the droplet discharge unit of the present invention have good efficiency. |
US09634226B2 |
Lamb wave device and manufacturing method thereof
A Lamb wave device according to an embodiment of the present invention includes a piezoelectric function member and a supporting member. The piezoelectric function member has a piezoelectric substrate, IDT electrodes, and a cutout portion. The IDT electrodes are disposed on the upper surface of the piezoelectric substrate. The cutout portion is formed in the piezoelectric substrate, and includes a step face provided between the upper surface and the lower surface of the piezoelectric substrate. The supporting member has a supporting surface and a cavity. The supporting surface is bonded to the lower surface of the piezoelectric substrate, and is exposed in the cutout portion toward the upper surface of the piezoelectric substrate. The cavity is formed adjacent to the supporting surface, and faces the IDT electrodes through the piezoelectric substrate. |
US09634225B2 |
Artificial muscle camera lens actuator
An artificial muscle structure has an electro-active polymer (EAP) layer having a frusto-conical shape and whose tip has an opening formed therein for use as a camera variable aperture. First, second and third electrode segments are formed on a rear face of the EAP layer. The second segment is positioned in a gap between the first and third segments so as to be electrically isolated from the first and third segments. The second segment has an opening formed therein that is aligned with the opening in the EAP layer. A complementary electrode is formed on a front face of the EAP layer. Other embodiments are also described. |
US09634221B2 |
Thin-film thermo-electric generator and fabrication method thereof
A method of manufacturing a thin-film thermo-electric generator includes the steps of: forming two or more PN junctions each having a three-layer structure; forming a substrate which has a first side and an opposed second side; coupling the PN junctions at the first side of the substrate to define a first group of PN junctions at the first side of the substrate; and providing two electrodes that one of the electrodes is extracted from the first group of PN junctions. Accordingly, each of the PN junctions is formed by depositing an insulating thin-film layer between a P-type thermo-electric thin-film layer and a N-type thermo-electric thin-film layer. |
US09634218B2 |
Fabrication method for synthesizing a Bi2TeySe3-y thermoelectric nanocompound and thermoelectric nanocompound thereby
The present invention provides a method for synthesizing a Bi2TeySe3-y thermoelectric nanocompound (0 |
US09634216B2 |
Light emitting device
According to one embodiment of the present invention, the light emitting device includes an LED element, a side wall which surrounds the LED element, a phosphor layer which is fixed to the side wall with an adhesive layer therebetween, and is positioned above the LED element, and a metal pad as a heat dissipating member. The side wall includes an insulating base which surrounds the LED element and a metal layer which is formed on a side surface at the LED element side of the base, and is in contact with the metal pad and the adhesive layer. The adhesive layer includes a resin layer that includes a resin containing particles which have higher thermal conductivity than the resin or a layer that includes solder. |
US09634208B2 |
Shallow reflector cup for phosphor-converted LED filled with encapsulant
An LED die (26) conformally coated with phosphor (28) is mounted at the base (24) of a shallow, square reflector cup (16). The cup has flat reflective walls (20) that slope upward from its base to its rim at a shallow angle of approximately 33 degrees. A clear encapsulant (30) completely fills the cup to form a smooth flat top surface. Any emissions from the LED die or phosphor at a low angle (48, 50) are totally internally reflected at the flat air-encapsulant interface toward the cup walls. This combined LED/phosphor light is then reflected upward by the walls (20) and out of the package. Since a large percentage of the light emitted by the LED and phosphor is mixed by the TIR and the walls prior to exiting the package, the color and brightness of the reflected light is fairly uniform across the beam. The encapsulant is intentionally designed to enhance TIR to help mix the light. |
US09634207B2 |
Semiconductor component and method of producing a semiconductor component
A method of producing a semiconductor component includes providing an optoelectronic semiconductor chip; applying a molding compound for an optical element, wherein the molding compound is based on a highly refractive polymer material; precuring the molding compound at a temperature of at most 50° C.; and curing the molding compound. |
US09634206B1 |
LED luminaire
A compact light unit having light emitting diodes (LEDs) includes a circuit board assembly and a lens including optical structures, a front face, and a rim disposed about the front face. The lens may include a pocket on a back portion of the lens opposite the front face within which the circuit board assembly is mounted with the LEDs being optically aligned with the optical structures. The LED light unit further includes a bezel having an interior opening with the bezel configured to be mounted to the lens with the rim engaged with an interior portion of the bezel and the front face exposed through the interior opening. Various optical structures may be provided to direct light projected by the LEDs at different angles. |
US09634199B2 |
Methods of tuning light emitting devices and tuned light emitting devices
Methods of treating an emission spectrum of visible light emitted from a light emitting source, and resulting apparatus, are disclosed. The methods include obtaining the visible light emission spectrum emitted from the light emitting source and a desired visible light emission spectrum. The methods may also include determining at least one wavelength of the emission spectrum of the source with an irradiance or intensity that is less than that of the desired emission spectrum. The methods may include selecting at least one pigment that is effective in tuning the emission spectrum of the source by increasing the intensity or irradiance of the at least one wavelength. The methods may include applying the at least one pigment to the light emitting source to treat the emission spectrum emitted therefrom. |
US09634197B2 |
Wafer level packaging of multiple light emitting diodes (LEDs) on a single carrier die
An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide multiple LED dies that are joined to a single carrier die. The multiple LED dies on the single carrier die are connected in series and/or in parallel by interconnection in the LED dies and/or in the single carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area. Related devices and fabrication methods are described. |
US09634193B2 |
Light emitting diode and method of manufacturing the same
A light-emitting diode including a substrate, a first semiconductor layer disposed on the substrate, an active layer disposed on the first semiconductor layer, a second semiconductor layer disposed on the active layer and having a conductivity type different than that of the first semiconductor layer, and a reflective pattern disposed on the second semiconductor layer and configured to reflect light emitted from the active layer, the reflective pattern having heterogeneous metal layers and configured to absorb stress caused by differences in coefficient of thermal expansion between the heterogeneous metal layers. |
US09634190B2 |
White light-emitting element
A white light-emitting device of the present invention includes a substrate (101); a diamond semiconductor layer (105) provided on the substrate (101), in which one or a plurality of p-type α layers (102), a p-type or n-type γ layer (103), and one or a plurality of n-type β layers (104) are laminated in this order from the substrate (101); a first electrode (106) provided on the α layer (102) which injects an electric current; a second electrode (107) provided on the β layer (104) which injects an electric current; and a fluorescent member (108) which coats a light emission extraction region of the surface of the diamond semiconductor layer. |
US09634189B2 |
Patterned substrate design for layer growth
A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation. |
US09634179B2 |
Selective removal of a coating from a metal layer, and solar cell applications thereof
A method and resulting structure of patterning a metal film pattern over a substrate, including forming a metal film pattern over the substrate; depositing a coating over the substrate surface and the metal film pattern; and removing the coating over the metal film pattern by laser irradiation. The substrate and coating do not significantly interact with the laser irradiation, and the laser irradiation interacts with the metal film pattern and the coating, resulting in the removal of the coating over the metal film pattern. The invention offers a technique for the formation of a metal pattern surrounded by a dielectric coating for solar cells, where the dielectric coating may function as an antireflection coating on the front surface, internal reflector on the rear surface, and may further may function as a dielectric barrier for subsequent electroplating of metal patterns on either surface. |
US09634177B2 |
Solar cell emitter region fabrication with differentiated P-type and N-type region architectures
Methods of fabricating solar cell emitter regions with differentiated P-type and N-type regions architectures, and resulting solar cells, are described. In an example, a back contact solar cell includes a substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region of a first conductivity type is disposed on a first thin dielectric layer disposed on the back surface of the substrate. A second polycrystalline silicon emitter region of a second, different, conductivity type is disposed on a second thin dielectric layer disposed on the back surface of the substrate. A third thin dielectric layer is disposed laterally directly between the first and second polycrystalline silicon emitter regions. A first conductive contact structure is disposed on the first polycrystalline silicon emitter region. A second conductive contact structure is disposed on the second polycrystalline silicon emitter region. |
US09634176B2 |
Method for manufacturing crystalline silicon-based solar cell and method for manufacturing crystalline silicon-based solar cell module
A method for manufacturing a crystalline silicon-based solar cell having a photoelectric conversion section includes a silicon-based layer of an opposite conductivity-type on a first principal surface side of a crystalline silicon substrate of a first conductivity-type, and a collecting electrode formed by an electroplating method on a first principal surface of the photoelectric conversion section. By applying laser light from a first or second principal surface side of the photoelectric conversion section, an insulation-processed region his formed where a short-circuit between the first principal surface and a second principal surface of the photoelectric conversion section is eliminated. On the collecting electrode and/or the insulation-processed region, a protecting layer s formed for preventing diffusion of a metal contained in the collecting electrode into the substrate. After the protecting layer is formed, the insulation-processed region is heated to eliminate leakage between the substrate and the silicon-based layer. |
US09634175B2 |
Systems and methods for thermally managing high-temperature processes on temperature sensitive substrates
A method for depositing one or more thin-film layers on a flexible polyimide substrate having opposing front and back outer surfaces includes the following steps: (a) heating the flexible polyimide substrate such that a temperature of the front outer surface of the flexible polyimide substrate is higher than a temperature of the back outer surface of the flexible polyimide substrate, and (b) depositing the one or more thin-film layers on the front outer surface of the flexible polyimide substrate. A deposition zone for executing the method includes (a) one of more physical vapor deposition sources adapted to deposit one or more metallic materials on the front outer surface of the substrate, and (b) one or more radiant zone boundary heaters. |
US09634169B1 |
Hybrid solar concentrator utilizing a dielectric spectrum splitter
A hybrid solar concentrator that utilizes one or more dielectric mirrors to isolate components of the solar spectrum compatible with specific PV band-gaps and to pass longer wavelengths through to a heat receiver, generating both electricity and heat from a single set of dual-axis heliostats. |
US09634168B2 |
Attachment structures for building integrable photovoltaic modules
Provided are novel building integrable photovoltaic (BIP) modules having specially configured attachment structures for securing these modules to building structures and other BIP modules. In certain embodiments, a BIP module includes a base sheet supporting photovoltaic cells and having a rigid polymer portion and a flexible polymer portion. The flexible portion is designed to be penetrated with mechanical fasteners during installation. The flexible portion may include fastening pointers and/or through holes for identifying specific penetration locations. The rigid portion provides necessary structural rigidity and support to the module and more specifically to the photovoltaic cells. In certain other embodiments, a BIP module includes an adhesive bumper strip disposed along one edge of the module and configured for secure this module with respect to another module. During installation, the strip is positioned between a back sealing sheet of one module and a front sealing sheet of another module. |
US09634164B2 |
Reduced light degradation due to low power deposition of buffer layer
Methods for forming a photovoltaic device include forming a buffer layer between a transparent electrode and a p-type layer. The buffer layer includes a work function that falls substantially in a middle of a barrier formed between the transparent electrode and the p-type layer to provide a greater resistance to light induced degradation. An intrinsic layer and an n-type layer are formed over the p-type layer. |
US09634163B2 |
Lateral collection photovoltaics
A nanostructured or microstructured array of elements on a conductor layer together form a device electrode of a photovoltaic or detector structure. The array on the conductor layer has a high surface area to volume ratio configuration defining a void matrix between elements. An active layer or active layer precursors is disposed into the void matrix as a liquid to form a thickness coverage giving an interface on which a counter-electrode is positioned parallel to the conduction layer or as a vapor to form a conformal thickness coverage of the array and conduction layer. The thickness coverage is controlled to enhance collection of at least one of electrons and holes arising from photogeneration, or excitons arising from photogeneration, to the device electrode or a device counter-electrode as well as light absorption in said active layer via reflection and light trapping of said device electrode. |
US09634161B2 |
Nanoscale precursors for synthesis of Fe2(Si,Ge)(S,Se)4 crystalline particles and layers
Thin films comprising crystalline Fe2XY4, wherein X is Si or Ge and Y is S or Se, are obtained by coating an ink comprised of nanoparticle precursors of Fe2XY4 and/or a non-particulate amorphous substance comprised of Fe, X and Y on a substrate surface and annealing the coating. The coated substrate thereby obtained has utility as a solar absorber material in thin film photovoltaic devices. |
US09634156B2 |
Semiconductor photomultiplier and readout method
A silicon photomultiplier device is provided. The device comprises a plurality of photosensitive cells each having a photo-detector, a quench resistive load and a first stage capacitive load. The device is arranged in a three electrode connection configuration comprising first and second electrodes arranged to operably provide a biasing of the device and a third electrode operably used to readout a signal from the device. A second stage capacitive load is operably coupled to two or more photosensitive cells. |
US09634155B2 |
Method for producing an electrical terminal support
The invention relates to a method for producing an electrical terminal support for an optoelectronic semiconductor body, comprising the following steps: providing a carrier assembly (1), which comprises a carrier body (11), an intermediate layer (12) arranged on an outer surface (111) of the carrier body (11), and a use layer (13) arranged on the intermediate layer (12); introducing at least two openings (4), which are mutually spaced in the lateral direction (L), in the use layer (13) via an outer surface (131) of the use layer (13), wherein the openings extend completely through the use layer (13) in the vertical direction (V); electrically insulating lateral surfaces (41) of the openings (4) and of the outer face (131) of the use layer (13); arranging electrically conductive material (6) at least in the openings (4), wherein after completion of the terminal carrier (100), the electrically conductive material (6) has an interruption (U) in the progression thereof along the outer surface (131) of the use layer (13) in the lateral direction (L) between adjoining openings (4). |
US09634153B2 |
Sensor using sensing mechanism having combined static charge and field effect transistor
The present invention relates to a sensor that uses a sensing mechanism having a combined static charge and a field effect transistor, the sensor including: a substrate; source and drain units formed on the substrate and separated from each other; a channel unit interposed between the source and drain units; a membrane separated from the channel unit, disposed on a top portion and displaced in response to an external signal; and a static charge member formed on a bottom surface of the membrane separately from the channel unit and generating an electric field. Accordingly, since the sensor using a sensing mechanism having a combined static charge and a field effect transistor according to an embodiment of the present invention can measure the displacement or movement of the sensor by measuring a change of the electric field of the channel unit of the field effect transistor by using a static member, the electric field can be formed so as to be proportional to an amount of charge and inversely proportional to a squared distance regardless of the intensity and distribution of an external electric field. Therefore, sensitivity is improved without being affected by an external electric field. |
US09634150B2 |
Semiconductor device, display device, input/output device, and electronic device
A self-aligned transistor including an oxide semiconductor film, which has excellent and stable electrical characteristics, is provided. A semiconductor device is provided with a transistor that includes an oxide semiconductor film, a gate electrode overlapping with part of the oxide semiconductor film, and a gate insulating film between the oxide semiconductor film and the gate electrode. The oxide semiconductor film includes a first region and second regions between which the first region is positioned. The second regions include an impurity element. A side of the gate insulating film has a depressed region. Part of the gate electrode overlaps with parts of the second regions in the oxide semiconductor film. |
US09634148B2 |
Thin film transistor and manufacturing method thereof
The disclosure is related to a thin film transistor and a method of manufacturing the thin film transistor. The thin film transistor comprises a substrate, a first semiconductor layer, an etch stop layer and a second semiconductor layer stacked on a surface of the substrate, and a first via and a second via formed on the etch stop layer; a source and a drain formed separating from each other and the source and the drain overlapping two ends of the second semiconductor layer respectively, wherein the source connects the first semiconductor layer through the first via, and the drain connects the first semiconductor layer through the second via, a gate insulation layer formed on the source and the drain; and a gate formed on the gate insulation layer. The thin film transistor of the disclosure have a higher on-state current of the thin film transistor and a faster switching speed. |
US09634147B2 |
Thin film transistor array substrate and liquid crystal display panel using same
A thin film transistor (TFT) array substrate of a liquid crystal display (LCD) panel includes a first substrate, a gate located on the first substrate, a gate insulation layer located on the first substrate and covers the gate and the first substrate, a source layer located on the gate insulation layer to correspond to the gate, an etching stopping layer located on the source layer, and a source and a drain located on the etching stopping layer. The etching stopping layer is made of color photoresist. |
US09634145B2 |
TFT substrate with variable dielectric thickness
A transistor includes a substrate and an electrically conductive gate over the substrate. The gate has a gate length. A source electrode and a drain electrode are over the substrate, and are separated by a gap defining a channel region. The channel region has a channel length that is less than the gate length. A semiconductor layer is in contact with the source electrode and drain electrode. A dielectric stack is in contact with the gate, and has first, second, and third regions. The first region is in contact with the semiconductor layer in the channel region, and has a first thickness. The second region is adjacent to the first region that has the first thickness. The third region is adjacent to the second region, and has a thickness that is greater than the first thickness. |
US09634143B1 |
Methods of forming FinFET devices with substantially undoped channel regions
One disclosed method includes forming a fin in a substrate by etching a plurality of fin-formation trenches, forming a layer of insulating material in the trenches, performing a densification anneal process on the layer of insulating material and, after performing the densification anneal process, performing at least one ion implantation process to form a counter-doped well region in the fin. The method also includes forming an undoped semiconductor material on an exposed upper surface of the fin, recessing the insulating material so as to expose at least a portion of the undoped semiconductor material and forming a gate structure around the exposed portion of the undoped semiconductor material. |
US09634142B1 |
Method for improving boron diffusion in a germanium-rich fin through germanium concentration reduction in fin S/D regions by thermal mixing
A method may include forming a germanium-including fin on a substrate, and forming a dummy gate extending over the germanium-including fin, creating a channel under the gate and a source/drain region of the germanium-including fin extending from under the dummy gate on each side of the dummy gate. An in-situ p-type doped silicon germanium layer may be grown over the source/drain region, the germanium-including fin having a higher concentration of germanium than the in-situ p-type doped silicon germanium layer. An anneal thermally mixes the germanium of the in-situ p-type doped silicon germanium layer and the germanium of the germanium-including fin in the source/drain region of the germanium-including fin and diffuses the p-type dopant of the in-situ p-type doped silicon germanium layer into the channel of the germanium-including fin, forming a source/drain extension. A portion of the channel has a higher germanium concentration than the source/drain region. |
US09634141B1 |
Interlayer dielectric film in semiconductor devices
A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer. |
US09634135B2 |
Power field effect transistor
A field-effect transistors (FET) cell structure has a substrate, an epitaxial layer of a first conductivity type on the substrate, first and second base regions of the second conductivity type arranged within the epitaxial layer or well and spaced apart, and first and second source regions of a first conductivity type arranged within the first and second base region, respectively. Furthermore, a gate structure insulated from the epitaxial layer by an insulation layer is provided and arranged above the region between the first and second base regions and covering at least partly the first and second base region, and a drain contact reaches from a top of the device through the epitaxial layer to couple a top contact or metal layer with the substrate. |
US09634132B2 |
Semiconductor structures and methods for multi-level band gap energy of nanowire transistors to improve drive current
A semiconductor device is provided having a channel formed from a nanowire with multi-level band gap energy. The semiconductor device comprises a nanowire structure formed between source and drain regions. The nanowire structure has a first band gap energy section joined with a second band gap energy section. The first band gap energy section is coupled to the source region and has a band gap energy level greater than the band gap energy level of the second band gap energy section. The second band gap energy section is coupled to the drain region. The first band gap energy section comprises a first material and the second band gap energy section comprises a second material wherein the first material is different from the second material. The semiconductor device further comprises a gate region around the junction between the first band gap energy section and the second band gap energy section. |
US09634131B2 |
Insulated gate bipolar device
A semiconductor device includes: metal collector layer on backside, P-type collector layer, N-type field stop layer and N− drift layer. There are active cells and dummy cells on top of the device. The active cell and dummy cell are separated by gate trench. The gate trench is formed by polysilicon and gate oxide layer. There are N+ region and P+ region in active cells, and they are connected to metal emitter layer through the window in the insulation layer. There are P-well regions in both active cells and dummy cells. The P-well regions in active cells are continuous and connected to emitter electrode through P+ region. The P-well regions in dummy cells are discontinuous and electrically floating. |
US09634129B2 |
Insulated gate bipolar transistor (IGBT) and related methods
An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and the gate trench and electrically isolating the gate trench from an electrically conductive layer. A contact opening in the electrically insulative layer extends into the emitter trench and the electrically conductive layer electrically couples with the emitter trench therethrough. A P surface doped (PSD) region and an N surface doped (NSD) region are each located between the electrically conductive layer and a plurality of semiconductor layers of the IGBT and between the gate trench and the emitter trench. The electrically conductive layer electrically couples to the plurality of semiconductor layers through the PSD region and/or the NSD region. |
US09634127B2 |
FinFET device and method for fabricating same
Methods are disclosed herein for fabricating integrated circuit devices, such as fin-like field-effect transistors (FinFETs). An exemplary method includes forming a first semiconductor material layer over a fin portion of a substrate; forming a second semiconductor material layer over the first semiconductor material layer; and converting a portion of the first semiconductor material layer to a first semiconductor oxide layer. The fin portion of the substrate, the first semiconductor material layer, the first semiconductor oxide layer, and the second semiconductor material layer form a fin. The method further includes forming a gate stack overwrapping the fin. |
US09634122B2 |
Device boost by quasi-FinFET
Some embodiments relate to an integrated circuit (IC) including one or more field-effect transistor devices. A field effect transistor device includes source/drain regions disposed in an active region of a semiconductor substrate and separated from one another along a first direction by a channel region. A shallow trench isolation (STI) region, which has an upper STI surface, laterally surrounds the active region. The STI region includes trench regions, which have lower trench surfaces below the upper STI surface and which extend from opposite sides of the channel region in a second direction which intersects the first direction. A metal gate electrode extends in the second direction and has lower portions which are disposed in the trench regions and which are separated from one another by the channel region. The metal gate electrode has an upper portion bridging over the channel region to couple the lower portions to one another. |
US09634121B2 |
Method of manufacturing display panel
A method of manufacturing a display panel having a plurality of lightly doped drain thin film transistors arranged as a matrix includes forming a semiconductor pattern with a predetermined shape on a substrate; forming a dielectric layer covering the semiconductor pattern on the substrate; forming a metal layer on the dielectric layer; forming a photoresist patterns smaller than the semiconductor pattern on the metal layer above the semiconductor pattern; etching the metal layer to form a gate electrode smaller than the photoresist pattern; doping high concentration ions by using the photoresist pattern as a mask to form a pair of highly doped regions on the semiconductor pattern not covered by the photoresist pattern; removing the photoresist pattern; and doping low concentration ions by using the gate electrode as a mask to form a pair of lightly doped regions between the highly doped regions and a part of the semiconductor pattern. |
US09634117B2 |
Self-aligned contact process enabled by low temperature
Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity. |
US09634114B2 |
Tunnel field-effect transistor, method for manufacturing same, and switch element
A tunnel field-effect transistor (TFET) is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting p-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. Alternatively, the tunnel field-effect transistor is configured by disposing a III-V compound semiconductor nano wire on a (111) plane of a IV semiconductor substrate exhibiting n-type conductivity, and arbitrarily disposing electrodes of a source, drain and gate. The nano wire is configured from a first region and a second region. For instance, the first region is intermittently doped with a p-type dopant, and the second region is doped with an n-type dopant. |
US09634113B2 |
Fully silicided linerless middle-of-line (MOL) contact
A method of making a semiconductor device includes forming a source/drain region on a substrate; disposing a gate stack on the substrate and adjacent to the source/drain region, the gate stack including a gate spacer along a sidewall of the gate stack; disposing an inter-level dielectric (ILD) layer on the source/drain region and the gate stack; removing a portion of the ILD layer on the source/drain region to form a source/drain contact pattern; filling the source/drain contact pattern with a layer of silicon material, the layer of silicon material being in contact with the source/drain region and in contact with the gate spacer; depositing a metallic layer over the first layer of silicon material; and performing a silicidation process to form a source/drain contact including a silicide. |
US09634112B2 |
Field effect transistor and method of fabricating the same
A field effect transistor is provided. The field effect transistor may include a capping layer on a substrate, a source ohmic electrode and a drain ohmic electrode on the capping layer, a first insulating layer and a second insulating layer stacked on the capping layer to cover the source and drain ohmic electrodes, a Γ-shaped gate electrode including a leg portion and a head portion, the leg portion being connected to the substrate between the source ohmic electrode and the drain ohmic electrode, and the head portion extending from the leg portion to cover a top surface of the second insulating layer, a first planarization layer on the second insulating layer to cover the Γ-shaped gate electrode, and a first electrode on the first planarization layer, the first electrode being connected to the source ohmic electrode or the drain ohmic electrode. |
US09634111B2 |
Passivation technique for wide bandgap semiconductor devices
A method of protecting a semiconductor structure from water and a semiconductor structure formed by the method. The semiconductor structure includes a wide-bandgap semiconductor material in which at least one semiconductor device is formed. The method includes heating the semiconductor structure in a vacuum to a temperature of at least 200° C. to remove water from the semiconductor structure. The method also includes, after the heating of the semiconductor structure, forming a layer comprising a hydrophobic material over the semiconductor structure. The semiconductor structure is kept in the vacuum between the heating of the semiconductor structure and the forming of the layer comprising the hydrophobic material. |
US09634110B2 |
POC process flow for conformal recess fill
A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a sacrificial gate material and a hard mask layer; forming a first gate spacer along a sidewall of the first dummy gate and a second gate spacer along a sidewall of the second dummy gate; performing an epitaxial growth process to form a source/drain on the substrate between the first and second dummy gates; disposing a conformal liner over the first and second dummy gates and the source/drain; disposing an oxide on the conformal liner between the first and second dummy gates; recessing the oxide to a level below the hard mask layers of the first and second dummy gates to form a recessed oxide; and depositing a spacer material over the recessed oxide between the first dummy gate and the second dummy gate. |
US09634108B2 |
Method of manufacturing a device by locally heating one or more metalization layers and by means of selective etching
A method of manufacturing a device comprises depositing one or more metallization layers to a substrate, locally heating an area of the one or more metallization layers to obtain a substrate/metallization-layer compound or a metallization-layer compound, the compound comprising an etch-selectivity toward an etching medium which is different to that of the one or more metallization layers outside the area, and removing the one or more metallization layers in the area or outside the area, depending on the etching selectivity in the area or outside the area, by etching with the etching medium to form the device. |
US09634107B2 |
Low temperature ohmic contacts for III-N power devices
The disclosure relates to a method for manufacturing an Au-free ohmic contact for an III-nitride (III-N) device on a semiconductor substrate and to a III-N device obtainable therefrom. The III-N device includes a buffer layer, a channel layer, a barrier layer, and a passivation layer. A 2DEG layer is formed at an interface between the channel layer and the barrier layer. The method includes forming a recess in the passivation layer and in the barrier layer up to the 2DEG layer, and forming an Au-free metal stack in the recess. The metal stack comprises a Ti/Al bi-layer, with a Ti layer overlying and in contact with a bottom of the recess, and a Al layer overlying and in contact with the Ti layer. A thickness ratio of the Ti layer to the Al layer is between 0.01 to 0.1. After forming the metal stack, a rapid thermal anneal is performed. Optionally, prior to forming the Ti/Al bi-layer, a silicon layer may be formed in contact with the recess. |
US09634101B2 |
Semiconductor component with a monocrystalline semiconductor region arranged in a via region
A MOS transistor semiconductor component includes a semiconductor body with first and second surfaces, a first contact electrode on the first surface, a second contact electrode on the second surface, a first insulation layer separating a via region at least from a drift region, a monocrystalline semiconductor region arranged in the via region and extending between the first surface and the second surface, a gate electrode electrically connected to the first contact electrode, a source electrode electrically insulated from the gate electrode, and arranged at least partially above the first surface, and a drain electrode electrically insulated from the second contact electrode on the second surface. The MOS transistor has a gate terminal formed by the second contact electrode and electrically connected to a gate-electrode of the MOS transistor through the via region. The gate-electrode is formed next to the first surface and disposed outside the via region. |
US09634096B2 |
Semiconductor device with trench isolation
A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer. |
US09634094B1 |
Strain-enhanced transistors with adjustable layouts
A transistor may include a semiconductor region such as a rectangular doped silicon well. Gate fingers may overlap the silicon well. The gate fingers may be formed from polysilicon and may be spaced apart from each other along the length of the well by a fixed gate-to-gate spacing. The edges of the well may be surrounded by field oxide. Epitaxial regions may be formed in the well to produce compressive or tensile stress in channel regions that lie under the gate fingers. The epitaxial regions may form source-drain terminals. The edges of the field oxide may be separated from the nearest gate finger edges by a distance that is adjusted automatically with a computer-aided-design tool and that may be larger than the gate-to-gate spacing. Dummy gate finger structures may be provided to ensure desired levels of stress are produced. |
US09634091B2 |
Silicon and silicon germanium nanowire formation
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon and silicon germanium stacks are utilized to form PMOS transistors comprising germanium nanowire channels and NMOS transistors comprising silicon nanowire channels. In an example, a first silicon and silicon germanium stack is oxidized to transform silicon to silicon oxide regions, which are removed to form germanium nanowire channels for PMOS transistors. In another example, silicon and germanium layers within a second silicon and silicon germanium stack are removed to form silicon nanowire channels for NMOS transistors. PMOS transistors having germanium nanowire channels and NMOS transistors having silicon nanowire channels are formed as part of a single fabrication process. |
US09634089B2 |
Selective amorphization for signal isolation and linearity
Provided is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and a method for the structure's fabrication. The structure comprises a gate situated on the top semiconductor layer, the top semiconductor layer situated over a base oxide layer, and the base oxide layer situated over a handle wafer. The top surface of the handle wafer is amorphized by an inert implant of Xenon or Argon to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer. |
US09634086B2 |
Method of manufacturing semiconductor devices using light ion implantation and semiconductor device
A first doped region is formed in a single crystalline semiconductor substrate. Light ions are implanted through a process surface into the semiconductor substrate to generate crystal lattice vacancies between the first doped region and the process surface, wherein a main beam axis of an implant beam used for implanting the light ions deviates by at most 1.5 degree from a main crystal direction along which channeling of the light ions occurs. A second doped region with a conductivity type opposite to the first doped region is formed based on the crystal lattice vacancies and hydrogen atoms. |
US09634082B2 |
Semiconductor device and method for manufacturing semiconductor device
A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor. |
US09634078B2 |
Organic display device
The present inversion provides an organic display device comprising at least infrared display pixel, the infrared display pixel includes a transparent substrate which is deposited with a first electrode layer, an infrared organic light emitting layer and a second electrode layer thereon, and the infrared organic light emitting layer is filled with an infrared light emitting material. The present invention can allow the organic display device to carry out large area of infrared display; and the present invention uses the flexible transparent substrate, so as to conveniently use and carry the organic display device. |
US09634070B2 |
Organic light emitting display device
An organic light emitting display device includes: a display panel including scan lines, and pixels, a pixel of the pixels including: a driving transistor having a gate electrode; an insulator layer disposed on the gate electrode of the driving transistor; an electrode disposed on the insulator layer and coupled to the gate electrode of the driving transistor through a first contact hole; a first passivation layer disposed on the electrode; a first voltage line disposed on the first passivation layer and configured to supply a first voltage; a second passivation layer disposed on the first voltage line; and an organic light emitting diode (OLED) having an anode coupled to the driving transistor, wherein the anode is disposed on the second passivation layer, and wherein the first voltage line overlaps with the electrode and the anode. |
US09634069B2 |
Display device
A display device includes an element substrate including a display area where a plurality of self-light-emitting elements are formed, and a driver IC disposed outside the display area in the element substrate. A first metal layer is disposed on the reverse side of the element substrate at a position opposite to the display area. A second metal layer is disposed with a space between the first metal layer and the second metal layer on the reverse side of the element substrate at a position opposite to the driver IC. |
US09634067B2 |
Electro-optical apparatus, manufacturing method for electro-optical apparatus, and electronic device
An electro-optical apparatus includes a first pixel and a second pixel. The first pixel and the second pixel include a reflective layer, an insulating layer, a functional layer, and an opposing electrode. The insulating layer includes a first insulating layer, a second insulating layer having a first opening, and a third insulating layer having a second opening. A first pixel electrode is provided on the first insulating layer in the first opening. A second pixel electrode is provided on the second insulating layer. |
US09634064B2 |
Semiconductor memory device having stacked word lines and conductive pillar
According to one embodiment, a manufacturing method of a semiconductor memory device includes forming a stacked body in which word line material layers and insulating layers are alternately stacked on a base layer. The method includes forming first holes on the stacked body so as to be arranged in a first direction and in a second direction that intersects with the first direction. The method includes forming resistance-change films on inner walls of the first holes, forming bit lines inside the resistance-change films in the first holes, and dividing the stacked body in the first direction by forming second holes so that a portion in the stacked body adjacent to the resistance-change films in the second direction. The method includes forming inter-bit line insulating films in the second holes. |
US09634062B2 |
Light sources utilizing segmented LEDs to compensate for manufacturing variations in the light output of individual segmented LEDs
A light source and method for making the same are disclosed. The light source includes a plurality of Segmented LEDs connected in parallel to a power bus and a controller. The power bus accepts a variable number of Segmented LEDs. The controller receives AC power and provides a power signal on the power bus. Each Segmented LED is characterized by a driving voltage that is greater than 3 times the driving voltage of a conventional LED fabricated in the same material system as the Segmented LED. The number of Segmented LEDs in the light source is chosen to compensate for variations in the light output of individual Segmented LEDs introduced by the manufacturing process. In another aspect of the invention, the number of Segmented LEDs connected to the power bus can be altered after the light source is assembled. |
US09634054B2 |
Solid-state image pickup device and method of driving the same
A solid-state image pickup device includes: a photoelectric conversion element including a charge accumulation region, the photoelectric conversion element performing photoelectric conversion on incident light and accumulating, in the charge accumulation region, electric charge obtained through the photoelectric conversion; a charge-voltage conversion element accumulating the electric charge obtained through the photoelectric conversion; and a charge accumulation element adjacent to the photoelectric conversion element, part or all of the charge accumulation element overlapping the charge accumulation region, and the charge accumulation element adding capacitance to capacitance of the charge-voltage conversion element. |
US09634051B2 |
Optical devices, in particular computational cameras, and methods for manufacturing the same
Then optical device comprises a first member (P) and a second member (O) and, arranged between said first and second members, a third member (S) referred to as spacer. The spacer (S) comprises —one or more portions referred to as distancing portions (Sd) in which the spacer has a vertical extension referred to as maximum vertical extension; —at least two separate portions referred to as open portions (4) in which no material of the spacer is present; and —one or more portions referred to as structured portions (Sb) in which material of the spacer is present and in which the spacer has a vertical extension smaller than said maximum vertical extension. Such optical devices can be used in or as multi-aperture cameras. |
US09634047B2 |
Solid-state image pickup device, method of manufacturing solid-state image pickup device, and electronic apparatus
There is provided a solid-state image pickup device including: a semiconductor substrate (21); a photodiode (11A, 11B) formed in the semiconductor substrate; a transistor (10) having a gate electrode (14) part or all of which is embedded in the semiconductor substrate, the transistor being configured to read a signal electric charge from the photodiode via the gate electrode; and an electric charge transfer layer (13) provided between the gate electrode and the photodiode. |
US09634040B2 |
Array substrate and curved display device
The Present disclosure relates to the field of display technology and discloses an array substrate and a curved display device which can solve the technical problem of dark area on both sides of the existing curved display device. The array substrate according to the present disclosure comprises a number of sub pixel units arranged as an array, each sub pixel unit comprising a main sub pixel, a secondary sub pixel and a voltage-dividing capacitor. Said array substrate is divided into a compensation region and a non-compensation region. The capacitance of the voltage-dividing capacitor of the sub pixel unit in the compensation region is smaller than that of the voltage-dividing capacitor of the sub pixel unit in the non-compensation region. The present disclosure is applicable to curved display devices such as curved television and curved display, etc. |
US09634037B2 |
Array substrate for display devices
An array substrate for display devices is provided. According to an exemplary embodiment, the array substrate for display device includes: a plurality of gate lines that extend along a first direction; and a data line that is formed by connecting a plurality of first sub-data lines extending along a second direction and a plurality of second sub-data lines extending along a third direction, wherein the gate lines overlap the second sub-data lines with an insulating layer interposed therebetween. |
US09634034B2 |
Display panel, display apparatus having the same and method of manufacturing the same
A display panel includes a display area configured to display an image, and a peripheral area adjacent to the display area. The peripheral area includes a pad area in which a plurality of output pads are disposed. The output pads are arranged in a matrix formed having M row*N column (M and N are normal numbers, M is 3 or larger than 3). Each of the output pads has a center of the output pad spaced apart from a center of an adjacent output pad by a distance D in a first direction. Each of the output pads is spaced apart from an adjacent output pad by a gap. Each of the output pads has a center of the output pad spaced apart from a center of an adjacent output pad by a pitch P in a second direction which is substantially perpendicular to the first direction. An equation “P |
US09634032B2 |
Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (53′) with ion doping process; the method implements the patterning process to the bottom gate isolation layer (31) and the top gate isolation layer (32) at the same time with one photo process; the method manufactures the first top gate (71), the first source (81), the first drain (82), the second top gate (72), the second source (83), the second drain (84) at the same time with one photo process; the method implements patterning process to the flat layer (9), the passivation layer (8) and the top gate isolation layer (32) at the same time with one photo process, to reduce the number of the photo processes to five for shortening the manufacture procedure, raising the production efficiency and lowering the production cost. |
US09634031B2 |
Semiconductor device comprising oxide semiconductor
To suppress change in electric characteristics and improve reliability of a semiconductor device including a transistor formed using an oxide semiconductor. A semiconductor device includes a transistor including a gate electrode, a first insulating film, an oxide semiconductor film, a second insulating film, and a pair of electrodes. The gate electrode and the oxide semiconductor film overlap with each other. The oxide semiconductor film is located between the first insulating film and the second insulating film and in contact with the pair of electrodes. The first insulating film is located between the gate electrode and the oxide semiconductor film. An etching rate of a region of at least one of the first insulating film and the second insulating film is higher than 8 nm/min when etching is performed using a hydrofluoric acid. |
US09634028B2 |
Metallized junction FinFET structures
FinFET devices are provided wherein the current path is minimized and mostly limited to spacer regions before the channel carriers reach the metal contacts. The fins in the source/drain regions are metallized to increase the contact area and reduce contact resistance.Selective removal of semiconductor fins in the source/drain regions following source/drain epitaxy facilitates replacement thereof by the metallized fins. A spacer formed subsequent to source/drain epitaxy prevents the etching of extension/channel regions during semiconductor fin removal. |
US09634027B2 |
CMOS structure on SSOI wafer
A method of forming fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device are described. The method includes forming a strained silicon-on-insulator (SSOI) layer in both a pFET region and an nFET region, etching the strained silicon layer, the insulator, and a portion of the bulk substrate in only the pFET region to expose the bulk substrate, epitaxially growing silicon (Si) from the bulk substrate in only the pFET region, and epitaxially growing additional semiconductor material on the Si in only the pFET region. The method also includes forming fins from the additional semiconductor material and a portion of the Si grown on the bulk substrate in the pFET region, and forming fins from the strained silicon layer and the insulator in the nFET region. |
US09634023B2 |
Vertical memory devices
According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other. |
US09634018B2 |
Split gate non-volatile memory cell with 3D finFET structure, and method of making same
A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively. |
US09634014B2 |
Method of making a programmable cell and structure thereof
A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region. |
US09634011B2 |
Semiconductor device having buried gate structure and method for manufacturing the same, memory cell having the same and electronic device having the same
A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer. |
US09634009B1 |
System and method for source-drain extension in FinFETs
A fin-type field effect transistor (finFET) device includes a gate disposed over at least two fins, each fin defining a source outboard portion and a drain outboard portion extending beyond the gate. There is a source contact that electrically connects the source outboard portions of the fins, and similarly on the opposed side of the gate there is a drain contact electrically connecting the drain outboard portions of the fins. A first dielectric spacer layer is disposed adjacent to the gate and overlying the fins, and a second dielectric spacer layer is disposed adjacent to the first spacer layer and also overlying the fins. The second dielectric spacer layer electrically isolates the gate from the drain contact and/or from the source contact. A method of making a finFET device is also detailed. |
US09634008B2 |
Semiconductor device and manufacturing method of semiconductor device
According to one embodiment, a semiconductor device includes an element isolation insulating film, a gate electrode film, source/drain regions, a channel region, and an air gap. The element isolation insulating film partitions an element arrangement area on one main face side of a semiconductor substrate. The channel region is disposed near a surface of the semiconductor substrate below the gate electrode film. The air gap is disposed at a region of the element isolation insulating film contacting with the channel region. |
US09634003B2 |
Special construct for continuous non-uniform RX FinFET standard cells
Methods for abutting two cells with different sized diffusion regions and the resulting devices are provided. Embodiments include abutting a first cell having first drain and source diffusion regions and a second cell having second drain and source diffusion regions, larger than the first diffusion regions, by: forming a dummy gate at a boundary between the two cells; forming a continuous drain diffusion region having an upper portion crossing the dummy gate and encompassing the entire first drain diffusion region and part of the second drain diffusion region and having a lower portion beginning over the dummy gate and encompassing a remainder of the second drain diffusion region; forming a continuous source diffusion region that is the mirror image of the continuous drain diffusion region; and forming a poly-cut mask over the dummy gate between, but separated from, the continuous drain and source diffusion regions. |
US09633997B2 |
Semiconductor device and method for manufacturing semiconductor device
A semiconductor device, in which, in a density distribution of first conductivity type impurities in the first conductivity type region measured along a thickness direction of the semiconductor substrate, a local maximum value N1, a local minimum value N2, a local maximum value N3, and a density N4 are formed in this order from front surface side, a relationship of N1>N3>N2>N4 is satisfied, a relationship of N3/10>N2 is satisfied, and a distance “a” from the surface to the depth having the local maximum value N1 is larger than twice a distance “b” from the depth having the local maximum value N1 to the depth having the local minimum N2. |
US09633988B2 |
Apparatuses and methods of communicating differential serial signals including charge injection
Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed. |
US09633986B2 |
Technique for fabrication of microelectronic capacitors and resistors
A sequence of semiconductor processing steps permits formation of both vertical and horizontal nanometer-scale serpentine resistors and parallel plate capacitors within a common structure. The method takes advantage of a CMP process non-uniformity in which the CMP polish rate of an insulating material varies according to a certain underlying topography. By establishing such topography underneath a layer of the insulating material, different film thicknesses of the insulator can be created in different areas by leveraging differential polish rates, thereby avoiding the use of a lithography mask. In one embodiment, a plurality of resistors and capacitors can be formed as a compact integrated structure within a common dielectric block, using a process that requires only two mask layers. The resistors and capacitors thus formed as a set of integrated circuit elements are suitable for use as microelectronic fuses and antifuses, respectively, to protect underlying microelectronic circuits. |
US09633984B2 |
Semiconductor module
According to one embodiment, a semiconductor module includes a first semiconductor element, a second semiconductor element, a first light emitting element and a second light emitting element. The first semiconductor element is provided with a first light receiving circuit and a first output circuit. The second semiconductor element is provided with a second light receiving circuit and a second output circuit. The first light emitting element is electrically connected to the second output circuit and mounted on the first semiconductor element such that first light emitted from the first light emitting element is received by the first light receiving circuit. The second light emitting element is electrically connected to the first output circuit and mounted on the second semiconductor element such that second light emitted from the second light emitting element is received by the second light receiving circuit. |
US09633978B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a wiring substrate, a first semiconductor chip flip-chip connected to the wiring substrate, a first underfill resin filled between the wiring substrate and the first semiconductor chip, the first underfill resin including a pedestal portion arranged in a periphery of the first semiconductor chip, a second semiconductor chip flip-chip connected to the first semiconductor chip, and being larger in area than the first semiconductor chip, and a second underfill resin filled between the first semiconductor chip and the second semiconductor chip, the second underfill resin covering an upper face of the pedestal portion of the first underfill resin and a side face of the second semiconductor chip. |
US09633972B2 |
Method for manufacturing semiconductor display panel
A manufacturing method includes: attaching a film onto a bonding surface of a wafer; performing laser cutting on the wafer to obtain a plurality of semiconductor light-emitting eutectic chips; attaching light-emitting surfaces of the plurality of eutectic chips on to an expansion film; detaching films from bonding surfaces of the plurality of eutectic chips; performing wafer expansion on the expansion film so that the plurality of eutectic chips have the same intervals as chip loading spaces on a substrate; attaching the expansion film onto a tray, and moving the tray so that positions of the plurality of eutectic chips correspond to that of the chip loading spaces; moving the tray so that the plurality of eutectic chips approach the chip loading spaces on the substrate; and embedding the plurality of eutectic chips into the chip loading spaces so that the plurality of eutectic chips are electrically connected to the substrate. |
US09633971B2 |
Structures and methods for low temperature bonding using nanoparticles
A method of making an assembly can include forming a first conductive element at a first surface of a substrate of a first component, forming conductive nanoparticles at a surface of the conductive element by exposure to an electroless plating bath, juxtaposing the surface of the first conductive element with a corresponding surface of a second conductive element at a major surface of a substrate of a second component, and elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles cause metallurgical joints to form between the juxtaposed first and second conductive elements. The conductive nanoparticles can be disposed between the surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. |
US09633966B2 |
Stacked semiconductor package and manufacturing method thereof
A stacked semiconductor package and a manufacturing method thereof. For example and without limitation, various aspects of this disclosure provide a semiconductor package in which an upper interposer and/or package are electrically and mechanically coupled to a lower package utilizing an adhesive member comprising conductive particles. |
US09633965B2 |
Semiconductor structure and manufacturing method of the same
The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the semiconductor die and a second surface opposing to the first surface. The first surface includes a core region having a plurality of landing pads and a periphery region surrounding the core region and having a plurality of landing traces. A pitch of the landing pads is from about 55 μm to about 280 μm. The semiconductor die includes a third surface facing the first surface of the substrate and a fourth surface opposing to the third surface. The third surface includes a plurality of elongated bump positioned correspondingly to the landing pads and the landing traces of the substrate, and the elongated bump includes a long axis and a short axis perpendicular to the long axis on a cross section thereof. |
US09633964B2 |
Wiring substrate and electronic component device
A wiring substrate includes a connection pad formed in the outermost wiring layer, a dummy pad formed in the outermost wiring layer, and a dummy wiring portion formed in the outermost wiring layer, the dummy wiring portion connecting the connection pad and the dummy pad. The maximum width of each of the connection pad and the dummy pad is set to be larger than the width of the dummy wiring portion. A bump of an electronic component is flip-chip connected to a connection pad through a resin-containing solder. |
US09633961B2 |
Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to a second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element comprises a first side and a second side coupled to the first side. The first side and the second side of the transition element are non-tangential to the PPI pad. |
US09633960B2 |
Chip with I/O pads on peripheries and method making the same
A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; at least two metal layers, formed above the substrate, each metal layer forming a specific circuit, wherein two adjacent metal layers are separated by an inter-metal dielectric layer; and a passivation layer, formed on a top side of the chip. By changing the I/O pad from the top of the chip to the peripheries, the extra thickness of the packaged chip caused by wire bonding in the prior arts can be reduced. |
US09633959B2 |
Integrated circuit die with corner IO pads
An integrated circuit (IC) die has side input/output (IO) pads located along each side of the die interior. Each die corner has a corner IO pad. The side IO pads adjacent to the corner IO pads have shortened passivation regions in the top metal layer (TML) that define TML access regions. TML traces run through the TML access regions to connect the corner IO pads to the die interior. Providing corner IO pads enables an IC die to have up to four more IO pads than a comparable conventional IC die that does not have any corner IO pads, or an IC die to have the same number of IO pads within a smaller overall footprint. |
US09633955B1 |
Semiconductor integrated circuit structure including dielectric having negative thermal expansion
A semiconductor IC structure includes a semiconductor substrate, a multi-layered dielectric structure disposed on the semiconductor substrate, a first conductive layer disposed in the multi-layered dielectric structure, and a second conductive layer disposed on the multi-layered dielectric structure. The multi-layered dielectric structure further includes a first dielectric layer disposed on the semiconductor substrate, and a second dielectric layer disposed on the first dielectric layer. A coefficient of thermal expansion (CTE) of the first dielectric layer is larger than zero, and a CTE of the second dielectric layer is smaller than zero. |
US09633953B2 |
Methodology to achieve zero warpage for IC package
A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness. |
US09633951B2 |
Semiconductor package including a semiconductor die having redistributed pads
A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die. |
US09633949B2 |
Copper etching integration scheme
The present disclosure is directed to an integrated circuit. The integrated circuit has a conductive body disposed over a substrate. The conductive body has tapered sidewalls that cause an upper surface of the conductive body to have a greater width than a lower surface of the conductive body. The integrated circuit also has a projection disposed over the conductive body. The projection has tapered sidewalls that cause a lower surface of the projection to have a greater width than an upper surface of the projection and a smaller width than an upper surface of the conductive body. A dielectric material surrounds the conductive body and the projection. |
US09633948B2 |
Low energy etch process for nitrogen-containing dielectric layer
A stack that includes, from bottom to top, a nitrogen-containing dielectric layer, an interconnect level dielectric material layer, and a hard mask layer is formed on a substrate. The hard mask layer and the interconnect level dielectric material layer are patterned by an etch. Employing the patterned hard mask layer as an etch mask, the nitrogen-containing dielectric layer is patterned by a break-through anisotropic etch, which employs a fluorohydrocarbon-containing plasma to break through the nitrogen-containing dielectric layer. Fluorohydrocarbon gases used to generate the fluorohydrocarbon-containing plasma generate a carbon-rich polymer residue, which interact with the nitrogen-containing dielectric layer to form volatile compounds. Plasma energy can be decreased below 100 eV to reduce damage to physically exposed surfaces of the interconnect level dielectric material layer. |
US09633947B2 |
Folded ballistic conductor interconnect line
A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material. |
US09633940B2 |
Structure and method for a high-K transformer with capacitive coupling
The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer. |
US09633938B2 |
Hybrid pitch package with ultra high density interconnect capability
A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts). |
US09633936B2 |
Semiconductor package
A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate. First and second conductive traces are disposed on the substrate. A conductive pillar bump is disposed on the second conductive trace, and a first conductive structure is disposed between the second conductive trace and the conductive pillar bump or between the second conductive trace and the substrate. A semiconductor die is disposed over the first conductive trace, wherein the conductive pillar bump connects to the semiconductor die. |
US09633927B2 |
Chip arrangement and method for producing a chip arrangement
A chip arrangement includes semiconductor chips coupled to opposing sides of an insulating layer. The arrangement includes a first semiconductor chip having a first chip surface presenting a first chip conductive region. An electrically insulating layer includes a first layer surface presenting a first layer conductive region, and a second, opposing surface presenting a second layer conductive region. The electrically insulating layer is coupled to the first semiconductor chip by applying the first layer conductive region to the first chip conductive region. The electrically insulating layer is then coupled to the second chip conductive region by applying the second layer conductive region to the second chip conductive region. |
US09633924B1 |
Package structure and method for forming the same
A package structure and method for forming the same are provided. The package structure includes a substrate and a semiconductor die formed over the substrate. The package structure also includes a package layer covering the semiconductor die and a conductive structure formed in the package layer. The package structure includes a first insulating layer formed on the conductive structure, and the first insulating layer includes monovalent metal oxide. A second insulating layer is formed between the first insulating layer and the package layer. The second insulating layer includes monovalent metal oxide, and a weight ratio of the monovalent metal oxide in the second insulating layer is greater than a weight ratio of the monovalent metal oxide in first insulating layer. |
US09633920B2 |
Low damage passivation layer for III-V based devices
The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer. |
US09633919B2 |
Package structure with an elastomer with lower elastic modulus
A package structure includes a substrate, at least one electronic component, a housing and at least one strut. The at least one electronic component is disposed on a first surface of the substrate. The housing covers the first surface of the substrate. The housing has an accommodation space. The at least one electronic component is accommodated within the accommodation space. The at least one strut is protruded from an inner surface of the housing and extended toward the accommodation space. The at least one elastomer is arranged between the corresponding strut and the substrate. |
US09633915B1 |
Method of using dummy patterns for overlay target design and overlay control
Methodologies for using dummy patterns for overlay target design and overlay control are provided. Embodiments include providing a first dummy pattern on a first layer as an outer overlay target for an integrated circuit (IC); providing a pattern associated with a second dummy pattern on a second layer as a target for measuring overlay; and utilizing a scanning electron microscope (SEM) to obtain an overlay measurement between the first and second dummy patterns. |
US09633910B2 |
Backside contacts for integrated circuit devices
A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a transistor formed at a front side of the semiconductor substrate. A source/drain region of the transistor is disposed in the well region. A well pickup region is disposed in the well region, wherein the well pickup region is at a back side of the semiconductor substrate. A through-via penetrates through the semiconductor substrate, wherein the through-via electrically inter-couples the well pickup region and the source/drain region. |
US09633907B2 |
Self-aligned nanowire formation using double patterning
A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned multi-patterning process is performed to pattern a pattern-reservation layer. The remaining portions of the pattern-reservation layer include pattern-reservation strips extending in a first direction that is parallel to the major surface of the semiconductor substrate. A second self-aligned multi-patterning process is performed to pattern the pattern-reservation layer in a second direction parallel to the major surface of the semiconductor substrate. The remaining portions of the pattern-reservation layer include patterned features. The patterned features are used as an etching mask to form semiconductor nanowires by etching the semiconductor substrate. |
US09633905B2 |
Semiconductor fin structures and methods for forming the same
A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region. |
US09633902B2 |
Method for manufacturing semiconductor device that includes dividing semiconductor substrate by dry etching
According to an embodiment, a method for manufacturing a semiconductor device includes: selectively forming a plurality of mask layers on a first surface of a semiconductor substrate, and the semiconductor substrate having the first surface and a second surface; dividing the semiconductor substrate by forming a gap piercing from the first surface to the second surface of the semiconductor substrate, the gap being formed by dry-etching the first surface of the semiconductor substrate exposed between the plurality of mask layers, and a width of the gap on the second surface side being larger than a width of the gap on the first surface side; and forming a first electrode under a reduced-pressure atmosphere on the first surface of the semiconductor substrate after the semiconductor substrate being divided. |
US09633901B2 |
Method for manufacturing semiconductor device
A method for manufacturing a semiconductor device is provided. The method includes forming a first semiconductor element and a second semiconductor element in a semiconductor wafer. The first semiconductor element includes a first electrode formed on a front surface of the semiconductor wafer. The second semiconductor element is adjacent to the first semiconductor element and includes a second electrode formed on the front surface. The method further includes forming a first insulating layer on the front surface located at a first boundary portion between the first electrode and the second electrode; applying a specific potential different from a potential of the second electrode on the first electrode after the formation of the first insulating layer; and cutting the semiconductor wafer at the first boundary portion so as to divide the first semiconductor element from the second semiconductor element. |
US09633899B2 |
Method for patterning a graphene layer and method for manufacturing a display substrate
The invention provides a method for patterning a graphene layer and a method for manufacturing a display substrate. The method for patterning a graphene layer comprises: forming an isolation layer on a graphene layer; forming a photoresist layer on the isolation layer; patterning the photoresist layer; etching the isolation layer according to the patterned photoresist layer to form a patterned isolation layer; etching the graphene layer according to the patterned photoresist layer to form a patterned graphene layer; and removing the patterned isolation layer. In the method of the invention, the unfavorable condition of the prior art may be avoided that a graphene film sloughs off or a photoresist remains on a graphene film when a photoresist material is peeled off, and the product yield can be improved in the case that the production cost is controlled. |
US09633892B2 |
Method for manufacturing SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced and method for manufacturing semiconductor device
A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced even if a single crystal semiconductor substrate including crystal defects is used. A first oxide film is formed on a single crystal semiconductor substrate; the first oxide film is removed; a surface of the single crystal semiconductor substrate from which the first oxide film is removed is irradiated with laser light; a second oxide film is formed on the single crystal semiconductor substrate; an embrittled region is formed in the single crystal semiconductor substrate by irradiating the single crystal semiconductor substrate with ions through the second oxide film; bonding the second oxide film and the semiconductor substrate so as to face each other; and the single crystal semiconductor substrate is separated at the embrittled region by heat treatment to obtain a single crystal semiconductor layer bonded to the semiconductor substrate. |
US09633891B2 |
Method for forming a transistor structure comprising a fin-shaped channel structure
An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other. |
US09633884B2 |
Performance enhancement of coating packaged ESC for semiconductor apparatus
An advanced coating for electrostatic chuck used in plasma processing chamber is provided. The advanced coating is formed using plasma enhanced physical vapor deposition. The coating is generally of Y2O3/Al2O3, although other material combinations can be used. Also, a multi-layered coating can be formed, such that an intermediate coating layer can be formed using standard plasma spray, and a top coating can be formed using PEPVD. The entire ESC assembly can be “packaged” by the coating. |
US09633883B2 |
Apparatus for transfer of semiconductor devices
An apparatus includes a first frame to hold a wafer tape having a first side and a second side. A plurality of semiconductor device dies are disposed on the first side of the wafer tape. A second frame includes a first clamping member and a second clamping member to clamp therebetween a product substrate having a circuit trace thereon. The second frame is configured to hold the product substrate such that the circuit trace is disposed facing the dies on the wafer tape. A needle is disposed adjacent to the second side of the wafer tape. A length of the needle extends in a direction toward the wafer tape. A needle actuator is connected to the needle to move the needle to a die transfer position. A laser points toward a portion of the product substrate corresponding to the transfer position to affix the die. |
US09633880B2 |
Elevator linear motor drive
Disclosed is a substrate processing system with a magnetic conduit configuration to improve the movement of a substrate carrier within the system. The configuration specifically provides for safe, secure movement of a carrier between multiple levels of a substrate processing system by using magnetic conduits to redirect magnetic forces created by a linear motor, permitting the linear motor to be positioned outside of the system and in a location that will not interfere with the movement of the carrier. |
US09633877B2 |
Wafer container with door mounted shipping cushions
A cushioned wafer container system having removable wafer cushions for transporting large-diameter wafers. The system includes a wafer container enclosure defining a front opening and including a rear wall, and a plurality of wafer supports defining a plurality of slots; a front door configured to attach to the wafer enclosure at the front opening and defining a front side and a rear side; a primary wafer cushion coupled to a rear side of the front door at a central portion of the front door, the primary wafer cushion defining a plurality of wafer grooves, each of the grooves of the primary wafer cushion aligned with a slot of the wafer supports; and a first removable wafer cushion attachable to the rear side of the front door adjacent the primary wafer cushion, the first removable wafer cushion defining a plurality of wafer-receiving grooves in alignment with the grooves and slots. |
US09633868B2 |
Heat treatment method and heat treatment apparatus
After a substrate implanted with impurities is heated to a preheating temperature, the front surface of the substrate is heated to a target temperature by irradiating the front surface of the substrate with a flash of light. Further, the flash irradiation is continued to maintain the temperature of the front surface near the target temperature for a predetermined time period. At this time, a flash irradiation time period in the flash heating step is made longer than a heat conduction time period required for heat conduction from the front surface of the substrate to the back surface thereof, and a difference in temperature between the front and back surfaces of the substrate is controlled to be always not more than one-half of an increased temperature from the preheating temperature to the target temperature during the flash irradiation. This alleviates the concentration of stresses resulting from a difference in thermal expansion between the front and back surfaces of the substrate to thereby prevent the cracking of the substrate. |
US09633864B2 |
Etching method
There is provided a method for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride by performing plasma processing on a target object including the second region formed to have a recess, the first region provided to fill the recess and to cover the second region, and a mask provided on the first region. The method includes: (a) generating a plasma of a processing gas containing a fluorocarbon gas in a processing chamber where the target object is accommodated and forming a deposit containing fluorocarbon on the target object; (b) generating a plasma of a processing gas containing an oxygen-containing gas and an inert gas in the processing chamber; and (c) etching the first region by radicals of fluorocarbon contained in the deposit. A sequence including the step (a), the step (b) and the step (c) is repeatedly performed. |
US09633863B2 |
Compositions and methods for selective polishing of silicon nitride materials
The present invention provides an acidic aqueous polishing composition suitable for polishing a silicon nitride-containing substrate in a chemical-mechanical polishing (CMP) process. The composition, at point of use, preferably comprises about 0.01 to about 2 percent by weight of at least one particulate ceria abrasive, about 10 to about 1000 ppm of at least one non-polymeric unsaturated nitrogen heterocycle compound, 0 to about 1000 ppm of at least one cationic polymer, optionally, 0 to about 2000 ppm of at least one polyoxyalkylene polymer, and an aqueous carrier therefor. The cationic polymer preferably is selected from a poly(vinylpyridine) polymer, a quaternary ammonium-substituted acrylate polymer, a quaternary ammonium-substituted methacrylate polymer, or a combination thereof. Methods of polishing substrates and of selectively removing silicon nitride from a substrate in preference to removal of polysilicon using the compositions are also provided. |
US09633861B2 |
Cu/barrier interface enhancement
Embodiments of the present invention provide processes to selectively form a metal layer on a conductive surface, followed by flowing a silicon based compound over the metal layer to form a metal silicide layer. In one embodiment, a substrate having a conductive surface and a dielectric surface is provided. A metal layer is then deposited on the conductive surface. A metal silicide layer is formed as a result of flowing a silicon based compound over the metal layer. A dielectric is formed over the metal silicide layer. |
US09633859B2 |
Semiconductor device and a manufacturing method thereof
The performances of a semiconductor device are improved. In a method for manufacturing a semiconductor device, a first insulation film, a conductive film, a silicon-containing second insulation film, and a third film formed of silicon are sequentially formed at the surface of a control gate electrode. Then, the third film is etched back to leave the third film at the side surface of the control gate electrode via the first insulation film, the conductive film, and the second insulation film, thereby to form a spacer. Then, the conductive film is etched back to form a memory gate electrode formed of the conductive film between the spacer and the control gate electrode, and between the spacer and the semiconductor substrate. |
US09633858B2 |
Methods for forming semiconductor device
A method for forming a semiconductor device includes forming first and second hard mask layers overlying a semiconductor substrate and forming trenches through the second hard mask, the first hard mask, and into the substrate. A dielectric material is formed in the trenches to form shallow trench isolation regions, removing the second hard mask layer, and a floating gate material is formed overlying the first hard mask and the trenches. The method further includes repeating at least twice a process of forming a buffer layer over the floating gate material and using a polishing process to remove a portion of the buffer layer and a top portion of the floating gate material. Next, a dry etch process to remove a portion of the floating gate material above the shallow trench isolation regions and the remaining portions of the buffer layer to form floating gate structures. |
US09633856B2 |
Method of forming a singe metal that performs N and P work functions in high-K/metal gate devices
The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate with a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a metal layer over the high-k dielectric layer, the metal layer having a first work function, protecting the metal layer in the first region, treating the metal layer in the second region with a de-coupled plasma that includes carbon and nitrogen, and forming a first gate structure in the first region and a second gate structure in the second region. The first gate structure includes the high-k dielectric layer and the untreated metal layer. The second gate structure includes the high-k dielectric layer and the treated metal layer. |
US09633854B2 |
MOSFET and method for manufacturing the same
The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer comprising a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being disposed on the semiconductor substrate, and the semiconductor layer being disposed on the buried insulating layer; a gate stack disposed on the semiconductor layer; a source region and a drain region embedded in the semiconductor layer and disposed on both sides of the gate stack; and a channel region embedded in the semiconductor layer and sandwiched between the source region and the drain region, wherein the MOSFET further comprises a back gate and a counter doped region, and wherein the back gate is embedded in the semiconductor substrate, the counter doped region is disposed under the channel region and embedded in the back gate, and the back gate has a doping type opposite to that of the counter doped region. The MOSFET can adjust a threshold voltage by changing the doping type of the back gate. |
US09633853B2 |
Method for forming an electrical contact
A method for forming an electrical contact to a semiconductor structure is provided. The method includes providing a semiconductor structure, providing a metal on an area of said semiconductor structure, wherein said area exposes a semiconductor material and is at least a part of a contact region, converting said metal to a Si-comprising or a Ge-comprising alloy, thereby forming said electrical contact on said area, wherein said converting is done by performing a vapor-solid reaction, whereby said semiconductor structure including said metal is subjected to a silicon-comprising precursor gas or a germanium-comprising precursor gas. |
US09633852B2 |
Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a first doped region, a second doped region, a doped strip and a top doped region. The first doped region has a first type conductivity. The second doped region is formed in the first doped region and has a second type conductivity opposite to the first type conductivity. The doped strip is formed in the first doped region and has the second type conductivity. The top doped region is formed in the doped strip and has the first type conductivity. The top doped region has a first sidewall and a second sidewall opposite to the first sidewall. The doped strip is extended beyond the first sidewall or the second sidewall. |
US09633849B2 |
Implant profiling with resist
A process for forming at least two different doping levels at the surface of a wafer using one photo resist pattern and implantation process step. A resist layer is developed (but not baked) to form a first resist geometry and a plurality of sublithographic resist geometries. The resist layer is baked causing the sublithographic resist geometries to reflow into a continuous second resist geometry having a thickness less that the first resist geometry. A high energy implant implants dopants through the second resist geometry but not through the first resist geometry. A low energy implant is blocked by both the first and second resist geometries. |
US09633848B2 |
Photosensitive resin composition, method for producing patterned cured film, semiconductor element and electronic device
Disclosed is a photosensitive resin composition comprising (A) an alkali-soluble resin having a structural unit represented by the following formula (1), (B) a compound that generates an acid by light, (C) a thermal crosslinking agent, and (D) an acryl resin having a structural unit represented by the following formula (2): wherein R1 represents a hydrogen atom or a methyl group; R2 represents an alkyl group having 1 to 10 carbon atoms, or the like; and a represents an integer of 0 to 3, b represents an integer of 1 to 3, and the total of a and b is 5 or less, and wherein R3 represents a hydrogen atom or a methyl group; and R4 represents a hydroxyalkyl group having 2 to 20 carbon atoms. |
US09633847B2 |
Using sub-resolution openings to aid in image reversal, directed self-assembly, and selective deposition
A method for treating a microelectronic substrate to form a chemical template includes patterning the substrate to form a trench structure with a plurality of trenches of a defined trench width and depositing a photoactive material on the substrate to overfill the trench structure to form a fill portion in the plurality of trenches and an overfill portion above the trench structure. The method further includes exposing the photoactive material to electromagnetic radiation comprising a wavelength that is at least four times greater than the defined trench width such that the overfill portion is modified by the exposure while the electromagnetic radiation fails to penetrate into the plurality of trenches leaving the fill portion unmodified and removing the modified overfill portion of the photoactive material to form a planarized filled trench structure for use as a chemical template for selective reactive ion etching, selective deposition, or directed self-assembly. |
US09633845B2 |
Method of manufacturing a substrate having a crystallized layer and a laser crystallizing apparatus for the same
A method of manufacturing a substrate includes: irradiating, along a first path, a laser beam emitted from a source onto a substrate, wherein the substrate includes a target layer of the laser beam, and wherein the substrate is disposed on a stage; and irradiating, along a second path, a portion the laser beam, which was emitted from the source and reached the target layer, by reflecting the laser beam back onto the target layer using a reflection mirror. An area of a second region of the target layer is greater than an area of a first region of the target layer, wherein the laser beam is irradiated along the second path in the second region, and the laser beam is irradiated along the first path in the first region. |
US09633843B2 |
Silicon substrates with compressive stress and methods for production of the same
A heterostructure may include a substrate having a first primary surface, a second primary surface, and a diffusion layer extending a depth into the substrate from the first primary surface; and a deposition layer disposed on the second primary surface of the substrate. The heterostructure may further include an epitaxial layer disposed on the deposition layer. |
US09633838B2 |
Vapor deposition of silicon-containing films using penta-substituted disilanes
Disclosed are methods of depositing silicon-containing films on one or more substrates via vapor deposition processes using penta-substituted disilanes, such as pentahalodisilane or pentakis(dimethylamino)disilane. |
US09633837B2 |
Methods of providing dielectric to conductor adhesion in package structures
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a CVD dielectric material on a package dielectric material, and then forming a conductive material on the CVD dielectric material. |
US09633833B2 |
Methods and apparatus for cleaning semiconductor wafers
A method for cleaning semiconductor substrate using ultra/mega sonic device comprising holding a semiconductor substrate by using a chuck, positioning a ultra/mega sonic device adjacent to the semiconductor substrate, injecting chemical liquid on the semiconductor substrate and gap between the semiconductor substrate and the ultra/mega sonic device, changing gap between the semiconductor substrate and the ultra/mega sonic device for each rotation of the chuck during the cleaning process by turn the semiconductor substrate or the ultra/mega sonic device clockwise or counter clockwise. |
US09633832B2 |
Method for metal gate surface clean
The present disclosure provides a method for forming an integrated circuit (IC) structure. The method includes providing a metal gate (MG), an etch stop layer (ESL) formed on the MG, and a dielectric layer formed on the ESL. The method further includes etching the ESL and the dielectric layer to form a trench. A surface of the MG exposed in the trench is oxidized to form a first oxide layer on the MG. The method further includes removing the first oxide layer using a H3PO4 solution. |
US09633827B2 |
Apparatus and method for sampling of confined spaces
In various embodiments of the invention, a cargo container can be monitored at appropriate time intervals to determine that no controlled substances have been shipped with the cargo in the container. The monitoring utilizes reactive species produced from an atmospheric analyzer to ionize analyte molecules present in the container which are then analyzed by an appropriate spectroscopy system. In an embodiment of the invention, a sorbent surface can be used to absorb, adsorb or condense analyte molecules within the container whereafter the sorbent surface can be interrogated with the reactive species to generate analyte species characteristic of the contents of the container. |
US09633818B2 |
Charged particle beam apparatus, image forming method using a charged particle beam apparatus, and image processing apparatus
To provide a charged particle beam apparatus capable of obtaining an image with high contrast and high visibility, the apparatus has: a charged particle optical system; a detection part to detect secondary charged particles generated from the sample; an image formation part to receive a detection signal from the detection part and form an image of the sample; an image processing part to process the image formed with the image formation part; and a display part to display the result of processing with the image processing part, wherein the image formation part has a pulse-count signal processing part to generate cumulative histogram information on a pulse signal component in the detection signal, set a threshold value for pulse signal detection using information on the generated cumulative histogram, and output a detection signal having a value higher than the set threshold value as a pulse signal. |
US09633815B1 |
Emitter for an electron beam, electron beam device and method for producing and operating an electron emitter
A cold field emitter for emitting an electron beam for an electron beam device is described. The emitter includes an emitter tip having a tip surface; and two or more adjacent facets formed at the tip surface and having facet boundaries, each of the facets forming a recess in the emitter tip, wherein the facets are separated. An intermediate area is provided between and around the two or more adjacent facets and the intermediate area is configured for electron emission. Further, an electron beam device, a method for operating an electron beam device and a method for producing an emitter for an electron beam device is described. |
US09633810B2 |
Combination switch
A combination switch 10 outputs operation command signals to a driving system of a vehicle according to a switching operation of a switching unit 11 and includes a storage part 21 that stores determination information 21a indicating whether combinations of operation command signals to be outputted from switches of the switching unit 11 are abnormal or normal, a determination part 22 that refers to the determination information 21a in the storage part 21, determines whether or not a combination of the operation command signals is abnormal, and if an abnormal combination of the operation command signals continues longer than a predetermined time, adds, to the operation command signals, abnormality information indicating that the combination of the operation command signals is abnormal, and a communication part 13 that transmits the operation command signals added with the abnormality information. |
US09633809B2 |
Trip device for circuit breaker
A trip device for a circuit breaker comprises a first terminal; a second terminal; and a bimetal in which a slot with one side opened is formed at one end of the bimetal, the one end is divided into a first end portion and a second end portion, the first end portion is connected to the first terminal, and the second end portion is connected to the second terminal, wherein the bimetal generates heat with a current which flows between the first end portion and the second end portion, and a heating amount of the bimetal is changed based on a length of the slot. Accordingly, a desired rated current can be set, the bimetal can be prevented from being damaged by a fault current, and the fault current can be effectively detected by obtaining a sufficient amount of heat and a bending amount of the bimetal. |
US09633802B2 |
Vacuum bulb, circuit-breaker pole including such a vacuum bulb, and method to manufacture such devices
A vacuum bulb is provided, including a sealed chamber; two electrical contacts, which move relative to one another, the chamber including a cylindrical body of a dielectric material and closed at ends thereof by two metal covers, each of the two metal covers being connected to one of the two electrical contacts: and a dielectric coating, which covers an outer surface of the chamber, and includes at least two layers, including an overmolding layer of a synthetic material and an intermediate layer of silicone, the intermediate layer being interposed between the outer surface and the overmolding layer, the intermediate layer being discontinuous and localized on metal portions of the chamber so as to cover at least partially an outer surface of the metal portions, and the silicone includes compressible hollow bodies having a skin of a thermoplastic material. |
US09633799B2 |
Long-term energy storage assembly comprising an intermediate connection part
The invention relates to an electrical energy storage assembly comprising an envelope and a capacitive element (30) contained in the envelope, said envelope comprising: at least one side wall (22); and two bottom walls (41) each located at an end of the side wall. Said storage assembly comprises at least one electroconductive intermediate connection part (50) to be arranged between the capacitive element and a bottom wall (41), in addition to a covering plate (51) for covering the end of the capacitive element (20), said covering plate (51) including at least one vent (53) for the passage of a fluid. The covering plate (51) is fixed to the capacitive element in such a way as to be in electrical contact therewith, and the intermediate connection part (50) is also fixed to the envelope in certain areas enabling a deformation of the bottom wall in relation to the intermediate connection part. |
US09633796B2 |
High voltage tantalum anode and method of manufacture
Tantalum powders produced using a tantalum fiber precursor are described. The tantalum fiber precursor is chopped or cut into short lengths having a uniform fiber thickness and favorable aspect ratio. The chopped fibers are formed into a primary powder having a controlled size and shape, narrow/tight particle size distribution, and low impurity level. The primary powder is then agglomerated into an agglomerated powder displaying suitable flowability and pressability such that pellets with good structural integrity and uniform pellet porosity are manufacturable. The pellet is sintered and anodized to a desired formation voltage. The thusly created capacitor anode has a dual morphology or dual porosity provided by a primary porosity of the individual tantalum fibers making up the primary powder and a larger secondary porosity formed between the primary powders agglomerated into the agglomerated powder. |
US09633793B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor that contains at least one kind of a first element that forms a covalent hydride with hydrogen (except for an element generating a hydride having a boiling point of less than 125° C.) and a second element that forms a hydride in a boundary region with hydrogen between an outermost plating layer constituting an external electrode and a dielectric layer constituting a ceramic element body. |
US09633792B2 |
Conductive paste for external electrode, multilayer ceramic electronic component using the same, and manufacturing method thereof
A conductive paste for an external electrode, a multilayer ceramic electronic component using the same, and a manufacturing method of a multilayer ceramic electronic component are provided. The conductive paste for an external electrode includes first conductive particles containing a metal, second conductive particles formed of ceramic particles coated with silver (Ag), and a thermosetting resin. |
US09633791B2 |
Monolithic capacitor
A monolithic capacitor includes a multilayer body including a plurality of stacked dielectric layers, first and second capacitor electrodes inside the multilayer body, and outer electrodes on at least one surface of the multilayer body. The first and second capacitor electrodes are arranged perpendicularly or substantially perpendicularly to first and second surfaces of the multilayer body. The first capacitor electrode includes a capacitor portion opposed to the second capacitor electrode with the dielectric layer interposed therebetween, a lead portion connected to one outer electrode, and an intermediate portion not opposed to the second outer electrode. The second capacitor electrode includes a capacitor portion opposed to the first capacitor electrode with the dielectric layer interposed therebetween, and a lead portion connected to the other outer electrode. The intermediate portion is arranged in a gap area that is surrounded, when viewed in a stacking direction of the dielectric layers, by imaginary lines extending from inner exposed ends of the lead portions in a direction interconnecting the first and second surfaces of the multilayer body, by the capacitor portions, and by the first surface. |
US09633789B2 |
Laminated capacitor mounted structure
A mounted structure includes a laminated capacitor, a wiring substrate, and a joint material. The laminated capacitor includes a body with dielectric layers and internal electrode layers alternately stacked, and an external electrode connected to the internal electrode layers. The body includes a side surface coated with a side surface coating portion of the external electrode. The joint material is joined to the side surface coating portion and a land provided on the wiring substrate so as to cover the outer surfaces thereof. The outer end portion of the thickest portion of the joint material covering the side surface coating portion is located farther outside an outer end of the land in a direction perpendicular or substantially perpendicular to a side surface of the body. |
US09633787B2 |
Multilayer capacitor and installation structure of multilayer capacitor
In a multilayer capacitor, a multilayer capacitor main body includes first and second main surfaces, first and second side surfaces, and first and second end surfaces, the first and second main surfaces extending in a length direction and a width direction, the first and second side surfaces extending in the length direction and a thickness direction, and the first and second end surfaces extending in the width direction and the thickness direction. The second main surface is depressed in a portion extending from opposite ends of the second main surface toward a center of the second main surface in the length direction. |
US09633786B2 |
Multilayer capacitor and usage method therefor
A multilayer capacitor includes a multilayer body including a dielectric layer, first through third inner electrodes, and first and second capacitor sections, and first through third outer electrodes on surfaces of the multilayer body. The first capacitor section is electrically connected between the first and second outer electrodes. The second capacitor section is electrically connected between the second and third outer electrodes. The first, second, and third inner electrodes are connected to the first, second, and third outer electrodes, respectively. The first and third inner electrodes oppose each other with the dielectric layer therebetween, thus defining the first capacitor section. The second and third inner electrodes oppose each other with the dielectric layer therebetween, thus defining the second capacitor section. |
US09633785B2 |
Multilayer ceramic electronic component and board having the same
A multilayer ceramic electronic component may includes: a ceramic body including dielectric layers; an active layer including first and second internal electrodes disposed to be exposed to both end surfaces of the ceramic body in a length direction of the ceramic body, respectively, first floating electrodes overlapping the first and second internal electrodes while being spaced apart from each other in the thickness direction of the ceramic body, second floating electrodes each disposed to be spaced apart from the first and second internal electrodes, and first and second dummy electrodes disposed to be spaced apart from the first floating electrodes; upper and lower cover layers disposed upwardly and downwardly of the active layer, respectively; third and fourth dummy electrodes disposed to be exposed to both end surfaces of the ceramic body in the length direction of the ceramic body, respectively; and fifth dummy electrodes. |
US09633780B2 |
Apparatus and method for controlling resonator of wireless power transmission system
A source device configured to transmit a magnetic field via magnetic resonance with a target device includes a source resonator including a plurality of loop circuits respectively configured to generate different magnetic fields each depending on a length of a corresponding one of the plurality of loop circuits, and a circuit selector configured to select one loop circuit among the plurality of loop circuits based on information associated with the target device. |
US09633778B2 |
Magnetic component with balanced flux distribution
An embodiment of an inductor assembly includes at least a first inductive loop with a first wire formed into a plurality of conductive windings around a first magnetic core section. The first magnetic core section includes at least a radially inner magnetic core portion with a first inner effective radius, Rin(1), and a radially outer magnetic core portion with a first outer effective radius, Rout(1). The radially inner magnetic core portion is formed from a first material having a first core maximum permeability value, Mmax(1). The radially outer magnetic core portion is formed from a second material having a first core minimum permeability value, Mmin(1), less than the first core maximum permeability value, Mmax(1). A single turn of each winding extends fully around both the first radially inner and outer core portions without passing between them. |
US09633777B2 |
High impedance air core reactor
Air core reactor includes a coil connected between first and second terminals. The coil is made of a succession of bundles of conductor (B1, B2, B3, . . . , BN) connected in series along an axis between the first terminal and the second terminal. Each bundle is made of one wire wound around the axis to form a multi-layer winding having a cross-section of N winding layers in a direction perpendicular to the axis, from a winding layer of rank 1 which is the closest to the axis to a winding layer of rank N which is the furthest from the axis. Each perpendicular winding layer includes several winding layers in the direction of the axis. The number of axial winding of the perpendicular winding layer of rank j (j=2, . . . , N) is equal or less than the number of axial winding layers of the perpendicular winding layer of rank j−1. |
US09633776B2 |
Variable core electromagnetic device
An electromagnetic device includes a variable magnetic flux core having a plurality of core sections stacked on one another. At least one core section of the plurality of core sections may include a different selected geometry and/or a different chosen material. The at least one core section is configured to provide a predetermined inductance performance. An opening is provided through the stacked plurality of core sections for receiving a conductor winding. An electrical current flowing through the conductor winding generates a magnetic field about the conductor winding and a magnetic flux flow in each of the plurality of core sections. The magnetic flux flow in the at least one core section is different from the other core sections in response to the different selected geometry and/or the different chosen material of the at least one core section to provide the predetermined inductance performance. |
US09633774B2 |
Method for making magnetics assembly including transformer
A method for making a magnetic assembly comprises the following steps: twisting a first to eighth magnetic wires to form a bundle of wires having a first end and an opposite second end; providing a magnetic core; winding the bundle of magnetic wires around the magnetic core; sorting the first end and the second end of the bundle of wires to form individual first ends and individual second ends of the first to eighth wires; picking out the second ends of the first wire and the second wire, and the first ends of the third wire and the fourth wire to form a center tap of a primary coil of a transformer; and picking out the second ends of the fifth wire and the sixth wire, and the first ends of the seventh wire and the eighth wire to form a center tap of a secondary coil of the transformer. |
US09633768B2 |
Chip resistor and mounting structure thereof
A chip resistor with a reduced thickness is provided. The chip resistor includes an insulating substrate, a resistor embedded in the substrate, a first electrode electrically connected to the resistor, and a second electrode electrically connected to the resistor. The first electrode and the second electrode are spaced apart from each other in a lateral direction that is perpendicular to the thickness direction of the substrate. |
US09633764B2 |
Conducting line shield structure
A conductive line shield structure includes a first conductive line and a shielding member. The first conductive line includes a conductive part and an insulative part. The shielding member is a sheet including an insulative base material and a metal foil, and is wrapped so as to enclose the first conductive line therein. One side end part of the shielding member overlaps an outside surface of the insulative base material so that one side end part of the insulative base material is in contact with the outside surface of the insulative base material. |
US09633759B2 |
Waterproofing structure for insulation-coated electrical wire, and wire harness
The present invention relates to a waterproofing structure for an insulation-coated electrical wire that includes a tubular protection member and a resin material that is accommodated in the protection member. An exposed conductor section includes a plurality of bare wires bent to double back in a reverse direction in the protection member, the protection member including a tubular section that surrounds the exposed conductor section and the pair of on intermediate ends of the coating tube that are adjacent to both ends of the exposed conductor section; and a closed section that is distanced from the exposed conductor section in the axial direction and closes one end of the tubular section. The resin material is made of a thermosetting resin that is cured, between the protection member and the insulation-coated electrical wire, while closely fitting to the closed section, the exposed conductor section, and the pair of intermediate ends. |
US09633757B2 |
Wire harness and wire harness manufacturing method
A wire harness having a portion of an electrical line group configured to easily housed in a protector without requiring the task of opening an overlapping portion of the protector, and a method for manufacturing said wire harness are provided. The protector includes a shape-memory panel having a shape-memory polymer sheet and noise suppression metal coating films formed on two surfaces thereof and are electrically conductive with each other. The shape-memory polymer sheet is molded in a shape-memory state for covering a portion of the electrical line group in a scroll-like manner, and then opened into a flat plate shape. The portion of the electrical line group is placed on the flat plate-shaped shape-memory panel, and then heated so that the shape-memory panel returns to the shape-memory state and covers the portion of the electrical line group in a scroll-like manner. |
US09633756B2 |
Device for connecting a circuit breaker
An arrangement for connecting a circuit breaker in a circuit, for example, in a switchgear, having conductors designed in the form of busbars and supported against each other for receiving forces resulting from normal operating behavior and from short circuit situations. The conductors are disposed in at least two-part claddings each completely peripherally enclosing the respective conductor and serving as electrical insulation. |
US09633751B2 |
Liquid lithium first walls for electromagnetic control of plasmas in fusion power reactor environments
A method, system, and apparatus are disclosed for liquid lithium first walls for electromagnetic control of plasmas in fusion power reactor environments. In particular, the method involves installing at least one layer of at least one tile on the surface area of the internal walls of the reactor chamber. A portion of the tile(s) facing the interior of the reactor chamber includes a plurality of channels. The method further involves applying an electric charge to the liquid lithium. Further, the method involves circulating the liquid lithium throughout the interior network of the tile(s) to allow for the liquid lithium to flow into the channels and to reach the external surface of the tile(s) that faces the interior of the reactor chamber. In some embodiments, the method also involves installing at least one magnetic coil between the tile(s) and the surface area of the internal walls of the reactor chamber. |
US09633749B2 |
System and method of managing tags associated with read voltages
A data storage device includes a controller coupled to a non-volatile memory. The non-volatile memory is configured to store multiple tags that include a first tag and a second tag. The controller is configured to determine one or more candidate values associated with a candidate tag. The one or more candidate values may be determined based on an operation applied to the first tag and the second tag. The controller is further be configured to cause the non-volatile memory to remove the first tag or the second tag from the multiple tags. |
US09633746B2 |
Semiconductor device, semiconductor system including the same and test method thereof
A semiconductor device includes a memory region suitable for providing a plurality of read data in parallel at every read operation cycle, an output path suitable for outputting the plurality of read data at a set time in response to an internal clock and one or more internal control signals at the every read operation cycle, and an output path control unit suitable for generating the internal control signal in response to a read command and generating the internal clock in response to a system clock, wherein a shifting time of a first edge of the internal clock is adjusted by a set level at the every read operation cycle during a test mode. |
US09633742B2 |
Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices
In non-volatile memory circuits, the amount of time needed for bit lines to settle can vary significantly depending on the location of the blocks selected. For example, in a sensing operation, the amount of time for bit lines to settle when being pre-charged by sense amplifiers will be shorter for blocks near the sense amps than for far side blocks. These variations can be particularly acute in high density memory structures, such as in 3D NAND memory, such as that of the BiCS variety. Rather than use the same timing for all blocks, the blocks can be segmented into groups based on their proximity to the sense amps. When performing a sensing operation, the timing can be adjusted based on the block group to which a selected page of memory cells belongs. |
US09633736B2 |
Semiconductor memory device capable of reducing chip size
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines. |
US09633735B2 |
System and method to inhibit erasing of portion of sector of split gate flash memory cells
A system and method to inhibit the erasing of a portion of a sector of split gate flash memory cells while allowing the remainder of the sector to be erased is disclosed. The inhibiting is controlled by control logic that applies one or more bias voltages to the portion of the sector whose erasure is to be inhibited. |
US09633731B2 |
Semiconductor memory device including three-dimensional array structure
A semiconductor memory device may include source selection transistors coupled to a common source line, source side dummy memory cells coupled between the source selection transistors and the normal memory cells, and drain selection transistors coupled to a bit line. The semiconductor memory device may include drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells. A number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and a number of the drain selection transistors may be greater than the source selection transistors. |
US09633730B2 |
Semiconductor memory device
A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line. |
US09633729B2 |
Non-volatile memory for high rewrite cycles application
A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell. |
US09633725B2 |
Method for determining electrical parameters used to programme a resistive random access memory
A method determines electrical parameters for programming a resistive random access memory in an insulating state and in a conducting state, by formation or dissolution of a filament. |
US09633721B2 |
Storage device with 2D configuration of phase change memory integrated circuits
A storage device, apparatus, and method to write and/or read data from such storage device. The storage device, comprises a channel controller and phase change memory integrated circuits (PCM ICs) arranged in sub-channels, wherein each of the sub-channels comprises several PCM ICs connected by at least one data bus line, which at least one data bus line connects to the channel controller. The channel controller is configured to write data to and/or read data from the PCM ICs according to a matrix configuration of PCM ICs, wherein: a number of columns of the matrix configuration respectively corresponds to a number of the sub-channels, the sub-channels forming a channel, and a number of rows of the matrix configuration respectively corresponds to a number of sub-banks, the sub-banks forming a bank, wherein each of the sub-banks comprises PCM ICs that belong, each, to distinct sub-channels of the sub-channels. |
US09633719B2 |
Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
Embodiments of methods and memory devices for performing the methods are disclosed. In an embodiment, one such method includes programming all memory cells that are to be respectively programmed to different levels other than a lowest level, corresponding to a lowest data state, to an intermediate level from the lowest level and respectively programming all the memory cells that are to be respectively programmed to the different levels other than the lowest level to the different levels other than the lowest level from the intermediate level. |
US09633718B1 |
Nonvolatile memory device
There is provided a nonvolatile memory device having a writing error preventing function with high noise resistance. This structure includes a switch and a noise filter circuit connected in parallel to a clock terminal, wherein a clock pulse monitoring circuit compares the number of clocks input from the clock terminal with a prescribed number, and when detecting abnormality in the number of clocks, switches to a noise countermeasure mode in which the switch is turned off to validate the noise filter circuit. |
US09633717B2 |
Tracking cell and method
A circuit includes a first power node that receives a first operational voltage having a first operational voltage level and a second power node that receives a second operational voltage having a second operational voltage level different from the first operational voltage level. A memory cell is coupled with the first power node, the memory cell configured to store a logic value, and a tracking cell is coupled with the second power node, the tracking cell configured to generate a signal having a timing responsive to the second operational voltage level. The circuit is configured to read the logic value of the memory cell based on the signal. |
US09633711B2 |
Method of managing data of storage devices responsive to temperature
Methods of managing data of a storage device responsive to temperature can include measuring a temperature of the storage device, changing a duration of a refresh interval of the buffer memory responsive to the measured temperatures, changing a number of refresh bursts during the refresh interval responsive to the measured temperature, and refreshing data of the buffer memory based on the refresh interval and the number of the refresh bursts that are changed responsive to temperature. |
US09633709B2 |
Storage device including transistor comprising oxide semiconductor
A highly reliable storage device with small data deterioration is provided. The storage device includes a first circuit, a second circuit, a third circuit, and a memory cell. The first circuit has a function of detecting power-on. The second circuit has a function of specifying the address of the memory cell. The third circuit has a function of refreshing the memory cell at the address specified by the second circuit after the first circuit detects power-on. The memory cell preferably includes an oxide semiconductor transistor. |
US09633708B2 |
Semiconductor storage device using STT-MRAM
A memory circuit (100) includes a plurality of memory cells (50), an N-type MOSFET (30a) and an N-type MOSFET (30b). The drain of the N-type MOSFET (30a) is connected to one of a pair of bit lines, and the drain of the N-type MOSFET (30b) is connected to the other of the pair of bit lines. The gate of the N-type MOSFET (30a) is connected to the drain of the N-type MOSFET (30b), and the gate of the N-type MOSFET (30b) is connected to the drain of the N-type MOSFET (30a). |
US09633701B2 |
Resistor switching circuit, storage circuit, and consumable chip
A resistor switching circuit, a storage circuit and a consumable chip. The resistor switching circuit is used in the consumable chip, and includes a plurality of resistor switching branch circuits, the resistor switching branch circuit including a switching switch and a resistor, the switching switch and the resistor being connected in series in a conducting loop of a signal wire; and a decoder, connected to a data storage module in the consumable chip, and used for generating a switching instruction according to a signal output by the data storage module to control a switching switch of a corresponding resistor switching branch circuit to put a corresponding resistor into the conducting loop of the signal wire, so as to change a resistance value of the conducting loop of the signal wire. |
US09633697B2 |
Zoom indication for stabilizing unstable video clips
A computer-implemented method for zoom indication for stabilizing unstable video clips is described. To indicate zoom, a zoom value associated with an unstable segment of a video clip is received. The zoom value represents a value by which frames of the video clip in the unstable segment need to be zoomed to stabilize the unstable segment. An indicia is displayed representing the zoom value in a thumbnail in a user interface. The thumbnail represents the video clip. The indicia displayed over a region in the thumbnail corresponding to the unstable segment in the video clip. |
US09633694B2 |
Full fidelity remote video editing
Video editing methods and systems enable an editor to edit a video project for which source media assets are located at a media storage server located remotely from the editor with substantially the same fidelity and editing feature set that would be available if the source media assets and editor were co-located. A video editing client used by the editor maintains a persistent cache of proxy media with the layers of the video project stored independently, facilitating editing with combinations locally originated assets and remote assets. The client requests frames not already cached from the remote server via a low bandwidth network. Unless a frame is purged from the cache, no frame is requested from the server more than once. A multi-level priority prefetching scheme, including sequence-based prefetching, populates the cache with frames likely to be requested during editing. |
US09633693B2 |
Interface for media publishing
Methods and apparatus for implementing an interface for media publishing. In one implementation, a method of publishing media data includes: accessing a media interface of a media device; capturing media data using a media capture component of said media device; storing said captured media data in a media file in storage of said media device; modifying said captured media data; and publishing said modified media data to a network server; wherein said capturing, modifying, and publishing are performed using said media interface. |
US09633691B2 |
Storage controller, storage device, and method
A storage controller includes a control unit and an interface. The control unit, when write data input as data to be written onto a magnetic disk includes a bit string of a first pattern, inverts one or more bits of the bit string. The write data includes a redundancy bit string used for data error correction. The interface outputs write data including bit inverted by the control unit. |
US09633689B1 |
Continuously zoned servo preamble detection and frequency acquisition
An apparatus for storing data includes a storage medium with user data regions and with servo data regions containing preamble patterns. Servo data in the servo data regions is written with a varying clock frequency across the storage medium. The apparatus also includes a head assembly disposed in relation to the storage medium and operable to read and write data on the storage medium. The apparatus also includes a preamble detection circuit adapted to search an input stream derived from the head assembly for the preamble patterns in a number of frequency bins. |
US09633687B2 |
Symbol timing recovery scheme for parallel recording channel systems
An apparatus includes a loop filter that receives a plurality of input signals. Each of the input signals is based on a different timing error detector output signal. The apparatus also includes a plurality of read channels, a plurality of interpolation filters, and an array of transducers. Each of the interpolation filters is in communication with a corresponding one of the read channels. Each of the transducers is in communication with a corresponding one of the read channels. The loop filter processes the plurality of input signals, and outputs a different total phase signal for each received input signal. Each of the interpolation filters samples the corresponding read channel based on one of the total phase signals output by the loop filter. The loop filter processes the plurality of input signals by calculating a phase estimate of the samples, and a skew estimate of the samples, relative to written data. |
US09633680B2 |
Head suspension having a flexure tail with a covered conductive layer and structural layer bond pads
A head gimbal assembly has a laminate flexure that includes a metallic conductive layer that includes a plurality of electrically conductive traces that are elongated and narrow and electrically connected to the read head, and a metallic structural layer that is stiffer than the conductive layer. A first dielectric layer is disposed between the structural layer and the conductive layer. A second dielectric layer substantially covers the conductive layer in a flexure tail bonding region that overlaps a flexible printed circuit (FPC). The structural layer includes a plurality of flexure bond pads that are aligned with, facing, and bonded to corresponding FPC bond pads. The flexure bond pads in the structural layer are electrically connected to the electrically conductive traces in the conductive layer by vias through the first dielectric layer. In certain embodiments, the flexure tail is folded upon itself in the flexure tail bonding region. |
US09633679B2 |
Sensor stack structure with RKKY coupling layer between free layer and capping layer
A reader stack, such as for a magnetic storage device, the stack having a top synthetic antiferromagnetic (SAF) layer, a magnetic capping layer adjacent to the top SAF layer, an RKKY coupling layer adjacent to the magnetic capping layer opposite the top SAF layer, and a free layer adjacent to the RKKY coupling layer opposite the magnetic capping layer. Also included is a method for biasing a free layer in a reader stack by providing an exchange coupling between the free layer and a top synthetic antiferromagnetic (SAF) layer using a layer having RKKY coupling property positioned between the free layer and the top SAF layer and a magnetic capping layer between the SAF layer and the layer having RKKY coupling property. |
US09633678B2 |
Data reader with spin filter
A data reader may be configured with at least a detector stack positioned on an air bearing surface and consisting of a spin accumulation channel continuously extending from the air bearing surface to an injector stack. The injector stack can have at least one cladding layer contacting the spin accumulation channel. The at least one cladding layer may have a length as measured perpendicular to the ABS that filters minority spins from the detector stack. |
US09633676B2 |
Magnetic storage medium comprised of magnetic nanoparticles contained within nanotubes
A magnetic storage medium is formed of magnetic nanoparticles that are encapsulated within nanotubes (e.g., carbon nanotubes). |
US09633673B2 |
Accurate forward SNR estimation based on MMSE speech probability presence
Acoustic noise in an audio signal is reduced by calculating a speech probability presence (SPP) factor using minimum mean square error (MMSE). The SPP factor, which has a value typically ranging between zero and one, is modified or warped responsive to a value obtained from the evaluation of a sigmoid function, the shape of which is determined by a signal-to-noise ratio (SNR), which is obtained by an evaluation of the signal energy and noise energy output from a microphone over time. The shape and aggressiveness of the sigmoid function is determined using an extrinsically-determined SNR, not determined by the MMSE determination. The extrinsically-determined SNR is obtained from a long term history of previously-determined speech presence probabilities and a long term history of previously-determined noise histories. |
US09633671B2 |
Voice quality enhancement techniques, speech recognition techniques, and related systems
An echo canceller can be arranged to receive an input signal and to receive a reference signal. The echo canceller can subtract a linear component of the reference signal from the input signal. A noise suppressor can suppress non-linear effects of the reference signal in the input signal in correspondence with a large number of selectable parameters. Such suppression can be provided on a frequency-by-frequency basis, with a unique set of tunable parameters selected for each frequency. A degree of suppression provided by the noise suppressor can correspond to an estimate of residual echo remaining after the one or more linear components of the reference signal have been subtracted from the input signal, to an estimated double-talk probability, and to an estimated signal-to-noise ratio of near-end speech in the input signal for each respective frequency. A speech recognizer can receive a processed input signal from the noise suppressor. |
US09633665B2 |
Process and associated system for separating a specified component and an audio background component from an audio mixture signal
Processes are described herein for transforming an audio mixture signal data structure into a specified component data structure and a background component data structure. In the processes described herein, pitch differences between a guide signal and a dialogue component of an audio mixture signal are accounted for by explicit modeling. Processes described herein can involve obtaining an audio guide signal data structure that corresponds to a dubbing of the specified component, determining parametric spectrogram model data structures for spectrograms of the specified component and the background component, estimating parameters of the parametric spectrogram model data structures to produce data structures representing, a temporary specified signal and a temporary background signal, and filtering the audio mixture signal data structure using the data structures representing the temporary specified signal and the temporary background signal in order to produce data structures representing a specified audio signal and an audio background signal. |
US09633664B2 |
Audio encoder, audio decoder, method for encoding and audio information, method for decoding an audio information and computer program using a modification of a number representation of a numeric previous context value
An audio decoder includes an arithmetic decoder for providing decoded spectral values on the basis of an arithmetically-encoded representation of the spectral values and a frequency-domain-to-time-domain converter for providing a time-domain audio representation using the decoded spectral values. The arithmetic decoder selects a mapping rule describing a mapping of a code value onto a symbol code in dependence on a context state described by a numeric current context value, and determines the numeric current context value in dependence on a plurality of previously-decoded spectral values. The arithmetic decoder modifies a number representation of a numeric previous context value, describing a context state associated with one or more previously decoded spectral values, in dependence on a context subregion value, to acquire a number representation of a numeric current context value describing a context state associated with one or more spectral values to be decoded. An audio encoder uses a similar concept. |
US09633663B2 |
Apparatus, method and computer program for avoiding clipping artefacts
An audio encoding apparatus includes an encoder for encoding a time segment of an input audio signal to be encoded to obtain a corresponding encoded signal segment. The audio encoding apparatus further includes a decoder for decoding the encoded signal segment to obtain a re-decoded signal segment. A clipping detector is provided for analyzing the re-decoded signal segment with respect to at least one of an actual signal clipping or an perceptible signal clipping and for generating a corresponding clipping alert. The encoder is further configured to again encode the time segment of the audio signal with at least one modified encoding parameter resulting in a reduced clipping probability in response to the clipping alert. |
US09633661B1 |
Speech-responsive portable speaker
A portable music device may operate in response to user speech. In situations in which the music device is operating primarily from battery power, a push-to-talk (PTT) button may be used to indicate when the user is directing speech to the device. When the music device is receiving external power, the music device may continuously monitor a microphone signal to detect a user utterance of a wakeword, which may be used to indicate that subsequent speech is directed to the device. When operating from battery power, the device may send audio to a network-based support service for speech recognition and natural language understanding. When operating from external power, the speech recognition and/or natural language understanding may be performed by the music device itself. |
US09633660B2 |
User profiling for voice input processing
The present disclosure generally relates to systems and methods for processing received voice inputs for user identification. In an example process, voice input can be processed using a subset of words from a library used to identify the words or phrases of the voice input. The subset can be selected such that voice inputs provided by the user are more likely to include words from the subset. The subset of the library can be selected using any suitable approach, including for example based on the user's interests and words that relate to those interests. For example, the subset can include one or more words related to media items stored by the user on the electronic device, names of the user's contacts, applications or processes used by the user, or any other words relating to the user's interactions with the device. |
US09633658B2 |
Computer-implemented system and method for transcription error reduction during a live call
A computer-implemented system and method for transcription error reduction during a live call is provided. Speech utterances are transcribed during a live call. A confidence score is assigned to each transcribed speech utterance. One of the transcribed speech utterances with a low confidence score is identified. An attempt is made to identify a pool of related transcribed speech utterances by monitoring other live calls for a predetermined amount of time. Similar transcribed speech utterances with low confidence scores are identified and a group of the similar transcribed speech utterances and the identified transcribed speech utterance is formed. A determination is made as to whether the group includes a predetermined number of transcribed speech utterances upon termination of the predetermined time. If so, a sample of the transcribed speech utterances in the pool is processed to verify a validity of the transcribed speech utterances. |
US09633657B2 |
Systems and methods for supporting hearing impaired users
A method for providing speech recognition to a user on a mobile device are provided, the method comprising: 1) receiving, by a processor, audio data; 2) processing the audio data, by a speech recognition engine, to determine one or more corresponding text, wherein the processing comprises querying a local language model and a local acoustic model; and 3) displaying the one or more corresponding text on a screen of the mobile device. |
US09633655B1 |
Voice sensing and keyword analysis
Methods for voice sensing and keyword analysis are provided. An example method allows for causing a mobile device to transition to a second power mode, from a first power mode, in response to a first acoustic signal. The method includes authenticating a user based at least in part on a second acoustic signal. While authenticating the user, the second acoustic signal is compared to a spoken keyword. The spoken keyword is analyzed for authentication strength based on the length of the spoken keyword, quality of a series of phonemes used to represent the spoken keyword, and likelihood of the series of phonemes to be detected by a voice sensing. While receiving the first and second acoustic signals, a signal to noise ratio (SNR) is determined. The SNR is used to adjust sensitivity of a detection threshold of a voice sensing. |
US09633652B2 |
Methods, systems, and circuits for speaker dependent voice recognition with a single lexicon
Embodiments reduce the complexity of speaker dependent speech recognition systems and methods by representing the code phrase (i.e., the word or words to be recognized) using a single Gaussian Mixture Model (GMM) which is adapted from a Universal Background Model (UBM). Only the parameters of the GMM need to be stored. Further reduction in computation is achieved by only checking the GMM component that is relevant to the keyword template. In this scheme, keyword template is represented by a sequence of the index of best performing component of the GMM of the keyword model. Only one template is saved by combining the registration template using Longest Common Sequence algorithm. The quality of the word model is continuously updated by performing expectation maximization iteration using the test word which is accepted as keyword model. |
US09633651B2 |
Apparatus and method for providing an informed multichannel speech presence probability estimation
An apparatus for providing a speech probability estimation is provided. The apparatus includes a first speech probability estimator for estimating speech probability information indicating a first probability on whether a sound field of a scene includes speech or on whether the sound field of the scene does not include speech. Moreover, the apparatus includes an output interface for outputting the speech probability estimation depending on the speech probability information. The first speech probability estimator is configured to estimate the first speech probability information based on at least spatial information about the sound field or spatial information on the scene. |
US09633649B2 |
System and method for creating voice profiles for specific demographics
Systems, methods, and computer-readable storage devices for receiving an utterance from a user and analyzing the utterance to identify the demographics of the user. The system then analyzes the utterance to determine the prosody of the utterance, and retrieves from the Internet data associated with the determined demographics. Using the retrieved data, the system retrieves, also from the Internet, recorded speech matching the identified prosody. The recorded speech, which is based on the demographic data of the utterance and has a prosody matching the utterance, is then saved to a database for future use in generating speech specific to the user. |
US09633645B2 |
Adaptive noise control system with improved robustness
A method for determining an estimation of a secondary path transfer characteristic in an ANC system is described herein. In accordance with one example of the invention, the method includes the positioning of a microphone array in a listening room symmetrically with respect to a desired listening position and reproducing at least one test signal using a loudspeaker arranged within the listening room to generate an acoustic signal. The acoustic signal is measured with the microphones of the microphone array to obtain a microphone signal from each microphone of the microphone array, and a numerical representation of the secondary path transfer characteristic is calculated for each microphone signal based on the test signal and the respective microphone signal. The method further includes averaging the calculated numerical representations of the secondary path transfer characteristic to obtain the estimation of the secondary path transfer characteristic to be used in the ANC system. |
US09633639B2 |
Guitar effector module, and multi-type guitar effector using same
A guitar effector module includes: a component circuit board in which an analog guitar effector circuit is formed; a module case in which a knob for adjusting a sound by a circuit is mounted, and the component circuit board is installed therein; and a circuit connection unit, in which a circuit input unit, a circuit output unit, and a circuit power supply unit with respect to the circuit are formed, which is electrically connected with the component circuit board, and is installed on an external side of the module case. |
US09633635B2 |
Musical instrument stand clamp
A musical instrument stand clamp, which to be fixed to a stand, comprises a fixed part, a movable part, and a screwing-lock part. The movable part is pivotally coupled to a pivotal point of the fixed part. The fixed part includes a locked section and a clamping section respectively at two sides of the pivotal point. The movable part includes an outer curved surface near the locked section and a movable member far away from the locked section. The screwing-lock part is screwed through the locked section to push the outer curved surface of the movable part and rotate the movable part with respect to the fixed part so as to move the movable member toward a clamping member of the locked section, whereby the clamp is fixed to the stand. Thus, the clamp can be fast assembled or disassembled merely via rotating the screwing-lock part. |
US09633634B2 |
Magnetic throw-off floating attachment
A snare drum attachment is disclosed. A mounted body is mounted to the snare drum and houses a first magnet. A moveable body is coupled to the mounted body. The moveable body is configured to retain tensioned snares a set distance from a snare head of the snare drum. The moveable body houses a second magnet magnetically coupled to the first magnet so as to generate a magnetic force. A manual actuator is coupled to the first magnet. Actuation of the manual actuator alters the magnetic force so as to displace the moveable body relative to the mounted body. The displacement changes the set distance of the tensioned snares from the snare head. |
US09633633B1 |
Drum beater foot pedal
Disclosed herein is an adjustable foot pedal for a percussion drum. In one example, the foot pedal utilizes a transversely split footboard having a heel end pivotably coupled to a heel plate and a toe end coupled to a step force transfer member. In one example the heel end is longitudinally adjustable relative to the toe end. A connecting rod may be utilized having an intermediate point coupled to the eccentric cam plate at a position offset from the axis of rotation of the rotational shaft so as to pivot and linearly slide relative thereto; a first end of the connecting rod fixed to the frame body; and wherein the connecting rod couples to the eccentric cam plate between the attachment to the frame body and at least one compression member. A pivot arm may be used pivotably coupled to the connecting member and pivotably coupled to the footboard. |
US09633629B2 |
Piano or grand piano with strings and a sound bridge with reduced mass and improved tonal quality
The present invention relates to a piano or a grand piano with a resonance board and strings which rest on a sound bridge with two longitudinal faces. Such a sound bridge serves to transmit vibration energy which is output by the strings of the instrument to a resonance board. The invention is based on the realization that, on the one hand, the rigidity of the sound bridge must be maintained at the locations at which it is in contact with the strings and the resonance board. On the other hand, it is advantageous if the mass of the sound bridge is reduced. For this reason, according to the invention it is proposed that the sound bridge have a first cutout and a second cutout, wherein the two cutouts are arranged on the two longitudinal edges of the sound bridge which lie opposite one another. |
US09633626B2 |
Adjusting an electronic display based on gaze tracking
A system for adjusting an electronic display is provided herein. The system includes a gaze tracking device to capture an image of a pupil associated with a viewer of the electronic display, and a diameter of the pupil being ascertained via the image of the pupil. In another example, the system may also include an ambient light sensor receiver to logarithmically receive light information from an ambient light sensor; and a display adjuster to adjust a luminance of the electronic display based on a combination of a diameter and the light information. |
US09633625B2 |
Pixel circuit and method for driving the same
A pixel circuit includes a plurality of pixels. Each pixel includes a data storage capacitor to store a voltage for controlling a gray scale value based on an input data signal, a plurality of switch transistors connected in series between a data signal line and the data storage capacitor, and a plurality of connection transistors coupled to the pixels. The switch transistors have a gate electrode connected to a first gate control signal line. At least one connection transistor is connected between at least one node between the switch transistors of a first pixel and at least one node between the switch transistors of a second pixel adjacent to the first pixel. The at least one connection transistor includes a gate electrode connected to a second gate control signal line. |
US09633618B2 |
Device and method of modifying image signal
An image signal modifying method is disclosed. In one aspect, the image signal modifying method includes inputting a gray level interval of a first dynamic capacitance compensation (DCC) lookup table to a current gray level which is a target in a previous image signal when it is overdriven (DTG) and 0 to a gray level of the previous image signal (PIG). The method also includes searching for a data value in an adaptive color correction (ACC) lookup table corresponding to a gray level equal to a numerical value of the DTG (ALT) and performing an algorithm based on the DTG, the ALT, and the gray level interval of the first DCC lookup table. The method further includes generating a second DCC lookup table based on the algorithm, and performing second DCC processing on the input image signal based on the second DCC lookup table. |
US09633616B2 |
Display device and electronic apparatus
According to an aspect, a display device includes: a plurality of pixels aligned in row and column directions, each of the pixels including a drive element; a plurality of scan lines each coupled with the drive elements included in the pixels aligned in the row direction to transmit thereto a scan signal for selecting the pixels row by row; a plurality of signal lines each coupled with the drive elements included in the pixels aligned in the column direction to write display data; and a display control unit. The display control unit alternately repeats a display period and a stop period. In a latter term of the stop period, display control unit provides the display data written in the respective pixels in a row that has been selected during the display period immediately before the stop period, to the signal lines corresponding to the respective pixels. |
US09633614B2 |
Display device and a method for driving a display device including four sub-pixels
According to an aspect, a display device includes an image display panel and a signal processing unit. The signal processing unit derives a generation signal for a fourth sub-pixel in each of pixels based on an input signal for a first sub-pixel, an input signal for a second sub-pixel, an input signal for a third sub-pixel, and an extension coefficient. The signal processing unit derives a correction value based on a hue of an input color corresponding to a color to be displayed based on the input signal for the first sub-pixel, the input signal for the second sub-pixel, and the input signal for the third sub-pixel. The signal processing unit derives the output signal for the fourth sub-pixel in each of the pixels based on the generation signal for the fourth sub-pixel and the correction value and outputs the output signal to the fourth sub-pixel. |
US09633612B2 |
Display control system and method, and display device
The present disclosure relates to the field of display technology, and particularly to a display control system and control method, and a display device. The display control system comprises a plurality of source drive chips, a plurality of gate drive chips, a power-on timing controller and a standby timing controller, each of the source drive chips being connected with the power-on timing controller and the standby timing controller, respectively, the power-on timing controller being connected in series with the plurality of gate drive chips, the standby timing controller being also connected in series with the plurality of gate drive chip. The display control system further comprises a backlight source drive chip, both the power-on timing controller and the standby timing controller being connected with the backlight source drive chip. A display of a background-pushed message by a display device in a standby state can be achieved in the present disclosure by employing a design of two timing controllers, the power-on timing controller and the standby timing controller. This solves the problem that existing display devices only enable a prompt of a background-pushed message in the standby state but fail to display the contents of the background-pushed message. |
US09633609B2 |
Display compensating method and display compensating system
A display compensating method for eliminating a mura of a display panel. The display compensating method includes capturing an image displayed by the display panel to generate a capturing image; generating a plurality of compensation results according to a plurality of brightness values in the capturing image corresponding to a plurality of display units of the display panel; and setting brightness of the plurality of display units according to the plurality of compensation results to eliminate the mura of the display panel. |
US09633608B2 |
Display device having a plurality of regions and method of driving the same at different of frequencies
In one aspect, the display device includes a display panel including a first region and a second region, wherein the first region is configured to display a first image having a first luminance and wherein the second region is configured to display a second image having a second luminance. The display device also includes a panel driver configured to drive the first region at a first frequency and the second region at a second frequency less than the first frequency and a luminance compensator configured to compensate for the difference between the first and second luminances. |
US09633600B2 |
Display device and electronic appliance
There is provided a display device including a light-emitting portion configured to constitute a pixel and emit light by a drive current, a writing transistor configured to write a video signal into pixel capacitance, a driving transistor configured to control the drive current of the light-emitting portion on the basis of the video signal written in the pixel capacitance, a first metal layer configured to constitute a drain and a source of each of the driving transistor and the writing transistor, and a second metal layer configured to constitute a gate of each of the driving transistor and the writing transistor. |
US09633594B2 |
Display device and electronic apparatus
A display device includes an array of display cells having a plurality of display subunits; a plurality of first type of drive lines and a plurality of second type of drive lines, each of the plurality of first type of drive lines intersecting with each of the plurality of second type of drive lines, intersection thereof corresponding to each display subunit of the plurality of display subunits, to provide a display drive signal for each display subunit; a display drive unit, connected with the drive lines, to provide a display drive signal for the plurality of first type of drive lines and the plurality of second type of drive lines; wherein at least one drive line of at least one type of drive lines of the plurality of first type of drive lines and the plurality of second type of drive lines is a curve. |
US09633593B2 |
Organic light emitting diode display panel
An organic light emitting diode display panel is disclosed which is defined into a plurality of pixel regions and includes: first through third pixel drivers arranged in each of the pixel regions and configured to each drive respective organic light emitting diode; and first through third pixel electrodes arranged in each of the pixel regions and connected to the first through third pixel drivers. The first and second pixel drivers within an odd-numbered pixel region share a first power supply line with each other. The third pixel driver within the odd-numbered pixel region shares a second power supply line with the first pixel driver within an even-numbered pixel region adjacent to the odd-numbered pixel region. The second and third pixel electrodes are arranged along a first direction parallel to a major axis of the first pixel electrode and disposed to expend along second directions perpendicular to the first direction. |
US09633587B2 |
Backlight simulation at reduced resolutions to determine spatial modulation of light for high dynamic range images
Embodiments of the invention relate generally to generating images with an enhanced range of brightness levels, and more particularly, to facilitating high dynamic range imaging by adjusting pixel data and/or using predicted values of luminance, for example, at different resolutions. In at least one embodiment, a method generates an image with an enhanced range of brightness levels. The method can include accessing a model of backlight that includes data representing values of luminance for a number of first samples. The method also can include inverting the values of luminance, as well as upsampling inverted values of luminance to determine upsampled values of luminance. Further, the method can include scaling pixel data for a number of second samples by the upsampled values of luminance to control a modulator to generate an image. |
US09633581B2 |
Recycling processes and labels and adhesives and use therein
A method for recycling materials having an affixed label is disclosed. The present invention also includes labels and adhesives that is readily removable from a material during a process for recycling the material. |
US09633580B2 |
Label for in-mold molding, in-mold molded article and method for molding same
A label for in-mold molding, which comprises a laminate film comprising a substrate layer (A) and a heat-sealable resin layer (B), wherein the substrate layer (A) comprises a thermoplastic resin in an amount of from 40 to 90% by weight and at least one of an inorganic fine powder and an organic filler in an amount of from 10 to 60% by weight, the heat-sealable resin layer (B) comprises a thermoplastic resin in an amount of from 50 to 100% by weight, the laminate film is at least uniaxially stretched, the porosity of the laminate film is from 10% to 45%, the thermal conductivity of the label is from 0.04 to 0.11 W/mK, and the bonding strength of the label stuck to an adherend formed of a propylene-based resin at 200° C. and 60 MPa is from 250 to 1500 g/15 mm. |
US09633578B2 |
Methods and systems for tracking occurrences and non-occurrences of medical-related events
Described in some aspects of the present invention are methods and systems that can be used to track occurrences and/or non-occurrences of medical-related events, for example, to record whether one or more medical-related events have occurred at a particular time or during a particular time interval. Any suitable number of events may be tracked using such methods and systems, and the types and varieties of events that can be tracked are diverse. Examples include but are not limited to vaccine or other drug administrations, physical therapies, tests, diagnoses and surgeries. In some preferred embodiments, these and/or other medical-related occurrences or events will be tracked using an article that can be worn about the body of a patient although a variety of non-wearable articles can be utilized as well. |
US09633573B1 |
Mechanical release archery training device
An archery training system provides an archer the ability to safely condition psychologically and physically without the need of a bow and arrow while maintaining the sensation of using a bow and arrow. The archery training system is easily portable or stowed, and offers a combination of variables replicating the activity of compound bow shooting, such as a counter balanced replication of a grasped bow while drawing a bowstring, the utilization of accessory bow sights for target acquisition and aiming, the adjustability to accommodate the various hand grip styles unique to each archer, and immediate visual feedback to performance or shooting technique. |
US09633572B2 |
Systems and methods for computerized interactive skill training
The present invention is directed to interactive training, and in particular, to methods and systems for computerized interactive skill training. An example embodiment provides a method and system for providing skill training using a computerized system. The computerized system receives a selection of a first training subject. A training challenge related to the first training subject is accessed from computer readable memory. The training challenge is provided to a user via a terminal, optionally in verbal form. A first score related to the correctness and/or completeness of a verbalized challenge response provided by the user is stored in memory. A second score related to how quickly the trainee provided the verbalized challenge response is stored in memory. A third challenge score related to the confidence and/or style with which the trainee verbalized the challenge response is stored in memory. |
US09633567B1 |
Ground collision avoidance system (iGCAS)
The present invention is a system and method for aircraft ground collision avoidance (iGCAS) comprising a modular array of software, including a sense own state module configured to gather data to compute trajectory, a sense terrain module including a digital terrain map (DTM) and map manger routine to store and retrieve terrain elevations, a predict collision threat module configured to generate an elevation profile corresponding to the terrain under the trajectory computed by said sense own state module, a predict avoidance trajectory module configured to simulate avoidance maneuvers ahead of the aircraft, a determine need to avoid module configured to determine which avoidance maneuver should be used, when it should be initiated, and when it should be terminated, a notify Module configured to display each maneuver's viability to the pilot by a colored GUI, a pilot controls module configured to turn the system on and off, and an avoid module configured to define how an aircraft will perform avoidance maneuvers through 3-dimensional space. |
US09633562B2 |
Automotive telemetry protocol
Method and apparatus whereby one or more vehicle nodes are configured for use in a vehicular communications network which provides for exchange of data between a plurality of vehicle nodes and a plurality of stationary nodes, where each stationary node comprises a computing unit operable to broadcast periodic announcements of services, and to receive identity messages from the vehicle node on at least one common IEEE 802.11 Medium Access Control (MAC) channel. Preferably, each stationary node is configured to provide for exchange of data with the plurality of vehicle nodes, where each vehicle node comprises at least one on-board computing unit which is operable to broadcast identity messages to and to receive service announcements from the stationary node on the at least one common IEEE 802.11 MAC channel. |
US09633560B1 |
Traffic prediction and control system for vehicle traffic flows at traffic intersections
A method and a traffic prediction and control system (TPCS) for predicting and controlling vehicle traffic flow through a traffic intersection dynamically with proximal traffic intersections are provided. The TPCS dynamically receives sensor data from sensors at a local traffic intersection, determines traffic flow parameters, and determines a traffic flow flux using the traffic flow parameters. The TPCS dynamically receives analytical parameters from sensors at proximal traffic intersections and determines a minimum safe driving distance between leading and trailing vehicles, a traffic free flow density, a synchronized traffic flow density, and a traffic jam density to predict transitions of the vehicle traffic flow across traffic flow phases through the local traffic intersection. The TPCS controls the vehicle traffic flow by dynamically adjusting duration of traffic signals of the local traffic intersection and transmitting traffic signal time adjustment instructions to the proximal traffic intersections to maintain an optimized traffic flow flux. |
US09633555B2 |
Remote device location identification
A method, system, and computer usable program product for remote device location identification are provided in the illustrative embodiments. A command to identify a remote device is received, at the remote device in a data processing environment. The command is included in a predetermined communication directed to the remote device. A determination is made whether the command is supported at the remote device. The remote device is identified by transmitting an identification of a location associated with the remote device. |
US09633553B2 |
Systems and methods for compensating for sensor drift in a hazard detection system
Systems and methods for compensating for sensor drift of a smoke sensor are described herein. Sensor drift may be caused by accumulated buildup of dust or other particulates within an enclosure of the smoke sensor. Embodiments described herein can account for sensor drift by adjusting a clear air offset value. |
US09633550B2 |
Evacuation system
A method includes receiving, at a node located in a structure, an indication of an evacuation condition. The structure includes a plurality of nodes in communication with one another. The method also includes sending, by the node, a message to one or more additional nodes. The message informs the one or more additional nodes that the node is going to determine an evacuation route in response to the indication of the evacuation condition such that the one or more additional nodes do not determine the evacuation route. The method also includes determining, by the node, the evacuation route based at least in part on the indication of the evacuation condition and at least in part on a layout of the structure. The method further includes providing, by the node, the evacuation route to the one or more additional nodes. |
US09633549B2 |
Emergency auto-notification
According to an embodiment, methods and systems can provide emergency auto-notification. Thus, in the event of an emergency, such as a predefined emergency, one or more people can be notified of a user's condition, needs, environment, and location, for example. The people to be notified can be predetermined, such as during a set up procedure. The people to be notified can be notified by text messaging, email, vice, voice mail, or any other method. The notification can be triggered by any desired criteria. For example, the notification can be triggered by the user's condition, location, or environment. |
US09633548B2 |
Leveraging a user's geo-location to arm and disarm a network enabled device
A method of controlling operation of a security device in a location by a mobile user device, comprises monitoring a region around a location of interest, via a mobile user device; providing at least one security device within the region, wherein the security device comprises at least one sensor to monitor a location. The user device recognizes that the user device has entered the region, and searches for a security device within the region. The security device is detected and at least certain security features and/or sensors are disarmed. Disarming may mean that at least certain notifications are not sent about the status of the location. When the user device recognizes that the device is leaving the region, security features and/or sensors may be armed. |
US09633545B2 |
Hygiene compliance module
A hygiene compliance module is configured to be retrofit with a compatible dispenser to enable hygiene compliance monitoring functions. The hygiene compliance module is configured to be coupled to the dispenser via a communication interface to receive power, ground, and dispenser actuation signals therefrom. In addition, the hygiene compliance module is enabled to communicate with a wireless data tag that is worn by a user of the dispenser and with a remote hygiene compliance monitoring station. |
US09633542B2 |
Electronic device and computer-based method for reminding using the electronic device
In a method for reminding using an electronic device, the method includes controlling a front camera of the electronic device to capture a facial image, determining whether a user needs to shave according to the characteristic information of a beard region of the facial image, and controlling a reminding device to remind the user to shave. |
US09633536B1 |
Motion sensor alarm and sprinkler device
An intruder alarm and deterrent system includes a plurality of motion sensors around a dwelling being in communication with an existing sprinkler system. Upon sensing an adult intruder, the sprinkler system is activated to broadcast a spray of water to douse, startle, and scare away the intruder. The intruder alarm also provides an audible alarm. |
US09633535B2 |
Method and system for advanced electronic border security
A system (10) for protecting a border (B) comprises a fiber-optic cable (12) extending from one end of a border to the other end thereof. The cable includes a bundle of optical fibers which connect to sensors placed at intervals long the border. Included within the fiber-optic cable is a high voltage conductor by which high voltage AC is introduced into, and passes through, the cable for powering the sensors. The high voltage is stepped down and rectified from AC to DC for this purpose. Various types of sensors (100-700) are arranged in pods (14) located at intervals along the length of the border. A method of border protection is also disclosed. |
US09633533B2 |
System and method for interacting with digital video recorders through networking applications
A method and apparatus are provided. The method includes the steps of providing a web or social networking account within a chat server for a digital video recorder (DVR) of a security system, the DVR receiving a chat message from a person through the chat server, and the DVR automatically executing a predetermined instruction corresponding to a content of the chat message. |
US09633531B1 |
Clamp and pivoting flag for tables
Devices, apparatus, and methods for clamping a pivoting arm/flag onto an edge of furniture, such as a table edge, countertop edge, and the like, with or without messages and advertising indicia thereon, in order to signal servers and wait staff that service is being requested. The clamp can include a one-piece clip with a substantially horizontal top leg perpendicular to a top edge of a back panel, and an upwardly angled lower leg attached to a bottom edge of the back panel. |
US09633527B2 |
Allocation of variable award in gaming devices
Embodiments of the present invention set forth systems, apparatuses and methods for allocating variable awards in gaming devices. Accordingly, a gaming device can be configured to provide a variable award that is allocated over a variety of selectable play options. Each of the selectable play options has distinguishing play characteristics that provide different game play while maintaining a substantially similar expected outcome value to the other selectable play options. |
US09633522B2 |
Gaming device having card game
Embodiments of the present invention are directed to an apparatus, system, computer readable storage media, and/or method that involve or otherwise facilitate a card game or secondary card game played on a gaming device. The card game may be structured to use similar rules to a blackjack-styled card game. The card game may be played against an opponent, such as a computer, dealer, or another player. Alternatively, the card game may include the display of one or more cards and a process to determine if a total value of the cards meets a predefined criterion. A win against an opponent or satisfaction of the predefined criterion may progress the card game to another round of play. These rounds of play may continue until an opponent wins, or until the predefined criterion is not satisfied. |
US09633506B2 |
Gaming system and method for providing a game including roaming wild symbols
In various embodiments, the present disclosure relates generally to gaming systems and methods for providing one or more games employing roaming wild symbols. |
US09633505B2 |
System and method for on-demand delivery of audio content for use with entertainment creatives
A method of creating and delivering an on-demand audio asset for inclusion in a creative is described. The method includes the steps of accessing a central processing environment, requesting at least one recording of at least a portion of an audio transmission generated from a communication device, generating at least one audio asset, adding the audio asset to a pool of related assets stored in a vault connected to the central processing environment, selecting the generated audio asset and at least one other related asset from the pool of related assets to form a creative, then requesting delivery of the creative to another communication device, and finally delivering the creative to the other communication device. The method is performed in part by a creative composition engine, which is also described. The engine includes a central processing environment having a processor, a digital recorder and a digital asset storage vault. |
US09633502B2 |
Controlled coin portal
A controlled coin inlet or portal is described that allows for improved alignment of a coin with the coin entry slot of a coin acceptor mechanism. A coin entry slot having at least an upper or lower edge is dimensioned to allow entry of a coin of a desired maximum width in a substantially on-edge orientation. The coin portal may include at least one outwardly extending coin guide slot of substantially corresponding maximum width as the coin entry slot and positioned adjacent to the upper or lower edge of the coin entry slot. |
US09633501B2 |
Cash automatic transaction device
A cash automatic transaction device capable of, upon storage of a banknote sent from a depositing/dispensing port in a banknote storage box, or upon accumulation of a banknote sent from the banknote storage box in the depositing/dispensing port, preventing the occurrence of trouble such as paper jam or poor posture. The cash automatic transaction device has a depositing/dispensing port used for depositing/dispensing of banknotes, and a banknote storage box for storage of deposited/dispensed banknotes. The depositing/dispensing port has depositing/dispensing space to store the deposited/dispensed banknotes, and accumulation space in which the banknote is accumulated upon dispensing. The width of the depositing/dispensing space is smaller than the exit and entrance width of the storage box, while the width of the accumulation space is greater than the exit and entrance width of the storage box. |
US09633500B1 |
Systems, methods and devices for managing rejected coins during coin processing
Currency processing systems, coin processing machines, computer-readable storage media, and methods of managing processed coins are presented herein. A method is presented for managing coins processed by a currency processing system. The method includes: receiving a batch of coins by the currency processing system; feeding the coins into a coin processing unit which includes one or more coin discriminating sensors; sorting the batch of coins into genuine fit target coins and reject coins; sorting the reject coins into a plurality of reject groups, each of which corresponds to a respective category of rejected coins; analyzing at least one of the reject groups to determine if any genuine target coins were mischaracterized and erroneously sorted into that reject group; and, crediting a user of the currency processing system for any genuine target coins in the reject group determined to have been mischaracterized and erroneously sorted. |
US09633499B2 |
System and method for detecting presence of one or more user identification device
A method for detecting presence of one or more security token comprises a host device transmitting a wake-up message for receipt by the security token. Based on the wake-up message and a condition of the one or more security token, the security token either awakens or returns to an inactive state. The wake-up message comprises a security code that is unique to a host device and an instruction code that is configured to selectively instruct at least one of the one or more security tokens associated with the vehicle to awaken. A system for detecting presence of a user includes a host device configured for transmitting a wake-up message to be received by a security token. The wake-up message comprises a unique security code and an instruction code that is configured to instruct security tokens associated with the vehicle to awaken. |
US09633494B1 |
Secure destruction of storage devices
Techniques are provided for securely destroying storage devices stored in a data storage center. A server room may be situated in the data storage center that is configured to store a plurality of server racks for storing storage devices that are associated with a radio frequency identifier tag. The data storage center may include a secure area that includes destruction devices for destroying a storage. The data storage center may include a computer system for transmitting instructions to a user device for identifying the storage device for removal and transfer to the secure area, tracking a location of the storage device based at least in part on an associated RFID tag, and transmitting an alarm to the data storage center based at least in part on the location of the storage device and the expiration of a time interval. |
US09633493B2 |
Secure short-distance-based communication and validation system for zone-based validation
A secure short-distance-based communication and validation system validates users in a validation area. The system may include multiple zones in the validation area and beacons in each zone. A run-time mobile device identifier and keys that may be location-specific, device-specific and time-specific are generated and utilized for secure communication between mobile devices and a zone computer in a zone. The validation area may be in a vehicle, and validation may include deducting a fare. |
US09633492B2 |
System and method for a vehicle scanner to automatically execute a test suite from a storage card
Disclosed are systems and methods for a vehicle scanner to automatically execute applications from a removable storage card. The method includes detecting a presence of one or more executable diagnostic requests in removable data storage, and responsive to the detection, transmitting one or more corresponding requests for vehicle diagnostic data to the vehicle via a vehicle interface. Responsive to the transmission, the vehicle scanner receives and processes diagnostic data from the vehicle. The vehicle scanner may store the data back to the removable storage card, or may transmit the data via a wired or wireless interface to a display device. As part of the detection process, the vehicle scanner may first authenticate the removable storage card before executing vehicle diagnostic instructions from the card. |
US09633491B2 |
Monitoring belt operation to predict belt lifespan
A system and a method for monitoring a belt to predict a lifespan for the belt are described. An indicator of belt speed and an indicator of torque from a motor for driving the belt can be determined for a first time interval. A belt service value can be determined for the first time interval based upon the indicators of belt speed and torque from the motor. The belt service value can indicate a deviation from one or more reference belt speeds and torques from the motor. An effective service interval can be determined for the operation of the belt during the first time interval, based upon the belt service value. An indicator of a remaining operational lifespan for the belt can then be determined, based upon the effective service interval. |
US09633488B2 |
Methods and apparatus for acquiring, transmitting, and storing vehicle performance information
The present invention includes the methods and the apparatus for acquiring, transmitting, and storing vehicle performance information. The methods of the present invention can be embodied in a wireless mobile computer device or non-transitory computer-readable medium. The embodiments include a processor, a memory storage device, a display screen, and a software application. The software application includes computer-readable instructions stored on the memory storage device and configured for execution by this process. These computer-readable instructions further include steps for acquiring instructions, storing instructions, displaying instructions, and transmitting instructions. |
US09633485B2 |
System and method for the access to information contained in motor vehicles
System and method for the access to information contained in motor vehicles. The system comprises: —a control unit (206) configured for: •capturing determined information of the vehicle (100) coming from some electronic component, preferable from the ECU (214); •generating a data message from said information—an optical transmitter (216) for the transmission of said data message (122) by means of visible optical communication through some light (104) of the vehicle. The information is captured by a communications terminal (102) by means of an optical receiver (106) and is sent to an analysis terminal (114) for its processing, being able to be employed for the control of access or diagnostic of the vehicle, among other applications. |
US09633483B1 |
System for filtering, segmenting and recognizing objects in unconstrained environments
Described is a system for filtering, segmenting and recognizing objects. The system receives a three-dimensional (3D) point cloud having a plurality of data points in 3D space and down-samples the 3D point cloud to generate a down-sampled 3D point cloud with reduced data points in the 3D space. A ground plane is then identified and removed, leaving above-ground data points in the down-sampled 3D point cloud. The above-ground data points are clustered to generate a plurality of 3D blobs, each of the 3D blobs having a cluster size. The 3D blobs are filtered based on cluster size to generate a set of 3D candidate blobs. Features are extracted from each 3D candidate blob. Finally, at least one of the 3D candidate blobs is classified as a pre-defined object class based on the extracted features. |
US09633480B2 |
Radiographic image analyzing device, method, and recording medium
An image obtaining unit obtains a subject image, a body thickness distribution modifying unit receives input of a virtual model having an estimated body thickness distribution and modifies the estimated body thickness distribution of the virtual model to output the modified estimated body thickness distribution, and a body thickness distribution determining unit determines the outputted estimated body thickness distribution to be used as the body thickness distribution of the subject. The body thickness distribution determining unit includes a judging unit for switching, according to a judgment condition, between a first control under which the body thickness distribution modifying process is iteratively executed until a first termination condition is satisfied and a second control under which the body thickness distribution modifying process is iteratively executed until a second termination condition that is different from the first termination condition is satisfied so that the first control or the second control is executed. |
US09633479B2 |
Time constrained augmented reality
A method of displaying virtual content on an augmented reality device (101) is disclosed. The virtual content is associated with a scene. An image of a scene captured using the augmented reality device (101) is received. A viewing time of the scene is determined, according to a relative motion between the augmented reality device and the scene. Virtual content is selected, from a predetermined range of virtual content, based on the determined viewing time. The virtual content is displayed on the augmented reality device (101) together with the image of the scene. |
US09633477B2 |
Wearable device and method of controlling therefor using location information
The present specification relates to a wearable device and a method of controlling therefor. According to one embodiment, a method of controlling a wearable device includes the steps of detecting a real object and displaying a first virtual object based on the detected real object when the real object is detected, and detecting the real object and a first interaction and displaying a second virtual object when the real object and the first interaction are detected, wherein the second virtual object is displayed based on the second virtual object information transmitted by the external device. |
US09633475B2 |
Modeling geologic surfaces using unilateral non-node constraints from neighboring surfaces in the stratigraphic sequence
Systems and methods for modeling three-dimensional (“3D”) geologic surfaces, which represent a constraining surface and a constrained surface, in a stratigraphic conforming relationship that do not intersect or overlap. |
US09633467B2 |
Stencil mapped shadowing system
Aspects comprise shadowing system as part of ray tracing. It is based on uniform grid of cells, and on local stencils in cells. The acceleration structures are abandoned along with high traversal and construction costs of these structures. The amount of intersection tests is cut down. The stencils are generated in the preprocessing stage and utilized in runtime. The relevant part of scene data, critical for shadowing of all visible intersection points in a cell, is registered in the local stencil map, as a volumetric data. The runtime use of stencils allows a complete locality at each cell, enhanced utilization of processing resources and load balancing of parallel processing. |
US09633463B2 |
User gesture driven avatar apparatus and method
Apparatuses, methods and storage medium associated with animating and rendering an avatar are disclosed herein. In embodiments, the apparatus may include a gesture tracker and an animation engine. The gesture tracker may be configured to detect and track a user gesture that corresponds to a canned facial expression, the user gesture including a duration component corresponding to a duration the canned facial expression is to be animated. Further, the gesture tracker may be configured to respond to a detection and tracking of the user gesture, and output one or more animation messages that describe the detected/tracked user gesture or identify the canned facial expression, and the duration. The animation engine may be configured to receive the one or more animation messages, and drive an avatar model, in accordance with the one or more animation messages, to animate the avatar with animation of the canned facial expressions for the duration. Other embodiments may be described and/or claimed. |
US09633462B2 |
Providing pre-edits for photos
Implementations generally relate to providing pre-edits to photos. In some implementations, a method includes detecting one or more objects in a photo. The method further includes classifying the one or more objects. The method further includes selecting one or more parameter values for one or more respective filters based on the classifying of the one or more objects. |
US09633458B2 |
Method and system for reducing a polygon bounding box
In a graphics processing pipeline, a processing unit establishes a bounding box around a polygon in order to identify sample points that are covered by the polygon. For a given sample point included within the bounding box, the processing unit constructs a set of lines that intersect at the sample point, where each line in the set of lines is parallel to at least one side of the polygon. When all vertices of the polygon reside on one side of at least one line in the set of lines, the processing unit may reduce the size of the bounding box to exclude the sample point. |
US09633457B2 |
Apparatus and method for automatically determining graph types, based on analysis of electronic document
An information processing apparatus includes a processor to generate an electronic document including a graph. The processor extracts specialized vocabulary words from a title of the electronic document. These specialized vocabulary words are respectively associated with vectors having a plurality of elements, each element indicating a tendency to a specific purpose of documents. The processor specifies a document purpose of the electronic document, based on an average of the vectors associated with the extracted specialized vocabulary words. The processor then determines a graph type, based on the document purpose, and generates a graph of the determined graph type, based on data of the electronic document. |
US09633456B2 |
System and method for providing flavor advisement and enhancement
A method and apparatus for generating a visual representation of a flavor or texture profile based on flavor or texture preferences of a user with respect to each of a plurality of flavor or texture categories or based on flavor or texture characteristic information representing flavor or texture characteristics of a product or recipe for each of a plurality of flavor or texture categories. The flavor or texture preferences of a user and the flavor or texture characteristics of a product or recipe with respect to each of a plurality of flavor or texture categories is determined by way of a method and apparatus for determining a flavor or texture profile for a user and a method and apparatus for determining a flavor or texture profile for a food element, respectively. Also described is a method and apparatus for providing food element recommendations based on flavor or texture. |
US09633455B1 |
Dictionary-free MR parameter inference for fingerprinting reconstruction
A method of generating Magnetic Resonance (MR) parameter maps includes creating one or more parameter maps, each respective parameter map comprising initial parameter values associated with one of a plurality of MR parameters. A dynamical update process is performed over a plurality of time points. The dynamical update process performed at each respective time point includes applying a randomized pulse sequence to subject using an MR scanner to acquire a k-space dataset. This randomized pulse sequence is configured to excite a distinct range of values associated with the plurality of MR parameters. The dynamical update process further includes applying a reconstruction process to the k-space dataset to generate an image and using a tracking process to update the one or more parameter maps based on the randomized pulse sequence and the image. |
US09633453B2 |
Image processing device, image processing method, and non-transitory recording medium
A volume of an object is constructed from images obtained by imaging the object or the like and depicting the object. The calculator 102 of the image processing device 101 calculates a statistic of each of first material images depicting an object. The initializer 104 constructs a volume of the object from multiple second material images depicting the object and multiple second imaging directions associated respectively with the multiple second material images. The estimator 103 estimates the statistic associated with an observation direction from the calculated statistics. The render 105 renders an image by observing the constructed volume in the observation direction. The corrector 106 corrects the rendered image based on the statistic estimated in association with the observation direction. The constructor 107 constructs a volume of the object from at least the observation direction and corrected image. |
US09633450B2 |
Image measurement device, and recording medium
An image measurement device calculates a disparity value from image data of images having disparity, acquires three-dimensional position information at the time of capturing the image data by using the disparity value, and calculates a three-dimensional plane from a region on an image serving as a same plane as a designated measurement region. Three-dimensional positions of the measurement region are acquired from the calculated three-dimensional plane to calculate a length. Accordingly, by using captured images having disparity, it is possible to measure a length of any part even in a region that the disparity value is hard to be acquired. |
US09633448B1 |
Hue-based color naming for an image
Systems and methods are provided for associating colors or color names with a color image based on hue. A set of hue values can be extracted from color data, such as a color palette, corresponding to a color image. A representative hue can be derived from the set of hue values. Colors included in the color data that are attributable to the representative hue can be identified and one or more colors can be derived therefrom as representative of a subject depicted by the color image. Color names matching the representative colors can be identified and associated with the color image. In particular, a common color name can be determined therefrom and associated with the subject of the color image. |
US09633442B2 |
Array cameras including an array camera module augmented with a separate camera
Systems with an array camera augmented with a conventional camera in accordance with embodiments of the invention are disclosed. In some embodiments, the array camera is used to capture a first set of image data of a scene and a conventional camera is used to capture a second set of image data for the scene. An object of interest is identified in the first set of image data. A first depth measurement for the object of interest is determined and compared to a predetermined threshold. If the first depth measurement is above the threshold, a second set of image data captured using the conventional camera is obtained. The object of interest is identified in the second set of image data and a second depth measurement for the object of interest is determined using at least a portion of the first set of image data and at least a portion of the second set of image data. |
US09633436B2 |
Systems and methods for multi-dimensional object detection
Systems and methods for multi-dimensional object detection are described. Embodiments disclose receiving image frames, extracting image components in the image frame, identifying line segments in the extracted components, grouping the line segments into groups, based at least in part on one or more similarities between the slope associated with a line segment and the spatial proximity between the line segments, and merging each of the one or more identified line segments in a selected group into a single line segment. Embodiments additionally disclose detecting the position of one or more objects in the image frame by identifying objects in the image frame, producing a second version of the image frame, applying at least one image classifier to the image frame and the second version of the image frame, and identifying coordinates associated with at least one target object. Some embodiments additionally couple lane and object detection with alert generation. |
US09633435B2 |
Calibrating RGB-D sensors to medical image scanners
A computer-implemented method for automatically calibrating an RGB-D sensor and an imaging device using a transformation matrix includes using a medical image scanner to acquire a first dataset representative of an apparatus attached to a downward facing surface of a patient table, wherein corners of the apparatus are located at a plurality of corner locations. The plurality of corner locations are identified based on the first dataset and the RGB-D sensor is used to acquire a second dataset representative of a plurality of calibration markers displayed on an upward facing surface of the patient table at the corner locations. A plurality of calibration marker locations are identified based on the second dataset and the transformation matrix is generated by aligning the first dataset and the second dataset using the plurality of corner locations and the plurality of calibration marker locations. Then, a translation is added to the transformation matrix corresponding to a maximum height associated with the apparatus. |
US09633430B2 |
Method for analyzing functional MRI brain images
A method for analyzing fMRI brain data, comprising: collecting the fMRI data including spatial information and temporal information from subjects; preprocessing the fMRI data; computing independent components (ICs) and their corresponding time course for each individual subjects; constructing an initial functional connectivity pattern; constructing a classifier based on the functional connectivity pattern; and applying the classifier to functional connectivity patterns of individual subjects for statistical analysis or diagnosis. The method may be used in fMRI based studies of a brain function and brain disorder diagnosis. |
US09633425B2 |
System for detecting image abnormalities
Image capture systems including a moving platform; an image capture device having a sensor for capturing an image, the image having pixels, mounted on the moving platform; and a detection computer executing an abnormality detection algorithm for detecting an abnormality in the pixels of the image immediately after the image is captured by scanning the image utilizing predetermined parameters indicative of characteristics of the abnormality and then automatically and immediately causing a re-shoot of the image. |