最新美国发明专利第2017-04-25期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09634709B2	Removable electronic device case with supplemental antenna element A removable case may receive an electronic device. A male connector in the case may mate with a female connector in the device. A battery in the case may supply power to the device through the male connector. The electronic device may have an antenna formed from peripheral conductive housing structures and an antenna ground. The case may have a supplemental antenna that restores antenna performance when the device is received within the case. The supplemental antenna may be formed from a monopole antenna resonating element coupled to the antenna ground through the power pin. The monopole element may have a portion that runs parallel to the peripheral conductive housing structures. During operation of the antenna in the electronic device, the supplemental antenna in the case may be indirectly fed by near-field coupling between the supplemental antenna and the antenna of the electronic device.
US09634701B2	Phase noise suppression A system comprises a modulator circuit, a test signal generator circuit, and a control circuit. The modulator circuit is operable to generate a data-carrying signal based on a reference signal. The test signal generator circuit is operable to generate a test signal based on the reference signal. The control circuit is operable to determine current status of a microwave backhaul link. The control circuit is operable to configure a nominal frequency at which the test signal generator circuit generates the test signal based on the determined status of the microwave backhaul link. The control circuit is operable to determine an amount of whitespace to have on either side of the test signal based on the current status of the microwave backhaul link. The control circuit is operable to configure the modulator circuit such that the data-carrying signal has the determined amount of whitespace surrounding the nominal frequency of the test signal.
US09634698B2	Adaptive ISO-gain pre-distortion for an RF power amplifier operating in envelope tracking The output of a Radio Frequency (RF) Power Amplifier (PA) is sampled and down-converted, and the amplitude envelope of the baseband feedback signal is extracted. This is compared to the envelope of a transmission signal, and the envelope tracking modulation of the RF PA supply voltage is adaptively pre-distorted to achieve a constant ISO-Gain (and phase) in the RF PA. In particular, a nonlinear function is interpolated from a finite number gain values calculated from the feedback and transmission signals. This nonlinear function is then used to pre-distort the transmission signal envelope, resulting in a constant gain at the RF PA over a wide range of supply voltage values. Since the gains are calculated from a feedback signal, the pre-distortion may be recalculated at event triggers, such as an RF frequency change.
US09634694B2	Transmitter with a reduced complexity digital up-converter The present disclosure is directed to a system and method for performing digital up-conversion of a signal to a desired RF carrier frequency. The system and method efficiently perform digital up-conversion of the signal, in one example, by controlling a sample clock that is used by a DAC to sample and convert the up-converted signal from the digital domain to the analog domain to have a frequency that is four or eight times the desired RF carrier frequency. By controlling the sample clock of the DAC to have a frequency that is four or eight times the desired RF carrier frequency, the system and method can be implemented using currently available IC process geometries such that the implementation consumes much less area and/or power than an analog up-converter configured to have equivalent up-conversion functionality.
US09634693B2	Apparatus and method for decoding LDPC codes in a communications system An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword.
US09634690B2	Method and apparatus for arbitrary resolution video coding using compressive sampling measurements The present invention relates to method and apparatus for arbitrary resolution video coding using compressive measurements. The method includes receiving at least one measurement of a set of measurements that was generated at an encoder. The set of measurements represents encoded video data. The method further includes determining a display resolution, where the display resolution is the same or different than an original display resolution. The method further includes determining an expansion matrix based on at least a number of pixels for the determined display resolution, and reconstructing the video data using the determined expansion matrix such that the original display resolution is resized to the determined display resolution if the determined display resolution is different than the original display resolution. The expansion matrix includes a pattern of values.
US09634689B2	Method and system for arranging numeric data for compression A computer-implemented method for arranging numeric data for compression is described. The method is implemented using a computing device in communication with a memory and a measurement device. The method includes receiving, by the computing device and from the measurement device, numeric data that includes a sequence of numbers, each number including at least a first byte followed by a second byte. The method additionally includes arranging the first bytes into a first contiguous set, arranging the second bytes into a second contiguous set, and storing the first contiguous set and the second contiguous set in a file in the memory, such that the first contiguous set is contiguous with the second contiguous set.
US09634685B2	Telescopic amplifier with improved common mode settling Telescopic amplifier circuits are disclosed. In an embodiment, a telescopic amplifier includes an input stage for receiving differential input signals, an output stage for outputting differential output signals at the drains of a first output transistor and a second output transistor, a tail current transistor coupled to sources of a first input transistor and a second input transistor, a common mode feedback circuit coupled to the differential output signals and outputting a common mode output signal, and a circuit element coupled between the common mode output signal and a gate of the tail current transistor. In an embodiment the circuit element is a resistor. In another embodiment the circuit element is a source follower transistor. In additional embodiments a phase margin of the common mode feedback open loop gain of the amplifier is determined by the value of the resistor. Additional embodiments are disclosed.
US09634681B1	Analog-to-digital conversion with linearity calibration The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators.
US09634680B1	Large-error detection and correction of digital sample sequence from analog-to-digital converter A system and method for detecting and correcting large errors during ADC operation. The system includes an ADC; an AAF at the input of the ADC, having bandwidth less than information bandwidth of the ADC; and a large-error detection and correction processing unit at the output of the ADC. The large-error detection and correction circuit includes an interpolation filter to determine values of predicted digital samples corresponding to actual digital samples in a sequence of digital samples from the ADC based on information from neighboring digital samples. A signal-delay circuit in parallel with the interpolation filter delays the actual digital samples by an amount of a lag from the interpolation filter. An adder determines differences between the predicted and actual digital samples, a matched filter detects a pattern of the differences, and a large-error detection processing unit determines whether a large error occurs based on the pattern of the differences.
US09634679B1	Digital down converter with equalization A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization.
US09634678B1	Feedback control system with rising and falling edge detection and correction A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal.
US09634676B2	Circuits and methods providing clock frequency adjustment in response to supply voltage changes Methods, systems, and circuits for providing compensation for voltage variation are disclosed. A system includes: a voltage comparator configured to assert a control signal in response to detecting that one or more of power supply voltages droops below a threshold amount; a phase locked loop (PLL) configured to divide an output frequency for the PLL in response to the assertion of the control signal; a plurality of voltage sensors corresponding to the plurality of power supply voltages, the voltage sensors configured to output respective digital signals indicative of a voltage level of its corresponding power supply voltage; and a control circuit configured to control an oscillator frequency in the PLL during the open-loop mode responsive to the respective digital signals.
US09634675B2	Phase locked loop with jump-free holdover mode A phase locked loop with holdover mode has a loop filter for creating an offset frequency value for a controlled oscillator. The loop filter includes a register for storing the current offset frequency value the said controlled oscillator. A first multiplexer responsive to a holdover signal selects, depending on the quality of a reference signal, the output of the loop filter or a holdover queue to control the controlled oscillator. A second multiplexer responsive to the holdover signal selects for input to the register, depending on the quality of the reference signal, the sum of an output of the register and a value derived from the current phase difference between the output of the controlled oscillator and the reference signal or a current output value of the holdover queue.
US09634672B2	Semiconductor circuit device, oscillator, electronic apparatus, and moving object A semiconductor circuit device includes an oscillation circuit, an output circuit that receives a signal output from an oscillation circuit and outputs an oscillation signal, a temperature sensing element, a characteristic adjustment circuit that adjusts characteristics of the oscillation circuit on the basis of a signal output from the temperature sensing element, and a first connection terminal that is electrically connected to the output circuit and via which the oscillation signal is output, in which a distance between the output circuit and the first connection terminal is shorter than a distance between the temperature sensing element and the first connection terminal in a plan view.
US09634669B2	Reconfigurable system-on-chip and related methods A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.
US09634663B2	Semiconductor circuit, semiconductor device and potential supply circuit A semiconductor circuit including a level shifter circuit that, in accordance with supply of a power supply voltage, converts a potential of an input signal from a first potential to a second potential that is higher than the first potential and outputs the second potential through an output node; a potential supply circuit, to which a reset signal at a level in accordance with the power supply voltage is supplied, that supplies a predetermined potential in accordance with the level of the reset signal; and a control circuit that controls the potential of the output node of the level shifter circuit in accordance with the level of the predetermined potential supplied from the potential supply circuit.
US09634661B1	Optical switch keyboard An optical switch keyboard includes a circuit module and plural keys. The circuit module includes a circuit board, plural light emitters, plural light receivers and plural light sources. Each key corresponds to a light emitter, a light receiver and a light source. The plural light emitters and the plural light receivers are disposed under the circuit board. Consequently, the plural light emitters and the plural light receivers are not interfered by the ambient light that comes from the top side of the circuit board. In case that the light sources are disposed over the circuit board, the light beams from the light sources are transmitted upwardly through light-transmissible triggering elements of the corresponding keys and projected to the keycaps. Consequently, a visual effect is generated.
US09634659B2	Voltage controller for radio-frequency switch One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example.
US09634657B1	System and method for overcurrent protection for a field controlled switch A method includes detecting current from a first terminal of the switch to a second terminal of the switch, wherein the current exceeds a current limit for a linear region of the switch. The method includes controlling a gate voltage of the switch from a first voltage to a second voltage. The second voltage is configured to enable the switch to operate in an active region of the switch. The method further includes opening the switch when the switch is operating in the active region.
US09634655B2	Drive device having first and second switching devices with different gate widths A drive device that drives a semiconductor switching device includes a capacitor and an output selection unit that selects whether or not to supply charge of the capacitor to a conduction control terminal of the semiconductor switching device, in which the output selection unit includes a first switching device and a second switching device, the charge of the capacitor is supplied to the conduction control terminal of the semiconductor switching device by the first switching device going to a conducting state, the charge is extracted from the conduction control terminal of the semiconductor switching device by the second switching device going to the conducting state, and a gate width of the second switching device is smaller than the gate width of the first switching device.
US09634650B2	State change stabilization in a phase shifter/attenuator circuit An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits.
US09634644B2	Acoustic wave elements and antenna duplexers, and modules and electronic devices using same An acoustic wave element according to certain examples includes a piezoelectric body, an interdigital transducer (IDT) electrode disposed above the piezoelectric body, and a connection electrode disposed above the piezoelectric body and connected to the IDT electrode. A first insulation layer covers the connection electrode, and a second insulation layer covers the IDT electrode. The first insulation layer disposed above the connection electrode has a first thickness T in a direction perpendicular to an upper surface of the piezoelectric body and the second insulation layer disposed above the IDT electrode has a second thickness K in the direction perpendicular to the upper surface of the piezoelectric body. The first thickness T is less than the second thickness K.
US09634642B2	Acoustic resonator comprising vertically extended acoustic cavity A bulk acoustic wave (BAW) resonator having a vertically extended acoustic cavity is provided. The BAW resonator includes a bottom electrode disposed on a substrate over a cavity formed in the substrate; a piezoelectric layer disposed on the bottom electrode, and a top electrode disposed on the piezoelectric layer. The piezoelectric layer has a thickness of approximately λ/2, wherein λ is a wavelength corresponding to a thickness extensional resonance frequency of the BAW resonator. At least one of the bottom electrode and the top electrode comprises a composite electrode having a thickness of approximately λ/2.
US09634639B2	Tunable electronic circuit which converts balanced signals to unbalanced signals Balun with tunable bandpass filter characteristic includes first, second and third coupling elements disposed on a substrate. The first and second coupling elements are arranged on the substrate relative to the third coupling element to couple two identical but out of phase signals to form a corresponding unbalanced signal in the third coupling element. A plurality of tunable resonator elements are distributed within an area of the substrate defined on one side by the first and second coupling elements and on an opposing side by the third coupling element. The tunable resonator elements are configured to selectively produce a bandpass filter response.
US09634635B2	RF attenuator device and system A device includes a thermally conductive and electrically insulative substrate having a first major surface and a second major surface. A coupling structure is configured to reduce the RF input signal by substantially a predetermined amount of attenuation power. A tuning circuit is characterized by a tuning reactance substantially matched to a predetermined system impedance. A resistor is disposed on a majority of the first major surface and is characterized by a parasitic capacitance that is substantially negated by the tuning reactance. The resistor includes a first resistive portion and a second resistive portion; each of the first resistive portion and the second resistive portion being configured to direct approximately one-half of the attenuation power to the ground portion.
US09634633B2	Electronic component An electronic component includes a device body and first through n-th LC parallel resonators connected in series with each other. The first through n-th LC parallel resonators respectively include first through n-th inductors and first through n-th capacitors. The first through n-th inductors are disposed in the device body such that they are arranged in a first direction in this order. The first and n-th inductors are provided with a spiral shape such that they turn around respective winding axes extending along the first direction. At least one of the second through (n−1)-th inductors is provided with a helical shape such that it turns around a winding axis extending along the first direction.
US09634625B2	Radio frequency transmitter with extended power range and related radio frequency transmission method A radio frequency transmitter includes a digital power amplifier and a bias control circuit. The digital power amplifier is arranged for receiving at least a radio frequency input signal, a digital amplitude control word signal and at least one bias voltage to generate a radio frequency output signal. The bias control circuit is coupled to the digital power amplifier, and is arranged for adjusting the at least one bias voltage according to a power control signal.
US09634624B2	Method of operating digital-to-analog processing chains, corresponding device, apparatus and computer program product A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain.
US09634623B2	Class-D power amplifier The invention is provided with a first class-D amplifying unit for amplifying an inputted audio signal and supplying the amplified signal to a positive side of an audio output terminal, a second class-D amplifying unit for amplifying an inputted audio signal inverted in an inverting unit and supplying the amplified signal to a negative side of the audio output terminal, wherein, in a first mode, the first and second class-D amplifying units are activated and outputs of the first and second class-D amplifying units are kept equal to or less than a first current value, and wherein, in a second mode, the first class-D amplifying unit is activated, the second class-D amplifying unit is inactivated, the negative side of the audio output terminal is grounded, and output of the first class-D amplifying unit is kept equal to or less than a second current value larger than the first current value.
US09634621B1	Charge-pump power supply with voltage-headroom-dependent supply voltage A method may include providing a power supply voltage to a power supply input of a power amplifier by a charge pump power supply having a select input for selecting an operating mode of the charge pump power supply, such that in a first operating mode, the power supply voltage is equal to a first voltage, and such that in a second operating mode the power supply voltage is equal to a fraction of the first voltage; wherein the power amplifier has an audio input for receiving an audio input signal, and an audio output for providing the output signal, and generates the output signal based on the audio input signal. The method may also include selecting an operating mode of the charge pump power supply based on a magnitude of the power supply voltage and a magnitude of the output signal, such that the charge pump power supply operated in the operating mode having the lowest power supply voltage in which a difference between a magnitude of the power supply voltage and a magnitude of the output signal is more than the predetermined threshold voltage.
US09634613B1	Bias circuit having reduced power consumption A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor.
US09634608B2	Crystal oscillation circuit and electronic timepiece To provide a crystal oscillation circuit low in current consumption and stably short in oscillation start time. A crystal oscillation circuit is equipped with a crystal vibrator, a feedback resistor, a bias circuit, a constant voltage circuit, and an oscillation inverter configured by a constant current inverter. The oscillation inverter is configured so as to be controlled by currents based on input signals from the bias circuit and the crystal vibrator and driven by an output voltage of the constant voltage circuit.
US09634606B2	Offset building integrable photovoltaic structures and assemblies having multi-conductor return lines Provided are novel building integrable photovoltaic (BIPV) structures having multiple photovoltaic portions offset with respect to each other along their lengths. An offset direction can correspond to the length of a row of installed BIPV structures. In some embodiments, a BIPV structure may include three offset photovoltaic portions and three corresponding flap portions for extending under photovoltaic portions of adjacent structures and sealing interfaces between installed structures. The novel BIPV structures can facilitate installation, while providing the flexibility to avoid obstacles. Provided also are novel BIPV assemblies having multi-conductor return lines extending through the assemblies. A BIPV assembly having a multi-conductor return line may include a return line for the assembly itself, and one or more return lines for other assemblies.
US09634604B2	Device for controlling a multi-phase motor An electronic device is for controlling motor drive circuits for driving a multi-phase motor in a force assisted system. Each motor drive circuit selectively permitting current to flow into or out of a respective phase of the multi-phase motor connected to the motor drive circuit in response to being driven by respective control signals. A motor control circuit generates the control signals. A fault processor detects at least one fault condition causing a fault current in a first motor drive circuit. In the event of the fault condition being detected, at least one alternative control signal is generated for at least one motor drive circuit for permitting at least one compensation current to flow for reducing a faulty force due to the fault current.
US09634601B2	Energy storage device, system comprising an energy storage device, and method for actuating an energy storage device The invention relates to an energy storage device for generating an n-phase supply voltage, wherein n>1, comprising n energy supply branches connected in parallel, which are each coupled to a respective output connection of the energy storage device, wherein each of the energy supply branches has a plurality of energy storage modules connected in series. The energy supply branches each have a respective energy storage cell module, which has at least one energy storage cell, and a respective coupling device having first coupling elements, which are designed to selectively connect the energy storage cell module into the respective energy supply branch or bypass the energy storage cell module. At least one of the energy supply branches has at least one second coupling element, which is coupled between output connections of energy storage cell modules that are adjacent in the at least one energy supply branch and which is designed to connect the coupled energy storage cell modules into the respective energy supply branch in parallel with each other.
US09634593B2	System and method for permanent magnet motor control A method of operating an electric motor is disclosed. The method includes: starting the electric motor in an open loop control mode; operating an estimator that estimates operating conditions of the electric motor; and, while the electric motor is in the open loop control mode, evaluating a first parameter of the estimator. The method further includes: in response to the evaluation of the first parameter, determining whether the estimator has converged; and in response to a determination that the estimator has not converged within a predetermined period of time after starting the electric motor, signaling a first fault condition.
US09634592B2	Method of estimating rotational position of motor, and control apparatus of motor A method of estimating a rotational position of a motor having saliency includes the steps of a) superimposing, on a drive voltage to rotate a rotating portion of the motor, a measuring voltage having a predetermined frequency higher than a frequency of the drive voltage to generate a plurality of voltages, and supplying the plurality of voltages to a stationary portion of the motor; b) in parallel with step a), extracting a component of the predetermined frequency in a current flowing in the stationary portion as an extracted current; c) calculating a sum of squares of the extracted current and a phase-shifted current obtained by shifting a phase of the extracted current by π/2 to acquire a composite signal related to an amplitude of the extracted current; and d) acquiring a rotational position of the rotating portion based on the composite signal.
US09634590B2	Drive device A drive device that includes an alternating-current rotary electric machine in which currents of a plurality of phases flow; an inverter that includes switching element units for respective phases corresponding to the respective phases, and that is connected between a direct-current power supply and the alternating-current rotary electric machine and performs conversion between a direct current and an alternating current; and shunt resistors that detect currents flowing in the respective switching element units for the corresponding phases between the direct-current power supply and the switching element units for the respective phases.
US09634589B2	Drive device Both downsizing of an apparatus as a whole and reduction in a product cost are attained. The preferred embodiments relate to a drive device including an alternating-current rotary electric machine, an inverter, and a case. The inverter is fixed to the case. The case and the inverter are disposed in a driving force source room. The inverter includes shunt resistors to detect currents flowing in respective switching element units for corresponding phases.
US09634587B2	Motor control apparatus, electric power steering apparatus and vehicle using the same A motor control apparatus includes a motor current shutoff unit inserted between a multi-phase inverter circuit and a multi-phase electric motor to shut off a current for each of plural phases, the inverter circuit including an arm for each of the plural phases, a redundant arm unit including one or more arms, a connection selecting unit selecting which one of windings of the electric motor is to be connected to each of the one or more arms of the redundant arm unit, an abnormal arm detection unit detecting an abnormality in each of the plural phases of the inverter circuit, and an abnormality control unit shutting off connection between an abnormal arm and the motor when the abnormal arm detection unit detects the abnormal arm, and connecting the one or more arms of the redundant arm unit to a winding of the motor shut off.
US09634585B2	Control method for reducing torque ripple in an electrical machine A method of controlling torque ripple in an electrical machine that includes a field winding for creating nominally constant field current using DC current and an armature winding for creating a rotating magnetic field using AC current, calls for superimposing a spatially varying current component on to the DC current of the field winding. Other methods are also disclosed that are suitable for electrical machines that have a winding that is excited with nominal DC current including SRMs, FSMs, and wound-field synchronous motors.
US09634583B2	Motor driven appliance and protection method thereof A motor driven appliance in one aspect of embodiments of the present disclosure comprises a motor, a first switching element, a second switching element, an operation unit, a control unit, and a monitoring unit. The first and second switching elements are provided on a current path from a power source to the motor, and are connected in series to each other. The monitoring unit monitors an operating state of a protection function by the control unit, and, when the protection function is activated, outputs an OFF signal for turning off the second switching element.
US09634580B2	Power converter controller A difference command generator generates a difference command equivalent to a time integral of three-phase voltage applied to an inductive load in a predetermined cycle in a complex plane. A vector command generator generates vector commands that are respectively time integrals of voltage vectors and compose the difference command. A switching signal generator generates switching signals for controlling three pairs of switches in an inverter on the basis of the vector commands. A phase-current computing unit obtains an estimated value for the three-phase current on the basis of a current flowing DC buses and the vector commands. At least two of the vector commands that are time integrals of different ones of the non-zero voltage vectors have magnitudes greater than or equal to a predetermined value corresponding to a minimum required amount of time to maintain switching patterns in order for the phase-current computing unit to detect the current.
US09634575B2	Control method and control device for inverter system The present application discloses a control method and a control device for parallel inverters. The method comprises: receiving a feedback signal Vmg reflecting load voltage and a voltage reference signal Vref to generate a command signal Pset reflecting active power and a command signal Qset reflecting reactive power; taking the command signal Pset reflecting active power as the first offset of an active power-output voltage frequency curve (P-F) of an inverter unit, and taking the command signal Qset reflecting reactive power as the second offset of an reactive power-output voltage amplitude curve (Q-V) of the inverter unit; transversely translating the curve (P-F) of the inverter unit according to the first offset, transversely translating the curve (Q-V) of the inverter unit according to the second offset, and adjusting the load voltage of the inverter system by means of adjusted output voltage frequency and output voltage amplitude of the inverter unit.
US09634572B2	Switching mode power supply and the controller and the method thereof A switching mode power supply with resonant technology. The switching mode power supply current uses current polarity evaluation to avoid capacitive mode by triggering the capacitive protection if the evaluation indicates that the system will enter capacitive mode.
US09634569B1	DC-to-DC output current sensing Method and circuits enable measuring output current in DC/DC converters operating in pulse frequency modulation (PFM) mode and in pulse width modulation (PWM) mode. The method is applicable to DC/DC converters using an inductor at the output. Current is sampled on one pass transistor only. The DC/DC converter disclosed turns a PMOS transistor off when the output current reaches its current limit.
US09634564B2	Control circuit and control method of digital control power supply circuit, and digital control power supply circuit, electronic device and base station using the same A control circuit of a digital control power supply circuit includes: an A/D converter that samples a feedback voltage according to an output voltage of the power supply circuit when a strobe signal is asserted, and converts the sampled feedback voltage into digital feedback data; an error detector that generates error data which indicates a difference between the feedback data and target data; a compensator that generates a duty command value which is adjusted to approximate the error data to zero; a digital pulse width modulator that receives the duty command value and generates a pulse signal having a duty ratio corresponding to the duty command value; and a strobe signal generator that generates the strobe signal and adjusts a sampling timing at which the strobe signal is asserted such that the sampling timing approximates a target position set in a substantial center of a slope of the output voltage.
US09634562B1	Voltage doubling circuit and charge pump applications for the voltage doubling circuit A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated.
US09634561B1	Programmable charge pump A charge pump includes a charge pump core circuit, a replica bias circuit, and a differential amplifier. The charge pump core circuit includes current source and sink circuits for charging and discharging an output node of the charge pump core circuit. The current source and current sink circuits are user programmable using bit signals to adjust a bandwidth and a phase margin of a phase-locked loop (PLL) that includes the charge pump. An impedance of the replica bias circuit varies based on the bit signals. The differential amplifier and the replica bias circuit form a feedback loop that reduces current mismatch between the current source and sink circuits.
US09634559B2	Charge pumping apparatus for low voltage and high efficiency operation A charge pump (CP) that operates at low input voltage with high power conversion efficiency is disclosed. A first embodiment provides a negative CP used for controlling load switches of a voltage doubler. Using a negative CP extends the operating region below ground to relieve the power delivery limitation of the CP. A second embodiment provides a low power adaptive dead-time circuit, which has several dead-time signals having different lengths of dead-times and selects one according to the input voltage level. A low input voltage detector in the adaptive dead-time circuit is used to determine which dead-time should be used. A third embodiment provides a switching body bias used for the low input voltage CP. The switching body bias uses both forward and reverse body bias applied to the CP to minimize reverse current and maximize power transfer. The first, second, and third embodiments can be used together or independently.
US09634555B2	Method for operating a non-isolated switching converter having synchronous rectification capability suitable for power factor correction applications A power factor correction (PFC) boost circuit. The PFC boost circuit can include a first switching device, a second switching device, a first gate driver coupled to the first switching device, a second gate driver coupled to the second switching device, and a PFC controller configured to control the first and second gate drivers. The PFC controller will utilize a new technique, referred to herein as “predictive diode emulation” to control the switching devices in a desired manner and to overcome inefficiencies and other problems that might arise using traditional diode emulation. The PFC controller is configured to operate in synchronous and non-synchronous modes.
US09634554B2	Short-circuit switch having semiconductor switch and arrangement for short-circuiting a three-phase alternating voltage A short-circuit switch for use with a first electrical conductor and a second electrical conductor includes a controllable semiconductor switch that is configured to short-circuit a voltage present between the first conductor and the second conductor responsive to receipt of a trigger, and a mechanical press-pack structure. The controllable semiconductor switch is a press-pack-type thyristor having a first planar electrode and a second planar electrode on contact sides situated opposite one another. The thyristor is disposed in the mechanical press-pack structure. The mechanical press-pack structure includes: a first terminal electrode that is configured to connect the first planar electrode to the first conductor, wherein the first terminal electrode is resiliently supported by a spring assembly; and a second terminal electrode that is configured to connect the second planar electrode to the second conductor. The press-pack structure forms a protective cover enveloping the thyristor.
US09634553B2	Method and control device for protection time setting in an electric drive system The invention relates to a control device (12) for actuating a pulse-controlled converter of an electric drive system, having: an open-loop/closed-loop control circuit (12a) which is configured to generate pulse-width-modulated actuation signals for switching devices of the pulse-controlled converter; a fault logic circuit (12b) which can detect fault states in the drive system and which is configured to select a switching state or a sequence of switching states for the switching devices of the pulse-controlled converter which are assigned to the corresponding fault state; and a protection circuit (12c) which is embodied in hardware and which comprises a signal delay device (15), which is configured to delay the actuation signals in order to implement a minimum protection time, and a locking device (16a, 16b) which is configured to lock two complementary switching devices of a bridge branch of the pulse-controlled converter with respect to one another.
US09634552B2	Solid-state phase splitting transformer A solid state power transformer is described for converting an input power signal at a first phase or voltage to an output signal of a second voltage or opposite phase by the use of bidirectional solid state switches switched at a high carrier frequency to produce a double-sideband, suppressed-carrier representation of the input power signal, which is then synchronously demodulated using further similar switches to produce the desired output. It is further disclosed that multiple instances of the above with relative phase-staggering of the switching frequency may be operated in parallel and activated or deactivated according to output current demand to provide maximum efficiency over a wide range of current and power levels.
US09634551B2	Direct current brushless motor A motor includes a frame, a shaft rotatably mounted onto the frame, and at least one disc mounted onto the shaft. At least one permanent magnet is mounted on the disc, and at least one electromagnet and at least one coil are mounted to the frame in rotational magnetic proximity to the permanent magnet. A battery is connectable to the electromagnet and the coil for energizing the electromagnet and for receiving electrical current from the coil for charging the battery. A relay switch controls the transmission of electrical power from the battery to the electromagnet. A sensor generates a signal to the relay switch to activate electrical power to the electromagnet upon sensing that the permanent magnet is positioned with respect to the electromagnet such that a magnetic force generated by the electromagnet would be effective for inducing movement of the permanent magnet and consequent rotation of the disc.
US09634549B2	Dual phase magnetic material component and method of forming A magnetic component having intermixed first and second regions, and a method of preparing that magnetic component are disclosed. The first region includes a magnetic phase and the second region includes a non-magnetic phase. The method includes mechanically masking pre-selected sections of a surface portion of the component by using a nitrogen stop-off material and heat-treating the component in a nitrogen-rich atmosphere at a temperature greater than about 900° C. Both the first and second regions are substantially free of carbon, or contain only limited amounts of carbon; and the second region includes greater than about 0.1 weight % of nitrogen.
US09634547B1	Motor grounding seal A shaft seal assembly is disclosed having a stator including a main body and axial and radial projections therefrom. The rotor may be radially extended to encompass the axial and radial projections from said stator. A passageway formed between the radial projection of stator and rotor results in an axial passageway having its opening facing rearwardly from the rotor and away from the source of impinging coolant and/or contaminant. A concentric circumferential receptor groove in the stator facing the housing allows insertion of a conductive insert for transmission of electrostatic charge away from the shaft through the shaft seal assembly to the housing and ground. The receptor groove is opposite the axial passageway and provides for both a substantially lower contaminant environment and improved engagement with the conductive insert.
US09634542B2	Electric device for a bicycle An electric device for a bicycle has a casing, a pedal shaft, a motor shaft, a rotor assembly, a stator assembly, a gear assembly, a chain wheel and a control unit. Because a normal of the circuit board of the control unit is parallel to the motor shaft, the circuit board can be axially adjacent to a side surface of the rotor assembly to detect the rotor assembly. Thus, one single circuit board can detect the rotor assembly as well as maintain electric connection with other components, thereby saving space and reducing the volume of the casing. As the casing has a reduced volume, interference with the rear wheel can be avoided.
US09634538B2	Terminal assembly for refrigeration compressor A terminal assembly configured to conduct current from an external power source to a hermetical motor-compressor unit. The terminal assembly includes a terminal board, at least one opening defined through the thickness of the terminal board, at least a conductive pin received in the opening, and an insulator having a convoluted contour. The insulator may be disposed over the conductive pin and spaced away from the terminal board.
US09634537B2	Motor provided with terminal block A motor which can reliably prevent varnish from ending up entering a terminal block. The motor is provided with a terminal block to which lead wires of coils are connected. The terminal block has a bottom wall, a plurality of side walls which face each other, a terminal part which is provided between adjoining side walls, and a dam wall which is arranged at a position closer to the coils than the terminal part and which is formed integrally with the bottom wall and side walls without clearance. The dam wall has a lead wire holding part for holding a lead wire.
US09634532B2	Inertial drive actuator An inertial drive actuator includes a shift unit that generates a shift in a first direction and in a second direction opposite to the first direction, a base plate that moves with the shift of the shift unit, and a mover disposed on a surface of the base plate and having a magnetic field generating unit. The mover has a first yoke that guides magnetic flux generated by the magnetic field generating unit such that the magnetic flux concentrates on a surface of the mover facing the base plate with respect to both S and N poles. Also included is a second yoke provided on a side of the base plate facing away from the mover. The frictional force acting between the mover and the base plate is controlled by controlling a magnetic field generated by the magnetic field generating unit to drive the mover.
US09634530B2	Interior permanent magnet motor with shifted rotor laminations A rotor comprises a first rotor lamination and a second rotor lamination. The first rotor lamination and the second rotor lamination are configured for defining, when joined into rotor assembly, a central axis of rotation and a plurality of interior magnet pockets disposed symmetrically about the central axis of rotation, each pocket of the plurality of interior magnet pockets is configured for housing and retaining a permanent magnet. A method of forming a rotor comprises forming a first rotor lamination and a second rotor lamination, rotating the second rotor lamination about an axis of symmetry of the second rotor lamination; and mating the first rotor lamination to the second rotor lamination such that a first notch of the first rotor lamination is disposed adjacent to the first notch of the second rotor lamination.
US09634525B2	Non-contact type power receiving apparatus In a non-contact type power receiving apparatus, two power receiving coils may share a single rectifying circuit. A non-contact type power receiving apparatus may include a first power receiving coil and a second power receiving coil, and a selective rectifying unit rectifying power from one of the first and second power receiving coils which receives the power from an external power transmitting coil in a non-contact scheme.
US09634524B2	Wireless power supply system A wireless power supply system includes a power-supplying device mounted on one of a mobile object and a structure different from the mobile object and a power-receiving device mounted on the other of the mobile object and the structure and supplies electric power from the power-supplying device to the power-receiving device disposed to face the power-supplying device under water or on surface of water. The wireless power supply system includes a contact portion that is disposed in the mobile object and that comes in contact with the structure and a thruster that presses the contact portion against the structure during the transmission of electric power.
US09634520B2	Case for mobile electronic device A case for a mobile electronic device is a case for a mobile electronic device which is capable of accommodating a mobile electronic device with a display surface, and supplying electric power to the mobile electronic device, the case including: a holder section having a first face which comes in contact with at least a portion of the mobile electronic device and a second face opposite from the first face; a protection cover to cover the display surface; a solar cell module provided on the protection cover to generate electric power, the solar cell module being externally exposed when the display surface is covered by the protection cover; and a moving mechanism capable of moving the protection cover over to the second face side while maintaining the solar cell module in an externally exposed state.
US09634516B2	Method and system for monitoring temperature of a power distribution circuit A method for monitoring a temperature change of a power distribution circuit having a power line and return line includes measuring an output current and output voltage of the power distribution circuit at an input to a load electrically connected to the power distribution circuit, and determining a change in temperature of at least one of the power line and return line based on a change in at least one of the output current and output voltage.
US09634515B2	Non-contact wireless communication coil, transmission coil, and portable wireless terminal A chargeable communication module is provided, which includes: a wireless power charging coil; a wireless communication coil being electrically isolated from the wireless power charging coil; and a magnetic body. The wireless power charging coil is disposed on a surface of the magnetic body. The wireless communication coil is arranged peripheral to the wireless power charging coil. A center of the wireless power charging coil is offset from a center of the wireless communication coil.
US09634514B2	Single stage rectification and regulation for wireless charging systems A rectification and regulation circuit for a wireless power receiver includes a coil, a full-wave rectifier circuit and a control unit. The full-wave rectifier has a first pair of controllable rectifiers including a first transistor connected to a first terminal of the coil and a second transistor connected to a second terminal of the coil. The control unit is operable to control switching of the transistors of the full-wave rectifier so that the full-wave rectifier (a) generates a rectified output for charging a battery of the wireless power receiver by rectifying current through the coil or voltage across the coil and (b) regulates the rectified output.
US09634510B2	Method of controlling charging and discharging of battery energy storage device and the battery energy storage device for the same A method of charging and discharging battery energy storage device is provided. The method includes measuring a voltage and a frequency of a grid, measuring a state of charge (SOC) value of a battery, calculating an SOC offset value and an SOC feedback gain value from the measured SOC value of the battery, and performing a voltage droop control based on the voltage of the grid and a frequency droop control on the basis of the frequency of the grid, the SOC offset value and the SOC feedback gain value and controlling charging and discharging of the battery.
US09634503B2	Battery chargers In one aspect according to the present teachings, a battery charger may include a body housing and a power supply connector disposed at a lateral side of the body housing. The power supply connector can supply a DC power to an external device.
US09634501B2	Protective circuit of unit cell The protective circuit includes a voltage dividing circuit connected in parallel between a first electrode and a second electrode of the unit cell and including a first voltage dividing resistor and a second voltage dividing resistor; a first switching device connected to a junction between the first voltage dividing resistor and the second voltage dividing resistor; a second switching device connected between the junction and the third switching device; and a fourth switching device connected between the junction and the third switching device, wherein, when output voltage of the unit cell becomes equal to or lower than a first reference voltage, the fourth switching device and the first switching device are sequentially turned off, the second switching device is turned on, and the third switching device is turned off, so that voltage output through the first output terminal can be cut off.
US09634500B2	Storage battery system The storage battery system includes a storage battery comprising a plurality of battery modules; a plurality of voltage monitoring circuits for monitoring a voltage of the battery module; and a control device that controls charging and discharging of the storage battery on the basis of monitoring information that is obtained by carrying out communication with the voltage monitoring circuits, wherein the control device comprises a determination unit that calculates an estimated output voltage of the storage battery by using the monitoring information that is obtained from any one of the voltage monitoring circuits before occurrence of a communication failure in a case where the communication failure with any one of the voltage monitoring circuits occurs, and compares the estimated output voltage and an output voltage of the storage battery after occurrence of the communication failure to determine an abnormal site of the communication failure.
US09634499B2	Adjusting device, battery pack device, and adjusting method An adjusting device that adjusts voltage differences among a plurality of storage batteries that are connected in series is provided with: charging means that charges said storage batteries; each switching means that corresponds to each of said plurality of storage batteries, that connects a corresponding storage battery to said charging means in parallel when turned ON, and that releases the connection between the corresponding storage battery and said charging means when turned OFF; detection means that detects each voltage of said plurality of storage batteries; and control means that turns ON, from among a plurality of said switching means, the control-object switching means that corresponds to the charge-object storage battery, which has the lowest voltage that is detected by said detection means, from among said plurality of storage batteries, and moreover, that turns OFF switching means other than said control-object switching means.
US09634497B2	Battery charging method and battery management system therefor A battery charging method, including obtaining a voltage capacity ratio for a reference charge C-rate and voltage capacity ratios for N (N an integer of 1 or more) charge C-rates greater than the reference charge C-rate, each of the voltage capacity ratios for the reference charge C-rate and the N charge C-rates being defined as a ratio of a voltage variance to a capacity variance depending on a change in state of charge (SOC) of a battery when the battery is charged at a corresponding one of the C-rates, comparing the voltage capacity ratio of the reference charge C-rate with each of the voltage capacity ratios of the N charge C-rates, and then setting a charge C-rate of the N charge C-rates so that a difference in voltage capacity ratio is minimized for each of SOC sections, and charging the battery with the charge C-rates corresponding to the SOC sections.
US09634495B2	Wireless power transfer using separately tunable resonators A system for wireless energy transfer includes a circuit for wireless transmission of energy, including a first, tunable resonator circuit including a transmitter coil and a variable capacitance device connected in shunt across the transmitter coil. Also disclosed is a circuit for wireless reception of energy including a tunable second resonator circuit including a receiver coil inductively coupled to the transmitter coil and a variable capacitance device connected in shunt across the receiver coil. Also disclosed is an arrangement for wireless energy transmission and reception that foregoes the necessity for separate circuits for DC rectification at the reception end of the arrangement. Also disclosed a system for wireless energy transfer where the system includes a tunable resonator circuit embedded in a surface such as piece of furniture, counter, etc., e.g., a table.
US09634492B2	Power generation method and system of power generator Provided are a power generation method and system of a power generator that can allow an output power of the power generator to be constant and cope with a case in which the velocity of a power generation source changes very quickly at a low lost. The power generation method includes determining a reference total power intended to be generated by a plurality of power generators, calculating a current command value through the reference total power and an instantaneous velocity sensed by each of the plurality of power generators, and regulating an output current of the power generator using the calculated current command value such that a total power output by the plurality of power generators is approximate to the reference total power.
US09634487B2	Architecture and management system and device for micro-grids with energy generation, storage and consumption, of the totally integrated, dynamic and self-configurable type Architecture system of a local grid made up of at least two single nodes constituting micro-grids, each managed by a self-configurable node controller that is also connected to the controllers of the other nodes and to the single energy generation, storage and consumption elements of its own node, the elements being variable in their configuration and dynamic in their behavior; the controller also optimizing the energy transfers according to specific management logics of the routine and sub-routine type.
US09634480B1	MOSFET protection using resistor-capacitor thermal network A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element. The RC circuit is responsive to the output current of the transconductance amplifier to produce an output voltage used to control the semiconductor element.
US09634475B2	Strain relief device for a harness or cable A strain relief device includes an elongated body having a first and second end, the elongated body defining an elongated hole extending from the first end to the second end; and edges in the body defining a plurality of voids between the first and second end, wherein the edges become shorter in length from the first end to the second end such that the shorter edges define progressively smaller voids in the body from the first end to the second end. A method of providing a strain relief is also disclosed.
US09634474B2	Electrical wiring system and method An electrical wiring system/method implementing transient voltage suppression is disclosed. The system/method incorporates HOT, NEUTRAL, GROUND wiring in conjunction with a series drop resistor (SDR) on the HOT conductor that supplies current to the load device. Parallel shunting metal oxide varistors (MOVs) are used in conjunction with corresponding shunt diode rectifiers (SDRs) to suppress transients on the HOT conductor to either the GROUND conductor and/or NEUTRAL conductor. The parallel shunting MOV/SDR pairs may be integrated into a singular structure that is encapsulated in an insulating material to permit implementation of the transient protection wiring system/method into electrical loads and common power distribution equipment such as electrical outlets and power strips.
US09634470B2	Method of constructing a distribution line using an extra-high voltage neutral line The present invention relates to a distribution line, and more particularly, to a method of constructing a distribution line using an extra-high voltage neutral line combined with an overhead earth wire having a separate installation structure of the extra-high voltage neutral line and a low-voltage neutral line for improving electric power quality, in which a distribution line simultaneously perform functions of an overhead earth wire for shielding lightning, an extra-high voltage neutral line for returning unbalanced currents and fault currents and an optical communication line for establishing a communication network, such that a number of disconnections of power lines is reduced by reducing surge voltage thereby achieving excellent lightning shielding effects such as improved power quality, etc., construction costs are reduced, load is reduced, construction quality is improved, and aesthetic features of the urban area is improved by simplifying the distribution equipment.
US09634467B2	Vertical cavity surface emitting laser and atomic oscillator A vertical cavity surface emitting laser includes: a laminated body; an insulation layer which is provided over at least a portion of the laminated body; an electrode of which at least a portion is provided over the laminated body; a pad; and a wiring which connects the electrode and the pad, wherein the laminated body includes a first mirror layer, an active layer, and a second mirror layer, the laminated body includes a first distortion imparting portion, a second distortion imparting portion, and a resonance portion which is provided between the first distortion imparting portion and the second distortion imparting portion, in a plan view, the electrode is provided so as to cover at least a portion of the resonance portion, in the plan view, a width of the wiring is greater than a width of the first distortion imparting portion and is smaller than a width of the electrode.
US09634466B2	External-cavity type laser with built-in wavemeter The present invention relates to an external cavity type laser provided with a wavemeter capable of precisely measuring a wavelength of a laser beam based on a transmission wavelength band of a wavelength selective filter inserted into a cavity regardless of a driving current of a laser diode chip. The external cavity type laser apparatus includes: a laser diode chip 100 emitting a laser beam; a beam feedback partial reflection mirror 500 reflecting a portion of the beam emitted from the laser diode chip 100 to feed the beam back to the laser diode chip 100; a collimating lens 200 installed on a path of a beam between the laser diode chip 100 and the beam feedback partial reflection mirror 500 to collimate the beam emitted from the laser diode chip 100; a 45-degree partial reflection mirror 300 converting a laser beam moving in parallel with a package bottom surface into a laser beam moving perpendicularly to the package bottom surface; a wavelength selective filter 400 transmitting a beam having a selected specific wavelength therethrough; a beam strength monitoring photodiode 600 disposed on a path of a beam moving from the collimating lens 200 to the 45-degree partial reflection mirror 300 and transmitting through the 45-degree partial reflection mirror 300; and a wavelength monitoring photodiode 700 disposed on a path of a beam moving from the wavelength selective filter 400 to the 45-degree partial reflection mirror 300 and transmitting through the 45-degree partial reflection mirror 300. A magnitude of a photocurrent flowing to the wavelength monitoring photodiode 700 is changed depending on a strength of a beam output oscillated in the laser diode chip 100 and a reflectivity at the wavelength selective filter 400, and a photocurrent flowing to the beam strength monitoring photodiode 600 is determined by the strength of the beam output outputted from the laser diode chip 100. Therefore, a value obtained by dividing the photocurrent flowing to the wavelength monitoring photodiode 700 by the photocurrent flowing to the beam strength monitoring photodiode 600 depends on only the reflectivity at the wavelength selective filter 400. Therefore, the value obtained by dividing the photocurrent flowing to the wavelength monitoring photodiode 700 by the photocurrent flowing to the beam strength monitoring photodiode 600 provides information on the wavelength of the laser beam based on the transmission band wavelength of the wavelength selective filter 400, and the wavelength of the laser beam may be figured out by measuring the value, and may be very precisely determined to be a predetermined wavelength.
US09634462B2	Slanted FBG for SRS suppression An example apparatus includes an optical fiber including a core and cladding, the core being situated to propagate an optical beam along a propagation axis associated with the core, and at least one fiber Bragg grating (FBG) situated in the core of the optical fiber, the fiber Bragg grating including a plurality of periodically spaced grating portions situated with respect to the propagation axis so that light associated with Raman scattering is directed out of the core so as to reduce the generation of optical gain associated with stimulated Raman scattering (SRS).
US09634461B1	Geometric isolator providing isolation between resonantly pumped cascaded laser A fiber optic geometric isolator is disclosed which is inserted between two cascaded, high-power fiber optic lasers and, in conjunction with a cladding mode stripper, provides improved optical Isolation between the two fiber optic lasers while maintaining highly-efficient laser operation. The isolator achieves this without the need for electromagnetic isolation between the two cascaded lasers. The isolator is an optical fiber designed to operate as a monolithic, continuous waveguide to enable a specific mode-coupling condition that converts the light of a first laser to that of a second, cascaded laser, with the light moving from the core of the first laser to both the core and the cladding of the second laser.
US09634456B2	Gas laser oscillation apparatus of orthogonal excitation type A gas laser oscillation apparatus of orthogonal excitation type includes an electric discharge region having a pair of electric discharge electrodes, an axial flow blower having a plurality of rotor vanes and working by a permanent magnet motor, a first heat exchanger having a plurality of cooling fins, the cooling fins arranged on a plane perpendicular to an optical axis, a second heat exchanger having a plurality of cooling fins, the cooling fins arranged on a plane perpendicular to the optical axis, a gas duct having a gas passageway and arranged between the electric discharge region and the first heat exchanger, the axial flow blower being arranged on the gas passageway. The axial flow blower is arranged on a windward side of the first heat exchanger. The second heat exchanger is arranged on a windward side of the axial flow blower.
US09634454B1	Laser illumination systems and methods for dual-excitation wavelength non-linear optical microscopy and micro-spectroscopy systems An illumination system is disclosed for providing dual excitation wavelength illumination for non-linear optical microscopy and micro-spectroscopy. The illumination system includes a laser system for providing a first train of pulses at a center optical frequency ω1, a frequency converting system for providing at least a second train of pulses at a center optical frequency ω2 and a third train of pulses at a center optical frequency ω3, where ω2 is different from ω1 and ω3 responsive to the first train of pulses, an amplifier system for amplifying the second train of pulses to provide an amplified second train of pulses, and an adjustment means for adjusting a time delay between the amplified second train of pulses and the third train of pulses for the dual-excitation wavelength illumination.
US09634452B2	Printed circuit board connector ejector A printed circuit board connector ejector includes a body extending from a first end to a second end. The body includes an outer surface and a passage extending through the body between the first and second ends. A plurality of threads extend at least partially though the passage. The plurality of threads is configured and disposed to engage with an electrical connector. An actuation member extends radially outwardly from the outer surface. The actuation member is configured and disposed to facilitate rotation of the body relative to an electrical connector.
US09634450B2	Electric wire with connector and method for manufacturing the same An electric wire with connector includes: an electric wire; a connector having a housing chamber to house an electric terminal provided at an end of the electric wire, the housing chamber opening on an end surface of the connector; and a waterproof member to cover the housing chamber. The waterproof member includes a sheet member having a width extending from the end surface of the connector as a reference position toward both of the connector and the electric wire. The sheet member has a wrapping shape winding around in a manner to have an overlapped region of the a front surface of one end of the sheet member and a back surface of the other end of the sheet member. The front surface and the back surface are contacted each other at the overlapped region. An inner peripheral surface of an end part of the waterproof member near the connector is contacted to an outer peripheral surface of the connector, and at least part of an inner peripheral surface of the other end part of the waterproof member near the electric wire is contacted to an outer peripheral surface of the electric wire.
US09634447B1	Electrical communication adapter system having an adapter board assembly and connector for interfacing with military communication systems An adapter system suited suitable for use in association with legacy military connectors including an adapter board assembly and an electrical cable connector. The adapter board assembly includes a pair of legacy connectors and a high density connector. A connector attachment block is attached to the adapter board assembly. The electrical cable connector includes a first side coupling assembly, a second side coupling assembly and a cable member extending therebetween. The first side coupling includes a connector matingly electrically attachable to the high density connector of the adapter board assembly, and a housing attachable to the connector attachment block. The adapter board assembly and the electrical cable connector are likewise separately disclosed.
US09634444B2	Cabinet backplane interconnect An interconnect for an installation environment adapted for housing at least one electrical component having a number of first connectors each having a first configuration, wherein the installation environment has pre-installed wiring having a number of second connectors each having a second configuration. The interconnect includes a backplane component including a number of third connectors adapted to connect with the number of first connectors, and a number of fourth connectors adapted to connect with the number of second connectors, wherein each of the number of fourth connectors is coupled to a respective one of the number of third connectors in a manner that maps the second configuration to the first configuration, and includes a mechanical bracket component adapted to allow for the installation of at least one electrical component such that the first connectors are connected to the third connectors.
US09634443B2	Connector and contact A connector includes a housing attached to a board; a ground terminal including a ground base disposed in the housing, and a first ground connection part extending from the ground base toward a first end of the housing and to be connected to a ground line of a coaxial cable; and a signal terminal including a signal base that is held in the housing and surrounded by the ground base while being insulated from the ground base, and a first signal connection part extending from the signal base toward the first end of the housing and to be connected to a signal line of the coaxial cable. The ground terminal and the signal terminal are configured to elastically bend at a second end of the housing when the housing is attached to the board.
US09634436B2	Electrical connector with locking structures for assembling contact modules An electrical connector includes an insulative housing, a number of first contact modules, a number of second contact modules and a number of third contacts all assembled into the insulative housing. Each first contact module includes a first wafer and first contacts insert-molded in the first wafer. Each second contact module includes a second wafer and second contacts insert-molded in the second wafer. The first contact modules, the second contact modules and the third contacts are arranged side by side after being inserted into the insulative housing. The adjacent first wafer and the second wafer cooperatively include mutual locking structures so that they can be inserted into the insulative housing in turn under a predetermined sequence.
US09634433B1	Communication jack having a dielectric film between plug interface contacts Embodiments of the present invention relate to designs for network jacks which can be used for cable connectivity. In an embodiment, the present invention is an RJ45 jack that utilizes a thin dielectric film between two layers of PICs that provide crosstalk compensation by way of their geometry. Compensation is achieved by way of capacitor plates which sandwich a thin dielectric film. This allows for the layers of PICs to be in close proximity and achieve higher coupling where desired, allowing a greater amount of compensation to occur close to the plug/jack contact point. This can have the effect of moving compensation closer to the plug/jack contact point, which in turn may reduce the amount of compensation needed further along the data path.
US09634432B2	High frequency connector with enhanced grounding for reduced crosstalk A high frequency connector with enhanced grounding for reduced crosstalk includes an insulative main body, a plurality of first terminals and second terminals, a back cover and a grounding member. The first terminals and the second terminals are disposed in the insulative main body, the back cover is provided at the second end of the insulative main body. The back cover is formed with an opening and capable of preventing the first terminals from being detached from the insulative main body. The grounding member has a body portion and contact sprint portion, the body portion is disposed inside the insulative main body and located between the first terminals and second terminals. The contact spring portion extends outward from the insulative main body and contacts the metal case of a mating plug connector for reducing crosstalk and restraining electromagnetic interference.
US09634430B1	Card edge connector A card edge connector can allow an insertion card with a locating groove on one side to be inserted thereto, the card edge connector including: a base housing, and an elastic clamping part. Two ends of the base body have two clamping portions, one sides thereof which are opposite are concaved to form a limiting slot, respectively; the elastic clamping part is fastened within one of the clamping portions, the elastic clamping part comprising a fastening base, an elastic arm, an elastic resisting portion and a limiting portion, one end of the fastening base can be retained in the clamping portion, another end thereof being connected with the elastic arm, a partial section of the elastic arm away from the fastening base being bent to form the elastic resisting portion, which can be exposed correspondingly to the limiting slot of the clamping portion retained by the elastic clamping part, one end of the elastic arm away from the fastening base having the limiting portion, so that it can be retained in the clamping portion; thereby, the insertion card may be prevented from vibration or shaking after insertion.
US09634429B2	Connector for a power input A connector includes a socket configured to be secured within a socket opening of a power input. A socket head has a plurality of plug insert receptacles. Each plug insert receptacle receives a conductive insert. The conductive insert connects with a cable that extends from the plug insert receptacle through and out of the socket. A plug contains a base. A head of the base has a plurality of plug insert units. Each plug insert unit receives a conductive insert that connects with a cable that extends out the base of the plug. A handle covers the base. The handle and the base are fixed and connected by a positioning device that includes an inverted tooth structure. The socket and plug when connected are secured in place by an elastic hasp.
US09634427B2	Shock and vibration resistant bulkhead connector with pliable contacts A high pressure and temperature, hermetically sealed bulkhead connector with pin and socket contacts for use in logging tools is described. The bulkhead connector comprises (a) one or more contact(s) placed within one or more channels wherein the channels provide a clearance path between contact(s) and bulkhead body and travel at least a partial longitudinal distance between proximal and distal ends. The contact(s) reside in the channel(s) and include at least; an optional movement limiter section, one central elongated section, and one fixed section where the contact(s) is attached to the bulkhead body at the distal end. The body correctly positions respective ends of the contact so that the body secures contact(s) to be parallel to each other and the contact(s) have terminal ends for connection. This arrangement provides at least one pivotable, pliable, free floating contact extending away from the fixed distal end of the bulkhead body.
US09634420B2	Electrical connector having a retainer An electrical connector has a retainer including a cantilever-type arm that operates with a small force. The retainer is held in the connector housing so as to be movable between a pre-latch position and a complete latch position, retaining terminals at the complete latch position. The retainer has: a first latch on the connector housing at the pre-latch position; a second latch on the connector housing at the complete latch position; a cantilever-type first elastic beam having a free end side formed with the pre-latch projection; and a second elastic beam having both ends supported by the first elastic beam and formed with the complete latch projection.
US09634419B2	Cold forming method for forming power pins and power pin formed thereof The invention discloses a cold forming method for forming power pins and a power pin formed thereof. The cold forming method for forming power pins comprises the following steps: step 1: cutting blank out; step 2: pre-forming the power pin body by necking; step 3: trimming the pre-formed power pin body, and pre-forming a pin fixing disk; step 4: forming the pin fixing disk and a staggered weld leg of pin. The invention also discloses a power pin formed by the cold forming method, composed of a power pin body, a pin fixing disk and a staggered weld leg of pin which are integrally formed into one piece by the cold forming method. The invention achieves high-speed automatic production and high production efficiency with a simple process, and improves material utilization and strength.
US09634417B2	Power connector A connector is disclosed including a housing and a pair of terminals. Each terminal includes a planar body portion and a planar mounting portion formed at the first end of the body portion with a bent contacting portion disposed therebetween. A wire securing portion is formed at the second end of the body portion with a pair of crimping portions to secure the wire to the terminal. The body portion and the mounting portion are received in a slot formed in the housing with the contacting portion extending through a window formed in the housing and the terminal mounting portion being translatable within the slot.
US09634416B2	Electrical connection arrangement A connection arrangement (10) for electrically connecting at least one sensor (12) or actuator to at least one conductor track (22) on a circuit board (24) has at least one compression spring (18) for electrically conductive connection. The compression spring (18) is arranged between the at least one sensor (12) or actuator and the circuit board (24) so as to be under a mechanical preload. The compression spring has a contact end section (36) of the at least one compression spring (18) configured to rest against a contact plate (20, 70, 80, 90) that is electrically conductively connected to the conductor track (22). As a result, the connection arrangement (10) achieves a high level of electrical contact reliability and corrosion-resistance.
US09634413B2	Connector A connector has a socket contact to be electrically connected to a counter-connector contact, the socket contact including: one or more pairs of conduction contact points disposed respectively on both sides of a fitting plane in an elastically displaceable manner; and one or more pairs of displacement regulator contact points disposed respectively on both sides of the fitting plane and coming into contact with the counter-connector contact when the counter-connector contact shifts, the one or more pairs of conduction contact points and the one or more pairs of displacement regulator contact points are disposed side by side in a direction along the fitting plane at a substantially same depth in a fitting direction, each of the pairs of displacement regulator contact points having a gap therebetween larger than that in each of the pairs of conduction contact points.
US09634411B2	Contact device mechanically mountable and electrically connectable on a printed circuit board by a fastening portion for receipt of an external plug element A contact device which is adapted to be mechanically mounted and electrically connected on a printed circuit board by a fastening portion and serves for receiving an external plug element. The contact device comprises a contact portion for inserting the external plug element for forming an electrical contact, an elastic support element for movably supporting the contact portion and for providing a possibility of movement in all spatial directions, wherein the support element includes a fastening part by which the contact device is fastened on the printed circuit board, a contact part for directly supporting the contact portion and a center part for connecting the fastening part and the contact part, the fastening part and the contact part bent relative to the center part, and of movement of the contact part and center part are limited by predetermined distances from adjacent external limiting means in the fastened state.
US09634408B2	Electrical circuit arrangement having a terminal on a flexible sheet disposed between a support layer and a counter contact In an electrical circuit with at least one flexible sheet element with electrical conductor tracks, at least one terminal arrangement for connection to a power supply and/or for data transmission, provision is made for the terminal to be formed by a portion of the sheet element with exposed conductor tracks, against which counter-contacts are positioned.
US09634407B2	Terminal module A terminal module is used for electrically connecting an electric element mounted on a first board to a second board opposing to the first board. A through-hole is opened in the second board. The terminal module includes: an electrically conductive terminal including at each of opposite ends thereof; a connection part through which the terminal module is electrically connected to the electric element; and a contact part to be inserted into the through-hole; and an electrically insulative base holding a part of the electrically conductive terminal to keep the electrically conductive terminal in a constant posture. The terminal module is mounted onto the first board keeping fixed thereto.
US09634402B2	Polarization diversity in array antennas An array antenna includes at least two antenna elements that are axially-aligned and axially-spaced. Polarization diversity is provided by at least one driven antenna element that provides horizontal and vertical polarizations. The driven element includes one or more feed points for the horizontal polarization and one or more feed points for the vertical polarization. A switching circuit is configured to switch between the one or more feed points to alternately provide the horizontal and vertical polarizations.
US09634401B2	Antenna array This antenna array includes at least one primary antenna, at least one secondary antenna and at least one load coupled to a secondary antenna. The load includes two separate components, a first component being a resistor and a second component being selected from an inductor or a capacitor. The antenna array can include one or more of the following characteristic features, taken into consideration individually or in accordance with any technically possible combinations: the first component has negative resistance; the second component has negative inductance or a negative capacitance; at least one load has an adjustable impedance. The antenna array may be used in a system, such as a vehicle, a terminal, a mobile telephone, a wireless network access point, a base station, or a radio frequency excitation probe.
US09634399B1	Antenna for transmitting partial orbital angular momentum beams An antenna system can impart orbital angular momentum (OAM) to an incident electromagnetic (EM) signal from a feed antenna. The antenna system can include a partial OAM antenna with a reflective surface that has only part of a full OAM shaped surface. The antenna system can thus reflect the incident EM signal as a partial OAM beam rather than a full OAM beam.
US09634392B2	Multi-coil module and electronic device The loss is reduced even when loop coils of a multi-coil module are overlaid with each other. The multi-coil module includes a first coil module, having a first magnetic sheet and a first loop coil provided on the first magnetic sheet and wound in a planar shape, and a second coil module, having a second magnetic sheet and a second loop coil provided on the second magnetic sheet and wound in a planar shape. The first coil module and the second coil module are stacked on each other, and at least an innermost coil pattern of the first loop coil and the second loop coil are overlaid with each other. The line width of the innermost coil pattern t of the first loop coil overlaid with the second loop coil is 1 mm or less.
US09634390B2	Antenna device A variable resonant circuit is inserted between a feeding point of a radiating element and a ground conductor. When the variable resonant circuit is not inserted, an input impedance of the radiating element is lower than about 50Ω and capacitive in a first low frequency band, lower than about 50Ω and inductive in a second low frequency band, and close to about 50Ω in a high frequency band. When the variable resonant circuit exhibits a first resonance characteristic, the variable resonant circuit is inductive in the first low frequency band, and its impedance in the high frequency band is higher than that in the first low frequency band. When the variable resonant circuit exhibits a second resonance characteristic, the variable resonant circuit is capacitive in the second low frequency band, and its impedance in the high frequency band is higher than that in the second low frequency band.
US09634389B2	Multipath switching system having adjustable phase shift array A multipath switching system comprising of an adjustable phase shift array includes, an adjustable phase shift array module and a control module. The adjustable phase shift array module receives a radio-frequency (RF) signal, and includes at least one RF switch, at least one coupler and at least one phase shifter. The at least one RF switch, the at least one coupler and the at least one phase shifter form a number of transmission paths. The transmission paths respectively produce the processed transmission RF signals corresponding to different phase shifts to an antenna array. The control module controls the at least one RF switch and the at least one phase shifter of the adjustable phase shift array module, so that the antenna array radiates a wireless signal whose direction is corresponding to a predetermined angle in space polar coordinates.
US09634388B2	Antenna beam A fixed phase shift for each of a plurality of radio frequency signal components directed to or received from a plurality of antenna elements is formed in a phase shifter. A desired antenna beam pattern with at least one grating lobe is formed on the basis of the phase-shifted radio frequency signal components of the antenna elements in a predefined antenna structure.
US09634385B2	Antenna apparatus and terminal device An antenna apparatus and a terminal device are provided, which relate to the field of communications technologies. A switch disposed at an end of an antenna arm controls an antenna to switch to different resonance frequencies, therefore reduced antenna efficiency caused by switch loss is avoided and space occupied by the antenna is not increased. The antenna apparatus includes an antenna and a printed circuit board, where a feedpoint and a first grounding point are disposed on the printed circuit board, the antenna is connected to the feedpoint, and the antenna includes a first arm.
US09634384B2	Chip antenna and manufacturing method thereof After a three-dimensional antenna pattern (10) is formed by bending a conductive plate, the three-dimensional antenna pattern (10) thus bent is supplied in an injection molding die set as an insert component and a base (20) is formed by injection molding of a resin. With this, a chip antenna (1) comprising the three-dimensional antenna pattern (10) can be formed easier as comparison to a case where the antenna pattern is formed over a plurality of surfaces by printing and the like.
US09634383B2	Galvanically separated non-interacting antenna sector apparatus and methods An antenna apparatus with isolated non-interactive sectors and methods operating and forming the same. In one embodiment, an antenna with a radiative element comprising a planar layer with multiple sectors is disclosed. The sectors are configured to be interactive or non-interactive. The interactive sectors contribute to the radiative profile of the antenna. The non-interactive sectors are galvanically isolated from the interactive sectors and do not substantially affect the radiative profile of the antenna. Region borders are present between various ones of the interacting and non-interacting sectors. These region borders provide the galvanic isolation between the interacting and non-interacting sectors. The antenna further includes feed portions coupled to the interactive sectors, thereby defining the antenna pattern. The non-interactive sectors are largely transparent to the radiative mode and thus do not substantially affect the antenna pattern.
US09634382B2	Portable antenna A portable antenna is disclosed that can be collapsed into, and erected from, a housing. There is also a pull cord mechanism arranged, when pulled, to cause the antenna to revert between the erect or collapsed configurations. The pull cord extends from the antenna to a position in easy reach of the soldier's hand so that the antenna can be erected/collapsed remotely.
US09634377B2	Electronic device An electronic device is provided. The electronic device includes a housing, a display, a supporting frame and an antenna. The display is disposed in the housing. The supporting frame supports the display. The antenna includes a radiator and a connection section. The connection section is connected to the radiator, wherein the connection section is coupled to the supporting frame.
US09634376B2	Wireless communication device A compact wireless communication includes a first radiating element and a second radiating element, which define and function as a dipole antenna, a feeder circuit including a wireless IC chip coupled with the first and second radiating elements, and a feeder substrate that is provided with the wireless IC chip. The first radiating element is provided to the feeder substrate. The second radiating element is provided to a substrate other than the feeder substrate.
US09634366B2	High-frequency module A high-frequency module includes port electrodes defining external connection terminals provided on a multilayer body including dielectric layers. A first port electrode is connected to an antenna. A plurality of port electrodes other than the first port electrode are respectively connected to communication systems supporting respective frequency bands. The first port electrode is connected to the plurality of other port electrodes through a plurality of switch elements. A first group of the plurality of switch elements and a second group of the plurality of switch elements are not connected to each other within a switch circuit and are connectable to each other through a common terminal outside of the switch circuit. As a result, a high-frequency module that allows a design change to be made using the same switch circuit without changing the switch circuit is provided.
US09634364B2	Support structure for traction battery assembly with integrated thermal plate A vehicle including a pair of spaced apart battery cell arrays, a pair of sub-structures configured to retain the arrays, and a thermal plate assembly disposed between the arrays is provided. Each of the sub-structures may include opposing endplates and opposing upper and lower sidewalls secured to the endplates and each having a flange extending toward and overlapping with the respective flange of the other sub-structure to join the sub-structures without mechanical fastening. The thermal plate assembly may be disposed between the overlapping flanges and the arrays to form a sandwich formation. The thermal plate assembly may include at least one thermal interface component disposed on a side of a thermal plate, and in contact with a portion of at least one of the battery cell arrays.
US09634362B2	Safety device for a vehicle and method for controlling the same A safety device for a vehicle having a battery system with a plurality of battery cells, a method for controlling the safety device, and a system that includes the safety device and the battery system. The safety device includes an electronic unit; a first device configured to detect an insulation resistance between components of the battery system and a reference potential, which components are connected in an electrically conductive manner to at least one battery cell; a second device configured to supply and/or discharge heat to and/or from the battery cells via a heat transfer medium which circulates in at least one circular flow pattern; and at least a first cut-off valve configured to interrupt the circular flow path of the heat transfer medium and which is actuated by the electronic unit from an open position into a closed position when the detected insulation resistance is below a predetermined limit value.
US09634356B2	Electrolyte for secondary battery and lithium secondary battery including the same Disclosed are an electrolyte for a lithium secondary battery which includes a non-aqueous solvent and a lithium salt, wherein the non-aqueous solvent includes an anion receptor, a cyclic carbonate, and a linear solvent, wherein an amount of the cyclic carbonate is in a range of 1 wt % to 30 wt % based on a total weight of the non-aqueous solvent, and a lithium secondary battery including the same.
US09634354B2	Solid state catholytes and electrolytes for energy storage devices The present invention provides an energy storage device comprising a cathode region or other element. The device has a major active region comprising a plurality of first active regions spatially disposed within the cathode region. The major active region expands or contracts from a first volume to a second volume during a period of a charge and discharge. The device has a catholyte material spatially confined within a spatial region of the cathode region and spatially disposed within spatial regions not occupied by the first active regions. The device has a protective material formed overlying exposed regions of the cathode material to substantially maintain the sulfur species within the catholyte material. Also included is a novel dopant configuration of the LiaMPbSc (LMPS) [M=Si, Ge, and/or Sn] containing material.
US09634353B2	Low internal resistance beta—and beta″—alumina electrolyte produced via vapor phase method A process for making a solid electrolyte for an electrochemical cell. The process includes providing a multilayer material having a porous layer and a nonporous layer, the nonporous layer containing a first oxide selected from alpha-alumina, gamma-alumina, alpha-gallium oxide, and/or combinations thereof. In addition, an alkali-metal oxide vapor is provided and the nonporous layer is exposed to the alkali-metal oxide vapor at an elevated temperature such that the nonporous layer is converted to a solid second oxide electrolyte layer that is conductive to alkali metal ions. The second oxide is an alkali-metal-beta-alumina, alkali-metal-beta″-alumina, alkali-metal-beta-gallate, and/or alkali-metal-beta″-gallate.
US09634351B2	Mechanical structures for maintaining structural integrity in cylindrical pouch cell batteries The disclosed embodiments relate to the design and manufacture of a battery cell. The battery cell includes a jelly roll containing layers which are wound together, including a cathode with an active coating, a separator, and an anode with an active coating. The battery cell also includes a mechanical structure disposed around a perimeter of the jelly roll to maintain a structural integrity of the jelly roll. Finally, the battery cell includes a pouch enclosing the mechanical structure and the jelly roll, wherein the pouch is flexible.
US09634345B2	Convective flow field for fuel cell stack The reactant distribution in a gas diffusion layer adjacent the landings of a solid polymer electrolyte fuel cell can be improved by using a flow field plate in which suitable sequential protrusions have been incorporated in the channels. The reactant flow field in the plate comprises a plurality of parallel channels in which protrusions are arranged in a sequence along each channel's length and the sequential protrusions in any given channel are offset with respect to the sequential protrusions in the channels immediately adjacent thereto.
US09634344B2	Hydrogen purifier, hydrogen generation apparatus, and fuel cell system A hydrogen purifier includes: a CO remover configured to reduce carbon monoxide in a hydrogen-containing gas through an oxidation reaction, the hydrogen-containing gas containing ammonia and carbon monoxide; and an ammonia remover provided upstream from the CO remover, the ammonia remover being configured to cause a reaction between ammonia in the hydrogen-containing gas and oxygen by using a catalyst to decompose the ammonia.
US09634341B2	Apparatus and method for diagnosing fuel cell An apparatus and method for diagnosing a fuel cell diagnoses a state of a fuel cell by estimating a fuel-cell equivalent circuit. The apparatus for diagnosing a fuel cell includes: an impedance measurement unit configured to measure impedance of a fuel cell within a predetermined frequency range; an equivalent circuit model unit configured to derive each parameter value by estimating a predetermined fuel-cell equivalent circuit model in response to the impedance received from the impedance measurement unit; and a fuel-cell-state diagnosis unit configured to diagnose a state of the fuel cell by detecting a variation of the parameter value derived from the equivalent circuit model unit.
US09634340B2	Plate-style water vapor transfer unit with integral headers A water vapor transfer unit having fluid flow conduits which distribute wet or dry fluid throughout the water vapor transfer unit, which are created by forming apertures in each wet and dry plate so that when the plates are stacked, fluid flow inlet and outlet headers are integrated into the flow stack. These integrated headers negate the need for traditional wet and dry fluid inlet and outlet manifolds external to the water vapor transfer unit stack. Because the plates are stacked and sealed so that the fluid flows cannot co-mingle, the fluids are introduced directly into the stack, flow across the flow fields, and exit the stack without leakage or flow contamination. The integrated header design allows for sealing the stack on no more than a single plane defined by the stack or on no more than two parallel opposing planes and allows for accommodation of stack expansion and contraction.
US09634339B2	Redox flow battery and method of operating the same A redox flow battery includes: a positive electrolyte storage tank; a negative electrolyte storage tank; a cell stack; a positive electrolyte outward path that sends positive electrolyte to positive electrode chambers in the cell stack; a positive electrolyte return path that sends positive electrolyte to the positive electrolyte storage tank; a negative electrolyte outward path that sends negative electrolyte to negative electrode chambers of the cells; a negative electrolyte return path that sends negative electrolyte to the negative electrolyte storage tank; an entrance open circuit voltage measuring portion that measures an upstream open circuit voltage between the positive electrolyte inside the positive electrolyte outward path and the negative electrolyte inside the negative electrolyte outward path; and an exit open circuit voltage measuring portion that measures a downstream open circuit voltage between the positive electrolyte inside the positive electrolyte return path and the negative electrolyte inside the negative electrolyte return path.
US09634338B2	Humidification cell A humidification cell of a fuel cell apparatus includes a first outer plate and a second outer plate. A gas chamber, a humidification chamber and a water-permeable membrane separating the two chambers, are disposed between the first outer plate and the second outer plate, starting from the first outer plate. A first water-permeable support element that prevents fibers from detaching and also prevents medium flows from blocking narrow gas outlets, is disposed between the first outer plate and the membrane in such a way that the first support element is made of a filter material.
US09634337B2	Freeze-resistant fuel cell condensers Cathode exhaust of an evaporatively cooled fuel cell stack (50) is condensed in a heat exchanger (12a, 23, 23a) having extended fins (14, 25a) or tubes (24, 24a) to prevent pooling of condensate, and/or having the entire exit surface of the condenser rendered hydrophilic with wicking (32) to conduct water away. The cathode exhaust flow paths may be vertical or horizontal, they may be partly or totally rendered hydrophilic, and if so, in liquid communication with hydrophilic end surfaces of the condenser, and the condensers (49) may be tilted away from a normal orientation with respect to earth's gravity.
US09634336B2	Fuel cell stack having end plate with external coolant manifold A first end plate of a fuel cell stack has a coolant supply manifold and a coolant discharge manifold. The coolant supply manifold includes a pair of manifold sections and a supply coupling section coupling upper portions of the pair of supply manifold sections. The pair of supply manifold sections communicate with a pair of coolant supply passages of the first end plate. A coolant supply pipe is coupled to a lower end of one of the supply manifold sections with an inclination of a predetermined angle from a vertical direction toward a horizontal direction.
US09634334B2	Laminated thin film battery Disclosed is a laminated thin film battery which is capable of exhibiting a high capacity and does not require a separate barrier to be formed on a surface after lamination. A first thin film battery and a second thin film battery, in which cathode current collectors and anode current collectors are formed on first surfaces, are laminated in such a type that the respective first surfaces face each other. The cathode current collectors of the first thin film battery and the second thin film battery are electrically connected to a cathode terminal, and the anode current collectors of the first thin film battery and the second thin film battery are electrically connected to an anode terminal.
US09634331B2	Non-PGM cathode catalysts for fuel cell application derived from heat treated heteroatomic amines precursors A method of preparing M-N—C catalysts utilizing a sacrificial support approach and inexpensive and readily available polymer precursors as the source of nitrogen and carbon is disclosed. Exemplary polymer precursors include non-porphyrin precursors with no initial catalytic activity. Examples of suitable non-catalytic non-porphyrin precursors include, but are not necessarily limited to low molecular weight precursors that form complexes with iron such as 4-aminoantipirine, phenylenediamine, hydroxysuccinimide, ethanolamine, and the like.
US09634327B2	Negative electrode active material for lithium ion secondary battery, method for producing the same, negative electrode, and battery In the case where a silicon substance having a high theoretical capacity as a negative electrode active material for a lithium ion secondary battery is used as a negative electrode active material, such a negative electrode active material is provided that has a high initial battery capacity and suffers less deterioration in performance even when many cycles of charge and discharge are repeated. A lithium ion secondary battery using the negative electrode active material is provided. Silicon and copper (II) oxide, or silicon, metallic copper and water are pulverized and simultaneously mixed in a pulverization device, thereby providing a negative electrode active material that has good cycle characteristics and a large battery capacity.
US09634326B2	Antimony based anode material for rechargeable batteries and preparation method An antimony based anode material for a rechargeable battery comprises nanoparticles of composition SbMxOy where M is a further element selected from the group consisting of Sn, Ni, Cu, In, Al, Ge, Pb, Bi, Fe, Co, Ga, with 0≦x<2 and 0≦y≦2.5+2x. The nanoparticles form a substantially monodisperse ensemble with an average size not exceeding a value of 30 nm and by a size deviation not exceeding 15%. A method for preparing the antimony based anode material is carried out in situ in a non-aqueous solvent and starts by reacting an antimony salt and an organometallic amide reactant and oleylamine.
US09634324B2	Nickel-metal hydride battery and method for producing hydrogen storage alloy It is an object of the present invention to improve the cycle performance in a nickel-metal hydride battery using a rare earth-Mg—Ni type alloy. The present invention provides a nickel-metal hydride battery having a negative electrode including an La—Mg—Ni based hydrogen absorbing alloy, wherein the hydrogen absorbing alloy has a crystal phase having Gd2Co7 type crystal structure and contains calcium.
US09634322B2	Active material for rechargeable battery, rechargeable battery, and electronic apparatus A rechargeable battery including: a positive electrode; a negative electrode including active material; and an electrolytic solution, in which the active material is capable of occluding and releasing lithium ions and includes Si and O as constituent elements, and an atomic ratio (Si/(Si+O)) of Si with respect to Si and O is 30 atomic % to 75 atomic % in a surface of the active material.
US09634317B2	Reactive separator for a metal-ion battery A reactive separator is provided for a metal-ion battery. The reactive separator is made up of a reactive layer that is chemically reactive to alkali or alkaline earth metals, and has a first side and a second side. A first non-reactive layer, chemically non-reactive with alkali or alkaline earth metals, is adjacent to the reactive layer first side. A second non-reactive layer, also chemically non-reactive with alkali or alkaline earth metals, is adjacent to the reactive layer second side. More explicitly, the first and second non-reactive layers are defined as having less than 5 percent by weight (wt %) of materials able to participate in electrochemical reactions with alkali or alkaline earth metals. The reactive layer may be formed as a porous membrane embedded with reactive components, where the porous membrane is carbon or a porous polymer. Alternatively, the reactive layer is formed as a polymer gel embedded with reactive components.
US09634315B2	Carbon containing binderless electrode formation An anode or negative electrode having a material matrix of carbon, graphene and an active element such as silicon or tin is described. The electrode is fabricated from an electrode slurry that does not utilize an organic binder. The electrode slurry comprises a combination of silicon and graphene oxide suspensions that is applied to a surface of a substrate such as a current collector. The layer of electrode slurry is heat treated to ensure adhesion of the layer of active electrode material to the surface of the current collector. The electrode may be incorporated within a lithium ion electrochemical cell.
US09634314B2	Battery pack and method of monitoring removal of secondary battery in battery pack A battery pack and a simple construction is provided. The battery pack includes a plurality of secondary batteries, a housing storing the plurality of secondary batteries, and an inspection circuit stored in the housing. The housing includes a main body section and a closing member to close an opening for taking the plurality of secondary batteries in and out of the main body section, and includes a plurality of fixing members for fixing the closing member on the main body section, the plurality of fixing members being made of a conductive material. An attachment state of the fixing members with respect to the closing member and the main body section is monitored by the inspection circuit, and an attachment order of the fixing members with respect to the closing member and the main body section is memorized by the inspection circuit.
US09634311B2	Separator including coating layer and battery including the same A separator includes a coating layer, the coating layer containing a polyvinylidene fluoride homopolymer, a polyvinylidene fluoride-hexafluoropropylene copolymer, a solvent, and inorganic particles, the solvent being present in an amount of about 100 ppm or less in the coating layer.
US09634308B2	Single layer structure of micron fibers applied in separator for battery A single layer structure of micron or nano fibers, and a multi-layer structure of micron and nano fibers. The single layer structure of micron fibers includes a web of micron fibers and an impregnating resin, and has a pore size of 1 nm-500 nm. The web of micron fibers is formed by plural interweaved micron fibers (D≧1 μm). The single layer structure of nano fibers includes a web of nano fibers formed by plural interweaved nano fibers (D<1 μm). The multi-layer structure of micron and nano fibers includes a web of interweaved micron fibers, a web of nano fibers formed by plural nano fibers interweaved on the web of micron fibers, a mixture layer formed by parts of the interweaved nano and micron fibers, and a resin at least impregnating the mixture layer and parts of the micron fibers of the web of micron fibers.
US09634307B2	Battery pack Provided is a battery pack that is unlikely to be affected by vibration, shock, or the like, and has stable characteristics.A battery pack includes a battery module 300 that is made by stacking battery holding bodies 200 on which film-covered batteries are placed with positive- and negative-electrode pull-out tabs being taken out from the same side in such a way that sides from which the positive- and negative-electrode pull-out tabs are pulled out are aligned with each other, wherein: an extension tab connected each of the tabs is pulled out from a battery holding body in such a way as to extend in a direction perpendicular to a direction of the pull-out tab and in a direction opposite to the other pull-out tab; and the extension tabs are each bent along a side surface in a direction perpendicular to a battery stacking surface, and are stacked up and electrically connected.
US09634304B2	Battery pack A battery pack includes a battery cell, a circuit board, and a holder. The battery cell includes a battery device covered with a laminate film. The circuit board is connected to the battery cell. The holder includes a cell holder that covers the battery cell and a circuit board holder that covers the circuit board. In battery pack, the circuit board holder covering the circuit board is arranged in a space formed above a terrace portion of the battery cell covered with the cell holder.
US09634288B2	Organic light emitting display device An organic light emitting display device includes a substrate, a light emitting structure, and a reflective metal layer. The substrate includes a pixel region and a peripheral region. The light emitting structure is disposed on the substrate. The reflective metal layer is disposed between the substrate and the light emitting structure. The reflective metal layer includes a plurality of nanowires and a plurality of openings that is defined by the nanowires.
US09634287B1	Display structure of display device with block members having different haights A display device and a method of manufacturing the display device are disclosed. In one aspect, the display device includes a substrate including a display region and a peripheral region. A first block member is in the peripheral region and surrounding display structures, the first block member having a first height. A second block member is spaced apart from the first block member in a first direction extending from the display region to the peripheral region, the second block member surrounding the first block member, the second block member having a second height that is greater than the first height. A first encapsulation layer is over the display structures, the first block member, and the second block member. A second encapsulation layer is over the first encapsulation layer, the second encapsulation layer overlapping at least a portion of the first block member in the depth dimension of the display device.
US09634282B2	OLED package structure and OLED packaging method The present invention provides an OLED package structure and an OLED packaging method. The OLED package structure includes a substrate (1), a package lid (2) arranged opposite to the substrate (1), an OLED device (11) arranged between the substrate (1) and the package lid (2) and mounted to the substrate (1), and enclosure rein (3) located between the substrate (1) and the package lid (2) and bonding the substrate (1) and the package lid (2) together. The package lid (2) includes a recess (21) formed therein at a location corresponding to the OLED device (11). The recess (21) includes therein a plurality of corrugation projection structures (212) arranged therein and extending outwards from a bottom of the recess (21). Desiccant (211) is attached to the bottom of the recess (21) in an area between two adjacent ones of the corrugation projection structures (212).
US09634281B2	Organic light-emitting display apparatus and method of manufacturing the same Disclosed is an organic light-emitting display apparatus. The organic light-emitting display apparatus includes a substrate, a first reflective electrode that is disposed over the substrate, an organic layer that is disposed over the first reflective electrode, and includes a light emission layer, and a second reflective electrode that is disposed over the organic layer. At least one of the first and second reflective electrodes comprises a low refractive layer having a refractive index of about 1.4 or less which is smaller than that of the organic layer.
US09634278B2	OLED pixel structure The present invention provides an OLED pixel structure, comprising: red, green and blue sub pixels, and the red sub pixel comprises a red light emitting layer, and the green sub pixel comprises a green light emitting layer, and the blue sub pixel comprises a blue light emitting layer, and material of the blue light emitting layer comprises inorganic quantum dots, and the blue light emitting layer emits white light, and a blue light filter is located corresponding to the blue sub pixel. By the blue sub pixel utilizing inorganic quantum dots+blue light filter, the stability and the life time of the OLED elements have been obviously promoted. The present invention further adds a white sub pixel, and the white sub pixel comprises a white light emitting layer, and material of the white light emitting layer comprises inorganic quantum dots. With the added white sub pixel, the luminous efficiency of the OLED is raised and the energy consumption thereof is reduced.
US09634275B2	Organic electroluminescent element, display device and illuminating device Disclosed is an organic electroluminescent element having high luminous efficiency and long life. Also disclosed are a display device and an illuminating device respectively using such an organic electroluminescent element. Specifically disclosed is an organic electroluminescent element comprising an electrode and at least one or more organic layers on a substrate. This organic electroluminescent element is characterized in that at least one of the organic layers is a light-emitting layer containing a phosphorescent compound and a host compound, the phosphorescent compound has a HOMO of −5.15 to −3.50 eV and a LUMO of from −1.25 to +1.00 eV, and the host compound has a 0-0 band of the phosphorescence spectrum at not more than 460 nm and a glass transition temperature of not less than 60° C.
US09634269B2	Conductive flexible substrate and manufacture thereof, and OLED display device and manufacture method thereof The present invention provides a conductive flexible substrate and a manufacture method thereof and an OLED display device and a manufacture method thereof. The conductive flexible substrate comprises a flexible substrate (1), mesh conductive lines (2) located on the flexible substrate (1) and embossing from a surface of one side of the flexible substrate (1), and a conductive layer (3) filling among the mesh conductive lines (2); a surface of one side of the flexible substrate (1) away from the mesh conductive lines (2) and the conductive layer (3) is flat. The conductive flexible substrate is capable of promoting the conductivity of the flexible substrate, and applying the conductive flexible substrate to an OLED display device can solve the issue of low conductivity of anodes in the OLED display device.
US09634267B2	Light-emitting element, light-emitting device, electronic device, and lighting device A light-emitting element of the present invention can have sufficiently high emission efficiency with a structure including a host material being able to remain chemically stable even if a phosphorescent compound having higher emission energy is used as a guest material. The relation between the relative emission intensity and the emission time of light emission obtained from the host material and the guest material contained in a light-emitting layer is represented by a multicomponent decay curve. The relative emission intensity of the slowest component of the multicomponent decay curve becomes 1/100 for a short time within a range where the slowest component is not interfered with by quenching of the host material (the emission time of the slowest component is preferably less than or equal to 15 μsec); thus, sufficiently high emission efficiency can be obtained.
US09634265B2	Organic electroluminescent materials and devices Novel organic compounds comprising ligands with deuterium substitution are provided. In particular, the compound is an iridium complex comprising methyl-d3 substituted ligands. The compounds may be used in organic light emitting devices to provide devices having improved color, efficiency and lifetime.
US09634263B2	Organic compound, light-emitting element, light-emitting device, display device, electronic device, and lighting device A novel organic compound that forms an exciplex emitting light with high efficiency is provided. An organic compound with a triarylamine skeleton in which the three aryl groups of the triarylamine skeleton are a p-biphenyl group, a fluoren-2-yl group, and a phenyl group to which a dibenzofuranyl group or a dibenzothiophenyl group is bonded. By the use of the organic compound and an organic compound with an electron-transport property, an exciplex that emits light with extremely high efficiency can be formed.
US09634260B2	Method for preparing conjugated compound having phenoxathiin and electron donating group of conjugated aromatic unit, and OLED device having the conjugated compound The disclosure provides a conjugated compound having phenoxathiinl, method for preparing the same and OLED. The conjugated compound has one of the following formulas: Different kinds of electron-rich conjugated aromatic units are reacted with intermediate having phenoxathiinl by Suzuki coupling, Buchwald-Hartwig coupling, or Cu-catalyzed amination of halogenated aromatic hydrocarbons for forming the conjugated compound having phenoxathiin. The prepared novel compound is fluorescent, so that it can be used as the material of light emitting layer of OLED devices.
US09634253B2	Donor-acceptor conjugated polymer and organic electronic device comprising the same Disclosed herein are a donor-acceptor conjugated polymer and an organic electronic device including the same. According to embodiments of the invention, it is possible to realize a conjugated polymer suitable for organic memory devices and a multi-functional, high-performance, large-area organic memory device for electronics including the same, the organic memory device operating in air.
US09634251B2	Nanotube solution treated with molecular additive, nanotube film having enhanced adhesion property, and methods for forming the nanotube solution and the nanotube film The present disclosure provides a nanotube solution being treated with a molecular additive, a nanotube film having enhanced adhesion property due to the treatment of the molecular additive, and methods for forming the nanotube solution and the nanotube film. The nanotube solution includes a liquid medium, nanotubes in the liquid medium, and a molecular additive in the liquid medium, wherein the molecular additive includes molecules that provide source elements for forming a group IV oxide within the nanotube solution. The molecular additive can introduce silicon (Si) and/or germanium (Ge) in the liquid medium, such that nominal silicon and/or germanium concentrations of the nanotube solution ranges from about 5 ppm to about 60 ppm.
US09634250B2	Resistive RAM devices and methods The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.
US09634242B2	Data reader with front shield coupling structure A data reader may consist of at least a magnetoresistive stack positioned on an air bearing surface. A portion of the magnetoresistive stack may be set to a first fixed magnetization by a pinning structure separated from the air bearing surface by a front shield that is set to a second fixed magnetization by a biasing structure. The front shield may be separated from the biasing structure by a coupling structure.
US09634235B2	Method for manufacturing liquid ejecting head A method for manufacturing a liquid ejecting head including a laminate formed of a flow path substrate having a flow path communicating with nozzle openings that eject a liquid, a first electrode, a piezoelectric layer, and a second electrode, the method including stacking the first electrode, the piezoelectric material, the second electrode, and a reinforcing member on top of one another to form a laminate; heating the laminate to form a piezoelectric layer made of the piezoelectric material; bonding the laminate to the flow path substrate on a first electrode side; and removing the reinforcing member.
US09634234B2	Downhole energy harvesting method and device A device generates electrical energy from mechanical motion in a downhole environment. The device includes a magnetostrictive element and an electrically conductive coil. The magnetostrictive element has a first end and a second end. The first and second ends are coupled between a rotor and a bearing. The magnetostrictive element is configured to experience axial strain in response to radial movement of at least one of the rotor or the bearing with reference to the other. The electrically conductive coil is disposed in proximity to the magnetostrictive element. The coil is configured to generate an electrical current in response to a change in flux density of the magnetostrictive element.
US09634223B2	Superconductor, superconducting wire, and method of forming the superconductor A super conductor is formed by a process including a first step of forming liquid-phase rare earth-copper-barium oxide by heat treating a superconductor precursor including a rare earth element, barium, and copper, a second step of forming a first superconductor of the rare earth-copper-barium oxide that is epitaxially grown from the liquid-phase rare earth-copper-barium oxide, and a third step of forming a second superconductor of the rare earth-copper-barium oxide by heat treating the first superconductor, wherein the heat treatment of the third step is performed in an atmosphere in which the rare earth-copper-barium oxide has no liquid phase.
US09634217B2	Thermally controllable energy generation system A thermally controllable energy generation system comprising an insulated, thermally-enhanced generator with a power circuit for conveying power. The thermally enhanced generator and its available voltage is controlled by a circuit which changes the ambient temperature of the generator through the use of a heating element and heating circuit. A controller circuit is in communication with the temperature sensor, the control circuit, the heating circuit and the power circuit. The thermally enhanced generator includes at least one cell, which comprises a layer of electron-rich donor material in contact with a layer of hole-rich acceptor material, sandwiched between an anode and a cathode. One of the layers is a stabilized mixture of carbon and an ionic material (carbon matrix) and the other layer is a stabilized oxide mixed with an ionic material (oxide matrix).
US09634215B2	Light emitting device package and light unit Embodiments provide a light emitting device package including a package body having a through-hole; a radiator disposed in the through-hole and including an alloy layer having Cu; and a light emitting device disposed on the radiator, wherein the alloy layer includes at least one of W or Mo, and wherein the package body includes cavity including a sidewall and a bottom surface, and wherein the through-hole is formed in the bottom surface.
US09634212B2	Semiconductor light emitting device and method for manufacturing the same A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.
US09634205B2	Light emitting device and image display unit A light emitting device includes a package having a recess, a lead frame buried in the package so that one end of the lead frame is exposed at a bottom of the recess and another end protrudes to an exterior of the package, a light emitting element arranged on the lead frame exposed at the bottom of the recess, and an encapsulant filled in the recess. The package includes, at the side face where the lead frame protrudes, a first side face formed inwardly relative to a side face of the lead frame, and a second side face formed at a lower portion of the first side face and protruded so as to cover a top face of the lead frame.
US09634203B2	Light emitting device, surface light source, liquid crystal display device, and method for manufacturing light emitting device A light emitting device includes: a substrate having a main surface; a phosphor layer provided on the main surface and containing an LED element that emits primary light and a fluorescent particle that absorbs a part of the primary light and emits secondary light; and a transparent resin layer having a refractive index n and covering the phosphor layer. The transparent resin layer has an outer circumferential surface that forms a boundary between the transparent resin layer and the atmosphere. When a minimum circumference that includes the overall phosphor layer and is concentric with the outer circumferential surface has a radius r in a cut surface where at least a part of the outer circumferential surface takes a shape of an arc having a radius R, a relationship of R>r·n is satisfied. With such configuration, the light extraction efficiency is enhanced.
US09634200B2	Semiconductor light emitting device A semiconductor light emitting device comprises a supporting substrate that has light reflecting characteristics; a wavelength conversion layer that is disposed on the supporting substrate, and contains semiconductor nanoparticles developing a quantum size effect; an optical semiconductor laminate that is disposed on the wavelength conversion layer and has light emitting characteristics; and a photonic crystal layer that is disposed on the optical semiconductor laminate, and that has first portions having a first refractive index and second portions having a second refractive index different from the first refractive index, the first portions and the second portions being arranged in a two-dimensional cyclic pattern.
US09634196B2	Nanostructure layer and light emitting diode with the same A nanostructure layer includes a number of nanostructures, wherein the number of nanostructures are aligned along a number of straight lines, a size of each of the number of nanostructures ranges from about 20 nanometers to about 100 nanometers, a distance between adjacent two nanostructures ranges from about 10 nanometers to about 300 nanometers, and each of the number of nanostructures includes a core and a shell coated on the core. A light emitting diode with the nanostructure layer is also provided.
US09634195B2	Light-emitting device A light-emitting device is provided. The light-emitting device comprises: a semiconductor system comprising a light-emitting semiconductor stack; and an electrode comprising a surface next to the semiconductor system and comprising a base material and a contact material different from the base material, wherein the contact material diffuses into the semiconductor system; wherein the contact material has a largest intensity at a first depth position from a SIMS spectrum, and a distance between the first depth position and the surface is not less than 500 nm.
US09634194B2	Light-emitting diode chip A light-emitting diode (LED) chip is disclosed. The chip includes a light-emitting diode and an electrode layer on the light-emitting diode. The electrode layer includes a reflective metal layer. The reflective metal layer includes a first composition and a second composition. The first composition includes aluminum or silver, and the second composition includes copper, silicon, tin, platinum, gold, palladium or a combination thereof. The weight percentage of the second composition is greater than 0% and less than 20%.
US09634192B2	Light emitting device and lighting system Disclosed are a light emitting device, a method of fabricating the same, a light emitting device package, and a lighting system. The light emitting device may include a substrate, a first conductive semiconductor layer on the substrate, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, an ohmic layer on the second conductive semiconductor layer, an insulating layer on the ohmic layer, a first branch electrode electrically connected with the first conductive semiconductor layer, a first pad electrode connected with the first branch electrode for electrical connection with the first conductive semiconductor layer, a second pad electrode in contact with the ohmic layer through the insulating layer, a second branch electrode connected with the second pad electrode on the insulating layer, and a second through electrode passing through the insulating layer to connect the second branch electrode with the ohmic layer.
US09634191B2	Wire bond free wafer level LED A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.
US09634184B2	Optoelectronic semiconductor device An optoelectronic semiconductor component includes a layer stack based on a nitride compound semiconductor and has an n-type semiconductor region , a p-type semiconductor region and an active layer arranged between the n-type semiconductor region and the p-type semiconductor region. In order to form an electron barrier, the p-type semiconductor region includes a layer sequence having a plurality of p-doped layers composed of AlxInyGa1−x−yN where 0<=x<=1, 0<=y<=1 and x+y<=1. The layer sequence includes a first p-doped layer having an aluminum proportion x1>=0.5 and a thickness of not more than 3 nm, and the first p-doped layer, at a side facing away from the active layer, is succeeded by at least a second p-doped layer having an aluminum proportion x2
US09634183B2	Semiconductor material doping A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s).
US09634181B2	Method of forming a composite substrate In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant a substrate. The III-nitride layer has a bulk lattice constant a layer. In some embodiments, [(\|a substrate−a layer\|)/asubstrate]*100% is no more than 1%.
US09634170B2	Concentrator photovoltaic panel, concentrator photovoltaic, and concentrator photovoltaic system A concentrator photovoltaic is formed by concentrator photovoltaic panels each having solar cells arranged on the back side of concentrating lenses. A plurality of portions of an image are imaged at the periphery of each of the solar cells in each of the panels. When each of the panels tracks the sun to be swung in the right-left direction and in the up-down direction, an image which can be identified through the concentrating lenses by a person who sees the image from a position in front of the concentrator photovoltaic is different according to an angle at which the panel is swung (direction rotation angle and elevation angle) due to the characteristic of the concentrating lenses. Therefore, the image of a letter or the like which appears with movement of the sun can be changed, and a message or the like according to time thereof can be displayed.
US09634166B2	Thin film photovoltaic cell with back contacts Photovoltaic cells, photovoltaic devices, and methods of fabrication are provided. The photovoltaic cells include a transparent substrate to allow light to enter the photovoltaic cell through the substrate, and a light absorption layer associated with the substrate. The light absorption layer has opposite first and second surfaces, with the first surface being closer to the transparent substrate than the second surface. A passivation layer is disposed over the second surface of the light absorption layer, and a plurality of first discrete contacts and a plurality of second discrete contacts are provided within the passivation layer to facilitate electrical coupling to the light absorption layer. A first electrode and a second electrode are disposed over the passivation layer to contact the plurality of first discrete contacts and the plurality of second discrete contacts, respectively. The first and second electrodes include a photon-reflective material.
US09634165B2	Regeneration method for restoring photovoltaic cell efficiency An apparatus, system, and method are disclosed for restoring efficiency of a photovoltaic cell. An illumination module illuminates photovoltaic cells so the cells receive a time integrated irradiance equivalent to at least 5 hours of solar illumination. After illumination, an annealing module anneals the photovoltaic cells at a temperature above 90 degrees Celsius for a minimum of 10 minutes. In one embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 20 hours of solar illumination. In another embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 16 hours of solar illumination while being heated to at least 50 degrees Celsius. In another embodiment, a solar concentrator irradiates the photovoltaic cells in sunlight for at least 10 hours and increases the irradiance of solar illumination on the cells by a factor of 2 to 5.
US09634162B2	Method of fabricating A(C)IGS based thin film using Se-Ag2Se core-shell nanoparticles, A(C)IGS based thin film fabricated by the same, and tandem solar cells including the A(C)IGS based thin film A method of fabricating an Ag—(Cu—)In—Ga—Se (A(C)IGS) based thin film using Se—Ag2Se core-shell nanoparticles, an A(C)IGS based thin film fabricated by the method, and a tandem solar cell having the A(C)IGS thin film are disclosed. More particularly, a method of fabricating a densified Ag—(Cu—)In—Ga—Se (A(C)IGS) based thin film by non-vacuum coating a substrate with a slurry containing Se—Ag2Se core-shell nanoparticles, an A(C)IGS based thin film fabricated by the method, and a tandem solar cell including the A(C)IGS based thin film are disclosed. According to the present invention, an A(C)IGS based thin film including Ag is manufactured by applying Se—Ag2Se core-shell nanoparticles in a process of manufacturing a (C)IGS thin film, thereby providing an A(C)IGS based thin film having a wide band gap.
US09634160B2	Solar cell and method for manufacturing the same A method for manufacturing asolar cell includes texturing a front surface of a semiconductor substrate having a first conductive type dopant by using a dry etching method, forming an emitter layer by ion-implanting a second conductive type dopant into the front surface of the semiconductor substrate, forming a back passivation film on a back surface of the semiconductor substrate; and forming a first electrode electrically connected to the emitter layer and a second electrode being in partial contact with the back surface of the semiconductor substrate.
US09634159B2	Integrated photodetector waveguide structure with alignment tolerance An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
US09634158B2	Semiconductor device and electronic equipment The present technology relates to a semiconductor device and electronic equipment in which a semiconductor device that suppresses the occurrence of noise by a leakage of light can be provided.A semiconductor device is configured which includes a light-receiving element 34, an active element for signal processing, and a light shielding structure 40 which is between the light-receiving element 34 and the active element to cover the active element and is formed of wirings 45 and 46. The semiconductor device further includes a first substrate on which the light-receiving element is formed, a second substrate on which the active element is formed, and a wiring layer which has a light shielding structure by the wirings which is formed on the second substrate, and in which the second substrate can be bonded to the first substrate through the wiring layer.
US09634157B2	Thin-film solar cell module and method for manufacturing the same A method for manufacturing a thin-film solar cell module includes a rear surface electrode layer deposition step for depositing a rear surface electrode layer on a substrate, an alkali metal adding step for adding an alkali metal to the rear surface electrode layer, a light absorbing layer deposition step for depositing a light absorbing layer on the rear surface electrode layer, a division groove forming step for forming a division groove that divides the light absorbing layer and exposing a front surface of the rear surface electrode layer in the division groove, an alloying step for alloying the rear surface electrode layer and the alkali metal on the front surface of the rear surface electrode layer exposed in the division groove, and a transparent conductive film deposition step for depositing a transparent conductive film on the light absorbing layer and in the division groove.
US09634154B1	Schottky diode having a well with peripherial cathod regions and center andoe region In some embodiments, a semiconductor device includes a first well region configured to be an anode of the semiconductor device, a first doped region configured to be a cathode of the semiconductor device, a second doped region configured to be another cathode of the semiconductor device, and a conductive region. The first well region is disposed between the first doped region and the second doped region, and is configured for electrical connection of the conductive region.
US09634149B2	Semiconductor device and method for manufacturing thereof A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region.
US09634144B2	Semiconductor devices and methods of fabricating the same Semiconductor devices and methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a fin disposed on a substrate. The fin may include an insulating layer pattern disposed in a top surface of the fin. The semiconductor devices may also include a wire pattern disposed on the insulating layer pattern to be separated from the insulating layer pattern and a gate electrode surrounding the wire pattern.
US09634137B2	Integrated power transistor circuit having a current-measuring cell An integrated power transistor circuit includes a contact structure with a first section and a second section. The first section contacts doped regions of transistor cells in a cell array. The second section includes one or more first subsections which adjoin the first section and extend beyond the cell array in the region of selected transistor cells. A second subsection adjoins the one or more first subsections and forms a tapping line, for example for making contact with source regions of power transistor cells. In the region of the cell array, an electrode structure rests on the contact structure. This electrode structure is absent over the second section. The tapping line can thus be formed at a short distance from the electrode structure, with the result that the active chip area is only insubstantially reduced by the tapping line.
US09634130B2	Semiconductor device A semiconductor device includes stripe-shaped gate trench formed in one major surface of n-type drift layer, gate trench including gate polysilicon formed therein, and gate polysilicon being connected to a gate electrode; p-type base layer formed selectively in mesa region between adjacent gate trenches, p-type base layer including n-type emitter layer and connected to emitter electrode; one or more dummy trenches formed between p-type base layers adjoining to each other in the extending direction of gate trenches; and electrically conductive dummy polysilicon formed on an inner side wall of dummy trench with gate oxide film interposed between dummy polysilicon and dummy trench, dummy polysilicon being spaced apart from gate polysilicon. Dummy polysilicon may be connected to emitter electrode. The structure according to the invention facilitates providing an insulated-gate semiconductor device, the Miller capacitance of which is small, even when the voltage applied between the collector and emitter is low.
US09634123B2	FinFET device including a dielectrically isolated silicon alloy fin A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.
US09634120B2	Electronic device and method for fabricating the same Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.
US09634118B2	Methods of forming semiconductor devices Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming first and second dielectric layers in first and second trenches. The method includes forming first and second conductive layers on the first and second dielectric layers, respectively. The method includes forming first and second protective layers on the first and second conductive layers, respectively. The method includes performing an annealing process while the first and second protective layers are on the first and second conductive layers. The method includes removing the first and second protective layers. The method includes removing the first conductive layer, after performing the annealing process. Moreover, the method includes forming first and second gate metals in the first and second trenches, respectively, after removing the first conductive layer.
US09634116B2	Method to improve reliability of high-K metal gate stacks A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer.
US09634105B2	Silicon nano-tip thin film for flash memory cells A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.
US09634104B2	FinFET and method of fabricating the same A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins.
US09634100B2	Semiconductor devices with integrated hole collectors Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons.
US09634099B2	Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact.
US09634098B2	Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony.
US09634092B2	Semiconductor devices having tapered active regions Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part.
US09634088B1	Junction formation with reduced CEFF for 22NM FDSOI devices A method of forming a semiconductor device is disclosed including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a transistor device on the silicon-on-insulator substrate including providing a gate structure on the semiconductor layer having a gate electrode and a first cap layer on the gate electrode, growing an oxide liner on the transistor device having a first part covering the gate structure and a second part covering the semiconductor layer, forming a second cap layer on the oxide liner, at least partially removing the second part of the oxide liner underneath the second cap layer and the first part of the oxide liner, and epitaxially forming raised source/drain regions on the semiconductor layer.
US09634087B1	FinFET and fabrication method thereof A method is provided for fabricating a FinFET. The method includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer may corresponds to a position of subsequently formed fin; forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through ion implantation process; forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in the doping region diffuse into the semiconductor substrate under the hard mask layer; and forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein the semiconductor substrates between the adjacent trenches constitutes a fin.
US09634085B1	Semiconductor device including a LDMOS transistor In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.
US09634083B2	Semiconductor structure and process thereof A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures.
US09634080B2	Display device A display device includes contact holes opened in an insulating film outside of a display area in which pixels are arranged, and having a conductive film exposed in bottom portions, a first metal film formed to cover the contact holes and come in contact with the conductive film of the bottom portions, and a transparent conductive film formed on the first metal film.
US09634077B2	Organic light emitting display devices and methods of manufacturing organic light emitting display devices An organic light emitting display device may include a substrate having a pixel region and a transparent region, a first capacitor disposed in the transparent region of the substrate, a semiconductor device disposed in the pixel region of the substrate, a second capacitor disposed on the semiconductor device, and an organic light emitting structure disposed on the second capacitor. The organic light emitting display device may have a sufficient capacitance for components including the semiconductor device and the organic light emitting structure without increasing an area of the pixel region while maintaining a transmittance of the organic light emitting display device.
US09634075B2	Organic light emitting display device An organic light emitting display device including: a first emission area including a first organic light emitting diode; a second emission area arranged adjacent to the first emission area and not overlapping with the first emission area, the second emission area including a second organic light emitting diode; a pixel circuit unit electrically connected to the first organic light emitting diode and the second organic light emitting diode; and a transmissive area adjacent to the first and second emission areas and not overlapping with the first and second emission areas, the transmissive area configured to transmit external light therethrough.
US09634073B2	Organic light-emitting display device and method of manufacturing the same An organic light-emitting display device includes a substrate. A buffer layer is formed on the substrate. A thin film transistor is disposed on the buffer layer. The thin film transistor includes an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer, and a second insulating layer. An uneven pattern is formed by patterning the buffer layer. A first pixel electrode is disposed in an opening formed in the second insulating layer. The first pixel electrode includes a transparent conductive oxide. A second pixel electrode is disposed on the first pixel electrode. The second pixel electrode includes a semi-transmissive layer. An organic lighting-emitting layer is formed on the second pixel electrode. An opposite electrode is formed on the organic lighting-emitting layer.
US09634072B2	Organic light-emitting display device and method of manufacturing the same An organic light-emitting display device includes: a substrate; an active layer on the substrate; a gate electrode insulated from the active layer and overlapping with the active layer; a source electrode including a first source electrode layer, connected to the active layer, and a second source electrode layer connected to the first source electrode layer, the second source electrode layer being larger than the first source electrode layer; a drain electrode including a first drain electrode layer connected to the active layer, and a second drain electrode layer connected to the first drain electrode layer, the second drain electrode layer being larger than the first drain electrode layer; a first electrode directly connected to a top surface of the source electrode or the drain electrode; an intermediate layer on the first electrode and including an organic emission layer; and a second electrode on the intermediate layer.
US09634071B2	Thin film transistor, and thin film transistor array panel and organic light emitting diode display including the same A thin film transistor includes a semiconductor which is disposed on a substrate and includes a source region, a drain region and a channel region, a gate insulating layer disposed on the semiconductor, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, contact holes defined in the interlayer insulating layer, the contact holes respectively exposing the source region and the drain region of the semiconductor, and a source electrode and a drain electrode which are disposed on the interlayer insulating layer and respectively contact the source region and the drain region through the contact holes, where at least one of the contact holes exposing the source region and the drain region obliquely traverses the semiconductor.
US09634061B2	Light emitting diode A light emitting diode including a first light emitting cell and a second light emitting cell disposed on a substrate and spaced apart from each other to expose a surface of the substrate, a first transparent layer disposed on and electrically connected to the first light emitting cell, first connection section disposed on a portion of the first light emitting cell, a second connection section disposed on a portion of the second light emitting cell, a first interconnection and a second interconnection electrically connecting the first light emitting cell and the second light emitting cell, and an insulation layer disposed between the first and second interconnections and a side surface of the first light emitting cell.
US09634059B2	Methods of forming image sensor integrated circuit packages A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.
US09634058B2	Image sensor and computing system having the same An image sensor includes a light receiving element, an anti-reflection layer, a high refractive pattern, a color filter, and a micro lens. The light receiving element is formed on a semiconductor substrate to generate charges responsive to incident light. The anti-reflection layer is formed on the semiconductor substrate. The high refractive pattern is formed on the anti-reflection layer in correspondence with the light receiving element. The color filter is formed on the anti-reflection layer while covering a top surface and lateral sides of the high refractive pattern. The micro lens is formed on the color filter. The image sensor provides an image having high quality.
US09634057B2	Digital detector possessing a generator of light enabling optical wiping A solid-state radiation detector comprising a photosensitive sensor comprises photosensitive elements that are organized in a matrix, and a light generator whose purpose is to optically wipe the photosensitive elements. The light generator comprises: an electroluminescent layer that is distributed over the surface of the sensor; at least one electrode that continuously covers the electroluminescent layer and in which electrons may flow, the light emitted by the electroluminescent layer being capable of passing through the electrode; and additional electrical conductors that are in electrical contact with the electrode, the additional electrical conductors forming branches that extend over the surface of the electrode, and being spatially distributed across the surface of the electrode.
US09634053B2	Image sensor chip sidewall interconnection An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided.
US09634052B2	Semiconductor device, solid-state image sensor and camera system The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.
US09634050B2	Fabrication of optics wafer Fabricating an optics wafer includes providing a wafer including a core region composed of a glass-reinforced epoxy. The wafer further includes a first resin layer on a top surface of the core region and a second resin layer on a bottom surface of the core region. The core region and first and second resin layers are substantially non-transparent for a specific range of the electromagnetic spectrum. The wafer further includes vertical transparent regions that extend through the core region and the first and second resin layers and are composed of a solid material that is substantially transparent for the specific range of the electromagnetic spectrum. The wafer is thinned, and optical structures are provided on one or more exposed surfaces of at least some of the transparent regions.
US09634049B2	Solid-state imaging devices with enhanced angular response A solid-state imaging device includes a substrate containing a plurality of photoelectric conversion elements arranged into a pixel array. A color filter layer including a plurality of color filter segments is disposed above the photoelectric conversion elements. A partition grid includes a plurality of partitions, and each of the partitions is disposed between two adjacent color filter segments. The color filter layer and the partition grid are disposed in the same layer. In addition, the partitions include a first partition disposed at a center line of the pixel array and a second partition disposed at an edge of the pixel array. The second partition has a top width that is larger than the top width of the first partition.
US09634048B2	Imaging device and electronic device An imaging device with excellent imaging performance is provided. The imaging device has a first circuit including a first photoelectric conversion element and a second circuit including a second photoelectric conversion element. The second circuit is shielded from light. In the imaging device, a current mirror circuit in which a transistor connected to the second photoelectric conversion element serves as an input transistor and a transistor connected to the first photoelectric conversion element serves as an output transistor is formed. With such a configuration, the amount of photocurrent in the first circuit from which the contribution of the dark current of the first photoelectric conversion element has been excluded can be detected.
US09634045B2	Method for forming thin film pattern The present disclosure provides a method for forming a thin film pattern. The method includes steps of: forming a mask pattern on a thin film in such a manner that the mask pattern includes a reserved portion corresponding to a region where the thin film pattern to be formed is located, and a partially-reserved portion neighboring the reserved portion; performing a wet-etching process to etch off a portion of the thin film which is not covered by the mask pattern; performing a dry etching process to remove the partially-reserved portion and thin the reserved portion; and performing a dry etching process to etch off a portion of the thin film which is not covered by the remaining mask pattern, so as to form the thin film pattern.
US09634044B2	Method for fabricating array substrate Embodiments of the invention provides a method for fabricating an array substrate comprising: forming, on a substrate, at least two semiconductor active islands, first patterns positioned on both sides of each of the semiconductor active islands, second patterns positioned at outer side of a part of the first patterns, and third patterns positioned at outer side of the rest of the first patterns, through a single patterning process; doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type.
US09634043B2	Array substrate, manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate patterning the metal film by one patterning process, and forming patterns of a gate electrode a source electrode, a drain electrode a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion, a pixel electrode and a bridge structure.
US09634041B2	Display apparatus and method of manufacturing the same A display apparatus includes a number of pixels. Each pixel includes a substrate including a pixel area and a non-pixel area disposed between adjacent pixel areas, a first electrode disposed on the substrate in the pixel area, and a second electrode extending in a first direction and being spaced apart upward from the substrate by a predetermined distance in the pixel area defining a tunnel-shaped cavity, an image display layer disposed in the tunnel-shaped cavity and driven by an electric field formed between the first electrode and the second electrode, a roof layer disposed on the second electrode, and a sealing layer extending in the first direction, having a black color, and being disposed in the non-pixel area between adjacent pixel areas in a second direction crossing the first direction to seal the tunnel-shaped cavity.
US09634030B2	Array substrate and manufacturing method thereof An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a black matrix layer having a plurality of black matrixes on a substrate; forming a switch array layer having a plurality of thin-film transistors on the black matrix layer; forming a color resist layer having a plurality of color resists on the switch array layer; and forming a transparent conductive layer on the color resist layer.
US09634026B1	Standard cell architecture for reduced leakage current and improved decoupling capacitance A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source.
US09634025B2	Integrated structures and methods of forming vertically-stacked memory cells Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells.
US09634024B2	Semiconductor device having vertical channel and air gap, and method of manufacturing thereof A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.
US09634021B2	Method of manufacturing semiconductor device A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area.
US09634016B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape.
US09634012B2	Method of forming active patterns, active pattern array, and method of manufacturing a semiconductor device In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions.
US09634007B2	Trench confined epitaxially grown device layer(s) Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.
US09634006B2	Third type of metal gate stack for CMOS devices A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack.
US09634005B2	Gate planarity for FinFET using dummy polish stop A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature.
US09634002B1	Semiconductor device and method of manufacturing the same A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts.
US09633998B2	Semiconductor device and method for making the same A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented.
US09633996B1	High density area efficient thin-oxide decoupling capacitor using conductive gate resistor A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1).
US09633995B2	Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.
US09633994B2	BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor A MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies.
US09633992B1	Electrostatic discharge protection device An ESD protection device is provided. Each of a first and a second well has a first conductive type. Each of a first and a second doping region has a second conductive type and is formed in the first well. A third doping region has the first conductive type. A fourth doping region has the second conductive type. The third and fourth doping regions are formed in the second doping region. Each of a fifth and a sixth doping region has the second conductive type and is formed in the second well. A seventh doping region has the first conductive type. An eighth doping region has the second conductive type. The seventh and eighth doping region are formed in the sixth doping region. A first and a second trigger gate are formed on the first and second wells and partially cover the second and sixth doping regions respectively.
US09633991B2	Mutual ballasting multi-finger bidirectional ESD device An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node.
US09633990B2	Bi-directional ESD protection device An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions.
US09633983B2	Semiconductor chip stacking assemblies Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second semiconductor device. An assembly comprises a first semiconductor chip that has a first and a second set of electrical interconnect regions disposed on its surface and a second semiconductor chip. The first set of electrical interconnect regions are electrically connected with the electrical interconnect regions of a second semiconductor chip, and the second set of electrical interconnect regions are electrically interconnected with the substrate. Direct electrical connections are for example, silicon photonics device-to-driver or device-to-signal converters, logic-to-memory, memory-to-memory, and logic-to-logic chip interconnections.
US09633982B2	Method of manufacturing semiconductor device array Present disclosure provides a method for manufacturing a semiconductor device array, including (1) providing a temporary substrate; (2) forming a plurality of discrete semiconductor structures over the temporary substrate; and (3) removing a surface portion of the temporary substrate to expose a peripheral bottom surface of the discrete semiconductor structure. Present disclosure also provides a method for transferring discrete semiconductor device, including (1) detaching discrete semiconductor structures of a first type from a first temporary substrate supporting the discrete semiconductor structures of the first type by a transfer stamp; (2) carrying the discrete semiconductor structures over a target substrate by the transfer stamp; and (3) dismounting the discrete semiconductor structures of the first type from the transfer stamp to predetermined sites on the target substrate. The transfer stamp includes a plurality of protrusions, positions of the plurality of protrusions being programmable to match the predetermined sites on the target substrate.
US09633980B2	Semiconductor device According to one embodiment, a semiconductor device includes a first semiconductor chip including a first circuit, a second circuit, a first interconnect connected to the first circuit, a second interconnect connected to the second circuit, and a third interconnect connecting the first interconnect and the second interconnect.
US09633979B2	Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation.
US09633976B1	Systems and methods for inter-chip communication A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device.
US09633975B2	Multi-die wirebond packages with elongated windows A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening.
US09633963B2	Packaging devices and methods of manufacture thereof Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region.
US09633962B2	Plug via formation with grid features in the passivation layer Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line.
US09633957B2	Semiconductor device, a power semiconductor device, and a method for processing a semiconductor device According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy.
US09633952B2	Substrate structure and method for manufacturing same Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate.
US09633950B1	Integrated device comprising flexible connector between integrated circuit (IC) packages Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer.
US09633946B1	Seamless metallization contacts The present disclosure relates to semiconductor structures and, more particularly, to seamless metallization structures and methods of manufacture. A structure includes: a contact opening formed in an oxide material and in alignment with an underlying structure; a metal liner lining the sidewalls and bottom of the contact opening, in direct electrical contact with the underlying structure; a conductive liner on the metal liner, within the contact opening; and tungsten fill material on the conductive liner and within the contact opening.
US09633945B1	Semiconductor device and method of manufacturing semiconductor device According to one embodiment, there is provided a semiconductor device, which includes an electrode lead-out part, a planarization film, contacts, and first and second columnar patterns. The electrode lead-out part is arranged such that an electrode film and an insulating film are alternately stacked in a plurality of layers, and layers of the electrode film are arranged stepwise. The planarization film is arranged above the electrode lead-out part. The first columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a first depth. The second columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a second depth larger than the first depth.
US09633942B1	Conductively doped polymer pattern placement error compensation layer A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.
US09633941B2	Semiconductor device structure and method for forming the same A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure.
US09633937B2	Electronic assembly that includes stacked electronic devices The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer.
US09633935B2	Stacked chip package including substrate with recess adjoining side edge of substrate and method for forming the same A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided.
US09633933B2	Lead frame with anchor-shaped lead A lead frame includes a die pad and a plurality of leads arranged around the die pad. Each of the leads includes an inner lead, a bent portion, and an external connection terminal. The inner lead includes a distal portion, adjacent to the die pad, and a connection end portion, located at an opposite end of the inner lead from the distal portion. The bent portion is connected to the connection end portion of the inner lead. The external connection terminal is connected by the bent portion to the connection end portion of the inner lead and located below the inner lead. The external connection terminal includes an upper surface that faces to and is parallel to a lower surface of the inner lead. The inner lead, the bent portion, and the external connection terminal are formed integrally in each of the leads.
US09633931B2	Chip rotated at an angle mounted on die pad region A package includes: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package; a die pad region surrounded with the lead frames in a plane view; a semiconductor chip mounted on the die pad region; a plurality of bonding pads disposed on the semiconductor chip; and a plurality of bonding wires configured to connect the lead frames and the bonding pads, respectively, wherein the bonding wires are respectively connected to front end portions of the lead frames by bonding with an angle ranging from 45 to 135 degrees with respect to a trace of front end portions of the lead frames in the plane view.
US09633929B2	TSV formation A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material.
US09633926B2	Semiconductor device and manufacturing method of semiconductor device A semiconductor device includes a stacked unit having a semiconductor module, a first cooler having a first opening and a first coolant flow path that is connected to the first opening, and a second cooler that has a second opening and a second coolant flow path that is connected to the second opening, and being formed by the first cooler and the second cooler sandwiching the semiconductor module and being stacked such that the first opening and the second opening face each other; a seal member that is arranged between the first opening and the second opening that are adjacent in a stacking direction, and that connect the first opening and the second opening; and a winding member that keeps pressure applied to the stacked unit in the stacking direction by being wound around the stacked unit.
US09633923B2	Electronic device module and manufacturing method thereof There are provided an electronic device module capable of increasing a degree of integration by mounting electronic components on both surfaces of a board, and a manufacturing method thereof. The electronic device module includes a board having mounting electrodes formed on both surfaces thereof, a plurality of electronic devices mounted on the mounting electrodes, a molded portion sealing the electronic devices, at least one connection wire having one end bonded to one surface of the board and the other end exposed to the outside of the molded portion, and an external connection terminal coupled to the other end of the connection wire.
US09633917B2	Three dimensional integrated circuit structure and method of manufacturing the same Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via.
US09633916B2	Display panel and method of manufacturing the same A display panel includes first to third test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer, and disposed adjacent to the first test pad in the second direction, a third test pad electrically connected to the third test line and disposed adjacent to the first test pad in the first direction, the third test pad and the third test line being formed from a same layer.
US09633911B2	Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided.
US09633908B2	Method for forming a semiconductor structure containing high mobility semiconductor channel materials A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer.
US09633904B1	Method for manufacturing semiconductor device with epitaxial structure A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses.
US09633903B2	Device manufacturing method of processing cut portions of semiconductor substrate using carbon dioxide particles A device manufacturing method according to an embodiment includes forming a film on the side of a second surface of a substrate having a first surface and the second surface, cutting the substrate, cutting the film, and injecting particles onto at least one of a first cut portion formed by the cutting of the substrate and a second cut portion formed by the cutting of the film, to process the at least one of the first cut portion or the second cut portion.
US09633900B2	Method for through silicon via structure A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.
US09633896B1	Methods for formation of low-k aluminum-containing etch stop films Dielectric AlO, AlOC, AlON and AlOCN films characterized by a dielectric constant (k) of less than about 10 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers and/or diffusion barriers. In one implementation, a substrate containing an exposed dielectric layer (e.g., a ULK dielectric) and an exposed metal layer is contacted with an aluminum-containing compound (such as trimethylaluminum) in an iALD process chamber and the aluminum-containing compound is allowed to adsorb onto the surface of the substrate. This step is performed in an absence of plasma. Next, the unadsorbed aluminum-containing compound is removed from the process chamber, and the substrate is treated with a process gas containing CO2 or N2O, and an inert gas in a plasma to form an AlO, AlOC, or AlON layer. These steps are then repeated.
US09633895B2	Integrated fan-out structure with guiding trenches in buffer layer A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die.
US09633893B2	Method to protect against contact related shorts on UTBB Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.
US09633887B2	Workpiece cutting method A workpiece cutting method is provided. The workpiece cutting method includes an attaching step of attaching an adhesive tape to the front side or back side of a workpiece, an applying step of applying a liquid resin to the front side or back side of a support member, a pressing step of superimposing the workpiece on the support member in the condition where the liquid resin and the adhesive tape come into contact with each other, and then pressing the workpiece or the support member, a fixing step of curing the liquid resin to thereby fix the workpiece to the support member, and a cutting step of cutting the workpiece fixed to the support member by using a cutting blade.
US09633885B2	Variable electrode pattern for versatile electrostatic clamp operation An electrostatic clamp (ESC) has a clamping surface, and first and second pairs of electrodes. Each of the first pair of electrodes are associated with a respective third of the clamping surface, and each of the second pair of electrodes are associated with a respective sixth of the clamping surface. A peripheral region of each of the first and second pairs of electrodes spirals toward the periphery of the clamping surface. A DC mode connects one of each of the first and second pair of electrodes to a positive and the other one of the respective first and second pair of electrodes to a negative of a power supply. An AC mode electrically connects first, second, and third phase terminals of the power supply to one of the first pair of electrodes, the other one of the first pair of electrodes, and both of the second pair of electrodes, respectively.
US09633882B2	Integrated circuits with alignment marks and methods of producing the same Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a base layer overlying a substrate, and forming an alignment mark overlying the base layer. A first layer is formed overlying the base layer and the alignment mark, and the first layer has a first layer thickness. A second layer is formed overlying the first layer, where the second layer has a second layer thickness and where a combined thickness of the first and second layer thicknesses is from about 2 to about 50 micrometers. A second component is formed from the second layer.
US09633879B2	Storage system in the ceiling space and storage method for goods thereby A storage system in a ceiling space includes overhead traveling vehicles and a traveling route for the same, a shuttle carriage configured to transport goods to and from processing devices and a traveling route for the same, an OHT port to and from which the overhead traveling vehicles and the shuttle carriage both transport goods, and buffers that are provided in the ceiling space above the processing device and are for the placement of goods by the shuttle carriage. The traveling route for the shuttle carriage enables delivery and reception of goods by the shuttle carriage between the load port of the processing devices, the buffers, and the OHT port.
US09633876B2	Selective reflectivity process chamber with customized wavelength response and method A customizable chamber spectral response is described which can be used at least to tailor chamber performance for wafer heating, wafer cooling, temperature measurement, and stray light. In one aspect, a system is described for processing a treatment object having a given emission spectrum at a treatment object temperature which causes the treatment object to produce a treatment object radiated energy. The chamber responds in a first way to the heating arrangement radiated energy and in a second way to the treatment object radiated energy that is incident thereon. The chamber may respond in the first way by reflecting the majority of the heat source radiated energy and in the second way by absorbing the majority of the treatment object radiated energy. Different portions of the chamber may be treated with selectively reflectivity based on design considerations to achieve objectives with respect to a particular chamber performance parameter.
US09633875B2	Apparatus for improving temperature uniformity of a workpiece An apparatus for improving the temperature uniformity of a workpiece during processing is disclosed. The apparatus includes a platen having a separately controlled edge heater capable to independently heating the outer edge of the platen. In this way, additional heat may be supplied near the outer edge of the platen, helping to maintain a constant temperature across the entirety of the platen. This edge heater may be disposed on an outer surface of the platen, or may, in certain embodiments, be embedded in the platen. In certain embodiments, the edge heater and the primary heating element are disposed in two different planes, where the edge heater is disposed closer to the top surface of the platen than the primary heating element.
US09633874B1	Package substrate warpage reshaping apparatus and method A warpage reshaping apparatus to reshape a warpage profile of a package substrate is disclosed. The warpage reshaping apparatus includes a metal boat, a plurality of planar boards and a plurality of spring-loaded clips. The metal boat includes a plurality of cavities. Package substrates are placed into each of the cavities. Each of the plurality of planar boards is disposed on a respective one of the package substrates. The spring-loaded clips have a first portion coupled to the metal boat and having a second portion biased against a respective one of the planar boards such that each planar board is biased against its respective package substrate. In addition to that, a method to operate the warpage reshaping apparatus is also disclosed and the manner in which the warpage reshaping apparatus changes the warpage profile of the package substrate is also disclosed.
US09633871B2	Light-emitting device To provide a highly reliable light-emitting device with less occurrence of cracks in a sealant bonding two facing substrates together. In a light-emitting device, a first substrate including a light-emitting unit, and a second substrate are bonded to each other with glass frit. A wiring in the area overlapping with a sealing material formed by melting and solidifying glass frit may be formed of a conductive material having a linear thermal expansion coefficient close to that of a substrate material. More specifically, the difference in the linear thermal expansion coefficient between the conductive material and the substrate material is 5 ppm/K or less at a temperature of 0° C. to 500° C.
US09633870B2	System and method for an improved interconnect structure Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 μm.
US09633869B2	Packages with interposers and methods for forming the same A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias.
US09633866B2	Method for patterning of laminated magnetic layer A microelectronic device is formed by forming a stack of alternating layers of a magnetic material and a dielectric material. An etch mask is formed over the magnetic laminate layer. An aqueous wet etch including 5 percent to 10 percent nitric acid, 0.5 percent to 2 percent sulphuric acid, and 0.5 percent to 3 percent hydrofluoric acid is used to etch the magnetic laminate layer where exposed by the etch mask to form a patterned magnetic laminate layer. An optional adhesion layer, if present, is also removed by the aqueous wet etch solution where exposed by the etch mask. The etch mask is subsequently removed.
US09633862B2	Semiconductor manufacturing apparatus and semiconductor manufacturing method A semiconductor manufacturing apparatus according to an embodiment includes a reactor, a mover, and a controller. The reactor houses an outer edge portion of a semiconductor substrate in inside thereof through a gap portion and scrapes the outer edge portion. The mover moves at least either the semiconductor substrate or end faces of the gap portion in a thickness direction of the semiconductor substrate to change distances in the thickness direction between the semiconductor substrate and the end faces of the gap portion. The controller controls a movement amount in the thickness direction of at least either the semiconductor substrate or the end faces of the gap portion according to a warp amount of the outer edge portion in the thickness direction.
US09633855B2	Planarization process Planarization processing methods are disclosed. In one aspect, the method includes patterning a material layer and planarizing the patterned material layer by using sputtering. Due to the patterning of the material layer, the loading requirements of nonuniformity on a substrate for sputtering the material layer are reduced, compared with that before the patterning.
US09633850B2	Masking methods for ALD processes for electrode-based devices Masking methods for atomic-layer-deposition processes for electrode-based devices are disclosed, wherein solder is used as a masking material. The methods include exposing electrical contact members of an electrical device having an active device region and a barrier layer formed by atomic layer deposition. This includes depositing solder elements on the electrical contact members, then forming the barrier layer using atomic layer deposition, wherein the barrier layer covers the active device region and also covers the solder elements that respectively cover the electrical contact members. The solder elements are then melted, which removes respective portions of the barrier layer covering the solder elements. Similar methods are employed for exposing contacts when forming layered capacitors.
US09633846B2	Internal plasma grid applications for semiconductor fabrication The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes.
US09633841B2	Methods for depositing amorphous silicon Methods for depositing an amorphous silicon layer on wafers are disclosed. A process wafer, a control wafer, and a dummy wafer may be loaded into a chamber where an amorphous silicon layer may be deposited on the process wafer. Afterwards, the process wafer and the control wafer may be removed from the chamber. The chamber and the dummy wafers are dry cleaned together. The dry cleaned dummy wafers are used in the next run for depositing amorphous silicon layer. The process may be controlled by a computer system issuing a control job comprising a first process job and a second process job, wherein the first process job is to deposit an amorphous silicon layer on the process wafer, and the second process job is to dry clean the chamber and the dummy wafer.
US09633840B2	Method of manufacturing silicon carbide semiconductor substrate and method of manufacturing silicon carbide semiconductor device A step of preparing a silicon carbide substrate (S11), a step of forming a first silicon carbide semiconductor layer on the silicon carbide substrate using a first source material gas (S12), and a step of forming a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer using a second source material gas (S13) are provided. In the step of forming a first silicon carbide semiconductor layer (S12) and the step of forming a second silicon carbide semiconductor layer (S13), ammonia gas is used as a dopant gas, and the first source material gas has a C/Si ratio of not less than 1.6 and not more than 2.2, the C/Si ratio being the number of carbon atoms to the number of silicon atoms.
US09633836B2	Methods of forming semiconductor devices including low-k dielectric layer Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges.
US09633835B2	Transistor fabrication technique including sacrificial protective layer for source/drain at contact location Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).
US09633831B2	Chemical mechanical polishing composition for polishing a sapphire surface and methods of using same A method of polishing a sapphire substrate is provided, comprising: providing a substrate having an exposed sapphire surface; providing a chemical mechanical polishing slurry, wherein the chemical mechanical polishing slurry comprises, as initial components: colloidal silica abrasive, wherein the colloidal silica abrasive has a negative surface charge; and, wherein the colloidal silica abrasive exhibits a multimodal particle size distribution with a first particle size maximum between 2 and 25 nm; and, a second particle size maximum between 75 and 200 nm; optionally, a biocide; optionally, a nonionic defoaming agent; and, optionally, a pH adjuster. A chemical mechanical polishing composition for polishing an exposed sapphire surface is also provided.
US09633830B2	Phosphor-containing coating systems and fluorescent lamps equipped therewith Coating systems suitable for use in generating fluorescent visible light, and lamps provided with such coating systems. The coating systems includes a phosphor-containing coating that contains at least a first phosphor that is predominantly excited by ultraviolet radiation of a first wavelength to emit visible light and absorbs but is less efficiently excited by ultraviolet radiation of a second wavelength. The coating system further includes a second phosphor that absorbs the ultraviolet radiation of the second wavelength and little if any of the ultraviolet radiation of the first wavelength.
US09633828B2	Ion focusing member and mass spectrometer using the same An ion focusing member includes a ball having a surface with a plurality of dimples. The ion focusing member is adapted for being disposed in a mass spectrometer in a way that the ball is located at a spray path of analyte ions and located between a metal capillary and a mass analyzer. When the analyte ions pass through the ball, the analyte ions can be gathered at a downstream position of the ball, which in turn flow into the mass analyzer by a potential difference. Therefore, the ion focusing member of the present disclosure can effectively enhance the amount of the analyte ions entering into the mass analyzer, thereby improving ion transmission efficiency. As a result, a mass spectrometer equipped with the ion focusing member may have increased signal intensity of analyte, lowered limit of detection (LOD), and minimized detection error.
US09633821B2	Microwave plasma processing apparatus and microwave supplying method Disclosed is a microwave plasma processing apparatus including: a processing container configured to define a processing space; a microwave generator configured to generate microwaves; a distributor configured to distribute the microwaves to a plurality of waveguides; an antenna installed in the processing container and to radiate the microwaves distributed to the plurality of waveguides to the processing space; a monitor unit configured to monitor a voltage of each of the plurality of waveguides; a storage unit configured to store a difference between a monitor value of the voltage monitored by the monitor unit and a predetermined reference value of the voltage and a control value of a distribution ratio of the distributor corresponding to the difference; and a control unit configured to acquire the control value of the distribution ratio of the distributor from the storage unit and to control the distribution ratio of the distributor.
US09633820B2	Method for forming resist film and charged particle beam writing method In a method for forming a resist film, a first resist film is formed on a light shielding film formed on a substrate, by using a spin coating method. A protective film is formed on the first resist film. The protective film and the first resist film are simultaneously removed at the same region to expose a portion of the light shielding film. A first region in which the second resist film is formed on the light shielding film and a second region in which the second resist film is formed on the first resist film through the protective film, are provided. The protective film and the second resist film are simultaneously removed in the second region to expose the first resist film. A region in which the first resist film, and a region in which the second resist film, is formed, are separately provided on the substrate.
US09633819B2	Microscopy imaging method and system Generally, the present disclosure provides a method and system for improving imaging efficiency for CPB systems while maintaining or improving imaging accuracy over prior CPB systems. A large field of view image of a sample is acquired at a low resolution and thus, at high speed. The low resolution level is selected to be sufficient for an operator to visually identify structures or areas of interest on the low resolution image. The operator can select one or more small areas of arbitrary shape and size on the low resolution image, referred to as an exact region of interest (XROI). The outline of the XROI is mapped to an x-y coordinate system of the image, and the CPB system is then controlled to acquire a high resolution image of only the XROI identified on the low resolution image. For 3D imaging, once the XROI is identified, each section of the sample can be iteratively imaged in the previously described manner, with the operator having the option to redefine the XROI later.
US09633817B2	Diaphragm mounting member and charged particle beam device Conventional devices have been difficult to use due to insufficient consideration being given to factors such as the cost necessary for diaphragm replacement and the convenience of the work. In the present invention, a diaphragm mounting member installed in a charged particle beam device for radiating a primary charged particle beam through a diaphragm separating a vacuum space and an atmospheric pressure space onto a sample placed in the atmospheric pressure space is provided with a diaphragm installation portion to which a TEM membrane is mounted and a casing fixing portion mounted on a casing of the charged particle beam device. The diaphragm installation portion has a positioning structure for positioning a platform on which the diaphragm is held.
US09633812B1	Triode tube emulator circuit Various examples are directed to analog vacuum tube emulator circuits. In various examples, a vacuum tube emulator circuit may comprise a first circuit and a second circuit. The first circuit may be effective to receive, a first voltage, a second voltage, and a third voltage. The first circuit may be effective to develop, at an input of the first circuit, a first current based on the first voltage, the second voltage, and the third voltage. The first circuit may output the first current to an output node. The second circuit may be effective to receive the first voltage, the second voltage, and the third voltage. The second circuit may be effective to develop, at an input of the second circuit, a second current based on the first voltage, the second voltage, and the third voltage. The second circuit may output the second current to the output node.
US09633811B2	Circuit breaker for hierarchically controlling short-circuit current and trips The invention discloses a short circuit current hierarchical control tripping parameter circuit breaker. According to the invention, resistance of an alloy magnetic resistance body is changed through circuit current, and contract control can be carried out on short-circuit current. The control range of the circuit breaker can achieve that no magnetic resistance will be generated when current is no more than 8 times of rated operational current, and current limiting may be realized by the magnetic resistance when current is 8 times more than rated value. In this way, hierarchical control on short-circuit current of different levels of circuits can be carried out, and short-circuit current can be limited in a predetermined range, thereby restricting the short-circuit current in a predetermined range, solving a problem of power supply flickering, and avoiding large-area power failure accidents caused by override trip existing in an electrical control switch.
US09633807B2	Modular solid dielectric switchgear Modular switchgear and methods for manufacturing the same. The modular switchgear includes a vacuum interrupter assembly, a source conductor assembly, and a housing assembly. The vacuum interrupter assembly includes a bushing, a fitting, and a vacuum interrupter at least partially molded within the bushing and including a movable contact and a stationary contact. The source conductor assembly includes a bushing, a fitting, and a source conductor molded within the bushing. The housing assembly includes a housing defining a chamber and a drive shaft and conductor positioned within the chamber. The housing assembly also includes a first receptacle for receiving the fitting of the vacuum interrupter assembly and a second receptacle for receiving the fitting of the source conductor assembly. The vacuum interrupter assembly, the source conductor assembly, and the housing assembly are coupled without molding the assemblies within a common housing.
US09633805B2	Pushbutton switch A pushbutton switch includes a pushbutton unit and a resilient member. The pushbutton unit includes a mounting seat for being in proximity to an activator of a switch assembly, and a pushbutton covering the mounting seat. The resilient member has a switch contactor adjacent to the activator, two resilient arms extending from the switch contactor, and two abutment segments connected respectively to the resilient arms and engaging the limiting seat. When the pushbutton is pressed to move toward the limiting seat, the resilient arms are resiliently deformed to have a resilient force for urging the pushbutton away from the limiting seat, and the switch contactor is driven by the pushbutton to contact and move the activator.
US09633804B2	Electrical connector having a domed metal switch A connector (100) and connector system are provided. A connector can include a domed metal switch (102) that is partially covered with a liquid impermeable barrier (101) such that a portion of the domed metal switch is exposed and the liquid impermeable barrier is coupled to the domed metal switch with a liquid impermeable junction (221). In a connector system, a complementary connector can include a dome switch actuator (706,707), partially covered with another liquid impermeable barrier. When pressed against the connector, the domed metal switch can deform to contact an electrical conductor (104). A control circuit (1309) can determine whether an electronic device or user is causing the deformation by detecting whether voltage or current is applied to the domed metal switch while deformed.
US09633800B1	Key structure A key structure includes a base, a keycap, a first longitudinal bar, a second longitudinal bar, a first transverse bar and a second transverse bar. The first longitudinal bar, the second longitudinal bar, the first transverse bar and the second transverse bar are uniformly distributed in the range of the keycap. Consequently, the keycap is stably moved relative to the base. The first longitudinal bar, the second longitudinal bar, the first transverse bar and the second transverse bar are made of a metallic material. Since these bars are thinner than the scissors-type connecting element of the conventional key structure, the key structure of the present invention has reduced thickness. Moreover, since these bars are made of the metallic material, the structural strength of the key structure is increased.
US09633798B2	Atomic capacitor This invention describes a capacitor that formed by a charge or species specific membrane material filled with aqueous or non-aqueous liquid with soluble salts dissolved and non-dissolved in solution and contained within the membrane material. When charged, the oppositely charged ion will leave the structure, leaving behind a charged atomic capacitor.
US09633794B2	Capacitor module of inverter for vehicle A capacitor module of an inverter for a vehicle includes: a DC-link capacitor configured to be connected in parallel to an input of an inverter between a first high voltage input terminal and a second high voltage input terminal; and a plurality of Y-capacitors configured to be connected in parallel to the inverter. Each of the plurality Y-capacitors includes a first capacitor element connected between the first high voltage input terminal and a ground bus bar and a second capacitor element connected between the second high voltage input terminal and the ground bus bar, and the ground bus bars of the plurality of Y-capacitors are separately provided and the ground holes of the ground bus bars are disposed so as to face each other in a first direction.
US09633790B1	Multilayer ceramic capacitor and board having the same A multilayer ceramic capacitor has a 3-terminal, vertical, multilayer structure in which portions of lead portions are not covered by external electrodes but are exposed to a mounting surface of a ceramic body. Insulating portions are disposed between the external electrodes on the mounting surface of the ceramic body. The insulating portions have an overlap portion covering portions of the external electrodes. 0.005≦i/e≦0.7 is satisfied, where i is a width of the overlap portion, and e is a width of the external electrode partially covered by the overlap portion.
US09633788B2	Multilayer ceramic capacitor A multilayer ceramic capacitor includes a ceramic body and external electrodes provided on opposite end surfaces of the ceramic body. The ceramic body includes an inner layer portion including a plurality of ceramic layers defining inner layers and a plurality of first and second internal electrodes each disposed at an interface of adjacent ones of the ceramic layers defining the inner layers, outer layer portions sandwiching the inner layer portion in a direction in which the layers are stacked, and side margin portions sandwiching the inner layer portion and the outer layer portions in a widthwise direction. The side margin portion includes pores that decrease in number along a direction from inside to outside of the ceramic body.
US09633784B2	Electronic component In an electronic component, a first terminal electrode is disposed on a first side surface and extends to a second principal surface. A second terminal electrode is disposed on a second side surface and extends to the second principal surface. A third terminal electrode is disposed on a third side surface and extends to the second principal surface. A fourth terminal electrode is disposed on a fourth side surface and extends to the second principal surface. Maximum values of thicknesses of portions located on the second principal surface of the third and fourth terminal electrodes are smaller than maximum values of thicknesses of portions located on the second principal surface of the first and second terminal electrodes.
US09633783B2	Transmission of signals through a non-contact interface A bi-directional transmission system for transmission of signals through a non-contact interface includes a transformer inductively coupling a first circuit to a second circuit. The second circuit includes at least a first transmitter circuit arranged to translate a first digital input signal into at least one voltage pulse and to provide the at least one voltage pulse to a first winding of the transformer, wherein the at least one voltage pulse takes a positive or negative form based on whether the first digital input signal has a positive or negative edge. The first circuit includes at least a first receiver circuit arranged to receive at least one induced voltage pulse from a second winding of the transformer and to provide a first digital output signal reflecting the first digital input signal based on the at least one induced voltage pulse.
US09633781B2	Ferroresonant transformer for use in uninterruptible power supplies A ferroresonant transformer is adapted to be connected to a primary power source, an inverter system, and a resonant capacitor. The ferroresonant transformer comprises a core, a main shunt arranged to define a primary side and a secondary side of the ferroresonant transformer, first windings arranged on the primary side of the ferroresonant transformer, second windings arranged on the secondary side of the ferroresonant transformer, and third windings arranged on the secondary side of the ferroresonant transformer. The first windings are operatively connected to the primary power source.
US09633775B2	Electronic device mounting apparatus An electronic device mounting apparatus to be mounted with multiple electronic components, each of which includes at least one wire. The electronic device mounting apparatus includes a base unit and multiple pin units. The base unit includes a base wall and two side walls extending from the base wall. Each of the side walls has a first surface. The pin units are correspondingly mounted in the side walls and are spaced apart from one another. Each of the pin units has a wire-connecting segment having a connection portion that projects from the first surface, and two projecting portions that project from the connection portion and that define a slit therebetween. The slit is for a corresponding wire to be clamped therein by the projecting portions.
US09633773B2	Thin film common mode filter and method of manufacturing the same Disclosed herein are a thin film common mode filter and a method of manufacturing the same. The thin film common mode filter according to the exemplary embodiment of the present invention includes a magnetic substrate made of a magnetic ceramic material; and coil patterns formed on the magnetic substrate, wherein external electrodes connected with the coil patterns are sequentially stacked and insulating layers formed on and beneath the coil pattern are made of a composite of ferrite powder and thermosetting resin.
US09633772B2	Solderable planar magnetic components An inductive component having a printed circuit board (“PCB”) with a first side and a second side. An aperture extends through the PCB and a conductive winding is printed onto the PCB surrounding the aperture. A core is formed by a first core member and a second core member. The first core member includes a first base member with at least one joining surface which is solderable to the first side. A first core leg extends at least partially through the aperture. The second core member includes at least a second base member and is coupled to the first core member or the second side. To manufacture the PCB, the first core member is soldered to the first side and then the PCB is inverted. The second core member is then coupled to at least one of the first core member or the second side.
US09633771B2	Magnetic coupling device A magnetic attachment comprises a stacked configuration including an attachment surface, a magnetic coupling device, and a device comprising at least one magnet. A thin non-conductive sheet may be positioned between the magnetic coupling device and the at least one magnet. The magnetic coupling device may include an aperture through which radio signals may pass. The magnetic coupling device may comprise alternating layers of magnetically permeable material and non-magnetically permeable material. The magnetic coupling device may have an adhesive backing layer and may be provided in a kit for a user to apply to a device. The embedded coupling device may be configured within the shell of a host device, or within a cover of a device.
US09633770B2	Method for improving coercive force of epsilon-type iron oxide, and epsilon-type iron oxide An epsilon-type iron oxide having an Fe-site that is substituted with a platinum group element, provided that Fe of a D-site of the epsilon-type iron oxide is not substituted with the platinum group element.
US09633767B2	Power cable polymer connector [Problem]A power cable polymer connector is provided which is lighter than when using a porcelain insulator and can exert a free-standing property to maintain the arranged position even if it is used horizontally. [Solution]A power cable polymer connector 1 includes a polymeric insulating tube 2 including a cable insertion hole 2a, 2b to allow an insertion of a stripped end 101 of a power cable 100. The polymeric insulating tube 2 further includes an insulation 20 including a polymer-based material and an embedded pipe 21 including a metal and embedded on an inner peripheral surface of the insulation 20 so as to face the end of the power cable 100.
US09633763B2	Wire harness and connector component Provided is a wire harness that enables a connector component and a cable bundle to be attached to an external member while facilitating the operation and preventing wobbling of the connector component. The connector component is connected to a cable branch line on the radially outward side of the cable bundle, and includes a pair of confining surfaces on each of two sides in the circumferential direction of the cable bundle. The pair of confining surfaces face each other across a gap. The bundling member is disposed between the pair of confining surfaces, and is wound around the connector component and the cable bundle together from the outer side. The fixture is fixed to the bundling member and to an external member.
US09633761B2	Center conductor tip A tip end conductor for an inner conductor of a coaxial cable, comprising a first portion engaging a first region of the outermost tip to mechanically engage the inner conductor and a second portion, axially inboard of the first portion, engaging a second region of the outermost tip to electrically engage the inner conductor. The first and second portions define first and second diameter dimensions, respectively, wherein the first diameter dimension is less than the second diameter dimension, and wherein the first portion of the tip end conductor includes a mechanically irregular surface for being press fit onto, and producing, a mechanical interlock along a first region of the terminal end of the inner conductor.
US09633754B2	Apparatus for generating focused electromagnetic radiation A method for generating electromagnetic radiation, including the steps of: providing a series of adjacent electrode pairs arranged on a common dielectric substrate, the electrodes of each electrode pair substantially aligned on opposite sides of the common dielectric substrate; energizing a first electrode pair in the series of electrode pairs at an energizing time to produce a volume polarization distribution pattern within the common dielectric substrate; energizing a next adjacent electrode pair in the series of adjacent electrode pairs at a next energizing time to produce a variation of the volume polarization distribution pattern within the common dielectric substrate, the center of the next adjacent electrode pair located a distance from the center of the previous adjacent electrode pair, wherein the next energizing time is a time interval after the previous energizing time, the time interval less than the time for light to travel the distance between the centers of the previous and the next adjacent electrode pairs; and repeating the step of energizing the next adjacent electrode pair for subsequent electrode pairs in the series of adjacent electrode pairs to produce a continuous time-varying volume polarization distribution pattern within the common dielectric substrate.
US09633753B2	Mobile transport and shielding apparatus for removable x-ray analyzer A mobile transport and shielding apparatus, which holds an x-ray analyzer for transport between operating sites, and also serves as a shielded, operational station for holding the x-ray analyzer during operation thereof. The x-ray analyzer is removably insertable into the apparatus and is operable either within the mobile transport and shielding apparatus, or outside of the apparatus. The apparatus may provide means to control, power, cool, and/or charge the x-ray analyzer during operation of the analyzer; and also means to transport the analyzer (e.g., a handle).
US09633752B2	Reactor shutdown trip algorithm using derivatives A controller for producing a nuclear reactor shutdown system trip signal in response to at least one detector signal. The controller includes a signal conditioning module receiving the at least one detector signal and outputting a measured flux signal. A rate module generates a rate signal from the measured flux signal. A comparator circuit compares the rate signal to a trip setpoint and generates a first trip signal.
US09633747B2	Semiconductor memory devices and methods of testing open failures thereof Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The data I/O unit selectively drives a first global I/O line and first/second global I/O lines according to the first or second test modes. The data transmitter selectively transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line, and the data on the first and second global I/O lines onto the first and second local I/O lines according to the first or second test modes.
US09633744B2	On demand knockout of coarse sensing based on dynamic source bounce detection Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold.
US09633743B2	Method of shaping a strobe signal, a data storage system and strobe signal shaping device A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal.
US09633740B1	Read retry operations where likelihood value assignments change sign at different read voltages for each read retry Read retry operations in a memory employ likelihood value assignments that change sign at different read voltages for a plurality of read retry operations. A method for multiple read retries of a memory comprises reading a codeword using a first read voltage to obtain a first read value; mapping the first read value to first likelihood values based on a first likelihood value assignment that changes sign substantially at the first read voltage; reading the codeword using a second read voltage to obtain a second read value, wherein the second read voltage is shifted from the first read voltage to compensate for an expected change in analog voltages; and mapping the second read value to second likelihood values based on a second likelihood value assignment, wherein the second likelihood value assignment changes sign substantially at the second read voltage. Read data is optionally generated using iterative decoding of the codeword based on the first likelihood values and/or the second likelihood values.
US09633739B2	Method of erasing information and device for performing same Methods and devices for erasing information stored on an electronic semiconductor component in a plurality of non-volatile memory elements are described. Irradiating the semiconductor component with erasing radiation until a target dose has been absorbed by the semiconductor component, the erasing radiation penetrating the semiconductor component, results in an ionization effect which influences the concentration of the charge carriers stored on the memory elements such that a statistical distribution of the threshold voltages of the memory elements forms a contiguous region.
US09633737B2	Semiconductor device A semiconductor device includes a plurality of memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages; and an operation circuit configured to output operating voltages to local lines of a selected memory block, among the plurality of memory blocks, to perform a program operation, a read operation and an erase operation on the selected memory block, wherein the operation circuit is configured to apply a dummy pulse having a positive potential to the local lines of the selected memory block after completing the program operation, the read operation and the erase operation.
US09633732B2	Semiconductor memory device and operating method thereof A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and a source line precharge path. The memory cell array may have a plurality of memory strings. The peripheral circuit may perform a program operation for the memory cell array. The control logic may control the peripheral circuit a channel precharge operation of the program operation. The source line precharge path may precharge channels of the plurality of memory strings through a source line of the memory cell array. The peripheral circuit may control, according to program data, a potential level of a selected one of a plurality of bit lines coupled to the plurality of memory strings during the channel precharge operation.
US09633728B2	Memory systems and memory programming methods Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.
US09633727B2	Resistive memory devices and methods of controlling resistive memory devices according to selected pulse power specifications A method of controlling a resistive memory device includes: accessing a first pulse power specification satisfying a memory cell coefficient associated with at least a first of a plurality of memory cells included in a memory cell array; generating a first pulse power according to the accessed first pulse power specification; and performing a write operation on at least the first of the plurality of memory cells using the generated first pulse power.
US09633726B2	Resistive memory device, resistive memory system, and method of operating resistive memory device A method of operating a resistive memory device having a plurality of word lines and a plurality of bit lines includes selecting one or more first memory cells connected to a first bit line, selecting one or more second memory cells connected to a second bit line, and simultaneously performing a reset write operation on the first and second memory cells using a first write driver.
US09633724B2	Sensing a non-volatile memory device utilizing selector device holding characteristics Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory.
US09633716B2	Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase.
US09633712B1	Semiconductor memory device capable of performing read operation and write operation simultaneously A semiconductor memory device includes a charge storage element, a read transistor, and a write transistor. The charge storage element is for preserving a first data voltage. The read transistor has a first terminal coupled to the charge storage element, a second terminal coupled to a read bit line, and a control terminal coupled to a read word line. The write transistor has a first terminal coupled to the first terminal of the read transistor, a second terminal coupled to a write bit line, and a control terminal coupled to a write word line. The semiconductor memory device is able to perform a read operation and a write operation to the charge storage element simultaneously through the read transistor and the write transistor.
US09633710B2	Method for operating semiconductor device Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.
US09633705B2	Semiconductor memory device, memory system and access method to semiconductor memory device A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array from which a page is to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array.
US09633702B2	Memory system with uniform decoder and operating method of same A memory system includes a memory array including a plurality of memory cells, and an encoder operatively coupled to the memory array, for encoding an original data element to be programmed into the memory cells into a uniform data element in which the number of “0”s approximately equals the number of “1”s.
US09633696B1	Systems and methods for automatically synchronizing media to derived content A system for creating synchronized content is provided. The system includes a memory, at least one processor coupled to the memory, and a synchronization engine component executable by the at least one processor. The synchronization engine component is configured to locate a media file associated with synchronization information; locate at least one clip derived from the media file; generate a reference template representative of the media file; generate a derived content template representative of the at least one clip; align the derived content template with the reference template to create alignment information; and generate the synchronized content based on the at least one clip, the alignment information, and the synchronization information.
US09633692B1	Continuous loop audio-visual display and methods An audiovisual work displaying a real world setting or object repeats as a video loop such that a viewer having normal visual and cognitive ability is unlikely or unable to detect the loop. The work is devoid of or has minimal instances of outliers which are otherwise more readily detected by a viewer upon successive looping of the segment. The segment may be of different lengths and optionally includes a corresponding audio component. The work is displayed on any type of screen for viewing, and may be delivered via the cloud, as a subscription, or other means. The display allows for a unique sensation where the viewer is locked in time (such as when viewing a still image) yet experiences video motion and audio variety without the sense of being caught in a continuous loop.
US09633686B1	Disc storage cassettes A disc cassette includes a curved portion configured to hold multiple discs and a platform portion abuts the curved portion. The platform portion and the curved portion each include multiple rib pairs configured to separate adjacent discs from touching one another, and to form a disc slot between each rib pair. Disc slots of the platform portion of the disc cassette are configured to provide a guide for disc removal from the disc cassette.
US09633685B2	Method of writing to an optical data storage medium, method of reading from an optical data storage medium, and optical data storage medium According to embodiments of the present invention, a method of writing to an optical data storage medium is provided. The method includes receiving a plurality of data elements, each data element having one of a plurality of values, wherein each value of the plurality of values is associated with a wavelength, and forming, for each data element, a nanostructure arrangement on the optical data storage medium, the nanostructure arrangement configured to reflect light of the wavelength associated with the value of the data element in response to a light irradiated on the optical data storage medium. According to further embodiments of the present invention, a method of reading from an optical data storage medium and an optical data storage medium are also provided.
US09633684B2	Magnetic recording medium, method for manufacturing magnetic recording medium, and magnetic recording/reproduction apparatus According to one embodiment, a magnetic recording medium includes a silicon oxide underlayer having a recess pattern having a plurality of recesses, a nonmagnetic underlayer having a first hole pattern having a plurality of holes corresponding to the recess pattern, and a magnetic recording layer having a second hole pattern having a plurality of holes connected with the first hole pattern. The silicon oxide underlayer, the nonmagnetic underlayer, and the magnetic recording layer are formed in order on the substrate.
US09633683B2	Mode conversion via tapered waveguide An apparatus includes a write head comprising a near-field transducer at a media-facing surface of the write head and a waveguide extending along a light-propagation direction. The waveguide is configured to receive light emitted from a light source at a fundamental transverse electric mode. The waveguide is configured to deliver the light to the near-field transducer at a transverse magnetic mode which directs surface plasmons to a recording medium in response thereto. The waveguide comprises a core with first and second tapers separated by a straight portion of constant cross sectional width. The first and second tapers successively decrease a cross-sectional width of the core as it nears the near-field transducer. The waveguide includes an end portion between the second taper and the near field transducer. The end portion comprises a top cladding layer, aside cladding layer, and a bottom cladding layer on the side cladding layer.
US09633682B1	Accurate spiral gate positioning in the presence of large non-repeatable runout A magnetic write head is positioned based on position signals generated by a read head as the read head crosses a plurality of reference spirals. The spiral gate for monitoring a particular reference spiral is timed to begin at a time based on the radial position of the magnetic head when crossing the preceding reference spiral. In this way, the spiral crossing time for the particular reference spiral can be estimated with sufficient accuracy that the spiral gate coincides with the magnetic head crossing the particular reference spiral. Consequently, spiral detection is assured, even in the presence of large non-repeatable runout.
US09633675B2	Interlaced magnetic recording super parity A storage device includes a storage medium having a first set of non-adjacent data tracks having a number of super parity sectors and a second set of non-adjacent data tracks interlaced with the first set of non-adjacent data tracks. The number of super parity sectors on a data track of the first set of non-adjacent data tracks is selected based on a distance between the data track and an inner diameter of the storage medium.
US09633674B2	System and method for detecting errors in interactions with a voice-based digital assistant The method is performed at an electronic device with one or more processors and memory storing one or more programs for execution by the one or more processors. A speech input containing a request is received from a user. At least one action in furtherance of satisfying the request is performed. A user interaction is detected, such as a speech input to a digital assistant or a physical interaction with a device. It is determined whether the user interaction is indicative of a problem in the performing of the at least one action. Upon determining that the user interaction is indicative of a problem, information relating to the request is stored in a repository for error analysis.
US09633668B2	System and method of improving communication in a speech communication system A speech communication system and a method of improving communication in such a speech communication system between at least a first user and a second user may be configured so the system (a) transcribes a recorded portion of a speech communication between the at least first and second user to form a transcribed portion, (b) selects and marks at least one of the words of the transcribed portion which is considered to be a keyword of the speech communication, (c) performs a search for each keyword and produces at least one definition for each keyword, (d) calculates a trustworthiness factor for each keyword, each trustworthiness factor indicating a calculated validity of the respective definition(s), and (e) displays the transcribed portion as well as each of the keywords together with the respective definition and the trustworthiness factor thereof to at least one of the first user and the second user.
US09633667B2	Adaptive audio signal filtering An apparatus comprising: an audio signal analyzer configured to analyze an audio signal; an audio signal processor configured to signal process the audio signal to enhance the speech component of the audio signal dependent on determining the audio signal comprises speech components; and signal processing the audio signal to enhance a loudness of the audio signal otherwise.
US09633666B2	Method and apparatus for detecting correctness of pitch period A method and an apparatus for detecting correctness of a pitch period. The method for detecting correctness of a pitch period includes determining, according to an initial pitch period of an input signal in a time domain, a pitch frequency bin of the input signal, where the initial pitch period is obtained by performing open-loop detection on the input signal; determining, based on an amplitude spectrum of the input signal in a frequency domain, a pitch period correctness decision parameter, associated with the pitch frequency bin, of the input signal; and determining correctness of the initial pitch period according to the pitch period correctness decision parameter. The method and apparatus for detecting correctness of a pitch period according to the embodiments of the present invention can improve, based on a relatively less complex algorithm, accuracy of detecting correctness of a pitch period.
US09633654B2	Low power voice detection Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.
US09633653B1	Context-based utterance recognition In some implementations, a digital work provider may provide language model information related to a plurality of different contexts, such as a plurality of different digital works. For example, the language model information may include language model difference information identifying a plurality of sequences of one or more words in a digital work that have probabilities of occurrence that differ from probabilities of occurrence in a base language model by a threshold amount. The language model difference information corresponding to a particular context may be used in conjunction with the base language model to recognize an utterance made by a user of a user device. In some examples, the recognition is performed on the user device. In other examples, the utterance and associated context information are sent over a network to a recognition computing device that performs the recognition.
US09633648B2	Loudspeaker membrane and method for manufacturing such a membrane The invention relates to a loudspeaker membrane having a sandwich structure, having a central web separating two layers of material based on high-rigidity threads impregnated with a polymer resin, characterized in that the central web is formed from a layer of material based on oriented natural fibers that are impregnated with a polymer resin.
US09633647B2	Self-tuning transfer function for adaptive filtering The technology described in this document can be embodied in a computer-implemented method that includes receiving, at one or more processing devices, a plurality of values representing a set of coefficients of an adaptive filter over a period of time, and identifying, by the one or more processing devices based on the plurality of values, a phase error associated with a transfer function of the adaptive filter. The method also includes adjusting, based on the identified phase error, a phase associated with the transfer function of the adaptive filter such that coefficients calculated using the adjusted transfer function reduce the phase error. The method further includes determining a set of coefficients for the adaptive filter based on the adjusted transfer function, and programming the adaptive filter with the determined set of coefficients to enable operation of the adaptive filter.
US09633646B2	Oversight control of an adaptive noise canceler in a personal audio device A personal audio device, such as a wireless telephone, includes an adaptive noise canceling (ANC) circuit that adaptively generates an anti-noise signal from a reference microphone signal and injects the anti-noise signal into the speaker or other transducer output to cause cancellation of ambient audio sounds. An error microphone is also provided proximate the speaker to measure the ambient sounds and transducer output near the transducer, thus providing an indication of the effectiveness of the noise canceling. A processing circuit uses the reference and/or error microphone, optionally along with a microphone provided for capturing near-end speech, to determine whether the ANC circuit is incorrectly adapting or may incorrectly adapt to the instant acoustic environment and/or whether the anti-noise signal may be incorrect and/or disruptive and then take action in the processing circuit to prevent or remedy such conditions.
US09633642B2	Electronic musical instrument system Provided is an electronic musical instrument system. A PC is configured to perform an operation of emulating an analog synthesizer by a first software synthesizer. The PC installs a second software synthesizer to a hardware synthesizer on condition that the hardware synthesizer is confirmed to be the device corresponding to the second software synthesizer. The hardware synthesizer performs the operation of emulating the analog synthesizer by the second software synthesizer. The first software synthesizer and the second software synthesizer related to the operation of emulating the analog synthesizer have the same function respectively, and are capable of generating the same tone respectively, the effect of reproducing the same function and tone as the synthesizer that is to be emulated can be achieved respectively in two different devices, i.e. the PC and the hardware synthesizer.
US09633640B1	Guitar effector Provided is an adjustment unit for guitar effector that is installed between input unit and output unit to adjust a volume and a tone based on the output signal by using a variable resistor in an analog circuit. The adjustment unit comprises one or more of a level part that adjusts a size of the output signal, a tone part that adjusts an amount of high-pitched sound and an amount of low-pitched sound, and a distortion part that adjusts a degree of distortion, one or more of the level part, the tone part and the distortion part are plural, and a switch comprising one or more of a level switch for selecting any one of the plurality of level parts, a tone switch for selecting any one of the plurality of tone parts, and a distortion switch for selecting any one of the plurality of distortion parts is installed.
US09633637B1	Magnetic resonance tuning device for stringed instruments A tuning device and method for tuning or verifying the tuning of a string of a stringed instrument is provided. The device includes an electromagnetic pickup physically separate from the stringed instrument. The electromagnetic pickup is a noise cancelling pickup. The electromagnetic pickup ultimately provides an electrical signal indicative of a movement of the string in a magnetic field of the electromagnetic pickup to a processor electronic tuner. Optional features of the electromagnetic pickup increase the effective range of the pickup.
US09633631B1	Foldable guitar A foldable guitar has a guitar body. The guitar body includes a main body and a rotating bar fixed to the main body. The rotating bar has a top end and a bottom end. Each of the top end and the bottom end is pivoted to the main body. A shape of the rotating bar matches a profile shape of the main body, and the rotating bar is foldable, such that a size of the guitar body is reduced when the rotating bar is folded toward the main body.
US09633627B2	Power supply, power control method thereof, and display apparatus having the same A power supply and method of controlling power supplied to a light source are disclosed. The power supply includes a dimming-control voltage generator configured to generate a dimming-control voltage based on first and second adjustment values; a dimming controller configured to output a dimming control signal for controlling analog dimming and pulse width modulation (PWM) dimming of a light source based on the dimming-control voltage; and a driver configured to control the analog dimming and the PWM dimming of the light source based on the dimming control signal.
US09633624B2	Data processing apparatus for transmitting/receiving compression-related indication information via display interface and related data processing method A data processing apparatus has a de-compressor and an input interface. The de-compressor de-compresses a compressed display data in an input bitstream. The input interface receives the input bitstream from another data processing apparatus via a display interface, parses indication information included in the input bitstream, and configures the de-compressor to employ a de-compression algorithm according to the indication information.
US09633622B2	Multi-user sensor-based interactions Disclosed in some examples are methods systems and machine readable mediums in which actions or states of a first user (e.g., natural interactions) having a first corresponding computing device are observed by a sensor on a second computing device corresponding to a second user. A notification describing the observed actions or states of a first user may be shared across a network with the first corresponding computing device. In this way, the first computing device may be provided with information concerning the state of the user without having to directly sense the user.
US09633621B2	Source driving circuit capable of compensating for amplifier offset, and display device including the same A display device capable of decreasing an amplifier offset using a gate-start pulse signal is disclosed. A display device includes a display panel, a control circuit, a gate driving circuit and a source driving circuit. The source driving circuit includes a plurality of source driving chips, compensates for an amplifier offset in response to the gate-start pulse signal, performs digital-to-analog (D/A) conversion on data received from the control circuit using gray scale voltages in response to the source control signal, and provides the converted data to the source lines.
US09633620B2	GOA circuit and liquid crystal display device The invention provides a GOA circuit and a liquid crystal display device each including multiple cascade connected GOA units. An nth-stage GOA unit is for charging an nth-stage horizontal scan line in a display area. The nth-stage GOA unit includes a pull-up control circuit, a pull-up circuit, a transfer circuit, a first pull-down control circuit, a first pull-down circuit, a second pull-down control circuit, a second pull-down circuit and a main pull-down circuit, where n is a positive integer. The invention can improve the stage-transfer efficiency of GOA circuit, improve the output quality of scan drive signal so as to increase charging ratio of LCD tubes and also can accelerate the pull-down speed of scan drive signal.
US09633611B2	Readiness signaling between master and slave controllers of a liquid crystal display A liquid crystal display includes a liquid crystal panel and a first to nth control substrates (n is an integer which is 2 or greater) which control the liquid crystal panel. When the first control substrate enters an operable status, the first control substrate transmits a readiness signal to the second control substrate which is at a next stage, and when the nth control substrate determines that the nth control substrate receives a readiness signal from a control substrate at a previous stage and is in an operable status, the nth control substrate transmits a readiness signal to the first control substrate, thereby being able to suppress a synchronization failure between the plurality of control substrates which are provided in a liquid crystal display.
US09633607B1	Adaptive RGBW conversion The subject matter disclosed herein relates to conversion of RGB image data into RGBW image data for display by an image display apparatus. The image display apparatus accesses Red Green Blue (RGB) image data that corresponds to one or more images to be displayed by a Red Green Blue White (RGBW) display of the image display apparatus. The image display apparatus receives one or more inputs. Based upon the one or more external factors, the RGB image data is converted into RGBW image data. Based upon the RGBW image data, the RGBW display displays the one or more images.
US09633606B2	Device for driving light-emitting diodes, light-emitting device, and display device A device for driving a light-emitting diode, a light-emitting device, and a display device are disclosed. The disclosed light-emitting diode driving device may include: a first transistor having a first conductive electrode connected with a source voltage terminal and having a second conductive electrode connected with an input terminal of the light-emitting diode; a second transistor having a control electrode connected with the second conductive electrode of the first transistor; and a capacitor having one end connected with a data voltage terminal and having the other end connected with a first node, which is connected with a control electrode of the first transistor and with a first conductive electrode of the second transistor.
US09633605B2	Pixel circuit having driving method for threshold compensation and display apparatus having the same A pixel circuit includes a first path coupled to a gate of a driving transistor and a second path passing through a source and drain of the driving transistor. An initialization voltage of the driving transistor is set based on a gray scale data voltage carried along the first path. A voltage is stored in a capacitor coupled to the gate of the driving transistor based on the gray scale data voltage carried along the second path. The voltage stored in the capacitor is based on the gray scale data voltage, and may be compensated for variation in a threshold voltage of the driving transistor.
US09633604B2	Display device, method for driving display device, and electronic apparatus Provided is a display device including a pixel array unit that is made by arranging a drive transistor to drive a light emitting unit, a sampling transistor to sample a signal voltage, and a pixel circuit having a storage capacitor to store the signal voltage which is written by sampling with the sampling transistor, and a drive unit that makes a gate node and a source node of the drive transistor be in a floating state up to performing writing of the signal voltage with the sampling transistor, after writing an initialization voltage in the gate node when the source node of the drive transistor is in a non-floating state.
US09633599B2	Pixel circuit, display device including the same and driving method of the display device A pixel circuit is capable of maintaining a display quality even in cases where an input transistor has a low mobility, or where it is impossible to take a sufficient selection period for each scanning line. A pixel circuit includes an organic EL element (OLED), transistors, and a capacitor. A drive transistor has its drain terminal connected to a HIGH level power supply line, and has its source terminal connected to an anode terminal of the OLED. The first input transistor has its gate terminal connected to a scanning line Si, and is disposed between a data line Dj and the gate terminal of the drive transistor. The second input transistor has its gate terminal connected to a scanning line (Si−1) in the (i−1)th row, and is disposed between a data line and the gate terminal of the drive transistor. The capacitor is disposed between the gate terminal and the source terminal of the drive transistor.
US09633598B2	Pixel circuit and driving method thereof A method for driving a display device includes driving a first pixel circuit based on first and second fields of a frame, and driving a second pixel circuit based on first and second fields of the frame. The first field of the first pixel circuit overlaps the second field of the second pixel circuit. The second field of the first pixel circuit overlaps the first field of the second pixel circuit. Operations performed in the first field include storing a gray scale data voltage, and operations performed in the second field include supplying an amount of current to a light emitter based on the stored gray scale data voltage. The first and second pixel circuits are in adjacent rows of the display device.
US09633597B2	Stable driving scheme for active matrix displays A method and system for operating a pixel array having at least one pixel circuit is provided. The method includes repeating an operation cycle defining a frame period for a pixel circuit, including at each frame period, programming the pixel circuit, driving the pixel circuit, and relaxing a stress effect on the pixel circuit, prior to a next frame period. The system includes a pixel array including a plurality of pixel circuits and a plurality of lines for operation of the plurality of pixel circuits. Each of the pixel circuits includes a light emitting device, a storage capacitor, and a drive circuit connected to the light emitting device and the storage capacitor. The system includes a drive for operating the plurality of lines to repeat an operation cycle having a frame period so that each of the operation cycle comprises a programming cycle, a driving cycle and a relaxing cycle for relaxing a stress on a pixel circuit, prior to a next frame period.
US09633592B2	Display apparatus and method of driving the same A display device includes an acquiring circuit, a calculator, and a delay controller. The acquiring circuit acquires a gray scale voltage of a gray scale value of a pixel. The calculator calculates a first delay correction value based on a voltage currently retained on a data signal line to which the gray scale voltage is output and a gray scale voltage to be subsequently output to the data signal line. The delay controller determines a timing when the gray scale voltage is to be output to the data signal line based on the first delay correction value.
US09633591B2	Digital-to-analog converter, programmable gamma correction buffer circuit and display apparatus A digital-to-analog converter is for outputting a first output analog voltage according to a N-bit first digital signal or outputting a second output analog voltage according to a N-bit second digital signal and includes: a first voltage generator coupled between first and second reference voltages and for generating 2N first analog voltage between the first and second reference voltages, a first voltage selector for selecting the first output analog voltage from the 2N first analog voltage according to the N-bit first digital signal, a second voltage generator coupled to second and third reference voltages and for generating 2N second analog voltages between the second and third reference voltages, a second voltage selector for selecting the second output analog voltage from the 2N second analog voltages according to the N-bit second digital signal. A programmable gamma correction buffer circuit and a display apparatus also are provided.
US09633589B2	Display device having ESD circuit A display device includes a first interconnection line, a first data driver, a second interconnection line, an electrostatic discharge (ESD) circuit, and a display panel. The first connection line transmits a data driving signal. The first data driver includes the first interconnection line and output a data signal based on the data driving signal. The second interconnection line passes through the first data driver and transmits a gate driving signal. The ESD) circuit in the first data driver and discharges static electricity transmitted through the second interconnection line. The first gate driver outputs a gate signal based on the gate driving signal transmitted through the second interconnection line. The display panel receives the data signal and the gate signal.
US09633579B2	Fibers with physical features used for coding Disclosed are fibers which contains identification fibers. The identification fibers can contain a plurality of distinct features, or taggants, which vary among the fibers and/or along the length of the identification fibers, a fiber band, or yarn. The disclosed embodiments also relate to the method for making and characterizing the fibers. Characterization of the fibers can include identifying distinct features, combinations of distinct features, and number of fibers with various combinations of distinct features and correlating the distinct features to supply chain information. The supply chain information can be used to track the fibers, fiber band, or yarn from manufacturing through intermediaries, conversion to final product, and/or the consumer.
US09633577B2	CPR training system and methods A system including a chest compression sensor configured to detect at least one parameter corresponding to chest compressions of a subject and an electrocardiogram signal simulator configured to generate a simulated electrocardiogram signal and combine and/or modify the simulated electrocardiogram signal with an output of the chest compression sensor to produce a simulated electrocardiogram signal with a CPR artifact.
US09633575B2	Methods of treating overweight and obesity The present disclosure relates to compositions, kits, uses, systems and methods for treating overweight and obesity using naltrexone plus bupropion, preferably in combination with a comprehensive web-based and/or telephone-based weight management program, and preferably in subjects at increased risk of adverse cardiovascular outcomes.
US09633571B2	Art instruction systems and methods using a border guide Improved systems and methods using a border guide and/or border guide easel that enables art instruction in a relatively low cost and simple to use manner suitable for group or individual instruction of a relatively sophisticated nature. A scaled border guide preferably labeled with numbers and letters provides a virtual coordinate or reference system that enables artists to locate multiple random points on the surface to be painted. A physical grid or stencil or the like are not used on the artist's surface. The scaled border lines are used to define a virtual grid on the artist's working surface that may be used to indicate reference, points, positions, sizes and shapes for drawing or painting. Art instruction methods allow the teaching of drawing and painting in a more classical and relatively sophisticated style as compared to paint-by-numbers or grid art.
US09633570B2	Systems and methods incorporating animated widgets in a virtual learning environment Systems and methods for teaching in a virtual learning environment. In one example method comprises displaying a problem on a graphical user interface (GUI) of a computing system, receiving a user input of one or more potential solutions to the problem, animating, via the GUI, one or more graphical representations of the one or more potential solutions, receiving a user input selecting a first one of the one or more potential solutions, and displaying, on the GUI, an animation that illustrates a workability or accuracy of the one or more potential solutions.
US09633566B2	Trailer backing path prediction using GPS and camera images A method of controlling a vehicle and trailer assembly comprises obtaining an image for a current position of the vehicle and trailer assembly from a GPS system. The image is displayed on a display screen and a location is selected to indicate a desired final position for the vehicle and trailer assembly. An intended trailer backing path is determined with the desired final position of the vehicle and trailer assembly and a predicted trailer backing path is determined based upon a steering angle of the vehicle and an angle between the vehicle and the trailer. The predicted trailer backing path and the intended trailer backing path are displayed on the display screen to assist the operator in steering the vehicle.
US09633564B2	Determining changes in a driving environment based on vehicle behavior A method and apparatus are provided for determining whether a driving environment has changed relative to previously stored information about the driving environment. The apparatus may include an autonomous driving computer system configured to detect one or more vehicles in the driving environment, and determine corresponding trajectories for those detected vehicles. The autonomous driving computer system may then compare the determined trajectories to an expected trajectory of a hypothetical vehicle in the driving environment. Based on the comparison, the autonomous driving computer system may determine whether the driving environment has changed and/or a probability that the driving environment has changed, relative to the previously stored information about the driving environment.
US09633563B2	Integrated object detection and warning system In one aspect, an object warning system for a machine is disclosed. The object warning system includes an object detection system and an operator interface having a visual display, and a controller in communication with the object detection system and the operator interface. The controller is configured to control the display to represent a warning level as a function of a status of the machine and a distance of an object relative to the machine.
US09633559B2	Projecting vehicle transportation network information A method and apparatus for generating projected vehicle transportation network information for use in traversing a vehicle transportation network may include receiving a remote vehicle message including remote vehicle information indicating remote vehicle geospatial state information and remote vehicle kinematic state information, identifying host vehicle information including host vehicle geospatial state information and host vehicle kinematic state information, generating projected vehicle transportation network information representing a portion of the vehicle transportation network based on the remote vehicle information and the host vehicle information, and traversing a part of the portion of the vehicle transportation network represented by the projected vehicle transportation network information using the projected vehicle transportation network information.
US09633558B2	Processing method and apparatus for implementing control of target device A processing method for implementing control of a target device includes: providing an interface for confirming or inputting a target device identifier; receiving a target device identifier confirmed or selected by a user; providing an interface for confirming or selecting a function parameter of a target device; receiving a function parameter of a target device confirmed or selected by the user; providing a control interface image; and generating and storing, according to the received target device identifier and function parameter that are sent by the user and correspondence between the function parameter of the target device and a value of a control signal, correspondence among the target device identifier, an operation instruction for the control interface image, and the value of the control signal.
US09633556B2	Adjusting acknowledgement requests for remote control transmissions based on previous acknowledgements A remote receives an instruction to transmit and determines whether or not to include an acknowledgement request in the instruction based on statistics regarding receipt of acknowledgements associated with previously transmitted instructions. If so, the remote control device includes the request before transmitting. The remote control may determine whether or not to include the request in a variety of different ways in a variety of different implementations. In some implementations, the remote control may classify instructions into two or more different classifications and may treat instructions of different classifications differently. In other implementations, the remote control may treat the same instruction differently depending on the number of requested acknowledgements successfully received during a time period. In various other implementations, the remote control may perform various combinations of these approaches.
US09633552B2	Methods, systems, and devices for managing, reprioritizing, and suppressing initiated alarms Present example embodiments relate generally to methods, systems, computing devices, and logic for managing a plurality of alarms initiated by a plurality of alarm sensors. The method comprises the steps of: receiving the plurality of initiated alarm, prioritizing the initiated alarms, creating an initiated alarm being a condition-based alarm when an initiated alarm satisfies an event condition, reprioritizing an initiated alarm when said initiated alarm satisfies a reprioritization condition, suppressing an initiated alarm, reporting an unsuppressed initiated alarm based on the prioritizing of said alarm, and providing information comprising an operator action for the unsuppressed initiated alarm and an initiated alarm suppressed based on the unsuppressed initiated alarm.
US09633551B2	Enhanced wireless location system and method An identification tag has at least a controller, a receiver for receiving wireless signals from an exciter, and a transmitter for transmitting wireless signals to at least one location receiver (which may be a WLAN access point). The tag's controller can determine the presence of interference from sources unrelated to the location system, such as smartphones, tablets, computer monitors etc., and signal an alert accordingly.
US09633547B2	Security monitoring and control Systems, methods, and software for monitoring and controlling a security system for a structure are provided herein. An exemplary method may include receiving sensor data from at least one first peripheral, the sensor data associated with at least one of activity inside and activity outside of a structure; determining a critical event based in part on the sensor data; creating an alert based in part on the critical event; getting user preferences associated with at least one of a user and a base unit; determining a response based in part on the alert and user preferences; and activating at least one of a second peripheral and a service based in part on the response.
US09633546B2	Touchless compliance system A touchless compliance method and system can include: a server beacon, the server beacon including a gesture sensor, a motion sensor, a microphone, a server beacon mass storage, and a server beacon power transceiver; detecting gesture data from the gesture sensor; recording audio data with the microphone; a power station including a power station power transceiver, a station control unit, upload coordinator, and a station storage unit; sending a packet from the server beacon to the power station; prioritizing the packet; uploading a message including the audio data to the power station; uploading the message to an audio database server; transcribing the audio data; and displaying the transcription along with an option to replay the audio data on an external computer.
US09633544B2	Hygiene compliance module A hygiene compliance module is configured to be retrofit with a compatible dispenser to enable hygiene compliance monitoring functions. The hygiene compliance module is configured to be coupled to the dispenser via a communication interface to receive power, ground, and dispenser actuation signals therefrom. In addition, the hygiene compliance module is enabled to communicate with a wireless data tag that is worn by a user of the dispenser and with a remote hygiene compliance monitoring station.
US09633541B2	Display system for tracking large numbers of persons and/or objects A display system for tracking large numbers of persons or objects in real-time is disclosed. The display system utilizes a tracking system that employs various types of technologies, such as RFID, to determine the location of the person and/or objects being tracked. The displays of the present invention utilize colors, graphics, and the physical groupings of related data on a display device, usually a computer monitor, to present tracking information in a compact, readily changeable, and easily analyzed format in real-time.
US09633539B2	Collision sensor assembly for a stationary structure A collision sensor assembly is attachable to a stationary structure such as a pallet rack, a door frame, the corner of a wall, or the like. The collision sensor is configured to sense when a collision occurs with the stationary structure such as when a piece of movable machinery contacts the stationary structure. The collision sensor assembly includes a sensor operatively connected to a processor which determines when a collision occurs, and produces a signal to an output signal generator to provide an external indication of the collision.
US09633537B2	Methods and apparatus to detect and warn proximate entities of interest Systems and methods to detect and warn proximate entities of interest are described herein. An example method includes determining threat levels for hazards in a plurality of different zones within a building, classifying the threat levels into at least one of a first threat level and a second threat level, designating a first zone of the plurality of different zones having the first threat level with a first detectable indicator, and designating a second zone having the second threat level with a second detectable indicator.
US09633529B2	Medium pick-up apparatus, medium process apparatus and financial device Provided is a pick-up apparatus. The medium pick-up apparatus comprise a support plate to support a medium, a pick-up roller unit comprising a pick-up roller for picking up the medium, a detection unit to detect the number of medium that is picked up by the pick-up roller, and a pick-up roller moving device to move the pick-up roller unit to space the pick-up roller unit from the medium supported by the support plate when the pick-up of predetermined number of medium is detected by the detection unit.
US09633526B2	Electronic gaming device with near field functionality Examples disclosed herein relate to an electronic gaming device including a memory, a processor, and a plurality of reels. The memory may include one or more near field modules. A processor may generate one or more symbols to be located in the one or more areas. The processor may initiate one or more game play functions based on location data.
US09633525B2	Gaming machine and methods of allowing a player to play gaming machines having selectable reel configurations A gaming device is described herein. The gaming device includes a display unit and a controller that is coupled to the display unit. The display unit is configured to display a game including a plurality of reels being displayed in a display grid. Each reel is adapted to display one of a plurality of symbols. The controller is configured to randomly determine an outcome of the game, select a reel configuration including a plurality of reel groups, determine, for each reel group, a single random symbol being displayed in each reel of the corresponding reel group in the determined outcome, spin and stop each reel of the corresponding reel groups to display the outcome including displaying the same symbols in each reel of the corresponding reel group during rotation, and provide an award to the player as a function of the determined outcome.
US09633524B2	Gaming machine conducting indication effect A gaming machine stores an effect combination table in which each of predetermined combination conditions of symbols has probabilities associated with respective effect combinations each constituted by one or more indication effect. The gaming machine executes a process of randomly determining the symbols to be rearranged on the reel unit. The gaming machine executes a process of determining to which one of the combination conditions the combination of the determined symbols corresponds. The gaming machine executes a process of selecting an effect combination table based on the corresponding combination condition and randomly selecting one effect combination from a plurality of effect combinations based on the probabilities in the selected effect combination table. The gaming machine executes a process of executing an indication effect indicated by the selected effect combination, by means of the notification device.
US09633523B2	Apparatus, system, method, and computer-readable medium for casino card handling with multiple hand recall feature Apparatuses, systems, methods, and computer-readable media are disclosed for detecting, storing, and retrieving information about the composition of present and past hands of cards in a casino table game. The method includes causing a card-handling device to substantially automatically generate a plurality of hands wherein each hand includes one or more cards. Card information is identified that includes a rank and a suit of each card as each card moves through the card-handling device. A play history is maintained of a card composition of more than one round wherein the card composition of each round includes the cards in each hand of each round. The card information of at least one hand from at least one round may be displayed.
US09633520B2	System and method for implementing an additional game to players of a lottery game A computer-implemented system and method for providing a lottery game includes providing players with a unique validation code for each desired play of a lottery game. A first encryption code is generated for each validation code and stored so that the first encryption code and algorithm are present only as electronic data in the computer system and are not provided to the players. Players submit their respective unique validation code for registration in the lottery game and the computer system applies the algorithm to each code submitted by a player to create a second encryption code for each unique validation code. The computer system compares the second encryption code with a record of the first encryption codes to determine whether a match exists between the second encryption code and one of the first encryption codes.
US09633518B2	Continuous play in historical racing devices A system for wagering during a wagering period having a wagering base with a first plurality of pools each with an outcome accessed by an input wager. A plurality of terminals is provided at which wagers are input, each directed to access an outcome in one of the pools. A processing system is configured to process the input wagers in a manner whereby each input wager either: a) accesses; or b) fails to access an outcome. The processing system is further configured so that there is an initial pre-assigned probability of accessing the outcome of each pool through an input wager. The processing system is further configured to identify a collective return by determining the number of input wagers that have accessed an outcome in a particular pool. The processing system is further configured to change the wagering base after the wagering period has begun and before the wagering period is concluded based upon one or more system operating parameters detected during the wagering period.
US09633517B2	Gaming machine having free game, wherein the number of adding free game is added The present invention provides a gaming machine employing a free game system which provides an enhanced game element. The gaming machine determines the number of adding free game based on a game number lottery table under the condition that a first symbol is rearranged in the symbol display unit in the free game, and adds a preset number of free game under the condition that a second symbol is rearranged in the symbol display unit in the free game.
US09633514B2	Systems, apparatuses and methods enhancing gaming outcome opportunities Embodiments of the present invention set forth systems, apparatuses and methods for providing game features. In a game of chance involving at least one outcome, a plurality of alternative outcomes can be derived for a gaming event, such as when one of the outcomes will provide a payout at or above a certain level. The player is presented with an opportunity to select among the alternative outcomes, without being aware of the particular characteristics or values associated with the outcomes. While the player will only select the outcome having the payout at/above the threshold level a certain percentage of the time, the opportunity can be presented to the player more often, while keeping the mathematical probabilities the same or similar if desired, thereby providing the player with the feeling of getting higher value opportunities more often.
US09633513B2	Method and system for gaming revenue A method and system comprises integrating a contest framework into a game. The contest framework at least comprises means for communicating with a transactional server, a plurality of listeners being configured to monitor interactions during a play of the game for communication to the transactional server, and means for displaying notifications from the transactional server. The transactional server is at least configured for processing received interactions in conjunction with a progressive jackpot contest associated with the game and communicating notifications regarding the processing to the contest framework. A communicating with the transactional server at least comprises associating the game with a progressive jackpot contest and setting parameters for the progressive jackpot contest.
US09633512B2	Method and apparatus for triggering a bonus Embodiments of the present invention are directed to a bonus game that is common to a bank of electronic gaming devices. One or more pools accrue with each wager placed. A player qualifies to play the bonus game when at least one tracked player or game criterion, such as wagers made, exceeds a threshold, triggers a mystery-jackpot counter, or is selected by a weighted pay table. The bonus game includes a video display of a wheel bouncing against a brick wall with bricks being exploded by coins. After an opening is formed in the wall and the wheel escapes, a wheel spin determines the bonus game outcome. More than one player may play the bonus game in sequence until the last player spins the wheel.
US09633511B2	Gaming system and method for providing a game which populates symbols along a path In various embodiments, the present disclosure relates generally to a game including a path of different symbol display positions. The gaming system generates one or more symbols (and/or one or more awards) at one or more of the symbol display positions of a matrix or grid. The gaming system then randomly forms a path including a plurality of the symbol display positions and determines an award for the player based on which symbol display positions are included in the formed path.
US09633510B2	Method, apparatus and system for perpetual bonus game Methods of playing games and gaming systems and devices useful for playing games. Gaming devices include a first gaming unit for randomly selecting and displaying indicia associated with play of a primary game and for generating a signal relating to play on the first gaming unit. The gaming device also includes a second gaming unit connected to the first gaming unit for conducting an ongoing bonus game and enabling participation by a player in the ongoing bonus game in response to a signal generated by the first gaming unit. The ongoing bonus game may be administered by and communicated from a second gaming unit in the form of a host server to a number of networked gaming devices. Players may enter and exit play of the ongoing bonus game while it is still in progress, participating only in a segment thereof.
US09633507B2	System for providing a game at a gaming machine A server includes a memory, a network interface configured to receive data related to a game available as part of a gaming system, and a processor. The processor is configured to receive the game data via the network interface, determine demand for the game within a gaming environment based on the game data and determine a weighting factor associated with the game based on the demand, and upload the game at one or more gaming machines within the gaming environment based on the weighting factor. The prominence of the game within the gaming environment varies according to the weighting factor.
US09633504B2	System, method, and apparatus for purchasing, dispensing, or sampling of products Systems, methods, and apparatus for the purchase of and/or free sampling of products. The systems, methods, and/or apparatus may permit push notifications of purchased products and/or free product samples being available and may permit the use of mobile devices and/or mobile device applications to be used to purchase products or dispense free samples of products via a product dispenser or vending machine.
US09633503B2	Vendor The present application provides a vendor for vending a number of products. The vendor may include a cooler and a vending device positioned within the cooler. The vending device may include a number of product shelves with a number of product gates and one or more product locking systems that permit the removal of only one product at a time from the product gates.
US09633497B2	Systems and methods for medical monitoring device gesture control lockout A medical monitoring device may include a gesture control sensor for detecting gesture commands from users. The medical monitoring device may enable gesture control when it receives an identifier from a tag and the identifier is authenticated. The tag may include an RFID tag and/or a barcode. The identifier may be authenticated locally and/or by a remote device communicatively coupled to the medical monitoring device (e.g., over a network). Once gesture control is enabled, gestures by the user may be identified by the medical monitoring device, an action corresponding to the gesture may be determined, and the action may be performed. The gesture control sensor may be disabled manually or automatically when predetermined criteria are satisfied to prevent the gesture control sensor from receiving inadvertent commands.
US09633496B2	Vehicle contents inventory system A vehicle may include a passive entry system having a controller and at least one antenna within the vehicle. The controller is operably arranged with the at least one antenna, and configured to cause, in response to a trigger event, the at least one antenna to transmit at least one challenge, receive a response to the challenge indicative of a tag in a vicinity of the vehicle, and identify an item based on the tag.
US09633495B2	System and method for wirelessly authenticating a device having a sensor A method for wireless authentication of a device to a machine is provided. The device has a sensor and the method includes sensing, by a sensor of the device, a first input pattern of physical parameters received at the device. The method includes wirelessly transmitting, from the device, an identification signal to a machine upon said sensing of the first input pattern. The method includes wirelessly receiving, at the device, an authentication signal indicating an authentication of the device, wherein the device is configured to interact with the machine upon the wireless receiving of the authentication.
US09633489B2	Configurable onboard information processing A system and method of processing information onboard a vehicle. Execution attributes on the vehicle are read by a computer program running on a data processing system on the vehicle. The execution attributes define a number of information processing actions. The number of information processing actions are performed on the vehicle by the computer program running on the data processing system on the vehicle using the execution attributes.
US09633487B2	Method and system for logging vehicle behavior Methods and systems for logging driving information associated with a vehicle when driven are disclosed. In one aspect, a mobile telecommunications device is provided that is adapted for installation to a vehicle and configured to log driving information associated with the vehicle when driven. The mobile device is arranged to register the start of a driving period during which the mobile device is installed to the vehicle and the vehicle is being driven by a driver. The mobile device is also arranged to process sensor data during the driving period to derive driving information associated with how the vehicle is driven. The mobile device is also arranged to store a selection of the driving information to a memory.
US09633486B2	Method for data communication between vehicle and fuel pump A method for data communication between a vehicle and fuel pump includes storing vehicle operating data on an onboard recorder in the vehicle, and transmitting the vehicle operating data from the onboard recorder to the fuel pump. The vehicle operating data includes vehicle identification information.
US09633484B2	Vehicle device installation system A device installation system for providing a tool for use by installers to assist in obtaining vehicle specific information such as wiring diagrams, technical information and direct access to technical support technicians. The system further provide for testing, trouble shooting and configuration of installed vehicle devices.
US09633482B2	Apparatus and method for restricting image data visualization An image processing apparatus comprises a data receiving unit for receiving a medical image data set, the medical image data set being representative of at least part of a patient, and a processing unit for processing the medical image data set to restrict visualization of at least part of the patient's skin surface.
US09633478B2	Display apparatus and control method thereof A display apparatus is provided. The display apparatus includes: a transparent display; a scanner configured to scan an object seen through the transparent display, a position of the scanner being adjustable with respect to the transparent display; and a controller configured to provide information corresponding to the scanned object on the transparent display, in response to occurrence of a predetermined event.
US09633473B2	Efficient compression of 3D models based on octree decomposition To reduce the entropy of occupancy codes of an octree and improve compression efficiency, the present principles provide a method and an apparatus for traversing sub-cells in a cell according to the geometrical property of 3D models. That is, a surface smoothness measure is calculated for each sub-cell and the sub-cells are traversed in a pre-determined order of surface smoothness measures. To compute the surface smoothness measure, a sub-cell is connected to neighboring cells of its parent cell to form triangles and angles. Subsequently, the triangle areas or angular measures are used to compute the surface smoothness measure. When the connectivity information is not available in the 3D model data, the present principles also provide a method and an apparatus for estimating the connectivity.
US09633472B2	Master model for data related to a spatial region The present disclosure involves systems, software, and computer-implemented methods for providing a master model for data about a spatial region. An example method includes identifying a master model associated with a spatial region, the master model including a plurality of pixels, each pixel corresponding to a particular portion of the spatial region and including a length and a width for the particular portion of the spatial region; identifying a data set including values of a physical property of at least a portion of the spatial region for a particular time; determining, based at least in part on the data set, a set of values of the physical property including a value for each pixel in the master model; and storing the set of values of the physical property as a value for each pixel.
US09633470B2	Generating slice data representing a cross section cut from a three-dimensional modeled object To make it possible to generate slice data without the need to modify a polygon mesh that does not satisfy conditions of a perfect solid model. A slice data generator for generating slice data representing a cross section cut from a three-dimensional modeled object, wherein the slice data generator has: changing means for changing topology information of a polygon mesh so that a contour polyline is obtained indicating a contour line of a cut cross section of the polygon mesh; and modifying means for acquiring the contour polyline from the polygon mesh, the topology information of the polygon mesh having been changed by the changing means, and modifying the contour polyline so that an inside which is a region inside the acquired contour polyline can be normally filled; slice data being generated on the basis of the contour polyline modified by the modifying means.
US09633469B2	Conservative rasterization of primitives using an error term A system, method, and computer program product are provided for conservative rasterization of primitives using an error term. In use, an edge equation is determined for each edge of a primitive, the edge equation having coefficients defining the edge of the primitive. Each edge of the primitive is shifted to enlarge the primitive by modifying coefficients of the edge equation defining the edge by an error term that is a predetermined amount. Pixels that intersect the primitive are then determined using the enlarged primitive.
US09633466B2	Low latency ink rendering pipeline Systems and methods are provided for improving the latency for display of ink during user creation of ink content with a stylus, mouse, finger (or other touch input), or other drawing device for tracing a desired location for ink content in a display area. In order to reduce or minimize the time for display of ink content created by a user using a stylus/mouse/touch input/other device, a separate ink rendering process thread can be used that operates within the operating system and in parallel to other application threads. When it is desired to create ink content within an application, user interactions corresponding to creation of ink content can be handled by the separate ink rendering process thread. This can avoid potential delays in displaying ink content due to an application handling other events in a process flow.
US09633464B2	Automatic animation generation Some embodiments of the invention provide a method that receives a selection of an animation to apply to two or more graphical objects in a scene over a particular time duration. The method identifies parameters for each of the graphical objects. Based on the selected animation, the method generates modifications to at least one parameter for each of the graphical objects over the particular time duration. The parameter of a first graphical object is modified differently than the parameter of a second graphical object. The method stores the modifications as data for the scene.
US09633460B2	Systems and methods for seamless patch matching A method implemented in an image editing device comprises determining a source region in a source image and determining a target region in a target image. At least one image characteristic of each of the source region and a region outside the target region is analyzed. The content in the source region is adjusted according to the at least one image characteristic of the source region and the at least one image characteristic of the region outside the target region. The adjusted content from the source region is inserted into the target region.
US09633452B2	Resolving multi-sampled anti-aliasing buffers into single sampled buffers The resolve operation in multi-sampled anti-aliasing may be avoided on a per pixel basis if all subsamples are determined to have the same color and the same storage is used for the resolved image as for one of the subsample planes.
US09633447B2	Adaptable framework for cloud assisted augmented reality A mobile platform efficiently processes image data, using distributed processing in which latency sensitive operations are performed on the mobile platform, while latency insensitive, but computationally intensive operations are performed on a remote server. The mobile platform acquires image data, and determines whether there is a trigger event to transmit the image data to the server. The trigger event may be a change in the image data relative to previously acquired image data, e.g., a scene change in an image. When a change is present, the image data may be transmitted to the server for processing. The server processes the image data and returns information related to the image data, such as identification of an object in an image or a reference image or model. The mobile platform may then perform reference based tracking using the identified object or reference image or model.
US09633446B2	Method, apparatus and computer program product for segmentation of objects in media content In an example embodiment a method, apparatus and computer program product are provided. The method includes extracting a first set of target-object regions and at least one set of non-target object regions from a plurality of regions of a video content based at least on likelihood information. A plurality of unlabeled regions of the video content are classified based on the first set of target-object regions and the at least one set of non-target object regions to generate a second set of target object regions that is denser than the first set of target object regions. A model is learned for modelling at least one of the target object and non-target objects of the video content based at least on the second set of target object regions. The target object in the video content is segmented based on the model and the second set of target object regions.
US09633443B2	Image processing device, image processing method, and program for cutting out a cut-out image from an input image There is provided an image processing device including an image generation unit that analyzes an input image, cuts out, based on an analysis result of the input image, a cut-out image from the input image, and generates cut-out image information in which the cut-out image is associated with a restrictive condition that the cut-out image satisfies.
US09633441B2	Systems and methods for obtaining image depth information A system for obtaining image depth information for at least one object in a scene includes (a) an imaging objective having a first portion for forming a first optical image of the scene, and a second portion for forming a second optical image of the scene, the first portion being different from the second portion, (b) an image sensor for capturing the first and second optical images and generating respective first and second electronic images therefrom, and (c) a processing module for processing the first and second electronic images to determine the depth information. A method for obtaining image depth information for at least one object in a scene includes forming first and second images of the scene, using respective first and second portions of an imaging objective, on a single image sensor, and determining the depth information from a spatial shift between the first and second images.
US09633437B2	Method for displaying successive image frames on a display to stabilize the display of a selected feature in the image frames A method for displaying successive image frames on a display. The method including: processing image data containing the successive image frames to identify features in an image frame and to display the image frame to a user with two or more of the identified features highlighted; manually selecting one of the identified features by a user; determining a portion of a subsequent image frame in which the selected feature is likely to be present; and if the selected feature is found in the portion of the subsequent image frame, displaying the subsequent image frame to change the position of the selected feature.
US09633434B2	Calibration of camera-based surveillance systems A computer implemented method, computer program product, and computer system for determining camera calibration data. The computer system receives geo-positional data of a moving object, wherein the geo-positional data is associated with an indicator (112). The computer system receives further a sequence of frames (140) from the at least one camera (150), wherein at least one frame has a picture of the moving object (118) with a structure and with an encoded version of the indicator which are optically recognizable. The indicator associated with the at least one frame is extracted by decoding (170) the optically encoded version of the indicator of the at least one frame. The geo-positional data of the moving object which is in the picture of the at least one frame is obtained by matching (172) the indicator associated with the geo-positional data of the moving object and the decoded indicator associated with the at least one frame. At least one reference point of the at least one frame is identified by analyzing the optically recognizable structure in the picture of the at least one frame. The camera calibration data of the at least one camera is determined by applying a geometric transformation (174) on the at least one reference point and its associated geopositional data of the moving object which is in the at least one frame.
US09633433B1	Scanning system and display for aligning 3D images with each other and/or for detecting and quantifying similarities or differences between scanned images The subject invention is a scanning system and display and more particularly a scanning system and display for detecting and quantifying similarities or differences between stored data and data collected from a scan. The system operates to perform surface scans and/or deep scans or a combination thereof and utilizes a method or process that decreases the time required for calculating a pose estimate thus increasing its performance thereby making it more practical for many applications that require real-time operations. In a preferred embodiment of the invention the system comprises one or more sensing components for scanning and measuring various surface or internal features of an object and determines differences between data obtained from two or more scans. Preferably the system can operate to scan numerous objects including mechanical objects, biological objects or medical conditions, artifacts, geographical objects, agricultural objects, or used in conjunction with robotic manufacturing systems, robotic surgical systems, aircraft systems, and marine applications.
US09633432B2	Image analysis method and apparatus for assessment of peritoneal dialysis complication in peritoneal dialysis An image analysis method and an apparatus thereof for assessment of PD (peritoneal dialysis) complications in peritoneal dialysis are provided. An analysis procedure is executed on an image under test of a dialysis bag, so as to obtain a color location in a color space corresponding to the image under test. A prompt signal is sent when the color locations obtained in a time period gradually become close to a disease warning range after executing the analysis procedure on a plurality of images under test.
US09633429B2	Pattern outline extraction device, pattern outline extraction method, and computer program product According to one embodiment, a pattern outline extraction device includes a control unit, a secondary storage unit and a memory. The control unit reads the image data of the patterns formed by changing the process condition, and extracts outlines of the patterns from the image data. The control unit superposes the outlines, and sets straight measurement lines. The control unit calculates variations on the measurement lines relative to measurement points on the measurement lines at points of intersection of the measurement lines and the outlines, and calculates variation-process condition correspondence information. The control unit calculates predicted variations on the measurement lines relative to the measurement points corresponding to a desired process condition based on the variation-process condition correspondence information, calculates calculated points that are obtained by adding the predicted variations to the measurement points on the measurement lines, and calculates a predicted outline by connecting the calculated points.
US09633428B2	Automatic occlusion region identification using radiation imaging modality Among other things, one or more systems and/or techniques for identifying an occlusion region in an image representative of an object subjected to examination is provided for herein. Such systems and/or techniques may find particular application in the context of object recognition analysis. An image is generated of the object and an orientation of the object is determined from the image. Based upon the determined orientation of the object relative to the direction the object is translated during examination, one or more parameters utilized for segmenting a second image of the object, identifying features in the image, and/or determining if the image comprises an occlusion region may be adjusted. In this way, the parameters utilized may be a function of the determined orientation of the object, which may mitigate false positives of detected occlusion regions.
US09633419B2	Lens distortion correction device and application processor having the same A lens distortion correction device and an application processor having the same include a distortion correction unit configured to correct a distorted image into an undistorted image and an image enhancement unit configured to improve the undistorted image using a high-frequency component of the distorted image.
US09633418B2	Image processing device, imaging apparatus, image processing method, and program An image processing unit 36 includes an information acquisition unit 40, a filter acquisition unit 42, and a filter processing unit 44. The information acquisition unit 40 acquires imaging information of original image data which is acquired by capturing an object image using an optical system. In a case in which the imaging information includes the first imaging condition and does not include the second imaging condition, the filter acquisition unit 42 acquires a sharpening filter which is associated with the first imaging condition and is associated with a representative condition of the second imaging condition. The filter processing unit 44 applies the sharpening filter acquired by the filter acquisition unit 42 to the original image data to acquire sharp image data.
US09633415B2	Systems and methods for improving video stutter in high resolution progressive video Systems and methods for improving video stutter in high resolution progressive video captured with fast exposure times. In a first approach, digital video is captured with fast shutter speeds that cause objects moving within the frame to appear motionless. The video codec generates motion information that may be utilized to add an artificial motion blur to each frame of the digital video during processing in a digital video pipeline. The motion blur creates the appearance that an object is moving in the frame. In a second approach, the lens assembly of the digital camera includes an electronically controlled filter that attenuates the light reaching an image sensor such that the shutter speeds may be decreased in order to capture motion blur. The electronically controlled filter may be a liquid crystal display (LCD) device that is set to a plurality of different transparency levels based on a target exposure value.
US09633412B2	Method of adjusting screen magnification of electronic device, machine-readable storage medium, and electronic device A method of adjusting a screen magnification of an electronic device is provided. The method includes displaying a Dots Per Inch (DPI) setting screen in order to adjust a screen magnification of an object that is to be displayed on a display unit of the electronic device, receiving information about changed DPI through the DPI setting screen, calculating a screen magnification using the changed DPI and a preset Device-Independent Pixel (DIP), changing a size of the object to correspond to the calculated screen magnification, and displaying the object according to the changed size.
US09633407B2	CPU/GPU synchronization mechanism A thread on one processor may be used to enable another processor to lock or release a mutex. For example, a central processing unit thread may be used by a graphics processing unit to secure a mutex for a shared memory.
US09633404B2	Method and system for secure co-browsing of patient records on communication devices A method and system are provided for co-browsing of patient records on communication devices. The method includes setting up a communication session between a first communication device and one or more second communication devices, where the communication session is initiated by the first communication device. Further, the method includes accessing one or more patient records via a server, where the one or more patient records are accessed at the first communication device. The method further includes sending a reference of the one or more patient records to the one or more second communication devices, where the reference is sent from the first communication device.
US09633393B2	Extensible software architecture for processing level 2 financial data The present invention processes and distributes Level 2 financial data. This invention comprises a constituent component that identifies various pieces of information that are contained in stock feeds. These pieces of information are identified and keys are generated based on the various pieces of information and combinations of pieces of information. The information in the incoming stock feeds can be sorted and processed based on a particular key or keys depending on the desires of a particular client. In addition, new keys can be generated based on the preference of a particular client. This flexibility to create the various keys to be used to process feed information is different from conventional methods that use only a standard set of sorting and processing criteria for all feeds and for all clients.
US09633392B2	Integrated finding experience systems and methods An integrated finding experience is a workflow configured to facilitate a search by a user for one or more items among many items (e.g., an inventory of items). An integrated finding experience machine may provide one or more user interfaces that support the workflow in presenting information differently as the user progresses through a search process (e.g., a finding experience) with respect to a database (e.g., storing information regarding one or more items). For example, the workflow may include various stages of a search process from defining a query, to refining the query, to visually scanning search results, to displaying details of one or more selected search results, to comparing selected search results to each other. Each stage may have a specialized user interface configured to facilitate one or more user activities pertinent to that stage.
US09633386B1	Display of items from search Disclosed are various embodiments for determining categories of items to include in a search results listing. Items to include in a search result listing are identified in response to a search request. The items are classified in multiple categories. A particular seller of multiple sellers is identified based at least in part on the search request. A subset of the categories is determined for which corresponding items are to be included in the search results listing. The subset is determined by applying one or more rules specified by the particular seller.
US09633381B2	Mobile application monitoring system A method and system to test, monitor, and share revenue associated with third-party software applications operating on mobile devices over a network operator's wireless network. An application may be tested by the mobile application monitoring system to simulate the expected load of the application on a mobile device and the wireless network utilized by the mobile device, and to determine any services utilized by the application. Based on the simulation, the system determines a compensation arrangement under which revenue associated with the application will be shared between the network operator and the application provider. In some embodiments, the compensation arrangement is determined from a variable reward table. Revenue is shared inversely with an application's impact on customers and on the network operator.
US09633379B1	Qualified video delivery advertisement A video server is configured to provide streaming video to players of computer games over a computing network. The video server can provided video of different games to different players simultaneously. This is accomplished by rendering several video streams in parallel using a single GPU. The output of the GPU is provided to graphics processing pipelines that are each associated with a specific client/player and are dynamically allocated as needed. A client qualifier may be used to assure that only clients capable of presenting the streaming video to a player at a minimum level of quality receive the video stream.
US09633377B2	Image content and advertisement data providing method, system, and apparatus To provide an image contest providing method capable promoting advertisement effect by dynamically inserting an advertisement image to a distributed image content, an image content reproducing apparatus requests an image content providing apparatus to distribute the image content. Then, the image content is distributed to the image content reproducing apparatus and a viewer can utilize the image content. At this occasion, the image content providing apparatus distributes the image content, detects an advertisement inserting position and requests an advertisement image providing apparatus to distribute an advertisement image. Then, the advertisement image providing apparatus selects the advertisement a image to be inserted to the image content and transmits thereof to the image content providing apparatus. Thereafter, the image content providing apparatus inserts the advertisement image to a position of the image content for inserting the advertisement and distribute thereof the image content reproducing apparatus.
US09633374B2	System and methods for rebroadcasting of radio ads over other mediums A method and system for specifying content of interest using a digital radio broadcast receiver is described. A digital radio broadcast signal includes an alternate way of distributing content-rich Advertisements over the digital radio broadcast networks and rebroadcast these Advertisements over technologies like Bluetooth, Wi-Fi and the like to smart devices. A digital out-of-home network system will act as a bridge to relay the received Advertisements to smart devices.
US09633373B2	Activating display and performing additional function in mobile terminal with one-time user input Disclosed is a mobile terminal including a touch screen display, a camera, a power button and an activation button for turning on the touch screen display. The mobile terminal has a first function and a second function to perform in response to user input and provides user settings for configuring at least one of the first and second functions such that the at least one of the first and second functions is performed along with turning on the touch screen display when pressing of the activation button is detected while the touch screen display is turned off. The mobile terminal is configured to perform the first and second functions depending upon length of pressing of the activation button in addition to turning on the touch screen display.
US09633372B2	Anonymous digital identification Methods and systems for anonymous digital identification are disclosed and may include detecting the presence of a first wireless communication device utilizing a second communication device, the first wireless communication device being associated with a first set of content that is distinguishable from an identifier associated with said first wireless communication device. In response to a determination that the first wireless communication device and the second communication device are geographically proximate to one another based on location detection capabilities of the first wireless communication device or the second communication device, content may be provided to the first wireless communication device. The content may be based at least in part on a shared or complementary interest associated with the first wireless communication device, and the interest may have previously been expressed by a user of said first wireless communication device. The wireless communication device may be associated with a unique identifier.
US09633364B2	Method and apparatus for detecting fraudulent advertising traffic initiated through an application An approach is provided for detecting fraudulent advertising traffic initiated through an application. An advertising platform receives a request, from an advertising module, for serving of advertisement information, wherein code for executing the advertising module is integrated with other code of an application executing at a device. The advertising platform causes, at least in part, processing of the advertisement information to include at least one verification check of the advertising module, the code for executing advertising module, the application, the other code associated with the application, or a combination thereof. The advertising platform causes, at least in part, transmission of the at least one verification check in response to the request for serving of the advertisement information. The advertising platform causes, at least in part, processing of one or more results of the at least one verification check to determine a functioning of the advertising module.
US09633363B2	System and method of incentivized advertising Exemplary embodiments of methods and systems of incentivized advertising are presented. A content identifier identifying a digital content item, such as a song, is displayed on a user computing device. The digital content item is typically of the type available for a purchase price by the general public. A selection icon is provided in visual association with the content identifier. If the icon is selected by the user, an advertisement media item, such as a video advertisement, is presented on the user computing device. If the advertisement media item is presented for at least a requisite ad impression period, the digital content item is imparted to the user for free. Follow-up ad engagement views are typically presented to the user with a button to redeem the earned digital content item. Administrator and server elements are configured to facilitate performance of the method, and to optimize efficient use of advertiser's budget.
US09633362B2	System and method for creating reservations The systems, methods, and computer program products (collectively “systems”) described herein are generally configured to monitor actions in digital channels. More specifically, the systems are capable of creating reservations for items and initiating payments for the items based on actions or information received from the digital channel. The systems are capable of syncing transaction accounts with various digital channels. Moreover, the systems are capable of initiating or completing transaction based on user information. The systems may also be capable of providing rewards based on activities or accomplishments in the digital channels. Moreover, the systems may be capable of verifying activities based on transaction information.
US09633357B2	Net utility determination based on product replacement and service plan coverage decisions Example embodiments relate to net utility determinations based on product replacement and coverage decisions of a customer. In example embodiments, a number of net utility values corresponding to each possible product replacement decision and each possible coverage decision in each of a plurality of time periods is determined. An expected net utility attributable to the customer over the plurality of time periods is then determined based on the determined utility values.
US09633355B2	Knowledge based verification of the identity of a user According to certain embodiments of the disclosure, a system receives a request from a user device to conduct an activity with an enterprise and determines an authentication level associated with the activity. The system receives information associated with the user from a plurality of disparate channels and calculates a risk score associated with the user based on the received information associated with the user. The system generates a token based on the authentication level and risk score and communicates the token to the user device.
US09633350B2	Card reader communication method A card reader includes a body, the body being configured for coupling with a device, the device including a device light sensor and a device light source; a reader light sensor that is configured to capture light being emitted from the device light source, wherein, when the body is coupled to the user device, the reader light sensor is positioned adjacent to the device light source; a reader light source that is configured to emit light to the device light sensor, wherein, when the body is coupled to the user device, the reader light source is positioned adjacent to the device light sensor; a reader interface positioned in the body and configured to read the card; and circuitry configured to communicate data between the card reader and the user device using the reader light sensor and the reader light source.
US09633349B1	3D packaging of power amplifier dice apparatus and articles of manufacture An article of manufacture provides a compact assembly of power amplifiers in series and in parallel. A plurality of radial power splitters and radial power combiners couple surface mounted power amplifier dice into a power platter. Thermal conduction probes chained through the power platters remove heat from the vicinity of the power amplifier dice. Surface mounted power amplifier dice may be enclosed within a matched pair of power platters. Stackable power platters may be assembled to form a 3D power amplifier pile.
US09633345B2	Merchant point of sale security system A point of sale (POS) security system includes a POS device including a non-transitory memory, one or more hardware processors, and one or more environment sensors. A plurality of POS instructions are located on the non-transitory memory in the POS device and executable by the one or more hardware processors in the POS device to provide a POS engine that is configured to receive and transmit payment information for conducting a payment transaction associated with a purchase. A plurality of security instructions are located on the non-transitory memory in the POS device and are executable by the one or more hardware processors in the POS device to provide a security engine that is configured to receive environment signals from the one or more environment sensors in the POS device and analyze those environment signals to determine a security breach.
US09633343B2	Stacking purge-bin Apparatus and methods for a stacking purge-bin (“SPB”) are provided. The SPB may be configured to rotate. The SPB may include a plurality of receiving sections. One or more tangible items retracted by the SSK may be stored in each receiving section. Rotating the SPB between each retraction may prevent tangible items from two consecutive retractions from being stored in a single receiving section. Preventing tangible items from two consecutive retractions from being stored in a single receiving section may allow each tangible item to be associated with transaction information corresponding to a retraction. The SPB may store separators. A separator may be inserted between tangible items received from two consecutive retractions. Separating between tangible items received from two consecutive retractions may allow each tangible item to be associated with transaction information corresponding to a retraction. Transaction information associated with a retraction may be marked on the separator.
US09633341B2	Silent SMS triggering for mobile billing at a billing server The invention provides a method of processing transactions with a billing server, including receiving, with the billing server, a transaction request API call from a merchant computer including a msisdn, transmitting, with the billing server, a transaction request response to the merchant computer in response to the transaction request API call, including a transmission ID, receiving, with the billing server, a payment authorization text message from a consumer device at the msisdn including a transaction ID, determining, with the billing server, a match between the transaction ID in the text message with the transaction ID in the transaction request response and if a match is determined between the transaction ID's, transmitting, with the billing server, a charge request to a carrier server to charge an account on the carrier server corresponding to the msisdn.
US09633338B2	Out of office message improvements Embodiments of the present invention relate to set of improvements to the out of office assistant that send out of office messages to senders of messages while a recipient is out of the office. One embodiment of the out of office assistant associates an out of office message with a calendar event to ensure the out of office message is sent only for the predetermined time period associated with the calendar event. Other embodiments of the out of office assistant generating different messages to people internal to an organization and people external to an organization, and the out of office assistant allows different rich text formatting for the different messages. In a further embodiment, a persistent reminder reminds the user that the out of office message application is turned on.
US09633336B2	Method, system, and apparatus for truncating markup language email messages Truncating markup language email messages involves receiving a markup-language-formatted, source email having a message size that exceeds a predetermined size limit. The source email is truncated to conform to the predetermined size limit. The existence of unclosed tags in the truncated email is determined, and a suffix is appended to the truncated email. The suffix includes closing tags that correspond to the unclosed tags to the truncated email. A truncation index indicating where the truncation occurred is added to the message, as is a unique identifier usable to uniquely identify the source email stored on an email server. The truncated email is then sent to a recipient email client.
US09633335B2	Managing relationship and contact information Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for managing a relationship with and information about a contact. An example includes a client device that can be used to manage and keep track of information about a contact's family.
US09633333B2	System for dynamic data gathering and analysis A system is provided which enables customized sessions for data gathering and analysis. The system receives data and commands from one or more user devices to generate and modify a session dataset and to select and activate system functions. The results of user inputs and actions are published to other user devices in the session. One or more functions for generating datasets, organizing datasets and analyzing the datasets may be independently selected and activated. The system enables a data gathering and analysis session to be preconfigured with a predetermined set and order of functions or for a session to be conducted with a dynamic selection and activation of functions and a dynamic selection of the orders of functions. In some embodiments, there is provided a software as a service (SaaS) application for implementing the data gathering and analysis session functions.
US09633325B2	Systems and methods for supply chain management Systems and methods are directed to supply chain management. In particular, the tracking, tracing, authenticating, and reporting of supply chain events for products, is disclosed. Various embodiments can store, analyze, and track supply chain events and help to coordinate and maintain trading partner connections. Various embodiments also help to enhance patient safety, secure the supply chains for pharmaceuticals, medical devices, and other healthcare products, and help users to follow regulatory requirements.
US09633322B1	Adjustment of knowledge-based authentication Systems and methods are provided for adjustment of difficulty level, quantity, and/or other parameters of knowledge-based authentication. The questions may be asked of a consumer based on one or more generated risk scores associated with the consumer's behavior, which may be derived from information received from the consumer, a representative responsible for entering information regarding the consumer, and/or from the consumer's computing device.
US09633321B2	Systems and methods for facilitating call request aggregation over a network A method for facilitating electronic commerce over a network includes identifying input dependencies for a call request based on information passed with the call request, identifying state dependencies for the call request based on information passed with the call request, parallelizing calls from the call request based on at least one of the identified input dependencies and the identified state dependencies, developing a service execution map by grouping calls in an execution order including parallelized calls, and processing the service execution map by executing grouped calls in the execution order including parallelized calls.
US09633316B2	Predictive modeling based on summary data and modeling user's age at line level A system and method are disclosed for classifying a record of data when the record of data does not contain class membership information. In one example, summary data is utilized with predictive modeling to predict the age range of a user of a line of service. A prior probability that a user within the summary data belongs to a respective class, a first conditional probability of a first predictor within the summary data and a second conditional probability of a second predictor within the summary data are calculated. For each record of data, a probability of class membership is calculated based on the calculated prior probability and the first and second conditional probabilities.
US09633315B2	Method and system for distributed machine learning Method, system, and programs for distributed machine learning on a cluster including a plurality of nodes are disclosed. A machine learning process is performed in each of the plurality of nodes based on a respective subset of training data to calculate a local parameter. The training data is partitioned over the plurality of nodes. A plurality of operation nodes are determined from the plurality of nodes based on a status of the machine learning process performed in each of the plurality of nodes. The plurality of operation nodes are connected to form a network topology. An aggregated parameter is generated by merging local parameters calculated in each of the plurality of operation nodes in accordance with the network topology.
US09633312B1	Predicting user interests Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for predicting user interests. In one aspect, a method includes training a prediction model to generate a category prediction of a next query from a set of queries, the category prediction specifying categories to which a next query belongs, the prediction model comprising a plurality of prediction functions that each generate a category prediction of a next query, wherein the prediction functions include two or more of a time-based prediction functions that generate a category prediction based on the category data and a difference of submission times of the queries, a rank-based prediction functions that generate a category prediction based on the category data and a rank order by which the queries were received, and a category-based prediction function that generates a category prediction based on the category data.
US09633311B2	Decision tree learning A method of generating a decision tree is provided. A leaf assignment for each proposed split in generating the decision tree is incremented using a Gray code.
US09633308B2	Information processing apparatus, information processing method, and program for evaluating content There is provided an information processing apparatus including an evaluation giving unit that gives an evaluation based on a second user to an item in a list created on a basis of a first user, and a display control unit that controls display of the list, on a basis of the evaluation based on the second user.
US09633304B2	Booster antenna configurations and methods A booster antenna (BA) for a smart card comprises a card antenna (CA) component extending around a periphery of a card body (CB), a coupler coil (CC) component at a location for an antenna module (AM), and an extension antenna (EA) component contributing to the inductance of the booster antenna (BA). At least one of the components may have a pitch which is different than one or more of the other components. A method of wire embedding is also disclosed, by controlling a force and ultrasonic power applied by an embedding tool at different positions on the card body (CB).
US09633303B2	Smart card module arrangement In various embodiments, a smart card module arrangement is provided. The smart card module arrangement includes a carrier, in which a depression is formed, a smart card module, which is arranged in the depression, and a smart card antenna. The smart card antenna can be coupled to the smart card module in a contactless manner.
US09633302B1	RFID integrated circuits with channels for reducing misalignment Embodiments are directed to an RFID tag integrated circuit (IC) having antenna contacts separated by a channel. The channel has a smaller cross-section at its center than at its ends, which facilitates fluid flow from the channel center to the channel ends. During attachment of the IC to an inlay or strap, the channel facilitates the flow of liquid adhesive so as to reduce the turbulence and the propagation velocity associated with the liquid adhesive, thereby reducing misalignment caused by the movement of the IC with respect to the inlay or strap.
US09633301B2	IC module, dual IC card, and method for manufacturing IC module An IC module of the present invention includes: a sheet-like base having a first surface and a second surface and having a first through hole and a second through hole spaced apart from the first through hole; an IC chip provided to the first surface, having a contact communication function and a contactless communication function, and having two terminals formed thereon; a connecting coil formed on the first surface and having two ends; a contact terminal portion provided to the second surface and configured to contact an external contact machine; bridge wiring provided to the second surface, provided at a position overlapping with the first and second through holes, and electrically insulated from the contact terminal portion; a first conductive wire inserted through the first through hole and connecting the first terminal of the IC chip to the bridge wiring; a second conductive wire inserted through the second through hole and connecting the bridge wiring to the first end of the connecting coil; and a third conductive wire connecting the second end of the connecting coil to the second terminal of the IC chip.
US09633299B2	Chip-embedded RFID tag and manufacturing method thereof Provided is a chip-embedded RFID tag, comprising: a first metal casing; a spacer insulator disposed on the first metal casing; a second metal casing disposed on the spacer insulator; a first electrical connecting component, the first metal casing and the second metal casing forming electrical connection via the first electrical connecting component; second electrical connecting components, an RFID chip forming electrical connection with the first metal casing and the second metal casing via the second electrical connecting components; and the first metal casing is separated from the second metal casing by the spacer insulator. Also provided is a method for manufacturing the chip-embedded RFID tag. The chip-embedded RFID tag directly utilizes a metal casing as the antenna of a tag, improving the tag read performance, and also greatly impact resistance and environment resistance performance thereof.
US09633295B2	Far view two-dimensional symbology To encode information into a two-dimensional (2D) symbol, a palette is selected to represent data in the 2D symbol, the palette including a set of shape fillers. A Base number system is selected according to the palette. A rule is selected, where the rule determines a manner of reading an encoded form of the data from the 2D symbol. The rule and the data are encoded as a set of shapes, where the shapes in the set of shapes are configured using the palette and arranged into a grid pattern, with or without visible grid lines, to form the 2D symbol. The 2D symbol is output in a size that matches an area.
US09633294B2	Optical code An optical code, a method for encoding data according to said code, and a method for reading data encoded according to said code. The code formed of an array of equal-size elements, each element being the smallest representation of a data value. Elements being one of the following types of element; a first type where the entire area of the element is a single color, a second type where the area is divided into at least two portions and each portion being a respective color. The array having at least one of the second type of element.
US09633291B2	Method and system for configuring network printers A print control system includes one or more first printers each having a print unit that can print on print media, a second printer that communicates with the first printers via a first network and has a print unit that can print on print media, and a print control server that connects to the second printer through a second network. The control print server sends, to the second printer, configuration control data containing attribute information that can be used to identify one of the first printers. The second printer forwards the configuration control data to the identified first printer and the identified first printer executes a configuration process in response to the configuration control data.
US09633288B2	Image forming apparatus An image forming apparatus includes a density-measuring unit that has a substantially circular measurement field and that measures a density of a to-be-measured image for density measurement, which is moving in a moving direction, and a density-control unit that controls a density of an image and includes a to-be-measured image forming unit that forms the to-be-measured image having a shape following an outline of a density-measurement area defined by a path of the measurement field during a measurement rather than a substantially rectangular shape extending in the moving direction and including a front end of the to-be-measured image in the moving direction, the shape being within the substantially rectangular shape, a density-measuring section that causes the density-measuring unit to measure a density of the to-be-measured image, and a gradation-correction unit that performs gradation correction on the image by using the density of the to-be-measured image measured by the density-measuring section.
US09633287B2	Color information processing method, color information processing apparatus, and color information processing system A color information processing method includes: inputting reference data including color information about each pixel or each pixel group of a reference medium and evaluation target data including color information about each pixel or each pixel group of an evaluation medium by an input means; performing an image matching process of image matching the input reference data and evaluation target data; setting a specific area which is a unit of evaluation and includes a plurality of pixels to each data item subjected to the image matching process; and comparing the color information items about each pixel or each pixel group in the reference data and the evaluation target data in the set specific area to calculate a color difference and performing an averaging process to calculate an average evaluation result for the specific area by a calculation means.
US09633284B2	Image processing apparatus and image processing method of identifying object in image The degree of similarity between corresponding local feature amounts out of a plurality of local feature amounts of the object in the input image and a plurality of local feature amounts of an object in an image registered in advance is obtained. At least one degree of similarity is selected out of the obtained degrees of similarity based on a capturing condition for the object in the input image and a capturing condition for the object in the registered image, and one degree of similarity is derived from the at least one selected degree of similarity. It is determined based on the one derived degree of similarity whether the object in the input image belongs to the same category as the object in the registered image.
US09633279B2	Free space positioning method and system A free space positioning method for estimating an attitude angle of an object in a free space includes: capturing an image of a light source module that includes four light sources to generate a to-be-judged image; analyzing coordinates of the light sources in the to-be-judged image to obtain to-be-judged information; comparing the to-be-judged information with pre-stored light source orientation data to obtain candidate light source orientation data; and estimating an attitude angle of the object according to a pre-stored attitude angle corresponding to each of the candidate light source orientation data.
US09633278B2	Object identification device, method, and storage medium Disclosed is an object identification device and the like for reducing identification error in a reference image which presents an object that is only slightly difference from an object presented in an input image. The object identification device includes a local feature quantity matching unit for calculating geometric transformation information for transformation from a coordinate in a reference image to a corresponding coordinate in an input image, and matching a local feature quantity extracted from the reference image and a local feature quantity extracted from the input image, an input image different area determination unit for transforming the different area in the reference image on a basis of the geometric transformation information about the input image determined to be in conformity by the matching, and determining a different area in the input image corresponding to the different area in the reference image, an input image different area feature quantity extraction unit for correcting a different area in the input image, and extracting a feature quantity from the corrected different area of the input image, and a feature quantity matching unit for matching a feature quantity extracted by the input image different area feature quantity extraction unit and a feature quantity extracted from the different area in the reference image, and outputting a matching result.
US09633277B2	Apparatus and methods for identifying and evaluating bright spot indications observed through optical coherence tomography Exemplary embodiments of the present disclosure include apparatus and methods for identifying bright spot indications observed through optical coherence tomography. The indications can be evaluated, for example, to link risk factors or other conditions to clinically relevant outcomes.
US09633276B2	Blood detection system with real-time capability and method of operation thereof A blood detection system, and a method of operation thereof, including: a camera for obtaining an input image frame; and a processing unit connected to the camera, the processing unit including: an image block module for extracting image blocks from the input image frame, and an automatic blood detection module, coupled to the image block module, for calculating an overall blood probability of the image blocks including: determining a red color dominance probability, determining a red color deviation probability, and determining a red color colorfulness probability.
US09633272B2	Real time object scanning using a mobile phone and cloud-based visual search engine A system for tagging an object comprises and interface and a processor. The interface is configured to receive an image. The processor is configured to determine a key frame. Determining a key frame comprises determining that the image is stable. The processor is configured to determine a tag for an item in the key frame.
US09633271B2	Targeted optical character recognition (OCR) for medical terminology Embodiments of the present invention provide concepts for correcting optical character recognition (OCR) errors from and OCR scan result by sequentially applying an anagram hash (AH) and Levenshtein-Distance (LD) measurement for concurrent character identity-based (machine code) and character shape-based (OCR-Key) corrections. The OCR-Key classifies characters by shape into one or more disjoint and overlapping classes. Similar shaped-based classes appearing in consecutive characters are appended to a cardinality term, a repetition count of the class. The LD measurement groups OCR-Keys and differentiates on both class and cardinality to arrive at a shape-based mismatch error between competing candidate words from an associated dictionary and a target word from the OCR scan. The shape-based LD measurement errors are then functionally merged with the character identity-based deletion, substitution, and insertion errors to find a minimum error for the set of candidate words, corresponding to the preferred candidate word match to the target word.
US09633269B2	Image-based liveness detection for ultrasonic fingerprints A liveness-detection method and/or system is disclosed. A method of detecting liveness can comprise obtaining a single ultrasonic image of a biometric object. The single ultrasonic image can be subdivided into a plurality of overlapping sample blocks. Feature vectors can be extracted in a spatial domain and a frequency domain from each of the plurality of sample blocks. The feature vectors can be compared from each of the plurality of sample blocks to a classification model.
US09633268B1	Method and device for gait recognition Disclose is a gait recognition method, firstly, extracting an initial gait feature of a gait video of a person to be recognized; secondly obtaining a corresponding optimized gait feature according to a trained sub neural network and the initial gait feature; then determining corresponding degrees of similarity according to the optimized gait feature of the person to be recognized and the optimized gait feature of each known person in a matching library, and determining information of the person to be recognized according to information of the known person in the matching library corresponding to the optimized gait feature which has the highest degree of similarity with the optimized gait feature of the person to be recognized.
US09633267B2	Robust windshield detection via landmark localization A system and method that includes training a classifier using uniquely defined landmark points along the windshield region based on an elastic deformation model. The deformation model uses mixtures of trees with a shared pool of parts and can be globally optimized with dynamic programming and still capture much relevant global elastic structure. Once a candidate area is identified in the scene, a learned threshold is applied to the classification score of the candidate area to determine if the candidate area is a windshield. The identified area is then cropped out for further downstream process.
US09633257B2	Method and system of pre-analysis and automated classification of documents Automatic classification of different types of documents is disclosed. An image of a form or document is captured. The document is assigned to one or more type definitions by identifying one or more objects within the image of the document. A matching model is selected via identification of the document image. In the case of multiple identifications, a profound analysis of the document type is performed—either automatically or manually. An automatic classifier may be trained with document samples of each of a plurality of document classes or document types where the types are known in advance or a system of classes may be formed automatically without a priori information about types of samples. An automatic classifier determines possible features and calculates a range of feature values and possible other feature parameters for each type or class of document. A decision tree, based on rules specified by a user, may be used for classifying documents. Processing, such as optical character recognition (OCR), may be used in the classification process.
US09633255B2	Substitution of handwritten text with a custom handwritten font Systems, apparatuses and methods may provide font substitution based on a custom font. In one example, a custom handwritten font may be generated based on a comparison between handwritten sample text and training text. In another example, handwritten original text may be converted to unique machine text based on a substitution of the handwritten original text with the custom handwritten font. Thus, a user's handwriting may be converted to the user's own best or preferred handwriting.

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