| Document | Document Title |
|---|---|
| US09635107B2 |
System and method for managing data delivery in a peer-to-peer network
A system and method for managing content data transfers in a peer-to-peer communications network is described. The system includes a hierarchical arrangement of tracker modules, each tracker module being responsible for managing a tracker domain of network elements. Each tracker module has stored therein a content table including a record of content data available to the network elements within its respective tracker domain. Each tracker module responsible for a tracker domain containing end user peers is configured so that, if a content data request is received from a requesting peer in its respective tracker domain and the requested content is held by other peers in that tracker domain, a list of peers having the content data stored thereon is sent to the requesting peer. If the requested content is not held by enough other peers in that tracker domain, the content data request is transferred to the next tracker module up in the hierarchy. |
| US09635102B2 |
Broker module for managing and monitoring resources between internet service providers
Disclosed is a method for managing resources between a plurality of internet service providers, that includes receiving a set of resources and constraints for each internet service provider of the plurality of internet service providers and allocating resources of the plurality of internet service providers to service client devices of the plurality of internet service providers, wherein at least some resources of a first internet service provider are allocated for servicing a client device that is associated with a second internet service provider. |
| US09635097B2 |
Cloud computing system and method for managing storage resources therein
A cloud computing system and a method therein. The cloud computing system includes: a resource server cluster, where the resource server cluster includes at least two resource servers, each resource server in the resource server cluster has at least one type of resources of computing resources and storage resources, and at least one resource server in the resource server cluster has computing resources and storage resources; a computing resource management module configured to manage the computing resources in the resource server cluster, so as to provide a virtual computing service; and a storage resource management module configured to manage a shared storage resource pool established using the storage resources in the resource server cluster, so as to provide a virtual storage service, where storage resources included in each storage resource pool are from at least two resource servers in the resource server cluster. |
| US09635095B1 |
Data purge distribution and coherency
Systems, methods, and software for operating a content delivery system are provided herein. In one example, a method includes, in a first content delivery node, receiving a purge instruction to purge first content stored in the first content delivery node and responsively purging the first content. Responsive to purging the first content, the method includes transferring a content request for delivery to a second content delivery node, where the content request comprises a request for second content to replace the first content and a revision indicator of the first content. Responsive to the content request, the method includes receiving the second content for storage in the first content delivery node. |
| US09635090B2 |
Device abstraction for page generation
A request for information to be provided as a page of content is received. The page is provided by a server device communicatively coupled to receive the request from a remote requesting device. A requesting physical device class corresponding to the remote requesting device is determined. The server device is configurable to utilize a plurality of styles to be selected by device class. The page of content is constructed with the server device in response to the request based on the device class by dynamically assembling a response by providing device-specific styles that are compatible with the requesting device are selected from the plurality of styles that can be used to provide the content. The dynamically constructed page of content is transmitted to the requesting device. |
| US09635086B2 |
Hierarchal maximum information rate enforcement
A communication system may be configured to transmit information from one or more information sources to a plurality of users over limited capacity media while enforcing one or more Quality of Service policies, such as maximum information rate (MIR) policies. Methods are presented herein for enforcing maximum information rate on two or more levels in a hierarchal and extendable manner, for at least the purposes of maximizing utilization of available capacity over said media and of fair distributing said capacity between all users. Also presented herein is a method for estimating load over said media. |
| US09635081B2 |
Retrieval and display of related content using text stream data feeds
Mechanisms are provided for retrieving and presenting related content using text stream data feeds. Text stream data feeds such as caption information associated with media content or conversations associated with social networking applications are aggregated and used to retrieve related media content, text documents, and advertisements. Text stream data feeds that a user is exposed to may indicate that the user is interested or at least primed for particular types of related content. In particular examples, an inverse vector space search engine is used to determine particular pieces of related content and categories of interest. Post filtering may also be applied to the results. |
| US09635078B2 |
Server, user terminal apparatus, and method for providing streaming data service
A server, a user terminal apparatus, and a method for providing a streaming data service are disclosed. The method of providing streaming data to a user terminal apparatus from a server includes receiving a describe message from the user terminal apparatus via a real-time stream protocol scheme, transmitting a response message containing content execution information about at least one content of a streaming data service and content list information pre-stored in relation to at least one content stored in a storage medium to the user terminal apparatus when the describe message is received, and transmitting streaming data about content of the streaming data service or content stored in the storage medium to the user terminal apparatus when streaming data service request is received from the user terminal apparatus based on the response message. |
| US09635076B2 |
Apparatus and method for storing and playing content in a multimedia streaming system
To store and play contents streamed in a multimedia streaming system, an operating method of a server in the multimedia streaming system includes receiving a transmission request for a Media Presentation Description (MPD) file; and transmitting the MPD file including a flag indicating whether it is possible to generate a media file that is playable by a media file player by concatenating transmitted segments. |
| US09635068B2 |
Systems and methods for multi-context media control and playback
A method for controlling media presentation is performed at a first electronic device having one or more processors and memory storing one or more programs for execution by the one or more processors. A user input requesting a media-control operation to be implemented at a second electronic device distinct from the first electronic device is received. In response to receiving the user input, a first request is sent to a server system to cause the media-control operation to be implemented at the second electronic device, wherein the server system is distinct from the first electronic device. A second request is sent to the second electronic device, wherein the second request is a request to implement the media-control operation at the second electronic device. |
| US09635064B2 |
Apparatus, method, and computer program for streaming media peripheral address and capability configuration
A network-enabled device may include an interface operably connected to an interface of a streaming media device, and be configured to receive a request from the streaming media device. The network-enabled device may also include a processor configured to allow the request from the streaming media device based on a vendor matching policy. |
| US09635061B2 |
System and method for managing conference calls
A conference handling system for an enterprise is provided. The conference handling system includes a status determining module for determining a status of a conference bridge. The conference handling system further includes a conferee routing module for routing a conferee into a session comprising an active session and a waiting session, based on the status of the conference bridge, the conferee routing module further determining a contextual status of the active session. The conference handling system further includes a conferee serving module for providing services to the conferee into the waiting session based on the contextual status of the active session. The conference handling system further includes a conferee inviting module for adding additional conferees with a specific profile in the waiting session and the active session based on absence of a conferee having a similar profile. |
| US09635055B2 |
Encryption levels for secure application containers
Systems, methods, and software described herein provide encryption configurations for secure application containers. In one example, a method of operating a management system to provide encryption configurations to secure application containers includes identifying an encryption configuration from a plurality of encryption configurations for an application container. The method further includes transferring the encryption configuration to the application container, wherein the encryption configuration configures a security layer in the application container to act as an encryption intermediary between an application in the application container and processes external to the application container. |
| US09635054B2 |
Securing communication within a network endpoint
Systems and methods for securing communication within a network endpoint, for example, a meter. The meter may include a communication module and a metrology module where the modules are connected via a communication path that is external to both modules. The modules exchange a pairing key to establish a paired channel of communication. When the communication module receives a communication through a network for establishing a secure channel to the endpoint, the communications module sends some or all of the security data to the metrology module to establish a secure communication from a head-end system through the communication module to the metrology module. |
| US09635052B2 |
Phishing as-a-service (PHaas) used to increase corporate security awareness
An enhanced system is provided through a network such as the Internet that provides integrated network security (phishing) testing and training. The current system increases corporate security of users that can receive and send electronic messages in an entity, by creating and storing a set of phish messages, each classified by a difficulty level. The electronic addresses of the users are acquired and stored. A current difficulty level is set for all users to an initial level. A phish message of the current difficulty level for a given user is selected and sent to the user. The system monitors if the user clicks on or reports the phish message. If the user does not click on the phish message and reports it, the user's current level is increased up to a maximum level. Those that do not pass the test are provided on-line education. The above steps are repeated for all users until the testing is completed providing targeted phishing education to those which need it most. |
| US09635051B2 |
Detecting and preventing flooding attacks in a network environment
A method for processing network traffic data includes receiving a packet, and determining whether the packet is a previously dropped packet that is being retransmitted. A method for processing network traffic content includes receiving a plurality of headers, the plurality of headers having respective first field values, and determining whether the first field values of the respective headers form a first prescribed pattern. A method for processing network traffic content includes receiving a plurality of packets, and determining an existence of a flooding attack without tracking each of the plurality of packets with a SYN bit. |
| US09635041B1 |
Distributed split browser content inspection and analysis
Distributed split browser content inspection and analysis are described. A server, comprising a browser engine, stores a definition of sets of browser policies. A definition of one or more sets of users is stored. The server stores an association with a respective set of browser policies for the one or more sets of users. A request is received from a client browser associated with a user, wherein the client browser is configured to communicate with the server browser engine. The server determines which set of users the user is associated with. The server identifies a first set of browser policies that is associated with the determined set of users and applies the identified first set of browser policies to the request. A determination is made, for one or more browser processes, which browser processes are to be executed by the server browser engine and which browser processes are to be executed by the client browser. |
| US09635035B2 |
Managing user authentication in association with application access
A determination is made that an authentication mechanism is unable to complete an attempt to authenticate, in association with a user attempting to access an application, user credentials. The user credentials include a user identifier and an additional authentication factor. An access allowance rate for the authentication mechanism is identified. The access allowance rate is based on a plurality of prior completed authentication attempts associated with the user identifier. A determination is made that the access allowance rate satisfies a set of criteria. In response to the determination that the authentication mechanism is unable to complete the authentication attempt and further in response to the determination that the access allowance rate satisfies the set of criteria, the user is allowed access to the application. |
| US09635034B2 |
System for authorizing electronic communication of confidential or proprietary data to external entities
A platform for providing authorization of electronic communication of secure data to external entities, e.g., vendors, third parties or the like based on an assessment of the data risk associated with communicating the data to the external entity. The secure data that is to be communicated, in the form of specific data items, are identified as well as the associated security standards. The external identity is assessed to ensure their capabilities to properly meet the enterprise/sender's information security, business privacy and continuity standards, along with applicable industry standards. Based on the results of the assessment, remediation action may be required to address critical vulnerabilities or recommendations may be presented to a decision-making entity to grant authorization to electronically communicate the data in question to the external entity. In response to granting authorization, secure communication channels are allocated and established to allow for communication of the data. |
| US09635030B2 |
Policy enforcement of client devices
A method may include sending, by a client device, an access request to an authentication server device. The access request may include a request to access an administered resource. The method may include in response to the client device not complying with an administrative policy associated with the administered resource, receiving, from the authentication server device, one or more instructions regarding installation of a client application, receiving, by the client device, a client application in accordance with the instructions, and installing the client application on the client device. |
| US09635029B2 |
Role-based access control permissions
Devices, systems, and methods for role-based access control permissions are disclosed. One method includes a policy decision point that receives up-to-date security context information from one or more outside sources to determine whether to grant access for a data client to a portion of the system and creates an access vector including the determination; receiving, via a policy agent, a request by the data client for access to the portion of the computing system by the data client, wherein the policy agent checks to ensure there is a session established with communications and user/application enforcement points; receiving, via communications policy enforcement point, the request from the policy agent, wherein the communications policy enforcement point determines whether the data client is an authorized node, based upon the access vector received from the policy decision point; and receiving, via the user/application policy enforcement point, the request from the communications policy enforcement point. |
| US09635027B1 |
Data transmission using dynamically rendered message content prestidigitation
A communication method and system according to the present invention generates a unique cryptographically secure URI in response to receiving a user post. The user post and URI are stored temporarily. The URI is sent to an intended recipient. In response to a first instance of accessing the URI, the content is retrieved and sent to the intended recipient. The original uploaded content and URI are then deleted. In response to subsequent instances of accessing the URI, random content determined in part by a current environmental state of the communication, is returned. Recent subsequent instances can return thematically similar content. |
| US09635021B2 |
Trusted ephemeral identifier to create a group for a service and/or to provide the service
Devices and methods may provide for generating and/or using a trusted ephemeral identifier (TEID) to create a group for a service, and/or to provide the service. A verifier device may assign a value to a group that is to be created to provide the service, wherein the value may identify the group and may be issued to the prover device for use to generate the TEID value that is unique to the prover device and to participation of the prover device in the group. In addition, a prover device may generate the TEID value, wherein the TEID may be derived from a combination of a unique value that may be generated in a trusted execution environment (TEE) of the prover device and the value that may identify the group. |
| US09635020B2 |
Password-protected physical transfer of password-protected devices
A method for password-protected physical transfer of password-protected devices including at a receiving location, generating at least one security file including an encrypted element generated using a one-way encryption function utilizing at least one secure code, transmitting the at least one security file to a shipping location at which the password-protected devices are located, at the shipping location, using at least one shipping location password, loading the at least one security file into at least one password-protected device, shipping the at least one password-protected device to the receiving location and at the receiving location, employing the at least one secure code to supply an input to the at least one password-protected device and employing the at least one security file to enable establishment of at least one receiving location password for the at least one password-protected device which replaces the at least one shipping location password. |
| US09635016B2 |
Cyber gene identification technology based on entity features in cyber space
A new identification (ID) technology comprising unified and standardized object identification within Cyber Space is disclosed based upon intrinsic properties of the entity to be identified. This Cyber Gene ID (or Cyber ID) technology extracts intrinsic information from either the physical users or their cyberspace counterparts, and such information is categorized into client parameters, dynamic parameters, static parameters, cloud parameters, connection parameters and user parameters. |
| US09635015B1 |
Method to securely connect to and manage X11 applications on a remote system through an HTTP client
A web server authenticates a user with a web client using a database user table and provides a list of new applications, suspended application sessions, and running application sessions. In response to a request for a new application session, a connection is made from an agent server to an application server hosting the requested application, and connection information including a unique session_ID is added to a database session table such that the client can send a user selection for a session_ID to the web server, which associates the requested session_ID to an existing suspended or running application session using the connection database. For additional security, the client is determined to be trusted or untrusted, and if untrusted, connections to the client are made through a forwarding host, which makes connections to the agent server, and the agent server maintains persistent connections from the agent server to the application server. |
| US09635013B2 |
Secure data handling by a virtual machine
A system for executing a virtual machine instance is provided. An executing environment (11) is arranged for creating a virtual machine instance (10). The virtual machine instance (10) comprises an instance authorization unit (1) for receiving an instance authorization credential, wherein the instance authorization credential is uniquely associated with the virtual machine instance (10). A data key unit (2) is arranged for generating a request for a data key, based on the instance authorization credential associated with the virtual machine instance (10). A decryption unit (3) is arranged for decrypting a data item (7) based on the data key. A key server system (6) is arranged for issuing keys to a virtual machine instance (10). An instance authorization providing unit (22) is arranged for providing the instance authorization credential to the virtual machine instance (10). |
| US09635012B2 |
Method for deriving a verification token from a credential
A method for deriving a verification token from a credential may be provided. The credential may be a set of attributes certified by an issuer to a user using a public key of the issuer. The method may comprise generating the verification token out of the credential and binding the verification token to a context string, wherein the verification token may comprise at least one commitment. A commitment may be a blinded version of an attribute. The method may also comprise generating an opening key for the verification token enabling a generation of a confirmation for a validity of the attribute. |
| US09635004B2 |
Systems and methods for segment integrity and authenticity for adaptive streaming
System and method embodiments are provided for segment integrity and authenticity for adaptive streaming. In an embodiment, the method includes receiving at a data processing system a segment of a media stream, determining, with the data processing system, a digest or a digital signature for the segment, and comparing, with the data processing system, the digest/digital signature to a correct digest or a correct digital signature to determine whether the segment has been modified. |
| US09635003B1 |
Method of validating a private-public key pair
A key pair validation method provides for a first party to generate a seed to define a private key, a public key, a session key and a validation field for the purpose of performing a cryptographic activity with a second party. The validation field is determined by encrypting the first party seed. The second party receives the first party public key and the validation field from the first party. The second party calculates a session key and utilizing the calculated session key, decrypts a cipher text to recover the first party's seed and the first party's private and public key. The recovered first party public key is compared to the received first party public key. If the received and recovered public keys match, the private-public key pair received from the first party is validated and the second party proceeds with the cryptographic task. If the received and recovered public keys do not match, the second party simply reports to the first party that the cryptographic task failed. |
| US09635000B1 |
Blockchain identity management system based on public identities ledger
The invention describes an identity management system (IDMS) based on the concept of peer-to-peer protocols and the public identities ledger. The system manages digital identities, which are digital objects that contain attributes used for the identification of persons and other entities in an IT system and for making identity claims. The identity objects are encoded and cryptographically encapsulated. Identity management protocols include the creation of identities, the validation of their binding to real-world entities, and their secure and reliable storage, protection, distribution, verification, updates, and use. The identities are included in a specially constructed global, distributed, append-only public identities ledger. They are forward- and backward-linked using the mechanism of digital signatures. The linking of objects and their chaining in the ledger is based on and reflect their mutual validation relationships. The identities of individual members are organized in the form of linked structures called the personal identities chains. Identities of groups of users that validated identities of other users in a group are organized in community identities chains. The ledger and its chains support accurate and reliable validation of identities by other members of the system and by application services providers without the assistance of third parties. The ledger designed in this invention may be either permissioned or unpermissioned. Permissioned ledgers have special entities, called BIX Security Policy Providers, which validate the binding of digital identities to real-world entities based on the rules of a given security policy. In unpermissioned ledgers, community members mutually validate their identities. The identity management system provides security, privacy, and anonymity for digital identities and satisfies the requirements for decentralized, anonymous identities management systems. |
| US09634999B1 |
Mobile device key management
Mobile device key management is disclosed. A master key is secured using a password-based key to generate a first encryption information. The password-based key is generated based at least in part on a password associated with a mobile device. The master key is also secured using an unlock key to generate a second encryption information. The unlock key is stored at a server, and in certain cases is not stored on the mobile device. The first encryption information and the second encryption information are stored on the mobile device. The mobile device is configured to extract the master key from the first encryption information using the password. In the event that the master key is not extracted using the password, the mobile device is configured to extract the master key from the second encryption information using the unlock key received from the server. |
| US09634993B2 |
Internet-based proxy service to modify internet responses
A proxy server receives from a client device a request for a network resource that is hosted at an origin server for a domain. The request is received at the proxy server as a result of a DNS request for the domain resolving to the proxy server. The origin server is one of multiple origin servers that belong to different domains that resolve to the proxy server and are owned by different entities. The proxy server retrieves the requested network resource. The proxy server determines that the requested resource is an HTML page. The proxy server scans the HTML page to locate one or more modification tokens that each indicates content that is subject to being modified. For at least one of the located modification tokens, the proxy server automatically modifies at least a portion of the content of the HTML page that corresponds to that modification token. The proxy server then transmits the modified HTML page to the client device. |
| US09634992B1 |
Probabilistic duplicate detection
A first unclassified uniform resource locator (URL) is received. An originally primary bloom filter is initialized. A second bloom filter is initialized. In response to receiving a “no match” result from querying the primary bloom filter for the received first unclassified URL, insert operations are performed on both the originally primary bloom filter and the secondary bloom filter. At a time subsequent to inserting the first unclassified URL into both the originally primary and secondary bloom filters, a determination is made that a false positive rate associated with the originally primary bloom filter exceeds a threshold. In response to the determination, the secondary bloom filter is designated as a replacement primary. |
| US09634987B2 |
Obtaining a MAC address from an external source
A non-transitory computer readable medium storing instructions which, when executed on one or more processors, cause performance of operations. The operations include: receiving a first message from a device; determining, in response to the first message, a media access control (MAC) address of the device; and transmitting, in response to the first message, a second message comprising the MAC address to the device. |
| US09634984B2 |
Method for configuring DNS server and driving apparatus of wireless data access device
A method for configuring a Domain Name System (DNS) server and a driving apparatus of a wireless data access device are provided. The method includes: after a wireless data access device is successfully networked with a terminal, a driving apparatus of the wireless data access device judging whether a user has set a DNS server address in the terminal; and if yes, the driving apparatus not automatically configuring a DNS server address; otherwise, the driving apparatus setting a DNS server address obtained from the wireless data access device in the terminal. With the present invention, the problem in related technologies that the terminal cannot be guaranteed to use a DNS server manually configured by a user always in preference to a DNS server automatically configured by a driver is solved, normal use of IPv4 and IPv6 DNS servers is ensured, and the stability and accuracy of a system are improved. |
| US09634983B2 |
IP address and domain name automation of virtual infrastructure
Provisioning an Internet Protocol address is disclosed. A request to provision an Internet Protocol address to a virtual resource is received. An Internet Protocol address is automatically determined to allocate to the virtual resource. An Internet Protocol Address Management appliance is used to automatically allocate the determined Internet Protocol address to the virtual resource. |
| US09634982B2 |
Utilizing multiple interfaces when sending data and acknowledgement packets
Utilizing multiple network interfaces when sending data and acknowledgement packages comprises, in a low power and lossy network (LLN) or other network, a sender device comprises two or more network interfaces for communicating with one or more recipient devices. The sender device assesses the transmission capabilities of the network interfaces to determine data rates available for each interface. The sender device specifies which network interface will be used to transfer data and which network interface will be used to receive an acknowledgement from the recipient device. The sender device selects the network interface with the larger data capacity for transmitting a data packet and the network interface with the smaller data capacity for receiving an acknowledgement. The data transmission and the acknowledgement transmission may be transmitted simultaneously. The recipient device uses transmission parameters received from the sender device to determine the data rate with which to transmit the acknowledgement. |
| US09634980B2 |
Systems and methods for using social network analysis to schedule communications
Systems and methods for improving the effectiveness of communications over a social network. A method for controlling network communication, comprises analyzing a social network in response to a request made by a user to send a message to a node in the social network, delaying for a period of time sending of the message based on a result of the analyzing, and sending the message to the node in the social network after the period of time has elapsed. |
| US09634978B2 |
Systems and methods for improving efficiency of electronic transmission of messages
Systems and methods for improving the efficiency of propagating electronic messages are provided. In some embodiments, a feed of activities on a network such as an online social network (OSN) is analyzed to determine influenced activity probabilities and intrinsic activity probabilities for participants in the network. A Helmhotz Green's Function matrix is determined in order to calculate an overall influence weight for each participant in the network. A Woodbury-Sherman-Morrison formula may be used to accelerate computation of the Helmholtz Green's Function matrix, thus allowing efficient updates to the overall influence weights based on newly monitored activities. The participants with the highest overall influence weights may be selected to propagate a new message, thus providing the greatest likely distribution of the message with the fewest originating transmissions. |
| US09634969B2 |
Real-time messaging method and apparatus
A system and method for the late-biding of time-based media in real-time. With late binding, the sender may create time-based media before or at the same time an active delivery route to the recipient is discovered. As soon as the route becomes available, the media is transmitted. The existing DNS and email infrastructure is possibly used for route discovery, while any real-time transmission protocol may be used for the actual delivery of the media. “Progressive” emails may also be used for the real-time delivery of time-based media. |
| US09634963B2 |
Method and system for handling message on instant messaging open platform
Various embodiments provide a method and system for handling a message on an instant messaging (IM) open platform. In an exemplary method, a message sent to a network application can be received. The network application can be an application plugged in the IM open platform. The received message can be pushed to an access address of the network application. A reply message returned by the network application based on the message can be received and forwarded. An exemplary system for handling a message on an instant messaging (IM) open platform can include a receiving module, a pushing module, and/or a reply processing module. |
| US09634961B2 |
Automated configuration of network device
Some embodiments provide a system that includes a backup device and a plurality of switches coupled to the backup device. A switch in the plurality of switches may be coupled to the backup device using at least a special link. The at least special link may be configured by a replacement device when the switch coupled to the backup device using the at least the special link fails, the failed switch is replaced with the replacement device, and the replacement device receives configuration data associated with the special link from another switch of the plurality of switches via a simple link. The simple link may allow communication of data without configuration of the simple link. The backup device may be configured to manage backup data associated with the plurality of switches. |
| US09634959B2 |
High-density, fail-in-place switches for computer and data networks
A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards. |
| US09634954B2 |
Switchable business feature with prices and sales integration
The present disclosure describes methods, systems, and computer program products for providing a remote device remote access to software functions. One method includes providing a list of second software functions to a first remote device that are not accessible by the remote device, wherein the remote device has remote access to a first software function; receiving from the remote device a request for a software function of the provided list of second software functions and upon receiving the request, providing the remote device remote access to the requested software function by transmitting access data for the requested software function to the remote device; and after providing the remote access to the requested software function, receiving from the remote device a deactivation command for the requested software function or the first software function and, based on the deactivation command, deactivating the remote access of the remote device to the requested software function or the first software function. |
| US09634953B2 |
Scheduler for deciding final output queue by selecting one of multiple candidate output queues and related method
A scheduler performs a plurality of scheduler operations each scheduling an output queue selected from a plurality of output queues associated with an egress port. The scheduler includes a candidate decision logic and a final decision logic. The candidate decision logic is arranged to decide a plurality of candidate output queues for a current scheduler operation, regardless of a resultant status of packet transmission of at least one scheduled output queue decided by at least one previous scheduler operation. The final decision logic is arranged to select one of the candidate output queues as a scheduled output queue decided by the current scheduler operation after obtaining the resultant status of packet transmission of the at least one scheduled output queue decided by the at least one previous scheduler operation. |
| US09634952B2 |
System and method for dynamic bandwidth adjustments for cellular interfaces in a network environment
A method is provided in one example embodiment and may include determining a predicted average throughput for each of one or more cellular interfaces and adjusting bandwidth for each of the one or more of the cellular interfaces based, at least in part, on the predicted average throughput determined for each of the one or more cellular interfaces. Another method can be provided, which may include determining a variance in path metrics for multiple cellular interfaces and updating a routing table for the cellular interfaces using the determined variance if there is a difference between the determined variance and a previous variance determined for the cellular interfaces. Another method can be provided, which may include monitoring watermark thresholds for a MAC buffer; generating an interrupt when a particular watermark threshold for the MAC buffer is reached; and adjusting enqueueing of uplink packets into the MAC buffer based on the interrupt. |
| US09634951B1 |
Autonomous agent messaging
Apparatus and methods are disclosed for generating, sending, and receiving messages in a networked environment using autonomous (or semi-autonomous) agents. In one example of the disclosed technology, a method of collecting data from an agent executing on a host computer connected to one or more agent data consumers via a network connection includes collecting host data, the collecting occurring whether or not the agent can currently send data via the network connection. When the agent cannot send data via the network connection, the agent spools at least a portion of the collected host data in a spooler. When the agent can send data via the computer network, the agent sends at least a portion of the spooled host data to at least one of the agent data consumers. |
| US09634950B2 |
Ethernet media converter supporting high-speed wireless access points
Disclosed are method and system for Ethernet media conversion supporting high-speed wireless access points. The method includes receiving at each of a plurality of input-side Ethernet modules in a media converter, a plurality of input data streams at a first data rate. In the media converter each of the plurality of input data streams may be aggregated into an output data stream at a second data rate. The output data stream may then be transmitted at the second data rate from an output-side Ethernet module in the media converter. Each of the input data streams may be received from an Ethernet switch, and the output data stream may be transmitted to a wireless access point. In one exemplary implementation, each of the input-side Ethernet modules may include a 1G PHY, while the output-side Ethernet module may include one or both of a 2.5G PHY and a 4G PHY. |
| US09634948B2 |
Management of addresses in virtual machines
Methods for managing an address on a switching device, managing an address on a network switch, and screening addresses in a cloud computing environment are provided. One embodiment is directed towards a computer-implemented method for managing an address on a switching device that is communicatively coupled to a plurality of virtual machines. The method includes accessing an address pool that includes an assigned address for each virtual machine from the plurality of virtual machines. The method includes determining, on the switching device, a used address for the virtual machine from the plurality of virtual machines. The method includes determining whether the used address is matching the assigned address for each virtual machine. The method also includes routing traffic from the virtual machine to a hypervisor in response to the used address matching the assigned address. |
| US09634942B2 |
Adaptive scene complexity based on service quality
Content, such as a video game, may be delivered by a content provider to a destination using, for example, streaming content delivery techniques. The transmission of the content may be monitored in order to determine transmission conditions such as a quality of the network connection from the content provider to the destination. The determined transmission conditions may then be used to determine adjustments to a complexity of various scenes associated with the content. For example, in some cases, when transmission conditions are unfavorable, scenes may be adjusted by reducing a complexity of the scenes. |
| US09634937B2 |
Relay system and relay device
A ring control unit controls the ring network by transmitting and receiving a control frame through ring ports, and receives an address table deletion command via the control frame. When a first deletion command is received, an address table processing unit prohibits a learning process to the address table and then starts deleting the address table. Then, when a N-th (N is an integer of 2 or more) deletion command is received in a period before the completion of the deletion of the address table, the address table processing unit continues to execute the deletion of the address table. |
| US09634936B2 |
Service chaining across multiple networks
In some examples, a controller comprises one or more processors; a control unit configured to obtain, from a router in a first network, a route that specifies a next hop to an address prefix reachable by the first network; and a service chain unit configured to generate a modified route that specifies a service node as the next hop for the address prefix, wherein the service node is external to the first network, and wherein the control unit is further configured to send the modified route to a second network, the modified route marked with an import route target configured for a provider edge router of the second network so that traffic from the first network and destined for the second network is forwarded to the service node. |
| US09634931B2 |
Providing network communications using virtualization based on protocol information in packet
A method of providing network communications includes spawning a virtual machine that virtualizes network capabilities of the device such that a virtual network connection is provided; using the virtual network connection, transmitting a packet to a first node using a first routing protocol for communication to a destination device; setting a timer, the timer having a value corresponding to an amount of time greater than an average response time of the destination device; and, upon expiration of the timer, transmitting the packet to a second node using a second routing protocol for communication to the destination device. |
| US09634927B1 |
Post-routed VLAN flooding
A hierarchical lookup forwarding model to induce a Layer (L2) forwarding look up in a post-routed virtual local area network (VLAN). In one example, a line card of a networking device receives a packet for routing from a first virtual local VLAN to a second VLAN. The line card determines that the packet is associated with a host route having a corresponding incomplete Layer 3 (L3) adjacency. The line card steers the packet to a fabric module of the networking device. The fabric module performs an L2 lookup on the packet and floods the packet to one or more of line cards of the networking devices. The one or more line cards flood the packet on a plurality of external ports of the networking device. |
| US09634925B2 |
Technique for network routing
A technique for routing one or more service tunnels in a telecommunications backhaul network (110) is provided. The telecommunications backhaul network has a first routing path (132) and a second routing path (134). As to a method aspect of the technique, data of the one or more service tunnels is transmitted on the first routing path (132). A reduction in transmission capacity is detected on the first routing path (134) by means of a first routing path condition. The first routing path condition indicates a state of the first routing path (132). A second routing path condition is determined indicating a state of the second routing path (134) in response to the detected reduction in transmission capacity on the first routing path (132). It is decided upon rerouting one or more of the service tunnels from the first routing path (132) to the second routing path (132) based on both the first routing path condition and the second routing path condition. |
| US09634921B2 |
Wearable device coupled by magnets positioned in a frame in an interior of the wearable device with at least one electronic circuit
A wearable device is provided with a wearable device structure. A frame is positioned in an interior of the wearable device structure. A plurality of magnets are provided. At least a portion of the plurality of the magnets are coupled to the frame. Electronic circuitry is positioned in an interior of the wearable device structure adjacent to the frame. |
| US09634918B2 |
Invalidation sequencing in a content delivery framework
A computer-implemented method includes providing, at a first time and to a first group of CD services in a CDN, invalidation information relating to at least one resource; and providing the invalidation information, at a second time distinct from the first time and to a second group of CD services in the CDN, the second group of CD services being substantially distinct from the first group of CD services. |
| US09634917B2 |
Method and system for detecting use of wrong internet protocol address
An example embodiment includes a method and a network device for detecting use of wrong IP addresses by wireless client devices. Specifically, the network device matins a range of valid IP addresses for a particular IP subnet. Also, the network device receives a message from a wireless client device by an access point on the particular IP subnet. The network device then determines a source IP address in the message received on the particular IP subnet. Further, the network device determines that the source IP address does not match the range of valid IP addresses for the particular IP subnet. Responsive at least to determining that the source IP address does not match the range of valid IP addresses for the particular IP subnet, the network device transmits at least one message that causes the wireless client device to request a new IP address. |
| US09634914B2 |
Terahertz wireless communications-based peer-to-peer communications methods and systems
Terahertz wireless communications-based peer-to-peer communications methods and systems are provided. A system may comprise at least two monitoring nodes. A monitoring node may include a terahertz transceiver for transmitting and receiving monitoring data and connection request information. A monitoring node may be connected to a control module for use in controlling the monitoring node. A monitoring node may be connected to a terahertz transceiver. The system may provide increased transmission capacity, improved directionality of wireless communications, and peer communications between monitoring nodes. |
| US09634912B2 |
Computer, resource usage calculation method, and resource usage calculation program
Provided is a computer, comprising a memory which stores a program and a processor which executes the program which is stored in the memory for each predetermined processing unit, with which a computer resource usage is calculated by a process which is executed for each predetermined processing unit. The computer resources include overlapping resources which are used in an overlapping manner when the program is executed and non-overlapping resources which are not used in an overlapping manner when the program is executed. When calculating the computer resource usage by the process which is executed for each predetermined processing unit, the processor determines, by analyzing the computer resources, the overlapping resources which are used by the process and the non-overlapping resources which are used by the process, and calculates the computer resource usage by the process on the basis of the result of the determination. |
| US09634911B2 |
Communication device event captures
A user interaction or a timer event is detected in a communication device. A timestamp is associated with the user interaction or the timer event. In response to detecting the user interaction or the timer event in the communication device, the user interaction or the timer event and the timestamp are stored in a packet log file associated with the communication device. The packet log file can also include a packet trace of packets that are sent to and received by the communication device. This allows the user interactions and/or the timer events to be displayed chronologically in relation to the packets sent to and received by the communication device. |
| US09634904B2 |
Framework supporting content delivery with hybrid content delivery services
A framework supporting content delivery includes a plurality of devices, each device configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include hybrid CD services. |
| US09634902B1 |
Bloom filter index for device discovery
Identifying network devices having specified traits using a multi-level hierarchical data structure. Bloom filters representing traits of network devices are received and their bit vectors are decomposed into successive bytes. For each byte except the last one, memory for storing a pointer to memory on the next level is allocated on the level corresponding to the byte. The pointer storage is labeled by the value of the next byte. A pointer to the allocated memory is stored in the pointer storage on the previous level that was labeled by the value of the current byte. For the last byte, memory for storing references to network devices is allocated on the last level. A pointer to the allocated memory is stored in the pointer storage on the second-to-last level that was labeled by the value of the last byte. A reference to the network device is stored in the allocated memory. |
| US09634900B2 |
Declarative approach to virtual network creation and operation
A network controller may receive a request from an application via an application programming interface (API), wherein the request comprises program codes written in a declarative programming language, and wherein the program codes describe at least some aspects of a virtual network (VN). The network controller may further parse the program codes into internal objects of the network controller, with the internal objects representing the aspects of the VN described by the program codes. The network controller may then manage the VN according to the internal objects translated from the program codes. |
| US09634899B2 |
Function update method and function update system
A function update method improving household appliance functions by enabling new and existing household appliances to perform cooperative processing. In the method, a server stores registration information listing identification information for each household appliance owned by a user, combination information listing combinations each including household appliances performing cooperative processing, and update information for each household appliance in each combination, for updating a function for performing the cooperative processing. The method includes: receiving, from a household appliance having identification information not listed in the registration information, a request to list the identification information in the registration information, and listing the identification information in the registration information; selecting a combination listed in the combination information, the combination including the household appliance and all other household appliances in the combination being registered in the registration information; and transmitting update information to each household appliance requiring a function update in the combination. |
| US09634898B2 |
Communication management system, communication terminal, communication system, and recording medium storing control program
A management system modifies a group of one or more member communication terminals indicated by first candidate information of a first communication terminal in response to information indicating to modify the first candidate information of the first communication terminal to generate second candidate information of a second communication terminal. |
| US09634895B2 |
Operating a dual chipset network interface controller (‘NIC’) that includes a high performance media access control chipset and a low performance media access control chipset
Operating a dual chipset network interface controller (‘NIC’) that includes a high performance media access control chipset and a low performance media access control chipset, including: determining, by a NIC control module, an amount of network traffic being processed by the NIC; determining, by the NIC control module, whether the amount of network traffic being processed by the NIC exceeds a predetermined threshold; responsive to determining that the amount of network traffic being processed by the NIC exceeds a predetermined threshold, configuring, by the NIC control module, the NIC to utilize the high performance media access control chipset for data communications operations; and responsive to determining that the amount of network traffic being processed by the NIC does not exceed the predetermined threshold, configuring, by the NIC control module, the NIC to utilize the low performance media access control chipset for data communications operations. |
| US09634892B2 |
Configuring a vehicle to receive content data
A communication system and methods of using the communication system is described. One method includes configuring a telematics unit in a vehicle with at least one access point name (APN). The steps of the method include: configuring the telematics unit with a default APN prior to a legal transfer of possession of the vehicle; and thereafter, activating the telematics unit for the provision of content data in connection with the legal transfer of possession of the vehicle, wherein the activating includes replacing the default APN of the telematics unit with a geographically-specific APN. |
| US09634891B2 |
Discovery of management address/interface via messages sent to network management system
A network management application executing on a first computing system may discover a first interface on a network device and establish a connection with the network device over the first interface. In response, an identification (ID) value is generated and sent, over the connection established with the network device over the first interface, in a message that includes the ID value. The message sent to the network device over the first interface provokes the device to send a response message to the network management application over a second interface. The second interface may generally correspond to a preferred management interface of the network device. |
| US09634889B2 |
Method for migrating service of data center, apparatus, and system
A method for migrating a service of a data center is disclosed. When an active data center is faulty, a tunnel processing device disables a locally-saved tunnel entry of a server in the active data center. After receiving a service access request packet from a customer edge router, the tunnel processing device acquires an IP address of a tunnel processing module deployed on a server in a standby data center according to an IP address of a destination virtual machine, encapsulates the service access request packet and routes the encapsulated packet to the tunnel processing module, so as to migrate a data center service from the active data center to the standby data center. |
| US09634887B2 |
System, method and computer-readable medium for using a plurality of virtual machines
A system includes a first server configured to execute a first virtual machine among a plurality of virtual machines belonging to a first virtual network, the plurality of virtual machines identified by a common address in the first virtual network; and a second server; and a switch including a first port coupled to the first server and a second port coupled to the second server, and configured to: store an association between the common address and the first port; and update the association to associate the common address with the second port in place of the first port when the first virtual machine is migrated from the first server to the second server. |
| US09634886B2 |
Method and apparatus for providing tenant redundancy
Various embodiments provide a method and apparatus for providing a tenant redundancy architecture that does not require reserving a complete set of duplicate resources, pushing complexity into the application domain or require the application to communicate simultaneously with two active tenant instances. In particular, a shadow tenant is created that has the functionality of the service tenant but is hidden from the rest of the network until activated. |
| US09634885B2 |
Control target flow specifying method and control target flow specifying device
A computer-readable recording medium stores therein a program for causing a computer to execute a process. The process includes detecting a failure of a flow indicating a route on a network through which data of each tenant service provided by a tenant via a network flows; and specifying a control target flow influenced from the flow in which the failure has been detected based on association information in which each tenant service is associated with a flow of each tenant service. |
| US09634884B2 |
Monitoring apparatus, monitoring method and monitoring program
An apparatus monitors a communication system including at least one communication device. The monitoring apparatus includes a memory, a processor. A second virtual system is generated by changing a first virtual system determined according to a combination of an arrangement of a plurality of virtual machines arranged in the at least one communication device, and a communication path between the plurality of virtual machines. The memory stores system information that represents an arrangement and a communication path of virtual machines used in the second virtual system. The processor receives the fault information that reports an occurrence of a fault. The processor identifies the fault information as being generated in the virtual machine within the first virtual system when a specified fault detected in a case where the fault information is transmitted from any of the virtual machines within the second virtual system represented by the system information is not detected. |
| US09634881B2 |
Reliability in distributed environments
Technologies are generally described herein for deploying an application in a ubiquitous computing system. An allocation module may receive a command to deploy the application having multiple application modules to various nodes in the ubiquitous computing system. For at least one application module, the allocation module may identify, within the ubiquitous computing system, a set of heterogeneous nodes capable of executing the application module and having greater diversity over other sets of nodes in the ubiquitous computing system. The allocation module may deploy the application to the set of heterogeneous nodes. |
| US09634873B1 |
BPSK demodulator
The present invention discloses BPSK demodulator, which uses a delay circuit to delay a BPSK signal and mixes the delayed BPSK signal with the undelayed BPSK signal to output a demodulated data signal, and which uses a phase rotation circuit and the demodulated data signal to obtain a carrier clock signal. The operating frequency of the delay circuit is the same as or 0.5 times the carrier frequency. Therefore, the present invention consumes less power and is realized by digital circuits and analog circuits. |
| US09634872B2 |
Multimode receiver and receiving method therefor
Disclosed is a multimode receiver, comprising: an antenna system configured to receive a signal sent by a base station and select a receiving circuit front end according to the frequency band of the signal; more than one receiving circuit front end configured to perform down-conversion frequency processing on a signal sent by the antenna system and send the processed signal to an I/Q demodulator; the I/Q demodulator configured to demodulate the signal sent by the receiving circuit front ends and send the demodulated signal to a baseband unit; and the baseband unit configured to decode the demodulated signal. Disclosed is a receiving method for a multimode receiver. By adopting the present invention, one set of receiving circuit front ends can be utilized for signals of the same frequency band and different modes, decreasing the number of radio-frequency chips, and lowering the cost. |
| US09634866B2 |
Architecture and method for hybrid circuit-switched and packet-switched router
Techniques and mechanisms for performing circuit-switched routing and packet-switched routing for network communication. In an embodiment, a router evaluates control information of a packet received by the router, the evaluation to detect whether the packet includes data for a sideband communication. Based on the evaluation, the router performs a selection from among a plurality of modes of the router, the plurality of modes including a first mode to route the packet for packet-switched communication of sideband data in a network. The plurality of modes also includes a second mode to configure a circuit-switched channel according to the packet. In another embodiment, the router determines a direction for routing a packet in a hierarchical network, wherein the determining of the direction is based on a level of the router in a hierarchy of the hierarchical network. |
| US09634865B2 |
Method of providing quick answer service in SIP message service system
Disclosed is an SIP based message service. If a message service server receives a quick answer addition request from a user terminal, the server detects a quick answer text and a quick answer ID, assigned corresponding to the quick answer text, in the quick answer addition request, and stores the detected quick answer text and quick answer ID in a quick answer list corresponding to the user terminal's user, thereby implementing quick answer addition. Further, if the message service server receives a quick answer sending request from the user terminal, the server detects a quick answer text, corresponding to a user ID contained in the quick answer sending request, in the quick answer list, configures a message containing the detected quick answer text, and sends the configured message to a recipient user terminal, thereby implementing quick answer sending. |
| US09634864B2 |
Dynamic admission control for media gateways
A Media Gateway, in connection to a backbone, measures a packet loss and/or jitter, receives a call and notices an indication that a higher packet loss and/or jitter is acceptable. The Media Gateway decides, based on said measured packet loss or jitter and said indication, whether the call is admitted to be routed via said backbone even though the packet loss or jitter is above a predefined threshold. A Mobile Switching Centre Server in connection to a backbone, receives a call set-up, detects that a call set-up should be performed by a Media Gateway even if the packet loss or jitter is above a predefined threshold, and provides an indication to the Media Gateway that a higher packet loss or jitter is acceptable. |
| US09634860B2 |
Method and apparatus for communicating in wind farms
In the method according to the invention for communicating between installations, which are organized in an order according to a sortable feature, for example installation numbers, in a wind farm, in which information transmitted by an installation in the form of a message is received by all other installations in the wind farm, a cyclically recurring, temporal transmission interval is set up. A point in time in the transmission interval at which the installation can transmit a message is assigned to each installation on the basis of the position thereof in the order, wherein points in time are organized from the start of the transmission interval, starting from the installation number at the first position in the order, in accordance with the position in the order. The start of the transmission interval is synchronized in all installations using a message from the installation at the first position in the order. |
| US09634859B2 |
Method for detecting a defective node
Method for detecting a defective node which is connected to a bus, the node incrementing an internal error counter in a normal operating state when an error is detected, and the node switching to an isolated operating state, in which the node does not exchange any messages via the bus if the internal error counter of the node exceeds a predetermined error threshold value, and the node switching from the isolated operating state to the normal operating state when a condition is fulfilled and that change in state being detected, and the node being detected as being defective if a rate of the detected state changes exceeds an adjustable change rate or a number of detected state changes exceeds an adjustable state change threshold value. |
| US09634856B2 |
Air-conditioning system and relay device
In an air-conditioning system, an outdoor unit and an indoor unit communicate through a relay device, including a plurality of communication ports; a plurality of communication networks having logical connection relationships with the respective communication ports; and a plurality of nodes having logical connection relationships with the respective communication networks. The plurality of nodes are each associated with one of the outdoor unit and the indoor unit. Among the plurality of nodes, a certain node is set as a first node, and another certain node different from the first node is set as a second node. The relay device executes transfer processing of transferring a communication frame from the first node to the second node, and then if the relay device does not receive a reception acknowledgment signal from the second node, limits a number of re-transmission times when the relay device re-transfers the communication frame to the second node. |
| US09634850B2 |
System and method for providing smart grid communications and management
A method is provided in one example embodiment and includes receiving a request for a service that involves phasor measurement unit (PMU) data; identifying a service device in a network to perform the service; and multicasting one or more results of the service to a group of subscribers identified by a multicast group address. In more particular embodiments, particular PMU data is redirected to the service device via a service insertion architecture (SIA) protocol. In addition, the service can include replicating packets and masking a subset of traffic for forwarding to a first hop router of the network. In certain example instances, metadata is used in order to apply the service to certain traffic propagating in the network. |
| US09634845B2 |
Session switching during ongoing data delivery in a network
There is described a method of delivering data from a server to a client device in a network. Data packets with a first source address are sent in a first session from the server to the client device. A Session Switch Information (SSI) message, including a second source address, is sent from the server to the client device. A second session is configured between the server and the client device, and data packets with a second source address are sent in the second session from the server to the client device. The same transport protocol may be used for both sessions, and the method can be 10 used to switch between unicast and multicast delivery. |
| US09634844B2 |
Detection scheme for four wire pair Power Over Ethernet system
In a method performed by a PoE system, a PSE is able to detect whether a PD is compatible for receiving power via four wire pairs in the standard Ethernet cable. The PSE provides a current limited voltage to a first and second pair of wires in the cable, during a detection phase, to detect a characteristic impedance of the PD. In the PSE, a first resistor is connected to a third wire pair and a second resistor is connected to a fourth wire pair. During the detection phase, the PSE detects the relative currents through the resistors. If the currents are the same, then the PSE knows the PD is able to receive power via the four wire pairs. The PSE then applies the full PoE voltage to the first and second wire pairs and connects the third and fourth wire pairs to a low voltage via a MOSFET. |
| US09634843B2 |
Apparatus and methods for the secure transfer of electronic data
An embodiment of the invention provides a method for processing a secure electronic transaction over a network from a sender to a receiver, which includes the process of generating a first unique representation of information included in the transaction, encrypting the information with a first encryption layer, and forming an encryption packet which includes the first encryption layer. The encryption packet is then transmitted over a network and then received the by a receiver. The authenticity of the encryption packet is verified and a receipt is generated using the information included in the encryption packet. The receipt is then transmitted to an electronic postmark server which verifies authenticity of the receipt. A postmarked receipt is then created by the electronic postmark server and a copy is sent to the sender an/or the receiver. |
| US09634841B2 |
Computer implemented method and a computer system to prevent security problems in the use of digital certificates in code signing and a computer program product thereof
A computer implemented method including a software distributor signing via a first server at least one software file using a digital certificate with a digital signature and at least one user via a computing device acquiring a copy of the signed software file. The digital certificate to be used is previously recorded in a second server in communication with the first server, the digital certificate to be recorded being provided by the software distributor upon a registration of the latter in the second server and including information obtained from a trust certificate chain associated to the digital certificate when performing the registration. The second server generates, upon a request made by the software distributor, a hashstamp of the signed software file. |
| US09634835B2 |
Apparatus and method for the detection of attacks taking control of the single photon detectors of a quantum cryptography apparatus by randomly changing their efficiency
An apparatus and method for revealing both attack attempts performed on the single-photon detector(s) of a quantum cryptography system and Trojan horse attack attempts performed on quantum cryptography apparatus containing at least one single photon detector. The attacks detection relies on both the random modification of the setting parameters of the said single-photon detector(s) and the comparison of the measured detection probability values for each setting parameter with the expected detection probability values. The modified parameter of the single-photon detector can be its efficiency or its timing of activation for example. |
| US09634830B2 |
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. |
| US09634828B2 |
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. |
| US09634824B2 |
Method and apparatus for providing a synthetic system using a GPS clock
A method and apparatus of providing a configurable computer system capable of being modeled are disclosed. The system, in one embodiment, includes a configurable component and a clock distributor. The configurable component includes multiple programmable devices arranged in a predefined configuration. The predefined configuration, for example, is a cubical shape having multiple neighboring nodes. The configurable component is capable of being modeled in accordance with policies from a system program for data transmission. The clock distributor further includes a first clock element, which provides long-term accuracy, and a second clock element, which provides short-term accuracy. |
| US09634818B2 |
Method and apparatus for feeding back and receiving acknowledgement information of semi-persistent scheduling data packets
The application relates to radio communications and discloses a method and apparatus for feeding back and receiving acknowledgment (ACK) information of semi-persistent scheduling (SPS) data packets. The method includes receiving downlink data packets and an uplink data assignment indicator (UL DAI) from a base station, wherein a value of the UL DAI indicates a number (N) of all scheduled downlink sub-frames which scheduled by the base station for the user equipment, the number N is greater than 1, and a number k (k |
| US09634816B2 |
Method and apparatus for transmitting and receiving data
Disclosed are a method and an apparatus for transmitting and receiving data. A method for transmitting an uplink comprises the steps of: a terminal receiving first downlink data from a first cell through a first subframe; the terminal receiving second downlink data from a second cell through the first subframe; the terminal transmitting first uplink data, which is generated based on a first identifier of the first cell, as a reply to the first downlink data through a second subframe, and the terminal transmitting second uplink data, which is generated based on a second identifier of a second cell, as a reply to the second downlink data through the second subframe. |
| US09634809B2 |
Mobile communications terminal, and method for controlling radio frequency power amplifier thereof
The present invention discloses a mobile communications terminal. The mobile communications terminal includes a signal processing module and a radio frequency power amplifier, where the signal processing module outputs, to a radio frequency signal input end of the radio frequency power amplifier, a radio frequency signal corresponding to one group of data packets, and synchronously outputs an enable signal to an enable signal input end of the radio frequency power amplifier; and the signal processing module periodically stops outputting the enable signal to the enable signal input end within first predetermined duration, and outputs, to the radio frequency signal input end, a radio frequency signal corresponding to at least one piece of pilot data and synchronously outputs the enable signal to the enable signal input end within second predetermined duration. |
| US09634808B2 |
Radio communication system, radio communication method, user terminal and radio base station
To perform rate matching appropriately even when downlink signals are transmitted from a plurality of transmission points to a user terminal, a radio communication system having a user terminal capable of coordinate multi-point transmission and reception with several radio base stations is provided. A radio base station transmits downlink control information including bit information defining a predetermined rate matching pattern to the user terminal. The user terminal receives the downlink control information and performs rate matching based on the bit information defining the rate matching pattern. A combination of a cell-specific reference signal pattern and an interference measurement reference signal pattern in the case of transmission from several radio base stations each using an MBSFN subframe or NCT is defined in predetermined bits. The user terminal performs rate matching based on the bit information and the subframe configuration and interference measurement reference signal pattern of the radio base station. |
| US09634807B2 |
Joint user detection apparatus
A joint user detection apparatus for a wireless communication system, such as OFDM systems, arranged to account for timing impairments experienced by CAZAC codes.The proposed apparatus brings improvements over conventional receiving apparatuses by allowing joint user channel estimation processing and joint user equalization processing while considering timing impairments of user associated information present within a symbol of a received signal. The proposed solution could be used on conventional receiving apparatuses since both joint user channel estimation processing and joint user equalization processing can be activated independently such that either one or both improvements may be activated as needed or as required by the design of the conventional receiving apparatuses.A method and a computer program are also claimed. |
| US09634806B2 |
Data prioritization for a power-limited UE in a wireless communication system
Techniques for transmitting data by a power-limited user equipment (UE) in a wireless communication system are described. The UE may transmit data of different types on one or more carriers and may be power limited. In some aspects, the UE may prioritize the data to transmit based on the priorities of the different data types, the priorities of carriers on which the data is transmitted, and/or other criteria. In one design, the UE may obtain data to transmit on at least one carrier for the uplink. The UE may determine that it is power limited for transmission on the at least one carrier. The UE may prioritize the data to transmit based on at least one criterion. The UE may allocate its available transmit power to the prioritized data and may transmit the prioritized data at the allocated transmit power. |
| US09634804B2 |
Method and apparatus for stable signal demodulation in communication system
A method and apparatus provide for stable signal demodulation in a communication system. The method and apparatus includes including detecting an erroneous demodulation value based on backward-demodulation of received signals, using a difference between a received signal to be demodulated and a preceding signal of the received signals and correcting the error demodulation value. Alternatively, backward-demodulation is used to confirm received signals. |
| US09634801B2 |
User equipment identification specific scrambling
A base station for use in a code division multiple access communication system comprises circuitry configured to process a user equipment identification (UE ID) by 1/2 rate convolutionally encoding the UE ID to produce a sequence. The sequence is used by the base station for scrambling a high speed shared control channel (HS-SCCH). The base station is configured to transmit a wireless signal. The wireless signal provides the user equipment with payload data carried on a high speed physical downlink shared channel (HS-PDSCH). The HS-PDSCH is associated with the HS-SCCH. |
| US09634800B1 |
Sub-rate codes within the 10GBASE-T frame structure
A BASE-T Ethernet transceiver is disclosed. The transceiver includes a BASE-T Ethernet data framing module having an input interface to receive Ethernet block data bits at a first data rate, logic to associate the Ethernet block data bits with an auxiliary bit and a number of Reed-Solomon check bytes, and a forward error correction encoder. The encoder is coupled to the logic to encode all of the data bits, auxiliary bit and the Reed-Solomon check bytes into a first error encoded transport frame having plural error check bits. A symbol mapper receives the first error encoded transport frame and modulates the first error encoded transport frame into symbols, each of the symbols having uncoded bits. A BASE-T transmitter is coupled to the symbol mapper to transmit the first group of symbols over an Ethernet link at one of a selection of symbol rates. Errors in the uncoded bits are correctable via the Reed-Solomon check bytes. |
| US09634792B2 |
Method and apparatus of performing ONT wavelength tuning via a heat source
A method and apparatus of tuning a signal received from a first network terminal at a second network terminal is disclosed. The method may include receiving the signal at the second network terminal. The signal may be operating at a first wavelength. The method may also include determining a port used to receive the signal at the second network terminal, and identifying a predetermined port wavelength used as a basis to shift the first wavelength to the predetermined port wavelength for subsequent signals received. The method may also include transmitting the predetermined port wavelength information to the first network terminal to inform the first network terminal to tune subsequent signals to the desired wavelength for the port. |
| US09634791B2 |
Flexible optical spectrum management systems and methods
Flexible optical spectrum management systems and methods in an optical network including a plurality of interconnected network elements include determining an associated frequency/wavelength center and one or more bins for each of one or more traffic carrying channels on each of a plurality of optical fibers in the optical network; and managing the one or more traffic carrying channels on the plurality of optical fibers using the one or more bins of bins and the associated frequency/wavelength center, wherein at least one of the one or more traffic carrying channels comprises a coherent optical signal occupying a flexible spectrum on the plurality of optical fibers. |
| US09634783B2 |
Systems and methods for serial packet synchronization in a voice processing system
A serial packet sync encoder is used to encode a serial packet sync datastream. In an embodiment, the serial packet sync datastream is made up of the packet sync vector and a unique preamble bit sequence that is preselected. In another embodiment, the serial packet sync datastream is made up of a non-unique bit sequence. A serial packet sync transmitter is used to transmit the serial packet sync datastream. A serial packet sync receiver is provided for receiving the serial packet sync datastream. In an embodiment, the serial packet sync transmitter and the serial packet sync receiver are shift registers. In this way, the serial packet sync datastream can be transmitted and received using only a single pin. The serial packet sync datastream is useful for providing an indication that an event, such as a grant arrival, has occurred. A preamble comparator is provided to compare the received serial packet sync datastream and the preselected preamble to determine if the two match. In cases where a match is made, the packet sync vector is written into a holding register for access from other applications and or system components such as a digital signal processor. |
| US09634782B2 |
Clock synchronization system, clock synchronization method, and storage medium whereupon clock synchronization program is stored
A slave node (104) includes N time regeneration units (105 to 107) each of which communicates with each of N master nodes (101 to 103) to compute a propagation delay between each master node (101 to 103) and the slave node (104) and regenerates a time of each master node (101 to 103), a time comparison unit (108) that independently computes each comparison result between the time of each master node (101 to 103), which is regenerated by each of N time regeneration units (105 to 107), and a reference time held by the slave node (104), and a reference time determination unit (109) that computes each correction value by carrying out weighting for each comparison result computed by the time comparison unit (108) based on the propagation delay and determines a reference time of the slave node (104) by carrying out statistical processing by using the correction value. With this configuration, it is possible to improve precision and accuracy of synchronization of the time of the slave node at low cost. |
| US09634772B2 |
Harmonic suppression system
A harmonic suppression system, including an interface connector is connected to a common end of a first differential SPMT switch; a control port of the first differential SPMT switch is connected to a control port of a second differential SPMT switch, and a gating throw end of the first differential SPMT switch is separately connected to one end of each LC trap network in a one-to-one correspondence; the control port of the second differential SPMT switch is connected to a baseband chip, each gating throw end of the second differential SPMT switch is separately connected to the other end of each LC trap network in a one-to-one correspondence, and a common end of the second differential SPMT switch is connected to the baseband chip; the baseband chip is connected to an antenna switch; and the antenna switch is connected to a antenna. |
| US09634771B2 |
Optical connector interconnection system and method
A method for connecting adjacent computing board devices. A source computing board may be provided. An optical engine attaches to the source computing board. A plurality of source optical connectors couples to the optical engine. A first optical connector may be positioned at a location on the source computing board for a first preset type of computing component on an adjacent computing board. A second optical connector may be positioned at a fixed coordinate related to the first optical connector on the source computing board. |
| US09634767B2 |
Power control in bidirectional WDM optical link
A bidirectional WDM optical communications link has WDM signals sent in opposite directions along a shared optical path and using at least one common wavelength. An optical amplifier (20, 21, 22, 70, A1D, A2U, A2D) optically amplifies (144) a first WDM signal separately from a second WDM signal in the other direction. This separated optical amplification is controlled (134) according to indications of transmission quality at the common wavelength, to alter the relative optical powers of the first and second WDM signals to enable crosstalk at the common wavelength to be limited. Cross talk at the common wavelength can be improved by rebalancing relative amounts of cross talk in the different directions, to enable the capacity benefits of using a common wavelength for both directions to be obtained while using greater optical signal power. This is particularly useful where the optical power is asymmetric, such as in WDM PON systems. |
| US09634762B2 |
Optical transmission system, node apparatus, and reachability determination method
A node apparatus is installed at a node located on a route from a start node to an end node, and includes: a parameter calculating unit configured to, upon receiving routing information specifying the route and a first parameter representing an amount of signal degradation, update the first parameter by using a second parameter representing an amount of signal degradation along a transmission route to an adjacent node, and generate a third parameter representing an amount of signal degradation along a transmission route between the start node and the node, specified by the routing information; and a determination unit configured to determine reachability of the route specified by the routing information in accordance with the third parameter and a fourth parameter representing an amount of signal degradation along a transmission route from the node to the end node specified by the routing information. |
| US09634761B2 |
Apparatus and method for optical-network monitoring
A method, apparatus, and system for network monitoring, and more specifically for correlating downstream devices in an optical network with downstream ports of an optical splitter through which they are communicating with a central office. The downstream devices operational on the network are indentified and listed in a correlation table. Selected subsets of these devices are then monitored, preferably by an ISM under the direction of a management node, in a series of monitoring cycles until a satisfactory correlation may be achieved. The correlation cycle may be performed at startup, as needed, or on a periodic basis. |
| US09634759B2 |
System and apparatus for inspecting fiber optic cables
An apparatus for fiber optic network testing includes a housing configured and adapted to couple to a mobile device and one or more network interfaces in communication with the housing. The one or more network interfaces are configured and adapted to operatively couple to a terminal end of a fiber optic cable. The apparatus also includes a magnification lens in operative communication with the housing and the one or more network interfaces. |
| US09634752B2 |
Method and apparatus for transmitting and receiving feedback information in a mobile communication system
A method and user equipment for transmitting channel state information (CSI) are provided. The method includes identifying a first CSI configuration with a first index and a first information for a period and an offset; identifying a second CSI configuration with a second index and a second information for a period and an offset; and reporting a CSI for a CSI configuration with a lowest index among the first CSI configuration and the second CSI configuration, in case of collision between report of a CSI for the first CSI configuration and report of a CSI for the second CSI configuration. |
| US09634749B2 |
Method and apparatus for efficient feedback in a wireless communication system supporting multiple antenna
A method for transmitting channel status information (CSI) via uplink in a wireless communication system includes transmitting a first precoding matrix indicator (PMI) and a second PMI at a subframe. A subsampled codebook for each of a precoding codebook for Rank-1 and a precoding codebook for Rank-2 is determined based on at least the first PMI or the second PMI. In case of the Rank-1 or the Rank-2, a number of elements for the first PMI is 8. |
| US09634745B2 |
Enhancing MU-MIMO to group clients across multiple BSSIDS for a physical radio
MU-MIMO provides a mechanism for a wireless network device to transmit to multiple client devices at the same time. When employing MU-MIMO, a network device may group two or more associated client devices, and transmit beamformed signals to each group. In some implementations, a network device may initiate channel sounding. Channel sounding may include transmitting sounding frames to client devices associated with two or more basic service sets. Channel sounding may facilitate beamforming transmissions to client devices associated with the two or more basic service sets. The network device may receive feedback frames from client devices associated with the two or more basic service sets. A feedback frame may indicate how a sounding frame was received. In some implementations, the network device may further construct a feedback table from the feedback frames. The feedback table may facilitate grouping of the client devices for beamforming transmissions. |
| US09634743B2 |
Multiple spatial channel transmission with rate control
A MIMO ARC transmitter derives demux streams (15, 20) carrying different parts of the information, at given data rates, processes each demux stream by coding and modulation (25, 30) before transmission over the channels, and varies (50, 165) the coding or modulation according to channel conditions, and controls the data rates (50, 155) according to conditions of the channels independently of the variations in coding and modulation. The separate control of processing and of data rates for each demux stream can provide a better balance of rapid response to changing conditions and efficiency in less rapidly changing conditions. The frequency of updating the processing can be limited since these take more time to adapt in the receiver. Sensitivity to rapid changes can be achieved by the data rate changes since these involve less overhead than changes in the processing. |
| US09634742B2 |
Techniques to manage channel prediction
A system, apparatus, method and article to manage channel prediction for a wireless communication system are described. The apparatus may include a media access control processor to perform channel prediction, and a transceiver to communicate information using the channel prediction. Other embodiments are described and claimed. |
| US09634737B2 |
Periodic near field directors (PNFD) for short-range milli-meter-wave-wireless-interconnect (M2W2-interconnect)
Periodic near field directors (PNFDs) are coupled to a transmitter and a receiver for a short-range millimeter wave wireless (M2W2) interconnect for transmitting and receiving radio frequency (RF) signals at millimeter-wave frequencies for short-range communication with high data rate capability between the transmitter and receiver. Each of the periodic near field directors is comprised of one or more periodic coupling structures (PCSs), wherein the periodic coupling structures are comprised of metallic strips positioned such that their lengthwise dimension is substantially perpendicular to a propagation direction of the radio frequency signals between the transmitter and receiver. Each of the periodic coupling structures is positioned parallel to adjacent periodic coupling structures with a separation distance between each periodic coupling structure being within one wavelength of the radio frequency signal. The periodic near field directors may include first and second periodic near field directors that are coupled to each other for transmitting and receiving the radio frequency signals between the first and second periodic near field directors, wherein there is an air gap between the first and second periodic near field directors. |
| US09634736B2 |
Periodic bandwidth widening for inductive coupled communications
In described examples, a method of inductive coupled communications includes providing a first resonant tank (first tank) and a second resonant tank (second tank) tuned to essentially the same resonant frequency, each having antenna coils and switches positioned for changing a Q and a bandwidth of their tank. The antenna coils are separated by a distance that provides near-field communications. The first tank is driven to for generating induced oscillations to transmit a predetermined number of carrier frequency cycles providing data. After the predetermined number of cycles, a switch is activated for widening the bandwidth of the first tank. Responsive to the oscillations in the first tank, the second tank begins induced oscillations. Upon detecting a bit associated with the induced oscillations, a switch is activated for widening the bandwidth of the second tank and a receiver circuit receiving an output of the second tank is reset. |
| US09634733B2 |
Contactless power feeding system, vehicle, power feeding facility and method of controlling contactless power feeding system
When an impedance adjustment process of a resonant system is started, a power feeding facility outputs power for adjustment. Then, an ECU of the power feeding facility adjusts an impedance matching box provided in the power feeding facility, and when the adjustment is completed, transmits an instruction for adjustment in a vehicle to the vehicle. When the vehicle receives the adjustment instruction from the power feeding facility, the vehicle adjusts an impedance matching box provided in the vehicle. That is, in this contactless power feeding system, the impedance adjustment in the power feeding facility is performed first, and the adjustment in the vehicle is performed thereafter. |
| US09634732B2 |
Apparatus and method for inductive power transfer on an electrified roadway using a rotating secondary inductor
The invention described herein provides an energy transfer system via a tire based inductor system. By using the tire, the area inside the tire, the tire rim, or the wheel as the inductive pick-up for a powered roadway system the prior art problems are solved. Namely, since the tire/wheel is always in contact, or near contact with the road, the air gap is reduced to a minimum, and substantially fixed, distance. By mounting the secondary on the perimeter of a wheel, relative motion between the road and inductor is minimized. In addition, the pick-up can be encased in the tire, eliminating the problem of road debris, snow and ice entirely. Also, some heating of the tire due to electrical losses may enhance traction and tread performance on snowy or wet roads. In all configurations, the vehicle's wheel suspension adjusts vertically adjusting for road imperfections and obstacles. |
| US09634724B2 |
Energy delivery on paths used for communication
Systems and methods for delivering energy on a bus used for communication between devices are provided. Systems and methods dynamically provide a predetermined recovery time between communication messages calculated from forward and response message types and/or length, and a model of the energy reserve in the network devices to allow time for energy storage circuits in the devices to charge. In addition or alternatively, systems and methods provide an extra recovery time between messages to allow the bus voltage to recover from a fold-back mode and/or include an extra current limit circuit to increase a power supply current when the combined energy required by the network devices is greater than a current limit on a power supply. |
| US09634722B2 |
Cable network spectral measurement during upstream packet transmission
Apparatus and method are provided for obtaining an upstream signal spectrum as it was during a time of transmission of a received upstream data packet. The apparatus includes an analog-to-digital converter (ADC), a packet detector coupled to ADC, and a spectrum calculation unit coupled to the ADC and the packet detector. In operation, the spectrum calculation unit computes a spectrum of the digitized upstream signal as it was between the start and end times of the first packet. As a result, the obtained spectrum is representative of a condition of the transmission path during transmission of the upstream data packet. |
| US09634720B2 |
Apparatuses and a method for crosstalk estimations
It is described an apparatus for determining a PLC-to-DSL crosstalk estimate. The apparatus comprises a PLC-to-DSL channel estimator which is arranged to receive an input signal, comprising a DSL contribution and a PLC-to-DSL crosstalk contribution, and which is arranged to determine channel state information of a PLC-to-DSL channel responsible for the PLC-to-DSL crosstalk contribution in the input signal. The apparatus further comprises a crosstalk processor which is arranged to determine the PLC-to-DSL crosstalk estimate based on the channel state information and a reconstructed PLC transmit signal. |
| US09634717B2 |
Single local oscillator architecture for dual-band microwave/millimeter-wave transceiver
Systems for a dual-band transceiver that re-uses a lower frequency transmitter to drive a local oscillator (LO) for high frequency circuits are disclosed herein. The need for a LO lineup requiring high frequency and high power is eliminated. The output of a lower frequency band is modified to be used as a LO drive for the higher frequency band transceiver. Using a carrier recovery loop, the system is operable to simultaneously operate in both bands. The result is a solution that eliminate the design of a high performance LO circuits for a higher band of a mmW dual-band system. This significantly reduces the overall complexity of the system. Furthermore, the inventive architecture reduces the design complexity and overall cost to implement dual-band circuit. |
| US09634716B2 |
Enhanced granularity operational parameters adjustment of components and modules in a multi-band, multi-standard communication device
Enhanced granularity operational parameters adjustment of components and modules in a multi-band, multi-standard communication device. For supporting two-way communications, a communication device includes receiver and transmitter modules. Each module includes various components that are configurable and/or programmable based on a protocol and band pair by which the communication device is operating. The communication device is a multi-protocol and multi-band capable communication device capable to operate in accordance with any one protocol and band at a first time and another protocol and band at a second time. The various components within each of the receiver and transmitter modules can be adjusted using one or more operational parameters. In some instances, a given component can be controlled by more than one operational parameter. Alternatively, certain components are controlled only one operational parameter. The operational parameters that configure the components may be calculated, retrieved from a memory, and/or determined using other means. |
| US09634715B2 |
Signaling between master and slave components using a shared communication node of the master component
A network slave device includes a transceiver for communicating over a communication bus in accordance with a point-to-point network protocol. The network slave device may have an address to identify the network slave device on the network. It may also have a communication circuit configured to process a series of commands received by the transceiver and respond to a command if a position of the command in the series of commands corresponds to the address of the network slave device. A master device communicating on the network may send the series of command in accordance with the point-to-point network protocol. In an embodiment, the point-to-point protocol is the SENT protocol. |
| US09634713B1 |
Transceiver with multiple correlators
A digital broadcast communication system includes a transceiver configured to receive a preamble having one of at least four preamble patterns characterized by a bit pattern and a length, produce the received preamble to each of at least four preamble correlator circuits, and at each correlator circuit, compare the received preamble to a reference code pattern. If a specified level of correlation exists between the received preamble and the reference code, produce an indication that the comparison was favorable. In one embodiment, the transceiver includes 16 correlator circuits and further includes 128 preamble reference codes for detecting preambles that have control, synchronization or data content. |
| US09634709B2 |
Removable electronic device case with supplemental antenna element
A removable case may receive an electronic device. A male connector in the case may mate with a female connector in the device. A battery in the case may supply power to the device through the male connector. The electronic device may have an antenna formed from peripheral conductive housing structures and an antenna ground. The case may have a supplemental antenna that restores antenna performance when the device is received within the case. The supplemental antenna may be formed from a monopole antenna resonating element coupled to the antenna ground through the power pin. The monopole element may have a portion that runs parallel to the peripheral conductive housing structures. During operation of the antenna in the electronic device, the supplemental antenna in the case may be indirectly fed by near-field coupling between the supplemental antenna and the antenna of the electronic device. |
| US09634701B2 |
Phase noise suppression
A system comprises a modulator circuit, a test signal generator circuit, and a control circuit. The modulator circuit is operable to generate a data-carrying signal based on a reference signal. The test signal generator circuit is operable to generate a test signal based on the reference signal. The control circuit is operable to determine current status of a microwave backhaul link. The control circuit is operable to configure a nominal frequency at which the test signal generator circuit generates the test signal based on the determined status of the microwave backhaul link. The control circuit is operable to determine an amount of whitespace to have on either side of the test signal based on the current status of the microwave backhaul link. The control circuit is operable to configure the modulator circuit such that the data-carrying signal has the determined amount of whitespace surrounding the nominal frequency of the test signal. |
| US09634698B2 |
Adaptive ISO-gain pre-distortion for an RF power amplifier operating in envelope tracking
The output of a Radio Frequency (RF) Power Amplifier (PA) is sampled and down-converted, and the amplitude envelope of the baseband feedback signal is extracted. This is compared to the envelope of a transmission signal, and the envelope tracking modulation of the RF PA supply voltage is adaptively pre-distorted to achieve a constant ISO-Gain (and phase) in the RF PA. In particular, a nonlinear function is interpolated from a finite number gain values calculated from the feedback and transmission signals. This nonlinear function is then used to pre-distort the transmission signal envelope, resulting in a constant gain at the RF PA over a wide range of supply voltage values. Since the gains are calculated from a feedback signal, the pre-distortion may be recalculated at event triggers, such as an RF frequency change. |
| US09634694B2 |
Transmitter with a reduced complexity digital up-converter
The present disclosure is directed to a system and method for performing digital up-conversion of a signal to a desired RF carrier frequency. The system and method efficiently perform digital up-conversion of the signal, in one example, by controlling a sample clock that is used by a DAC to sample and convert the up-converted signal from the digital domain to the analog domain to have a frequency that is four or eight times the desired RF carrier frequency. By controlling the sample clock of the DAC to have a frequency that is four or eight times the desired RF carrier frequency, the system and method can be implemented using currently available IC process geometries such that the implementation consumes much less area and/or power than an analog up-converter configured to have equivalent up-conversion functionality. |
| US09634693B2 |
Apparatus and method for decoding LDPC codes in a communications system
An apparatus and method decode LDPC code. The apparatus includes a memory and a number of LDPC processing elements. The memory is configured to receive a LDPC codeword having a length equal to a lifting factor times a base LDPC code length, wherein the lifting factor is greater than one. The number of LDPC processing elements configured to decode the LDPC codeword, wherein each of the number of LDPC processing elements decode separate portions of the LDPC codeword. |
| US09634690B2 |
Method and apparatus for arbitrary resolution video coding using compressive sampling measurements
The present invention relates to method and apparatus for arbitrary resolution video coding using compressive measurements. The method includes receiving at least one measurement of a set of measurements that was generated at an encoder. The set of measurements represents encoded video data. The method further includes determining a display resolution, where the display resolution is the same or different than an original display resolution. The method further includes determining an expansion matrix based on at least a number of pixels for the determined display resolution, and reconstructing the video data using the determined expansion matrix such that the original display resolution is resized to the determined display resolution if the determined display resolution is different than the original display resolution. The expansion matrix includes a pattern of values. |
| US09634689B2 |
Method and system for arranging numeric data for compression
A computer-implemented method for arranging numeric data for compression is described. The method is implemented using a computing device in communication with a memory and a measurement device. The method includes receiving, by the computing device and from the measurement device, numeric data that includes a sequence of numbers, each number including at least a first byte followed by a second byte. The method additionally includes arranging the first bytes into a first contiguous set, arranging the second bytes into a second contiguous set, and storing the first contiguous set and the second contiguous set in a file in the memory, such that the first contiguous set is contiguous with the second contiguous set. |
| US09634685B2 |
Telescopic amplifier with improved common mode settling
Telescopic amplifier circuits are disclosed. In an embodiment, a telescopic amplifier includes an input stage for receiving differential input signals, an output stage for outputting differential output signals at the drains of a first output transistor and a second output transistor, a tail current transistor coupled to sources of a first input transistor and a second input transistor, a common mode feedback circuit coupled to the differential output signals and outputting a common mode output signal, and a circuit element coupled between the common mode output signal and a gate of the tail current transistor. In an embodiment the circuit element is a resistor. In another embodiment the circuit element is a source follower transistor. In additional embodiments a phase margin of the common mode feedback open loop gain of the amplifier is determined by the value of the resistor. Additional embodiments are disclosed. |
| US09634681B1 |
Analog-to-digital conversion with linearity calibration
The embodiments described herein provide analog-to-digital converters (ADCs) and systems and methods for calibrating ADCs, including ADCs with poorly characterized nonlinearities that cannot be effectively calibrated with traditional calibration techniques. In general, the embodiments described herein calibrate by measuring output values from an ADC with a known calibration input values being applied. The measured output values are used to determine localized polynomial interpolants. Each of the determined localized polynomial interpolants is then evaluated at an uncorrected output value, and the evaluated localized polynomial interpolants are then used to generate correction values. These correction values can then be used to calibrate the ADC during later operation. Such a calibration technique can provide effective calibration for a variety of ADCs, including ADCs that use inverter-based voltage-to-current (VI) converters and current-controlled ring oscillators. |
| US09634680B1 |
Large-error detection and correction of digital sample sequence from analog-to-digital converter
A system and method for detecting and correcting large errors during ADC operation. The system includes an ADC; an AAF at the input of the ADC, having bandwidth less than information bandwidth of the ADC; and a large-error detection and correction processing unit at the output of the ADC. The large-error detection and correction circuit includes an interpolation filter to determine values of predicted digital samples corresponding to actual digital samples in a sequence of digital samples from the ADC based on information from neighboring digital samples. A signal-delay circuit in parallel with the interpolation filter delays the actual digital samples by an amount of a lag from the interpolation filter. An adder determines differences between the predicted and actual digital samples, a matched filter detects a pattern of the differences, and a large-error detection processing unit determines whether a large error occurs based on the pattern of the differences. |
| US09634679B1 |
Digital down converter with equalization
A digital down converter with equalization includes a composite ADC that performs demodulation of a received analog signal, converting the signal into in phase baseband signal and quadrature baseband signal. Equalization is performed to correct for misalignment of the frequency responses of the sub-ADCs in the composite ADC. In a form, ADC output signals are applied to a mixer array to frequency down-shift the digital form of the input signal, followed by digital filtering to effect convolutions of portions of the digital form of the input signal with a set of convolution coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. In another form, the ADC output signals are directly applied to a digital filter to effect both frequency down-shifting and convolutions, with filter coefficients determined so that the net processing is mathematically equivalent to down conversion with equalization. |
| US09634678B1 |
Feedback control system with rising and falling edge detection and correction
A technique for reducing noise in an output clock signal of a feedback control system (e.g., a PLL or FLL) samples rising edge errors and falling edge errors between a reference clock signal and a feedback clock signal. The technique applies edge alignment correction to reduce or eliminate edge alignment errors between the reference clock signal and the feedback clock signal. A PLL generates an output clock signal based on a control signal generated using an error signal generated based on a rising edge difference between a rising edge of an input clock signal and a corresponding edge of an edge alignment corrected feedback clock signal and based on a falling edge difference between a falling edge of the input clock signal and a corresponding edge of the edge alignment corrected feedback clock signal. The edge alignment corrected feedback clock signal is partially based on the output clock signal. |
| US09634676B2 |
Circuits and methods providing clock frequency adjustment in response to supply voltage changes
Methods, systems, and circuits for providing compensation for voltage variation are disclosed. A system includes: a voltage comparator configured to assert a control signal in response to detecting that one or more of power supply voltages droops below a threshold amount; a phase locked loop (PLL) configured to divide an output frequency for the PLL in response to the assertion of the control signal; a plurality of voltage sensors corresponding to the plurality of power supply voltages, the voltage sensors configured to output respective digital signals indicative of a voltage level of its corresponding power supply voltage; and a control circuit configured to control an oscillator frequency in the PLL during the open-loop mode responsive to the respective digital signals. |
| US09634675B2 |
Phase locked loop with jump-free holdover mode
A phase locked loop with holdover mode has a loop filter for creating an offset frequency value for a controlled oscillator. The loop filter includes a register for storing the current offset frequency value the said controlled oscillator. A first multiplexer responsive to a holdover signal selects, depending on the quality of a reference signal, the output of the loop filter or a holdover queue to control the controlled oscillator. A second multiplexer responsive to the holdover signal selects for input to the register, depending on the quality of the reference signal, the sum of an output of the register and a value derived from the current phase difference between the output of the controlled oscillator and the reference signal or a current output value of the holdover queue. |
| US09634672B2 |
Semiconductor circuit device, oscillator, electronic apparatus, and moving object
A semiconductor circuit device includes an oscillation circuit, an output circuit that receives a signal output from an oscillation circuit and outputs an oscillation signal, a temperature sensing element, a characteristic adjustment circuit that adjusts characteristics of the oscillation circuit on the basis of a signal output from the temperature sensing element, and a first connection terminal that is electrically connected to the output circuit and via which the oscillation signal is output, in which a distance between the output circuit and the first connection terminal is shorter than a distance between the temperature sensing element and the first connection terminal in a plan view. |
| US09634669B2 |
Reconfigurable system-on-chip and related methods
A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory. |
| US09634663B2 |
Semiconductor circuit, semiconductor device and potential supply circuit
A semiconductor circuit including a level shifter circuit that, in accordance with supply of a power supply voltage, converts a potential of an input signal from a first potential to a second potential that is higher than the first potential and outputs the second potential through an output node; a potential supply circuit, to which a reset signal at a level in accordance with the power supply voltage is supplied, that supplies a predetermined potential in accordance with the level of the reset signal; and a control circuit that controls the potential of the output node of the level shifter circuit in accordance with the level of the predetermined potential supplied from the potential supply circuit. |
| US09634661B1 |
Optical switch keyboard
An optical switch keyboard includes a circuit module and plural keys. The circuit module includes a circuit board, plural light emitters, plural light receivers and plural light sources. Each key corresponds to a light emitter, a light receiver and a light source. The plural light emitters and the plural light receivers are disposed under the circuit board. Consequently, the plural light emitters and the plural light receivers are not interfered by the ambient light that comes from the top side of the circuit board. In case that the light sources are disposed over the circuit board, the light beams from the light sources are transmitted upwardly through light-transmissible triggering elements of the corresponding keys and projected to the keycaps. Consequently, a visual effect is generated. |
| US09634659B2 |
Voltage controller for radio-frequency switch
One or more systems and techniques for limiting a voltage potential between an antenna and a radio-frequency switch circuit are provided. A voltage controller comprises a voltage generator, a voltage detection circuit and a switch cell. The voltage detection circuit is coupled to the voltage generator and to the switch cell, and the switch cell is coupled to a voltage source, and to a node between the radio-frequency switch circuit and the antenna. When the voltage potential exceeds a specified threshold, the voltage generator produces a voltage which the voltage detection circuit measures such that the voltage detection circuit activates the switch cell, resulting in a short circuit between the radio-frequency switch circuit and the voltage source. This serves to inhibit the voltage potential from exceeding the specified threshold, for example. |
| US09634657B1 |
System and method for overcurrent protection for a field controlled switch
A method includes detecting current from a first terminal of the switch to a second terminal of the switch, wherein the current exceeds a current limit for a linear region of the switch. The method includes controlling a gate voltage of the switch from a first voltage to a second voltage. The second voltage is configured to enable the switch to operate in an active region of the switch. The method further includes opening the switch when the switch is operating in the active region. |
| US09634655B2 |
Drive device having first and second switching devices with different gate widths
A drive device that drives a semiconductor switching device includes a capacitor and an output selection unit that selects whether or not to supply charge of the capacitor to a conduction control terminal of the semiconductor switching device, in which the output selection unit includes a first switching device and a second switching device, the charge of the capacitor is supplied to the conduction control terminal of the semiconductor switching device by the first switching device going to a conducting state, the charge is extracted from the conduction control terminal of the semiconductor switching device by the second switching device going to the conducting state, and a gate width of the second switching device is smaller than the gate width of the first switching device. |
| US09634650B2 |
State change stabilization in a phase shifter/attenuator circuit
An electronic system that includes a digitally selectable phase shifter circuit and an insertion loss fine adjustment circuit such that the system as a whole exhibits little or no change in insertion loss when changing phase state, and/or a digitally selectable attenuator circuit and a phase fine adjustment circuit such that the system as a whole exhibits little or no effect on phase when changing attenuation state. Included are methods for selecting adjustment control words for such circuits. |
| US09634644B2 |
Acoustic wave elements and antenna duplexers, and modules and electronic devices using same
An acoustic wave element according to certain examples includes a piezoelectric body, an interdigital transducer (IDT) electrode disposed above the piezoelectric body, and a connection electrode disposed above the piezoelectric body and connected to the IDT electrode. A first insulation layer covers the connection electrode, and a second insulation layer covers the IDT electrode. The first insulation layer disposed above the connection electrode has a first thickness T in a direction perpendicular to an upper surface of the piezoelectric body and the second insulation layer disposed above the IDT electrode has a second thickness K in the direction perpendicular to the upper surface of the piezoelectric body. The first thickness T is less than the second thickness K. |
| US09634642B2 |
Acoustic resonator comprising vertically extended acoustic cavity
A bulk acoustic wave (BAW) resonator having a vertically extended acoustic cavity is provided. The BAW resonator includes a bottom electrode disposed on a substrate over a cavity formed in the substrate; a piezoelectric layer disposed on the bottom electrode, and a top electrode disposed on the piezoelectric layer. The piezoelectric layer has a thickness of approximately λ/2, wherein λ is a wavelength corresponding to a thickness extensional resonance frequency of the BAW resonator. At least one of the bottom electrode and the top electrode comprises a composite electrode having a thickness of approximately λ/2. |
| US09634639B2 |
Tunable electronic circuit which converts balanced signals to unbalanced signals
Balun with tunable bandpass filter characteristic includes first, second and third coupling elements disposed on a substrate. The first and second coupling elements are arranged on the substrate relative to the third coupling element to couple two identical but out of phase signals to form a corresponding unbalanced signal in the third coupling element. A plurality of tunable resonator elements are distributed within an area of the substrate defined on one side by the first and second coupling elements and on an opposing side by the third coupling element. The tunable resonator elements are configured to selectively produce a bandpass filter response. |
| US09634635B2 |
RF attenuator device and system
A device includes a thermally conductive and electrically insulative substrate having a first major surface and a second major surface. A coupling structure is configured to reduce the RF input signal by substantially a predetermined amount of attenuation power. A tuning circuit is characterized by a tuning reactance substantially matched to a predetermined system impedance. A resistor is disposed on a majority of the first major surface and is characterized by a parasitic capacitance that is substantially negated by the tuning reactance. The resistor includes a first resistive portion and a second resistive portion; each of the first resistive portion and the second resistive portion being configured to direct approximately one-half of the attenuation power to the ground portion. |
| US09634633B2 |
Electronic component
An electronic component includes a device body and first through n-th LC parallel resonators connected in series with each other. The first through n-th LC parallel resonators respectively include first through n-th inductors and first through n-th capacitors. The first through n-th inductors are disposed in the device body such that they are arranged in a first direction in this order. The first and n-th inductors are provided with a spiral shape such that they turn around respective winding axes extending along the first direction. At least one of the second through (n−1)-th inductors is provided with a helical shape such that it turns around a winding axis extending along the first direction. |
| US09634625B2 |
Radio frequency transmitter with extended power range and related radio frequency transmission method
A radio frequency transmitter includes a digital power amplifier and a bias control circuit. The digital power amplifier is arranged for receiving at least a radio frequency input signal, a digital amplitude control word signal and at least one bias voltage to generate a radio frequency output signal. The bias control circuit is coupled to the digital power amplifier, and is arranged for adjusting the at least one bias voltage according to a power control signal. |
| US09634624B2 |
Method of operating digital-to-analog processing chains, corresponding device, apparatus and computer program product
A signal processing chain, such as an audio chain, produces an analog output signal from a digital input signal. The signal processing chain is operated by generating a first flag signal for the analog output signal and one or more second flag signals for the digital input signal. Each flag signal assumes a first level or a second level and is set to the first level when a signal from which the flag is generated has a value within an amplitude window. An amount the first flag signal for the analog output signal and the second flag signal for the digital input signal match each other may be calculated for issuing an alert flag which indicates an impaired operation of the signal processing chain. |
| US09634623B2 |
Class-D power amplifier
The invention is provided with a first class-D amplifying unit for amplifying an inputted audio signal and supplying the amplified signal to a positive side of an audio output terminal, a second class-D amplifying unit for amplifying an inputted audio signal inverted in an inverting unit and supplying the amplified signal to a negative side of the audio output terminal, wherein, in a first mode, the first and second class-D amplifying units are activated and outputs of the first and second class-D amplifying units are kept equal to or less than a first current value, and wherein, in a second mode, the first class-D amplifying unit is activated, the second class-D amplifying unit is inactivated, the negative side of the audio output terminal is grounded, and output of the first class-D amplifying unit is kept equal to or less than a second current value larger than the first current value. |
| US09634621B1 |
Charge-pump power supply with voltage-headroom-dependent supply voltage
A method may include providing a power supply voltage to a power supply input of a power amplifier by a charge pump power supply having a select input for selecting an operating mode of the charge pump power supply, such that in a first operating mode, the power supply voltage is equal to a first voltage, and such that in a second operating mode the power supply voltage is equal to a fraction of the first voltage; wherein the power amplifier has an audio input for receiving an audio input signal, and an audio output for providing the output signal, and generates the output signal based on the audio input signal. The method may also include selecting an operating mode of the charge pump power supply based on a magnitude of the power supply voltage and a magnitude of the output signal, such that the charge pump power supply operated in the operating mode having the lowest power supply voltage in which a difference between a magnitude of the power supply voltage and a magnitude of the output signal is more than the predetermined threshold voltage. |
| US09634613B1 |
Bias circuit having reduced power consumption
A depletion mode FET having a source electrode connected to ground; and a bias circuit for producing a bias current for a gate electrode of the FET. The bias circuit includes a pair of source follower transistors circuits; a first one of the pair of two source follower transistor circuits being coupled between a first voltage supply having a first polarity relative to the ground potential and a second voltage supply having a second polarity relative to ground potential, the first polarity being opposite to the second polarity, the first one of the pair of the source follower transistor circuits supplying a control signal to a second one of the pair of source follower transistor circuits. The second one of the pair of source follower transistors circuits is coupled between the second voltage supply and the ground potential and wherein the second one of the pair of source follower transistor circuits produces a bias signal for the control electrode of the output transistor. |
| US09634608B2 |
Crystal oscillation circuit and electronic timepiece
To provide a crystal oscillation circuit low in current consumption and stably short in oscillation start time. A crystal oscillation circuit is equipped with a crystal vibrator, a feedback resistor, a bias circuit, a constant voltage circuit, and an oscillation inverter configured by a constant current inverter. The oscillation inverter is configured so as to be controlled by currents based on input signals from the bias circuit and the crystal vibrator and driven by an output voltage of the constant voltage circuit. |
| US09634606B2 |
Offset building integrable photovoltaic structures and assemblies having multi-conductor return lines
Provided are novel building integrable photovoltaic (BIPV) structures having multiple photovoltaic portions offset with respect to each other along their lengths. An offset direction can correspond to the length of a row of installed BIPV structures. In some embodiments, a BIPV structure may include three offset photovoltaic portions and three corresponding flap portions for extending under photovoltaic portions of adjacent structures and sealing interfaces between installed structures. The novel BIPV structures can facilitate installation, while providing the flexibility to avoid obstacles. Provided also are novel BIPV assemblies having multi-conductor return lines extending through the assemblies. A BIPV assembly having a multi-conductor return line may include a return line for the assembly itself, and one or more return lines for other assemblies. |
| US09634604B2 |
Device for controlling a multi-phase motor
An electronic device is for controlling motor drive circuits for driving a multi-phase motor in a force assisted system. Each motor drive circuit selectively permitting current to flow into or out of a respective phase of the multi-phase motor connected to the motor drive circuit in response to being driven by respective control signals. A motor control circuit generates the control signals. A fault processor detects at least one fault condition causing a fault current in a first motor drive circuit. In the event of the fault condition being detected, at least one alternative control signal is generated for at least one motor drive circuit for permitting at least one compensation current to flow for reducing a faulty force due to the fault current. |
| US09634601B2 |
Energy storage device, system comprising an energy storage device, and method for actuating an energy storage device
The invention relates to an energy storage device for generating an n-phase supply voltage, wherein n>1, comprising n energy supply branches connected in parallel, which are each coupled to a respective output connection of the energy storage device, wherein each of the energy supply branches has a plurality of energy storage modules connected in series. The energy supply branches each have a respective energy storage cell module, which has at least one energy storage cell, and a respective coupling device having first coupling elements, which are designed to selectively connect the energy storage cell module into the respective energy supply branch or bypass the energy storage cell module. At least one of the energy supply branches has at least one second coupling element, which is coupled between output connections of energy storage cell modules that are adjacent in the at least one energy supply branch and which is designed to connect the coupled energy storage cell modules into the respective energy supply branch in parallel with each other. |
| US09634593B2 |
System and method for permanent magnet motor control
A method of operating an electric motor is disclosed. The method includes: starting the electric motor in an open loop control mode; operating an estimator that estimates operating conditions of the electric motor; and, while the electric motor is in the open loop control mode, evaluating a first parameter of the estimator. The method further includes: in response to the evaluation of the first parameter, determining whether the estimator has converged; and in response to a determination that the estimator has not converged within a predetermined period of time after starting the electric motor, signaling a first fault condition. |
| US09634592B2 |
Method of estimating rotational position of motor, and control apparatus of motor
A method of estimating a rotational position of a motor having saliency includes the steps of a) superimposing, on a drive voltage to rotate a rotating portion of the motor, a measuring voltage having a predetermined frequency higher than a frequency of the drive voltage to generate a plurality of voltages, and supplying the plurality of voltages to a stationary portion of the motor; b) in parallel with step a), extracting a component of the predetermined frequency in a current flowing in the stationary portion as an extracted current; c) calculating a sum of squares of the extracted current and a phase-shifted current obtained by shifting a phase of the extracted current by π/2 to acquire a composite signal related to an amplitude of the extracted current; and d) acquiring a rotational position of the rotating portion based on the composite signal. |
| US09634590B2 |
Drive device
A drive device that includes an alternating-current rotary electric machine in which currents of a plurality of phases flow; an inverter that includes switching element units for respective phases corresponding to the respective phases, and that is connected between a direct-current power supply and the alternating-current rotary electric machine and performs conversion between a direct current and an alternating current; and shunt resistors that detect currents flowing in the respective switching element units for the corresponding phases between the direct-current power supply and the switching element units for the respective phases. |
| US09634589B2 |
Drive device
Both downsizing of an apparatus as a whole and reduction in a product cost are attained. The preferred embodiments relate to a drive device including an alternating-current rotary electric machine, an inverter, and a case. The inverter is fixed to the case. The case and the inverter are disposed in a driving force source room. The inverter includes shunt resistors to detect currents flowing in respective switching element units for corresponding phases. |
| US09634587B2 |
Motor control apparatus, electric power steering apparatus and vehicle using the same
A motor control apparatus includes a motor current shutoff unit inserted between a multi-phase inverter circuit and a multi-phase electric motor to shut off a current for each of plural phases, the inverter circuit including an arm for each of the plural phases, a redundant arm unit including one or more arms, a connection selecting unit selecting which one of windings of the electric motor is to be connected to each of the one or more arms of the redundant arm unit, an abnormal arm detection unit detecting an abnormality in each of the plural phases of the inverter circuit, and an abnormality control unit shutting off connection between an abnormal arm and the motor when the abnormal arm detection unit detects the abnormal arm, and connecting the one or more arms of the redundant arm unit to a winding of the motor shut off. |
| US09634585B2 |
Control method for reducing torque ripple in an electrical machine
A method of controlling torque ripple in an electrical machine that includes a field winding for creating nominally constant field current using DC current and an armature winding for creating a rotating magnetic field using AC current, calls for superimposing a spatially varying current component on to the DC current of the field winding. Other methods are also disclosed that are suitable for electrical machines that have a winding that is excited with nominal DC current including SRMs, FSMs, and wound-field synchronous motors. |
| US09634583B2 |
Motor driven appliance and protection method thereof
A motor driven appliance in one aspect of embodiments of the present disclosure comprises a motor, a first switching element, a second switching element, an operation unit, a control unit, and a monitoring unit. The first and second switching elements are provided on a current path from a power source to the motor, and are connected in series to each other. The monitoring unit monitors an operating state of a protection function by the control unit, and, when the protection function is activated, outputs an OFF signal for turning off the second switching element. |
| US09634580B2 |
Power converter controller
A difference command generator generates a difference command equivalent to a time integral of three-phase voltage applied to an inductive load in a predetermined cycle in a complex plane. A vector command generator generates vector commands that are respectively time integrals of voltage vectors and compose the difference command. A switching signal generator generates switching signals for controlling three pairs of switches in an inverter on the basis of the vector commands. A phase-current computing unit obtains an estimated value for the three-phase current on the basis of a current flowing DC buses and the vector commands. At least two of the vector commands that are time integrals of different ones of the non-zero voltage vectors have magnitudes greater than or equal to a predetermined value corresponding to a minimum required amount of time to maintain switching patterns in order for the phase-current computing unit to detect the current. |
| US09634575B2 |
Control method and control device for inverter system
The present application discloses a control method and a control device for parallel inverters. The method comprises: receiving a feedback signal Vmg reflecting load voltage and a voltage reference signal Vref to generate a command signal Pset reflecting active power and a command signal Qset reflecting reactive power; taking the command signal Pset reflecting active power as the first offset of an active power-output voltage frequency curve (P-F) of an inverter unit, and taking the command signal Qset reflecting reactive power as the second offset of an reactive power-output voltage amplitude curve (Q-V) of the inverter unit; transversely translating the curve (P-F) of the inverter unit according to the first offset, transversely translating the curve (Q-V) of the inverter unit according to the second offset, and adjusting the load voltage of the inverter system by means of adjusted output voltage frequency and output voltage amplitude of the inverter unit. |
| US09634572B2 |
Switching mode power supply and the controller and the method thereof
A switching mode power supply with resonant technology. The switching mode power supply current uses current polarity evaluation to avoid capacitive mode by triggering the capacitive protection if the evaluation indicates that the system will enter capacitive mode. |
| US09634569B1 |
DC-to-DC output current sensing
Method and circuits enable measuring output current in DC/DC converters operating in pulse frequency modulation (PFM) mode and in pulse width modulation (PWM) mode. The method is applicable to DC/DC converters using an inductor at the output. Current is sampled on one pass transistor only. The DC/DC converter disclosed turns a PMOS transistor off when the output current reaches its current limit. |
| US09634564B2 |
Control circuit and control method of digital control power supply circuit, and digital control power supply circuit, electronic device and base station using the same
A control circuit of a digital control power supply circuit includes: an A/D converter that samples a feedback voltage according to an output voltage of the power supply circuit when a strobe signal is asserted, and converts the sampled feedback voltage into digital feedback data; an error detector that generates error data which indicates a difference between the feedback data and target data; a compensator that generates a duty command value which is adjusted to approximate the error data to zero; a digital pulse width modulator that receives the duty command value and generates a pulse signal having a duty ratio corresponding to the duty command value; and a strobe signal generator that generates the strobe signal and adjusts a sampling timing at which the strobe signal is asserted such that the sampling timing approximates a target position set in a substantial center of a slope of the output voltage. |
| US09634562B1 |
Voltage doubling circuit and charge pump applications for the voltage doubling circuit
A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated. |
| US09634561B1 |
Programmable charge pump
A charge pump includes a charge pump core circuit, a replica bias circuit, and a differential amplifier. The charge pump core circuit includes current source and sink circuits for charging and discharging an output node of the charge pump core circuit. The current source and current sink circuits are user programmable using bit signals to adjust a bandwidth and a phase margin of a phase-locked loop (PLL) that includes the charge pump. An impedance of the replica bias circuit varies based on the bit signals. The differential amplifier and the replica bias circuit form a feedback loop that reduces current mismatch between the current source and sink circuits. |
| US09634559B2 |
Charge pumping apparatus for low voltage and high efficiency operation
A charge pump (CP) that operates at low input voltage with high power conversion efficiency is disclosed. A first embodiment provides a negative CP used for controlling load switches of a voltage doubler. Using a negative CP extends the operating region below ground to relieve the power delivery limitation of the CP. A second embodiment provides a low power adaptive dead-time circuit, which has several dead-time signals having different lengths of dead-times and selects one according to the input voltage level. A low input voltage detector in the adaptive dead-time circuit is used to determine which dead-time should be used. A third embodiment provides a switching body bias used for the low input voltage CP. The switching body bias uses both forward and reverse body bias applied to the CP to minimize reverse current and maximize power transfer. The first, second, and third embodiments can be used together or independently. |
| US09634555B2 |
Method for operating a non-isolated switching converter having synchronous rectification capability suitable for power factor correction applications
A power factor correction (PFC) boost circuit. The PFC boost circuit can include a first switching device, a second switching device, a first gate driver coupled to the first switching device, a second gate driver coupled to the second switching device, and a PFC controller configured to control the first and second gate drivers. The PFC controller will utilize a new technique, referred to herein as “predictive diode emulation” to control the switching devices in a desired manner and to overcome inefficiencies and other problems that might arise using traditional diode emulation. The PFC controller is configured to operate in synchronous and non-synchronous modes. |
| US09634554B2 |
Short-circuit switch having semiconductor switch and arrangement for short-circuiting a three-phase alternating voltage
A short-circuit switch for use with a first electrical conductor and a second electrical conductor includes a controllable semiconductor switch that is configured to short-circuit a voltage present between the first conductor and the second conductor responsive to receipt of a trigger, and a mechanical press-pack structure. The controllable semiconductor switch is a press-pack-type thyristor having a first planar electrode and a second planar electrode on contact sides situated opposite one another. The thyristor is disposed in the mechanical press-pack structure. The mechanical press-pack structure includes: a first terminal electrode that is configured to connect the first planar electrode to the first conductor, wherein the first terminal electrode is resiliently supported by a spring assembly; and a second terminal electrode that is configured to connect the second planar electrode to the second conductor. The press-pack structure forms a protective cover enveloping the thyristor. |
| US09634553B2 |
Method and control device for protection time setting in an electric drive system
The invention relates to a control device (12) for actuating a pulse-controlled converter of an electric drive system, having: an open-loop/closed-loop control circuit (12a) which is configured to generate pulse-width-modulated actuation signals for switching devices of the pulse-controlled converter; a fault logic circuit (12b) which can detect fault states in the drive system and which is configured to select a switching state or a sequence of switching states for the switching devices of the pulse-controlled converter which are assigned to the corresponding fault state; and a protection circuit (12c) which is embodied in hardware and which comprises a signal delay device (15), which is configured to delay the actuation signals in order to implement a minimum protection time, and a locking device (16a, 16b) which is configured to lock two complementary switching devices of a bridge branch of the pulse-controlled converter with respect to one another. |
| US09634552B2 |
Solid-state phase splitting transformer
A solid state power transformer is described for converting an input power signal at a first phase or voltage to an output signal of a second voltage or opposite phase by the use of bidirectional solid state switches switched at a high carrier frequency to produce a double-sideband, suppressed-carrier representation of the input power signal, which is then synchronously demodulated using further similar switches to produce the desired output. It is further disclosed that multiple instances of the above with relative phase-staggering of the switching frequency may be operated in parallel and activated or deactivated according to output current demand to provide maximum efficiency over a wide range of current and power levels. |
| US09634551B2 |
Direct current brushless motor
A motor includes a frame, a shaft rotatably mounted onto the frame, and at least one disc mounted onto the shaft. At least one permanent magnet is mounted on the disc, and at least one electromagnet and at least one coil are mounted to the frame in rotational magnetic proximity to the permanent magnet. A battery is connectable to the electromagnet and the coil for energizing the electromagnet and for receiving electrical current from the coil for charging the battery. A relay switch controls the transmission of electrical power from the battery to the electromagnet. A sensor generates a signal to the relay switch to activate electrical power to the electromagnet upon sensing that the permanent magnet is positioned with respect to the electromagnet such that a magnetic force generated by the electromagnet would be effective for inducing movement of the permanent magnet and consequent rotation of the disc. |
| US09634549B2 |
Dual phase magnetic material component and method of forming
A magnetic component having intermixed first and second regions, and a method of preparing that magnetic component are disclosed. The first region includes a magnetic phase and the second region includes a non-magnetic phase. The method includes mechanically masking pre-selected sections of a surface portion of the component by using a nitrogen stop-off material and heat-treating the component in a nitrogen-rich atmosphere at a temperature greater than about 900° C. Both the first and second regions are substantially free of carbon, or contain only limited amounts of carbon; and the second region includes greater than about 0.1 weight % of nitrogen. |
| US09634547B1 |
Motor grounding seal
A shaft seal assembly is disclosed having a stator including a main body and axial and radial projections therefrom. The rotor may be radially extended to encompass the axial and radial projections from said stator. A passageway formed between the radial projection of stator and rotor results in an axial passageway having its opening facing rearwardly from the rotor and away from the source of impinging coolant and/or contaminant. A concentric circumferential receptor groove in the stator facing the housing allows insertion of a conductive insert for transmission of electrostatic charge away from the shaft through the shaft seal assembly to the housing and ground. The receptor groove is opposite the axial passageway and provides for both a substantially lower contaminant environment and improved engagement with the conductive insert. |
| US09634542B2 |
Electric device for a bicycle
An electric device for a bicycle has a casing, a pedal shaft, a motor shaft, a rotor assembly, a stator assembly, a gear assembly, a chain wheel and a control unit. Because a normal of the circuit board of the control unit is parallel to the motor shaft, the circuit board can be axially adjacent to a side surface of the rotor assembly to detect the rotor assembly. Thus, one single circuit board can detect the rotor assembly as well as maintain electric connection with other components, thereby saving space and reducing the volume of the casing. As the casing has a reduced volume, interference with the rear wheel can be avoided. |
| US09634538B2 |
Terminal assembly for refrigeration compressor
A terminal assembly configured to conduct current from an external power source to a hermetical motor-compressor unit. The terminal assembly includes a terminal board, at least one opening defined through the thickness of the terminal board, at least a conductive pin received in the opening, and an insulator having a convoluted contour. The insulator may be disposed over the conductive pin and spaced away from the terminal board. |
| US09634537B2 |
Motor provided with terminal block
A motor which can reliably prevent varnish from ending up entering a terminal block. The motor is provided with a terminal block to which lead wires of coils are connected. The terminal block has a bottom wall, a plurality of side walls which face each other, a terminal part which is provided between adjoining side walls, and a dam wall which is arranged at a position closer to the coils than the terminal part and which is formed integrally with the bottom wall and side walls without clearance. The dam wall has a lead wire holding part for holding a lead wire. |
| US09634532B2 |
Inertial drive actuator
An inertial drive actuator includes a shift unit that generates a shift in a first direction and in a second direction opposite to the first direction, a base plate that moves with the shift of the shift unit, and a mover disposed on a surface of the base plate and having a magnetic field generating unit. The mover has a first yoke that guides magnetic flux generated by the magnetic field generating unit such that the magnetic flux concentrates on a surface of the mover facing the base plate with respect to both S and N poles. Also included is a second yoke provided on a side of the base plate facing away from the mover. The frictional force acting between the mover and the base plate is controlled by controlling a magnetic field generated by the magnetic field generating unit to drive the mover. |
| US09634530B2 |
Interior permanent magnet motor with shifted rotor laminations
A rotor comprises a first rotor lamination and a second rotor lamination. The first rotor lamination and the second rotor lamination are configured for defining, when joined into rotor assembly, a central axis of rotation and a plurality of interior magnet pockets disposed symmetrically about the central axis of rotation, each pocket of the plurality of interior magnet pockets is configured for housing and retaining a permanent magnet. A method of forming a rotor comprises forming a first rotor lamination and a second rotor lamination, rotating the second rotor lamination about an axis of symmetry of the second rotor lamination; and mating the first rotor lamination to the second rotor lamination such that a first notch of the first rotor lamination is disposed adjacent to the first notch of the second rotor lamination. |
| US09634525B2 |
Non-contact type power receiving apparatus
In a non-contact type power receiving apparatus, two power receiving coils may share a single rectifying circuit. A non-contact type power receiving apparatus may include a first power receiving coil and a second power receiving coil, and a selective rectifying unit rectifying power from one of the first and second power receiving coils which receives the power from an external power transmitting coil in a non-contact scheme. |
| US09634524B2 |
Wireless power supply system
A wireless power supply system includes a power-supplying device mounted on one of a mobile object and a structure different from the mobile object and a power-receiving device mounted on the other of the mobile object and the structure and supplies electric power from the power-supplying device to the power-receiving device disposed to face the power-supplying device under water or on surface of water. The wireless power supply system includes a contact portion that is disposed in the mobile object and that comes in contact with the structure and a thruster that presses the contact portion against the structure during the transmission of electric power. |
| US09634520B2 |
Case for mobile electronic device
A case for a mobile electronic device is a case for a mobile electronic device which is capable of accommodating a mobile electronic device with a display surface, and supplying electric power to the mobile electronic device, the case including: a holder section having a first face which comes in contact with at least a portion of the mobile electronic device and a second face opposite from the first face; a protection cover to cover the display surface; a solar cell module provided on the protection cover to generate electric power, the solar cell module being externally exposed when the display surface is covered by the protection cover; and a moving mechanism capable of moving the protection cover over to the second face side while maintaining the solar cell module in an externally exposed state. |
| US09634516B2 |
Method and system for monitoring temperature of a power distribution circuit
A method for monitoring a temperature change of a power distribution circuit having a power line and return line includes measuring an output current and output voltage of the power distribution circuit at an input to a load electrically connected to the power distribution circuit, and determining a change in temperature of at least one of the power line and return line based on a change in at least one of the output current and output voltage. |
| US09634515B2 |
Non-contact wireless communication coil, transmission coil, and portable wireless terminal
A chargeable communication module is provided, which includes: a wireless power charging coil; a wireless communication coil being electrically isolated from the wireless power charging coil; and a magnetic body. The wireless power charging coil is disposed on a surface of the magnetic body. The wireless communication coil is arranged peripheral to the wireless power charging coil. A center of the wireless power charging coil is offset from a center of the wireless communication coil. |
| US09634514B2 |
Single stage rectification and regulation for wireless charging systems
A rectification and regulation circuit for a wireless power receiver includes a coil, a full-wave rectifier circuit and a control unit. The full-wave rectifier has a first pair of controllable rectifiers including a first transistor connected to a first terminal of the coil and a second transistor connected to a second terminal of the coil. The control unit is operable to control switching of the transistors of the full-wave rectifier so that the full-wave rectifier (a) generates a rectified output for charging a battery of the wireless power receiver by rectifying current through the coil or voltage across the coil and (b) regulates the rectified output. |
| US09634510B2 |
Method of controlling charging and discharging of battery energy storage device and the battery energy storage device for the same
A method of charging and discharging battery energy storage device is provided. The method includes measuring a voltage and a frequency of a grid, measuring a state of charge (SOC) value of a battery, calculating an SOC offset value and an SOC feedback gain value from the measured SOC value of the battery, and performing a voltage droop control based on the voltage of the grid and a frequency droop control on the basis of the frequency of the grid, the SOC offset value and the SOC feedback gain value and controlling charging and discharging of the battery. |
| US09634503B2 |
Battery chargers
In one aspect according to the present teachings, a battery charger may include a body housing and a power supply connector disposed at a lateral side of the body housing. The power supply connector can supply a DC power to an external device. |
| US09634501B2 |
Protective circuit of unit cell
The protective circuit includes a voltage dividing circuit connected in parallel between a first electrode and a second electrode of the unit cell and including a first voltage dividing resistor and a second voltage dividing resistor; a first switching device connected to a junction between the first voltage dividing resistor and the second voltage dividing resistor; a second switching device connected between the junction and the third switching device; and a fourth switching device connected between the junction and the third switching device, wherein, when output voltage of the unit cell becomes equal to or lower than a first reference voltage, the fourth switching device and the first switching device are sequentially turned off, the second switching device is turned on, and the third switching device is turned off, so that voltage output through the first output terminal can be cut off. |
| US09634500B2 |
Storage battery system
The storage battery system includes a storage battery comprising a plurality of battery modules; a plurality of voltage monitoring circuits for monitoring a voltage of the battery module; and a control device that controls charging and discharging of the storage battery on the basis of monitoring information that is obtained by carrying out communication with the voltage monitoring circuits, wherein the control device comprises a determination unit that calculates an estimated output voltage of the storage battery by using the monitoring information that is obtained from any one of the voltage monitoring circuits before occurrence of a communication failure in a case where the communication failure with any one of the voltage monitoring circuits occurs, and compares the estimated output voltage and an output voltage of the storage battery after occurrence of the communication failure to determine an abnormal site of the communication failure. |
| US09634499B2 |
Adjusting device, battery pack device, and adjusting method
An adjusting device that adjusts voltage differences among a plurality of storage batteries that are connected in series is provided with: charging means that charges said storage batteries; each switching means that corresponds to each of said plurality of storage batteries, that connects a corresponding storage battery to said charging means in parallel when turned ON, and that releases the connection between the corresponding storage battery and said charging means when turned OFF; detection means that detects each voltage of said plurality of storage batteries; and control means that turns ON, from among a plurality of said switching means, the control-object switching means that corresponds to the charge-object storage battery, which has the lowest voltage that is detected by said detection means, from among said plurality of storage batteries, and moreover, that turns OFF switching means other than said control-object switching means. |
| US09634497B2 |
Battery charging method and battery management system therefor
A battery charging method, including obtaining a voltage capacity ratio for a reference charge C-rate and voltage capacity ratios for N (N an integer of 1 or more) charge C-rates greater than the reference charge C-rate, each of the voltage capacity ratios for the reference charge C-rate and the N charge C-rates being defined as a ratio of a voltage variance to a capacity variance depending on a change in state of charge (SOC) of a battery when the battery is charged at a corresponding one of the C-rates, comparing the voltage capacity ratio of the reference charge C-rate with each of the voltage capacity ratios of the N charge C-rates, and then setting a charge C-rate of the N charge C-rates so that a difference in voltage capacity ratio is minimized for each of SOC sections, and charging the battery with the charge C-rates corresponding to the SOC sections. |
| US09634495B2 |
Wireless power transfer using separately tunable resonators
A system for wireless energy transfer includes a circuit for wireless transmission of energy, including a first, tunable resonator circuit including a transmitter coil and a variable capacitance device connected in shunt across the transmitter coil. Also disclosed is a circuit for wireless reception of energy including a tunable second resonator circuit including a receiver coil inductively coupled to the transmitter coil and a variable capacitance device connected in shunt across the receiver coil. Also disclosed is an arrangement for wireless energy transmission and reception that foregoes the necessity for separate circuits for DC rectification at the reception end of the arrangement. Also disclosed a system for wireless energy transfer where the system includes a tunable resonator circuit embedded in a surface such as piece of furniture, counter, etc., e.g., a table. |
| US09634492B2 |
Power generation method and system of power generator
Provided are a power generation method and system of a power generator that can allow an output power of the power generator to be constant and cope with a case in which the velocity of a power generation source changes very quickly at a low lost. The power generation method includes determining a reference total power intended to be generated by a plurality of power generators, calculating a current command value through the reference total power and an instantaneous velocity sensed by each of the plurality of power generators, and regulating an output current of the power generator using the calculated current command value such that a total power output by the plurality of power generators is approximate to the reference total power. |
| US09634487B2 |
Architecture and management system and device for micro-grids with energy generation, storage and consumption, of the totally integrated, dynamic and self-configurable type
Architecture system of a local grid made up of at least two single nodes constituting micro-grids, each managed by a self-configurable node controller that is also connected to the controllers of the other nodes and to the single energy generation, storage and consumption elements of its own node, the elements being variable in their configuration and dynamic in their behavior; the controller also optimizing the energy transfers according to specific management logics of the routine and sub-routine type. |
| US09634480B1 |
MOSFET protection using resistor-capacitor thermal network
A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element. The RC circuit is responsive to the output current of the transconductance amplifier to produce an output voltage used to control the semiconductor element. |
| US09634475B2 |
Strain relief device for a harness or cable
A strain relief device includes an elongated body having a first and second end, the elongated body defining an elongated hole extending from the first end to the second end; and edges in the body defining a plurality of voids between the first and second end, wherein the edges become shorter in length from the first end to the second end such that the shorter edges define progressively smaller voids in the body from the first end to the second end. A method of providing a strain relief is also disclosed. |
| US09634474B2 |
Electrical wiring system and method
An electrical wiring system/method implementing transient voltage suppression is disclosed. The system/method incorporates HOT, NEUTRAL, GROUND wiring in conjunction with a series drop resistor (SDR) on the HOT conductor that supplies current to the load device. Parallel shunting metal oxide varistors (MOVs) are used in conjunction with corresponding shunt diode rectifiers (SDRs) to suppress transients on the HOT conductor to either the GROUND conductor and/or NEUTRAL conductor. The parallel shunting MOV/SDR pairs may be integrated into a singular structure that is encapsulated in an insulating material to permit implementation of the transient protection wiring system/method into electrical loads and common power distribution equipment such as electrical outlets and power strips. |
| US09634470B2 |
Method of constructing a distribution line using an extra-high voltage neutral line
The present invention relates to a distribution line, and more particularly, to a method of constructing a distribution line using an extra-high voltage neutral line combined with an overhead earth wire having a separate installation structure of the extra-high voltage neutral line and a low-voltage neutral line for improving electric power quality, in which a distribution line simultaneously perform functions of an overhead earth wire for shielding lightning, an extra-high voltage neutral line for returning unbalanced currents and fault currents and an optical communication line for establishing a communication network, such that a number of disconnections of power lines is reduced by reducing surge voltage thereby achieving excellent lightning shielding effects such as improved power quality, etc., construction costs are reduced, load is reduced, construction quality is improved, and aesthetic features of the urban area is improved by simplifying the distribution equipment. |
| US09634467B2 |
Vertical cavity surface emitting laser and atomic oscillator
A vertical cavity surface emitting laser includes: a laminated body; an insulation layer which is provided over at least a portion of the laminated body; an electrode of which at least a portion is provided over the laminated body; a pad; and a wiring which connects the electrode and the pad, wherein the laminated body includes a first mirror layer, an active layer, and a second mirror layer, the laminated body includes a first distortion imparting portion, a second distortion imparting portion, and a resonance portion which is provided between the first distortion imparting portion and the second distortion imparting portion, in a plan view, the electrode is provided so as to cover at least a portion of the resonance portion, in the plan view, a width of the wiring is greater than a width of the first distortion imparting portion and is smaller than a width of the electrode. |
| US09634466B2 |
External-cavity type laser with built-in wavemeter
The present invention relates to an external cavity type laser provided with a wavemeter capable of precisely measuring a wavelength of a laser beam based on a transmission wavelength band of a wavelength selective filter inserted into a cavity regardless of a driving current of a laser diode chip. The external cavity type laser apparatus includes: a laser diode chip 100 emitting a laser beam; a beam feedback partial reflection mirror 500 reflecting a portion of the beam emitted from the laser diode chip 100 to feed the beam back to the laser diode chip 100; a collimating lens 200 installed on a path of a beam between the laser diode chip 100 and the beam feedback partial reflection mirror 500 to collimate the beam emitted from the laser diode chip 100; a 45-degree partial reflection mirror 300 converting a laser beam moving in parallel with a package bottom surface into a laser beam moving perpendicularly to the package bottom surface; a wavelength selective filter 400 transmitting a beam having a selected specific wavelength therethrough; a beam strength monitoring photodiode 600 disposed on a path of a beam moving from the collimating lens 200 to the 45-degree partial reflection mirror 300 and transmitting through the 45-degree partial reflection mirror 300; and a wavelength monitoring photodiode 700 disposed on a path of a beam moving from the wavelength selective filter 400 to the 45-degree partial reflection mirror 300 and transmitting through the 45-degree partial reflection mirror 300. A magnitude of a photocurrent flowing to the wavelength monitoring photodiode 700 is changed depending on a strength of a beam output oscillated in the laser diode chip 100 and a reflectivity at the wavelength selective filter 400, and a photocurrent flowing to the beam strength monitoring photodiode 600 is determined by the strength of the beam output outputted from the laser diode chip 100. Therefore, a value obtained by dividing the photocurrent flowing to the wavelength monitoring photodiode 700 by the photocurrent flowing to the beam strength monitoring photodiode 600 depends on only the reflectivity at the wavelength selective filter 400. Therefore, the value obtained by dividing the photocurrent flowing to the wavelength monitoring photodiode 700 by the photocurrent flowing to the beam strength monitoring photodiode 600 provides information on the wavelength of the laser beam based on the transmission band wavelength of the wavelength selective filter 400, and the wavelength of the laser beam may be figured out by measuring the value, and may be very precisely determined to be a predetermined wavelength. |
| US09634462B2 |
Slanted FBG for SRS suppression
An example apparatus includes an optical fiber including a core and cladding, the core being situated to propagate an optical beam along a propagation axis associated with the core, and at least one fiber Bragg grating (FBG) situated in the core of the optical fiber, the fiber Bragg grating including a plurality of periodically spaced grating portions situated with respect to the propagation axis so that light associated with Raman scattering is directed out of the core so as to reduce the generation of optical gain associated with stimulated Raman scattering (SRS). |
| US09634461B1 |
Geometric isolator providing isolation between resonantly pumped cascaded laser
A fiber optic geometric isolator is disclosed which is inserted between two cascaded, high-power fiber optic lasers and, in conjunction with a cladding mode stripper, provides improved optical Isolation between the two fiber optic lasers while maintaining highly-efficient laser operation. The isolator achieves this without the need for electromagnetic isolation between the two cascaded lasers. The isolator is an optical fiber designed to operate as a monolithic, continuous waveguide to enable a specific mode-coupling condition that converts the light of a first laser to that of a second, cascaded laser, with the light moving from the core of the first laser to both the core and the cladding of the second laser. |
| US09634456B2 |
Gas laser oscillation apparatus of orthogonal excitation type
A gas laser oscillation apparatus of orthogonal excitation type includes an electric discharge region having a pair of electric discharge electrodes, an axial flow blower having a plurality of rotor vanes and working by a permanent magnet motor, a first heat exchanger having a plurality of cooling fins, the cooling fins arranged on a plane perpendicular to an optical axis, a second heat exchanger having a plurality of cooling fins, the cooling fins arranged on a plane perpendicular to the optical axis, a gas duct having a gas passageway and arranged between the electric discharge region and the first heat exchanger, the axial flow blower being arranged on the gas passageway. The axial flow blower is arranged on a windward side of the first heat exchanger. The second heat exchanger is arranged on a windward side of the axial flow blower. |
| US09634454B1 |
Laser illumination systems and methods for dual-excitation wavelength non-linear optical microscopy and micro-spectroscopy systems
An illumination system is disclosed for providing dual excitation wavelength illumination for non-linear optical microscopy and micro-spectroscopy. The illumination system includes a laser system for providing a first train of pulses at a center optical frequency ω1, a frequency converting system for providing at least a second train of pulses at a center optical frequency ω2 and a third train of pulses at a center optical frequency ω3, where ω2 is different from ω1 and ω3 responsive to the first train of pulses, an amplifier system for amplifying the second train of pulses to provide an amplified second train of pulses, and an adjustment means for adjusting a time delay between the amplified second train of pulses and the third train of pulses for the dual-excitation wavelength illumination. |
| US09634452B2 |
Printed circuit board connector ejector
A printed circuit board connector ejector includes a body extending from a first end to a second end. The body includes an outer surface and a passage extending through the body between the first and second ends. A plurality of threads extend at least partially though the passage. The plurality of threads is configured and disposed to engage with an electrical connector. An actuation member extends radially outwardly from the outer surface. The actuation member is configured and disposed to facilitate rotation of the body relative to an electrical connector. |
| US09634450B2 |
Electric wire with connector and method for manufacturing the same
An electric wire with connector includes: an electric wire; a connector having a housing chamber to house an electric terminal provided at an end of the electric wire, the housing chamber opening on an end surface of the connector; and a waterproof member to cover the housing chamber. The waterproof member includes a sheet member having a width extending from the end surface of the connector as a reference position toward both of the connector and the electric wire. The sheet member has a wrapping shape winding around in a manner to have an overlapped region of the a front surface of one end of the sheet member and a back surface of the other end of the sheet member. The front surface and the back surface are contacted each other at the overlapped region. An inner peripheral surface of an end part of the waterproof member near the connector is contacted to an outer peripheral surface of the connector, and at least part of an inner peripheral surface of the other end part of the waterproof member near the electric wire is contacted to an outer peripheral surface of the electric wire. |
| US09634447B1 |
Electrical communication adapter system having an adapter board assembly and connector for interfacing with military communication systems
An adapter system suited suitable for use in association with legacy military connectors including an adapter board assembly and an electrical cable connector. The adapter board assembly includes a pair of legacy connectors and a high density connector. A connector attachment block is attached to the adapter board assembly. The electrical cable connector includes a first side coupling assembly, a second side coupling assembly and a cable member extending therebetween. The first side coupling includes a connector matingly electrically attachable to the high density connector of the adapter board assembly, and a housing attachable to the connector attachment block. The adapter board assembly and the electrical cable connector are likewise separately disclosed. |
| US09634444B2 |
Cabinet backplane interconnect
An interconnect for an installation environment adapted for housing at least one electrical component having a number of first connectors each having a first configuration, wherein the installation environment has pre-installed wiring having a number of second connectors each having a second configuration. The interconnect includes a backplane component including a number of third connectors adapted to connect with the number of first connectors, and a number of fourth connectors adapted to connect with the number of second connectors, wherein each of the number of fourth connectors is coupled to a respective one of the number of third connectors in a manner that maps the second configuration to the first configuration, and includes a mechanical bracket component adapted to allow for the installation of at least one electrical component such that the first connectors are connected to the third connectors. |
| US09634443B2 |
Connector and contact
A connector includes a housing attached to a board; a ground terminal including a ground base disposed in the housing, and a first ground connection part extending from the ground base toward a first end of the housing and to be connected to a ground line of a coaxial cable; and a signal terminal including a signal base that is held in the housing and surrounded by the ground base while being insulated from the ground base, and a first signal connection part extending from the signal base toward the first end of the housing and to be connected to a signal line of the coaxial cable. The ground terminal and the signal terminal are configured to elastically bend at a second end of the housing when the housing is attached to the board. |
| US09634436B2 |
Electrical connector with locking structures for assembling contact modules
An electrical connector includes an insulative housing, a number of first contact modules, a number of second contact modules and a number of third contacts all assembled into the insulative housing. Each first contact module includes a first wafer and first contacts insert-molded in the first wafer. Each second contact module includes a second wafer and second contacts insert-molded in the second wafer. The first contact modules, the second contact modules and the third contacts are arranged side by side after being inserted into the insulative housing. The adjacent first wafer and the second wafer cooperatively include mutual locking structures so that they can be inserted into the insulative housing in turn under a predetermined sequence. |
| US09634433B1 |
Communication jack having a dielectric film between plug interface contacts
Embodiments of the present invention relate to designs for network jacks which can be used for cable connectivity. In an embodiment, the present invention is an RJ45 jack that utilizes a thin dielectric film between two layers of PICs that provide crosstalk compensation by way of their geometry. Compensation is achieved by way of capacitor plates which sandwich a thin dielectric film. This allows for the layers of PICs to be in close proximity and achieve higher coupling where desired, allowing a greater amount of compensation to occur close to the plug/jack contact point. This can have the effect of moving compensation closer to the plug/jack contact point, which in turn may reduce the amount of compensation needed further along the data path. |
| US09634432B2 |
High frequency connector with enhanced grounding for reduced crosstalk
A high frequency connector with enhanced grounding for reduced crosstalk includes an insulative main body, a plurality of first terminals and second terminals, a back cover and a grounding member. The first terminals and the second terminals are disposed in the insulative main body, the back cover is provided at the second end of the insulative main body. The back cover is formed with an opening and capable of preventing the first terminals from being detached from the insulative main body. The grounding member has a body portion and contact sprint portion, the body portion is disposed inside the insulative main body and located between the first terminals and second terminals. The contact spring portion extends outward from the insulative main body and contacts the metal case of a mating plug connector for reducing crosstalk and restraining electromagnetic interference. |
| US09634430B1 |
Card edge connector
A card edge connector can allow an insertion card with a locating groove on one side to be inserted thereto, the card edge connector including: a base housing, and an elastic clamping part. Two ends of the base body have two clamping portions, one sides thereof which are opposite are concaved to form a limiting slot, respectively; the elastic clamping part is fastened within one of the clamping portions, the elastic clamping part comprising a fastening base, an elastic arm, an elastic resisting portion and a limiting portion, one end of the fastening base can be retained in the clamping portion, another end thereof being connected with the elastic arm, a partial section of the elastic arm away from the fastening base being bent to form the elastic resisting portion, which can be exposed correspondingly to the limiting slot of the clamping portion retained by the elastic clamping part, one end of the elastic arm away from the fastening base having the limiting portion, so that it can be retained in the clamping portion; thereby, the insertion card may be prevented from vibration or shaking after insertion. |
| US09634429B2 |
Connector for a power input
A connector includes a socket configured to be secured within a socket opening of a power input. A socket head has a plurality of plug insert receptacles. Each plug insert receptacle receives a conductive insert. The conductive insert connects with a cable that extends from the plug insert receptacle through and out of the socket. A plug contains a base. A head of the base has a plurality of plug insert units. Each plug insert unit receives a conductive insert that connects with a cable that extends out the base of the plug. A handle covers the base. The handle and the base are fixed and connected by a positioning device that includes an inverted tooth structure. The socket and plug when connected are secured in place by an elastic hasp. |
| US09634427B2 |
Shock and vibration resistant bulkhead connector with pliable contacts
A high pressure and temperature, hermetically sealed bulkhead connector with pin and socket contacts for use in logging tools is described. The bulkhead connector comprises (a) one or more contact(s) placed within one or more channels wherein the channels provide a clearance path between contact(s) and bulkhead body and travel at least a partial longitudinal distance between proximal and distal ends. The contact(s) reside in the channel(s) and include at least; an optional movement limiter section, one central elongated section, and one fixed section where the contact(s) is attached to the bulkhead body at the distal end. The body correctly positions respective ends of the contact so that the body secures contact(s) to be parallel to each other and the contact(s) have terminal ends for connection. This arrangement provides at least one pivotable, pliable, free floating contact extending away from the fixed distal end of the bulkhead body. |
| US09634420B2 |
Electrical connector having a retainer
An electrical connector has a retainer including a cantilever-type arm that operates with a small force. The retainer is held in the connector housing so as to be movable between a pre-latch position and a complete latch position, retaining terminals at the complete latch position. The retainer has: a first latch on the connector housing at the pre-latch position; a second latch on the connector housing at the complete latch position; a cantilever-type first elastic beam having a free end side formed with the pre-latch projection; and a second elastic beam having both ends supported by the first elastic beam and formed with the complete latch projection. |
| US09634419B2 |
Cold forming method for forming power pins and power pin formed thereof
The invention discloses a cold forming method for forming power pins and a power pin formed thereof. The cold forming method for forming power pins comprises the following steps: step 1: cutting blank out; step 2: pre-forming the power pin body by necking; step 3: trimming the pre-formed power pin body, and pre-forming a pin fixing disk; step 4: forming the pin fixing disk and a staggered weld leg of pin. The invention also discloses a power pin formed by the cold forming method, composed of a power pin body, a pin fixing disk and a staggered weld leg of pin which are integrally formed into one piece by the cold forming method. The invention achieves high-speed automatic production and high production efficiency with a simple process, and improves material utilization and strength. |
| US09634417B2 |
Power connector
A connector is disclosed including a housing and a pair of terminals. Each terminal includes a planar body portion and a planar mounting portion formed at the first end of the body portion with a bent contacting portion disposed therebetween. A wire securing portion is formed at the second end of the body portion with a pair of crimping portions to secure the wire to the terminal. The body portion and the mounting portion are received in a slot formed in the housing with the contacting portion extending through a window formed in the housing and the terminal mounting portion being translatable within the slot. |
| US09634416B2 |
Electrical connection arrangement
A connection arrangement (10) for electrically connecting at least one sensor (12) or actuator to at least one conductor track (22) on a circuit board (24) has at least one compression spring (18) for electrically conductive connection. The compression spring (18) is arranged between the at least one sensor (12) or actuator and the circuit board (24) so as to be under a mechanical preload. The compression spring has a contact end section (36) of the at least one compression spring (18) configured to rest against a contact plate (20, 70, 80, 90) that is electrically conductively connected to the conductor track (22). As a result, the connection arrangement (10) achieves a high level of electrical contact reliability and corrosion-resistance. |
| US09634413B2 |
Connector
A connector has a socket contact to be electrically connected to a counter-connector contact, the socket contact including: one or more pairs of conduction contact points disposed respectively on both sides of a fitting plane in an elastically displaceable manner; and one or more pairs of displacement regulator contact points disposed respectively on both sides of the fitting plane and coming into contact with the counter-connector contact when the counter-connector contact shifts, the one or more pairs of conduction contact points and the one or more pairs of displacement regulator contact points are disposed side by side in a direction along the fitting plane at a substantially same depth in a fitting direction, each of the pairs of displacement regulator contact points having a gap therebetween larger than that in each of the pairs of conduction contact points. |
| US09634411B2 |
Contact device mechanically mountable and electrically connectable on a printed circuit board by a fastening portion for receipt of an external plug element
A contact device which is adapted to be mechanically mounted and electrically connected on a printed circuit board by a fastening portion and serves for receiving an external plug element. The contact device comprises a contact portion for inserting the external plug element for forming an electrical contact, an elastic support element for movably supporting the contact portion and for providing a possibility of movement in all spatial directions, wherein the support element includes a fastening part by which the contact device is fastened on the printed circuit board, a contact part for directly supporting the contact portion and a center part for connecting the fastening part and the contact part, the fastening part and the contact part bent relative to the center part, and of movement of the contact part and center part are limited by predetermined distances from adjacent external limiting means in the fastened state. |
| US09634408B2 |
Electrical circuit arrangement having a terminal on a flexible sheet disposed between a support layer and a counter contact
In an electrical circuit with at least one flexible sheet element with electrical conductor tracks, at least one terminal arrangement for connection to a power supply and/or for data transmission, provision is made for the terminal to be formed by a portion of the sheet element with exposed conductor tracks, against which counter-contacts are positioned. |
| US09634407B2 |
Terminal module
A terminal module is used for electrically connecting an electric element mounted on a first board to a second board opposing to the first board. A through-hole is opened in the second board. The terminal module includes: an electrically conductive terminal including at each of opposite ends thereof; a connection part through which the terminal module is electrically connected to the electric element; and a contact part to be inserted into the through-hole; and an electrically insulative base holding a part of the electrically conductive terminal to keep the electrically conductive terminal in a constant posture. The terminal module is mounted onto the first board keeping fixed thereto. |
| US09634402B2 |
Polarization diversity in array antennas
An array antenna includes at least two antenna elements that are axially-aligned and axially-spaced. Polarization diversity is provided by at least one driven antenna element that provides horizontal and vertical polarizations. The driven element includes one or more feed points for the horizontal polarization and one or more feed points for the vertical polarization. A switching circuit is configured to switch between the one or more feed points to alternately provide the horizontal and vertical polarizations. |
| US09634401B2 |
Antenna array
This antenna array includes at least one primary antenna, at least one secondary antenna and at least one load coupled to a secondary antenna. The load includes two separate components, a first component being a resistor and a second component being selected from an inductor or a capacitor. The antenna array can include one or more of the following characteristic features, taken into consideration individually or in accordance with any technically possible combinations: the first component has negative resistance; the second component has negative inductance or a negative capacitance; at least one load has an adjustable impedance. The antenna array may be used in a system, such as a vehicle, a terminal, a mobile telephone, a wireless network access point, a base station, or a radio frequency excitation probe. |
| US09634399B1 |
Antenna for transmitting partial orbital angular momentum beams
An antenna system can impart orbital angular momentum (OAM) to an incident electromagnetic (EM) signal from a feed antenna. The antenna system can include a partial OAM antenna with a reflective surface that has only part of a full OAM shaped surface. The antenna system can thus reflect the incident EM signal as a partial OAM beam rather than a full OAM beam. |
| US09634392B2 |
Multi-coil module and electronic device
The loss is reduced even when loop coils of a multi-coil module are overlaid with each other. The multi-coil module includes a first coil module, having a first magnetic sheet and a first loop coil provided on the first magnetic sheet and wound in a planar shape, and a second coil module, having a second magnetic sheet and a second loop coil provided on the second magnetic sheet and wound in a planar shape. The first coil module and the second coil module are stacked on each other, and at least an innermost coil pattern of the first loop coil and the second loop coil are overlaid with each other. The line width of the innermost coil pattern t of the first loop coil overlaid with the second loop coil is 1 mm or less. |
| US09634390B2 |
Antenna device
A variable resonant circuit is inserted between a feeding point of a radiating element and a ground conductor. When the variable resonant circuit is not inserted, an input impedance of the radiating element is lower than about 50Ω and capacitive in a first low frequency band, lower than about 50Ω and inductive in a second low frequency band, and close to about 50Ω in a high frequency band. When the variable resonant circuit exhibits a first resonance characteristic, the variable resonant circuit is inductive in the first low frequency band, and its impedance in the high frequency band is higher than that in the first low frequency band. When the variable resonant circuit exhibits a second resonance characteristic, the variable resonant circuit is capacitive in the second low frequency band, and its impedance in the high frequency band is higher than that in the second low frequency band. |
| US09634389B2 |
Multipath switching system having adjustable phase shift array
A multipath switching system comprising of an adjustable phase shift array includes, an adjustable phase shift array module and a control module. The adjustable phase shift array module receives a radio-frequency (RF) signal, and includes at least one RF switch, at least one coupler and at least one phase shifter. The at least one RF switch, the at least one coupler and the at least one phase shifter form a number of transmission paths. The transmission paths respectively produce the processed transmission RF signals corresponding to different phase shifts to an antenna array. The control module controls the at least one RF switch and the at least one phase shifter of the adjustable phase shift array module, so that the antenna array radiates a wireless signal whose direction is corresponding to a predetermined angle in space polar coordinates. |
| US09634388B2 |
Antenna beam
A fixed phase shift for each of a plurality of radio frequency signal components directed to or received from a plurality of antenna elements is formed in a phase shifter. A desired antenna beam pattern with at least one grating lobe is formed on the basis of the phase-shifted radio frequency signal components of the antenna elements in a predefined antenna structure. |
| US09634385B2 |
Antenna apparatus and terminal device
An antenna apparatus and a terminal device are provided, which relate to the field of communications technologies. A switch disposed at an end of an antenna arm controls an antenna to switch to different resonance frequencies, therefore reduced antenna efficiency caused by switch loss is avoided and space occupied by the antenna is not increased. The antenna apparatus includes an antenna and a printed circuit board, where a feedpoint and a first grounding point are disposed on the printed circuit board, the antenna is connected to the feedpoint, and the antenna includes a first arm. |
| US09634384B2 |
Chip antenna and manufacturing method thereof
After a three-dimensional antenna pattern (10) is formed by bending a conductive plate, the three-dimensional antenna pattern (10) thus bent is supplied in an injection molding die set as an insert component and a base (20) is formed by injection molding of a resin. With this, a chip antenna (1) comprising the three-dimensional antenna pattern (10) can be formed easier as comparison to a case where the antenna pattern is formed over a plurality of surfaces by printing and the like. |
| US09634383B2 |
Galvanically separated non-interacting antenna sector apparatus and methods
An antenna apparatus with isolated non-interactive sectors and methods operating and forming the same. In one embodiment, an antenna with a radiative element comprising a planar layer with multiple sectors is disclosed. The sectors are configured to be interactive or non-interactive. The interactive sectors contribute to the radiative profile of the antenna. The non-interactive sectors are galvanically isolated from the interactive sectors and do not substantially affect the radiative profile of the antenna. Region borders are present between various ones of the interacting and non-interacting sectors. These region borders provide the galvanic isolation between the interacting and non-interacting sectors. The antenna further includes feed portions coupled to the interactive sectors, thereby defining the antenna pattern. The non-interactive sectors are largely transparent to the radiative mode and thus do not substantially affect the antenna pattern. |
| US09634382B2 |
Portable antenna
A portable antenna is disclosed that can be collapsed into, and erected from, a housing. There is also a pull cord mechanism arranged, when pulled, to cause the antenna to revert between the erect or collapsed configurations. The pull cord extends from the antenna to a position in easy reach of the soldier's hand so that the antenna can be erected/collapsed remotely. |
| US09634377B2 |
Electronic device
An electronic device is provided. The electronic device includes a housing, a display, a supporting frame and an antenna. The display is disposed in the housing. The supporting frame supports the display. The antenna includes a radiator and a connection section. The connection section is connected to the radiator, wherein the connection section is coupled to the supporting frame. |
| US09634376B2 |
Wireless communication device
A compact wireless communication includes a first radiating element and a second radiating element, which define and function as a dipole antenna, a feeder circuit including a wireless IC chip coupled with the first and second radiating elements, and a feeder substrate that is provided with the wireless IC chip. The first radiating element is provided to the feeder substrate. The second radiating element is provided to a substrate other than the feeder substrate. |
| US09634366B2 |
High-frequency module
A high-frequency module includes port electrodes defining external connection terminals provided on a multilayer body including dielectric layers. A first port electrode is connected to an antenna. A plurality of port electrodes other than the first port electrode are respectively connected to communication systems supporting respective frequency bands. The first port electrode is connected to the plurality of other port electrodes through a plurality of switch elements. A first group of the plurality of switch elements and a second group of the plurality of switch elements are not connected to each other within a switch circuit and are connectable to each other through a common terminal outside of the switch circuit. As a result, a high-frequency module that allows a design change to be made using the same switch circuit without changing the switch circuit is provided. |
| US09634364B2 |
Support structure for traction battery assembly with integrated thermal plate
A vehicle including a pair of spaced apart battery cell arrays, a pair of sub-structures configured to retain the arrays, and a thermal plate assembly disposed between the arrays is provided. Each of the sub-structures may include opposing endplates and opposing upper and lower sidewalls secured to the endplates and each having a flange extending toward and overlapping with the respective flange of the other sub-structure to join the sub-structures without mechanical fastening. The thermal plate assembly may be disposed between the overlapping flanges and the arrays to form a sandwich formation. The thermal plate assembly may include at least one thermal interface component disposed on a side of a thermal plate, and in contact with a portion of at least one of the battery cell arrays. |
| US09634362B2 |
Safety device for a vehicle and method for controlling the same
A safety device for a vehicle having a battery system with a plurality of battery cells, a method for controlling the safety device, and a system that includes the safety device and the battery system. The safety device includes an electronic unit; a first device configured to detect an insulation resistance between components of the battery system and a reference potential, which components are connected in an electrically conductive manner to at least one battery cell; a second device configured to supply and/or discharge heat to and/or from the battery cells via a heat transfer medium which circulates in at least one circular flow pattern; and at least a first cut-off valve configured to interrupt the circular flow path of the heat transfer medium and which is actuated by the electronic unit from an open position into a closed position when the detected insulation resistance is below a predetermined limit value. |
| US09634356B2 |
Electrolyte for secondary battery and lithium secondary battery including the same
Disclosed are an electrolyte for a lithium secondary battery which includes a non-aqueous solvent and a lithium salt, wherein the non-aqueous solvent includes an anion receptor, a cyclic carbonate, and a linear solvent, wherein an amount of the cyclic carbonate is in a range of 1 wt % to 30 wt % based on a total weight of the non-aqueous solvent, and a lithium secondary battery including the same. |
| US09634354B2 |
Solid state catholytes and electrolytes for energy storage devices
The present invention provides an energy storage device comprising a cathode region or other element. The device has a major active region comprising a plurality of first active regions spatially disposed within the cathode region. The major active region expands or contracts from a first volume to a second volume during a period of a charge and discharge. The device has a catholyte material spatially confined within a spatial region of the cathode region and spatially disposed within spatial regions not occupied by the first active regions. The device has a protective material formed overlying exposed regions of the cathode material to substantially maintain the sulfur species within the catholyte material. Also included is a novel dopant configuration of the LiaMPbSc (LMPS) [M=Si, Ge, and/or Sn] containing material. |
| US09634353B2 |
Low internal resistance beta—and beta″—alumina electrolyte produced via vapor phase method
A process for making a solid electrolyte for an electrochemical cell. The process includes providing a multilayer material having a porous layer and a nonporous layer, the nonporous layer containing a first oxide selected from alpha-alumina, gamma-alumina, alpha-gallium oxide, and/or combinations thereof. In addition, an alkali-metal oxide vapor is provided and the nonporous layer is exposed to the alkali-metal oxide vapor at an elevated temperature such that the nonporous layer is converted to a solid second oxide electrolyte layer that is conductive to alkali metal ions. The second oxide is an alkali-metal-beta-alumina, alkali-metal-beta″-alumina, alkali-metal-beta-gallate, and/or alkali-metal-beta″-gallate. |
| US09634351B2 |
Mechanical structures for maintaining structural integrity in cylindrical pouch cell batteries
The disclosed embodiments relate to the design and manufacture of a battery cell. The battery cell includes a jelly roll containing layers which are wound together, including a cathode with an active coating, a separator, and an anode with an active coating. The battery cell also includes a mechanical structure disposed around a perimeter of the jelly roll to maintain a structural integrity of the jelly roll. Finally, the battery cell includes a pouch enclosing the mechanical structure and the jelly roll, wherein the pouch is flexible. |
| US09634345B2 |
Convective flow field for fuel cell stack
The reactant distribution in a gas diffusion layer adjacent the landings of a solid polymer electrolyte fuel cell can be improved by using a flow field plate in which suitable sequential protrusions have been incorporated in the channels. The reactant flow field in the plate comprises a plurality of parallel channels in which protrusions are arranged in a sequence along each channel's length and the sequential protrusions in any given channel are offset with respect to the sequential protrusions in the channels immediately adjacent thereto. |
| US09634344B2 |
Hydrogen purifier, hydrogen generation apparatus, and fuel cell system
A hydrogen purifier includes: a CO remover configured to reduce carbon monoxide in a hydrogen-containing gas through an oxidation reaction, the hydrogen-containing gas containing ammonia and carbon monoxide; and an ammonia remover provided upstream from the CO remover, the ammonia remover being configured to cause a reaction between ammonia in the hydrogen-containing gas and oxygen by using a catalyst to decompose the ammonia. |
| US09634341B2 |
Apparatus and method for diagnosing fuel cell
An apparatus and method for diagnosing a fuel cell diagnoses a state of a fuel cell by estimating a fuel-cell equivalent circuit. The apparatus for diagnosing a fuel cell includes: an impedance measurement unit configured to measure impedance of a fuel cell within a predetermined frequency range; an equivalent circuit model unit configured to derive each parameter value by estimating a predetermined fuel-cell equivalent circuit model in response to the impedance received from the impedance measurement unit; and a fuel-cell-state diagnosis unit configured to diagnose a state of the fuel cell by detecting a variation of the parameter value derived from the equivalent circuit model unit. |
| US09634340B2 |
Plate-style water vapor transfer unit with integral headers
A water vapor transfer unit having fluid flow conduits which distribute wet or dry fluid throughout the water vapor transfer unit, which are created by forming apertures in each wet and dry plate so that when the plates are stacked, fluid flow inlet and outlet headers are integrated into the flow stack. These integrated headers negate the need for traditional wet and dry fluid inlet and outlet manifolds external to the water vapor transfer unit stack. Because the plates are stacked and sealed so that the fluid flows cannot co-mingle, the fluids are introduced directly into the stack, flow across the flow fields, and exit the stack without leakage or flow contamination. The integrated header design allows for sealing the stack on no more than a single plane defined by the stack or on no more than two parallel opposing planes and allows for accommodation of stack expansion and contraction. |
| US09634339B2 |
Redox flow battery and method of operating the same
A redox flow battery includes: a positive electrolyte storage tank; a negative electrolyte storage tank; a cell stack; a positive electrolyte outward path that sends positive electrolyte to positive electrode chambers in the cell stack; a positive electrolyte return path that sends positive electrolyte to the positive electrolyte storage tank; a negative electrolyte outward path that sends negative electrolyte to negative electrode chambers of the cells; a negative electrolyte return path that sends negative electrolyte to the negative electrolyte storage tank; an entrance open circuit voltage measuring portion that measures an upstream open circuit voltage between the positive electrolyte inside the positive electrolyte outward path and the negative electrolyte inside the negative electrolyte outward path; and an exit open circuit voltage measuring portion that measures a downstream open circuit voltage between the positive electrolyte inside the positive electrolyte return path and the negative electrolyte inside the negative electrolyte return path. |
| US09634338B2 |
Humidification cell
A humidification cell of a fuel cell apparatus includes a first outer plate and a second outer plate. A gas chamber, a humidification chamber and a water-permeable membrane separating the two chambers, are disposed between the first outer plate and the second outer plate, starting from the first outer plate. A first water-permeable support element that prevents fibers from detaching and also prevents medium flows from blocking narrow gas outlets, is disposed between the first outer plate and the membrane in such a way that the first support element is made of a filter material. |
| US09634337B2 |
Freeze-resistant fuel cell condensers
Cathode exhaust of an evaporatively cooled fuel cell stack (50) is condensed in a heat exchanger (12a, 23, 23a) having extended fins (14, 25a) or tubes (24, 24a) to prevent pooling of condensate, and/or having the entire exit surface of the condenser rendered hydrophilic with wicking (32) to conduct water away. The cathode exhaust flow paths may be vertical or horizontal, they may be partly or totally rendered hydrophilic, and if so, in liquid communication with hydrophilic end surfaces of the condenser, and the condensers (49) may be tilted away from a normal orientation with respect to earth's gravity. |
| US09634336B2 |
Fuel cell stack having end plate with external coolant manifold
A first end plate of a fuel cell stack has a coolant supply manifold and a coolant discharge manifold. The coolant supply manifold includes a pair of manifold sections and a supply coupling section coupling upper portions of the pair of supply manifold sections. The pair of supply manifold sections communicate with a pair of coolant supply passages of the first end plate. A coolant supply pipe is coupled to a lower end of one of the supply manifold sections with an inclination of a predetermined angle from a vertical direction toward a horizontal direction. |
| US09634334B2 |
Laminated thin film battery
Disclosed is a laminated thin film battery which is capable of exhibiting a high capacity and does not require a separate barrier to be formed on a surface after lamination. A first thin film battery and a second thin film battery, in which cathode current collectors and anode current collectors are formed on first surfaces, are laminated in such a type that the respective first surfaces face each other. The cathode current collectors of the first thin film battery and the second thin film battery are electrically connected to a cathode terminal, and the anode current collectors of the first thin film battery and the second thin film battery are electrically connected to an anode terminal. |
| US09634331B2 |
Non-PGM cathode catalysts for fuel cell application derived from heat treated heteroatomic amines precursors
A method of preparing M-N—C catalysts utilizing a sacrificial support approach and inexpensive and readily available polymer precursors as the source of nitrogen and carbon is disclosed. Exemplary polymer precursors include non-porphyrin precursors with no initial catalytic activity. Examples of suitable non-catalytic non-porphyrin precursors include, but are not necessarily limited to low molecular weight precursors that form complexes with iron such as 4-aminoantipirine, phenylenediamine, hydroxysuccinimide, ethanolamine, and the like. |
| US09634327B2 |
Negative electrode active material for lithium ion secondary battery, method for producing the same, negative electrode, and battery
In the case where a silicon substance having a high theoretical capacity as a negative electrode active material for a lithium ion secondary battery is used as a negative electrode active material, such a negative electrode active material is provided that has a high initial battery capacity and suffers less deterioration in performance even when many cycles of charge and discharge are repeated. A lithium ion secondary battery using the negative electrode active material is provided. Silicon and copper (II) oxide, or silicon, metallic copper and water are pulverized and simultaneously mixed in a pulverization device, thereby providing a negative electrode active material that has good cycle characteristics and a large battery capacity. |
| US09634326B2 |
Antimony based anode material for rechargeable batteries and preparation method
An antimony based anode material for a rechargeable battery comprises nanoparticles of composition SbMxOy where M is a further element selected from the group consisting of Sn, Ni, Cu, In, Al, Ge, Pb, Bi, Fe, Co, Ga, with 0≦x<2 and 0≦y≦2.5+2x. The nanoparticles form a substantially monodisperse ensemble with an average size not exceeding a value of 30 nm and by a size deviation not exceeding 15%. A method for preparing the antimony based anode material is carried out in situ in a non-aqueous solvent and starts by reacting an antimony salt and an organometallic amide reactant and oleylamine. |
| US09634324B2 |
Nickel-metal hydride battery and method for producing hydrogen storage alloy
It is an object of the present invention to improve the cycle performance in a nickel-metal hydride battery using a rare earth-Mg—Ni type alloy. The present invention provides a nickel-metal hydride battery having a negative electrode including an La—Mg—Ni based hydrogen absorbing alloy, wherein the hydrogen absorbing alloy has a crystal phase having Gd2Co7 type crystal structure and contains calcium. |
| US09634322B2 |
Active material for rechargeable battery, rechargeable battery, and electronic apparatus
A rechargeable battery including: a positive electrode; a negative electrode including active material; and an electrolytic solution, in which the active material is capable of occluding and releasing lithium ions and includes Si and O as constituent elements, and an atomic ratio (Si/(Si+O)) of Si with respect to Si and O is 30 atomic % to 75 atomic % in a surface of the active material. |
| US09634317B2 |
Reactive separator for a metal-ion battery
A reactive separator is provided for a metal-ion battery. The reactive separator is made up of a reactive layer that is chemically reactive to alkali or alkaline earth metals, and has a first side and a second side. A first non-reactive layer, chemically non-reactive with alkali or alkaline earth metals, is adjacent to the reactive layer first side. A second non-reactive layer, also chemically non-reactive with alkali or alkaline earth metals, is adjacent to the reactive layer second side. More explicitly, the first and second non-reactive layers are defined as having less than 5 percent by weight (wt %) of materials able to participate in electrochemical reactions with alkali or alkaline earth metals. The reactive layer may be formed as a porous membrane embedded with reactive components, where the porous membrane is carbon or a porous polymer. Alternatively, the reactive layer is formed as a polymer gel embedded with reactive components. |
| US09634315B2 |
Carbon containing binderless electrode formation
An anode or negative electrode having a material matrix of carbon, graphene and an active element such as silicon or tin is described. The electrode is fabricated from an electrode slurry that does not utilize an organic binder. The electrode slurry comprises a combination of silicon and graphene oxide suspensions that is applied to a surface of a substrate such as a current collector. The layer of electrode slurry is heat treated to ensure adhesion of the layer of active electrode material to the surface of the current collector. The electrode may be incorporated within a lithium ion electrochemical cell. |
| US09634314B2 |
Battery pack and method of monitoring removal of secondary battery in battery pack
A battery pack and a simple construction is provided. The battery pack includes a plurality of secondary batteries, a housing storing the plurality of secondary batteries, and an inspection circuit stored in the housing. The housing includes a main body section and a closing member to close an opening for taking the plurality of secondary batteries in and out of the main body section, and includes a plurality of fixing members for fixing the closing member on the main body section, the plurality of fixing members being made of a conductive material. An attachment state of the fixing members with respect to the closing member and the main body section is monitored by the inspection circuit, and an attachment order of the fixing members with respect to the closing member and the main body section is memorized by the inspection circuit. |
| US09634311B2 |
Separator including coating layer and battery including the same
A separator includes a coating layer, the coating layer containing a polyvinylidene fluoride homopolymer, a polyvinylidene fluoride-hexafluoropropylene copolymer, a solvent, and inorganic particles, the solvent being present in an amount of about 100 ppm or less in the coating layer. |
| US09634308B2 |
Single layer structure of micron fibers applied in separator for battery
A single layer structure of micron or nano fibers, and a multi-layer structure of micron and nano fibers. The single layer structure of micron fibers includes a web of micron fibers and an impregnating resin, and has a pore size of 1 nm-500 nm. The web of micron fibers is formed by plural interweaved micron fibers (D≧1 μm). The single layer structure of nano fibers includes a web of nano fibers formed by plural interweaved nano fibers (D<1 μm). The multi-layer structure of micron and nano fibers includes a web of interweaved micron fibers, a web of nano fibers formed by plural nano fibers interweaved on the web of micron fibers, a mixture layer formed by parts of the interweaved nano and micron fibers, and a resin at least impregnating the mixture layer and parts of the micron fibers of the web of micron fibers. |
| US09634307B2 |
Battery pack
Provided is a battery pack that is unlikely to be affected by vibration, shock, or the like, and has stable characteristics.A battery pack includes a battery module 300 that is made by stacking battery holding bodies 200 on which film-covered batteries are placed with positive- and negative-electrode pull-out tabs being taken out from the same side in such a way that sides from which the positive- and negative-electrode pull-out tabs are pulled out are aligned with each other, wherein: an extension tab connected each of the tabs is pulled out from a battery holding body in such a way as to extend in a direction perpendicular to a direction of the pull-out tab and in a direction opposite to the other pull-out tab; and the extension tabs are each bent along a side surface in a direction perpendicular to a battery stacking surface, and are stacked up and electrically connected. |
| US09634304B2 |
Battery pack
A battery pack includes a battery cell, a circuit board, and a holder. The battery cell includes a battery device covered with a laminate film. The circuit board is connected to the battery cell. The holder includes a cell holder that covers the battery cell and a circuit board holder that covers the circuit board. In battery pack, the circuit board holder covering the circuit board is arranged in a space formed above a terrace portion of the battery cell covered with the cell holder. |
| US09634288B2 |
Organic light emitting display device
An organic light emitting display device includes a substrate, a light emitting structure, and a reflective metal layer. The substrate includes a pixel region and a peripheral region. The light emitting structure is disposed on the substrate. The reflective metal layer is disposed between the substrate and the light emitting structure. The reflective metal layer includes a plurality of nanowires and a plurality of openings that is defined by the nanowires. |
| US09634287B1 |
Display structure of display device with block members having different haights
A display device and a method of manufacturing the display device are disclosed. In one aspect, the display device includes a substrate including a display region and a peripheral region. A first block member is in the peripheral region and surrounding display structures, the first block member having a first height. A second block member is spaced apart from the first block member in a first direction extending from the display region to the peripheral region, the second block member surrounding the first block member, the second block member having a second height that is greater than the first height. A first encapsulation layer is over the display structures, the first block member, and the second block member. A second encapsulation layer is over the first encapsulation layer, the second encapsulation layer overlapping at least a portion of the first block member in the depth dimension of the display device. |
| US09634282B2 |
OLED package structure and OLED packaging method
The present invention provides an OLED package structure and an OLED packaging method. The OLED package structure includes a substrate (1), a package lid (2) arranged opposite to the substrate (1), an OLED device (11) arranged between the substrate (1) and the package lid (2) and mounted to the substrate (1), and enclosure rein (3) located between the substrate (1) and the package lid (2) and bonding the substrate (1) and the package lid (2) together. The package lid (2) includes a recess (21) formed therein at a location corresponding to the OLED device (11). The recess (21) includes therein a plurality of corrugation projection structures (212) arranged therein and extending outwards from a bottom of the recess (21). Desiccant (211) is attached to the bottom of the recess (21) in an area between two adjacent ones of the corrugation projection structures (212). |
| US09634281B2 |
Organic light-emitting display apparatus and method of manufacturing the same
Disclosed is an organic light-emitting display apparatus. The organic light-emitting display apparatus includes a substrate, a first reflective electrode that is disposed over the substrate, an organic layer that is disposed over the first reflective electrode, and includes a light emission layer, and a second reflective electrode that is disposed over the organic layer. At least one of the first and second reflective electrodes comprises a low refractive layer having a refractive index of about 1.4 or less which is smaller than that of the organic layer. |
| US09634278B2 |
OLED pixel structure
The present invention provides an OLED pixel structure, comprising: red, green and blue sub pixels, and the red sub pixel comprises a red light emitting layer, and the green sub pixel comprises a green light emitting layer, and the blue sub pixel comprises a blue light emitting layer, and material of the blue light emitting layer comprises inorganic quantum dots, and the blue light emitting layer emits white light, and a blue light filter is located corresponding to the blue sub pixel. By the blue sub pixel utilizing inorganic quantum dots+blue light filter, the stability and the life time of the OLED elements have been obviously promoted. The present invention further adds a white sub pixel, and the white sub pixel comprises a white light emitting layer, and material of the white light emitting layer comprises inorganic quantum dots. With the added white sub pixel, the luminous efficiency of the OLED is raised and the energy consumption thereof is reduced. |
| US09634275B2 |
Organic electroluminescent element, display device and illuminating device
Disclosed is an organic electroluminescent element having high luminous efficiency and long life. Also disclosed are a display device and an illuminating device respectively using such an organic electroluminescent element. Specifically disclosed is an organic electroluminescent element comprising an electrode and at least one or more organic layers on a substrate. This organic electroluminescent element is characterized in that at least one of the organic layers is a light-emitting layer containing a phosphorescent compound and a host compound, the phosphorescent compound has a HOMO of −5.15 to −3.50 eV and a LUMO of from −1.25 to +1.00 eV, and the host compound has a 0-0 band of the phosphorescence spectrum at not more than 460 nm and a glass transition temperature of not less than 60° C. |
| US09634269B2 |
Conductive flexible substrate and manufacture thereof, and OLED display device and manufacture method thereof
The present invention provides a conductive flexible substrate and a manufacture method thereof and an OLED display device and a manufacture method thereof. The conductive flexible substrate comprises a flexible substrate (1), mesh conductive lines (2) located on the flexible substrate (1) and embossing from a surface of one side of the flexible substrate (1), and a conductive layer (3) filling among the mesh conductive lines (2); a surface of one side of the flexible substrate (1) away from the mesh conductive lines (2) and the conductive layer (3) is flat. The conductive flexible substrate is capable of promoting the conductivity of the flexible substrate, and applying the conductive flexible substrate to an OLED display device can solve the issue of low conductivity of anodes in the OLED display device. |
| US09634267B2 |
Light-emitting element, light-emitting device, electronic device, and lighting device
A light-emitting element of the present invention can have sufficiently high emission efficiency with a structure including a host material being able to remain chemically stable even if a phosphorescent compound having higher emission energy is used as a guest material. The relation between the relative emission intensity and the emission time of light emission obtained from the host material and the guest material contained in a light-emitting layer is represented by a multicomponent decay curve. The relative emission intensity of the slowest component of the multicomponent decay curve becomes 1/100 for a short time within a range where the slowest component is not interfered with by quenching of the host material (the emission time of the slowest component is preferably less than or equal to 15 μsec); thus, sufficiently high emission efficiency can be obtained. |
| US09634265B2 |
Organic electroluminescent materials and devices
Novel organic compounds comprising ligands with deuterium substitution are provided. In particular, the compound is an iridium complex comprising methyl-d3 substituted ligands. The compounds may be used in organic light emitting devices to provide devices having improved color, efficiency and lifetime. |
| US09634263B2 |
Organic compound, light-emitting element, light-emitting device, display device, electronic device, and lighting device
A novel organic compound that forms an exciplex emitting light with high efficiency is provided. An organic compound with a triarylamine skeleton in which the three aryl groups of the triarylamine skeleton are a p-biphenyl group, a fluoren-2-yl group, and a phenyl group to which a dibenzofuranyl group or a dibenzothiophenyl group is bonded. By the use of the organic compound and an organic compound with an electron-transport property, an exciplex that emits light with extremely high efficiency can be formed. |
| US09634260B2 |
Method for preparing conjugated compound having phenoxathiin and electron donating group of conjugated aromatic unit, and OLED device having the conjugated compound
The disclosure provides a conjugated compound having phenoxathiinl, method for preparing the same and OLED. The conjugated compound has one of the following formulas: Different kinds of electron-rich conjugated aromatic units are reacted with intermediate having phenoxathiinl by Suzuki coupling, Buchwald-Hartwig coupling, or Cu-catalyzed amination of halogenated aromatic hydrocarbons for forming the conjugated compound having phenoxathiin. The prepared novel compound is fluorescent, so that it can be used as the material of light emitting layer of OLED devices. |
| US09634253B2 |
Donor-acceptor conjugated polymer and organic electronic device comprising the same
Disclosed herein are a donor-acceptor conjugated polymer and an organic electronic device including the same. According to embodiments of the invention, it is possible to realize a conjugated polymer suitable for organic memory devices and a multi-functional, high-performance, large-area organic memory device for electronics including the same, the organic memory device operating in air. |
| US09634251B2 |
Nanotube solution treated with molecular additive, nanotube film having enhanced adhesion property, and methods for forming the nanotube solution and the nanotube film
The present disclosure provides a nanotube solution being treated with a molecular additive, a nanotube film having enhanced adhesion property due to the treatment of the molecular additive, and methods for forming the nanotube solution and the nanotube film. The nanotube solution includes a liquid medium, nanotubes in the liquid medium, and a molecular additive in the liquid medium, wherein the molecular additive includes molecules that provide source elements for forming a group IV oxide within the nanotube solution. The molecular additive can introduce silicon (Si) and/or germanium (Ge) in the liquid medium, such that nominal silicon and/or germanium concentrations of the nanotube solution ranges from about 5 ppm to about 60 ppm. |
| US09634250B2 |
Resistive RAM devices and methods
The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element. |
| US09634242B2 |
Data reader with front shield coupling structure
A data reader may consist of at least a magnetoresistive stack positioned on an air bearing surface. A portion of the magnetoresistive stack may be set to a first fixed magnetization by a pinning structure separated from the air bearing surface by a front shield that is set to a second fixed magnetization by a biasing structure. The front shield may be separated from the biasing structure by a coupling structure. |
| US09634235B2 |
Method for manufacturing liquid ejecting head
A method for manufacturing a liquid ejecting head including a laminate formed of a flow path substrate having a flow path communicating with nozzle openings that eject a liquid, a first electrode, a piezoelectric layer, and a second electrode, the method including stacking the first electrode, the piezoelectric material, the second electrode, and a reinforcing member on top of one another to form a laminate; heating the laminate to form a piezoelectric layer made of the piezoelectric material; bonding the laminate to the flow path substrate on a first electrode side; and removing the reinforcing member. |
| US09634234B2 |
Downhole energy harvesting method and device
A device generates electrical energy from mechanical motion in a downhole environment. The device includes a magnetostrictive element and an electrically conductive coil. The magnetostrictive element has a first end and a second end. The first and second ends are coupled between a rotor and a bearing. The magnetostrictive element is configured to experience axial strain in response to radial movement of at least one of the rotor or the bearing with reference to the other. The electrically conductive coil is disposed in proximity to the magnetostrictive element. The coil is configured to generate an electrical current in response to a change in flux density of the magnetostrictive element. |
| US09634223B2 |
Superconductor, superconducting wire, and method of forming the superconductor
A super conductor is formed by a process including a first step of forming liquid-phase rare earth-copper-barium oxide by heat treating a superconductor precursor including a rare earth element, barium, and copper, a second step of forming a first superconductor of the rare earth-copper-barium oxide that is epitaxially grown from the liquid-phase rare earth-copper-barium oxide, and a third step of forming a second superconductor of the rare earth-copper-barium oxide by heat treating the first superconductor, wherein the heat treatment of the third step is performed in an atmosphere in which the rare earth-copper-barium oxide has no liquid phase. |
| US09634217B2 |
Thermally controllable energy generation system
A thermally controllable energy generation system comprising an insulated, thermally-enhanced generator with a power circuit for conveying power. The thermally enhanced generator and its available voltage is controlled by a circuit which changes the ambient temperature of the generator through the use of a heating element and heating circuit. A controller circuit is in communication with the temperature sensor, the control circuit, the heating circuit and the power circuit. The thermally enhanced generator includes at least one cell, which comprises a layer of electron-rich donor material in contact with a layer of hole-rich acceptor material, sandwiched between an anode and a cathode. One of the layers is a stabilized mixture of carbon and an ionic material (carbon matrix) and the other layer is a stabilized oxide mixed with an ionic material (oxide matrix). |
| US09634215B2 |
Light emitting device package and light unit
Embodiments provide a light emitting device package including a package body having a through-hole; a radiator disposed in the through-hole and including an alloy layer having Cu; and a light emitting device disposed on the radiator, wherein the alloy layer includes at least one of W or Mo, and wherein the package body includes cavity including a sidewall and a bottom surface, and wherein the through-hole is formed in the bottom surface. |
| US09634212B2 |
Semiconductor light emitting device and method for manufacturing the same
A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface. |
| US09634205B2 |
Light emitting device and image display unit
A light emitting device includes a package having a recess, a lead frame buried in the package so that one end of the lead frame is exposed at a bottom of the recess and another end protrudes to an exterior of the package, a light emitting element arranged on the lead frame exposed at the bottom of the recess, and an encapsulant filled in the recess. The package includes, at the side face where the lead frame protrudes, a first side face formed inwardly relative to a side face of the lead frame, and a second side face formed at a lower portion of the first side face and protruded so as to cover a top face of the lead frame. |
| US09634203B2 |
Light emitting device, surface light source, liquid crystal display device, and method for manufacturing light emitting device
A light emitting device includes: a substrate having a main surface; a phosphor layer provided on the main surface and containing an LED element that emits primary light and a fluorescent particle that absorbs a part of the primary light and emits secondary light; and a transparent resin layer having a refractive index n and covering the phosphor layer. The transparent resin layer has an outer circumferential surface that forms a boundary between the transparent resin layer and the atmosphere. When a minimum circumference that includes the overall phosphor layer and is concentric with the outer circumferential surface has a radius r in a cut surface where at least a part of the outer circumferential surface takes a shape of an arc having a radius R, a relationship of R>r·n is satisfied. With such configuration, the light extraction efficiency is enhanced. |
| US09634200B2 |
Semiconductor light emitting device
A semiconductor light emitting device comprises a supporting substrate that has light reflecting characteristics; a wavelength conversion layer that is disposed on the supporting substrate, and contains semiconductor nanoparticles developing a quantum size effect; an optical semiconductor laminate that is disposed on the wavelength conversion layer and has light emitting characteristics; and a photonic crystal layer that is disposed on the optical semiconductor laminate, and that has first portions having a first refractive index and second portions having a second refractive index different from the first refractive index, the first portions and the second portions being arranged in a two-dimensional cyclic pattern. |
| US09634196B2 |
Nanostructure layer and light emitting diode with the same
A nanostructure layer includes a number of nanostructures, wherein the number of nanostructures are aligned along a number of straight lines, a size of each of the number of nanostructures ranges from about 20 nanometers to about 100 nanometers, a distance between adjacent two nanostructures ranges from about 10 nanometers to about 300 nanometers, and each of the number of nanostructures includes a core and a shell coated on the core. A light emitting diode with the nanostructure layer is also provided. |
| US09634195B2 |
Light-emitting device
A light-emitting device is provided. The light-emitting device comprises: a semiconductor system comprising a light-emitting semiconductor stack; and an electrode comprising a surface next to the semiconductor system and comprising a base material and a contact material different from the base material, wherein the contact material diffuses into the semiconductor system; wherein the contact material has a largest intensity at a first depth position from a SIMS spectrum, and a distance between the first depth position and the surface is not less than 500 nm. |
| US09634194B2 |
Light-emitting diode chip
A light-emitting diode (LED) chip is disclosed. The chip includes a light-emitting diode and an electrode layer on the light-emitting diode. The electrode layer includes a reflective metal layer. The reflective metal layer includes a first composition and a second composition. The first composition includes aluminum or silver, and the second composition includes copper, silicon, tin, platinum, gold, palladium or a combination thereof. The weight percentage of the second composition is greater than 0% and less than 20%. |
| US09634192B2 |
Light emitting device and lighting system
Disclosed are a light emitting device, a method of fabricating the same, a light emitting device package, and a lighting system. The light emitting device may include a substrate, a first conductive semiconductor layer on the substrate, an active layer on the first conductive semiconductor layer, a second conductive semiconductor layer on the active layer, an ohmic layer on the second conductive semiconductor layer, an insulating layer on the ohmic layer, a first branch electrode electrically connected with the first conductive semiconductor layer, a first pad electrode connected with the first branch electrode for electrical connection with the first conductive semiconductor layer, a second pad electrode in contact with the ohmic layer through the insulating layer, a second branch electrode connected with the second pad electrode on the insulating layer, and a second through electrode passing through the insulating layer to connect the second branch electrode with the ohmic layer. |
| US09634191B2 |
Wire bond free wafer level LED
A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device. |
| US09634184B2 |
Optoelectronic semiconductor device
An optoelectronic semiconductor component includes a layer stack based on a nitride compound semiconductor and has an n-type semiconductor region , a p-type semiconductor region and an active layer arranged between the n-type semiconductor region and the p-type semiconductor region. In order to form an electron barrier, the p-type semiconductor region includes a layer sequence having a plurality of p-doped layers composed of AlxInyGa1−x−yN where 0<=x<=1, 0<=y<=1 and x+y<=1. The layer sequence includes a first p-doped layer having an aluminum proportion x1>=0.5 and a thickness of not more than 3 nm, and the first p-doped layer, at a side facing away from the active layer, is succeeded by at least a second p-doped layer having an aluminum proportion x2 |
| US09634183B2 |
Semiconductor material doping
A solution for designing and/or fabricating a structure including a quantum well and an adjacent barrier is provided. A target band discontinuity between the quantum well and the adjacent barrier is selected to coincide with an activation energy of a dopant for the quantum well and/or barrier. For example, a target valence band discontinuity can be selected such that a dopant energy level of a dopant in the adjacent barrier coincides with a valence energy band edge for the quantum well and/or a ground state energy for free carriers in a valence energy band for the quantum well. Additionally, a target doping level for the quantum well and/or adjacent barrier can be selected to facilitate a real space transfer of holes across the barrier. The quantum well and the adjacent barrier can be formed such that the actual band discontinuity and/or actual doping level(s) correspond to the relevant target(s). |
| US09634181B2 |
Method of forming a composite substrate
In a method according to embodiments of the invention, a III-nitride layer is grown on a growth substrate. The III-nitride layer is connected to a host substrate. The growth substrate is removed. The growth substrate is a non-III-nitride material. The growth substrate has an in-plane lattice constant a substrate. The III-nitride layer has a bulk lattice constant a layer. In some embodiments, [(|a substrate−a layer|)/asubstrate]*100% is no more than 1%. |
| US09634170B2 |
Concentrator photovoltaic panel, concentrator photovoltaic, and concentrator photovoltaic system
A concentrator photovoltaic is formed by concentrator photovoltaic panels each having solar cells arranged on the back side of concentrating lenses. A plurality of portions of an image are imaged at the periphery of each of the solar cells in each of the panels. When each of the panels tracks the sun to be swung in the right-left direction and in the up-down direction, an image which can be identified through the concentrating lenses by a person who sees the image from a position in front of the concentrator photovoltaic is different according to an angle at which the panel is swung (direction rotation angle and elevation angle) due to the characteristic of the concentrating lenses. Therefore, the image of a letter or the like which appears with movement of the sun can be changed, and a message or the like according to time thereof can be displayed. |
| US09634166B2 |
Thin film photovoltaic cell with back contacts
Photovoltaic cells, photovoltaic devices, and methods of fabrication are provided. The photovoltaic cells include a transparent substrate to allow light to enter the photovoltaic cell through the substrate, and a light absorption layer associated with the substrate. The light absorption layer has opposite first and second surfaces, with the first surface being closer to the transparent substrate than the second surface. A passivation layer is disposed over the second surface of the light absorption layer, and a plurality of first discrete contacts and a plurality of second discrete contacts are provided within the passivation layer to facilitate electrical coupling to the light absorption layer. A first electrode and a second electrode are disposed over the passivation layer to contact the plurality of first discrete contacts and the plurality of second discrete contacts, respectively. The first and second electrodes include a photon-reflective material. |
| US09634165B2 |
Regeneration method for restoring photovoltaic cell efficiency
An apparatus, system, and method are disclosed for restoring efficiency of a photovoltaic cell. An illumination module illuminates photovoltaic cells so the cells receive a time integrated irradiance equivalent to at least 5 hours of solar illumination. After illumination, an annealing module anneals the photovoltaic cells at a temperature above 90 degrees Celsius for a minimum of 10 minutes. In one embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 20 hours of solar illumination. In another embodiment, the illumination module illuminates the photovoltaic cells for a time integrated irradiance equivalent to at least 16 hours of solar illumination while being heated to at least 50 degrees Celsius. In another embodiment, a solar concentrator irradiates the photovoltaic cells in sunlight for at least 10 hours and increases the irradiance of solar illumination on the cells by a factor of 2 to 5. |
| US09634162B2 |
Method of fabricating A(C)IGS based thin film using Se-Ag2Se core-shell nanoparticles, A(C)IGS based thin film fabricated by the same, and tandem solar cells including the A(C)IGS based thin film
A method of fabricating an Ag—(Cu—)In—Ga—Se (A(C)IGS) based thin film using Se—Ag2Se core-shell nanoparticles, an A(C)IGS based thin film fabricated by the method, and a tandem solar cell having the A(C)IGS thin film are disclosed. More particularly, a method of fabricating a densified Ag—(Cu—)In—Ga—Se (A(C)IGS) based thin film by non-vacuum coating a substrate with a slurry containing Se—Ag2Se core-shell nanoparticles, an A(C)IGS based thin film fabricated by the method, and a tandem solar cell including the A(C)IGS based thin film are disclosed. According to the present invention, an A(C)IGS based thin film including Ag is manufactured by applying Se—Ag2Se core-shell nanoparticles in a process of manufacturing a (C)IGS thin film, thereby providing an A(C)IGS based thin film having a wide band gap. |
| US09634160B2 |
Solar cell and method for manufacturing the same
A method for manufacturing asolar cell includes texturing a front surface of a semiconductor substrate having a first conductive type dopant by using a dry etching method, forming an emitter layer by ion-implanting a second conductive type dopant into the front surface of the semiconductor substrate, forming a back passivation film on a back surface of the semiconductor substrate; and forming a first electrode electrically connected to the emitter layer and a second electrode being in partial contact with the back surface of the semiconductor substrate. |
| US09634159B2 |
Integrated photodetector waveguide structure with alignment tolerance
An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure. |
| US09634158B2 |
Semiconductor device and electronic equipment
The present technology relates to a semiconductor device and electronic equipment in which a semiconductor device that suppresses the occurrence of noise by a leakage of light can be provided.A semiconductor device is configured which includes a light-receiving element 34, an active element for signal processing, and a light shielding structure 40 which is between the light-receiving element 34 and the active element to cover the active element and is formed of wirings 45 and 46. The semiconductor device further includes a first substrate on which the light-receiving element is formed, a second substrate on which the active element is formed, and a wiring layer which has a light shielding structure by the wirings which is formed on the second substrate, and in which the second substrate can be bonded to the first substrate through the wiring layer. |
| US09634157B2 |
Thin-film solar cell module and method for manufacturing the same
A method for manufacturing a thin-film solar cell module includes a rear surface electrode layer deposition step for depositing a rear surface electrode layer on a substrate, an alkali metal adding step for adding an alkali metal to the rear surface electrode layer, a light absorbing layer deposition step for depositing a light absorbing layer on the rear surface electrode layer, a division groove forming step for forming a division groove that divides the light absorbing layer and exposing a front surface of the rear surface electrode layer in the division groove, an alloying step for alloying the rear surface electrode layer and the alkali metal on the front surface of the rear surface electrode layer exposed in the division groove, and a transparent conductive film deposition step for depositing a transparent conductive film on the light absorbing layer and in the division groove. |
| US09634154B1 |
Schottky diode having a well with peripherial cathod regions and center andoe region
In some embodiments, a semiconductor device includes a first well region configured to be an anode of the semiconductor device, a first doped region configured to be a cathode of the semiconductor device, a second doped region configured to be another cathode of the semiconductor device, and a conductive region. The first well region is disposed between the first doped region and the second doped region, and is configured for electrical connection of the conductive region. |
| US09634149B2 |
Semiconductor device and method for manufacturing thereof
A transistor that is formed using an oxide semiconductor film is provided. A transistor that is formed using an oxide semiconductor film with reduced oxygen vacancies is provided. A transistor having excellent electrical characteristics is provided. A semiconductor device includes a first insulating film, a first oxide semiconductor film, a gate insulating film, and a gate electrode. The first insulating film includes a first region and a second region. The first region is a region that transmits less oxygen than the second region does. The first oxide semiconductor film is provided at least over the second region. |
| US09634144B2 |
Semiconductor devices and methods of fabricating the same
Semiconductor devices and methods of fabricating the semiconductor devices are provided. The semiconductor devices may include a fin disposed on a substrate. The fin may include an insulating layer pattern disposed in a top surface of the fin. The semiconductor devices may also include a wire pattern disposed on the insulating layer pattern to be separated from the insulating layer pattern and a gate electrode surrounding the wire pattern. |
| US09634137B2 |
Integrated power transistor circuit having a current-measuring cell
An integrated power transistor circuit includes a contact structure with a first section and a second section. The first section contacts doped regions of transistor cells in a cell array. The second section includes one or more first subsections which adjoin the first section and extend beyond the cell array in the region of selected transistor cells. A second subsection adjoins the one or more first subsections and forms a tapping line, for example for making contact with source regions of power transistor cells. In the region of the cell array, an electrode structure rests on the contact structure. This electrode structure is absent over the second section. The tapping line can thus be formed at a short distance from the electrode structure, with the result that the active chip area is only insubstantially reduced by the tapping line. |
| US09634130B2 |
Semiconductor device
A semiconductor device includes stripe-shaped gate trench formed in one major surface of n-type drift layer, gate trench including gate polysilicon formed therein, and gate polysilicon being connected to a gate electrode; p-type base layer formed selectively in mesa region between adjacent gate trenches, p-type base layer including n-type emitter layer and connected to emitter electrode; one or more dummy trenches formed between p-type base layers adjoining to each other in the extending direction of gate trenches; and electrically conductive dummy polysilicon formed on an inner side wall of dummy trench with gate oxide film interposed between dummy polysilicon and dummy trench, dummy polysilicon being spaced apart from gate polysilicon. Dummy polysilicon may be connected to emitter electrode. The structure according to the invention facilitates providing an insulated-gate semiconductor device, the Miller capacitance of which is small, even when the voltage applied between the collector and emitter is low. |
| US09634123B2 |
FinFET device including a dielectrically isolated silicon alloy fin
A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate. |
| US09634120B2 |
Electronic device and method for fabricating the same
Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate. |
| US09634118B2 |
Methods of forming semiconductor devices
Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming first and second dielectric layers in first and second trenches. The method includes forming first and second conductive layers on the first and second dielectric layers, respectively. The method includes forming first and second protective layers on the first and second conductive layers, respectively. The method includes performing an annealing process while the first and second protective layers are on the first and second conductive layers. The method includes removing the first and second protective layers. The method includes removing the first conductive layer, after performing the annealing process. Moreover, the method includes forming first and second gate metals in the first and second trenches, respectively, after removing the first conductive layer. |
| US09634116B2 |
Method to improve reliability of high-K metal gate stacks
A method of fabricating a gate stack for a semiconductor device includes the following steps after removal of a dummy gate: growing a high-k dielectric layer over an area vacated by the dummy gate; depositing a thin metal layer over the high-k dielectric layer; annealing the replacement gate structure in an ambient atmosphere containing hydrogen; and depositing a gap fill layer. |
| US09634105B2 |
Silicon nano-tip thin film for flash memory cells
A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided. |
| US09634104B2 |
FinFET and method of fabricating the same
A method of fabricating a fin field effect transistor (FinFET) includes forming a first fin and a second fin extending upward from a substrate major surface to a first height, forming an insulation layer comprising a top surface extending upward from the substrate major surface to a second height less than the first height, selectively forming a bulbous epitaxial layer covering a portion of each fin, annealing the substrate to convert at least a portion of the bulbous epitaxial layer to silicide and depositing a metal layer at least in the cavity. The first fin and the second fin are adjacent. A portion of the first fin and a portion of the second fin extend beyond the top surface of the insulation layer. The bulbous epitaxial layer defines an hourglass shaped cavity between adjacent fins. |
| US09634100B2 |
Semiconductor devices with integrated hole collectors
Transistor devices which include semiconductor layers with integrated hole collector regions are described. The hole collector regions are configured to collect holes generated in the transistor device during operation and transport them away from the active regions of the device. The hole collector regions can be electrically connected or coupled to the source, the drain, or a field plate of the device. The hole collector regions can be doped, for example p-type or nominally p-type, and can be capable of conducting holes but not electrons. |
| US09634099B2 |
Lateral double diffused metal-oxide-semiconductor device and method for fabricating the same
A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact. |
| US09634098B2 |
Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method
A method for controlling oxygen precipitation in a single crystal silicon wafer having a wafer resistivity of less than about 10 milliohm-cm is provided so that the wafer has uniformly high oxygen precipitation behavior from the central axis to the circumferential edge. The single crystal silicon wafer comprises an additional dopant selected from among carbon, arsenic, and antimony. |
| US09634092B2 |
Semiconductor devices having tapered active regions
Provided is a finFET device. The finFET device may include an active region which protrudes vertically from a substrate, a channel region disposed on a center of the active region, a drain region disposed on one side surface of the channel region, and a source region disposed on the other side surface of the channel region, a gate insulating layer formed on two opposing side surfaces of the channel region and having a U-shaped cross-section, gate spacers formed on outer surfaces of the gate insulating layer, drain spacers formed on two opposing side surfaces of the drain region, and source spacers formed on two opposing side surfaces of the source region, and at least one of the two side surfaces of the drain region has a tapered part. |
| US09634088B1 |
Junction formation with reduced CEFF for 22NM FDSOI devices
A method of forming a semiconductor device is disclosed including providing a silicon-on-insulator substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, and forming a transistor device on the silicon-on-insulator substrate including providing a gate structure on the semiconductor layer having a gate electrode and a first cap layer on the gate electrode, growing an oxide liner on the transistor device having a first part covering the gate structure and a second part covering the semiconductor layer, forming a second cap layer on the oxide liner, at least partially removing the second part of the oxide liner underneath the second cap layer and the first part of the oxide liner, and epitaxially forming raised source/drain regions on the semiconductor layer. |
| US09634087B1 |
FinFET and fabrication method thereof
A method is provided for fabricating a FinFET. The method includes providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer may corresponds to a position of subsequently formed fin; forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through ion implantation process; forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in the doping region diffuse into the semiconductor substrate under the hard mask layer; and forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein the semiconductor substrates between the adjacent trenches constitutes a fin. |
| US09634085B1 |
Semiconductor device including a LDMOS transistor
In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm·cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor. |
| US09634083B2 |
Semiconductor structure and process thereof
A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures. |
| US09634080B2 |
Display device
A display device includes contact holes opened in an insulating film outside of a display area in which pixels are arranged, and having a conductive film exposed in bottom portions, a first metal film formed to cover the contact holes and come in contact with the conductive film of the bottom portions, and a transparent conductive film formed on the first metal film. |
| US09634077B2 |
Organic light emitting display devices and methods of manufacturing organic light emitting display devices
An organic light emitting display device may include a substrate having a pixel region and a transparent region, a first capacitor disposed in the transparent region of the substrate, a semiconductor device disposed in the pixel region of the substrate, a second capacitor disposed on the semiconductor device, and an organic light emitting structure disposed on the second capacitor. The organic light emitting display device may have a sufficient capacitance for components including the semiconductor device and the organic light emitting structure without increasing an area of the pixel region while maintaining a transmittance of the organic light emitting display device. |
| US09634075B2 |
Organic light emitting display device
An organic light emitting display device including: a first emission area including a first organic light emitting diode; a second emission area arranged adjacent to the first emission area and not overlapping with the first emission area, the second emission area including a second organic light emitting diode; a pixel circuit unit electrically connected to the first organic light emitting diode and the second organic light emitting diode; and a transmissive area adjacent to the first and second emission areas and not overlapping with the first and second emission areas, the transmissive area configured to transmit external light therethrough. |
| US09634073B2 |
Organic light-emitting display device and method of manufacturing the same
An organic light-emitting display device includes a substrate. A buffer layer is formed on the substrate. A thin film transistor is disposed on the buffer layer. The thin film transistor includes an active layer, a gate electrode, a source electrode, a drain electrode, a first insulating layer, and a second insulating layer. An uneven pattern is formed by patterning the buffer layer. A first pixel electrode is disposed in an opening formed in the second insulating layer. The first pixel electrode includes a transparent conductive oxide. A second pixel electrode is disposed on the first pixel electrode. The second pixel electrode includes a semi-transmissive layer. An organic lighting-emitting layer is formed on the second pixel electrode. An opposite electrode is formed on the organic lighting-emitting layer. |
| US09634072B2 |
Organic light-emitting display device and method of manufacturing the same
An organic light-emitting display device includes: a substrate; an active layer on the substrate; a gate electrode insulated from the active layer and overlapping with the active layer; a source electrode including a first source electrode layer, connected to the active layer, and a second source electrode layer connected to the first source electrode layer, the second source electrode layer being larger than the first source electrode layer; a drain electrode including a first drain electrode layer connected to the active layer, and a second drain electrode layer connected to the first drain electrode layer, the second drain electrode layer being larger than the first drain electrode layer; a first electrode directly connected to a top surface of the source electrode or the drain electrode; an intermediate layer on the first electrode and including an organic emission layer; and a second electrode on the intermediate layer. |
| US09634071B2 |
Thin film transistor, and thin film transistor array panel and organic light emitting diode display including the same
A thin film transistor includes a semiconductor which is disposed on a substrate and includes a source region, a drain region and a channel region, a gate insulating layer disposed on the semiconductor, a gate electrode disposed on the gate insulating layer, an interlayer insulating layer disposed on the gate electrode, contact holes defined in the interlayer insulating layer, the contact holes respectively exposing the source region and the drain region of the semiconductor, and a source electrode and a drain electrode which are disposed on the interlayer insulating layer and respectively contact the source region and the drain region through the contact holes, where at least one of the contact holes exposing the source region and the drain region obliquely traverses the semiconductor. |
| US09634061B2 |
Light emitting diode
A light emitting diode including a first light emitting cell and a second light emitting cell disposed on a substrate and spaced apart from each other to expose a surface of the substrate, a first transparent layer disposed on and electrically connected to the first light emitting cell, first connection section disposed on a portion of the first light emitting cell, a second connection section disposed on a portion of the second light emitting cell, a first interconnection and a second interconnection electrically connecting the first light emitting cell and the second light emitting cell, and an insulation layer disposed between the first and second interconnections and a side surface of the first light emitting cell. |
| US09634059B2 |
Methods of forming image sensor integrated circuit packages
A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor. |
| US09634058B2 |
Image sensor and computing system having the same
An image sensor includes a light receiving element, an anti-reflection layer, a high refractive pattern, a color filter, and a micro lens. The light receiving element is formed on a semiconductor substrate to generate charges responsive to incident light. The anti-reflection layer is formed on the semiconductor substrate. The high refractive pattern is formed on the anti-reflection layer in correspondence with the light receiving element. The color filter is formed on the anti-reflection layer while covering a top surface and lateral sides of the high refractive pattern. The micro lens is formed on the color filter. The image sensor provides an image having high quality. |
| US09634057B2 |
Digital detector possessing a generator of light enabling optical wiping
A solid-state radiation detector comprising a photosensitive sensor comprises photosensitive elements that are organized in a matrix, and a light generator whose purpose is to optically wipe the photosensitive elements. The light generator comprises: an electroluminescent layer that is distributed over the surface of the sensor; at least one electrode that continuously covers the electroluminescent layer and in which electrons may flow, the light emitted by the electroluminescent layer being capable of passing through the electrode; and additional electrical conductors that are in electrical contact with the electrode, the additional electrical conductors forming branches that extend over the surface of the electrode, and being spatially distributed across the surface of the electrode. |
| US09634053B2 |
Image sensor chip sidewall interconnection
An image sensor chip having a sidewall interconnect structure to bond and/or electrically couple the image sensor chip to a package substrate is provided. The image sensor chip includes a substrate supporting an integrated circuit (IC) configured to sense incident light. The sidewall interconnect structure is arranged along a sidewall of the substrate and electrically coupled with the IC. A method for manufacturing the image sensor chip and an image sensor package including the image sensor chip are also provided. |
| US09634052B2 |
Semiconductor device, solid-state image sensor and camera system
The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip. |
| US09634050B2 |
Fabrication of optics wafer
Fabricating an optics wafer includes providing a wafer including a core region composed of a glass-reinforced epoxy. The wafer further includes a first resin layer on a top surface of the core region and a second resin layer on a bottom surface of the core region. The core region and first and second resin layers are substantially non-transparent for a specific range of the electromagnetic spectrum. The wafer further includes vertical transparent regions that extend through the core region and the first and second resin layers and are composed of a solid material that is substantially transparent for the specific range of the electromagnetic spectrum. The wafer is thinned, and optical structures are provided on one or more exposed surfaces of at least some of the transparent regions. |
| US09634049B2 |
Solid-state imaging devices with enhanced angular response
A solid-state imaging device includes a substrate containing a plurality of photoelectric conversion elements arranged into a pixel array. A color filter layer including a plurality of color filter segments is disposed above the photoelectric conversion elements. A partition grid includes a plurality of partitions, and each of the partitions is disposed between two adjacent color filter segments. The color filter layer and the partition grid are disposed in the same layer. In addition, the partitions include a first partition disposed at a center line of the pixel array and a second partition disposed at an edge of the pixel array. The second partition has a top width that is larger than the top width of the first partition. |
| US09634048B2 |
Imaging device and electronic device
An imaging device with excellent imaging performance is provided. The imaging device has a first circuit including a first photoelectric conversion element and a second circuit including a second photoelectric conversion element. The second circuit is shielded from light. In the imaging device, a current mirror circuit in which a transistor connected to the second photoelectric conversion element serves as an input transistor and a transistor connected to the first photoelectric conversion element serves as an output transistor is formed. With such a configuration, the amount of photocurrent in the first circuit from which the contribution of the dark current of the first photoelectric conversion element has been excluded can be detected. |
| US09634045B2 |
Method for forming thin film pattern
The present disclosure provides a method for forming a thin film pattern. The method includes steps of: forming a mask pattern on a thin film in such a manner that the mask pattern includes a reserved portion corresponding to a region where the thin film pattern to be formed is located, and a partially-reserved portion neighboring the reserved portion; performing a wet-etching process to etch off a portion of the thin film which is not covered by the mask pattern; performing a dry etching process to remove the partially-reserved portion and thin the reserved portion; and performing a dry etching process to etch off a portion of the thin film which is not covered by the remaining mask pattern, so as to form the thin film pattern. |
| US09634044B2 |
Method for fabricating array substrate
Embodiments of the invention provides a method for fabricating an array substrate comprising: forming, on a substrate, at least two semiconductor active islands, first patterns positioned on both sides of each of the semiconductor active islands, second patterns positioned at outer side of a part of the first patterns, and third patterns positioned at outer side of the rest of the first patterns, through a single patterning process; doping a semiconductor at the second patterns for once to form a semiconductor of a first conductivity type; and doping a semiconductor at the third patterns for once to form a semiconductor of a second conductivity type. |
| US09634043B2 |
Array substrate, manufacturing method thereof, display device, thin-film transistor (TFT) and manufacturing method thereof
An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate patterning the metal film by one patterning process, and forming patterns of a gate electrode a source electrode, a drain electrode a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion, a pixel electrode and a bridge structure. |
| US09634041B2 |
Display apparatus and method of manufacturing the same
A display apparatus includes a number of pixels. Each pixel includes a substrate including a pixel area and a non-pixel area disposed between adjacent pixel areas, a first electrode disposed on the substrate in the pixel area, and a second electrode extending in a first direction and being spaced apart upward from the substrate by a predetermined distance in the pixel area defining a tunnel-shaped cavity, an image display layer disposed in the tunnel-shaped cavity and driven by an electric field formed between the first electrode and the second electrode, a roof layer disposed on the second electrode, and a sealing layer extending in the first direction, having a black color, and being disposed in the non-pixel area between adjacent pixel areas in a second direction crossing the first direction to seal the tunnel-shaped cavity. |
| US09634030B2 |
Array substrate and manufacturing method thereof
An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a black matrix layer having a plurality of black matrixes on a substrate; forming a switch array layer having a plurality of thin-film transistors on the black matrix layer; forming a color resist layer having a plurality of color resists on the switch array layer; and forming a transparent conductive layer on the color resist layer. |
| US09634026B1 |
Standard cell architecture for reduced leakage current and improved decoupling capacitance
A standard cell IC may include a plurality of pMOS transistors each including a pMOS transistor drain, a pMOS transistor source, and a pMOS transistor gate. Each pMOS transistor drain and pMOS transistor source of the plurality of pMOS transistors may be coupled to a first voltage source. The standard cell IC may also include a plurality of nMOS transistors each including an nMOS transistor drain, an nMOS transistor source, and an nMOS transistor gate. Each nMOS transistor drain and nMOS transistor source of the plurality of nMOS transistors are coupled to a second voltage source lower than the first voltage source. |
| US09634025B2 |
Integrated structures and methods of forming vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, vertically-stacked memory cells within the conductive levels, an insulative material over the stack and a select gate material over the insulative material. An opening extends through the select gate material, through the insulative material, and through the stack of alternating dielectric and conductive levels. A first region of the opening within the insulative material is wider along a cross-section than a second region of the opening within the select gate material, and is wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels. Channel material is within the opening and adjacent the insulative material, the select gate material and the memory cells. Some embodiments include methods of forming vertically-stacked memory cells. |
| US09634024B2 |
Semiconductor device having vertical channel and air gap, and method of manufacturing thereof
A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure. |
| US09634021B2 |
Method of manufacturing semiconductor device
A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a second area; forming a first gate oxide film by oxidizing the silicon layer; removing the first gate oxide film from the second area, while maintaining the first gate oxide film in the first area; thereafter, increasing a thickness of the first gate oxide film in the first area and simultaneously forming a second gate oxide film by oxidizing the silicon layer in the second area; and forming a first gate electrode and a second gate electrode over the first gate oxide film and the second gate oxide film, respectively, wherein after the formation of the first and second gate electrodes, the silicon layer in the first area is thicker than the silicon layer in the second area. |
| US09634016B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes a substrate having a cell region, wherein a contact region, page buffer regions, and a scribe lane region are defined around the cell region; a cell structure located in the cell region, including first conductive layers and first insulating layers which are alternately stacked, and having a non-stepped shape; a contact structure located in the contact region, including second conductive layers and second insulating layers which are alternately stacked, and having a stepped shape; a first dummy structure located in the page buffer region, including first sacrificial layers and third insulating layers which are alternately stacked, and having the non-stepped shape; and a second dummy structure located in the scribe lane region, including second sacrificial layers and fourth insulating layers which are alternately stacked, and having the stepped shape. |
| US09634012B2 |
Method of forming active patterns, active pattern array, and method of manufacturing a semiconductor device
In a method of forming active patterns, first patterns are formed in a first direction on a cell region of a substrate, and a second pattern is formed on a peripheral circuit region of the substrate. The first pattern extends in a third direction crossing the first direction. First masks are formed in the first direction on the first patterns, and a second mask is formed on the second pattern. The first mask extends in a fourth direction crossing the third direction. Third masks are formed between the first masks extending in the fourth direction. The first and second patterns are etched using the first to third masks to form third and fourth patterns. Upper portions of the substrate are etched using the third and fourth patterns to form first and second active patterns in the cell and peripheral circuit regions. |
| US09634007B2 |
Trench confined epitaxially grown device layer(s)
Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer. |
| US09634006B2 |
Third type of metal gate stack for CMOS devices
A third type of metal gate stack is provided above an isolation structure and between a replacement metal gate n-type field effect transistor and a replacement metal gate p-type field effect transistor. The third type of metal gate stack includes at least three different components. Notably, the third type of metal gate stack includes, as a first component, an n-type workfunction metal layer, as a second component, a p-type workfunction metal layer, and as a third component, a low resistance metal layer. In some embodiments, the uppermost surface of the first, second and third components of the third type of metal gate stack are all substantially coplanar with each other. In other embodiments, an uppermost surface of the third component of the third type of metal gate stack is non-substantially coplanar with an uppermost surface of both the first and second components of the third type of metal gate stack. |
| US09634005B2 |
Gate planarity for FinFET using dummy polish stop
A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes a screen layer over tops of the fins. An etch stop feature is formed on the screen layer. The etch stop feature is patterned down to the screen layer in regions across the device. A dummy gate material formed over the fins is planarized down to the etch stop feature, a dielectric fill between gate structures patterned from the dummy gate material is planarized down to the etch stop feature and a gate conductor is planarized to the etch stop feature. |
| US09634002B1 |
Semiconductor device and method of manufacturing the same
A semiconductor device and method of manufacturing the same are provided in the present invention. Multiple spacer layers are used in the invention to form spacers with different predetermined thickness on different active regions or devices, thus the spacing between the strained silicon structure and the gate structure (SiGe-to-Gate) can be properly controlled and adjusted to achieve better and more uniform performance for various devices and circuit layouts. |
| US09633998B2 |
Semiconductor device and method for making the same
A semiconductor device is provided. The semiconductor device includes an avalanche photodiode unit and a thyristor unit. The avalanche photodiode unit is configured to receive incident light to generate a trigger current and comprises a wide band-gap semiconductor. The thyristor unit is configured to be activated by the trigger current to an electrically conductive state. A semiconductor device and a method for making a semiconductor device are also presented. |
| US09633996B1 |
High density area efficient thin-oxide decoupling capacitor using conductive gate resistor
A semiconductor device arranged between a source voltage (Vss) and a power voltage (Vdd) may include a first terminal coupled to the power voltage Vdd. The semiconductor device may also include a decoupling capacitor. The decoupling capacitor may include a semiconductor fin coupled to the first terminal, a dielectric layer on the semiconductor fin, and a gate on the dielectric layer. The semiconductor device may further include a second terminal. The second terminal may include a conductive gate resistor coupled in series with the gate of the decoupling capacitor. The second terminal may be coupled to the source voltage Vss via a first interconnect layer (M1). |
| US09633995B2 |
Method of forming a gate shield in an ED-CMOS transistor and a base of a bipolar transistor using BICMOS technologies
A method of fabricating a MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies. |
| US09633994B2 |
BICMOS device having commonly defined gate shield in an ED-CMOS transistor and base in a bipolar transistor
A MOSFET transistor in a SiGe BICMOS technology and resulting structure having a drain-gate feedback capacitance shield formed between a gate electrode and the drain region. The shield does not overlap the gate and thereby minimizes effect on the input capacitance of the transistor. The process does not require complex or costly processing since the shield is composed of bipolar base material commonly used in SiGe BICMOS technologies. |
| US09633992B1 |
Electrostatic discharge protection device
An ESD protection device is provided. Each of a first and a second well has a first conductive type. Each of a first and a second doping region has a second conductive type and is formed in the first well. A third doping region has the first conductive type. A fourth doping region has the second conductive type. The third and fourth doping regions are formed in the second doping region. Each of a fifth and a sixth doping region has the second conductive type and is formed in the second well. A seventh doping region has the first conductive type. An eighth doping region has the second conductive type. The seventh and eighth doping region are formed in the sixth doping region. A first and a second trigger gate are formed on the first and second wells and partially cover the second and sixth doping regions respectively. |
| US09633991B2 |
Mutual ballasting multi-finger bidirectional ESD device
An integrated circuit includes a bidirectional ESD device which has a plurality of parallel switch legs. Each switch leg includes a first current switch and a second current switch in a back-to-back configuration. A first current supply node of each first current switch is coupled to a first terminal of the ESD device. A second current supply node of each second current switch is coupled to a second terminal of the ESD device. A first current collection node of each first current switch is coupled to a second current collection node of the corresponding second current switch. The first current collection nodes in each first current switch is not coupled to any other first current collection node, and similarly, the second current collection node in each instance second current switch is not coupled to any other second current collection node. |
| US09633990B2 |
Bi-directional ESD protection device
An integrated circuit and method with a bidirectional ESD transistor. A base diffusion separates an emitter diffusion and a collector diffusion. Silicide is blocked from the base diffusion, the emitter-base junction, the collector-base junction, and from equal portions of the emitter diffusion and the collector diffusions. |
| US09633983B2 |
Semiconductor chip stacking assemblies
Embodiments of the invention provide semiconductor chip stacking assemblies that provide direct attachment of a first semiconductor device with a second semiconductor device. An assembly comprises a first semiconductor chip that has a first and a second set of electrical interconnect regions disposed on its surface and a second semiconductor chip. The first set of electrical interconnect regions are electrically connected with the electrical interconnect regions of a second semiconductor chip, and the second set of electrical interconnect regions are electrically interconnected with the substrate. Direct electrical connections are for example, silicon photonics device-to-driver or device-to-signal converters, logic-to-memory, memory-to-memory, and logic-to-logic chip interconnections. |
| US09633982B2 |
Method of manufacturing semiconductor device array
Present disclosure provides a method for manufacturing a semiconductor device array, including (1) providing a temporary substrate; (2) forming a plurality of discrete semiconductor structures over the temporary substrate; and (3) removing a surface portion of the temporary substrate to expose a peripheral bottom surface of the discrete semiconductor structure. Present disclosure also provides a method for transferring discrete semiconductor device, including (1) detaching discrete semiconductor structures of a first type from a first temporary substrate supporting the discrete semiconductor structures of the first type by a transfer stamp; (2) carrying the discrete semiconductor structures over a target substrate by the transfer stamp; and (3) dismounting the discrete semiconductor structures of the first type from the transfer stamp to predetermined sites on the target substrate. The transfer stamp includes a plurality of protrusions, positions of the plurality of protrusions being programmable to match the predetermined sites on the target substrate. |
| US09633980B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first semiconductor chip including a first circuit, a second circuit, a first interconnect connected to the first circuit, a second interconnect connected to the second circuit, and a third interconnect connecting the first interconnect and the second interconnect. |
| US09633979B2 |
Microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
A microelectronic assembly or package can include first and second support elements and a microelectronic element between inwardly facing surfaces of the support elements. First connectors and second connectors such as solder balls, metal posts, stud bumps, or the like face inwardly from the respective support elements and are aligned with and electrically coupled with one another in columns. The first connectors, the second connectors or both may be partially encapsulated prior to electrically coupling respective pairs of first and second connectors in columns. A method may include arranging extremities of first connectors or second connectors in a temporary layer before forming the partial encapsulation. |
| US09633976B1 |
Systems and methods for inter-chip communication
A quilt packaging system includes a first and second electronic device each comprising a plurality of edge surfaces at least a first edge surface of which comprises one or more interconnect modules disposed thereon. The first edge surface of the second electronic device is positioned contiguous to the first edge surface of the first electronic device, and at least one of the one or more interconnect nodules disposed on the first edge surface of the first electronic device is configured to be in physical contact with at least one of the one or more interconnect nodules disposed on the first edge surface of second electronic device so as to provide an electrical connection between the first and second electronic devices at the first edge surfaces of the first and second electronic device. |
| US09633975B2 |
Multi-die wirebond packages with elongated windows
A microelectronic package can include a substrate having first and second opposed surfaces extending in first and second transverse directions and an opening extending between the first and second surfaces and defining first and second distinct parts each elongated along a common axis extending in the first direction, first and second microelectronic elements each having a front surface facing the first surface of the substrate and a column of contacts at the respective front surface, a plurality of terminals exposed at the second surface, and first and second electrical connections aligned with the respective first and second parts of the opening and extending from at least some of the contacts of the respective first and second microelectronic elements to at least some of the terminals. The column of contacts of the first and second microelectronic elements can be aligned with the respective first and second parts of the opening. |
| US09633963B2 |
Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad. A second portion of the contact pad is exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes a hollow region. |
| US09633962B2 |
Plug via formation with grid features in the passivation layer
Solder bump connections and methods for fabricating solder bump connections. A passivation layer is formed on a dielectric layer. Via openings extend through the passivation layer from a top surface of the passivation layer to a metal line in the passivation layer. A conductive layer is formed on the top surface of the passivation layer and within each via opening. When the passivation layer and the conductive layer are planarized, a plug is formed that includes sections in the via openings. Each section is coupled with the metal line. |
| US09633957B2 |
Semiconductor device, a power semiconductor device, and a method for processing a semiconductor device
According to various embodiments, a semiconductor device may include: a layer stack formed at a surface of the semiconductor device, the layer stack including: a metallization layer including a first metal or metal alloy; a protection layer covering the metallization layer, the protection layer including a second metal or metal alloy, wherein the second metal or metal alloy is less noble than the first metal or metal alloy. |
| US09633952B2 |
Substrate structure and method for manufacturing same
Provided is a substrate structure, including: a first substrate and a second substrate arranged correspondingly. A first surface of the first substrate faces a second surface of the second substrate, wherein the first surface is successively arranged with a conductor interconnection layer and a bonding layer, with the bonding layer connecting the first substrate and the conductor interconnection layer to the second substrate. The substrate structure and a method for manufacturing the same. The second substrate can serve as a support substrate and the first substrate as a substrate for directly manufacturing a device. However, the first substrate is formed by the growth of a crystal without the problem of thickness and stress thereof, thereby avoiding unnecessary stress and further improving the performance of the device formed in the first substrate. |
| US09633950B1 |
Integrated device comprising flexible connector between integrated circuit (IC) packages
Some features pertain to an integrated device that includes a first integrated circuit (IC) package, a flexible connector and a second integrated circuit (IC) package. The first integrated circuit (IC) package includes a first die, a plurality of first interconnects, and a first dielectric layer encapsulating the first die. The flexible connector is coupled to the first integrated circuit (IC) package. The flexible connector includes the first dielectric layer, and an interconnect. The second integrated circuit (IC) package is coupled to the flexible connector. The second integrated circuit (IC) package includes the first dielectric layer, and a plurality of second interconnects. The first integrated circuit (IC) package, the second integrated circuit (IC) package, and the flexible connector are coupled together through at least a portion (e.g., contiguous portion) of the first dielectric layer. In some implementations, the flexible connector comprises a dummy metal layer. |
| US09633946B1 |
Seamless metallization contacts
The present disclosure relates to semiconductor structures and, more particularly, to seamless metallization structures and methods of manufacture. A structure includes: a contact opening formed in an oxide material and in alignment with an underlying structure; a metal liner lining the sidewalls and bottom of the contact opening, in direct electrical contact with the underlying structure; a conductive liner on the metal liner, within the contact opening; and tungsten fill material on the conductive liner and within the contact opening. |
| US09633945B1 |
Semiconductor device and method of manufacturing semiconductor device
According to one embodiment, there is provided a semiconductor device, which includes an electrode lead-out part, a planarization film, contacts, and first and second columnar patterns. The electrode lead-out part is arranged such that an electrode film and an insulating film are alternately stacked in a plurality of layers, and layers of the electrode film are arranged stepwise. The planarization film is arranged above the electrode lead-out part. The first columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a first depth. The second columnar pattern extends from a lowermost portion of the electrode lead-out part to a position lower than the upper side of the planarization film by a second depth larger than the first depth. |
| US09633942B1 |
Conductively doped polymer pattern placement error compensation layer
A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer. |
| US09633941B2 |
Semiconductor device structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure over the substrate. The semiconductor device structure includes a first dielectric layer over the substrate. The first dielectric layer has a first opening exposing the first conductive structure. The semiconductor device structure includes a seal layer covering an inner wall of the first opening and in direct contact with the first dielectric layer. The seal layer includes a dielectric material including an oxygen compound. The semiconductor device structure includes a second conductive structure filled in the first opening and surrounded by the seal layer. The second conductive structure is electrically connected to the first conductive structure. |
| US09633937B2 |
Electronic assembly that includes stacked electronic devices
The electronic package includes a substrate and an electronic component mounted to a surface of the substrate. An interposer is mounted to the surface of the substrate such that the interposer surrounds the electronic component and is electrically connected to the substrate. An over-mold covers the electronic component. In other forms, the example electronic package may be incorporated into an electronic assembly. The electronic assembly further includes a second electronic component mounted to the interposer. As an example, the second electronic component may be mounted to the interposer using solder bumps. It should be noted that any technique that is known now, or discovered in the future, may be used to mount the second electronic component to the interposer. |
| US09633935B2 |
Stacked chip package including substrate with recess adjoining side edge of substrate and method for forming the same
A stacked chip package is provided. The stacked chip package includes a first substrate having a first side and a second side opposite thereto. The first substrate includes a recess therein. The recess adjoins a side edge of the first substrate. A plurality of redistribution layers is disposed on the first substrate and extends onto the bottom of the recess. A second substrate is disposed on the first side of the first substrate. A plurality of bonding wires is correspondingly disposed on the redistribution layers in the recess, and extends onto the second substrate. A device substrate is disposed on the second side of the first substrate. A method of forming the stacked chip package is also provided. |
| US09633933B2 |
Lead frame with anchor-shaped lead
A lead frame includes a die pad and a plurality of leads arranged around the die pad. Each of the leads includes an inner lead, a bent portion, and an external connection terminal. The inner lead includes a distal portion, adjacent to the die pad, and a connection end portion, located at an opposite end of the inner lead from the distal portion. The bent portion is connected to the connection end portion of the inner lead. The external connection terminal is connected by the bent portion to the connection end portion of the inner lead and located below the inner lead. The external connection terminal includes an upper surface that faces to and is parallel to a lower surface of the inner lead. The inner lead, the bent portion, and the external connection terminal are formed integrally in each of the leads. |
| US09633931B2 |
Chip rotated at an angle mounted on die pad region
A package includes: a plurality of lead frames configured to extend inwardly from an outer circumferential portion of the package; a die pad region surrounded with the lead frames in a plane view; a semiconductor chip mounted on the die pad region; a plurality of bonding pads disposed on the semiconductor chip; and a plurality of bonding wires configured to connect the lead frames and the bonding pads, respectively, wherein the bonding wires are respectively connected to front end portions of the lead frames by bonding with an angle ranging from 45 to 135 degrees with respect to a trace of front end portions of the lead frames in the plane view. |
| US09633929B2 |
TSV formation
A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material. |
| US09633926B2 |
Semiconductor device and manufacturing method of semiconductor device
A semiconductor device includes a stacked unit having a semiconductor module, a first cooler having a first opening and a first coolant flow path that is connected to the first opening, and a second cooler that has a second opening and a second coolant flow path that is connected to the second opening, and being formed by the first cooler and the second cooler sandwiching the semiconductor module and being stacked such that the first opening and the second opening face each other; a seal member that is arranged between the first opening and the second opening that are adjacent in a stacking direction, and that connect the first opening and the second opening; and a winding member that keeps pressure applied to the stacked unit in the stacking direction by being wound around the stacked unit. |
| US09633923B2 |
Electronic device module and manufacturing method thereof
There are provided an electronic device module capable of increasing a degree of integration by mounting electronic components on both surfaces of a board, and a manufacturing method thereof. The electronic device module includes a board having mounting electrodes formed on both surfaces thereof, a plurality of electronic devices mounted on the mounting electrodes, a molded portion sealing the electronic devices, at least one connection wire having one end bonded to one surface of the board and the other end exposed to the outside of the molded portion, and an external connection terminal coupled to the other end of the connection wire. |
| US09633917B2 |
Three dimensional integrated circuit structure and method of manufacturing the same
Provided is a three dimensional integrated circuit structure including a first die, a through substrate via and a connector. The first die is bonded to a second die with a first dielectric layer of the first die and a second dielectric layer of the second die, wherein a first passivation layer is between the first dielectric layer and a first substrate of the first die, and a first test pad is embedded in the first passivation layer. The through substrate via penetrates through the first die and is electrically connected to the second die. The connector is electrically connected to the first die and the second die through the through substrate via. |
| US09633916B2 |
Display panel and method of manufacturing the same
A display panel includes first to third test lines connected to the each of data lines, extending in the second direction, and arranged in the first direction, a first test pad electrically connected to the first test line, the first test pad and the first test line being formed from a same layer, a second test pad electrically connected to the second test line through a contact hole formed through a first insulation layer, and disposed adjacent to the first test pad in the second direction, a third test pad electrically connected to the third test line and disposed adjacent to the first test pad in the first direction, the third test pad and the third test line being formed from a same layer. |
| US09633911B2 |
Simplified multi-threshold voltage scheme for fully depleted SOI MOSFETs
A method for semiconductor fabrication includes providing channel regions on a substrate including at least one Silicon Germanium (SiGe) channel region, the substrate including a plurality of regions including a first region and a second region. Gate structures are formed for a first n-type field effect transistor (NFET) and a first p-type field effect transistor (PFET) in the first region and a second NFET and a second PFET in the second region, the gate structure for the first PFET being formed on the SiGe channel region. The gate structure for the first NFET includes a gate material having a first work function and the gate structures for the first PFET, second NFET and second PFET include a gate material having a second work function such that multi-threshold voltage devices are provided. |
| US09633908B2 |
Method for forming a semiconductor structure containing high mobility semiconductor channel materials
A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an insulator layer and a germanium-containing layer. Next, hard mask material portions having an opening that exposes a portion of the germanium-containing layer are formed on the substrate. An etch is then performed through the opening to provide an undercut region in the germanium-containing layer. A III-V compound semiconductor material is grown within the undercut region by utilizing an aspect ratio trapping growth process. Next, portions of the III-V compound semiconductor material are removed to provide III-V compound semiconductor material portions located between remaining portions of the germanium-containing layer. |
| US09633904B1 |
Method for manufacturing semiconductor device with epitaxial structure
A method for manufacturing a semiconductor device with epitaxial structure includes following steps: A substrate including a plurality of gate structures formed thereon is provided, and a spacer is respectively formed on sidewalls of each gate structure. Next, a first etching process is performed to form a first recess respectively at two sides of the gate structures and followed by performing an ion implantation to the first recesses. After the ion implantation, a second etching process is performed to widen the first recesses to form widened first recesses and to form a second recess respectively at a bottom of each widened first recess. Then, an epitaxial structure is respectively formed in the widened first recesses and the second recesses. |
| US09633903B2 |
Device manufacturing method of processing cut portions of semiconductor substrate using carbon dioxide particles
A device manufacturing method according to an embodiment includes forming a film on the side of a second surface of a substrate having a first surface and the second surface, cutting the substrate, cutting the film, and injecting particles onto at least one of a first cut portion formed by the cutting of the substrate and a second cut portion formed by the cutting of the film, to process the at least one of the first cut portion or the second cut portion. |
| US09633900B2 |
Method for through silicon via structure
A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via. |
| US09633896B1 |
Methods for formation of low-k aluminum-containing etch stop films
Dielectric AlO, AlOC, AlON and AlOCN films characterized by a dielectric constant (k) of less than about 10 and having a density of at least about 2.5 g/cm3 are deposited on partially fabricated semiconductor devices to serve as etch stop layers and/or diffusion barriers. In one implementation, a substrate containing an exposed dielectric layer (e.g., a ULK dielectric) and an exposed metal layer is contacted with an aluminum-containing compound (such as trimethylaluminum) in an iALD process chamber and the aluminum-containing compound is allowed to adsorb onto the surface of the substrate. This step is performed in an absence of plasma. Next, the unadsorbed aluminum-containing compound is removed from the process chamber, and the substrate is treated with a process gas containing CO2 or N2O, and an inert gas in a plasma to form an AlO, AlOC, or AlON layer. These steps are then repeated. |
| US09633895B2 |
Integrated fan-out structure with guiding trenches in buffer layer
A bottom package includes a molding compound, a buffer layer over and contacting the molding compound, and a through-via penetrating through the molding compound. A device die is molded in the molding compound. A guiding trench extends from a top surface of the buffer layer into the buffer layer, wherein the guiding trench is misaligned with the device die. |
| US09633893B2 |
Method to protect against contact related shorts on UTBB
Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches. |
| US09633887B2 |
Workpiece cutting method
A workpiece cutting method is provided. The workpiece cutting method includes an attaching step of attaching an adhesive tape to the front side or back side of a workpiece, an applying step of applying a liquid resin to the front side or back side of a support member, a pressing step of superimposing the workpiece on the support member in the condition where the liquid resin and the adhesive tape come into contact with each other, and then pressing the workpiece or the support member, a fixing step of curing the liquid resin to thereby fix the workpiece to the support member, and a cutting step of cutting the workpiece fixed to the support member by using a cutting blade. |
| US09633885B2 |
Variable electrode pattern for versatile electrostatic clamp operation
An electrostatic clamp (ESC) has a clamping surface, and first and second pairs of electrodes. Each of the first pair of electrodes are associated with a respective third of the clamping surface, and each of the second pair of electrodes are associated with a respective sixth of the clamping surface. A peripheral region of each of the first and second pairs of electrodes spirals toward the periphery of the clamping surface. A DC mode connects one of each of the first and second pair of electrodes to a positive and the other one of the respective first and second pair of electrodes to a negative of a power supply. An AC mode electrically connects first, second, and third phase terminals of the power supply to one of the first pair of electrodes, the other one of the first pair of electrodes, and both of the second pair of electrodes, respectively. |
| US09633882B2 |
Integrated circuits with alignment marks and methods of producing the same
Methods of producing integrated circuits with interposers and integrated circuits produced from such methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming a base layer overlying a substrate, and forming an alignment mark overlying the base layer. A first layer is formed overlying the base layer and the alignment mark, and the first layer has a first layer thickness. A second layer is formed overlying the first layer, where the second layer has a second layer thickness and where a combined thickness of the first and second layer thicknesses is from about 2 to about 50 micrometers. A second component is formed from the second layer. |
| US09633879B2 |
Storage system in the ceiling space and storage method for goods thereby
A storage system in a ceiling space includes overhead traveling vehicles and a traveling route for the same, a shuttle carriage configured to transport goods to and from processing devices and a traveling route for the same, an OHT port to and from which the overhead traveling vehicles and the shuttle carriage both transport goods, and buffers that are provided in the ceiling space above the processing device and are for the placement of goods by the shuttle carriage. The traveling route for the shuttle carriage enables delivery and reception of goods by the shuttle carriage between the load port of the processing devices, the buffers, and the OHT port. |
| US09633876B2 |
Selective reflectivity process chamber with customized wavelength response and method
A customizable chamber spectral response is described which can be used at least to tailor chamber performance for wafer heating, wafer cooling, temperature measurement, and stray light. In one aspect, a system is described for processing a treatment object having a given emission spectrum at a treatment object temperature which causes the treatment object to produce a treatment object radiated energy. The chamber responds in a first way to the heating arrangement radiated energy and in a second way to the treatment object radiated energy that is incident thereon. The chamber may respond in the first way by reflecting the majority of the heat source radiated energy and in the second way by absorbing the majority of the treatment object radiated energy. Different portions of the chamber may be treated with selectively reflectivity based on design considerations to achieve objectives with respect to a particular chamber performance parameter. |
| US09633875B2 |
Apparatus for improving temperature uniformity of a workpiece
An apparatus for improving the temperature uniformity of a workpiece during processing is disclosed. The apparatus includes a platen having a separately controlled edge heater capable to independently heating the outer edge of the platen. In this way, additional heat may be supplied near the outer edge of the platen, helping to maintain a constant temperature across the entirety of the platen. This edge heater may be disposed on an outer surface of the platen, or may, in certain embodiments, be embedded in the platen. In certain embodiments, the edge heater and the primary heating element are disposed in two different planes, where the edge heater is disposed closer to the top surface of the platen than the primary heating element. |
| US09633874B1 |
Package substrate warpage reshaping apparatus and method
A warpage reshaping apparatus to reshape a warpage profile of a package substrate is disclosed. The warpage reshaping apparatus includes a metal boat, a plurality of planar boards and a plurality of spring-loaded clips. The metal boat includes a plurality of cavities. Package substrates are placed into each of the cavities. Each of the plurality of planar boards is disposed on a respective one of the package substrates. The spring-loaded clips have a first portion coupled to the metal boat and having a second portion biased against a respective one of the planar boards such that each planar board is biased against its respective package substrate. In addition to that, a method to operate the warpage reshaping apparatus is also disclosed and the manner in which the warpage reshaping apparatus changes the warpage profile of the package substrate is also disclosed. |
| US09633871B2 |
Light-emitting device
To provide a highly reliable light-emitting device with less occurrence of cracks in a sealant bonding two facing substrates together. In a light-emitting device, a first substrate including a light-emitting unit, and a second substrate are bonded to each other with glass frit. A wiring in the area overlapping with a sealing material formed by melting and solidifying glass frit may be formed of a conductive material having a linear thermal expansion coefficient close to that of a substrate material. More specifically, the difference in the linear thermal expansion coefficient between the conductive material and the substrate material is 5 ppm/K or less at a temperature of 0° C. to 500° C. |
| US09633870B2 |
System and method for an improved interconnect structure
Presented herein are an interconnect structure and method for forming the same. The interconnect structure comprises a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer comprising a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 μm. |
| US09633869B2 |
Packages with interposers and methods for forming the same
A package structure includes an interposer, a die over and bonded to the interposer, and a Printed Circuit Board (PCB) underlying and bonded to the interposer. The interposer is free from transistors therein (add transistor), and includes a semiconductor substrate, an interconnect structure over the semiconductor substrate, through-vias in the silicon substrate, and redistribution lines on a backside of the silicon substrate. The interconnect structure and the redistribution lines are electrically coupled through the through-vias. |
| US09633866B2 |
Method for patterning of laminated magnetic layer
A microelectronic device is formed by forming a stack of alternating layers of a magnetic material and a dielectric material. An etch mask is formed over the magnetic laminate layer. An aqueous wet etch including 5 percent to 10 percent nitric acid, 0.5 percent to 2 percent sulphuric acid, and 0.5 percent to 3 percent hydrofluoric acid is used to etch the magnetic laminate layer where exposed by the etch mask to form a patterned magnetic laminate layer. An optional adhesion layer, if present, is also removed by the aqueous wet etch solution where exposed by the etch mask. The etch mask is subsequently removed. |
| US09633862B2 |
Semiconductor manufacturing apparatus and semiconductor manufacturing method
A semiconductor manufacturing apparatus according to an embodiment includes a reactor, a mover, and a controller. The reactor houses an outer edge portion of a semiconductor substrate in inside thereof through a gap portion and scrapes the outer edge portion. The mover moves at least either the semiconductor substrate or end faces of the gap portion in a thickness direction of the semiconductor substrate to change distances in the thickness direction between the semiconductor substrate and the end faces of the gap portion. The controller controls a movement amount in the thickness direction of at least either the semiconductor substrate or the end faces of the gap portion according to a warp amount of the outer edge portion in the thickness direction. |
| US09633855B2 |
Planarization process
Planarization processing methods are disclosed. In one aspect, the method includes patterning a material layer and planarizing the patterned material layer by using sputtering. Due to the patterning of the material layer, the loading requirements of nonuniformity on a substrate for sputtering the material layer are reduced, compared with that before the patterning. |
| US09633850B2 |
Masking methods for ALD processes for electrode-based devices
Masking methods for atomic-layer-deposition processes for electrode-based devices are disclosed, wherein solder is used as a masking material. The methods include exposing electrical contact members of an electrical device having an active device region and a barrier layer formed by atomic layer deposition. This includes depositing solder elements on the electrical contact members, then forming the barrier layer using atomic layer deposition, wherein the barrier layer covers the active device region and also covers the solder elements that respectively cover the electrical contact members. The solder elements are then melted, which removes respective portions of the barrier layer covering the solder elements. Similar methods are employed for exposing contacts when forming layered capacitors. |
| US09633846B2 |
Internal plasma grid applications for semiconductor fabrication
The embodiments disclosed herein pertain to improved methods and apparatus for etching a semiconductor substrate. A plasma grid assembly is positioned in a reaction chamber to divide the chamber into upper and lower sub-chambers. The plasma grid assembly may include one or more plasma grids having slots of a particular aspect ratio, which allow certain species to pass through from the upper sub-chamber to the lower sub-chamber. In some cases, an electron-ion plasma is generated in the upper sub-chamber. Electrons that make it through the grid to the lower sub-chamber are cooled as they pass through. In some cases, this results in an ion-ion plasma in the lower sub-chamber. The ion-ion plasma may be used to advantage in a variety of etching processes. |
| US09633841B2 |
Methods for depositing amorphous silicon
Methods for depositing an amorphous silicon layer on wafers are disclosed. A process wafer, a control wafer, and a dummy wafer may be loaded into a chamber where an amorphous silicon layer may be deposited on the process wafer. Afterwards, the process wafer and the control wafer may be removed from the chamber. The chamber and the dummy wafers are dry cleaned together. The dry cleaned dummy wafers are used in the next run for depositing amorphous silicon layer. The process may be controlled by a computer system issuing a control job comprising a first process job and a second process job, wherein the first process job is to deposit an amorphous silicon layer on the process wafer, and the second process job is to dry clean the chamber and the dummy wafer. |
| US09633840B2 |
Method of manufacturing silicon carbide semiconductor substrate and method of manufacturing silicon carbide semiconductor device
A step of preparing a silicon carbide substrate (S11), a step of forming a first silicon carbide semiconductor layer on the silicon carbide substrate using a first source material gas (S12), and a step of forming a second silicon carbide semiconductor layer on the first silicon carbide semiconductor layer using a second source material gas (S13) are provided. In the step of forming a first silicon carbide semiconductor layer (S12) and the step of forming a second silicon carbide semiconductor layer (S13), ammonia gas is used as a dopant gas, and the first source material gas has a C/Si ratio of not less than 1.6 and not more than 2.2, the C/Si ratio being the number of carbon atoms to the number of silicon atoms. |
| US09633836B2 |
Methods of forming semiconductor devices including low-k dielectric layer
Methods of forming a dielectric layer are provided. The methods may include introducing oxygen radicals and organic silicon precursors into a chamber to form a preliminary dielectric layer on a substrate. Each of the organic silicon precursors may include a carbon bridge and a porogen such that the preliminary dielectric layer may include carbon bridges and porogens. The methods may also include removing at least some of the porogens from the preliminary dielectric layer to form a porous dielectric layer including the carbon bridges. |
| US09633835B2 |
Transistor fabrication technique including sacrificial protective layer for source/drain at contact location
Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures). |
| US09633831B2 |
Chemical mechanical polishing composition for polishing a sapphire surface and methods of using same
A method of polishing a sapphire substrate is provided, comprising: providing a substrate having an exposed sapphire surface; providing a chemical mechanical polishing slurry, wherein the chemical mechanical polishing slurry comprises, as initial components: colloidal silica abrasive, wherein the colloidal silica abrasive has a negative surface charge; and, wherein the colloidal silica abrasive exhibits a multimodal particle size distribution with a first particle size maximum between 2 and 25 nm; and, a second particle size maximum between 75 and 200 nm; optionally, a biocide; optionally, a nonionic defoaming agent; and, optionally, a pH adjuster. A chemical mechanical polishing composition for polishing an exposed sapphire surface is also provided. |
| US09633830B2 |
Phosphor-containing coating systems and fluorescent lamps equipped therewith
Coating systems suitable for use in generating fluorescent visible light, and lamps provided with such coating systems. The coating systems includes a phosphor-containing coating that contains at least a first phosphor that is predominantly excited by ultraviolet radiation of a first wavelength to emit visible light and absorbs but is less efficiently excited by ultraviolet radiation of a second wavelength. The coating system further includes a second phosphor that absorbs the ultraviolet radiation of the second wavelength and little if any of the ultraviolet radiation of the first wavelength. |
| US09633828B2 |
Ion focusing member and mass spectrometer using the same
An ion focusing member includes a ball having a surface with a plurality of dimples. The ion focusing member is adapted for being disposed in a mass spectrometer in a way that the ball is located at a spray path of analyte ions and located between a metal capillary and a mass analyzer. When the analyte ions pass through the ball, the analyte ions can be gathered at a downstream position of the ball, which in turn flow into the mass analyzer by a potential difference. Therefore, the ion focusing member of the present disclosure can effectively enhance the amount of the analyte ions entering into the mass analyzer, thereby improving ion transmission efficiency. As a result, a mass spectrometer equipped with the ion focusing member may have increased signal intensity of analyte, lowered limit of detection (LOD), and minimized detection error. |
| US09633821B2 |
Microwave plasma processing apparatus and microwave supplying method
Disclosed is a microwave plasma processing apparatus including: a processing container configured to define a processing space; a microwave generator configured to generate microwaves; a distributor configured to distribute the microwaves to a plurality of waveguides; an antenna installed in the processing container and to radiate the microwaves distributed to the plurality of waveguides to the processing space; a monitor unit configured to monitor a voltage of each of the plurality of waveguides; a storage unit configured to store a difference between a monitor value of the voltage monitored by the monitor unit and a predetermined reference value of the voltage and a control value of a distribution ratio of the distributor corresponding to the difference; and a control unit configured to acquire the control value of the distribution ratio of the distributor from the storage unit and to control the distribution ratio of the distributor. |
| US09633820B2 |
Method for forming resist film and charged particle beam writing method
In a method for forming a resist film, a first resist film is formed on a light shielding film formed on a substrate, by using a spin coating method. A protective film is formed on the first resist film. The protective film and the first resist film are simultaneously removed at the same region to expose a portion of the light shielding film. A first region in which the second resist film is formed on the light shielding film and a second region in which the second resist film is formed on the first resist film through the protective film, are provided. The protective film and the second resist film are simultaneously removed in the second region to expose the first resist film. A region in which the first resist film, and a region in which the second resist film, is formed, are separately provided on the substrate. |
| US09633819B2 |
Microscopy imaging method and system
Generally, the present disclosure provides a method and system for improving imaging efficiency for CPB systems while maintaining or improving imaging accuracy over prior CPB systems. A large field of view image of a sample is acquired at a low resolution and thus, at high speed. The low resolution level is selected to be sufficient for an operator to visually identify structures or areas of interest on the low resolution image. The operator can select one or more small areas of arbitrary shape and size on the low resolution image, referred to as an exact region of interest (XROI). The outline of the XROI is mapped to an x-y coordinate system of the image, and the CPB system is then controlled to acquire a high resolution image of only the XROI identified on the low resolution image. For 3D imaging, once the XROI is identified, each section of the sample can be iteratively imaged in the previously described manner, with the operator having the option to redefine the XROI later. |
| US09633817B2 |
Diaphragm mounting member and charged particle beam device
Conventional devices have been difficult to use due to insufficient consideration being given to factors such as the cost necessary for diaphragm replacement and the convenience of the work. In the present invention, a diaphragm mounting member installed in a charged particle beam device for radiating a primary charged particle beam through a diaphragm separating a vacuum space and an atmospheric pressure space onto a sample placed in the atmospheric pressure space is provided with a diaphragm installation portion to which a TEM membrane is mounted and a casing fixing portion mounted on a casing of the charged particle beam device. The diaphragm installation portion has a positioning structure for positioning a platform on which the diaphragm is held. |
| US09633812B1 |
Triode tube emulator circuit
Various examples are directed to analog vacuum tube emulator circuits. In various examples, a vacuum tube emulator circuit may comprise a first circuit and a second circuit. The first circuit may be effective to receive, a first voltage, a second voltage, and a third voltage. The first circuit may be effective to develop, at an input of the first circuit, a first current based on the first voltage, the second voltage, and the third voltage. The first circuit may output the first current to an output node. The second circuit may be effective to receive the first voltage, the second voltage, and the third voltage. The second circuit may be effective to develop, at an input of the second circuit, a second current based on the first voltage, the second voltage, and the third voltage. The second circuit may output the second current to the output node. |
| US09633811B2 |
Circuit breaker for hierarchically controlling short-circuit current and trips
The invention discloses a short circuit current hierarchical control tripping parameter circuit breaker. According to the invention, resistance of an alloy magnetic resistance body is changed through circuit current, and contract control can be carried out on short-circuit current. The control range of the circuit breaker can achieve that no magnetic resistance will be generated when current is no more than 8 times of rated operational current, and current limiting may be realized by the magnetic resistance when current is 8 times more than rated value. In this way, hierarchical control on short-circuit current of different levels of circuits can be carried out, and short-circuit current can be limited in a predetermined range, thereby restricting the short-circuit current in a predetermined range, solving a problem of power supply flickering, and avoiding large-area power failure accidents caused by override trip existing in an electrical control switch. |
| US09633807B2 |
Modular solid dielectric switchgear
Modular switchgear and methods for manufacturing the same. The modular switchgear includes a vacuum interrupter assembly, a source conductor assembly, and a housing assembly. The vacuum interrupter assembly includes a bushing, a fitting, and a vacuum interrupter at least partially molded within the bushing and including a movable contact and a stationary contact. The source conductor assembly includes a bushing, a fitting, and a source conductor molded within the bushing. The housing assembly includes a housing defining a chamber and a drive shaft and conductor positioned within the chamber. The housing assembly also includes a first receptacle for receiving the fitting of the vacuum interrupter assembly and a second receptacle for receiving the fitting of the source conductor assembly. The vacuum interrupter assembly, the source conductor assembly, and the housing assembly are coupled without molding the assemblies within a common housing. |
| US09633805B2 |
Pushbutton switch
A pushbutton switch includes a pushbutton unit and a resilient member. The pushbutton unit includes a mounting seat for being in proximity to an activator of a switch assembly, and a pushbutton covering the mounting seat. The resilient member has a switch contactor adjacent to the activator, two resilient arms extending from the switch contactor, and two abutment segments connected respectively to the resilient arms and engaging the limiting seat. When the pushbutton is pressed to move toward the limiting seat, the resilient arms are resiliently deformed to have a resilient force for urging the pushbutton away from the limiting seat, and the switch contactor is driven by the pushbutton to contact and move the activator. |
| US09633804B2 |
Electrical connector having a domed metal switch
A connector (100) and connector system are provided. A connector can include a domed metal switch (102) that is partially covered with a liquid impermeable barrier (101) such that a portion of the domed metal switch is exposed and the liquid impermeable barrier is coupled to the domed metal switch with a liquid impermeable junction (221). In a connector system, a complementary connector can include a dome switch actuator (706,707), partially covered with another liquid impermeable barrier. When pressed against the connector, the domed metal switch can deform to contact an electrical conductor (104). A control circuit (1309) can determine whether an electronic device or user is causing the deformation by detecting whether voltage or current is applied to the domed metal switch while deformed. |
| US09633800B1 |
Key structure
A key structure includes a base, a keycap, a first longitudinal bar, a second longitudinal bar, a first transverse bar and a second transverse bar. The first longitudinal bar, the second longitudinal bar, the first transverse bar and the second transverse bar are uniformly distributed in the range of the keycap. Consequently, the keycap is stably moved relative to the base. The first longitudinal bar, the second longitudinal bar, the first transverse bar and the second transverse bar are made of a metallic material. Since these bars are thinner than the scissors-type connecting element of the conventional key structure, the key structure of the present invention has reduced thickness. Moreover, since these bars are made of the metallic material, the structural strength of the key structure is increased. |
| US09633798B2 |
Atomic capacitor
This invention describes a capacitor that formed by a charge or species specific membrane material filled with aqueous or non-aqueous liquid with soluble salts dissolved and non-dissolved in solution and contained within the membrane material. When charged, the oppositely charged ion will leave the structure, leaving behind a charged atomic capacitor. |
| US09633794B2 |
Capacitor module of inverter for vehicle
A capacitor module of an inverter for a vehicle includes: a DC-link capacitor configured to be connected in parallel to an input of an inverter between a first high voltage input terminal and a second high voltage input terminal; and a plurality of Y-capacitors configured to be connected in parallel to the inverter. Each of the plurality Y-capacitors includes a first capacitor element connected between the first high voltage input terminal and a ground bus bar and a second capacitor element connected between the second high voltage input terminal and the ground bus bar, and the ground bus bars of the plurality of Y-capacitors are separately provided and the ground holes of the ground bus bars are disposed so as to face each other in a first direction. |
| US09633790B1 |
Multilayer ceramic capacitor and board having the same
A multilayer ceramic capacitor has a 3-terminal, vertical, multilayer structure in which portions of lead portions are not covered by external electrodes but are exposed to a mounting surface of a ceramic body. Insulating portions are disposed between the external electrodes on the mounting surface of the ceramic body. The insulating portions have an overlap portion covering portions of the external electrodes. 0.005≦i/e≦0.7 is satisfied, where i is a width of the overlap portion, and e is a width of the external electrode partially covered by the overlap portion. |
| US09633788B2 |
Multilayer ceramic capacitor
A multilayer ceramic capacitor includes a ceramic body and external electrodes provided on opposite end surfaces of the ceramic body. The ceramic body includes an inner layer portion including a plurality of ceramic layers defining inner layers and a plurality of first and second internal electrodes each disposed at an interface of adjacent ones of the ceramic layers defining the inner layers, outer layer portions sandwiching the inner layer portion in a direction in which the layers are stacked, and side margin portions sandwiching the inner layer portion and the outer layer portions in a widthwise direction. The side margin portion includes pores that decrease in number along a direction from inside to outside of the ceramic body. |
| US09633784B2 |
Electronic component
In an electronic component, a first terminal electrode is disposed on a first side surface and extends to a second principal surface. A second terminal electrode is disposed on a second side surface and extends to the second principal surface. A third terminal electrode is disposed on a third side surface and extends to the second principal surface. A fourth terminal electrode is disposed on a fourth side surface and extends to the second principal surface. Maximum values of thicknesses of portions located on the second principal surface of the third and fourth terminal electrodes are smaller than maximum values of thicknesses of portions located on the second principal surface of the first and second terminal electrodes. |
| US09633783B2 |
Transmission of signals through a non-contact interface
A bi-directional transmission system for transmission of signals through a non-contact interface includes a transformer inductively coupling a first circuit to a second circuit. The second circuit includes at least a first transmitter circuit arranged to translate a first digital input signal into at least one voltage pulse and to provide the at least one voltage pulse to a first winding of the transformer, wherein the at least one voltage pulse takes a positive or negative form based on whether the first digital input signal has a positive or negative edge. The first circuit includes at least a first receiver circuit arranged to receive at least one induced voltage pulse from a second winding of the transformer and to provide a first digital output signal reflecting the first digital input signal based on the at least one induced voltage pulse. |
| US09633781B2 |
Ferroresonant transformer for use in uninterruptible power supplies
A ferroresonant transformer is adapted to be connected to a primary power source, an inverter system, and a resonant capacitor. The ferroresonant transformer comprises a core, a main shunt arranged to define a primary side and a secondary side of the ferroresonant transformer, first windings arranged on the primary side of the ferroresonant transformer, second windings arranged on the secondary side of the ferroresonant transformer, and third windings arranged on the secondary side of the ferroresonant transformer. The first windings are operatively connected to the primary power source. |
| US09633775B2 |
Electronic device mounting apparatus
An electronic device mounting apparatus to be mounted with multiple electronic components, each of which includes at least one wire. The electronic device mounting apparatus includes a base unit and multiple pin units. The base unit includes a base wall and two side walls extending from the base wall. Each of the side walls has a first surface. The pin units are correspondingly mounted in the side walls and are spaced apart from one another. Each of the pin units has a wire-connecting segment having a connection portion that projects from the first surface, and two projecting portions that project from the connection portion and that define a slit therebetween. The slit is for a corresponding wire to be clamped therein by the projecting portions. |
| US09633773B2 |
Thin film common mode filter and method of manufacturing the same
Disclosed herein are a thin film common mode filter and a method of manufacturing the same. The thin film common mode filter according to the exemplary embodiment of the present invention includes a magnetic substrate made of a magnetic ceramic material; and coil patterns formed on the magnetic substrate, wherein external electrodes connected with the coil patterns are sequentially stacked and insulating layers formed on and beneath the coil pattern are made of a composite of ferrite powder and thermosetting resin. |
| US09633772B2 |
Solderable planar magnetic components
An inductive component having a printed circuit board (“PCB”) with a first side and a second side. An aperture extends through the PCB and a conductive winding is printed onto the PCB surrounding the aperture. A core is formed by a first core member and a second core member. The first core member includes a first base member with at least one joining surface which is solderable to the first side. A first core leg extends at least partially through the aperture. The second core member includes at least a second base member and is coupled to the first core member or the second side. To manufacture the PCB, the first core member is soldered to the first side and then the PCB is inverted. The second core member is then coupled to at least one of the first core member or the second side. |
| US09633771B2 |
Magnetic coupling device
A magnetic attachment comprises a stacked configuration including an attachment surface, a magnetic coupling device, and a device comprising at least one magnet. A thin non-conductive sheet may be positioned between the magnetic coupling device and the at least one magnet. The magnetic coupling device may include an aperture through which radio signals may pass. The magnetic coupling device may comprise alternating layers of magnetically permeable material and non-magnetically permeable material. The magnetic coupling device may have an adhesive backing layer and may be provided in a kit for a user to apply to a device. The embedded coupling device may be configured within the shell of a host device, or within a cover of a device. |
| US09633770B2 |
Method for improving coercive force of epsilon-type iron oxide, and epsilon-type iron oxide
An epsilon-type iron oxide having an Fe-site that is substituted with a platinum group element, provided that Fe of a D-site of the epsilon-type iron oxide is not substituted with the platinum group element. |
| US09633767B2 |
Power cable polymer connector
[Problem]A power cable polymer connector is provided which is lighter than when using a porcelain insulator and can exert a free-standing property to maintain the arranged position even if it is used horizontally. [Solution]A power cable polymer connector 1 includes a polymeric insulating tube 2 including a cable insertion hole 2a, 2b to allow an insertion of a stripped end 101 of a power cable 100. The polymeric insulating tube 2 further includes an insulation 20 including a polymer-based material and an embedded pipe 21 including a metal and embedded on an inner peripheral surface of the insulation 20 so as to face the end of the power cable 100. |
| US09633763B2 |
Wire harness and connector component
Provided is a wire harness that enables a connector component and a cable bundle to be attached to an external member while facilitating the operation and preventing wobbling of the connector component. The connector component is connected to a cable branch line on the radially outward side of the cable bundle, and includes a pair of confining surfaces on each of two sides in the circumferential direction of the cable bundle. The pair of confining surfaces face each other across a gap. The bundling member is disposed between the pair of confining surfaces, and is wound around the connector component and the cable bundle together from the outer side. The fixture is fixed to the bundling member and to an external member. |
| US09633761B2 |
Center conductor tip
A tip end conductor for an inner conductor of a coaxial cable, comprising a first portion engaging a first region of the outermost tip to mechanically engage the inner conductor and a second portion, axially inboard of the first portion, engaging a second region of the outermost tip to electrically engage the inner conductor. The first and second portions define first and second diameter dimensions, respectively, wherein the first diameter dimension is less than the second diameter dimension, and wherein the first portion of the tip end conductor includes a mechanically irregular surface for being press fit onto, and producing, a mechanical interlock along a first region of the terminal end of the inner conductor. |
| US09633754B2 |
Apparatus for generating focused electromagnetic radiation
A method for generating electromagnetic radiation, including the steps of: providing a series of adjacent electrode pairs arranged on a common dielectric substrate, the electrodes of each electrode pair substantially aligned on opposite sides of the common dielectric substrate; energizing a first electrode pair in the series of electrode pairs at an energizing time to produce a volume polarization distribution pattern within the common dielectric substrate; energizing a next adjacent electrode pair in the series of adjacent electrode pairs at a next energizing time to produce a variation of the volume polarization distribution pattern within the common dielectric substrate, the center of the next adjacent electrode pair located a distance from the center of the previous adjacent electrode pair, wherein the next energizing time is a time interval after the previous energizing time, the time interval less than the time for light to travel the distance between the centers of the previous and the next adjacent electrode pairs; and repeating the step of energizing the next adjacent electrode pair for subsequent electrode pairs in the series of adjacent electrode pairs to produce a continuous time-varying volume polarization distribution pattern within the common dielectric substrate. |
| US09633753B2 |
Mobile transport and shielding apparatus for removable x-ray analyzer
A mobile transport and shielding apparatus, which holds an x-ray analyzer for transport between operating sites, and also serves as a shielded, operational station for holding the x-ray analyzer during operation thereof. The x-ray analyzer is removably insertable into the apparatus and is operable either within the mobile transport and shielding apparatus, or outside of the apparatus. The apparatus may provide means to control, power, cool, and/or charge the x-ray analyzer during operation of the analyzer; and also means to transport the analyzer (e.g., a handle). |
| US09633752B2 |
Reactor shutdown trip algorithm using derivatives
A controller for producing a nuclear reactor shutdown system trip signal in response to at least one detector signal. The controller includes a signal conditioning module receiving the at least one detector signal and outputting a measured flux signal. A rate module generates a rate signal from the measured flux signal. A comparator circuit compares the rate signal to a trip setpoint and generates a first trip signal. |
| US09633747B2 |
Semiconductor memory devices and methods of testing open failures thereof
Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The data I/O unit selectively drives a first global I/O line and first/second global I/O lines according to the first or second test modes. The data transmitter selectively transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line, and the data on the first and second global I/O lines onto the first and second local I/O lines according to the first or second test modes. |
| US09633744B2 |
On demand knockout of coarse sensing based on dynamic source bounce detection
Systems, apparatuses and methods may provide for determining a magnitude of a bounce voltage on a source line associated with one or more memory cells and conducting, if the magnitude of the bounce voltage exceeds a threshold, a coarse-level program verification and a fine-level program verification of the one or more memory cells. Additionally, if the magnitude of the bounce voltage does not exceed the threshold, only the fine-level program verification of the one or more memory cells may be conducted. In one example, the coarse-level program verification is bypassed if the magnitude of the bounce voltage does not exceed the threshold. |
| US09633743B2 |
Method of shaping a strobe signal, a data storage system and strobe signal shaping device
A strobe signal shaping method for a data storage system includes receiving a strobe signal; boosting a first clock edge portion of the strobe signal when the strobe signal is received after having been idle or paused over a predetermined time period; and returning to an operating mode in which boosting is turned off with respect to a second clock edge portion of the strobe signal. |
| US09633740B1 |
Read retry operations where likelihood value assignments change sign at different read voltages for each read retry
Read retry operations in a memory employ likelihood value assignments that change sign at different read voltages for a plurality of read retry operations. A method for multiple read retries of a memory comprises reading a codeword using a first read voltage to obtain a first read value; mapping the first read value to first likelihood values based on a first likelihood value assignment that changes sign substantially at the first read voltage; reading the codeword using a second read voltage to obtain a second read value, wherein the second read voltage is shifted from the first read voltage to compensate for an expected change in analog voltages; and mapping the second read value to second likelihood values based on a second likelihood value assignment, wherein the second likelihood value assignment changes sign substantially at the second read voltage. Read data is optionally generated using iterative decoding of the codeword based on the first likelihood values and/or the second likelihood values. |
| US09633739B2 |
Method of erasing information and device for performing same
Methods and devices for erasing information stored on an electronic semiconductor component in a plurality of non-volatile memory elements are described. Irradiating the semiconductor component with erasing radiation until a target dose has been absorbed by the semiconductor component, the erasing radiation penetrating the semiconductor component, results in an ionization effect which influences the concentration of the charge carriers stored on the memory elements such that a statistical distribution of the threshold voltages of the memory elements forms a contiguous region. |
| US09633737B2 |
Semiconductor device
A semiconductor device includes a plurality of memory blocks including a plurality of memory cells, wherein the plurality of memory cells are divided into a plurality of pages; and an operation circuit configured to output operating voltages to local lines of a selected memory block, among the plurality of memory blocks, to perform a program operation, a read operation and an erase operation on the selected memory block, wherein the operation circuit is configured to apply a dummy pulse having a positive potential to the local lines of the selected memory block after completing the program operation, the read operation and the erase operation. |
| US09633732B2 |
Semiconductor memory device and operating method thereof
A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and a source line precharge path. The memory cell array may have a plurality of memory strings. The peripheral circuit may perform a program operation for the memory cell array. The control logic may control the peripheral circuit a channel precharge operation of the program operation. The source line precharge path may precharge channels of the plurality of memory strings through a source line of the memory cell array. The peripheral circuit may control, according to program data, a potential level of a selected one of a plurality of bit lines coupled to the plurality of memory strings during the channel precharge operation. |
| US09633728B2 |
Memory systems and memory programming methods
Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state. |
| US09633727B2 |
Resistive memory devices and methods of controlling resistive memory devices according to selected pulse power specifications
A method of controlling a resistive memory device includes: accessing a first pulse power specification satisfying a memory cell coefficient associated with at least a first of a plurality of memory cells included in a memory cell array; generating a first pulse power according to the accessed first pulse power specification; and performing a write operation on at least the first of the plurality of memory cells using the generated first pulse power. |
| US09633726B2 |
Resistive memory device, resistive memory system, and method of operating resistive memory device
A method of operating a resistive memory device having a plurality of word lines and a plurality of bit lines includes selecting one or more first memory cells connected to a first bit line, selecting one or more second memory cells connected to a second bit line, and simultaneously performing a reset write operation on the first and second memory cells using a first write driver. |
| US09633724B2 |
Sensing a non-volatile memory device utilizing selector device holding characteristics
Providing for improved sensing of non-volatile resistive memory to achieve higher sensing margins, is described herein. The sensing can leverage current-voltage characteristics of a volatile selector device within the resistive memory. A disclosed sensing process can comprise activating the selector device with an activation voltage, and then lowering the activation voltage to a holding voltage at which the selector device deactivates for an off-state memory cell, but remains active for an on-state memory cell. Accordingly, very high on-off ratio characteristics of the selector device can be employed for sensing the resistive memory, providing sensing margins not previously achievable for non-volatile memory. |
| US09633716B2 |
Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks
Methods and systems to provide a multi-Vcc environment, such as to selectively boost an operating voltage of a logic block and/or provide a level-shifted control to the logic block. A multi-Vcc environment may be implemented to isolate a Vmin-limiting logic block from a single-Vcc environment, such as to reduce Vmin and/or improve energy efficiency in the single-Vcc environment. The logic block may include bit cells of a register file, a low-level processor cache, and/or other memory system. A cell Vcc may be boosted during a read mode and/or write wordlines (WWLs) and/or read wordlines (RWLs) may be asserted with boost. A wordline decoder may include a voltage level shifter with differential split-level logic, and a dynamic NAND, which may include NAND logic, a keeper circuit, and logic to delay a keeper control based on a delay of the level shifter to reduce contention during an initial NAND evaluation phase. |
| US09633712B1 |
Semiconductor memory device capable of performing read operation and write operation simultaneously
A semiconductor memory device includes a charge storage element, a read transistor, and a write transistor. The charge storage element is for preserving a first data voltage. The read transistor has a first terminal coupled to the charge storage element, a second terminal coupled to a read bit line, and a control terminal coupled to a read word line. The write transistor has a first terminal coupled to the first terminal of the read transistor, a second terminal coupled to a write bit line, and a control terminal coupled to a write word line. The semiconductor memory device is able to perform a read operation and a write operation to the charge storage element simultaneously through the read transistor and the write transistor. |
| US09633710B2 |
Method for operating semiconductor device
Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period. |
| US09633705B2 |
Semiconductor memory device, memory system and access method to semiconductor memory device
A semiconductor memory device includes a block array having an m number of memory blocks in a row direction and an n number of memory blocks in a column direction (m being an integer of 2 or more and n being an integer of 1 or more), a page selection circuit configured to select a row in the block array from which a page is to be selected, and a page buffer configured to store data to be written in a page selected by the page selection circuit or data read from the page. Each of the memory blocks includes a memory cell array having a plurality of memory cells, a row selection circuit configured to select a row of the memory cell array, and a column selection circuit configured to select a column of the memory cell array. |
| US09633702B2 |
Memory system with uniform decoder and operating method of same
A memory system includes a memory array including a plurality of memory cells, and an encoder operatively coupled to the memory array, for encoding an original data element to be programmed into the memory cells into a uniform data element in which the number of “0”s approximately equals the number of “1”s. |
| US09633696B1 |
Systems and methods for automatically synchronizing media to derived content
A system for creating synchronized content is provided. The system includes a memory, at least one processor coupled to the memory, and a synchronization engine component executable by the at least one processor. The synchronization engine component is configured to locate a media file associated with synchronization information; locate at least one clip derived from the media file; generate a reference template representative of the media file; generate a derived content template representative of the at least one clip; align the derived content template with the reference template to create alignment information; and generate the synchronized content based on the at least one clip, the alignment information, and the synchronization information. |
| US09633692B1 |
Continuous loop audio-visual display and methods
An audiovisual work displaying a real world setting or object repeats as a video loop such that a viewer having normal visual and cognitive ability is unlikely or unable to detect the loop. The work is devoid of or has minimal instances of outliers which are otherwise more readily detected by a viewer upon successive looping of the segment. The segment may be of different lengths and optionally includes a corresponding audio component. The work is displayed on any type of screen for viewing, and may be delivered via the cloud, as a subscription, or other means. The display allows for a unique sensation where the viewer is locked in time (such as when viewing a still image) yet experiences video motion and audio variety without the sense of being caught in a continuous loop. |
| US09633686B1 |
Disc storage cassettes
A disc cassette includes a curved portion configured to hold multiple discs and a platform portion abuts the curved portion. The platform portion and the curved portion each include multiple rib pairs configured to separate adjacent discs from touching one another, and to form a disc slot between each rib pair. Disc slots of the platform portion of the disc cassette are configured to provide a guide for disc removal from the disc cassette. |
| US09633685B2 |
Method of writing to an optical data storage medium, method of reading from an optical data storage medium, and optical data storage medium
According to embodiments of the present invention, a method of writing to an optical data storage medium is provided. The method includes receiving a plurality of data elements, each data element having one of a plurality of values, wherein each value of the plurality of values is associated with a wavelength, and forming, for each data element, a nanostructure arrangement on the optical data storage medium, the nanostructure arrangement configured to reflect light of the wavelength associated with the value of the data element in response to a light irradiated on the optical data storage medium. According to further embodiments of the present invention, a method of reading from an optical data storage medium and an optical data storage medium are also provided. |
| US09633684B2 |
Magnetic recording medium, method for manufacturing magnetic recording medium, and magnetic recording/reproduction apparatus
According to one embodiment, a magnetic recording medium includes a silicon oxide underlayer having a recess pattern having a plurality of recesses, a nonmagnetic underlayer having a first hole pattern having a plurality of holes corresponding to the recess pattern, and a magnetic recording layer having a second hole pattern having a plurality of holes connected with the first hole pattern. The silicon oxide underlayer, the nonmagnetic underlayer, and the magnetic recording layer are formed in order on the substrate. |
| US09633683B2 |
Mode conversion via tapered waveguide
An apparatus includes a write head comprising a near-field transducer at a media-facing surface of the write head and a waveguide extending along a light-propagation direction. The waveguide is configured to receive light emitted from a light source at a fundamental transverse electric mode. The waveguide is configured to deliver the light to the near-field transducer at a transverse magnetic mode which directs surface plasmons to a recording medium in response thereto. The waveguide comprises a core with first and second tapers separated by a straight portion of constant cross sectional width. The first and second tapers successively decrease a cross-sectional width of the core as it nears the near-field transducer. The waveguide includes an end portion between the second taper and the near field transducer. The end portion comprises a top cladding layer, aside cladding layer, and a bottom cladding layer on the side cladding layer. |
| US09633682B1 |
Accurate spiral gate positioning in the presence of large non-repeatable runout
A magnetic write head is positioned based on position signals generated by a read head as the read head crosses a plurality of reference spirals. The spiral gate for monitoring a particular reference spiral is timed to begin at a time based on the radial position of the magnetic head when crossing the preceding reference spiral. In this way, the spiral crossing time for the particular reference spiral can be estimated with sufficient accuracy that the spiral gate coincides with the magnetic head crossing the particular reference spiral. Consequently, spiral detection is assured, even in the presence of large non-repeatable runout. |
| US09633675B2 |
Interlaced magnetic recording super parity
A storage device includes a storage medium having a first set of non-adjacent data tracks having a number of super parity sectors and a second set of non-adjacent data tracks interlaced with the first set of non-adjacent data tracks. The number of super parity sectors on a data track of the first set of non-adjacent data tracks is selected based on a distance between the data track and an inner diameter of the storage medium. |
| US09633674B2 |
System and method for detecting errors in interactions with a voice-based digital assistant
The method is performed at an electronic device with one or more processors and memory storing one or more programs for execution by the one or more processors. A speech input containing a request is received from a user. At least one action in furtherance of satisfying the request is performed. A user interaction is detected, such as a speech input to a digital assistant or a physical interaction with a device. It is determined whether the user interaction is indicative of a problem in the performing of the at least one action. Upon determining that the user interaction is indicative of a problem, information relating to the request is stored in a repository for error analysis. |
| US09633668B2 |
System and method of improving communication in a speech communication system
A speech communication system and a method of improving communication in such a speech communication system between at least a first user and a second user may be configured so the system (a) transcribes a recorded portion of a speech communication between the at least first and second user to form a transcribed portion, (b) selects and marks at least one of the words of the transcribed portion which is considered to be a keyword of the speech communication, (c) performs a search for each keyword and produces at least one definition for each keyword, (d) calculates a trustworthiness factor for each keyword, each trustworthiness factor indicating a calculated validity of the respective definition(s), and (e) displays the transcribed portion as well as each of the keywords together with the respective definition and the trustworthiness factor thereof to at least one of the first user and the second user. |
| US09633667B2 |
Adaptive audio signal filtering
An apparatus comprising: an audio signal analyzer configured to analyze an audio signal; an audio signal processor configured to signal process the audio signal to enhance the speech component of the audio signal dependent on determining the audio signal comprises speech components; and signal processing the audio signal to enhance a loudness of the audio signal otherwise. |
| US09633666B2 |
Method and apparatus for detecting correctness of pitch period
A method and an apparatus for detecting correctness of a pitch period. The method for detecting correctness of a pitch period includes determining, according to an initial pitch period of an input signal in a time domain, a pitch frequency bin of the input signal, where the initial pitch period is obtained by performing open-loop detection on the input signal; determining, based on an amplitude spectrum of the input signal in a frequency domain, a pitch period correctness decision parameter, associated with the pitch frequency bin, of the input signal; and determining correctness of the initial pitch period according to the pitch period correctness decision parameter. The method and apparatus for detecting correctness of a pitch period according to the embodiments of the present invention can improve, based on a relatively less complex algorithm, accuracy of detecting correctness of a pitch period. |
| US09633654B2 |
Low power voice detection
Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency. |
| US09633653B1 |
Context-based utterance recognition
In some implementations, a digital work provider may provide language model information related to a plurality of different contexts, such as a plurality of different digital works. For example, the language model information may include language model difference information identifying a plurality of sequences of one or more words in a digital work that have probabilities of occurrence that differ from probabilities of occurrence in a base language model by a threshold amount. The language model difference information corresponding to a particular context may be used in conjunction with the base language model to recognize an utterance made by a user of a user device. In some examples, the recognition is performed on the user device. In other examples, the utterance and associated context information are sent over a network to a recognition computing device that performs the recognition. |
| US09633648B2 |
Loudspeaker membrane and method for manufacturing such a membrane
The invention relates to a loudspeaker membrane having a sandwich structure, having a central web separating two layers of material based on high-rigidity threads impregnated with a polymer resin, characterized in that the central web is formed from a layer of material based on oriented natural fibers that are impregnated with a polymer resin. |
| US09633647B2 |
Self-tuning transfer function for adaptive filtering
The technology described in this document can be embodied in a computer-implemented method that includes receiving, at one or more processing devices, a plurality of values representing a set of coefficients of an adaptive filter over a period of time, and identifying, by the one or more processing devices based on the plurality of values, a phase error associated with a transfer function of the adaptive filter. The method also includes adjusting, based on the identified phase error, a phase associated with the transfer function of the adaptive filter such that coefficients calculated using the adjusted transfer function reduce the phase error. The method further includes determining a set of coefficients for the adaptive filter based on the adjusted transfer function, and programming the adaptive filter with the determined set of coefficients to enable operation of the adaptive filter. |
| US09633646B2 |
Oversight control of an adaptive noise canceler in a personal audio device
A personal audio device, such as a wireless telephone, includes an adaptive noise canceling (ANC) circuit that adaptively generates an anti-noise signal from a reference microphone signal and injects the anti-noise signal into the speaker or other transducer output to cause cancellation of ambient audio sounds. An error microphone is also provided proximate the speaker to measure the ambient sounds and transducer output near the transducer, thus providing an indication of the effectiveness of the noise canceling. A processing circuit uses the reference and/or error microphone, optionally along with a microphone provided for capturing near-end speech, to determine whether the ANC circuit is incorrectly adapting or may incorrectly adapt to the instant acoustic environment and/or whether the anti-noise signal may be incorrect and/or disruptive and then take action in the processing circuit to prevent or remedy such conditions. |
| US09633642B2 |
Electronic musical instrument system
Provided is an electronic musical instrument system. A PC is configured to perform an operation of emulating an analog synthesizer by a first software synthesizer. The PC installs a second software synthesizer to a hardware synthesizer on condition that the hardware synthesizer is confirmed to be the device corresponding to the second software synthesizer. The hardware synthesizer performs the operation of emulating the analog synthesizer by the second software synthesizer. The first software synthesizer and the second software synthesizer related to the operation of emulating the analog synthesizer have the same function respectively, and are capable of generating the same tone respectively, the effect of reproducing the same function and tone as the synthesizer that is to be emulated can be achieved respectively in two different devices, i.e. the PC and the hardware synthesizer. |
| US09633640B1 |
Guitar effector
Provided is an adjustment unit for guitar effector that is installed between input unit and output unit to adjust a volume and a tone based on the output signal by using a variable resistor in an analog circuit. The adjustment unit comprises one or more of a level part that adjusts a size of the output signal, a tone part that adjusts an amount of high-pitched sound and an amount of low-pitched sound, and a distortion part that adjusts a degree of distortion, one or more of the level part, the tone part and the distortion part are plural, and a switch comprising one or more of a level switch for selecting any one of the plurality of level parts, a tone switch for selecting any one of the plurality of tone parts, and a distortion switch for selecting any one of the plurality of distortion parts is installed. |
| US09633637B1 |
Magnetic resonance tuning device for stringed instruments
A tuning device and method for tuning or verifying the tuning of a string of a stringed instrument is provided. The device includes an electromagnetic pickup physically separate from the stringed instrument. The electromagnetic pickup is a noise cancelling pickup. The electromagnetic pickup ultimately provides an electrical signal indicative of a movement of the string in a magnetic field of the electromagnetic pickup to a processor electronic tuner. Optional features of the electromagnetic pickup increase the effective range of the pickup. |
| US09633631B1 |
Foldable guitar
A foldable guitar has a guitar body. The guitar body includes a main body and a rotating bar fixed to the main body. The rotating bar has a top end and a bottom end. Each of the top end and the bottom end is pivoted to the main body. A shape of the rotating bar matches a profile shape of the main body, and the rotating bar is foldable, such that a size of the guitar body is reduced when the rotating bar is folded toward the main body. |
| US09633627B2 |
Power supply, power control method thereof, and display apparatus having the same
A power supply and method of controlling power supplied to a light source are disclosed. The power supply includes a dimming-control voltage generator configured to generate a dimming-control voltage based on first and second adjustment values; a dimming controller configured to output a dimming control signal for controlling analog dimming and pulse width modulation (PWM) dimming of a light source based on the dimming-control voltage; and a driver configured to control the analog dimming and the PWM dimming of the light source based on the dimming control signal. |
| US09633624B2 |
Data processing apparatus for transmitting/receiving compression-related indication information via display interface and related data processing method
A data processing apparatus has a de-compressor and an input interface. The de-compressor de-compresses a compressed display data in an input bitstream. The input interface receives the input bitstream from another data processing apparatus via a display interface, parses indication information included in the input bitstream, and configures the de-compressor to employ a de-compression algorithm according to the indication information. |
| US09633622B2 |
Multi-user sensor-based interactions
Disclosed in some examples are methods systems and machine readable mediums in which actions or states of a first user (e.g., natural interactions) having a first corresponding computing device are observed by a sensor on a second computing device corresponding to a second user. A notification describing the observed actions or states of a first user may be shared across a network with the first corresponding computing device. In this way, the first computing device may be provided with information concerning the state of the user without having to directly sense the user. |
| US09633621B2 |
Source driving circuit capable of compensating for amplifier offset, and display device including the same
A display device capable of decreasing an amplifier offset using a gate-start pulse signal is disclosed. A display device includes a display panel, a control circuit, a gate driving circuit and a source driving circuit. The source driving circuit includes a plurality of source driving chips, compensates for an amplifier offset in response to the gate-start pulse signal, performs digital-to-analog (D/A) conversion on data received from the control circuit using gray scale voltages in response to the source control signal, and provides the converted data to the source lines. |
| US09633620B2 |
GOA circuit and liquid crystal display device
The invention provides a GOA circuit and a liquid crystal display device each including multiple cascade connected GOA units. An nth-stage GOA unit is for charging an nth-stage horizontal scan line in a display area. The nth-stage GOA unit includes a pull-up control circuit, a pull-up circuit, a transfer circuit, a first pull-down control circuit, a first pull-down circuit, a second pull-down control circuit, a second pull-down circuit and a main pull-down circuit, where n is a positive integer. The invention can improve the stage-transfer efficiency of GOA circuit, improve the output quality of scan drive signal so as to increase charging ratio of LCD tubes and also can accelerate the pull-down speed of scan drive signal. |
| US09633611B2 |
Readiness signaling between master and slave controllers of a liquid crystal display
A liquid crystal display includes a liquid crystal panel and a first to nth control substrates (n is an integer which is 2 or greater) which control the liquid crystal panel. When the first control substrate enters an operable status, the first control substrate transmits a readiness signal to the second control substrate which is at a next stage, and when the nth control substrate determines that the nth control substrate receives a readiness signal from a control substrate at a previous stage and is in an operable status, the nth control substrate transmits a readiness signal to the first control substrate, thereby being able to suppress a synchronization failure between the plurality of control substrates which are provided in a liquid crystal display. |
| US09633607B1 |
Adaptive RGBW conversion
The subject matter disclosed herein relates to conversion of RGB image data into RGBW image data for display by an image display apparatus. The image display apparatus accesses Red Green Blue (RGB) image data that corresponds to one or more images to be displayed by a Red Green Blue White (RGBW) display of the image display apparatus. The image display apparatus receives one or more inputs. Based upon the one or more external factors, the RGB image data is converted into RGBW image data. Based upon the RGBW image data, the RGBW display displays the one or more images. |
| US09633606B2 |
Device for driving light-emitting diodes, light-emitting device, and display device
A device for driving a light-emitting diode, a light-emitting device, and a display device are disclosed. The disclosed light-emitting diode driving device may include: a first transistor having a first conductive electrode connected with a source voltage terminal and having a second conductive electrode connected with an input terminal of the light-emitting diode; a second transistor having a control electrode connected with the second conductive electrode of the first transistor; and a capacitor having one end connected with a data voltage terminal and having the other end connected with a first node, which is connected with a control electrode of the first transistor and with a first conductive electrode of the second transistor. |
| US09633605B2 |
Pixel circuit having driving method for threshold compensation and display apparatus having the same
A pixel circuit includes a first path coupled to a gate of a driving transistor and a second path passing through a source and drain of the driving transistor. An initialization voltage of the driving transistor is set based on a gray scale data voltage carried along the first path. A voltage is stored in a capacitor coupled to the gate of the driving transistor based on the gray scale data voltage carried along the second path. The voltage stored in the capacitor is based on the gray scale data voltage, and may be compensated for variation in a threshold voltage of the driving transistor. |