| Document | Document Title |
|---|---|
| US09635210B2 |
Image reading apparatus that acquires of appropriate white reference data, image reading method, and image forming apparatus
An image reading apparatus includes a reading circuit, a white reference member, a control circuit, a memory circuit, and a processing circuit. The control circuit controls the reading circuit to: cause a light source to irradiate the white reference member with lights of a plurality of colors and cause a light receiving unit to receive the reflected lights. The processing circuit performs a process to identify abnormal data included in white reference data stored in the memory circuit. The processing circuit identifies information on the abnormal data in a light of an abnormal-data detected color among the plurality of colors. The processing circuit identifies the abnormal data in lights of other colors excluding the abnormal-data detected color among the plurality of colors based on the information on the abnormal data. The information is identified for the light of the abnormal-data detected color. |
| US09635207B2 |
Management system and information processing apparatus managing installation and settings of an application
An information processing apparatus comprises: an obtainment unit that obtains an application-related job from a management apparatus; a control unit that controls an application for the information processing apparatus in accordance with the obtained job; and a setting unit that changes, along with the control by the control unit, at least one of settings of the information processing apparatus and settings of the application in accordance with setting information included in the obtained job, wherein in a case where the obtained job represents an instruction to install the application, the control unit obtains, from the distribution apparatus, an application file and a license file that correspond to the application designated by the job, and installs the application using the application file and the license file. |
| US09635206B2 |
Image forming apparatus and power mode display method
Provided is an image forming apparatus that stops voltage supply to a display unit and a display control unit in a sleep mode and enables users to recognize a current power mode, with a simple structure. An image forming apparatus includes an operation unit, a main body control unit, and a power supply unit capable of supplying n voltages. The main body control unit includes a switching unit for switching to one of power modes including a ready mode in which n voltages are supplied, and p (n−m≧p≧1) sleep modes in which m voltages are not supplied, and one to n−m voltages are supplied. The operation unit includes light emitting elements, n power receiving units for respectively receiving the n voltages, and a light switching circuit for switching between supply and non-supply of the voltage to the light emitting element in accordance with a total number of the received voltages. |
| US09635201B2 |
Image forming apparatus having image reading device
In an image forming apparatus, when a pivot plate is at a closed position, a free end of the pivot plate is at a vertical level higher than first and second hinge portions which are arranged apart from each other in a width direction along a horizontal direction. A free end of the pivot plate moves in a space defined between first and second virtual vertical planes. The first virtual vertical plane is defined as a virtual vertical plane, on which a widthwise inner end of a first hinge portion is disposed, and which is perpendicular to a rotational center axis of the first hinge portion. The second virtual vertical plane is defined as a virtual vertical plane, on which a widthwise inner end of the second hinge portion is disposed, and which is perpendicular to a rotational center axis of the second hinge portion. |
| US09635193B2 |
Document reading device
Provided is a document reading device that can cause an image processing part to execute automatically image processing operations corresponding to respective plural functions, depending on a document mounting condition on a platen without performing a setting operation on a panel part. A system control part causes a document detection sensor to detect a part (periphery) of the document. The image processing operations corresponding to respective plural functions are made on image data of the document read by a scanner part. Further, when the platen cover plate open-close detection sensor detects that the platen cover plate is closed, the image processing part is allowed to execute a function that is assigned to the document detection part that has read the document. |
| US09635188B1 |
Mobile device data allocation system
A mobile device data allocation system includes a plurality of mobile devices that exchange data with a data service provider via a communication network. The data exchanged by each mobile device during a time period defines a total amount of exchanged data. An electronic shared-account device module is configured to determine a maximum amount of data at which the mobile devices are authorized to exchange during the time period. The shared-account device module further generates a control signal that regulates data exchange of the at least one mobile device in response to determining an upcoming event indicating the total amount of exchanged data will exceed the maximum amount of data. |
| US09635183B1 |
Providing compliance enforcement for manually dialed wireless numbers in a contact center
Systems and methods are disclosed for originating a call to a wireless number by a contact center while enforcing various compliance requirements. In one embodiment, a compliance server and a PBX cooperate to originate the call to the wireless number. The agent logs into the compliance server and the compliance server provides the agent with a wireless number to dial. The agent manually enters the wireless number using a phone connected to the PBX. The PBX queries the compliance server regarding establishing the wireless call. Upon authorization, the PBX establishes a first call leg to the compliance server, and a second call leg to the called party that is joined with the call leg to the agent's phone. Upon completion of the call, the agent dispositions the call to the compliance server, which then releases the first call leg. In response, the PBX then releases the second call leg. |
| US09635177B1 |
Agent training sensitive call routing system
A call-management method and system for distributing calls to agents, wherein each agent has a profile, e.g., defining agent skills, efficiency, etc. The call center management system implements an algorithm for selecting an agent to receive a call to optimize caller utility, call center efficiency, and agent training. Therefore, the algorithm does not seek to necessarily route a call to the agent having the skill set most suited to the call; rather, the call may be routed to an agent who needs experience in the area of the call, and thus serves as a training exercise. Skilled agents may be made available to shadow the training agent when available. |
| US09635174B1 |
Video relay service, communication system, and related methods for connecting users with N11 services in a video relay service environment
Video relay services, communication systems, and methods are disclosed connecting users with N11 services in a video relay service environment. A video relay service may comprise at least one server configured to manage a customer database including customer records for audibly-impaired users of the video relay service, manage an N11 database including alternate numbers corresponding to N11 codes for a plurality of different locations defined by political boundaries, receive incoming video calls including an N11 code from a calling party, resolve the N11 code to an appropriate alternate number for an N11 service based on a political boundary for the calling party responsive to a query of the N11 database, establish a first connection between a video communication device associated with the calling party and a call assistant station associated with a sign language interpreter, and establish a second connection between the call assistant station and the N11 service. |
| US09635172B2 |
Selective voice communication among multiple services
When a voice call is made between two users (Caller and Callee), both of which may have access to multiple voice communication services, the connection is made automatically by the communication equipment through a selectable communication service, based upon characteristics of connection. Those characteristics may include the services available to the users, the day of the week, the time of day, the availability of the Callee on a service, the geographic locations of the Caller and Callee, and Caller pre-established service preferences. Preferably, Caller preferences and associations of callees with unique destination identifiers are stored in a database created for the Caller and available to his communication equipment. An ultimate callee identifier selected for a particular call includes an indication of communication service, and connection an appropriate interface for that service is then provided automatically for the Caller. |
| US09635165B2 |
Method and terminal for connection switchover for headphone jack adaptor device
A method and terminal for switching a connection of a headphone jack adaptor device are provided. The method includes: monitoring a status of a phone, when it is determined that it is required to make/answer a call, disconnecting a signal connection between an audio signal and a headphone jack, and when it is determined that the call is ended, establishing a signal connection between the audio signal and the headphone jack. In the method for connection switchover for a headphone jack adaptor device according to the present disclosure, a connection status of a headphone jack adaptor device is switched according to monitoring a status of a phone, so that a user can normally make/answer a call without pulling out the headphone jack adaptor device when using the headphone jack adaptor device. |
| US09635159B2 |
Method and apparatus for providing immersive interaction via everyday devices
An approach is provided for providing immersive interaction via everyday devices based on one or more interaction events. In an example embodiment, an immersion service processes content presented at a device to determine one or more interaction events. The immersion service further determines (a) one or more control signals for controlling the device, one or more other devices, or a combination thereof to cause, at least in part, the one or more interaction events; (b) one or more protocols for transmitting the one or more control signals; or (c) a combination thereof. The immersion service also causes, at least in part, a transmission of the one or more control signals to the device, the one or more other devices, or a combination thereof. |
| US09635153B2 |
Test adapter
A test adapter for an electronic product to be tested includes a support structure and a product stand supported on the support structure for the product. The product stand is supported to the support structure by a guide structure that controls the vertical movement of the product stand. The product stand is arranged with a direct or indirect pressing movement from above to be movable from a top position to its low position supported by the guide structure. The test adapter includes a retaining structure for retaining the product stand in the low position and for retaining a latch structure of the adapter in its locking position. The latch structure is arranged to lock the product to the product stand. |
| US09635147B2 |
Protocol for an electronic device to receive a data packet from an external device
A protocol for transmitting data from an external device to an electronic device is provided in which the external device transmits a data stream which includes the same data packet repeated multiple times. The data packet has a predetermined length and has a header portion at a predetermined position. A receiver at the electronic device captures a block of data having the predetermined length from the transmitted data stream, and a decoder rotates the captured block of data to place the header portion at the predetermined position within the data packet. This eliminates the need for an accurate jitter-free clock reference at the electronic device. By shifting power consumption and system complexity to the external unit where power is typically not constrained, the energy efficiency of the electronic device can be increased. |
| US09635146B2 |
Method of using bit vectors to allow expansion and collapse of header layers within packets for enabling flexible modifications and an apparatus thereof
Embodiments of the apparatus for modifying packet headers relate to a use of bit vectors to allow expansion and collapse of protocol headers within packets for enabling flexible modification. A rewrite engine expands each protocol header into a generic format and applies various commands to modify the generalized protocol header. The rewrite engine maintains a bit vector for the generalized protocol header with each bit in the bit vector representing a byte of the generalized protocol header. A bit marked as 0 in the bit vector corresponds to an invalid byte, while a bit marked as 1 in the bit vector corresponds to a valid byte. The rewrite engine uses the bit vector to remove all the invalid bytes after all commands have been operated on the generalized protocol header to thereby form a new protocol header. |
| US09635144B2 |
Implementing an inter-pal pass-through
A system and method are provided that implement an inter-protocol adaptation layer (inter-PAL) pass-through processing scheme in wireless communicating devices operating with separate PALs to combine use of the individually-beneficial features of one PAL by allowing a first order capability for cross-talk between the PALs. A first PAL data packet is passed through the communicating system using a second PAL syntax. In so doing, a capacity to employ beneficial features of the second PAL advantageously in enhancement of the information in a data packet generated according to the first PAL is provided. |
| US09635143B2 |
Systems and methods for intermediaries to compress data communicated via a remote display protocol
The present solution automatically detects the remote display protocol capabilities of the client, server and/or intermediaries to determine whether the client and server should compress the remote display protocol data or the intermediaries, and in some cases both. |
| US09635139B2 |
User terminal, rule executing method thereof, server apparatus and rule executing system
A user terminal includes an inputter which receives a user command, a display, a communicator configured to communicate with an external server, and a controller configured to create a first rule in which the user terminal performs a first action when a first condition is met in another first user terminal, control the communicator to transmit the created first rule to the external server, and perform the first action according to an event command when the event command to perform the first action is received from the external server upon the first condition being met in the first user terminal. |
| US09635137B2 |
Geospatial visualization performance improvement for contiguous polylines with similar dynamic characteristics
Techniques are disclosed for rendering geographic information system (GIS) data. A server component responding to a request for GIS data for a given area combines contiguous elements that share the same dynamic characteristics. For example, a map server may combine the polylines of contiguous road segments sharing the same current speed/congestion conditions. Doing so may greatly reduce the number of individual polylines that are sent to a client for rendering. |
| US09635135B1 |
Systems and methods for handling replies to transaction requests
A client application may use a request/response protocol to request that a server perform a transaction. The client application may use an adapter to issue a request and to wait for a reply. The adapter may wait for the reply for a specific amount of time. If a reply is received after the time expires, then the reply may be received by a delayed reply handler employed by the client application. If the delayed reply handler receives a reply, it may identify the request to which the reply relates, and may then cause action to be taken. The particular action to be taken may depend on the nature of the transaction to be performed, and/or whether the transaction succeeded or failed. |
| US09635130B2 |
Method and apparatus for setting communication and recording medium thereof
Methods and apparatuses for setting communication with devices included in a group are provided. The method includes receiving, from a host device included in the group, a communication initiation request for setting communication between the host device and the first client device, determining whether to set communication with the host device based on a communication state of the first client device, receiving, from a second client device, a communication extension request for setting communication between the second client device and the first client device, determining whether the second client device is included in the group, and in response to the second client device being included in the group, determining whether to set communication with the second client device based on whether communication with the host device and the first client device is set. |
| US09635127B2 |
Personalization of devices while packaged
Devices are personalized while the devices are still at least partially contained within packaging. Discovery information may be exchanged between a packaged device and a user device. Such discover information may be exchanged as a result of the packaged device and the user device being moved into proximity with each other. A communication connection may be configured between the packaged device and the user device. Data may be obtained at the packaged device related to the communication connection. The packaged device may be personalized for a user utilizing the data. |
| US09635115B2 |
Unused location discriminator
Instrumentalities are effective to at least provide a user interface to a mobile device of the user for finding an unused space, among a plurality of spaces, according to a user-selected criteria, wherein the user interface is transmitted via a wireless protocol agreed during the wireless handshake; and in response, presenting the mobile device with first unused spaces meeting the user-selected criteria. Further, an access point may receive a problem space indication from the user concerning at least one of the unused spaces which associates a problem to the at least one of the unused spaces, thereby forming a problem space, and in response, second presenting a second at least one unused space to the mobile device without the problem space, wherein the second unused spaces are presented in order of nearness to a current user location. |
| US09635113B2 |
Software as a service framework for the digital engagement and conclusion of clients by service professionals
The software-as-a-service (the “Service”) is a web-based software product available to a service professional (an “SP”) allowing such SP to digitally engage clients on matters using any device that can connect to the internet such as a laptop, smartphone, tablet or other web-enabled devices (Google glasses, web-enabled watches etc.) (the “Device”). SPs can also use the Service to collaborate with their clients on matters by communicating and sharing documents with them in private collaboration portals exclusive to a specific client matter which are accessible through the Service and created by the Service during the Service's digital engagement process.The Service is presently directed to SPs such as lawyers for use in the digital engagement of, and collaboration with, their clients on client matters. However, the Service can be easily customized for use by other SPs—such as accountants, consultants, doctors, psychologists, dentists, contractors and others who perform services for clients, customers and/or patients—who would like to digitally secure terms of engagement, and subsequently communicate and share files, with their clients, customers and/or patients in a private digital collaboration portal. |
| US09635109B2 |
Enhancing reliability of a storage system by strategic replica placement and migration
Machines, systems and methods for optimizing data replication in a distributed storage network, the method comprising determining a need to create a replica for a data item in a remote failure zone in a data storage network; creating a temporary replica of the data item in a local failure zone defined in the data storage network, in response to determining that it is beneficial to create the temporary replica in the local failure zone based on a cost versus reliability improvement analysis; attempting to create the replica in the remote failure zone; and removing the temporary replica from the local failure zone, in response to successfully creating the replica in the remote failure zone. |
| US09635106B2 |
Identifying one or more peer devices in a peer-to-peer communication
Systems and methods for facilitating peer-to-peer communication are disclosed. A payor and a payee may establish a communication request with intent to execute a transaction in a P2P payment. The payee and the payor may transmit a first request and a second request respectively to an intermediary server to establish the communication. Based on the first request and the second request, the intermediary server sends one or more identification elements to the payee and payor. The payee and payor are identified at intermediary server as parties for P2P payment after an augmented reality (AR) experience and a resultant synchronized action that sends first trigger request and second trigger request from the respective devices. |
| US09635103B2 |
Dynamic virtual resource request rate control for utilizing physical resources
A virtualization host may implement dynamic virtual resource request rate controls for physical resources. Individual virtual resource request queues may be maintained for different virtual compute instances implemented at a virtualization host for a particular physical computer resource. After placing a work request from one of the individual virtual resource request queues into a physical resource request queue to be performed at the physical computer resource, a delay may be dynamically determined based, at least in part, on the workload of the physical resource request queue. After imposing the delay, a next work request from the individual virtual resource request queue may be placed into the physical resource request queue. In at least some embodiments, the dynamically determined delay may include a randomly added delay. |
| US09635100B2 |
Delivery of instructions in host applications
Embodiments of the systems described herein can implement one or more processes remotely delivering customized code to a host application and/or computing device. The host application may be configured as an Application Programming Interface with a customized code processing library that may configure the host application to receive further instructions remotely. The host application may be further configured to execute host code and/or third-party code. The host application may be configured to receive remote application logic, after the host application has been installed on a computing device, and to execute the received application logic to alter the behavior of the host application, such as selectively tracking end user interactions. |
| US09635094B2 |
Capturing and replaying application sessions using resource files
A capture and replay system identifies images displayed during an application session. A parser may generate Hypertext Markup Language (HTML) code from an application resource file or from the JSON post made by the application. A replay engine may use the HTML code to recreate at least some of the screens displayed during the application session. The capture and replay system may dynamically identify images that are not reproduced from the resources database and request an agent/(s) to asynchronously upload the image files associated with the images. The replay engine may use the uploaded image files to replay the application session. The capture and replay system may capture application sessions more efficiently by reproducing images from the resource file instead of capturing the images during the original application session and by dynamically requesting image files for the images were are not previously reproduced from the resource file. Once an image file is uploaded to server, it does not need to be requested again from any other agent. |
| US09635092B2 |
Method for processing shared file and cloud storage server
The present invention provides a method for processing a shared file and a cloud storage server. The method comprises: receiving, by a cloud storage server, an update request message from a second client; determining that a first file is located within a storage region of a first client according to an identifier of the first file and acquiring current version information of the first file from the storage region of the first client; and if it is determined that the version of the first file on the second client is older than the version of the first file within the storage region of the first client, generating a first download address and transmitting the first download address to the second client, so that the second client downloads the first file in the current version. According to an embodiment of the present invention, it is able to synchronously update the shared file. |
| US09635091B1 |
User interaction with desktop environment
Sharing resources by users of computing devices includes providing, at each computing device, a respective viewport to a common desktop environment that has the shared resources. The desktop is independently viewable and independently navigable through each respective viewport. Furthermore, each of the resources is independently viewable and able to be independently acted upon through each respective viewport. One or more resources of each computing device may be added to the desktop environment through the respective viewport of the computing device. A search user interface is provided for text string searching of resources of a respective viewport by a user at the computing device of the respective viewport; and an application launcher view user interface is provided for launching applications, which is viewable by clicking on an open space of the desktop environment as seen through the respective viewport, and by which launchable applications are searchable. |
| US09635089B2 |
Auto suggestion in search with additional properties
A computer initializes a configuration specified in an extensible markup language (XML) configuration file. The XML configuration file specifies at least one data source, a dimension to map each item of a plurality of items that include products, product accessories, or product support documents in the at least one data source, and a display priority for each item. Next, the computer reads data from the at least one data source specified in the configuration file. The computer generates an XML dimension hierarchy file for the read data using the configuration file. The XML dimension hierarchy file includes a dimension node for each item. Each dimension node has at least one property attached to each item and at least one synonym that is searchable to index each item. Finally, the computer preprocesses the XML dimension hierarchy file to index the at least one data source. |
| US09635084B1 |
Mission tuples in a streaming application environment
Tuple communication and decision determination is provided in a streaming environment. A processor: generates mission tuples, places the mission tuples in a computing stream of a stream application, accesses computing time upon, obtains the computing time of the mission tuples, determines: a current position in the computing stream for the mission tuples and a class and one or more sub-classes that each of the mission tuples belongs to, and communicates data: between the mission tuples and between the mission tuples and one or more runtime processes associated with the computing stream or one or more external processes associated with the computing stream. The mission tuples are configured to modify operations of the computing operators in the computing stream. |
| US09635082B2 |
Method of saving content to a file on a server and corresponding device
The invention relates to a method and a device for converting a data stream transporting content into a file on a server, the content including timestamps for its playback, the timestamps indicating the time elapsed since the start of said content, the method being wherein it includes steps for receiving, from a broadcast channel, streaming content, calculating at least one piece of temporal playback information from at least one of the timestamps and a reference clock, the reference clock being the time reference for a local area network, saving the content to a file on a server, the server file being accessible by a playback terminal connected to the local area network, and saving a piece of temporal playback information to a server file or to a description file associated with the server file. |
| US09635075B2 |
Method and apparatus for assigning identifiers to media services
A user assigns a major and minor channel number combination to a media service which does not have such a pre-existing combination, where such a media service is accessed by using such a channel combination without having to resort to the typical means of accessing the media service, such as using a web site URL or radio frequency. Optionally, the invention will automatically update the minor numbers associated with a media service when older versions of the media service become unavailable. |
| US09635072B1 |
System and method for remote presentation
Systems and methods for creating call reports which may allow a sales user to remotely present content to HCP users. Information for scheduling a remote meeting may be received from an application for creating call report on a first user computing device, a request for remote meeting may be sent to a conference system, and a group meeting ID may be received from the conference system. An individual meeting ID and an individual meeting invitation for the at least one invitee may be generated. The meeting invitation may include a link for the remote meeting. When the at least one invitee clicks on the link in the invitation, he/she is added to the remote meeting. The content is transmitted via the conference system, but no user interface of the conference system is displayed during the remote meeting. |
| US09635070B2 |
Method and apparatus for providing a collaborative workspace
A method and apparatus for providing collaborative workspace are disclosed. The method receives a request to establish a video conference for two or more participants, and obtains information from historical information on the two or more participants to be used with the collaborative workspace. The method determines preferences for each of the two or more participants as to a presentation of the collaborative workspace. The method receives one or more live images of the two or more participants and presents the collaborative workspace to each of the two or more participants in accordance with the preferences for each of the two or more participants. |
| US09635069B2 |
User feedback systems and methods
An exemplary method includes detecting, by a user feedback system, ring-back content provided to a first computing device during a connection period prior to beginning a communication session between the first computing device and a second computing device, and providing, by the user feedback system in conjunction with the detecting of the ring-back content provided to the first computing device, a feedback mechanism that facilitates a user of the first computing device providing feedback regarding the ring-back content. Corresponding systems and methods are also described. |
| US09635059B2 |
Systems, methods, and computer program products for adapting the security measures of a communication network based on feedback
An adaptable network security system includes trust mediator agents that are coupled to each network component. Trust mediator agents continuously detect changes in the security characteristics of the network and communicate the detected security characteristics to a trust mediator. Based on the security characteristics received from the trust mediator agents, the trust mediator adjusts security safeguards to maintain an acceptable level of security. Trust mediator also uses predetermined rules in determining whether to adjust security safeguards. Despite inevitable changes in security characteristics, an acceptable level of security and efficient network operation are achieved without subjecting users of the network to over burdensome security safeguards. |
| US09635058B1 |
Trust level modifier
A computer establishes normal activity levels of a factor associated with an application, system, network, or computing environment. The computer receives rules prescribing the trust levels assigned to users or devices during normal and abnormal activity levels exhibited by the factor. The computer monitors the activity level exhibited by the factor and determines whether the activity is normal or abnormal. If the computer determines that the factor is exhibiting abnormal activity, the computer modifies the trust level of associated users and devices according to the rules. The computer continues to monitor the activity of the factor until the computer determines that normal activity levels of the factor have returned, at which point the computer modifies the trust level of associated users or devices according to the rules. |
| US09635053B2 |
Computing system with protocol protection mechanism and method of operation thereof
A computing system includes: a control unit configured to: determine a protocol profile including a first protocol and a second protocol for communicating between a first device and a second device, generate a unified-protocol privacy mechanism for a privacy protection scenario, the unified-protocol privacy mechanism based on combining the first protocol and the second protocol; and a communication unit, coupled to the control unit, configured to communicate content information according to the unified-protocol privacy mechanism between the first device and the second device. |
| US09635050B2 |
Distributed supervised architecture for traffic segregation under attack
In one embodiment, data flows are received in a network, and information relating to the received data flows is provided to a machine learning attack detector. Then, in response to receiving an attack detection indication from the machine teaming attack detector, a traffic segregation procedure is performed including: computing an anomaly score for each of the received data flows based on a degree of divergence from an expected traffic model, determining a subset of the received data flows that have an anomaly score that is lower than or equal to an anomaly threshold value, and providing information relating to the subset of the received data flows to the machine learning attack detector. |
| US09635049B1 |
Detection of suspicious domains through graph inference algorithm processing of host-domain contacts
A processing device comprises a processor coupled to a memory and is configured to obtain data relating to communications initiated by host devices of a computer network of an enterprise, and to process the data to identify external domains contacted by the host devices. A graph inference algorithm is applied to analyze contacts of the host devices with the external domains in order to characterize one or more of the external domains as suspicious domains. The host devices are configured to counteract malware infection from the suspicious domains. The graph inference algorithm in some embodiments comprises a belief propagation algorithm, which may be initiated with one or more seeds corresponding to respective known suspicious domains or to respective ones of the external domains determined to be associated with command and control behavior. The processing device may be implemented in the computer network or an associated network security system. |
| US09635046B2 |
Systems, methods, user interfaces, and computer-readable media for investigating potential malicious communications
A data analysis system receives potentially undesirable electronic communications and automatically groups them in computationally-efficient data clusters, automatically analyze those data clusters, automatically tags and groups those data clusters, and provides results of the automated analysis and grouping in an optimized way to an analyst. The automated analysis of the data clusters may include an automated application of various criteria or rules so as to generate an ordered display of the groups of related data clusters such that the analyst may quickly and efficiently evaluate the groups of data clusters. In particular, the groups of data clusters may be dynamically re-grouped and/or filtered in an interactive user interface so as to enable an analyst to quickly navigate among information associated with various groups of data clusters and efficiently evaluate those data clusters. |
| US09635044B2 |
Electromagnetic persona generation based on radio frequency fingerprints
Electromagnetic (EM)/radio frequency (RF) emissions may be detected and corresponding EM personas may be created. One or more EM personas may be associated with a super persona corresponding to a particular entity. EM personas, super personas, and/or supplemental identifying information can be used to enforce security protocols. |
| US09635043B1 |
Method and apparatus for causing a delay in processing requests for internet resources received from client devices
A method and apparatus for causing a delay in processing requests for Internet resources received from client devices is described. A server receives from a client device a request for a resource. The server transmits a response to the first client device indicating that access to the resource is temporarily denied. The response includes a cryptographic token associated with the first request and a predetermined period of time during which the first client device is to wait prior to transmitting another request to access the resource. The server receives a second request for the resource, upon determining that the second request includes a valid cryptographic token, the server causes the second request to be processed. The server receives a third request for the resource, and upon determining that the third request does not include a valid cryptographic token, the server blocks the third request. |
| US09635042B2 |
Risk ranking referential links in electronic messages
A computer system enables a business to reduce risks from phishing electronic messages. One or more original web links embedded in the electronic message may be replaced with a replacement web link. If the determined risk score for the original webpage is large enough webpage and the user clicks on the embedded web link, a user is directed to an intermediate webpage rather than to the original webpage. The intermediate webpage may provide details about the original webpage so that the user can make an informed choice whether to proceed to the original website. For example, the intermediate webpage may provide pertinent information to a user such as the actual domain of the remote site, the country the site is hosted in, how long the site has been online, and a rendered screen capture of the remote website, and/or a confidence score. |
| US09635040B2 |
Method and apparatus for collecting information for identifying computer attack
A computer-implemented method and apparatus for identifying attacks, comprising: receiving information related to a computerized network, the information comprising description of the network and events occurring within the network; processing the events, comprising determining whether additional data is required; responsive to determining that additional information is required, collecting the additional information and processing the additional information; and providing attack information based on the information and on the additional information, wherein the additional information is more resource consuming to obtain or process than the information. |
| US09635037B2 |
Remote control of secure installations
Communication apparatus includes a one-way, hardware-actuated data relay, which includes a first hardware interface configured to receive a command from a communications network and a second hardware interface configured to convey the received command to a protected destination when the relay is actuated. A decoder includes a third hardware interface configured to receive a digital signature for the command from the communications network and hardware decoding logic coupled to verify the digital signature and to actuate the relay upon verifying the digital signature, whereby the command is conveyed via the second hardware interface to the protected destination. |
| US09635033B2 |
Methods, systems and computer readable media for detecting command injection attacks
Methods and systems are described for detecting command injection attacks. A positive, taint inference method includes receiving signature fragments on one hand, converting command injection instructions into command fragments on another hand, thus identifying potential attacks upon the condition that a command injection instruction includes critical untrusted parts by using signature fragments. A system detects command injection attacks using this kind of method, and remediates and rejects potential attacks. |
| US09635024B2 |
Methods for facilitating improved user authentication using persistent data and devices thereof
A method, non-transitory computer readable medium, and access policy management computing device that obtains a first set of attributes based on a login request received from a client device. The first set of attributes includes at least credentials for a user of the client device. A persistent data store record for the user is identified and a second set of attributes associated with the user, and included in the persistent data store record, is imported into a session cache record for the user. A fingerprint including the second set of attributes is compared to the first set of attributes. A multifactor or single factor authentication is initiated based on a result of the comparison to determine when the credentials for the user are valid. A session for the user is established and access by the user to network resource(s) is allowed, when the credentials for the user are valid. |
| US09635023B2 |
Secure digital communications
The present disclosure relates to an improved method for digital communication and, in particular, an improved method for digital communication in terms of improved authentication and traceability. More specifically, the present disclosure relates to a method of performing a transaction between a first device and a second device wherein the first device having an established trusted communication relation with a first trusted device and the second device having an established trusted communication relation with a second trusted device, the first and the second trusted device each having an established trusted communication relation with a fourth trusted device, the first and the second device being aware of a policy for the transaction specifying a role definition for the first and the second devices. |
| US09635017B2 |
Computer network security management system and method
A computer network security management system is provided, in which a corporate computer network can be substantially separated from an external network because the external exposure of the corporate computer network is minimized, and a possibility that a hacker may get into a relay server or a central server can be fundamentally cut off. The computer network security management system is expected to further enhance the security level of a corporate computer network. |
| US09635011B1 |
Encryption and decryption techniques using shuffle function
Encryption and decryption techniques based on one or more transposition vectors. A secret key is used to generate vectors that describe permutation (or repositioning) of characters within a segment length equal to a length of the transposition vector. The transposition vector is then inherited by the encryption process, which shifts characters and encrypts those characters using a variety of encryption processes, all completely reversible. In one embodiment, one or more auxiliary keys, transmitted as clear text header values, are used as initial values to vary the transposition vectors generated from the secret key, e.g., from encryption-to-encryption. Any number of rounds of encryption can be applied, each having associated headers used to “detokenize” encryption data and perform rounds to decryption to recover the original data (or parent token information). Format preserving encryption (FPE) techniques are also provided with application to, e.g., payment processing. |
| US09635007B2 |
Dynamic web services server
A method is provided for a multi-tenant system to accept web service calls from third party systems over a computer network. The method includes centrally receiving messages with different endpoint URLs from the third party systems over the computer network and processing each message by parsing an endpoint URL of the message to identify a tenant and an action for a payload of the message and authenticating the message. When the message is authenticated, the method further includes generating an acknowledgment of the message based on the identified tenant and the identified action and sending the acknowledgment over the computer network, routing the payload, the identified tenant, and the identified the action to a queue based on the identified tenant, retrieving the payload, the identified tenant, and the identified action from the queue, determining a user script corresponding to the identified action, and executing the user script on the payload. |
| US09635006B2 |
Hacker security solution for package transfer to and from a vehicle
A cloud based system for a package exchange with a vehicle service is discussed. The system can have servers having processors, ports, and databases and a security module running on the processors to receive a virtual key and one of a request for package exchange with a vehicle service, data, or both, from a package delivery vehicle. The virtual key has a first shelf life and is used for authentication of communications from the delivery vehicle. The security module can receive a security token having a second shelf life from a user. The security token is used for verification of the user and target vehicle. After the first authentication and in an overlap window of the two shelf lives, the security module can send the one or more commands to an on-board actuation module of the target vehicle to cause an electro-mechanical operation in the target vehicle. |
| US09634998B2 |
Electric system
An electric system including a first wireless apparatus, a display apparatus and a second wireless apparatus is provided. A first information is encrypted to be a first encrypted information and sent wirelessly by the first wireless apparatus. The display apparatus includes a display unit and a wireless communication unit electrically connected to the display unit. The wireless communication unit receives the first encrypted information and cause the display unit to display a first representative information corresponding to the first encrypted information. The first representative information and the first encrypted information are different. The second wireless apparatus reads the first encrypted information by the wireless communication unit, and the first encrypted information is decrypted to be the first encrypted information by the second wireless apparatus. |
| US09634996B2 |
Mapping and obscuring digital representations of a number of user accounts on a social network map
Mapping and obscuring digital representations of a number of user accounts on a social network map includes identifying a primary user account from a number of user accounts of a social network, determining, based on metadata associated with the user accounts, a relationship for each of the user accounts relative to the primary user account, mapping, based on the relationship for each of the user accounts relative to the primary user account, a digital representation of each of the user accounts to a territory on a social network map, determining, based on the relationship for each of the user accounts relative to the primary user account, an obscurity level for each of the user accounts, and obscuring, based on the obscurity level, the territory associated with the digital representation of each of the user accounts on a social network map from the primary user account. |
| US09634994B2 |
Custom responses for resource unavailable errors
A proxy server receives from a client device a request for a network resource hosted at an origins server for a domain. The request is received at the proxy server as a result of a DNS request for the domain resolving to the proxy server. The origin server is one of multiple origin servers that belong to different domains and resolve to the proxy server and are owned by different entities. The proxy server requests the network resource from the origin server. The proxy server receives a response from the origin server that indicates that the network resource is unavailable. The proxy server transmits a custom error page to the client device that indicates that the requested resource is unavailable. |
| US09634991B2 |
Method, apparatus, host, and network system for processing packet
A method, an apparatus, a host, and a network system for processing a packet. The method includes receiving, by a physical host through a virtual bridge in the physical host, a network packet sent by a source virtual machine in the physical host, where the network packet carries a source media access control (MAC) address and a target MAC address; obtaining, by the physical host according to the source MAC address and the target MAC address by querying correspondence between each virtual machine MAC address and a security domain, a security domain to which the source virtual machine corresponds and a security domain to which a target virtual machine corresponds; and controlling, by the physical host, the virtual bridge to discard the network packet, when the security domain to which the source virtual machine corresponds is different from a security domain corresponding to the virtual bridge. |
| US09634985B2 |
Selectively refreshing address registration information
Facilitating communications within a processing environment. Inbound traffic and outbound traffic on one or more virtual interfaces of the processing environment are monitored for a predefined amount of time. Based on the monitoring, a determination is made as to whether for a selected component of a virtual interface of the one or more virtual interfaces an inbound frame has been received but an outbound frame has not been transmitted for the predetermined amount of time. Based on determining that the inbound frame has been received but the outbound frame has not been transmitted, a generated outbound frame is forwarded to cause address registration information for the virtual interface to be refreshed. |
| US09634979B2 |
Systems and methods for using social network analysis to schedule communications
Systems and methods for improving the effectiveness of communications over a social network. A method for controlling network communication, comprises analyzing a social network in response to a request made by a user to send a message to a node in the social network, delaying for a period of time sending of the message based on a result of the analyzing, and sending the message to the node in the social network after the period of time has elapsed. |
| US09634977B2 |
Systems and methods of redactive messaging
The technology disclosed relates to embedding private comments in public messages. In particular, it relates to customizing public messages by including private comments that are directed to specific recipients. The private comments are included in the context of the public messages sent to their intended recipients but excluded from the public message when it is sent to other recipients. The private comments can be viewable only to their intended recipients and in the context of the public response. The public response as seen by recipients not intended to receive private comments does not include the private comments. This enables a sender of a private comment to efficiently communicate selected information to specific recipients without burdening all recipients with information which may not be relevant for them. Furthermore, it preserves the overall context of the original message. |
| US09634975B2 |
Systems and methods for distributed electronic signature documents
Systems and methods for providing a report describing the status of an electronic envelope. The electronic envelope includes a first electronic document to be distributed for electronic signature and an electronic signing template defining a set of at least one task that must be performed by an executor of the first electronic document to complete the electronic signature. The first electronic document is subject to a workflow including a plurality of events. The method includes receiving from a monitoring entity a selection of an identifier of an event of the plurality. The progress of the first electronic document through the workflow is monitored. That the at least one event has occurred with respect to the first electronic document is determined. In response to determining that the at least one event has occurred, the monitoring entity is notified of such. |
| US09634973B2 |
Method and apparatus for managing blind-carbon-copy account replies in e-mail communications
A apparatus and method for managing blind-carbon-copy replies in e-mail communications includes an electronic computing device configured to detect 602 that an e-mail account that is a blind-carbon-copy recipient of a received e-mail of an e-mail thread is sending a reply e-mail to at least one participant of a set of participants of the e-mail thread. The electronic computing device is also configured to determine 604, from the set of participants of the e-mail thread, an e-mail account adder that added the e-mail account to the e-mail thread as the blind-carbon-copy recipient. The electronic computing device is further configured to add 610 text to the reply e-mail indicating the e-mail account adder forwarded the received e-mail to the e-mail account or to send 614 an auto-generated e-mail notification to the at least one participant of the e-mail thread indicating the e-mail account adder added the e-mail account to the e-mail thread as a participant. |
| US09634972B1 |
Computer process to notify on the death of a loved one
The web application of this present process sends two text messages to a smartphone when the web page, where information on deaths and available funeral arrangements is initially entered, is closed; then, a third if information on funeral arrangements is updated. Two of the text messages, which provide notification of the death and a link to the web application to display information on the funeral arrangements, are forwarded to all relevant contacts in the smartphone, with the contacts forwarding the text messages to the relevant contacts in their smartphones. |
| US09634970B2 |
Apparatus and method for augmenting a message to facilitate spam identification
A computer includes a processor and a memory connected to the processor. The memory stores instructions executed by the processor to augment a message with network node attributes derived by linking from an original network node specified in the message to additional network nodes associated with the original network node. Message signatures representing the network node attributes are generated. The message signatures are evaluated to characterize the message. |
| US09634964B2 |
Contact matching method, instant messaging client, server and system
A computer-implemented method of providing matching information to prospective first and second users is performed at a server, the method including: receiving first audio data and first user information; receiving second audio data, and second user information; storing a first timestamp of the first audio data and first user information and a second timestamp of the second audio data and second user information; performing analysis processing on the first audio data to obtain first feature information, and performing analysis processing on the second audio data to obtain second feature information; judging whether the first timestamp and the second timestamp and the first feature information and the second feature information match; and if the first and second times of receipt and the first and second feature information match, sending the first user information to the second user and sending, by the server, the second user information to the first user. |
| US09634962B2 |
Pre-staging messages at a remote location
A method for message handling between a message producer and a remote message consumer in a shared queue computing environment. The method includes, receiving from a message producer, at least one message by a first queue manager. A first queue manager writes both the message data associated with at least one message, to a shared data repository, and a pointer, associated with the message data to a coupling facility, using an uncommitted key. The second queue manager, upon an indication that an uncommitted key is written to the coupling facility, reads the message from the shared data repository based on the pointer, and stores the message in an internal memory storage buffer. The first queue manager then commits a batch of messages. Finally, the second queue manager merges the pointer and the message from the internal memory storage buffer, in response to a remote message consumer requesting the message. |
| US09634960B2 |
Petabits-per-second packet switch employing cyclically interconnected switch units
A packet switching system of an access capacity scalable to multiple petabits per second is disclosed. A multiplicity of switch units, each of a relatively small dimension, is organized into orthogonal sets of switch units and the switch units of each set are cyclically interconnected through a respective dual rotator. Each switch unit has a contention-free switching mechanism and is coupled to a same number of dual rotators. Each switch unit has a switch-unit controller configured to route data received from external data sources to external data sinks coupled to any other switch unit by communicating with at most one switch-unit controller of an intermediate switch unit. |
| US09634957B2 |
Systems and methods for reducing server resources associated with a client connection
According to certain non-limiting embodiments disclosed herein, the functionality of a server is extended with a mechanism for identifying connections with clients that have exhibited attack characteristics (for example, characteristics indicating a DoS attack), and for transitioning internal ownership of those connections such that server resources consumed by the connection are reduced, while keeping the connection open. The connection thus moves from a state of relatively high resource use to a state of relatively low server resource use. According to certain non-limiting embodiments disclosed herein, the functionality of a server is extended by enabling the server to determine that any of a client and a connection exhibits one or more attack characteristics (e.g., based on at least one of client attributes, connection attributes, and client behavior during the connection, or otherwise). As a result of the determination, the server changes its treatment of the connection. |
| US09634940B2 |
Adaptive routing using inter-switch notifications
A method includes receiving in a network switch of a communication network communication traffic that originates from a source node and arrives over a route through the communication network traversing one or more preceding network switches, for forwarding to a destination node. In response to detecting in the network switch a compromised ability to forward the communication traffic to the destination node, a notification is sent to the preceding network switches. The notification is to be consumed by the preceding network switches and requests the preceding network switches to modify the route so as not to traverse the network switch. |
| US09634938B2 |
Adaptive scheduling of data flows in data center networks for efficient resource utilization
An approach is provided in which a first virtual machine, executing on a host computer system, generates a data packet with a target destination at a second virtual machine over a computer network. The host computer system identifies a data flow corresponding to the data packet based the data packet's header information, and analyzes path weightings of available paths that are made available to the identified data flow. In turn, the host computer system assigns one of the available paths to the identified data flow corresponding to a pre-defined physical layer path from the first virtual machine to the second virtual machine. |
| US09634933B2 |
Wireless communication method and apparatus thereof
To provide a stable high speed wireless network, the relay process is solved at the lower layers (PHY layer, MAC layer) without depending on upper layers to reduce the load of the upper layers to the utmost. Discrimination is made between a packet of one's own station and a relay packet to process the presence and absence of the relay packet without using a CPU to construct a wireless network executing the relay processing at a high speed. Further, the retransmission is executed without using a CPU to provide a stable wireless network. In addition, the table for relay process (routing table) is constantly updated to add to the table the information of the packets of which processes are not executed to eventually suppress unnecessary processes. |
| US09634930B2 |
Method of controlling virtual router, computer-readable recording medium, and control device
A method of controlling a virtual router includes: starting first and second virtual routers where a same address is set, on first and second networks; constructing, with respect to a plurality of virtual machines arranged in plural networks, a first virtual network that establishes coupling between first one or more virtual machines and coupling between the first one or more virtual machines and the first virtual router, and establishes coupling between second one or more virtual machines and coupling between the second one or more virtual machines and the second virtual router, the first one or more virtual machines being arranged on the first network, the second one or more virtual machines being arranged on the second network; constructing a second virtual network that establishes coupling between the first virtual router and the second virtual router; and creating and setting routing tables corresponding to the first and second virtual routers. |
| US09634929B2 |
Using context labels to scale MAC tables on computer network edge devices
In one embodiment, an access component of a local network edge device receives traffic, and generates a frame for the traffic that includes a remote context label that identifies an access component of the remote network edge device to which the traffic is to be forwarded upon arrival at the remote network edge device, and a virtual circuit label corresponding to a particular virtual service of the traffic. The local network edge device forwards the frame towards the remote network edge device. In another embodiment, the frame may be received at a core component of the remote network edge device, an in response to the remote context label identifying an access component of the remote network edge device, forwarded to the access component, which determines the particular virtual service, and forwards the traffic from the frame out the access component towards an endpoint for the traffic. |
| US09634928B2 |
Mesh network of simple nodes with centralized control
A mesh network of wired and/or wireless nodes is described in which a centralized controller provides seamless end-to-end service from the edge of the mesh network to mesh nodes located proximate to subscriber devices. The controller operates to provide a central configuration point for configuring forwarding planes of the mesh nodes of the mesh network, so as to set up transport data channels to transport traffic from the edge nodes via the mesh nodes to the subscriber devices. |
| US09634926B2 |
Method for use by an information processor
A method and apparatus for connecting an information processor to any network to perform communications are disclosed. A setting information indicating network settings to be set for an information processor when performing communications via a network is stored. A route setting packet, which is sent by a network device connected to the network to which the information processor is connected, is acquired to set a route to be used by the network device to communicate with another device. A device identification information for identifying a network device from which the route setting packet was sent is extracted from the route setting packet. The information processor is allowed to perform communications by acquiring the setting information associated with the extracted device identification information, and the information is specifically set for the information processor. |
| US09634922B2 |
Apparatus, system, and method for cloud-assisted routing
Among other aspects, the present disclosure provides a computer implemented method of routing information. A first routing information base is received at a proxy router. The first proxy router compares the first routing information based with a second routing information base associated with an assisted router. The proxy router updates the second routing information base based on the first routing information base. The proxy routing transmits updated routing information to the assisted router. |
| US09634919B2 |
Multipath data stream optimization
In one implementation, a source endpoint and a destination endpoint communicate using multipath. A data stream may be transmitted using a primary path. The source endpoint and the destination endpoint connect through an alternative path, but before portions of the data stream are transmitted using the alternative path, the alternative path is tested using one or more disposable packets. The source endpoint sends the disposable packet of the data stream using the alternative path to the destination path and receives a transmission parameter for the disposable packet of the data stream and the alternative path. |
| US09634915B2 |
Methods and computer program products for generating a model of network application health
Provided are methods and computer program products for generating a model of network application health. Methods may include receiving activity data that corresponds to activities of multiple applications that are operable to execute on at least one networked device, and combining the received activity data to remove redundant portions thereof and/or to reconcile inconsistencies therein. Based on the received activity data, ones of the multiple applications are identified, and relationships between the identified applications are determined. A model is generated including the identified applications and the relationships therebetween, and a representation of the model is displayed. Related computer program products are also provided. |
| US09634913B2 |
System for tracking diffusion
A tracking system is provided comprising a non-transitory computer readable storage medium having stored therein data representing instructions executable by a programmed processor for monitoring a database. The storage medium comprises instructions for receiving a current shortened content address from a requesting user, the current shortened content address including a shortened content address base and an appended link identifier, and instructions for determining a content address associated with the current shortened content address. The storage medium further comprises instructions for storing the shortened content address base and the appended link identifier in a database and instructions for determining if the tracking system has previously received a request for a shortened content address associated with the content address from the requesting user. The storage medium also comprises instructions for generating a new link identifier when the system has not previously received a request for a shortened content address associated with the content address from the requesting user and instructions for recording a chain of relationships of appended link identifiers with any new link identifiers in the database. |
| US09634910B1 |
Adaptive serving companion shared content
A system including a monitoring unit to monitor in-stream shared content and content served via the online service to a user; an in-stream shared content receiving unit to receive information about the in-stream shared content served with the content; a companion shared content selection unit to select the companion shared content based on the monitored in-stream shared content and content, and the received information; and a transmitting unit to transmit the selected companion shared content to the online service. |
| US09634909B2 |
Methods and systems of detection of most relevant insights for large volume query-based social data stream
The present invention relates to novel methods and implementing systems that afford a user the ability to automatically analyze all mentions and metrics/analytics of any query-based social data stream, and detect mentions or analytics that can be classified as important for a user of that stream. |
| US09634907B2 |
Devices and methods supporting content delivery with adaptation services with feedback
A device supporting content delivery is configured to run at least one content delivery (CD) service of a plurality of CD services. The plurality of CD services include adaptation services with feedback. |
| US09634905B2 |
Invalidation systems, methods, and devices
A computer-implemented method includes receiving, at a service running on the hardware, invalidation information relating to one or more resources; and determining whether the invalidation information relates to any resources currently stored on the service. Based on the determining, when the invalidation information relates to at least one resource not currently cached on the service, maintaining on the service at least some of the invalidation information; and using the maintained invalidation information on the service to prevent subsequent use of a version of at least one resource not currently stored on the service. |
| US09634903B2 |
Method and apparatus for distributing content to multiple devices
An approach is provided distributing content to multiple devices. Specifically, a distribution module causes, at least in part, a rendering of at least one user interface for distributing content among at least one device and one or more other devices with connectivity to the at least one device. The distribution module then causes, at least in part, one or more segmentations of the at least one user interface, wherein the one or more segmentations are associated with the at least one device, respective one or more of the one or more other devices, or a combination thereof. Next, the distribution module determines one or more interactions with the at least one user interface, the one or more segmentations, or a combination thereof to cause, at least in part, a distribution of the content. |
| US09634894B2 |
Network service aware routers, and applications thereof
In an embodiment, a computer-implemented method provides a service on a network. The method includes the following steps: (a) requesting, on a router, executable instructions from a remote server, the executable instructions specifying how the router is to operate to provide a service requested for a user of the network; (b) receiving the instructions; (c) initializing, on the router, a thread to execute the received instructions; (d) determining that a configuration of the router has changed; and (e) when the configuration of the router is determined to have changed, executing, on the initialized thread, the instructions to apply the service in accordance with the change in the router's configuration. |
| US09634893B2 |
Auto-provisioning edge devices in a communication network using control plane communications
In one embodiment, a network controller identifies a first sign of life for an edge device in a communication network (e.g., when the network controller receives an encapsulated workflow request for the edge device over a control plane of the communication network). The network controller further imports the encapsulated workflow request from the edge device over the control plane, determines configuration parameters for a tenant and a tenant network from the encapsulated workflow request, and transmits the configuration parameters to the edge device to provision the edge device for the tenant according to the configuration parameters. |
| US09634888B2 |
Method and system for transmitting data in parallel via wireless link and wired link
A method of the present invention includes: establishing one or more wireless links and one or more wired links for transmission data between a signal source end and a receiving end; allocating the transmission data to the wireless links and the wired links at the signal source end according to transmission rates of the wireless links and the wired links to transmit the transmission data in parallel via the wireless links and the wired links; and receiving data transmitted via the wireless links and the wired links at the receiving end, and restoring the received data into the transmission data. In the present invention, the data transmission abilities of the links are applied to the greatest extent. |
| US09634882B2 |
Method and system for continuous application state
Disclosed are methods and apparatuses to share application state across devices. This approach allows the user to switch devices and have the application on the new device share the same state as the previous device. In addition, this approach allows the user to shut down a device at a first point in time, and later be presented with the same state for the application at a second point in time on the same device when it is turned back on. |
| US09634880B2 |
Method for displaying user interface and display device thereof
Provided is a method for displaying a graphical user interface on a server device and a client device for controlling the server device. The method may include receiving AV data being played in the server device at the client device, receiving a command at the client device to control the server device, generating a first graphical user interface in response to the received command for display on the client device together with the AV data received from the server device, transmitting a control signal corresponding to the command to the server device, and receiving information related to a second graphical user interface displayed on the server device in response to the command. The first graphical user interface may be displayed on the client device before the information related to the second graphical user interface displayed on the server device is received. |
| US09634878B1 |
Systems and methods for data transfer using self-synchronizing quadrature amplitude modulation (QAM)
Quadrature Amplitude Modulation (QAM) methods, apparatus, and systems including a QAM transmit modulator to generate an output signal using a two-dimensional (2-D) QAM symbol constellation is disclosed. |
| US09634877B2 |
Trim for dual-port frequency modulation
Various methods provide for trimming the gain in a dual-port phase-locked loop (PLL) of a radio transceiver. Use is made of the radio's demodulator to perform modulation accuracy measurements, thereby reducing the cost and complexity of external test equipment. |
| US09634876B2 |
Phase reference symbol format for OFDM phase synchronization
The present invention describes an orthogonal frequency-division multiplexing, OFDM, transmitter and a method for embedding phase reference symbols into an OFDM symbol. The invention comprises a single-carrier pre-processing unit arranged to receive phase reference symbols and provide pre-processed phase reference samples as output and an OFDM modulator arranged to receive data symbols and the pre-processed phase reference samples as input and map the data symbols to sub-carriers and embed the single-carrier samples into a frequency sub-band of the OFDM symbol. While the invention particularly relates to an OFDM communication system, it should be noted that it could be applicable to any type of multicarrier communication system. |
| US09634875B2 |
Data and pilot sub-carrier or tone design for OFDM/OFDMA in wireless communications
A wireless communication device (alternatively, device) includes a communication interface and a processor, among other possible circuitries, components, elements, etc. to support communications with other wireless communication device(s) and to generate and process signals for such communications. A device is configured to generate various orthogonal frequency division multiplexing (OFDM) and/or orthogonal frequency division multiple access (OFDMA) packets (e.g., frames, signals, etc.) that are based on any of a group of set of OFDM/A frame structures. Across the various OFDM/A frame structures, the ratio of pilot sub-carriers to data sub-carriers across resource units (RUs) of decreases as the total number of sub-carriers across the RUs increases. In addition, some of the OFDM/A frame structures include different total number of sub-carriers yet same number of pilot sub-carriers. The device is configured to perform adaptation among and between the various OFDM/A frame structures based on any one or more considerations. |
| US09634871B2 |
Radio base station and method for transmitting common public radio interface data in radio base station
A method for transmitting Common Public Radio Interface (CPRI) data in a radio base station is provided, which is applicable to the radio base station having at least two CPRI links between a Radio Equipment Control (REC) and a Radio Equipment (RE). The method includes: dividing, by the REC, in-phase/quadrature phase (I/Q) data that needs to be transmitted to the RE into multiple paths of I/Q data with different content, where the multiple paths of I/Q data with different content make up the I/Q data before being divided; transmitting, by the REC, all paths of divided I/Q data to the RE over the at least two CPRI links. |
| US09634868B2 |
Wireless base station apparatus, wireless terminal apparatus, frequency resource allocation method, and method of forming transmission signal
A wireless base station apparatus and wireless terminal apparatus with a configuration which can prevent reductions in the accuracy of channel estimation when non-contiguous band transmission and SRS transmission are employed in an uplink line. In the base station apparatus (100), an allocation setting unit (106), which sets the reception band of an SRS at an SRS extraction unit (103) and sets the units of frequency allocation (RBG) at a CQI estimation unit (104) and allocation unit (105), matches the frequency position at the end of the SRS reception band to the frequency position at the end of any of the units of frequency allocation and sets the reception bandwidth of the reference signal to a natural number multiple of the bandwidth of the unit of frequency allocation. In the terminal apparatus (200), a band information setting unit (204), which sets the transmission band and units of frequency allocation (RBG), matches the frequency position at the end of the transmission band to the frequency position at the end of any of the units of frequency allocation and sets the transmission bandwidth of the SRS to a natural number multiple of the bandwidth of the unit of frequency allocation. |
| US09634863B2 |
Systems and methods for supporting two different protocols on a same physical connection
Systems and methods of supporting communications over a common network connection in a master-slave field bus network with a first type of packet formatted with a time-sensitive protocol and a second type of packet formatted with a non-time-sensitive protocol are provided. The slave devices are configured with filters to prevent the first type of packet from reaching a configurator and the second type from reaching a master device. The slave devices are also configured with arbitration logic so that the packets formatted with the time-sensitive protocol are provided with a priority over the packets formatted with the non-time-sensitive protocol. |
| US09634862B2 |
Parallel data switch
An interconnect apparatus enables improved signal integrity, even at high clock rates, increased bandwidth, and lower latency. An interconnect apparatus can comprise a plurality of logic units and a plurality of buses coupling the plurality of logic units in a selected configuration of logic units arranged in triplets comprising logic units LA, LC, and LD. The logic units LA and LC are positioned to send data to the logic unit LD. The logic unit LC has priority over the logic unit LA to send data to the logic unit LD. For a packet PKT divided into subpackets, a subpacket of the packet PKT at the logic unit LA, and the packet specifying a target either: (A) the logic unit LC sends a subpacket of the packet PKT to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD; (B) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA sends a subpacket of the packet PKT to the logic unit LD; or (C) the logic unit LC does not send a subpacket of data to the logic unit LD and the logic unit LA does not send a subpacket of the packet PKT to the logic unit LD. |
| US09634858B2 |
Field device with power over Ethernet
A field device that communicates in accordance with Ethernet signaling is provided. The field device is powered by virtue of its Ethernet connection. The field device preferably includes a feature board that includes an Ethernet network connection and a field device connection. The feature board is configured to power the field device with power received through the Ethernet network connection. The feature board interacts with the field device using a process industry standard communication protocol. A method of operating a field device is also provided. |
| US09634855B2 |
Electronic personal interactive device that determines topics of interest using a conversational agent
An interface device and method of use, comprising audio and image inputs; a processor for determining topics of interest, and receiving information of interest to the user from a remote resource; an audiovisual output for presenting an anthropomorphic object conveying the received information, having a selectively defined and adaptively alterable mood; an external communication device adapted to remotely communicate at least a voice conversation with a human user of the personal interface device. Also provided is a system and method adapted to receive logic for, synthesize, and engage in conversation dependent on received conversational logic and a personality. |
| US09634851B2 |
System, method, and computer readable medium for measuring network latency from flow records
The disclosure presents a system, method, and computer readable medium for computing network latencies. Network devices using flow processors create network traffic summary information in the form of flow records. A harvester may gather, process, and analyze flow records to find matching flows. Using matching flows, a harvester computes the latency, either one-way or round-trip, between two devices on the network. This information may be exported or stored on other devices on the network. The teachings of the present disclosure enable wide network coverage through the use of existing network traffic summary records. Further, the present disclosure mitigates network slowdowns associated with monitoring equipment. The present disclosure also reduces or eliminates the need for clock synchronization between devices on the network. |
| US09634848B2 |
Message broadcasting in a clustered computing environment
Approaches are provided for message broadcasting within a clustered computing environment such as a Cloud computing environment. Specifically, a message received from message queue (e.g., on a message queue server) is processed at a single node of a plurality of nodes within the clustered computing environment. The single node can be selected based on factors such as a best available node within the plurality of nodes. This single node identifies a set of message listeners to whom the message should be broadcast (e.g., based on a topic of the message and an association of the topic to the set of message listeners). The single node then publishes the message to the set of message listeners. Delivery confirmations, responses, etc. associated with the message are then tracked, processed, and/or routed by the single node. |
| US09634847B2 |
Robust multicast broadcasting
A method and system for multicasting IPTV channels includes using both a designated and a redundant network routing device. When the designated routing device detects that an MCDN network connection to an IPTV multicast source is unavailable, the designated routing device reduces its designation priority to a lower value. A message is sent to the redundant routing device with an instruction to increase its designation priority to a higher value. After the designation priorities have been modified, the designated routing device may serve as a new redundant routing device, while the redundant routing device may serve as a new designated routing device. The routing devices may remain in the new configuration, even after interrupted network connections are restored. |
| US09634846B2 |
Running link state routing protocol in CLOS networks
Systems, methods and transitory computer-readable storage media for running a link state routing protocol in a network that includes spine and leaf nodes. The methods include, receiving at a node in a network, one or more LSPs and re-forwarding the LSPs to other nodes. A spine node generates copies of the received LSPs and forwards the copies of the LSP to the leaf nodes in the network at a rate that is faster than the rate that the leaf nodes re-route the LSPs to the spine nodes using a hardware flooding mechanism in order to reduce the amount of processing that occurs at each spine node. In order to synchronize the LSP databases, the spine nodes send triggered CSNPs, using hardware flooding, to all leaf nodes in the network. |
| US09634842B2 |
Method for transmitting signed data and electronic signature token
Provided is a method for transmitting signed data and an electronic signature token, the method comprising: an electronic signature token obtaining a signing request data packet comprising data to be signed; signing the data to be signed to obtain signed data; obtaining a preset first transmitting strategy, and obtaining first data to be transmitted according to a part of the signed data and the first transmitting strategy, and transmitting the first data to be transmitted; after obtaining the signing request data packet, extracting and outputting the key information of the data to be signed; obtaining a confirmation instruction for the outputted critical information of the data to be signed; after obtaining the confirmation instruction, obtaining a preset second transmission strategy, and obtaining second data to be transmitted, according to a remaining part of the signed data and the second transmission strategy, and transmitting the second data to be transmitted. |
| US09634836B1 |
Key shadowing
A technique of generating key shadows performed by at least one computing device including at least one tangible computing element. The method includes receiving an indication of a first number X representing how many of the key shadows are to be generated, receiving an indication of a second number Y representing how many of the key shadows are to be required for decrypting an encrypted message, determining or receiving a master key for decrypting the encrypted message, and determining X key shadows of the master key. Y of those key shadows is sufficient to generate a range of more than one possible master keys that can be computationally feasibly searched for the master key. Less than Y of those key shadows is insufficient to determine any part of a value for the master key. Also, a technique of decrypting an encrypted message using Y of the key shadows. Further, associated systems. |
| US09634833B2 |
Gesture-based password entry to unlock an encrypted device
Systems and techniques are provided for gesture-based password entry to unlock an encrypted device. A gesture input from a user to a gesture interface may be received. The gesture input may be converted to gesture data which may be hashed using a hashing algorithm to obtain a table key. A table including a master key may be encrypted using the table key. The master key may include a key for decrypting a primary storage that is at least partially encrypted. A second gesture input may be receive. The second gesture input may be an input from a user to the gesture interface. The second gesture input may be converted to second gesture data which may be hashed using the hashing algorithm to obtain a key equivalent to the table key. The table including the master key may be decrypted using the key equivalent to the table key. |
| US09634832B2 |
Cryptanalysis method and system
A cryptanalysis method comprising: (A) Performing a ciphertext-only direct cryptanalysis of A5/1 and (B) Using results of Step (A) to facilitate the decryption and/or encryption of further communications that are consistent with encryption using the session key and/or decryption using the session key, wherein the cryptanalysis considers part of the bits of the session key to have a known fixed value, and wherein the cryptanalysis finds the session key. An efficient known plaintext attack on AS/2 comprises trying all the possible values for R4, and for each such value solving the linearized system of equations that describe the output; The solution of the equations gives the internal state of R1, R2, and R3; Together with R4, this gives the full internal state which gives a suggestion for the key. |
| US09634831B2 |
Role-based distributed key management
Implementations for providing role-based distributed key management (DKM) replication are described. A server node receives a request from a requester node to perform a DKM create or update function. The server node determines the role of the requester node based on a public key of the requester node. The server node determines whether the role of the requester node indicates that the requester node is authorized to request the DKM create or update function. If the requester node's role is authorized to request the DKM create or update function, then the server node performs the requested function. The DKM create or update function may involve a replication function. Public key and trust chains may be derived from physical cryptographic processors, such as TPMs. |
| US09634829B2 |
Flexible architecture and instruction for advanced encryption standard (AES)
A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers. |
| US09634826B1 |
Apparatus and method for automatic bandwidth calibration for phase locked loop
Described is an apparatus which comprises: a time-to-digital converter (TDC) to receive a reference clock and a feedback clock, wherein the TDC is to generate a digital output code representing a time difference between the reference clock and the feedback clock; a circuitry to apply a digital code to an output of the TDC; and a node to receive the digital output code from the TDC and the digital code from the circuitry, wherein the circuitry is to monitor the digital output code and to control the TDC according to at least the monitored digital output code. |
| US09634821B2 |
Method and apparatus for channel access in WLAN system
A channel access method in a wireless local area network (WLAN) system using a multi-channel configured by aggregation of a plurality of subchannels is provided. The method includes receiving from an access point (AP) a multi-channel switching request frame for requesting a first station operating in a first subchannel constituting the multi-channel to switch to a second subchannel constituting the multi-channel and transmitting a multi-channel switching response frame for reporting whether to switch to the second subchannel in response to the multi-channel switching request frame. |
| US09634820B2 |
Method and arrangement in a communications network
A method in a network node for adapting a Secondary cell, SCell, command to a user equipment, UE, is provided. The SCell command is one of a setup and release command. The network node adapts the SCell command by one of advancing and delaying the timing of sending said SCell command with respect to a start of a transmission occasion of disjoint signals on which one of the UE and the network node is performing at least one of a measurement, the disjoint signal is a signal that is not used for performing the measurement in every subframe, a data transmission, the disjoint signal is a signal that is not used for transmitting the data in every subframe, and a data reception, the disjoint signal is a signal that is not used for receiving the data reception in every subframe. |
| US09634819B2 |
Method and apparatus for signal interference processing
A system that incorporates the subject disclosure may perform, for example, a method for detecting signal interference in a first segment of a plurality of segments of a radio frequency spectrum of a wireless communication system, determining according to the signal interference a measure of quality of service of the first segment for transmitting voice traffic, comparing the measure of quality of service to a desired measure of quality of service measure for voice traffic, determining from the comparison that the first segment is not suitable for voice traffic, and notifying a system that the first segment is not suitable for voice traffic. Other embodiments are disclosed. |
| US09634817B2 |
Systems and methods for use with orthogonal frequency division multiplexing
Systems and methods are provided for enabling H-ARQ communication between a base station and one or more wireless terminals. Methods for enabling incremental redundancy (IR) based H-ARQ, Chase based H-ARQ and Space-Time Code combining (STC) based H-ARQ between devices for down-link and up-link direction transmissions are provided in the form of an information element (IE) for use with a Normal MAP convention as currently accepted in the draft version standard of IEEE 802.16. In addition, embodiments of the invention provide a resource management scheme to protect a network from abuse of resources from a wireless terminal not registered with the network. Components of the down-link and up-link mapping components of a data frame transmitted from the base station to one or more wireless terminals included messages that are readable by all wireless terminals as well as some messages that are encrypted and only readable by wireless terminals that are authenticated as being registered with the network. |
| US09634814B2 |
Efficiency of traffic communication over a downlink (DL) channel
An apparatus and method for communication including determining an assignment for one of a plurality of symbol durations in a format combination; determining if at least one bit from one or more first upper channels is available if the assignment is associated with the one or more first upper channels and occupying the one of the plurality of symbol durations with the at least one bit, or if unavailable, occupying the one of the plurality of symbol durations with at least one bit from one or more second upper channels or another first upper channel, wherein the first upper channels and the second upper channels are different; and disabling transmission of format information; or including enabling a BTFD hypothesis testing mode; receiving one or more symbol durations on a physical channel; and attempting to decode the received symbol duration with a first hypothesis that a DCCH channel is not transmitted. |
| US09634798B2 |
Processing method and device for packet loss compensation in video-conferencing system
A processing method and device for packet loss compensation in video-conferencing system are provided. The method includes: when a video conference is held, judging whether terminals participating in the video conference include one or more FEC terminals, if yes, matching code stream processing capabilities of transmitting terminal and receiving terminal between FEC terminals which transmit a code stream or between an FEC terminal and an ordinary terminal which transmit code stream, and converting a data code stream transmission rate of the transmitting terminal into a bearable data code stream rate of the receiving terminal. The device includes a judgment component and a matching component. The solution enables a terminal with packet loss to activate an FEC function to compensate lost data, and also enables an ordinary terminal without packet loss to keep an original data code stream rate for communication, thereby maximally ensuring the image quality of the video-conferencing system. |
| US09634797B2 |
Method of transmitting a digital signal for a semi-orthogonal MS-marc system, and a corresponding program product and relay device
A method for semi-orthogonal transmission of a signal intended for a system with N sources, M relays and a single receiver whereby the simultaneous transmission on a same spectral resource by the relays is successive and not simultaneous to a simultaneous transmission on a same spectral resource by the sources. The includes, by relay: joint iterative detection/decoding of messages transmitted respectively by the sources to obtain decoded messages, detecting errors on the decoded messages, interleaving the detected messages without errors followed by algebraic network coding consisting of a linear combination in a finite group of an order strictly higher than two of the interleaved messages to obtain a coded message, the linear combinations being independent, two by two, between the relays of the system, and formatting including channel coding to generate a signal representative of the network coded message. |
| US09634796B2 |
Optical transmission device and optical transmission system
An optical transmission device includes an error correction scheme determining unit, an error correction encoder, a modulation format determining unit and an optical transmitter. The error correction scheme determining unit determines an error correction scheme based on a latency between the optical transmission device and a correspondent device. The error correction encoder generates encoded data by performing an error correction encoding on transmission data using the error correction scheme determined by the error correction scheme determining unit. The modulation format determining unit determines a modulation format based on the error correction scheme determined by the error correction scheme determining unit and transmission characteristics between the optical transmission device and the correspondent device. The optical transmitter generates a modulated optical signal from the encoded data with the modulation format determined by the modulation format determining unit. |
| US09634795B2 |
Configurable constellation mapping to control spectral efficiency versus signal-to-noise ratio
Mixed mode constellation mapping to map a data block to a block of sub-carriers based on a configurable set of one or more constellation mapping schemes, and corresponding mixed mode least likelihood ratio (LLR) de-mapping based on the configurable set of one or more modulation schemes. The set may be configurable to include multiple modulation schemes to provide to a SEvSNR measure that is a non-weighted or weighted average of SEvSNR measures of the multiple modulation schemes. Mixed mode constellation mapping may be useful be configurable to control spectral efficiency versus SNR (SEvSNR) over a range of SNR with relatively fine SNR granularity, and may be configurable to control SEvSNR over a range of SNR at a fixed FEC code rate, which may include a highest available or highest permitted code rate. |
| US09634789B2 |
Method and device for determining whether a configuration of an optical transmission interface has to be adjusted and the configuring thereof
For determining whether a configuration of an optical transmission interface of a first device has to be adjusted for transmitting optical signals to a second device via an optical band-pass filter, the second device having an optical reception interface configured to enable receiving optical signals output by said optical band-pass filter and transmitted by the first device on a carrier wavelength when said carrier wavelength is comprised in the passband of the optical band-pass filter, said carrier wavelength and/or said passband of the optical band-pass filter being a priori unknown, a monitoring device performs: monitoring an evolution of a difference level between codewords received by the second device via said optical signals and corresponding codewords transmitted by the first device; and determining whether the configuration of the optical transmission interface of the first device has to be adjusted, on the basis of said monitoring. |
| US09634787B2 |
Optical add-drop multiplexer
Input light includes a multicarrier signal and first CW light of a first optical frequency. A transmitter generates a modulated optical signal based on an inverted signal of a dropped signal. A light source generates second CW light of a second optical frequency. A delay element adjusts a phase difference between the modulated optical signal and the second CW light. The multicarrier signal, the first CW light, the modulated optical signal and the second CW light are input to nonlinear optical medium. A detector detects beat frequency component between the modulated optical signal and the second CW light. A controller controls the delay element so as to increase the beat frequency component. A difference between the first optical frequency and an optical frequency of the dropped optical signal is substantially the same as a difference between the second optical frequency and an optical frequency of the modulated optical signal. |
| US09634780B2 |
Powerline interference indication and mitigation for DSL transceivers
The present disclosure outlines mechanisms, systems, methods, techniques and algorithms that gateway devices and powerline communication (PLC) networks can follow to mitigate adverse effects from the aforementioned inter-network interference. Although the present disclosure provides implementation details for G.hn and VDSL2, the mechanisms, systems, methods, techniques and algorithms described herein are equally applicable to other similar technologies. Therefore, when referring to non-implementation specific systems, methods, techniques and algorithms the term PLC is used to refer to a powerline network and the term customer premises equipment (CPE) is used to refer to a home-gateway device. |
| US09634779B2 |
System and method for selecting input feeds to a media player
A system and method are provided for enabling a plurality of media feeds, such as internet radio stations, to be played through a standard media player, such as a radio receiving device, using the tuning or input selection controls of the media player to control the selection of which media feed to play. Identification signatures are added to channels and transmitted to the media player by transmitter. A controller captures the feedback of the media player and, if it detects one of the signature signals in the feedback, instructs the media feed selector to select a media feed which corresponds to the detected identification signature. The selected audio feed may then be transmitted to the media player on the corresponding channel for playback. |
| US09634778B2 |
Measurement device and measuring method using simulated uplink fading
A measuring device for measuring a reaction of a device under test to an uplink channel quality parameter, indicating a quality of a transmission channel from the device under test to the measuring device, comprises signal generation means, set up for generating a first signal including the uplink channel quality parameter. The uplink channel quality parameter is set by the signal generation means independent from an actual channel quality of the transmission channel. Transmission means is set up for transmitting a second signal, which is derived from the first signal or is identical to the first signal to the device under test. Receiving means is set up for receiving a third signal transmitted by the device under test and created by the device under test based upon the uplink channel quality parameter and for determining the reaction of the device under test to the uplink channel quality parameter. |
| US09634776B1 |
Adapting envelope tracking parameters to operating conditions of mobile communication device
A mobile communication device may use sensor data to identify the current device state based on sensor data, device parameter values and/or device usage data. The mobile communication device may then measure the impedance value of a characteristic circuit, such as the antenna or the power amplifier. Responsive to determining that the measured impedance value differs from a pre-defined base impedance value by more than a certain threshold value, the mobile communication device may retrieve, from a memory, a set of envelope tracking (ET) parameter values corresponding to the current state of the communication device and the measured impedance value. The mobile communication device may calculate, using the retrieved ET parameter values, a target supply voltage to be applied to the power amplifier. |
| US09634775B2 |
Method for configuring a reconfigurable antenna system
The invention relates to a method (1) for configuring a reconfigurable antenna system (100). The method (1) comprises the following steps: a) selecting one or more groups of antenna configurations in a reference set of antenna configurations; and b) selecting one or more antenna configurations to be tested for each group of antenna configurations, which has been selected at the previous step a); and c) evaluating the radiating performance of said reconfigurable antenna system (100) for each antenna configuration, which has been selected at the previous step b), the radiating performance of said reconfigurable antenna system being evaluated on the base of estimation values that are calculated during one or more testing sessions of said reconfigurable antenna system; and d) selecting the optimal antenna configuration, for which said reconfigurable antenna system (100) has provided the best radiating performance during said testing sessions; and e) if the group of antenna configurations, to which said optimal antenna configuration belongs, comprises only said optimal antenna configuration, configuring said antenna elements (101) according to said optimal antenna configuration; or f) if the group of antenna configurations, to which said optimal antenna configuration belongs, comprises a plurality of antenna configurations, selecting said group of antenna configuration as new reference set of antenna configurations; and g) repeating the previous steps (a)-(d) for said new reference set of antenna configurations. |
| US09634774B1 |
Desense reduction via pin remap in modular device
A modular device system is provided having a base portable electronic communication device. The base portable electronic communication device has a display side and a reverse side, and one or more antennas being located along one or more of the device edges. A ground element on the reverse side of the housing is adjacent to the antennas and is grounded to the chassis. A multi-pin connector array on the same side is located adjacent to the ground element and the ground element lies between the connector array and the antennas. The connector array includes multiple pins supporting multiple data speeds, and the high speed data pins are located closer to the array center than the low speed data pins. The array is configured and located to electrically connect to a mating array on a module device when the module device is mated to the base portable electronic communication device. |
| US09634770B2 |
Quantum communication system
A transmitter for a quantum communication system, the transmitter comprising an interferometer, the interferometer having a first path with a phase modulator and a second path configured such that light pulses entering the interferometer follow either the first path or the second path, the output of the first and second paths being combined, the transmitter further comprising an optical filter positioned such that photons exiting the interferometer pass through the optical filter, the optical filter being configured to restrict the frequency range of pulses passing through the optical filter and temporally broaden the pulses. |
| US09634769B2 |
Coolerless fiber light source devices for harsh environments
A robust broadband ASE (amplified spontaneous emission) fiber light source device outputs a light beam which is little affected by temperature and radiation. The light source device is a single-pass backward or double-pass backward architecture, and has a coolerless pump laser and temperature compensated bandpass reflector. The light source device may have a high pass filtering element disposed between the wavelength division multiplexer thereof and the optical isolator thereof, so as to compensate the effect of the temperature to the mean wavelength of the light beam. The specific band of the temperature compensated bandpass reflector which reflects the light beam, and the band which the high pass filtering element transmits the light beam are within the band which the ASE unit amplifies the light beam, and the high pass filtering element mainly absorbs the light beam outside the specific band. |
| US09634768B2 |
Optical communication device and method of controlling optical modulator
An optical communication device has a Mach-Zehnder optical modulator; a monitor configured to monitor a modulated light output from the optical modulator; a first controller configured to set a substrate bias voltage or an amplitude of a drive signal applied to the first waveguide of a waveguide pair of the optical modulator to a desired level that provides a first modulation index; and a second controller configured to control a substrate bias voltage or an amplitude of the drive signal applied to the second waveguide of the waveguide pair based upon an output signal from the monitor such that a second modulation index for the second waveguide becomes the same or closer to the first modulation index set for the first waveguide. |
| US09634763B2 |
Tracking frequency conversion and network analyzer employing optical modulation
Tracking frequency conversion employs optical modulation of an optical signal to convert a radio frequency (RF) signal into an intermediate frequency (IF) output signal. A tracking frequency converter includes an optical modulator configured to receive the RF signal and to modulate the optical signal according to the received RF signal. The tracking frequency converter further includes a first square-law photodetector configured to receive the modulated optical signal and another optical signal to convert the received RF signal into the IF output signal. One or both of the modulated optical signal and the other optical signal is a tunable optical signal. |
| US09634756B2 |
Flexible payload and method of reconfiguring flexible payload in case of interference
A flexible payload for a satellite includes a main uplink antenna device configured to receive at least a main uplink signal over a main coverage area; a reconfigurable uplink antenna device configured to receive a complementary uplink signal over a complementary coverage area; a command device configured to define the complementary coverage area of the reconfigurable uplink antenna device, and an agile converting device configured to generate a spectral hole in the bandwidth of the main uplink signal. |
| US09634753B2 |
Data delivery to devices on vehicles using multiple forward links
Data content that is to be utilized, as a whole, at a target device on-board a vehicle is apportioned for delivery onto the vehicle via multiple forward links, each of which is included in a different frequency band and/or used a different protocol. A mapping or selection of a specific portion of the data content for a specific forward link may based on a data content type of the specific portion, as well as on other dynamic or static criteria. The target device may operate on the subsets of the data content as it receives each subset. Thus, time critical/foundational portions of the data content may be delivered using a faster forward link, larger elements of the data content may be delivered using a higher-bandwidth forward link, and/or portions of the data content requiring a higher degree of accuracy may be delivered using a more robust forward link, for example. |
| US09634751B2 |
Method for configuring channel state information reference signal, base station, and access point
A method for configuring a channel state information reference signal includes dividing access points into a first access point set and a second access point set, configuring a first CSI-RS pilot pattern for a user equipment and allocating the pattern to the first access point set, configuring a second CSI-RS pilot pattern and allocating the pattern to the second access point set, and configuring a third CSI-RS pilot pattern and allocating the pattern to an antenna set formed by a first antenna of a first access point in the first access point set and a first antenna of a first access point in the second access point set; and sending non-zero power CSI-RS configuration information to the user equipment, so that the user equipment measures and reports first downlink channel state information, second downlink channel state information, and third downlink channel state information of the antenna set. |
| US09634750B2 |
Beamforming method and apparatus for serving multiple users
A beamforming method is provided. The beamforming method includes determining different beams for pieces of user equipment based on channel information fed back from the pieces of user equipment, predicting beam qualities of the pieces of user equipment for the beams, determining whether the beam qualities satisfy Quality of Service (QoS) for the pieces of user equipment, generating a wide nulling beam by applying wide nulling to a second beam having a side lobe acting as interference against one first beam, when the beam quality of the first beam does not satisfy the QoS; predicting beam qualities for the beams including the wide nulling beam instead of the second beam, and simultaneously communicating with the user equipment through the beams including the wide nulling beam instead of the second beam, when the beam qualities for the beams including the wide nulling beam instead of the second beam satisfy the QoS. |
| US09634748B2 |
Method and apparatus for determining precoding matrix indicator, user equipment, and base station
A method and an apparatus determine a precoding matrix indicator user equipment and a base station. The method includes: determining a precoding matrix indicator PMI where the PMI corresponds to a precoding matrix W, and the precoding matrix W satisfies a first condition, a second condition or a third condition; and sending the PMI to a base station. Embodiments of the present invention further provide a corresponding apparatus, and the corresponding user equipment and base station. Technical solutions provided in the embodiments of the present invention can effectively control a beam, especially a beam shape and a beam orientation, in a horizontal direction and a perpendicular direction. |
| US09634747B2 |
Apparatus and method of processing signal, and recording medium
Disclosed are an apparatus and a method of processing a signal, and a recording medium. The apparatus for processing a signal includes: an estimating unit configured to estimate a first Signal-to-Interference plus Noise power Ratio (SINR) of a reception signal based on transmission path information based on a result of an estimation of a plurality of transmission paths and noise power notified from a wireless reception device; a signal processing unit configured to generate a first modulation symbol by modulating the information bit obtained based on a first modulation order and a first coding rate determined based on the first SINR on a basis of the first modulation order, and a perturbation addition processing unit configured to search for a perturbation vector based on the first modulation symbol generated for each of the plurality of transmission paths, and add the perturbation vector to the first modulation symbol. |
| US09634746B2 |
Method and apparatus for transceiving data in a MIMO system
The present invention relates to a method and apparatus for transceiving data. A method in which a transmitting terminal transmits data to a receiving terminal in a MIMO system according to one embodiment of the present invention comprises the following steps: generating a data field containing the data; generating a signal field containing information on the data field; generating a data frame containing the data field and the signal field; and transmitting the data frame to the receiving terminal. According to the present invention, an end of the frame being transmitted is accurately notified to the receiving terminal in a communication system in which the frame is transmitted using MIMO, thereby decoding the frame in a more efficient manner at the receiving terminal. |
| US09634744B2 |
Sparsity enhanced mismatch model for heterogeneous networks with doubly-selective fading channels
A deterministic mismatch model called Sparsity Enhanced Mismatch Model-Reverse discrete prolate spheroidal sequence which leads to a two stage transceiver design that outperforms precoding only strategy incorporating norm ball mismatch modeling. The inherent sparsity in the channel is brought forth by modeling the channel using a basis expansion model where discrete prolate spheroidal sequence is used as a basis. The sparsity enhanced mismatch model reverse discrete prolate spheroidal sequence disclosed herein better accounts for the channel state information estimate mismatch compared to the norm ball mismatch. The Sparsity Enhanced Mismatch Model-Reverse based transceiver system, which includes a two-stage precoder and decoder, allows the transceiver to utilize higher transmit power without violating the interference constraint placed at the victims, resulting in enhanced performance in the communication link. |
| US09634738B2 |
Hybrid power line/wireless appliance automation system, device, and power monitoring method utilizing the same
The present invention discloses a hybrid power line/wireless appliance automation system for interfacing between at least one electric power distribution circuit and at least one electronic device, a power line communication device, and a power monitoring method using the same. Each power line communication device can be communicatively interconnected via power line communication and/or wireless communication. A threshold value of each power line communication device is dynamically adjusted by a host device via wired or wireless connection, so as to determine whether to continuously supply or turn off power to an electronic device coupled to the power line communication device. The present invention may be implemented/integrated to existing household electric power network without the need for additional physical data network infrastructure/lines, therefore is suitable to be applied in an intelligent home management system. |
| US09634735B2 |
Magnetic antenna, and RF tag and board mounted with the RF tag
The present invention relates to an RF tag comprising a magnetic antenna for transmitting and receiving information using an electromagnetic induction method, and an IC mounted to the magnetic antenna, wherein the magnetic antenna comprises a magnetic core and a plurality of coils formed on the magnetic core; the coils each have an inductance L1 satisfying the specific relational formula, and are connected in parallel to each other in an electric circuit and disposed in series on the magnetic core; and a combined inductance L0 of the magnetic antenna satisfies the specific relational formula. The RF tag of the present invention is used as a magnetic antenna for information communication using a magnetic field component which is capable of satisfying both reduction in size and improvement in communication sensitivity. |
| US09634731B2 |
Wireless power transmitter
Disclosed is a wireless power transmitter. The wireless power transmitter for transmitting power to a wireless power receiver in a wireless scheme, includes a transmission circuit unit converting power supplied from a power supply unit into power having a frequency for resonance; a transmission induction coil coupling the converted power; and a transmission resonance coil disposed adjacent to the transmission induction coil to transfer the coupled power from the transmission induction coil to the wireless power receiver using the resonance, wherein the transmission circuit unit is vertically spaced apart from the transmission resonance coil. |
| US09634729B2 |
Demodulator for near field communication, near field communication device, and electronic device having the same
A demodulator for a near field communication (NFC) includes a first rectifier, a shifting rectifier, a field monitor and an edge detector. The first rectifier receives an antenna voltage through a first power terminal and a second power terminal, rectifies the antenna voltage and provides a first rectified signal to a first node. The shifting rectifier is enabled in response to an enable signal, receives the antenna voltage through the first power terminal and the second power terminal, increases a direct current (DC) level of the antenna voltage, rectifies the increased DC-level antenna voltage and provides a shifted rectified signal to the first node. The field monitor receives the antenna voltage through the first power terminal and the second power terminal, monitors a magnitude of the antenna voltage and generates the enable signal which is activated when the magnitude is smaller than a reference value. |
| US09634728B2 |
Contactless connector
A contactless connector includes an insulative housing having a mating interface configured to be coupled to a connector interface of an electronic device. The housing can be reversibly coupled to the connector interface in a first orientation or in a second orientation oriented 180 degrees relative to the first orientation. A communication circuit board is held within the housing that includes a first connector communication chip and a second connector communication chip configured to define wireless communication channels with corresponding device communication chips of the electronic device in either orientation. A sensor senses the orientation of the housing relative to the connector interface of the electronic device to determine if the housing is in the first orientation or in the second orientation. The mode of operation of the first and second connector communication chips is controlled based on the sensed orientation of the housing. |
| US09634723B1 |
Communication between photovoltaic devices on a shared power line
An electric system, method, and computer-readable medium facilitate shared access to a shared power line for communication using a PLC protocol. The electric system, method, and computer-readable medium may determine when the shared power line is available for a transmission, allocate unicast transmission time slots to each of a plurality of inverters, transmit a multicast message requesting that each of the plurality of inverters communicate information during its allocates transmission time slot, determine whether a first inverter in the plurality of inverters did not communicate using the shared power line during its allocated unicast transmission time slot, and if the first inverter did not communicate information during its allocated unicast transmission time slot, transmit with the line interface a jam signal during the first inverter's unicast transmission time slot. |
| US09634719B2 |
Methods of operating and implementing wireless OTFS communciations systems
Computerized wireless transmitter/receiver system that automatically uses combinations of various methods, including transmitting data symbols by weighing or modulating a family of time shifted and frequency shifted waveforms bursts, pilot symbol methods, error detection methods, MIMO methods, and other methods, to automatically determine the structure of a data channel, and automatically compensate for signal distortions caused by various structural aspects of the data channel, as well as changes in channel structure. Often the data channel is a two or three dimensional space in which various wireless transmitters, receivers and signal reflectors are moving. The invention's modulation methods detect locations and speeds of various reflectors and other channel impairments. Error detection schemes, variation of modulation methods, and MIMO techniques further detect and compensate for impairments. The invention can automatically optimize its operational parameters, and produce a deterministic non-fading signal in environments in which other methods would likely degrade. |
| US09634718B2 |
Architectures and methods related to insertion loss reduction and improved isolation in switch designs
Architectures and methods related to insertion loss reduction and improved isolation in switch designs. In some embodiments, a switching architecture can include a switch network having one or more switchable radio-frequency (RF) signal paths, where each path contributes to a parasitic effect associated with the switch network. The switching architecture can further include a parasitic compensation circuit coupled to a node of the switch network. The parasitic compensation circuit can be configured to compensate for the parasitic effect of the switch network. |
| US09634711B2 |
Universal device-holding case construction with magnetic fastener feature
A case construction for an electronic device having a select feature function operable via a posterior device portion includes a device-holding panel for removably retaining an electronic device and a case construction for selectively enabling (a) device-holding panel access and (b) device-holding panel encasement. The device-holding panel includes an anterior device-support portion, a posterior case interface portion, at least one feature-enabling edge, and a device retention mechanism for retaining the electronic device in anterior adjacency to the anterior device-support portion. The case construction includes an anterior case portion, a posterior case portion, and an anterior-to-posterior junction. The anterior case portion is pivotal relative to the posterior case portion via the anterior-to-posterior junction for selectively uncovering and covering the anterior device-support portion. The device-holding panel is magnetically attractive and fastenable to the case construction via first and second magnetically attractive material constructions embedded within the device-holding panel and case construction. |
| US09634710B2 |
Electronic device and method for making same
An electronic device includes a housing and a base plate. The housing includes a frame. The frame includes a metallic member and a plastic member. The plastic member is connected to the metallic member to cooperatively form the frame. The base plate includes a number of connecting tabs. The connecting tabs are fixedly attached to an inner surface of the frame. |
| US09634707B2 |
Mobile device case and armband with fluid chamber
A case for a mobile device including a body with a fluid chamber configured to retain fluid therein. An armband for a mobile device includes a band with a fluid chamber configured to retain fluid therein. The fluid chamber may serve to cushion the mobile device or wearer's arm when in use. |
| US09634704B2 |
FM analog demodulator compatible with IBOC signals
A method includes: receiving an FM radio signal including an analog-modulated portion; digitally sampling an analog-modulated portion of the radio signal to produce a plurality of samples; using a ratio between an average magnitude and an RMS magnitude of a block of the samples to compute a signal quality metric; detecting sum and difference components of the baseband multiplex signal content; using the baseband content to produce an output signal; and blending the output signal from stereo to monaural as the signal quality metric falls below a threshold value. |
| US09634703B2 |
Low power encoded signal detection
A method and receiver for detecting a signal wherein the signal is encoded the signal with a pair of spaced predetermined frequencies and wherein energy is detected in each of the pair of predetermined frequencies and in a predetermined frequency between the pair of predetermined frequencies. Energy detected in each of the pair of predetermined frequencies is compared with the energy detected in the predetermined frequency between the pair of predetermined frequencies. The detecting includes passing the encoded signal through narrow band filters, each one of the filters being tuned to a corresponding one of the pair of predetermined frequencies and the predetermined frequency between the pair of predetermined frequencies. |
| US09634702B2 |
Multiband filter for non-contiguous channel aggregation
Methods and apparatus, including computer program products, are provided for receivers. In one aspect there is provided an apparatus. In some example embodiments, there is provided an apparatus. The apparatus may include a first N-path filter configured with at least a first passband, wherein the first N-path filter is coupled to a radio frequency input port providing at least a first carrier aggregation signal, a second carrier aggregation signal, and an interfering signal; a second N-path filter configured with at least a second passband, wherein the second N-path filter is coupled to the radio frequency input port providing at least the first carrier aggregation signal, the second carrier aggregation signal, and the interfering signal; and a combiner configured to subtract a first output of the first N-path filter from a second output of the second N-path filter. Related apparatus, systems, methods, and articles are also described. |
| US09634700B2 |
Distributed noise shaping apparatus
Provided are, among other things, systems, apparatuses methods and techniques for attenuating the level of unwanted noise and/or distortion in a particular frequency band, without similarly attenuating the level of a desired signal in the same frequency band. One such apparatus includes a distributed network comprising a plurality of reactive impedance segments and gain cells that form transmission paths, over which continuous and quantized versions of an input signal propagate before combining with the input signal itself. |
| US09634699B2 |
Apparatus for controlling wide-band signal transmission gain in wireless communication systems and signal processing method of the same
Disclosed are an apparatus for controlling a wide-band signal transmission gain, which differently applies a transmission gain by the unit of an intermediate frequency (IF) at a transmitting side of a wide-band multi-IF wireless communication system which can convert multiple baseband digital signals into IF signals and thereafter, multiplex and simultaneously transmit the converted IF signals and a signal processing method of the same. |
| US09634691B2 |
Transmitting system and method of transmitting digital broadcast signal in transmitting system
A transmitting system and a method of transmitting digital broadcast signal are disclosed. The method of transmitting digital broadcasting signal in a transmitter includes multiplexing a specified number of mobile data packets, a first scalable number of mobile data packets, and a second scalable number of main data packets, interleaving mobile data in the mobile data packets and main data in the main data packets, transmitting the interleaved mobile and main data during a slot, wherein the data group includes a plurality of first blocks, each first block including a plurality of data segments, specified block of the plurality of first blocks including the mobile data, known data sequence, trellis initialization data and RS parity bytes inserted in pre-determined position of the data group, wherein the data group includes a plurality of regions, wherein the last region includes the first scalable number of mobile data packets. |
| US09634688B2 |
Integrator, delta-sigma modulator, and communications device
An integrator including: a resistive element connected to an input terminal; an operational amplifier configured to receive, through the resistive element, an input signal that has been supplied to the input terminal; and a voltage regulator circuit connected to an intermediate node between the resistive element and the operational amplifier. The voltage regulator circuit has a first current source connected to the intermediate node, and a switch connected between the intermediate node and the first current source and selectively turning ON or OFF. |
| US09634684B2 |
Method and apparatus for encoding analog signal into time intervals
Method for encoding analog signal into time intervals wherein a generation of time intervals using a time encoding machine. A signal of a constant value is held during a generated time interval on a time encoding machine input by the use of a sample-and-hold circuit, while the constant value of the signal held during the generated time interval represents an instantaneous value of the analog signal at the end of a generation of a previous time interval. Apparatus for encoding analog signal into time intervals comprising a time encoding machine, and a sample-and-hold circuit. The signal is provided to an input of the sample-and-hold circuit, whose output is connected to an output of the time encoding machine. The output of the time encoding machine is connected to an output of the apparatus, and to a control input of the sample-and-hold circuit. |
| US09634677B2 |
Clock generator and integrated circuit using the same and injection-locked phase-locked loop control method
A control technique for an injection-locked phase-locked loop (ILPLL) includes the following steps: providing the ILPLL with a sampling clock and an injection clock for an integral path and a proportional path of the ILPLL, respectively; making a change in the power level of the injection clock to get the phase error of the integral path of the ILPLL; and controlling the phase difference between the sampling clock and the injection clock based on the phase error of the integral path of the ILPLL. |
| US09634670B2 |
Frequency divider and related electronic device
A frequency divider may include the following elements: a first inverter, a second inverter, and a third inverter, which are connected in a ring structure, wherein the second inverter is connected to an output terminal of the frequency divider; a fourth inverter connected to a first input terminal of the frequency divider and to a power supply terminal of the first inverter; a fifth inverter connected to a second input terminal of the frequency divider and to a power supply terminal of the third inverter; a first transistor connected to the second input terminal of the frequency divider and to a ground terminal of the first inverter; and a second transistor connected to the first input terminal of the frequency divider and to a ground terminal of the third inverter. The second inverter, the fourth inverter, and the fifth inverter may receive a power supply voltage. |
| US09634667B2 |
Integrated circuit device with programmable analog subsystem
An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks. |
| US09634666B2 |
Push-pull driver, a transmitter, a receiver, a transceiver, an integrated circuit, a method for generating a signal at an output
A push-pull driver according to an example includes a push stage coupled via a first coupling capacitor to an output of the push-pull driver and a pull stage coupled via a second coupling capacitor to the output of the push-pull driver. Using an example may allow to improve a trade-off between saving energy, an overall complexity of a corresponding implementation, a robust and reliable operation and other parameters and design goals. |
| US09634665B2 |
Level shifters and integrated circuits thereof
An integrated circuit including a first level shifter configured to receive a first input signal and a first power supply signal, and to output a first output signal. The integrated circuit further includes a first inverter configured to receive the first output signal, and to output a first inverter signal. The integrated circuit further includes a second level shifter configured to receive a second input signal and a second power supply signal, and to output a second output signal, wherein a voltage level of the second power supply signal is different from a voltage level of the first power supply signal. The integrated circuit further includes a second inverter configure to receive the second output signal, and to output a second inverter signal. The integrated circuit further includes an output buffer configured to receive the first inverter signal and the second inverter signal, and to output a buffer output signal. |
| US09634653B2 |
Method and apparatus for a brown out detector
The disclosure provides a detector that includes a pre-charge circuit. The pre-charge circuit receives a supply voltage. A pre-charged comparator is coupled to the pre-charge circuit and receives the supply voltage. The pre-charged comparator generates a transition signal at a transition node. A slope of the transition signal is greater than a slope of the supply voltage. A first diode connected transistor receives the supply voltage. A first capacitor is coupled to the first diode connected transistor. An inverter is coupled to the first diode connected transistor and generates an enable signal when the supply voltage is below a threshold voltage. |
| US09634652B1 |
Method and apparatus for configuring delay lines
Embodiments include an apparatus including: a first delay line and a second delay line, wherein the first delay line is configured to receive a clock signal and output a first delayed signal, and wherein the second delay line is configured to receive the first delayed signal and output a second delayed signal; a first control circuit configured to (i) apply a first delay select to the first delay line and the second delay line such that the second delayed signal is delayed with respect to the clock signal by a half-clock period, and (ii) apply a second delay select to the first delay line such that the first delayed signal is delayed with respect to the clock signal by the half-clock period; and a second control circuit configured to control a third delay line based on the first delay select and the second delay select. |
| US09634646B1 |
Mismatch calibration of capacitive differential isolator
Embodiments of the present disclosure may provide a method of calibrating an isolator system. The method may comprise the steps of driving a common signal to a pair of input terminals of the isolator system; measuring differences in signals at output terminals of the isolator system; and varying impedance of impedance elements connected between the output terminals and a center-tap terminal of the isolator system until a mismatch at the output terminals is minimized. |
| US09634645B2 |
Integration of a replica circuit and a transformer above a dielectric substrate
A particular device includes a replica circuit disposed above a dielectric substrate. The replica circuit includes a thin film transistor (TFT) configured to function as a variable capacitor or a variable resistor. The device further includes a transformer disposed above the dielectric substrate and coupled to the replica circuit. The transformer is configured facilitate an impedance match between the replica circuit and an antenna. |
| US09634641B2 |
Electronic module having an interconnection substrate with a buried electronic device therein
An electronic device includes: a first substrate, a first function part in its first surface, an adhesive layer on the first surface so as to surround the first function part, a second substrate bonded to the first substrate by the adhesive layer to form a gap between the first and second substrates, a first via interconnection piercing the first substrate to connect the first surface and an opposite second surface, a second via interconnection piercing the second substrate to connect a third surface of the second substrate opposite to the first substrate and a fourth surface opposite to the third surface, a first terminal provided on the second surface and connected to the first via interconnection, a second terminal provided on the fourth surface and connected to the second via interconnection. The first function part is connected to at least one of the first and second via interconnections. |
| US09634638B2 |
Control device, automatic matching method for antennas, and wireless device
A control device includes a power detector that detects a power of a signal transmitted by an antenna, a transmitting power of the signal fluctuating due to transmit power control; and a controller that adjusts a setting value of a variable matching circuit in such a way that the power increases based on a result of comparison of a reference value with a detected power of the power detector, that detects fluctuation in the transmitting power based on a temporal change in the detected power, and that corrects the reference value based on the fluctuation in the transmitting power. |
| US09634637B2 |
Method for performing dynamic impedance matching and a communication apparatus thereof
Method for performing dynamic impedance matching and communication apparatus thereof are provided. With respect to an operating band of an impedance matching circuit of a communication device, a first number of times of tuning are performed on a first element of an impedance matching circuit, and a second number of times of tuning are performed on a second element of the impedance matching circuit, wherein the first number is different from the second number. |
| US09634636B2 |
Non-contact power transmission device
A non-contact power transmission device equipped with a ground-side device and a vehicle-side device. The ground-side device has a primary-side coil to which alternating-current power is input. The vehicle-side device includes a secondary-side coil, a battery, a secondary-side matching device, and a charging device. The secondary-side coil receives alternating-current power from the primary-side coil in a non-contact manner. The secondary-side matching device is provided between the secondary-side coil and the battery, and has a predetermined fixed inductance and fixed capacitance. The charging device has a switching element that performs a switching operation with a prescribed cycle. The charging device adjusts the duty ratio of the switching operation in accordance with the impedance of a load. |
| US09634634B2 |
Apparatus and methods for high voltage variable capacitor arrays with drift protection resistors
Apparatus and methods for high voltage variable capacitors are provided herein. In certain configurations, an integrated circuit (IC) includes a variable capacitor array and a bias voltage generation circuit that biases the variable capacitor array to control the array's capacitance. The variable capacitor array includes a plurality of variable capacitor cells electrically connected in parallel between a radio frequency (RF) input and an RF output of the IC. Additionally, each of the variable capacitor cells can include a cascade of two or more pairs of anti-series metal oxide semiconductor (MOS) capacitors between the RF input and the RF output. The pairs of anti-series MOS capacitors include a first MOS capacitor and a second MOS capacitor electrically connected in anti-series. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the variable capacitor cells. |
| US09634631B2 |
Control system for a power amplifier
An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop delays the first signal, such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The apparatus may be included in a satellite. |
| US09634630B2 |
Amplifier
An amplifier (1) is provided, in particular, wideband amplifier with an input (4) and an output (5) comprising a first amplifier stage (2) and a second amplifier stage (3), wherein the first amplifier stage (2) has an active power splitter with at least one injection point, wherein this injection point corresponds to the input (4) of the amplifier, and at least two discharge points (9a, 9b), wherein this active power splitter is formed according to a traveling wave amplifier principle and the second amplifier stage (3) has at least two injection points (11a, 11b) and at least one discharge point, wherein this discharge point corresponds to the output (5) of the amplifier and is formed as a power coupler. It is essential that the second amplifier stage (3) is formed as a power coupler, wherein this power coupler is formed according to the principle of a reactively matched amplifier. |
| US09634627B2 |
Amplification circuit and analog/digital conversion circuit
According to one embodiment, an amplification circuit includes a differential amplifier and a feedback circuit. The differential amplifier includes a sampling circuit that samples a first voltage which is a difference between an adjustment voltage supplied to a first terminal and a first input voltage, and a second voltage which is a difference between the adjustment voltage and a second input voltage. The differential amplifier amplifies the first voltage to output a first voltage signal and amplifies the second voltage to output a second voltage signal. The feedback circuit detects a common mode voltage of the first voltage signal and the second voltage signal, and adjusts the adjustment voltage which is supplied to the first terminal in accordance with the common mode voltage. |
| US09634626B2 |
Instrumentation amplifier
An instrumentation amplifier includes: a capacitive feedback closed-loop amplifier, an input capacitor charging module, a feedback capacitor discharging module, a noise separation module and a logic controller. The capacitive feedback closed-loop amplifier includes a fully differential operational amplifier, a first input capacitor, a second input capacitor, a first feedback capacitor and a second feedback capacitor. The input capacitor charging module is configured to charge the first input capacitor and the second input capacitor periodically. The feedback capacitor discharging module is configured to discharge the first feedback capacitor and the second feedback capacitor periodically. The noise separation module is configured to separate a noise from a signal using a chopping modulation technology. The logic controller is connected to the input capacitor charging module, the feedback capacitor discharging module and the noise separation module to control the modules to operate. |
| US09634619B2 |
Power amplifier bias circuit having parallel emitter follower
Improved power amplifier (PA) bias circuit having parallel emitter follower. In some embodiments, a bias circuit for a PA can include a first bias path implemented to couple a base node of an amplifying transistor and a supply node, with the first bias path being configured to provide a base bias current to the base node. The PA can further include a second bias path implemented to be electrically parallel with the first bias path between the base node and the supply node. The second bias path can be configured to provide an additional base bias current to the base node under a selected condition. |
| US09634616B2 |
Single-end amplifier and noise cancelling method thereof
A single-end amplifier includes: a noise cancelling circuit, coupled to a power supply, configured to receive a power signal and to cancel a part of ripples and noises in the power signal to generate an initial signal; an amplifying circuit, configure to receive the initial signal at a first end of the amplifying signal, and to amplify the initial signal to generate a first signal at a second end; and a first transmitting circuit, configured to receive the power signal and to generate a second signal at the second end of the amplifying circuit. The first signal and the second signal are superimposed and outputted to cancel most part of the ripples and noises in the power signal. The noise cancelling circuit includes a first capacitor and a first choke coil. |
| US09634615B1 |
Multi-band Doherty amplifier device and method therefor
A Doherty amplifier device operable over multiple frequency bands includes a controller that, in some embodiments, is configured to output a carrier bias signal to a first amplifier and a peaking bias signal to a second amplifier as part of a first operating configuration associated with a first frequency band, and output the peaking bias signal to the second amplifier and the carrier bias signal to a third amplifier as part of a second operating configuration associated with a second frequency band. In some embodiments, the controller is configured to select an impedance inverter configuration associated with a respective frequency band. At least one impedance inverter configuration includes a compound impedance inverter including two or more impedance inverters coupled in series with at least one node between the two or more impedance inverters coupled to an output of a third amplifier. |
| US09634614B2 |
Distributed power amplifier circuit
A distributed power amplifier circuit is disclosed. The distributed power amplifier circuit comprises an amplifier arrangement comprising a plurality of sub amplifiers, each having an output port for outputting an output signal of the sub-amplifier and an output combiner network for combining the output signals from the sub amplifiers. The output combiner network includes, for each sub amplifier, an associated auto transformer operatively connected to the output port of the sub amplifier for receiving the output signal of the sub amplifier. The auto transformers each have a first interconnection terminal and a second interconnection terminal. The auto transformers are operatively connected in series via the interconnection terminals, thereby forming a chain of auto transformers having a first end and a second end, wherein the first end is arranged to be connected to an antenna. |
| US09634607B2 |
Low noise and low power voltage-controlled oscillator (VCO) using transconductance (gm) degeneration
Certain aspects of the present disclosure generally relate to voltage-controlled oscillators (VCOs) using a lowered or an adjustable negative transconductance (−gm) compared to conventional VCOs. This −gm degeneration technique suppresses the noise injected into an inductor-capacitor (LC) tank of the VCO, thereby providing lower signal-to-noise ratio (SNR) for a given VCO voltage swing, lower power consumption, and decreased phase noise. One example VCO generally includes a resonant tank circuit, an active negative transconductance circuit connected with the resonant tank circuit, and a bias current circuit for sourcing or sinking a bias current through the resonant tank circuit and the active negative transconductance circuit to generate an oscillating signal. The active negative transconductance circuit includes cross-coupled transistors and an impedance connected between the cross-coupled transistors and a reference voltage. |
| US09634605B2 |
Motor drive controller
A motor drive controller includes: a phase current detection circuit including: an RC network circuit in which a resistor and a capacitor are connected in series, the RC network circuit being configured to be connected in parallel with one or more coils of each phase of a motor; and a filter circuit that smooths a signal based on a voltage signal across the capacitor, wherein the phase current detection circuit generates a DC voltage signal that corresponds to a change in a value of a phase current flowing in the coils; a motor driver that drives the motor by applying a voltage to each phase of the motor; and a controller that receives the DC voltage signal from the phase current detection circuit and controls the motor driver based on the DC voltage signal. |
| US09634602B2 |
Three-phase inverter apparatus and control method thereof
A three-phase inverter apparatus includes an inverter main circuit in three phases having a plurality of semiconductor switching devices to convert a DC voltage into the three-phase AC voltages to be supplied to a pulsating load, a current detector configured to detect first and second output currents from the inverter main circuit, a voltage detector configured to detect first to third output voltages from the inverter main circuit, and a control circuit configured to generate a command compensation value using a value obtained by dividing a current RSM obtained from the first and second output currents by an average value of the current RSM, and generate the compensated control command for each of the switching devices by multiplying the command compensation value by a corresponding one of control commands each of which is generated for a corresponding one of the switching devices, using the first to third output voltages. |
| US09634599B2 |
High speed ratio permanent magnet motor
A permanent magnet motor having a high speed ratio may remove the need for a gearbox or multiple windings in the permanent magnet motor. A gearbox or a multiple-winding configuration stator may thus be omitted. |
| US09634597B2 |
Aircraft engine and method for operating an aircraft engine
An aircraft engine includes at least one electrical apparatus, which can be driven by a driveshaft in order to generate electrical energy. A hydrodynamic torque converter, with guide blades, which can be adjusted via a mechanism, is arranged between the driveshaft and the electrical apparatus. The guide blades are adjusted as a function of a rotational speed of the driveshaft, wherein the rotational speed of a shaft of the electrical apparatus operated as a generator can be adjusted, essentially within a predefined rotational speed range, via the adjustment of the guide blades. |
| US09634595B2 |
Method and a generator system for operating a generator
The present disclosure relates to a method and a generator system for operating a generator. The method for operating the generator includes exciting the field winding of a rotor of the generator by a first exciter device, driving a second exciter device while operating the generator with the first exciter device, and switching the second exciter device to excite the generator in case the first exciter device feeds to the generator not sufficient energy for operating the generator during a malfunction of the first exciter device. Further, a corresponding generator system is described. |
| US09634591B2 |
System and method for motor control using position sensors
An embodiment method for motor control includes monitoring a plurality of position sensors coupled to a revolving motor. The monitoring includes measuring transition times of respective output patterns produced by the position sensors, the respective output patterns each including at least one transition time that repeats in accordance with each revolution of the motor. The method further includes determining a first revolution period in accordance with the measured transition times. The method also includes determining an elapsed fraction of the first revolution period that has elapsed since a start time of the first revolution period. |
| US09634582B2 |
Detachable generator device
Provided is a detachable generator device which can change the installation location with ease and which can effectively use a solar cell to generate electric power. The detachable generator device includes: a film-like solar cell; and attaching/detaching means for allowing the film-like solar cell to be attached to and detached from an attachment object at an installation location. The attaching/detaching means includes an adhesive film having an attaching/detaching surface which develops Van der Waals force to enable repeated affixation, or an electrostatic chuck for forming an attaching/detaching surface by turning on/off a voltage source connected to an attraction electrode sandwiched between two insulating layers to freely develop electrostatic attraction on a surface of at least one of the insulating layers. |
| US09634581B2 |
Piezoelectric generator for hydraulic systems
The present disclosure generally relates to electrical power generation from a piezoelectric material. A piezoelectric power generator assembly is disclosed including a housing, a piezoelectric transducer located in the housing, and a piston located in the housing, wherein the piezoelectric transducer is configured to generate an electrical charge when contacted by the piston. A piezoelectric power generator assembly is also disclosed including a housing comprising a flowline located within the housing and a piezoelectric transducer located in the housing and disposed about a perimeter of the flowline, wherein the piezoelectric transducer is configured to generate an electrical charge when contacted by a fluid contained in the flowline. A subsea drilling system is disclosed including a subsea blowout preventer stack and a piezoelectric power generator assembly for powering sensors on the blowout preventer stack configured to monitor characteristics of the stack. |
| US09634578B2 |
Current zero crossing in an inverter
Power electronics unit, which comprises a controller and at least one half bridge with a first switching element and with a second switching element, and has a phase current output between the two switching elements, at which phase current output the first switching element and the second switching element can be switched in the push-pull mode for a switching time at a cycle frequency, and at which the controller sets the switching time and/or the cycle frequency as a control variable, in order to provide, at the phase current output, a specified amplitude, frequency and phase position of the phase current in a switching cycle, so that the amplitude, the frequency and the phase position at the phase current output can be predicted at the phase current output for the switching cycle, the polarity of the phase current is used as an observation variable, and the determined switching time for the switching cycle is a function of the direction of the predicted phase current. |
| US09634577B2 |
Inverter/power amplifier with capacitive energy transfer and related techniques
Circuit topologies and control methods for a dc-to-rf converter circuit are described. |
| US09634574B2 |
Electric-power conversion system having inrush current prevention circuit
The number of constituent components is reduced so as to provide a small-size and inexpensive electric-power conversion system. The electric-power conversion system is provided with an inverter circuit (14) connected with the rear stage of an AC power source, a smoothing capacitor (22) connected with the rear stage of the inverter circuit (14) by way of a rectifying device (20), a charging switch (2) that is connected with the front stage of the inverter circuit (14), that inputs an electric quantity based on an output of the AC power source (1) to the inverter circuit (14) when being turned on, and that cuts off an input of the electric quantity to the inverter circuit (14) when being turned off, and an inrush current prevention circuit (7) having an inrush current prevention switch (3) and an inrush current prevention resistor (4) that is connected in series with the rear stage of the inrush current prevention switch (3); the electric-power conversion system is characterized in that the inrush current prevention circuit (7) is connected in parallel with the charging switch (2). |
| US09634570B2 |
Multi-mode power converter and associated control method
A multi-mode power converter and associated method for configuring and controlling a multi-mode power converter. The multi-mode power converter may have a boost operation mode and a buck operation mode. A first transistor is coupled between a switching terminal and a ground, and a second transistor and a third transistor are coupled in series between the switching terminal and an output port of the multi-mode power converter. In the buck mode, an on-resistance of the second transistor is regulated to ensure the multi-mode power converter to operate normally in the buck operation mode. |
| US09634568B2 |
Device for controlling and balancing currents for DC/DC converters
The invention provides a control device for regulating and balancing currents, for DC/DC converters, between first and second voltage sources, the device comprising: n converters (C1, C2, . . . Cn) that are connected in parallel to the first voltage source (11); n inductors (L1, L2, . . . Ln) that have their outlets connected to the second voltage source (R) via n connections; n current sensors (22) that are arranged on respective ones of the connections; and a single regulator system that has its inputs connected to respective ones of the n current sensors (22), and its output connected to the n converters (C1, C2, . . . Cn). |
| US09634567B2 |
Sensor data acquisition system with integrated power management
A microelectromechanical systems (MEMS) sensor with an integrated power management system that performs analog to digital conversion of weak signals is provided. The MEMs sensor can include a switching regulator that steps a supply voltage down to a voltage appropriate for an analog to digital converter (A/D converter). A timing circuit is provided to generate a clock frequency for the switching regulator and the A/D converter such that the clock frequencies are harmonically related. The frequency of the voltage ripples formed by the switching regulator will match the clock frequency provided to the switching regulator. When the sampling frequency of the A/D converter is harmonically related to the voltage ripple frequencies, the aliasing frequency will fall outside a range of frequencies associated with the analog signal. |
| US09634563B2 |
Ramp signal generating method and generator thereof, and pulse width modulation signal generator
A ramp signal generating method and a generator thereof, and a pulse width modulation signal generator are provided. The ramp signal generating method includes following steps: receiving an error signal, wherein the error signal relates to an output voltage of a power converter; generating an error delayed signal according to the error signal; and providing a ramp signal according to the error signal and the error delayed signal. The ramp signal is phase leading and inverting compared to the error signal. The ramp signal serves to improve a response speed of the power converter. |
| US09634560B2 |
Voltage modulator
A voltage modulator (400) comprises a multi-level switched capacitor modulator (44) connected in parallel with a switched voltage regulator (42). An output of the multi-level switched capacitor modulator and an output of the switched voltage regulator are combined, or both connected to an output node, to generate an output voltage. The voltage modulator has an input node to receive at least one input signal and further comprises a control unit (46) arranged to control the switched voltage regulator and the multi-level switched capacitor modulator such that the output voltage follows the input signal. |
| US09634558B2 |
Negative charge pump feedback circuit
The present invention discloses a negative charge pump feedback circuit, wherein the feedback circuit is connected between an AND gate and the output terminal of the negative charge pump, and a clock signal is connected to the negative charge pump through the AND gate and under the control of the feedback signal, with the feedback circuit including a switch-capacitor circuit and a comparator; a first terminal of a first capacitor of the switch-capacitor circuit is connected to the output terminal of the negative charge pump through a first switch, and grounded through a second switch; a first terminal of a second capacitor is connected to a second terminal of the first capacitor, grounded though a third switch, and connected to the comparator though a fourth switch; an adjustable capacitor is connected in parallel to both terminals of the second capacitor; a positive-phase input terminal of the comparator is connected to a reference voltage. The switch-capacitor circuit is made to switch constantly between two states by the control of four control signals over the four switches, achieving voltage division and positive/negative voltage conversion simultaneously. The present invention can reduce the circuit area, increase the feedback speed, and reduce the output voltage ripple of the charge pump. |
| US09634550B2 |
Inertial drive actuator
An inertial drive actuator includes a displacement unit which generates a minute displacement in a first direction, and in a second direction, a coil which generates a magnetic flux, a movable object which has a surface facing at least one surface of the coil, and a first yoke which converges the magnetic flux generated by the coil, at a predetermined position, a detecting unit which detects an electric signal of the coil, reflecting a change in the magnetic flux near the coil based on a positional relationship of the movable object and the coil, and a judging unit which judges a position of the movable object, and the inertial drive actuator drives the movable object by controlling a frictional force acting on the movable object, by controlling the magnetic flux generated by the coil, and the coil carries out generation of the magnetic flux and detection of the magnetic flux. |
| US09634548B2 |
Method for manufacturing an armature winding for an electric machine
In this method for manufacturing an armature winding for an electric machine, a rectangular conductor wire is wound helically by bending and shaping linking portions between rectilinear portions and coil ends to set angles while feeding the rectangular conductor wire, by repeating steps in which the rectangular conductor wire is fed by a set amount of feeding, the rectangular conductor wire is gripped and fixed by first through fourth chucks, the rectangular conductor wire is bent by pressing a first former near a root of the rectangular conductor wire, and gripping and fixing of the rectangular conductor wire by the first through fourth chucks is released. |
| US09634545B2 |
Component for an electric machine
An electric machine component includes a rotor assembly having at least one claw pole member having a number of pole members, an outer fan member support surface, and a central hub projecting from the outer fan member support surface. The central hub includes an anti-rotation member and a substantially planar bearing surface. |
| US09634543B2 |
Energy transforming unit for distance measurement sensor
The subject invention relates to an air spring (1) with a distance measurement sensor (100), an energy transforming unit (200), a first mounting element (10) being adapted for being mounted to a first vehicle portion (2) and a second mounting element (20) being adapted for being mounted to a second vehicle portion (3). An air volume (50) is arranged between the first mounting element and the second mounting element. The energy transforming unit is adapted to transform a transition of the air spring from a first state (s1) of the air spring to a second state (s2) of the air spring into electrical energy and to provide the generated electrical energy to the distance measurement sensor. The energy transforming unit is arranged in the air volume (50) of the air spring. |
| US09634541B2 |
Apparatus to provide motor backdrive resistance
Apparatus to provide motor backdrive resistance are described. An example apparatus described herein includes a brake to engage an output shaft of a motor. The example apparatus also includes a brake release arm operably coupled to the brake. A reaction arm is fixed relative to the brake release arm and operatively coupled to the motor. The reaction arm causes the brake to disengage the output shaft of the motor in response to a reaction torque of the motor. |
| US09634534B2 |
Brushless motor
A brushless motor includes a stator as an armature where a plurality of coils is housed and a rotor as a magnetic exciter having a permanent magnet, wherein an end portion of the coil housed in a slot of a stator stack is inserted into a wire binding board having a wire binding pattern of the coil, the end portion of the coil is soldered to a land of the wire binding board, and the wire binding board and a circuit board are electrically conducted to each other through an connecting terminal. |
| US09634529B2 |
Electrical machine
A method of making generally symmetrical lamination stacks for electrical machines comprises producing generally symmetrical pole tips from alternating asymmetrical pieces that each have an additional layer in the asymmetrical portion. With the alternating asymmetrical pieces combined, the resulting pole tip is generally symmetrical with a larger possible pole tip width compared with currently-used interleaved stamping techniques. |
| US09634528B2 |
Efficient electric machine
An electric machine having a stator and a rotor which is mounted so as to be rotatable about a rotor axis and has a rotor body, in which at least two permanent magnets are arranged in receptacles, a first of which component magnets is associated with a first set of permanent magnets, and a second of which component magnets is associated with a second set of permanent magnets. The permanent magnets of the first set differ from the permanent magnets of the second set with respect to the material composition, In particular to the magnetic properties, and wherein at least one permanent magnet of the first or second set or at least one composite body has a contour, the cross-sectional face of which, being located perpendicularly with respect to the longitudinal axis, decreases within the respective receptacle towards that end thereof which is radially further to the outside. |
| US09634527B2 |
Electrical machine with a high level of efficiency
An electrical machine is provided, in particular an electric motor having a stator and also a rotor which is mounted such that it can rotate about a rotor axis and has a rotor body, wherein permanent magnets are arranged in holders of the rotor body. The permanent magnets being composed of a mixed material, wherein the mixture is set in such a way that the mixed material has a remanence field strength Br of between 0.6 Tesla and 1 Tesla and a coercive field strength Hcj of between 1300 and 2500 KA/m. Permanent magnets or composite bodies can be arranged in holders, and the permanent magnets or composite bodies can have a contour, the cross-sectional area of said contour which is situated perpendicular to the longitudinal axis being reduced within the respective holder in the direction of the radially further outer end of said holder. |
| US09634519B2 |
Adjustable and portable mounting system for a tablet computing device and solar based charging system
An adjustable and portable mounting system for a tablet computing device and solar based charging system is described. An example mounting system for a tablet computing device includes a tablet enclosure with a plurality of gripping portions adjustable to hold tablets with different sizes and shapes, and each gripping portion is configured to grip a corner of the tablet computing device. The mounting system further includes an adjustable solar panel support, which is pivotally attached to the tablet enclosure and where a solar panel placed within the support can be configured to provide trickle charging to the tablet and to orient 360 degrees about three axes of rotation. The mounting system also includes a table stand, which is mounted to the tablet enclosure and provides support of the tablet computing device on a flat surface with a wide range of viewing angles. The mounting system also includes a connector configured to couple to a tripod stand mount, or a similar device. |
| US09634518B2 |
Method and system for supplying electrical energy from a battery power supply unit to a heating element
In order to improve the performance of a battery power supply unit for a bicycle electronic device at low atmospheric temperature, when its temperature is less than or equal to a lower temperature threshold, electrical energy is supplied by the power supply unit to a heating element thermally coupled with the power supply unit that, in this way, self-heats. Part of the electrical energy of the power supply unit can be simultaneously supplied to the electronic device. |
| US09634506B2 |
Multi-battery charging circuit and charging method thereof
A multi-battery charging circuit is described and it includes an electric power detecting unit for detecting remaining amount of electric power of each battery; a charging deciding unit provided with a first amount of electric power threshold and for comparing the remaining amount detected with the first threshold; and a charging unit for charging a plurality of batteries with a first strategy in a first time period, and with a second strategy in a second time period when the remaining amount of electric power of one or more of the batteries is equal to a second amount of electric power threshold, and with a third strategy in a third time period when the remaining amount is equal to a third amount of electric power threshold. |
| US09634504B2 |
Battery charging graphical user interface for wireless power transfer
An apparatus for charge management for an electric vehicle is disclosed. A system and method also perform the functions of the apparatus. The apparatus includes a battery status module that displays a battery charge status indicator on an electronic display of an electric device. The battery charge status indicator is for a battery providing power to the electric device. The apparatus includes a charging target module that displays a charging target on the electronic display. The charging target is related to the battery charge status indicator and indicates a desired charge level for the battery. The apparatus includes a target adjustment module that adjusts the charging target based on a predicted next battery charging and battery usage, wherein the battery charging and usage are based on a schedule and/or a planned route. |
| US09634502B2 |
Fast battery charging through digital feedback
Methods and apparatus for charging a battery of a portable device are disclosed, including receiving, by a charging component, an amount of voltage on a power bus connectable to an external device, wherein the charging component charges the battery with the amount of voltage received. The methods and apparatus include authenticating, by an authentication component, the portable device with the external device via a plurality of signal lines, wherein the authentication component is configured to transmit one or more authentication signals on one or more of the plurality of signal lines. The methods and apparatus include transmitting, by a configuration component, a modified voltage signal and a modified current signal to the external device via the plurality of signal lines, wherein the modified voltage signal and the modified current signal are operable to cause the external device to modify the amount of voltage transmitted to the power bus. |
| US09634491B2 |
Power managers and methods for operating power managers
A power manager including a power bus operable at a DC bus voltage. A plurality of device ports operably connect to the power bus. A first data processing device and a first memory device are associated with the first data processing device. A data communication channel extends between the first data processing device and each of the plurality of device ports. An energy management schema operates on the first data processing device. For each of the plurality of device ports, the energy management schema establishes a communication link with an external power device connected to the device port over the data communication channel and determines if an external power device is connected to the device port and if so, determines an external power device type. |
| US09634489B2 |
Electrical power transmission network
An improved management of an electrical power transmission network is obtained by providing at each of the subscriber premises a load control device which includes a power correction system for applying a capacitive load and/or a switched reactor for voltage correction across the input voltage and a sensing system defined by a pair of meters one at the supply and the second downstream of the voltage correction for detecting variations in power factor. A control system operates to control the power correction system in response to variations detected by the sensing system and to communicate between the load control device and the network control system so as to provide a bi-directional interactive system. |
| US09634486B2 |
Dynamic power rail control for clusters of loads
Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode. |
| US09634485B2 |
Power manager
An improved power manager includes a power bus (410) and multiple device ports (1-5), with at least one device port configured as a universal port (3 and 4) to be selectively connected to the power bus over an input power channel that includes an input power converter (510) or over a output or universal power channel (412, 416) that includes an output power converter (440, 442). The universal power channel (412) allows the input port (4) to be selected as an output power channel instead of an input power channel (i.e. operated as a universal port) for outputting power to device port (4) over power converter (440). The improved power manager (500) includes operating modes for altering an operating voltage of the power bus (505), to minimize overall power conversion losses due to DC to DC power conversions used to connect non-bus voltage compatible power devices to the power bus. |
| US09634482B2 |
Apparatus and methods for transient overstress protection with active feedback
Apparatus and methods for providing transient overstress protection with active feedback are disclosed. In certain configurations, a protection circuit includes a transient detection circuit, a bias circuit, a clamp circuit, and a sense feedback circuit that generates a positive feedback current when the clamp circuit is clamping. The transient detection circuit can detect a presence of a transient overstress event, and can generate a detection current in response to detection of the transient overstress event. The detection current and the positive feedback current can be combined to generate a combined current, and the bias circuit can turn on the clamp circuit in response to the combined current. While the transient overstress event is present and the clamp circuit is clamping, the sense feedback circuit can generate the positive feedback current to maintain the clamp circuit turned on for the event's duration. |
| US09634481B2 |
MOSFET protection using resistor-capacitor thermal network
A circuit for protecting a semiconductor element is provided in a system for supplying power from an input node to an output node. The circuit has an analog multiplier responsive to a voltage across the semiconductor element and a current flowing through the semiconductor element to produce an output voltage. A transconductance amplifier is coupled to an output of the analog multiplier for receiving the output voltage of the analog multiplier to produce an output current. An analog RC circuit coupled to the output of the transconductance amplifier is configurable to include a selected number of resistive elements having selected resistance values and a selected number of capacitive elements having selected capacitance values. The configuration of the RC circuit is carried out to provide an RC thermal model that reproduces a desired thermal behavior of the semiconductor element. The RC circuit is responsive to the output current of the transconductance amplifier to produce an output voltage used to control the semiconductor element. |
| US09634477B2 |
Method for adjusting an inrush current of a domestic appliance, and domestic appliance, in particular cooking range, comprising a control unit for carrying out the method
In a method for setting an inrush current of a domestic appliance to a region-specific inrush current, the domestic appliance is switched to a setting mode, in which the inrush current is limited at the domestic appliance to one of a number of region-specific inrush currents that are selectable at the domestic appliance. |
| US09634476B1 |
Apparatus for breaking line bidirectional current and control method thereof
An apparatus for breaking a line bidirectional current and a control method therefore. The apparatus comprises a breaking current branch circuit and an on-state current branch circuit, the breaking current branch circuit comprises one nonlinear resistor being connected in parallel to one first power semiconductor device, or one nonlinear resistor being connected in parallel to at least two first power semiconductor devices mutually connected in series; and the on-state current branch circuit comprises at least one bidirectional power semiconductor switch being connected in series to at least one high-speed isolation switch. The apparatus also comprises a bridge-type branch circuit. An apparatus for breaking a line bidirectional current, thereby greatly reducing costs of the apparatus and reducing difficulty in device layout, mounting and wiring of the apparatus on the premise of ensuring a breaking speed that is quick enough and a low loss. |
| US09634473B2 |
Redundant wired pipe-in-pipe telemetry system
A system and method for providing redundant wired pipe-in-pipe telemetry is described. In one embodiment, a system includes an outer pipe and an inner pipe disposed within the outer pipe. The outer pipe axially supports the inner pipe using a collar of the inner pipe. A first conductive element is coupled to the inner pipe and disposed at least partially within an annulus between the inner pipe and the outer pipe. A second conductive element is disposed within the outer pipe. A wired path controller is coupled to the collar of the inner pipe, and also coupled to the first conductive element and the second conductive element. A connector is coupled to the collar of the inner pipe, which coupled the second conductive element to the wired path controller. |
| US09634472B2 |
Adjustable cable managers
A cable management system includes elongated members mounted to a panel; and gate members configured to couple to at least some of the elongated members. Adjacent ones of the elongated members define management regions therebetween. Each gate member is rotatable relative to the respective elongated member to selectively inhibit and allow access to the respective management region. Each gate member can be fixed at any axial point along an adjustment region of the respective elongated member to adjust the depth of the management region. |
| US09634471B2 |
Grommet and sealing structure using grommet
Provided are a grommet capable of preventing a corrugated tube from being crushed due to attaching of a fixing member, and a sealing structure using a grommet. A grommet has a main portion having a tubular shape capable of being externally fitted to an end portion of an exterior member of a wire harness, the exterior member having a relatively high rigidity. An inner circumferential face of the main portion is a first sealing face capable of establishing intimate contact with an outer circumferential face of the exterior member. An outer circumferential face of the main portion is a second sealing face capable of establishing intimate contact with an inner circumferential face of an end portion of a corrugated tube, the end portion being put over the outside of the main portion. |
| US09634464B2 |
Method for generating a compressed optical pulse
There is presented a method of for generating a compressed optical pulse (112) comprising emitting from a wavelength tunable microcavity laser system (102), comprising an optical cavity (104) with a mechanically adjustable cavity length (L), a primary optical pulse (111) having a primary temporal width (T1) while adjusting the optical cavity length (L) so that said primary optical pulse comprises temporally separated photons of different wavelengths, and transmitting said pulse through a dispersive medium (114), so as to generate a compressed optical pulse (112) with a secondary temporal width (T2), wherein the secondary temporal width (T2) is smaller than the primary temporal width (T1). |
| US09634460B2 |
Compensation for a disturbance in an optical source
A pulsed light beam emitted from an optical source is received, the pulsed light beam being associated with a temporal repetition rate; a frequency of a disturbance in the optical source is determined, the frequency being an aliased frequency that varies with the temporal repetition rate of the pulsed light beam; a correction waveform is generated based on the aliased frequency; and the disturbance in the optical source is compensated by modifying a characteristic of the pulsed light beam based on the generated correction waveform. |
| US09634459B2 |
Generation of a high power pulse-laser using field generated coherence
A laser system including a laser cavity, a gain medium disposed in the laser cavity, a pump configured to excite an atom of the gain medium to an excited state, an optical device configured to couple a ground state of the atom of the gain medium to the excited state by applying an optical field to the gain medium, and a microwave device configured to couple the ground state of the atom of the gain medium to a different ground state by applying a microwave field to the gain medium. |
| US09634458B2 |
Pump recycling integrated amplifier
A laser system and method of use are provided in which the laser system may include a fiber laser oscillator and rare earth doped piece of optical fiber which may absorb unused pump light which is unabsorbed in the oscillator. |
| US09634449B1 |
Soft contacting rotational interface for RF rotary joint
The current invention, by using a plurality of conductive fiber brush bundles and a coaxial line to transfer RF signal(s) between relatively rotatable objects, creates easy-maintenance, long duration a RF rotary joint with soft contacting rotational interfaces. It consists of a stationary shield conductor assembly, a stationary core conductor assembly, a rotational shield conductor assembly with a tapered round head, a rotational core conductor assembly with a tapered round head, and rotational and stationary insulating assemblies with a central bore. Both stationary and rotational shield conductor assemblies having a conductive fiber brush bundle, which further containing a plurality of hair-thin conductive filaments to form a symmetrical flexible tube. The interfaces of the core soft contacting rotational and the shield soft contacting rotational are formed between the free end portions of the conductive fiber brush bundles and the tapered round head of the rotational cone conductor and rotational shield conductor respectively. |
| US09634448B2 |
Liquid crystal display matrix with irregular aperture geometry
In the field of active matrix liquid crystal displays and, more particularly, to microdisplays produced using collective fabrication technologies, a matrix comprises, for each pixel, a transparent electrode and opaque regions resulting from the presence in the pixel of at least one row conductor, one column conductor, and one control transistor for the pixel connected to the electrode of the pixel. The pixel comprises at least three possible geometrical configurations, the position of the transistor with respect to the rows and to the columns being different in the various configurations, the various configurations being distributed in a pseudo-random manner within at least one region of the matrix. |
| US09634445B1 |
Electrical bus bar connector system
A bus bar connector system and an electrical distribution center suitable for use in a motor vehicle including such a bus bar connection system is presented. The bus bar connector system includes a first bus bar, a second bus bar, and a spring clip configured to apply a contact force to the first and second bus bars effective to bring at least a portion the first and second bus bars into intimate contact with one another. The spring clip may comprise two longitudinal spring arms each extending from a lateral spring base interconnecting the spring arms. These spring arms are angled toward one another and end portions of the spring arms may be angled away from one another, thereby forming an hourglass or X-shaped spring clip. The end portions of the spring arms may be configured to retain the spring clip within a slot defined by a connector housing. |
| US09634442B2 |
System of plug connectors fixed on mounting rails
A latching device for a first system of plug connectors, which are fastened to a first mounting rail, and a second system of plug connectors, which are fastened to a second mounting rail, includes a passive latching part and an active latching part. When the active latching part is latched to the passive latching part, the first mounting rail and the second mounting rail are connected to each other, and the plug connectors located on the first mounting rail and the second mounting rail are brought into contact with each other. |
| US09634441B2 |
High voltage connector for vehicle
A high voltage connector for a vehicle includes: a first connector connected to a first wire to transfer a current and including an interlock switch part controlling an interlock signal to open or close a voltage transfer; and a second connector connected to a second wire to transfer a current and including a pressing part pressing a portion of the interlock switch part of the first connector to control the opening or closing of the voltage transfer of the interlock switch part. |
| US09634440B2 |
GFCI with cycle counter
Systems and methods for providing end-of-life functionality in an electrical component using a count of plugging operations are shown. In some configurations, a GFCI counts plugging operations and then provides an LED end-of-life indication when a threshold of plugging operations is met. |
| US09634438B2 |
Electrical apparatus comprising a temperature sensor housed in a support element
The electrical accessory (100) includes an electrically insulating body (110) housing at least two electrical connection elements (121, 122, 123), and a temperature sensor (200). The temperature sensor is received in a thermally conductive and electrically insulating support element (150) that is distinct from the body, and that is fitted inside the body in such a manner as to extend between the electrical connection elements, being set back from the outside faces of the body. |
| US09634435B1 |
Electric vehicle power supply equipment with interchangeable power supply cords conforming to different technical standards
An electric vehicle supply equipment (EVSE) assembly for an electric vehicle (EV) or plug-in hybrid electric vehicle (PHEV), often referred to as, optionally having one of at least two interchangeable power supply cords with plugs that conform to different technical standards, such as National Electrical Manufacturers Association (NEMA) 5-15P or 6-20P. The interchangeable power supply cord plugs each include a thermistor adapted to monitor plug temperatures. The electronic module is configured to disable charging until a proper resistance of the thermistor in the plug is detected. The electronic module is also configured to automatically switch between 120 volt and 240 volt operation based on which of the interchangeable power supply cords is connected to the electronic module. |
| US09634434B1 |
Electrical connector and differential signal assembly thereof
A differential signal assembly includes two pairs of differential signal wafers arranged in one row. Each differential signal wafer includes a plurality of mating portions arranged in one column and a plurality of mounting portions arranged in one column. In one of the two pairs of differential signal wafers, each differential signal wafer has a grounding pin and an offset grounding pin respectively arranged at two opposite ends of the column of mounting portions thereof, each offset grounding pin has an offset with respect to the corresponding column of mounting portions, the two distal ends of the mounting portions of each differential signal wafer are two signal mounting portions, cooperating with the two signal mounting portions of the other differential signal wafer. Thus, the grounding pin and the offset grounding pin of each differential signal wafer are configured to shield the adjacent signal mounting portions. |
| US09634431B1 |
Clamp cup to secure electrical connectors having first and second mating structures
A device comprises a connector support configured to receive and support a first electrical connector and comprising a first surface configured to face and attach to a housing wall and a second surface comprising first mating structure extending away from the housing wall; and a clamp cup configured to receive and at least partially surround a cable and a second electrical connector attached to the cable, the second electrical connector being configured to mate with the first electrical connector, the clamp cup comprising an outer surface and a second mating structure, the clamp cup being configured to removably fit over and attach to the connector support by mutual engagement of the first and second mating structures to mate the first and second electrical connectors and hold the mated first and second electrical connectors against the housing wall. |
| US09634426B2 |
Electronic device with hidden connector
An electronic device has a self-healing elastomer applied over one or more external electronic connectors. The self-healing elastomer may obscure the electronic connectors from the user as well as provide environmental protection for the connector and the electronic device. Electronic probes may temporarily penetrate the self-healing elastomer to mate with the electronic connector. After removal of the probes the self-healing elastomer may elastically reform and self-heal. |
| US09634422B2 |
Plug connector with improved insulative housing for retaining terminals
An electrical connector includes an insulative housing defining a chamber, a number of terminals mounted in the insulative housing, and an insulative block mounted to the insulative housing. Each terminal includes a mounting section mounted in the insulative housing, a contacting section protruding forwards from the mounting portion, and a soldering section protruding backwards from the mounting portion. The contacting sections are exposed to the chamber. The insulative block has a number of guiding ribs and a number of stopping ribs located behind the guiding ribs respectively. Two adjacent guiding ribs define a receiving slot for receiving the soldering section. The stopping rib has a top blocking section. |
| US09634415B2 |
Device for coupling a PLC bus
In order to facilitate the vertical placement of modules (104, 106) within a PLC (100) and thus decrease the size of the PLC (100) without reducing the capability of the PLC (100), modules (104, 106) of the PLC (100) each includes a printed circuit board (PCB) (200, 202, 204), a spring loaded pin connector (214) supported by and in electrical communication with a first surface (206, 208) of the PCB (200, 202, 204), and a receptacle (216) supported by and in electrical communication with a second surface (206, 208) of the PCB (200, 202, 204). The spring loaded pin connector (214) and the receptacle (216) are in electrical communication with each other via the PCB (200, 202, 204). |
| US09634409B2 |
Electrical connector receptacle with combined first and second contacts
An electrical receptacle connector includes a metallic shell, an insulated housing, a plurality of first receptacle terminals, and a plurality of second receptacle terminals. The insulated housing received in the metallic shell is assembled with the first receptacle terminals and the second receptacle terminals. The tail portion of the power terminal of the second receptacle terminals is adjacent to and combined with the tail portion of the power terminal of the first receptacle terminals. The tail portion of the ground terminal of the second receptacle terminals is adjacent to and combined with the tail portion of the ground terminal of the first receptacle terminals. The combined tail portions can be inserted into the same soldering hole of a circuit board. Therefore, the cost and time for the soldering procedure of the connector manufacturing can be reduced. |
| US09634405B2 |
Terminal weld tab having a wire squeeze limiter
One variation may include an electrical connection terminal (20) including at least a first weld tab (22). The first weld tab (22) including an outer face (23) and a weldable inner face (33). The weldable inner face (33) includes a substantially planar first portion (25) and a substantially planar second portion (27), and wherein the first portion (25) and second portion (27) are not in the same plane. Another variation may include an electrical connection post (56) having a first post portion (64) and a second post portion (404), the first post portion having a first width and the second post portion having a second width, and wherein the first width is greater than the second width. |
| US09634403B2 |
Radio frequency emission pattern shaping
Pattern shaping elements shape a radiation pattern generated by one or more antennas. A MIMO antenna system generates an omnidirectional radiation pattern. One or more pattern shaping elements may include metal objects which act as directors or reflectors to shape the radiation pattern. The shaping may be controlled by selectively coupling the pattern shaping elements to a ground plane, thus making them appear transparent to the radiation pattern. The pattern shaping elements may be amorphous, have varying shape, and may be symmetrical or asymmetrical. Different configurations of selected pattern shaping elements may provide different shapes for a radiation pattern. |
| US09634400B2 |
Dish antenna having a self-supporting sub-reflector assembly
An antenna has a waveguide horn extending from a main reflector. A dielectric tube extends from the distal end of the waveguide horn to support a sub-reflector in the focal region of the main reflector. An insert is placed into the dielectric tube to seat against the distal end of the dielectric tube. A fastener secures the insert to the sub-reflector, thereby securing the sub-reflector to the distal end of the dielectric tube. The surface of the insert serves as a continuation of the sub-reflector. The dielectric tube can be equipped with an inwardly-extending collar about its distal end to engage the insert. |
| US09634398B2 |
Cassegrain satellite television antenna and satellite television receiving system thereof
The present invention discloses a Cassegrain satellite television antenna comprising a metamaterial plate. The metamaterial plate comprises a core layer. The core layer comprises core sublayers. Each core sublayer comprises a circular area and a plurality of annuli distributed around the circular area. According to the Cassegrain satellite television antenna of the present invention, the traditional parabolic antenna is replaced with a sheet-like metamaterial plate which is easier to process and has a lower cost. In addition, the present invention also provides a satellite television receiving system equipped with the above-mentioned Cassegrain satellite television antenna. |
| US09634397B2 |
Ultra-wideband tapered slot antenna
An ultra-wideband tapered slot antenna that is capable of providing spatial independent band-stop characteristics which are irrelevant to the radiation direction of the antenna in a dual-stop band. The antenna includes an ultra-wideband tapered slot antenna includes a radiating unit formed on a first surface of a substrate and configured to radiate radio signals. A feeding unit is formed on a second surface of the substrate and is configured to provide the radio signals to the radiating unit. Separate stubs are formed to be spaced apart from the feeding unit around the feeding unit and are configured to reject frequencies in a first stop band from the radio signals radiated from the radiating unit. A slot is formed in a stub formed at a first end of the feeding unit and is configured to reject frequencies in a second stop band from the radio signals. |
| US09634395B2 |
Monopole antenna with a tapered Balun
Embodiments are directed to a balun structure comprising: a monopole antenna, and a microstrip coupled to the monopole antenna and comprising a ground plane modified to include at least two arms. Embodiments are directed to a balun structure comprising: a monopole antenna, and a microstrip coupled to the monopole antenna using a stepwise tapered microstrip feed. |
| US09634393B2 |
Antenna system for signal-attenuating containers
A system can include a container that includes a cabinet capable of attenuating or blocking wireless signals, an AED located within the cabinet, an internal patch antenna removably mounted to an internal surface of the cabinet, an external patch antenna removably mounted to an external surface of the cabinet, and an electrical connection between the internal patch antenna and the external patch antenna. The internal and external patch antennas can be configured to transmit wireless signals at a particular frequency and to receive wireless signals at the particular frequency. The system can be configured such that the internal patch antenna is operative to receive a first wireless signal from the AED, a first electrical signal based on the first wireless signal is provided via the electrical connection to the external patch antenna, and a second wireless signal based on the first electrical signal is radiated by the external patch antenna. |
| US09634387B2 |
Multiple-input multiple-output (MIMO) antenna
A multiple input multiple output (MIMO) antenna is provided. The MIMO antenna may include, but is not limited to, a printed circuit board having a plurality of edges and a ground layer including, but not limited to a plurality of antenna element mounting locations, at least one of the plurality of antenna element mounting locations being arranged on a first side of the printed circuit board and at least one of the plurality of antenna element mounting locations being arranged on a second side of the printed circuit board, a plurality of slots, each of the plurality of slots extending a predetermined distance from an edge of the printed circuit board, and at least one ground stub, the at least one ground stub comprising an extension of the ground layer of a predetermined electrical length at a predetermined angle relative to the edge of the printed circuit board. |
| US09634380B2 |
Antenna device and communication terminal device
An antenna device includes two conductor surfaces facing each other and spaced apart from each other, connecting conductors that connect the two conductor surfaces at at least two positions, and an antenna coil located in proximity to one of the connecting conductors. The connecting conductors and the two conductor surfaces define a closed loop containing a surface of a space. In a plan view of the surface of the space defined by the closed loop, the antenna coil is located at a position where the antenna coil does not overlap the surface of the space and at a position where electromagnetic induction by the antenna coil causes an induced current to flow through the connecting conductor. |
| US09634379B2 |
Radiation device for planar inverted-F antenna and antenna using the same
A planar inverted-F antenna according to an embodiment includes a ground plane, a radiator spaced apart from the ground plane, and a feeding member for feeding a current to the radiator. A first slot is formed in the radiator, and the first slot is excited as the current is fed to the radiator through the feeding member such that the current flows around the first slot and the first slot implements a resonance frequency according to the excitation. |
| US09634378B2 |
Peripheral electronic device housing members with gaps and dielectric coatings
An electronic device such as a handheld device may have a rectangular housing with a rectangular periphery. A conductive peripheral housing member may run along the rectangular periphery and may surround the rectangular housing. Radio-frequency transceiver circuitry within the electronic device may be coupled to antenna structures for transmitting and receiving radio-frequency signals. The conductive peripheral housing member may form part of the antenna structures. A gap in the conductive peripheral housing member may be filled with dielectric. The conductive peripheral housing member may be configured to form a recess. The recess may have the shape of a rectangle, oval, diamond, or other shape that overlaps and is bisected by the gap. The recess may also have the shape of a groove that extends around the entire periphery of the housing. The dielectric in the recess may include one or more different materials such as clear and opaque polymers. |
| US09634373B2 |
Antenna isolation shrouds and reflectors
Shroud isolation, including choke shroud isolation, apparatuses for wireless antennas for point-to-point or point-to-multipoint transmission/communication of high bandwidth signals, and integrated reflectors including a shroud or choke shroud. A choke shroud systems may include a cylindrical body with an isolation choke boundary at the distal opening to attenuate electromagnetic signals to, from, or within the antenna. The isolation choke boundary region may have ridges that may be tuned to a band of interest. The isolation choke boundary may provide RF isolation when used near other antennas. |
| US09634372B2 |
Apparatus for use in the receipt and/or transmission of data signals
Apparatus is provided which allows for the receipt and/or transmission of data signals, and, for the received signals, for the subsequent separation of the same into at least two sets of data signals which are orthogonal and provide these sets of data signals to subsequent processing components, whilst maintaining the isolation between the first and second data signal sets. For the transmission of the data signals the first and second sets of data signals are initially separate and then combined into one data set to allow the same to be transmitted. |
| US09634370B2 |
Waveguide structure and printed-circuit board
A waveguide structure or a printed-circuit board is formed using a plurality of unit structures which are repetitively aligned in a one-dimensional manner or in a two-dimensional manner. The unit structure includes first and second conductive planes which are disposed in parallel with each other, a transmission line having an open end which is formed in a layer different from the first and second conductive planes and positioned to face the second conductive plane, and a conductive via electrically connecting the transmission line to the first conductive plane. |
| US09634369B2 |
Waveguide structure and printed-circuit board
A waveguide structure or a printed-circuit board is formed using a plurality of unit structures which are repetitively aligned in a one-dimensional manner or in a two-dimensional manner. The unit structure includes first and second conductive planes which are disposed in parallel with each other, a transmission line having an open end which is formed in a layer different from the first and second conductive planes and positioned to face the second conductive plane, and a conductive via electrically connecting the transmission line to the first conductive plane. |
| US09634367B2 |
Filter
Embodiments of the present invention disclose a filter, including: a conductive box body, and an insulating substrate, a first conductor, and a second conductor that are arranged inside the conductive box body. The insulating substrate includes a first surface and a second surface. The first conductor is arranged on the first surface of the insulating substrate. A position on the second surface corresponding to the first conductor contacts with the conductive box body. The second conductor is arranged on the first surface or the second surface of the insulating substrate. The second conductor and the conductive box body form a coaxial resonant cavity together. Further, an end of the second conductor is coupled with the first conductor, and the other end of the second conductor is coupled with the conductive box body. The filter has advantages of a microstrip filter of simple manufacturing process and small volume. |
| US09634365B2 |
Metal-air battery
A metal-air battery includes first and second cells, each cell including a negative electrode metal layer, a negative electrode electrolytic film, a positive electrode layer configured to use oxygen as an active material, and a gas diffusion layer, wherein the negative electrode metal layer, the negative electrode electrolytic film, the positive electrode layer, and the gas diffusion layer are sequentially disposed, wherein each cell has an open surface through which at least a portion of the gas diffusion layer is in fluid communication with, outside air, wherein the first and second cells contact each other, and wherein a direction of a first open surface of the first cell is different from a direction of a second open surface of the second cell. |
| US09634360B2 |
All-solid-state secondary cell
An all-solid-state secondary cell is provided comprising at least a positive electrode, a negative electrode and a solid electrolyte layer which is positioned between the positive electrode and the negative electrode. The positive electrode contains a positive electrode active material consisting of Na2Sx (x=1 to 8) and the solid electrolyte layer contains an ion conductive glass ceramics represented by a formula (I): Na2S-MxSy, wherein M is P, Si, Ge, B or Al; x and y each is an integer giving a stoichiometric ratio depending upon the type of M; and Na2S is contained in an amount of more than 67 mole % and less than 80 mole %. |
| US09634359B2 |
Electrolyte for zinc-based rechargeable batteries, method for producing the same and batteries including said electrolyte
The present invention provides an electrolyte comprising polymer comprising alkyl-capped PEG; an alkaline agent; and water, wherein the water is present in an amount greater than or equal to about 60 wt % of the electrolyte and methods of producing the same. The present invention further provides an electrochemical cell comprising said electrolyte, and methods of producing the same. The present invention also provides a separator comprising alkyl-capped PEG and cellulose, and methods of producing the same. |
| US09634357B2 |
Hybrid type secondary battery including electrodes having different output and capacity properties
Disclosed herein is a battery cell having an electrode assembly, including a positive electrode, a negative electrode, and a separator interposed between the positive electrode and the negative electrode, mounted in a receiving part of a battery case, wherein a positive electrode terminal and a negative electrode terminal protrude from at least one side of the electrode assembly, and an insulative material is provided between the electrode assembly and the battery case. |
| US09634355B2 |
Polymer electrolyte for lithium battery and lithium battery including the polymer electrolyte
A polymer electrolyte for a lithium battery, the polymer electrolyte comprising a compound represented by Formula 1: wherein, in Formula 1, X1 to X6, Ar1, Ar2, R1, R2, m, and n are the same as defined in the detailed description of the present specification. |
| US09634352B2 |
Method for making lithium ion battery
A method for making lithium ion battery is provided. A cathode material layer and an anode material layer are provided. A cathode current collector is formed on a surface of the cathode material layer to obtain a cathode electrode. The cathode current collector includes a graphene layer and a carbon nanotube layer stacked with the graphene layer. An anode current collector is formed on a surface of the anode material layer to obtain an anode electrode. A separator is applied between the cathode electrode and the anode electrode thereby forming a battery cell. At least one battery cell is encapsulated in an external encapsulating shell. An electrolyte solution is injected into the external encapsulating shell. |
| US09634349B2 |
High silica content substrate such as for use in thin-film battery
A high silica content substrate, such as for a thin-film battery, is provided. The substrate has a high silica content, such as over 90% by weight silica, and is thin, for example less than 500 μm. The substrate may include a surface with a topography or profile that facilitates bonding with a coating layer, such as a coating of an electrochemical battery material. The high silica content substrate may be flexible, have high temperature resistance, high strength and/or be non-reactive. The substrate may be suitable for use in the high temperature environments used in many chemical deposition or formation processes, such as electrochemical battery material formation processes. |
| US09634348B2 |
Battery pressing device and battery pressing method
A battery pressing device for pressing a battery cell, the battery cell including an external casing, an electrolyte, a battery element in which electrodes and a separator are arranged in layers in the external casing, electrode terminals extending out of the external casing from an end of the battery element, and an insulating member for preventing short-circuiting of the electrode terminals attached to the electrode terminals inside the external casing, the battery pressing device includes a pressing member configured to press the battery cell in a layering direction of the battery element over a region so as to avoid pressing the insulating member inside the external casing. |
| US09634347B2 |
Method and components for repairing a ceramic fuel cell stack assembly
There is disclosed a method and components for repairing a fuel cell stack. In particular, the method and components relate to repairing a high temperature fuel cell stack incorporating ceramic components. The method includes identifying a fuel cell bundle within a fuel cell strip to be disconnected from the fuel cell strip, identifying at least one fuel feed pipe portion connected to the fuel cell bundle, and identifying at least one fuel outlet pipe portion connected to the fuel cell bundle. A cutting blade is positioned on the fuel feed pipe portion and cutting through the fuel feed pipe portion, and similarly for the fuel outlet pipe portion. The fuel cell bundle is then removed, and a replacement inserted in its place. |
| US09634346B2 |
Membrane electrode assembly and fuel cell battery
A membrane electrode assembly for use in a fuel cell battery includes: an electrolyte membrane; an anode catalyst layer formed on a first surface of the electrolyte membrane; a cathode catalyst layer formed on a second surface of the electrolyte membrane; an anode gas diffusion layer stacked on the anode catalyst layer; and a cathode gas diffusion layer stacked on the cathode catalyst layer. The anode catalyst layer, the cathode catalyst layer, the anode gas diffusion layer, and the cathode gas diffusion layer have the same thermal insulation performance per thickness. The membrane electrode assembly satisfies all relations of T1+T3 |
| US09634343B2 |
Hydrogen offloading in an electrochemical generator unit including a hydrogen fuel cell
In order to make more specifically water autonomous a hydrogen cell electrochemical generating unit (10), the generating unit (1) comprises a condenser (13) provided with a fan (13V) and with a radiator (13R) in contact with a tank (12) stocking hydrogen into a hydride. The condenser simultaneously transfers heat from a steam filled air (17E) to an endothermic reaction of the hydride into an alloy and into hydrogen via the radiator and condenses the steam into condensation water (13EC) being collected by a tank (14) supplying an electrolysis facility (11) with water for producing the hydrogen to be stocked. |
| US09634342B2 |
Fuel cell system and control method
A fuel cell system estimates a characteristic of an electric power generation of a fuel cell before a supply of an electric power is permitted from the fuel cell to an outside load, restricts or prohibits characteristic of the electric power generation of the fuel cell when a temperature of the fuel cell is equal to or lower than a first prescribed temperature. |
| US09634333B2 |
Catalyst production method and catalyst production apparatus, and method for controlling characteristics of reaction layer for fuel cell using the catalyst
The present invention is directed to improving a catalyst applied to a reaction layer having a structure (PFF structure) in which a polymer electrolyte phase surrounds a periphery of a catalyst with a hydrophilic region interposed therebetween and reducing the amount of catalyst metal particles used.A method for producing a catalyst for a fuel cell, in which a catalyst metal particle is supported on a carrier, includes the steps of: preparing an unmodified catalyst in which a catalyst metal particles is supported on a carrier; and modifying the catalyst metal particle in the unmodified catalyst with at least one type of modifying group selected from a nitric acid group, an amino group, a sulfonic acid group, a hydroxy group, and halogen groups. |
| US09634330B2 |
Anode and secondary battery
A secondary battery capable of improving the cycle characteristics is provided. The secondary battery includes a cathode, an anode, and an electrolytic solution. The electrolytic solution is impregnated in a separator provided between the cathode and the anode. The anode has an anode structure on an anode current collector. The anode structure has a structure in which a plurality of anode active material particles having silicon are held by a plurality of metal fibers forming a three-dimensional network structure. Due to the plurality of metal fibers, sufficient conductive paths are obtained among the plurality of anode active material particles. Thus, compared to a general anode in which an active material layer is provided on a current collector made of a metal foil or the like, the current collectivity is improved. |
| US09634329B2 |
Method of preparing graphene and anode mixture for lithium secondary battery including graphene prepared thereby
Disclosed herein is a method of preparing porous graphene from porous graphite, including 1) thermochemically reacting a highly crystalline carbide compound with a halogen element-containing gas to give a porous carbide-derived carbon; 2) treating the carbide-derived carbon with an acid, thus preparing a carbide-derived carbon oxide; and 3) reducing the carbide-derived carbon oxide. An anode mixture for a secondary battery including the graphene and an anode for a secondary battery including the anode mixture are also provided. |
| US09634325B2 |
Negative active material, negative electrode and lithium battery including the negative active material, and method of manufacturing the negative active material
A negative active material, a negative electrode, a lithium battery including the negative active material, and a method of manufacturing the negative active material, the negative electrode, and the lithium battery. The negative active material includes a silicon-based alloy including Si, Ti, Ni, and Fe components. The silicon-based alloy includes a Ti2Ni phase as an inactive phase and active silicon having a lower content than that of typical silicon-based alloys. The negative active material may improve discharge capacity and lifetime characteristics of lithium batteries. |
| US09634319B2 |
Bipolar battery and plate
A bipolar battery plate is utilized for production of a bipolar battery. The bipolar battery plate includes a frame, a substrate, first and second lead layers, and positive and negative active materials. The substrate includes a plurality of perforations through the substrate, and the substrate is positioned within the frame. The first lead layer is positioned on one side of the substrate, while the second lead layer is positioned on another side of the substrate. The first and second lead layers are electrically connected to each through the plurality of perforations. The positive active material is positioned on a surface of the first lead layer, while the negative active material is positioned on a surface of the second lead layer. |
| US09634318B2 |
Oxide shell formation on inorganic substrates via lithium polyoxoanion salt deposition
The present invention provides a process for depositing an oxide coating on an inorganic substrate, including providing an aqueous composition containing a tetraalkylammonium polyoxoanion and lithium hydroxide; contacting the aqueous composition with an inorganic substrate for a time sufficient to deposit a lithium polyoxoanion on surfaces of the inorganic substrate to form an initially coated inorganic substrate; and heating the initially coated inorganic substrate for a time sufficient to convert the lithium polyoxoanion to an oxide to form on the inorganic substrate an oxide coating derived from the polyoxoanion. The inorganic substrate may be a ceramic material or a semiconductor material, a glass or other dielectric material, and the ceramic material may be a lithium ion battery cathode material. |
| US09634313B2 |
Anti-rotation mechanism for electrode terminal post of lithium-ion battery
The present disclosure provides an anti-rotation mechanism for an electrode terminal post of a lithium-ion battery, the anti-rotation mechanism for the electrode terminal post of the lithium-ion battery is an insulative piece, the insulative piece is provided on an electrode terminal post base which is fixedly connected to the electrode terminal post, and the insulative piece is also fixedly connected to an inner wall of a battery case of the lithium-ion battery. The rotation of the electrode terminal post of the lithium-ion battery can be effectively prevented through the insulative piece which is provided on the electrode terminal post base and is fixedly connected to the inner wall of the battery case of the lithium-ion battery. |
| US09634310B2 |
Secondary battery
According to one embodiment, there is provided a secondary battery. This secondary battery includes an electrode and an organic-fiber layer. The electrode includes a current collector including an edge part, an active material-containing layer including an end part supported on the edge part, and a current-collecting tab including a surface a part of which is adjacent to the edge part. The organic-fiber layer is bonded with the end part of the active material-containing layer with maximum thickness and with the part of the surface of the current-collecting tab. |
| US09634309B2 |
Binder composition, separator including binder formed from the binder composition, lithium battery including the separator, and method of preparing the binder composition
A separator for a battery, a battery, and a method of preparing a graft copolymer for a binder, the separator including a porous substrate; a coating layer on at least one surface of the porous substrate, the coating layer including an inorganic oxide; and a binder between the porous substrate and the inorganic oxide or between adjacent particles of the inorganic oxide, the binder including a graft copolymer, wherein the graft copolymer has a backbone of a polyvinylidene fluoride-based polymer or a polyvinylidene fluoride-based copolymer, and a pendant chain grafted to the backbone, the pendant chain including a hydrophilic repeating unit, and fluorine atoms in the backbone of the graft copolymer are partially substituted with at least one of chlorine, bromine, or iodine. |
| US09634300B2 |
Secondary battery comprising reinforcement part and gasket
A secondary battery includes a case; a cap plate coupled to the case; at least one electrode assembly accommodated in the case, the electrode assembly including a positive electrode plate, a negative electrode plate, and a separator located between the positive and negative electrode plates; an electrode collector electrically connected to the electrode assembly; an electrode terminal connected to the electrode collector and protruding outward from the cap plate; a gasket surrounding the electrode terminal; and a reinforcement part coupled to the gasket such that at least a portion of the electrode collector is located between the reinforcement part and the gasket. |
| US09634298B2 |
Hermetically sealed battery and method for manufacturing the same
A sealed battery including: an electrode group 4 formed by winding or stacking a positive electrode plate 1 and a negative electrode plate 2 with a separator 3 interposed between the positive electrode plate 1 and the negative electrode plate 2, and housed in a battery case 5, an opening of the battery case 5 being sealed with a sealing plate, wherein a lead 11 extending from one of the electrode plates in the electrode group 4 is laser-welded to the sealing plate 10, and a melting width of an end section 13 of a welded portion 9 between the lead 11 and the sealing plate 10 is smaller than a melting width of a center section of the welded portion 9. |
| US09634297B2 |
Battery cell including pouch-type cell and transformed to prismatic shape
Disclosed herein is a prismatic battery cell including a pouch-shaped battery cell having an electrode assembly mounted in a pouch-shaped battery case, a cell case, in which the pouch-shaped battery cell is mounted, the cell case having a polyhedral shape, and a terminal case including external input and output terminals, to which electrode terminals of the pouch-shaped battery cell are coupled, the terminal case being coupled to one end of the cell case, the terminal case having a polyhedral shape. |
| US09634296B2 |
Thin film battery on an integrated circuit or circuit board and method thereof
The present invention relates to flexible thin film batteries on semiconducting surface or the conductive or insulating packaging surface of a semiconductor device and methods of constructing such batteries. Electrochemical devices may be glued to a semiconducting surface or the conductive or insulating packaging surface of a semiconductor device or deposited directly thereon. The invention also relates to flexible thin film batteries on flexible printed circuit board where the electrochemical devices may also be glued or deposited on the flexible printed circuit board. |
| US09634295B2 |
Expandable battery pack containment device for pouch battery cells
A pouch battery cell container, including at least, one battery cell compartment, is interposed between two end plates. The planar electrode surfaces of a pouch battery cell, housed within the battery cell compartment, are subjected to a constant and optimal amount of compressive force during cell expansion and contraction for battery cell optimization. A first end plate and a second end plate are coupled together by a plurality of connecting devices, wherein each connecting device includes an elastic deformation component. As the battery cells housed within the battery container expand and/or contract, the first and second end plates move relative to each other while constrained by the elastic deformation device so as to maintain a constant amount of compressive force on the planar electrode surfaces housed within the battery cell. |
| US09634292B2 |
Sealant curing system and a method of curing a sealant using the same
A sealant curing system and a method of curing a sealant using the same are disclosed. The sealant curing system includes a curing room and a UV light outputting panel. The curing room is used for receiving a display panel having the sealant which is ready to be cured. The UV light outputting panel is used for displaying a sealant curing image according to a preset displaying data, and is used for producing a UV light. The UV light is used for irradiating and curing the sealant of the display panel. The present invention is capable of eliminating a process in which different masks are replaced for display panels of different sizes. |
| US09634289B2 |
Transparent display panel and manufacturing method thereof, and transparent display device
Embodiments of this disclosure provide a transparent display panel and a manufacturing method thereof, and a display device. The transparent display panel comprises a plurality of light-emitting regions and a plurality of transparent regions. The transparent display panel further comprises at least one light-guiding component disposed on a light-emitting side of the transparent display panel, wherein the at least one light-guiding component is configured to transmit a part of light emitted from the light-emitting regions to the transparent regions. In the transparent display panel, a light-guiding component is used to transmit the light emitted by the light-emitting subpixels in the light-emitting regions to the transparent regions, and a plurality of light-redirecting members formed on a surface of the light-guiding component are used to change the direction of light transmitted to the transparent regions and to emit the light from the light-emitting side of the transparent regions. As a result, display uniformity of the whole transparent display panel is improved, and a better display performance can be achieved. |
| US09634286B2 |
Display panel and manufacturing method of the same
In one aspect, a display panel and a manufacturing method of the same is provided. The display panel includes a non-emission region layer having a plurality of emission regions and a connection region that is open to connect adjacent emission regions; an organic emission layer formed in each of the plurality of emission regions; a counter electrode formed in the emission regions and the connection region; and an encapsulation layer formed on the counter electrode. |
| US09634284B2 |
Display device including a protection film having nanobeads
A display device includes a display panel configured to display an image, and a protection film coupled to a lower portion of the display panel. The protection film includes a support film contacting the display panel and a stress control layer below the support film, and the stress control layer includes a plurality of nanobeads. |
| US09634283B2 |
Low temperature viscosity transition composition, display apparatus including the same, and method of manufacturing the same
A low-temperature viscosity transition (LVT) composition, including a tantalum oxide, a display apparatus including the same, and a method of manufacturing the same. |
| US09634280B2 |
Light-emitting device and manufacturing method thereof
An EL light-emitting element in which a lower electrode layer, an EL layer, and an upper electrode layer are stacked is formed on a substrate, and a wiring is formed on a counter substrate. Further, the substrate and the counter substrate are bonded so that the wiring is in physical contact with the upper electrode layer of the EL element. Accordingly, the wiring can serve as an auxiliary wiring for increasing conductivity of the upper electrode layer. With such an auxiliary wiring, a potential drop due to the resistance of the upper electrode layer can be suppressed even in the light-emitting device whose light-emitting portion is large. |
| US09634277B2 |
Structure of white OLED device
The present invention provides a structure of a white OLED device that includes a plurality of emissive layers, of which at least one emissive layer is made of a quantum dot and at least one emissive layer is made of an organic light emission material so as to combine the advantages of the quantum dot and the organic light emission material, where the manufacturing cost is low, the utilization of material is high, and the light emission efficiency is high thereby increasing the brightness of a display device and providing excellent performance for use in flat panel display devices, televisions, and other fields of display. |
| US09634276B2 |
Organic electroluminescent element, display device and illuminating device
Disclosed is an organic electroluminescent element having high luminous efficiency and long life. Also disclosed are a display device and an illuminating device respectively using such an organic electroluminescent element. Specifically disclosed is an organic electroluminescent element comprising an electrode and at least one or more organic layers on a substrate. This organic electroluminescent element is characterized in that at least one of the organic layers is a light-emitting layer containing a phosphorescent compound and a host compound, the phosphorescent compound has a HOMO of −5.15 to −3.50 eV and a LUMO of from −1.25 to +1.00 eV, and the host compound has a 0-0 band of the phosphorescence spectrum at not more than 460 nm and a glass transition temperature of not less than 60° C. |
| US09634271B2 |
Semiconductor device, method of manufacturing the same, and electronic apparatus
A semiconductor device includes: a gate electrode; an organic semiconductor film forming a channel; and a pair of source-drain electrodes formed on the organic semiconductor film, the pair of source-drain electrodes each including a connection layer, a buffer layer, and a wiring layer that are laminated in order. |
| US09634270B2 |
Method for manufacturing flexible display panel and flexible display device
A method for manufacturing a flexible display panel and the flexible display device are disclosed. The method for manufacturing the flexible display panel includes: forming a substrate, a flexible display and an overcoat layer on a support substrate in sequence; flipping over so that one side provided with the support substrate is placed upward; stripping off the support substrate; coating a curable material on a surface obtained after the support substrate is stripped off; and performing a curing process so that the coated curable material is cured to form a protective film. The method for manufacturing the flexible display panel can form the protective film without adopting laminating/bonding devices, is simple and easy, and does not require the vacuum defoamation process subsequently. |
| US09634266B2 |
Organic metal compound, organic light-emitting device, and lighting device employing the same
Organic metal compounds, organic light-emitting devices, and lighting devices employing the same are provided. The organic metal compound has a chemical structure represented by Formula (I): wherein M is Ir, Pt, Ru, Os, Cu, Au, or Pd; n is 1, 2, or 3; m is 0, 1, or 2, and the sum of m and n is equal to a valence of M; L is a bidentate ligand; R1 is hydrogen, C1-9 alkyl group, C5-10 cycloalkyl group, or C5-12 aromatic group; each of R2 is independent and can be hydrogen, halogen, cyano group, C1-9 alkyl group, C1-6 fluoroalkyl group, C5-10 cycloalkyl group, or C5-12 aromatic group; R3 is halogen; and, R4 and R5 are independently the same or different hydrogen, hydroxyl group, amine group, alkyl amine group, halogen, cyano group, C1-9 alkyl group, C1-6 fluoroalkyl group, C5-10 cycloalkyl group, or C5-12 aromatic group. |
| US09634264B2 |
Organic electroluminescent materials and devices
Novel iridium complexes containing phenylpyridine and pyridyl aza-benzo fused ligands are described. These complexes are useful as light emitters when incorporated into OLEDs. |
| US09634262B2 |
Charge transport material, host material, thin film and organic light emitting element
A compound represented by the following formula (1) is useful as a charge transporting material. R1 to R6 represent a group represented by the formula (2), R7 represents an aryl group or an aralkyl group, and R11 to R15 represent a hydrogen atom or a substituent. |
| US09634259B2 |
Condensed cyclic compound and organic light-emitting device including the same
A condensed cyclic compound is represented by Formula 1, and an organic light-emitting device includes the condensed cyclic compound. The organic light-emitting device includes a first electrode, a second electrode facing the first electrode, and an organic layer. The organic layer includes an emission layer and the condensed-cyclic compound. |
| US09634258B2 |
Compounds having bipyridyl group and carbazole ring, and organic electroluminescent element
The present invention relates to a compound having a bipyridyl group and a carbazole ring, which is represented by the following general formula (1); and an organic electroluminescent element containing a pair of electrodes and at least one organic layer interposed therebetween, in which the compound is used as a constituent material of the at least one organic layer: |
| US09634256B2 |
Electroluminescent devices including organic EIL layer
An OLED device comprises a cathode, an anode, and has therebetween a light emitting layer (LEL) comprising a phosphorescent emitting compound disposed in a host comprising a mixture of at least one electron transporting co-host which is a benzophenone derivative with a spiro substituent and at least one hole transporting co-host which is a triphenylamine which contains one trivalent nitrogen atom that is bonded only to carbon atoms, at least one of which is a member of an aromatic ring, wherein there is present an electron transporting layer contiguous to the LEL (HBL?) on the cathode side comprising an anthracene or a fluoranthene and wherein there is present an election injecting layer comprising a phenanthroline or a lithium quinolate contiguous to the cathode. |
| US09634255B2 |
Aromatic amine derivative and organic electroluminescence element using same
An aromatic amine derivative represented by formula (1): wherein L1, L2, Ar1, Ar2, R1, R2, a, b, and Q are as defined in the specification. An organic electroluminescence device having at least one organic thin film layer which includes the aromatic amine derivative has high emission efficiency and long lifetime. |
| US09634248B2 |
Insulator and memory device
According to one embodiment, an insulator includes a material including barium and hafnium oxide. The material has a crystal structure of a space group Pbc21. |
| US09634247B2 |
Complementary metal oxide heterojunction memory devices and methods related thereto
A resistive memory device is disclosed. The memory device comprises one or more metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation. |
| US09634245B2 |
Structures incorporating and methods of forming metal lines including carbon
Disclosed technology relates generally to integrated circuits, and more particularly, to structures incorporating and methods of forming metal lines including tungsten and carbon, such as conductive lines for memory arrays. In one aspect, a memory device comprises a lower conductive line extending in a first direction and an upper conductive line extending in a second direction and crossing the lower conductive line, wherein at least one of the upper and lower conductive lines comprises tungsten and carbon. The memory device additionally comprises a memory cell stack interposed at an intersection between the upper and lower conductive lines. The memory cell stack includes a first active element over the lower conductive line and a second active element over the first active element, wherein one of the first and second active elements comprises a storage element and the other of the first and second active elements comprises a selector element. The memory cell stack further includes an electrode interposed between the at least one of the upper and lower conductive lines and the closer of the first and second active elements. |
| US09634241B2 |
Method and system for providing magnetic junctions including Heusler multilayers
A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a reference layer and nonmagnetic spacer layer between the free and reference layers. At least one of the free and reference layers includes at least one Heusler multilayer. Each of the at least one Heusler multilayer includes a plurality of Heusler adjoining layers that at least one interface. The Heusler layers include a plurality of Heusler alloys, have a plurality of lattice parameters and have a plurality of coefficients of thermal expansion. The magnetic junction is configured such that the free layer is switchable between stable magnetic states when a write current is passed through the magnetic junction. |
| US09634240B2 |
Magnetic memory devices
Magnetic memory devices include a plurality of first magnetic patterns on a substrate so as to be spaced apart from each other, a first insulating pattern between the first magnetic patterns to define the first magnetic patterns, and a tunnel barrier layer covering the first magnetic patterns and the first insulating pattern. The first insulating pattern includes a first magnetic element, and the first magnetic element is the same as a second magnetic element constituting the first magnetic patterns. |
| US09634232B2 |
Piezoelectric signal generator
The piezoelectric signal generator (10;30) includes at least one piezoelectric element (12;20) connected with an emitter (14;35) which is capable of generating, from a current (C) produced by actuation of the piezoelectric element, an electromagnetic signal (S) capable of being wirelessly received by a receiver (16;36) removed from the signal generator (10;30), the piezoelectric element (20;31) comprises a piezoceramic layer (241) attached to an electrically conducting carrier stratum (242); the piezoceramic layer adheres to the carrier stratum and both are held by a positioning layer (23) which has a thickness (TP), and both are capable of a reversible deformation, predetermined by and limited to the thickness (TP) of the positioning layer (23); further, the piezoelectric element (20;31) comprises a gap layer (26) for buffering the reversible deformation of the carrier stratum (242) with the adhering piezoceramic layer (241); the gap (29) has a thickness (TG) such that TG≦TP. |
| US09634231B2 |
MEMS switch
A MEMS switch has fixed support, a plate-shaped flexible beam having at least one end immovably supported by the fixed support and having an extending movable surface, a movable electric contact disposed on the movable surface of the flexible beam, a fixed electric contact facing the movable electric contact and disposed at a fixed position relative to the fixed support, first piezoelectric driver disposed above the movable surface of the flexible beam, extending from a portion above the fixed support towards the movable electric contact, and capable of displacing the movable electric contact towards the fixed electric contact by voltage driving, and second piezoelectric driver disposed at least on the movable surface of the flexible beam and capable of so driving a movable part of the flexible beam by voltage driving that the movable electric contact is separated from the fixed electric contact. |
| US09634230B2 |
Fabrication method of electromechanical transducer film, electromechanical transducer element, liquid ejection head, and inkjet recording apparatus
Disclosed is a method of fabricating an electromechanical transducer film. The method includes treating a surface of a first electrode to be liquid-repellent, the first electrode being formed on one surface of a substrate, irradiating the surface of the first liquid-repellent electrode with an energy ray while moving an irradiation position in accordance with a shape of the electromechanical transducer film to be formed and a shape of an alignment mark to be formed, and forming the alignment mark by applying an application liquid to an area including a portion irradiated with the energy ray in accordance with the shape of the alignment mark in the irradiating step, the application liquid being applied by an inkjet method. |
| US09634228B2 |
Piezo vibration module
Disclosed herein is a piezo vibration module, including: a piezo element having a pattern of an internal electrode printed therein and having an external electrode connected to the internal electrode disposed on an outer surface thereof; a flexible printed circuit board (FPCB) having each terminal and applying power to the external electrodes of the piezo element; and a conductive adhesive interposed between the piezo element and the FPCB to electrically connect the piezo element to the flexible printed circuit board. |
| US09634227B1 |
Suppression of spurious modes of vibration for resonators and related apparatus and methods
Suppression of spurious modes of vibration for resonators and related apparatus and methods. A device may include a MEMS resonating structure, a substrate, and anchors between the MEMS resonating structure and the substrate. The MEMS resonating structure may have at least one main eigenmode of vibration and at least one spurious eigenmode of vibration. The anchors may be configured to suppress the response of the at least one spurious mode of vibration. |
| US09634224B2 |
Systems and methods for fabrication of superconducting circuits
In one aspect, fabricating a superconductive integrated circuit with a Josephson junction includes applying oxygen or nitrogen to at least part of a structure formed from an outer superconductive layer to passivate an artifact, if any, left from removing the portion of the outer superconductive layer. In another aspect, a first superconductive layer is deposited, a second superconductive layer is deposited on the first superconductive layer, an oxide layer is formed on the first superconductive layer, a dielectric layer is deposited on the oxide layer, a portion of the dielectric layer is removed, a first portion of the oxide layer is removed, a second oxide portion is formed in place of the first portion of the oxide layer, and a third superconductive layer is deposited on the dielectric layer and the second oxide portion. |
| US09634222B2 |
Highly conducting material
The present invention concerns electrically conductive nanocomposites. More specifically the electrical conductance of graphitic material can be improved significantly by a molecular coating that has well defined repeating structure. Even superconductivity of these materials may be possible at technologically meaningful temperatures. |
| US09634220B2 |
Fabrication method for synthesizing a BixSb2-xTe3 thermoelectric nanocompound and thermoelectric nanocompound thereby
The present invention provides a method for synthesizing a BixSb2-xTe3 thermoelectric nanocompound (0 |
| US09634219B2 |
Method for producing a thermoelectric object for a thermoelectric conversion device
A method for producing a thermoelectric object for a thermoelectric conversion device is provided. A starting material which contains elements in the ratio of a half-Heusler alloy is melted and then cast form an ingot. The ingot is heat-treated for 12 to 24 hours at a temperature of 1000° C. to 1200° C. The homogenised ingot is crushed and ground to provide a powder. The powder is cold-pressed and sintered for 0.5 to 24 hours at a temperature of 1000° C. to 1500° C. |
| US09634214B2 |
Graphite-containing substrates for LED packages
Substrates and packages for LED based light devices can incorporate a material with high thermal conductivity in at least the lateral direction (e.g., graphite or graphene) to spread heat across the surface of the substrate. A substrate or layer in a multi-layer substrate can have a graphite core disposed between ceramic sublayers that provide electrical insulation and thermal conductivity in the transverse direction. Another substrate or layer in a multi-layer substrate can be fabricated using a composite of graphite and ceramic materials. |
| US09634213B2 |
Light emitting device having dual sealing resins
Provided is a light emitting device with improved light extracting efficiency and further higher heat releasing performance. A light emitting device includes a planar lead frame having a first lead and a second lead, and includes a light emitting element mounted on the first lead, a resin frame surrounding a periphery of the light emitting element, a first sealing resin filled in the inner side of the resin frame and sealing the light emitting element, and a second sealing resin covering the resin frame and the first sealing resin. Lower end of inner surface of the resin frame is arranged only on the first lead, and at an outside of the resin frame, and the second resin member covers at least a part of the first lead and the second lead. Of the back-surface of the first lead, a region directly under the blight emitting element is exposed. |
| US09634211B2 |
Light-emitting module
Each of a plurality of semiconductor light-emitting element has, on an upper surface thereof that has a quadrilateral shape, a pair of connecting portions having different polarities from each other. The pair of connecting portions are aligned on a diagonal of the quadrilateral shape. The diagonal intersects a row direction along which the semiconductor light-emitting elements within a row are arranged. Connecting portions having identical polarity are positioned on an imaginary line parallel to the row direction. Metal wires intersect two sides extending from a corner, on the diagonal, of the upper surface of each of the semiconductor light-emitting elements when viewed from a direction perpendicular to a mounting surface of a substrate for mounting the semiconductor light-emitting elements. |
| US09634210B2 |
Optical semiconductor device production method and optical semiconductor device
There is provided a production method for an optical semiconductor device including a substrate having a silver plating layer formed on a surface and a light emitting diode bonded to the silver plating layer. The production method includes a film formation step of forming a clay film covering the silver plating layer and a connection step of electrically connecting the light emitting diode and the silver plating layer covered with the clay film by wire bonding, after the film formation step. |
| US09634209B2 |
Miniature surface mount device
A surface mount LED package includes a lead frame carrying a plurality of LEDs and a plastic casing at least partially encasing the lead frame. The lead frame includes an electrically conductive chip carrier and first, second, and third electrically conductive connection parts separate from the electrically conductive chip carrier. Each of the first, second and third electrically conductive connection parts has an upper surface, a lower surface, and a connection pad on the upper surface. The plurality of LEDs are disposed on an upper surface of the electrically conductive chip carrier. Each LED has a first electrical terminal electrically coupled to the electrically conductive chip carrier. Each LED has a second electrical terminal electrically coupled to the connection pad of a corresponding one of the first, second, and third electrically conductive connection parts. |
| US09634204B2 |
Resin molding, surface mounted light emitting apparatus and methods for manufacturing the same
The present invention provides a surface mounted light emitting apparatus which has long service life and favorable property for mass production, and a molding used in the surface mounted light emitting apparatus.The surface mounted light emitting apparatus comprises the light emitting device 10 based on GaN which emits blue light, the first resin molding 40 which integrally molds the first lead 20 whereon the light emitting device 10 is mounted and the second lead 30 which is electrically connected to the light emitting device 10, and the second resin molding 50 which contains YAG fluorescent material and covers the light emitting device 10. The first resin molding 40 has the recess 40c comprising the bottom surface 40a and the side surface 40b formed therein, and the second resin molding 50 is placed in the recess 40c. The first resin molding 40 is formed from a thermosetting resin such as epoxy resin by the transfer molding process, and the second resin molding 50 is formed from a thermosetting resin such as silicone resin. |
| US09634202B2 |
Light emitting device
A light emitting device includes a substrate, an electrode connection layer, an epitaxial structure and a plurality of pads. The substrate has an upper surface, a lower surface and a plurality of conductive through holes. The electrode connection layer is disposed on the upper surface of the substrate, and connects with the conductive through holes. An edge of the electrode connection layer is aligned with an edge of the substrate. The epitaxial structure is disposed on the electrode connection layer and electrically connected to the electrode connection layer. The pads are disposed on the lower surface of the substrate and connect with the conductive through holes. |
| US09634201B2 |
Light emitting device with nanostructured phosphor
Embodiments of the invention include a light emitting device (LED 10), a first wavelength converting material (13, in a matrix 14 to form a layer 12), and a second wavelength converting material (forming layer 16). The first wavelength converting material includes a nanostructured wavelength converting material. The nanostructured wavelength converting material includes particles having at least one dimension that is no more than 100 nm in length. The first wavelength converting material (13) is spaced apart from the light emitting device (10). |
| US09634198B2 |
Quantum dot chip on board
Quantum dots used to modify the spectral output of an LED exhibit less of a performance decrease (due to increased temperature) when incorporated in a chip on board (COB) as compared to conventional LED packages. A ceramic ring may be used to shield the quantum dots from the heat associated with connecting electrical leads to pads on the COB. The upper surface of the ceramic ring may be sealed with a glass disk or other transparent material. |
| US09634188B2 |
LED element
In order to achieve appropriate light distribution using light distribution characteristics resulting from diffraction while improving light extraction efficiency using a diffraction effect, an LED element provided with: a substrate in which periodic depressions or projections are formed on a front surface; a semiconductor laminated part that is formed on the front surface of the sapphire substrate, includes a light-emitting layer, and is formed of a group-III nitride semiconductor; and a reflecting part that reflects at least a part of light emitted from the light-emitting layer toward the front surface of the substrate, the LED element obtaining a diffraction effect of light emitted from the light-emitting layer at an interface between the substrate and the semiconductor laminated part, wherein a relation of 1/2×λ≦P≦16/9×λ is satisfied, where a period of the depressions or the projections is P and a peak wavelength of the light emitted from the light-emitting layer is λ. |
| US09634187B2 |
Flip chip light emitting diode having trnsparent material with surface features
Flip chip LEDs include a transparent substrate or carrier having an active material attached thereto and having a number of electrodes disposed along a common surface of the active material. The substrate may include a number of surface features disposed along a first surface adjacent the active material for improving light extraction from the active material, and includes a number of surface features along a second surface opposite the first surface for minimizing internal reflection of light through the substrate, thereby improving light extraction from the transparent substrate. The surface features on both surfaces may be arranged having a random or ordered orientation relative to one another. A plurality of such flip chip LEDs may be physically packaged together in a manner providing electrical connection with the same for a lighting end-use application. |
| US09634186B2 |
Method of manufacturing light emitting device package
A method of manufacturing a light emitting device package includes forming on a growth substrate a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer. First and second electrodes are formed on the light emitting structure to be connected to the first and second conductivity-type semiconductor layers, respectively. A first bonding layer is formed on the light emitting structure, and is polished A second bonding layer is formed on the polished first bonding layer, and a support substrate is bonded to the light emitting structure using the first and second bonding layers. |
| US09634185B2 |
Optical semiconductor device and method for making the device
An optical semiconductor device comprises, on a substrate, a fin of diamond-cubic semiconductor material and, at the base of the fin, a slab of that semiconductor material, in a diamond-hexagonal structure, that extends over the full width of the fin, the slab being configured as an optically active material. This semiconductor material can contain silicon. A method for manufacturing the optical semiconductor device comprises annealing the sidewalls of the fin, thereby inducing a stress gradient along the width of the fin. |
| US09634182B2 |
Semiconductor structures having active regions including indium gallium nitride, methods of forming such semiconductor structures, and related light emitting devices
Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs. |
| US09634180B2 |
Method for forming semiconductor device package with slanting structures
A method for forming semiconductor device package comprises providing a substrate with via contact pads and via through holes through said substrate, terminal pads on a bottom surface of said substrate and an exposed type through hole through said substrate. A die is provided with bonding pads thereon and an exposed type pad on a bottom surface of said die. A reflective layer is formed on an upper surface of the substrate. The die is adhered on the substrate. A dry film is formed on a top of the die as a slanting structure. A re-distribution layer conductive trace is formed by sputtering and E-plating on an upper surface of the slanting structure. |
| US09634178B1 |
Method of using laser welding to ohmic contact of metallic thermal and diffusion barrier layer for foil-based metallization of solar cells
Methods of fabricating solar cells using a metal-containing thermal and diffusion barrier layer in foil-based metallization approaches, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes forming a plurality of semiconductor regions in or above a substrate. The method also includes forming a metal-containing thermal and diffusion barrier layer above the plurality of semiconductor regions. The method also includes forming a metal seed layer on the metal-containing thermal and diffusion barrier layer. The method also includes forming a metal conductor layer on the metal seed layer. The method also includes laser welding the metal conductor layer to the metal seed layer. The metal-containing thermal and diffusion barrier layer protects the plurality of semiconductor regions during the laser welding. |
| US09634174B2 |
Photoelectric conversion apparatus and electronic device
A photoelectric conversion apparatus includes a substrate 13 and a photodiode 9 in which a first semiconductor layer 25, a second semiconductor layer 26 and a third semiconductor layer 27 are laminated on the substrate 13 in the stated order. The second semiconductor layer 26 is an i-type semiconductor layer, and one of the first semiconductor layer 25 and the third semiconductor layer 27 is an n-type semiconductor layer, and the other is a p-type semiconductor layer. Also, the first semiconductor layer 25 is covered by the second semiconductor layer 26. |
| US09634173B2 |
Photodetector for determining light wavelengths
There is described a photodetector comprising a semiconductor material having at least a region substantially depleted of free moving carriers, the photodetector comprising: a substrate of one of n-type and p-type; at least one charge collector along a surface of the substrate and having a doping-type opposite from the substrate; a substrate contact along the surface of the substrate spaced apart from the at least one charge collector to allow current to flow between the at least one charge collector and the substrate contact; and at least one non-conductive electrode positioned along the surface of the substrate in an alternating sequence with the at least one charge collector, and separated from the substrate by an insulator, and adapted to apply an electric potential to the substrate and cause charge carriers generated therein by application of a light source to advance towards the at least one charge collector due to the effects of an electric field, such that the at least one charge collector can measure carrier concentration within the substrate. |
| US09634172B1 |
Inverted metamorphic multijunction solar cell with multiple metamorphic layers
The disclosure describes multi-junction solar cell structures that include two or more graded interlayers. |
| US09634171B2 |
Monolithically integrated thin-film electronic conversion unit for lateral multijunction thin-film solar cells
An integrated thin-film lateral multi-junction solar device and fabrication method are provided. The device includes, for instance, a substrate, and a plurality of stacks extending vertically from the substrate. Each stack may include layers, and be electrically isolated against another stack. Each stack may also include an energy storage device above the substrate, a solar cell above the energy storage device, a transparent medium above the solar cell, and a micro-optic layer of spectrally dispersive and concentrating optical devices above the transparent medium. Furthermore, the device may include a first power converter connected between the energy storage device and a power bus, and a second power converter connected between the solar cell and the power bus. Further, different solar cells of different stacks may have different absorption characteristics. |
| US09634167B2 |
Solar cell module
A solar cell module comprising: a first protective member having a curved surface having a prescribed radius of curvature set in at least a first direction; a first filling material arranged upon the first protective member; a plurality of solar cell strings arranged in the first direction upon the first filling material and connected in parallel to each other; a second filling material arranged upon the solar cell strings; and a second protective member arranged upon the second filling material. The solar cell strings have connected in series a plurality of solar cells that are arranged in a second direction. The solar cells have end cross-sections along at least the first direction that have a waveform shape. |
| US09634152B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device includes memory blocks each configured to comprise a pair of channels, each channel including a pipe channel formed in a pipe gate of the memory block and a drain-side channel and a source-side channel coupled to the pipe channel; first slits placed between the memory blocks adjacent to other memory blocks; and a second slit placed between the source-side channel and the drain-side channel of each pair of channels. |
| US09634151B1 |
High voltage junctionless field effect device and its method of fabrication
A structure and a method of fabrication are disclosed of a high voltage junctionless field effect device. A channel layer and a barrier layer are formed sequentially underneath the gate structure. The width of energy band gap of the barrier layer is wider than that of the channel layer. Thus the two dimensional electron gas (2-DEG) generated in the interface between the channel layer and the barrier layer of this junctionless field effect device has higher electron mobility. The structure of the device of this disclosure has a higher breakdown voltage which is advantageous for a high voltage junctionless field device. The structure offers advantages in device performance and reliability. |
| US09634146B2 |
Method for manufacturing assembly of flexible display device and assembly of flexible display device manufactured with same
The present invention provides a method for manufacturing an assembly of a flexible display device and an assembly of a flexible display device manufactured therewith. The method includes: (1) providing a flexible base (22); (2) forming a graphene layer (24) on the flexible base (22); (3) forming a protective layer (26) on the graphene layer (24); (4) forming a low-temperature polysilicon layer (28) on the protective layer (26). The method for manufacturing an assembly of a flexible display device and the assembly of the flexible display device manufactured therewith according to the present invention are such that the graphene layer is formed on the flexible base to effectively conduct out heat generated in the process of forming the low-temperature polysilicon layer so as to protect the flexible base from being affected by the heat without increasing the thickness of the protective layer thereby reducing internal stress and facilitating the realization of thinning. |
| US09634140B2 |
Fabricating metal source-drain stressor in a MOS device channel
Exemplary embodiments provide methods and systems for fabricating a metal source-drain stressor in a MOS device channel having improved tensile stress. Aspects of exemplary embodiment include forming a recess in source and drain areas; forming a metal contact layer on surfaces of the recess that achieves low contact resistivity; forming a metallic diffusion barrier over the metal contact layer; forming a layer M as an intimate mixture of materials A and B that substantially fills the recess; capping the layer M with a capping layer so that layer M is fully encapsulated and the capping layer prevents diffusion of A and B; and forming a compound AxBy within the layer M via a thermal reaction resulting in a reacted layer M comprising the metal source-drain stressor. |
| US09634139B1 |
Dual-well metal oxide semiconductor (MOS) device and manufacturing method thereof
A dual-well metal oxide semiconductor (MOS) device includes: a semiconductor substrate, an active layer, a first conductive type well, a first conductive type body region, a second conductive type well, a gate, a second conductive type lightly doped diffusion (LDD) region, a second conductive type source, a second conductive type connection region, and a second conductive type drain. The second conductive type well is connected to the first conductive type well in a lateral direction, and a PN junction is formed therebetween right below the gate. The second conductive type connection region is formed right below a spacer of the gate, and is connected to the second conductive type source in a lateral direction to avoid OFF-channel. The second conductive type connection region is formed by a tilt-angle ion implantation process step through the spacer. |
| US09634138B1 |
Field-effect transistor (FET) devices employing adjacent asymmetric active gate / dummy gate width layout
Field-Effect Transistor (FET) devices employing an adjacent asymmetric active gate/dummy gate width layout are disclosed. In an exemplary aspect, a FET cell is provided that includes a FET device having an active gate, a source region, and a drain region. The FET cell also includes an isolation structure comprising a dummy gate over a diffusion break located adjacent to one of the source region and the drain region. The FET cell has an asymmetric active gate/dummy gate width layout in that a width of the active gate is larger than a width of the adjacent dummy gate. The increased width of the active gate provides increased gate control and the decreased width of the dummy gate increases isolation from the dummy gate, thus reducing sub-threshold leakage through the dummy gate. |
| US09634136B2 |
Semiconductor device
A semiconductor device according to an embodiment includes a SiC layer having a first plane and a second plane, a first SiC region of a first conductivity type which is provided in the SiC layer, first and second pillar regions of a second conductivity type, third and fourth pillar regions of a second conductivity type which are provided between the first and second pillar regions and the first plane, a gate electrode provided between the third pillar region and the fourth pillar region, first and second body regions of the second conductivity type, a gate insulating film, fifth and sixth pillar regions provided between the third and fourth pillar regions and the gate electrode, first and second source regions of the first conductivity type. |
| US09634134B2 |
Embedded transistor
An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell. A dielectric growth modifier may be implanted into sidewalls of the trench in order to tune the thickness of the gate dielectric. |
| US09634133B1 |
Method of forming fin structure on patterned substrate that includes depositing quantum well layer over fin structure
Embodiments provide a quantum well device and the method for forming this device with high mobility and higher punch through voltages. For forming the quantum well device, a buffer layer can be formed on a patterned substrate of a quantum well device. A fin-like structure can be formed through an etching process performed to the buffer layer. A quantum well layer, a barrier layer, a cover layer and a dielectric layer can be successively deposited on the buffer layer and surface of the fin-like structure. A metal layer can then be formed on the surface of the said dielectric layer. Metal gate electrode and gate dielectric layer can be formed on the metal layer and dielectric layer. The cover layer, the barrier layer and the quantum well can then be etched to form recessed source and drain regions. Such a quantum well device can have better performance and reliability. |
| US09634128B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, an insulating region, and a third semiconductor region of the first conductivity type. The first semiconductor region is provided between the first electrode and the second electrode, and is in contact with the first electrode. The second semiconductor region is provided between the first semiconductor region and the second electrode. The second semiconductor region is in contact with the second electrode. The insulating region extends in a direction from the second electrode toward the first semiconductor region. The insulating region is in contact with the second electrode. The third semiconductor region is provided between the second semiconductor region and the insulating region. |
| US09634126B2 |
Formation of high quality Fin in 3D structure by way of two-step implantation
The present disclosure discloses a method of fabricating a semiconductor device. A fin structure is formed over a substrate. The fin structure contains a semiconductor material. A first implantation process is performed to a region of the fin structure to form a fin seed within the region of the fin structure. The fin seed has a crystal structure. The first implantation process is performed at a process temperature above about 100 degrees Celsius. A second implantation process is performed to the region of the fin structure to cause the region of the fin structure outside the fin seed to become amorphous. The second implantation process is performed at a process temperature below about 0 degrees Celsius. Thereafter, an annealing process is performed to recrystallize the region of the fin structure via the fin seed. |
| US09634125B2 |
Fin field effect transistor device and fabrication method thereof
A field effect transistor (FinFET) device includes a substrate, a fin structure, a shallow trench isolation and a gate structure. The fin structure is formed on a surface of the substrate and includes a base fin structure and an epitaxial fin structure formed on the base fin structure. The shallow trench isolation structure is formed on the surface of the substrate and includes a peripheral zone and a concave zone. The peripheral zone physically contacts with the fin structure. The gate structure is disposed on the epitaxial fin structure perpendicularly. A method of fabricating the aforementioned field effect transistor is also provided. |
| US09634124B2 |
Interlayer dielectric for non-planar transistors
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor. |
| US09634119B2 |
Semiconductor devices utilizing partially doped stressor film portions
A method includes providing a gate structure over a semiconductor substrate and forming a source/drain region associated with the gate structure by etching an opening in the semiconductor substrate, performing a first epitaxial growth process while an entirety of a sidewall of the opening is exposed to grow a first epitaxy material in the opening. The first epitaxial growth process is free of a first dopant impurity. A second epitaxial growth process is performed after first epitaxial growth process to grow a second epitaxy material on the first epitaxy material. The second epitaxy material has the first dopant impurity at a first concentration. Further, a third epitaxial growth process is performed after the second epitaxial growth process that includes introducing the first dopant impurity at a second concentration, the second concentration greater than the first concentration. |
| US09634115B2 |
Methods of forming a protection layer on a semiconductor device and the resulting device
One illustrative method disclosed herein includes, among other things, forming a first high-k protection layer on the source/drain regions and adjacent the sidewall spacers of a transistor device, removing a sacrificial gate structure positioned between the sidewall spacers so as to thereby define a replacement gate cavity, forming a replacement gate structure in the replacement gate cavity, forming a second high-k protection layer above an upper surface of the spacers, above an upper surface of the replacement gate structure and above the first high-k protection layer, and removing portions of the second high-k protection layer positioned above the first high-k protection layer. |
| US09634109B2 |
Semiconductor device having dual work function gate structure, method for fabricating the same, transistor circuit having the same, memory cell having the same, and electronic device having the same
A semiconductor device including a substrate in which a trench is formed, a first impurity region and a second impurity region formed in the substrate separated from each other by the trench, a gate electrode formed to fill a lower part of the trench, and a capping layer formed over the gate electrode to fill an upper part of the trench. The gate electrode includes a first work function liner formed over a bottom surface and sidewalls of the lower part of the trench without overlapping with the first impurity region and the second impurity region, and including an aluminum-containing metal nitride; and a second work function liner formed over the sidewalls of the lower part of the trench over the first work function liner, overlapping with the first impurity region and the second impurity region, and including a silicon-containing non-metal material. |
| US09634106B2 |
Doped metal germanide and methods for making the same
In one aspect, methods of silicidation and germanidation are provided. In some embodiments, methods for forming metal silicide can include forming a non-oxide interface, such as germanium or solid antimony, over exposed silicon regions of a substrate. Metal oxide is formed over the interface layer. Annealing and reducing causes metal from the metal oxide to react with the underlying silicon and form metal silicide. Additionally, metal germanide can be formed by reduction of metal oxide over germanium, whether or not any underlying silicon is also silicided. In other embodiments, nickel is deposited directly and an interface layer is not used. In another aspect, methods of depositing nickel thin films by vapor phase deposition processes are provided. In some embodiments, nickel thin films are deposited by ALD. |
| US09634103B2 |
CMOS in situ doped flow with independently tunable spacer thickness
A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions. |
| US09634102B2 |
Nonvolatile memory devices having single-layered floating gates
A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. A first source and a second source are disposed in the substrate and spaced apart from the drain mesa. A first floating gate overlaps with a first sidewall surface of the drain mesa and extends onto the first source, and a second floating gate overlaps with a second sidewall surface of the drain mesa and extends onto the second source. Related methods are also provided. |
| US09634097B2 |
3D NAND with oxide semiconductor channel
Disclosed herein are 3D NAND memory devices having an oxide semiconductor vertical NAND channel and methods for forming the same. The oxide semiconductor may have a crystalline structure. The channel of the vertically-oriented NAND string may be cylindrically shaped. The crystalline structure has an axis that may be aligned crystalline with respect to the cylindrical shape of the vertically-oriented channel substantially throughout the vertically-oriented channel. The crystalline structure may have a first axis that is aligned parallel to the vertical channel, a second axis that is aligned perpendicular to a surface of the cylindrically shaped channel, etc. |
| US09634095B2 |
Semiconductor device and method for manufacturing the same
In a semiconductor device, a first conductivity-type first semiconductor region that abuts on a side surface of a contact trench adjacent to an opening portion of the contact trench, and has a higher impurity concentration than that of a second semiconductor layer is formed. Also, a second conductivity-type second semiconductor region that abuts on a bottom surface of the contact trench and a side surface of the contact trench adjacent to the bottom surface of the contact trench, and has a higher impurity concentration than that of a first semiconductor layer is formed. A first electrode that is connected electrically with the first semiconductor region and the second semiconductor region is disposed in the contact trench. Even when the semiconductor device is miniaturized by reducing the width of the contact trench, a breakage of the semiconductor device when switched from an on-state to an off-state is reduced. |
| US09634093B2 |
Method for fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask. |
| US09634090B2 |
Preventing buried oxide gouging during planar and FinFET processing on SOI
A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a material stack having an active semiconductor layer, an insulator layer, and an etch stop layer between the active semiconductor layer and the insulator layer; forming a fin-array from the active semiconductor layer; patterning the fin-array; and fabricating a FinFET device from the patterned fin-array; where the etch stop layer is resistant to processes the etch stop layer is exposed to during the forming, patterning, and fabricating operations, such that the etch stop layer and the insulator layer are not damaged during the forming, patterning, and fabricating operations. |
| US09634084B1 |
Conformal buffer layer in source and drain regions of fin-type transistors
Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor. |
| US09634081B2 |
Methods for producing polysilicon resistors
A method for producing a polysilicon resistor device may include: forming a polysilicon layer; implanting first dopant atoms into at least a portion of the polysilicon layer, wherein the first dopant atoms include deep energy level donors; implanting second dopant atoms into said at least a portion of said polysilicon layer; and annealing said at least a portion of said polysilicon layer. |
| US09634079B2 |
Organic electroluminescent device and electronic apparatus
An organic electroluminescent device includes a first transistor, a power supply line layer connected to one current terminal of the first transistor, a capacitive element including a first capacitive electrode connected to a gate of the first transistor, and a second capacitive electrode, a signal line, and a pixel electrode connected to the other current terminal of the first transistor, the first capacitive electrode is provided on a layer over the gate of the first transistor, and the power supply line layer is provided on a layer between the first capacitive electrode and the signal line. |
| US09634076B2 |
Organic light-emitting display apparatus and method of manufacturing the same
An organic light-emitting display apparatus includes a substrate; a thin film transistor (TFT) on the substrate; a first interlayer insulating layer between a gate electrode and the source electrode and between a drain electrode and the source electrode of the TFT and including an inorganic material; a second interlayer insulating layer between the first interlayer insulating layer and the source electrode and between the first interlayer insulating layer and the drain electrode and including an organic material; a first organic layer on the source electrode and the drain electrode; a capacitor, a second electrode, and the first interlayer insulating layer between the first electrode and the second electrode; a pixel electrode in an aperture in the second interlayer insulating layer adjacent to the thin film transistor and the capacitor and coupled to the source electrode or the drain electrode; an organic emission layer; and an opposite electrode. |
| US09634074B2 |
Transparent display substrates, transparent display devices and methods of manufacturing transparent display devices
A transparent display substrate including a base substrate having a pixel area and a transmission area, a thickness of the base substrate at the transmission area being less than a thickness of the base substrate at the pixel area, a pixel circuit at the pixel area of the base substrate, an insulation structure covering the pixel circuit, the insulation structure having an opening or a concave portion at the transmission area of the base substrate, and a pixel electrode at the pixel area of the base substrate and extending at least partially through the insulation structure to be electrically connected to the pixel circuit. |
| US09634068B2 |
Organic light emitting display devices and methods of manufacturing organic light emitting display devices
An organic light emitting display device and a method of manufacturing an organic light emitting display device are disclosed. The organic light emitting display device includes a first substrate, on which a display region and a non-display region surrounding the display region are defined, a second substrate disposed opposite to the first substrate, an organic light emitting element disposed in the display region between the first substrate and the second substrate, a third substrate disposed opposite to the second substrate, and a microphone disposed between the second substrate and the third substrate. |
| US09634066B2 |
Method for making organic light emitting diode array
The disclosure relates to a method of making organic light emitting diode array. A base defining a plurality of convexities is provided. A number of first electrodes are applied on the plurality of convexities. At least one hole injection layer is applied on the first electrodes. A number of hole transport layers are transfer printed on the at least one hole injection layer. Three of the hole transport layers, that correspond to the same pixel unit, have different thickness. A number of electroluminescent layers are applied on the hole transport layers. A patterned second insulative layer is made among the convexities to expose the electroluminescent layers. A second electrode is electrically connected to the electroluminescent layers. |
| US09634065B2 |
Solid-state image pickup device and manufacturing method thereof, and electronic apparatus
Provided is a solid-state image pickup device that makes it possible to enhance image quality, and a manufacturing method thereof, and an electronic apparatus. A solid-state image pickup device includes a pixel section that includes a plurality of pixels, the pixels each including one or more organic photoelectric conversion sections, wherein the pixel section includes an effective pixel region and an optical black region, and the organic photoelectric conversion sections of the optical black region include a light-shielding film and a buffer film on a light-incidence side. |
| US09634063B2 |
Method, system and device for recessed contact in memory array
Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device. |
| US09634060B2 |
Stacked solid-state image sensor and imaging apparatus including the same
An image sensor includes a first semiconductor chip having a first surface and a second surface, the first semiconductor chip a including an array of unit pixels configured to capture light corresponding to an image and to generate image signals based on the captured light; and a second semiconductor chip having a first surface and a second surface, the second semiconductor chip including first peripheral circuits configured to control the array of pixels and receive the generated image signals, the first peripheral circuits including a vertical scanning circuit, a horizontal scanning circuit, and a signal read-out circuit, the first semiconductor chip being stacked on the second semiconductor chip, the first semiconductor chip not being smaller than the second semiconductor chip. |
| US09634056B2 |
Digital x-ray detector and method for repairing a bad pixel thereof
Provided herein is a digital x-ray detector and a method for repairing a bad pixel thereof, the detector including a substrate; a gate line and a data line formed on the substrate such that the gate line and the data line intersect each other to form a pixel domain; a thin film transistor formed within the pixel domain such that the thin film transistor is adjacent to a portion where the gate line and the data line intersect each other, the thin film transistor including a gate electrode, an active layer, a source electrode and a drain electrode; a PIN diode which is formed within the pixel domain and which includes a lower electrode connected to the source electrode of the thin film transistor, a PIN layer formed on the lower electrode, and an upper electrode formed on the PIN layer; a bias line connected to the upper electrode of the PIN diode; and a scintillator arranged above the PIN diode, wherein on at least one of a surface of the drain electrode which faces the PIN diode and a surface of the PIN diode which faces the drain electrode, a groove is formed such that it expands a distance between the drain electrode and the PIN diode. |
| US09634055B2 |
Radiation detectors and methods of fabricating radiation detectors
Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps. The method also includes growing a passivation oxide layer on a top of the polished first surface and depositing patterned metal contacts on a top of the passivation oxide layer. The method further includes applying a protecting layer on the patterned deposited metal contacts, etching a second surface of the semiconductor and applying a monolithic cathode electrode on the etched second surface of the semiconductor. The method additionally includes removing the protecting layer from the patterned metal contacts on the first surface, wherein the patterned metal contacts are formed from one of (i) reactive metals and (ii) stiff-rigid metals for producing inter-band energy-levels in the passivation oxide layer. |
| US09634046B2 |
Semiconductor packages including electrical insulation features
A semiconductor package can include a substrate and a semiconductor chip inside the semiconductor package mounted on the substrate. A first conductive pattern can be on the substrate inside the semiconductor package and can be electrically connected to an input/output of the semiconductor chip. A holder can be on the substrate, where the holder can be configured to provide a recess in which the semiconductor chip is located. An electrically insulating adhesive layer can be configured to electrically insulate the first conductive pattern from an Electric Static Discharge (ESD) source located outside the semiconductor package and configured to adhere the holder to the substrate. |
| US09634042B2 |
Display substrate, method for manufacturing the same, and display device
The present disclosure provides a display substrate, a method for manufacturing the display substrate, and a display device. An intermediate layer is formed on an organic base plate, a thermal expansion coefficient of the intermediate layer is smaller than that of the organic base plate and greater than that of an inorganic thin film, and the inorganic thin film is formed on the intermediate layer. |
| US09634039B2 |
SiON gradient concept
Embodiments of the present disclosure generally relate to methods and devices for use of low temperature polysilicon (LTPS) thin film transistors in liquid crystal display (LCD) and organic light-emitting diode (OLED) displays. |
| US09634038B2 |
Display backplane having multiple types of thin-film-transistors
There is provided a TFT backplane having at least one TFT with oxide active layer and at least one TFT with poly-silicon active layer. In the embodiments of the present disclosure, at least one of the TFTs implementing the circuit of pixels in the active area is an oxide TFT (i.e., TFT with oxide semiconductor) while at least one of the TFTs implementing the driving circuit next to the active area is a LTPS TFT (i.e., TFT with poly-Si semiconductor). |
| US09634036B1 |
Metal oxide thin-film transistor, method of fabricating the same, and array substrate
The present disclosure proposes a metal oxide thin-film transistor, a method of fabricating the metal oxide thin-film transistor, and an array substrate. The metal oxide TFT includes a glass substrate, a gate, a gate insulating layer, a metal oxide active layer, an etching blocking layer with a source hole and a drain hole thereon, a blocking spread layer including a source blocking layer and a drain blocking layer, a source, and a drain. The blocking spread layer is doped with boron ions and/or phosphorus ions of predetermined concentration. |
| US09634035B2 |
Display device and method of manufacturing the same
A display device includes: a first wiring line and a second wiring line separated from each other on a substrate; a gate insulating layer on the first wiring line and the second wiring line; a step difference compensation pattern between the first wiring line and the second wiring line on the gate insulating layer; a protective layer on the step difference compensation pattern; and a pixel electrode on the protective layer. |
| US09634033B2 |
Thin film transistor and method of manufacturing the same, array substrate and display apparatus
The present disclosure discloses a thin film transistor comprising: an active layer; an etching barrier layer arranged on the active layer and formed with a plurality of via holes therein; and a source electrode and a drain electrode arranged on the etching barrier layer, wherein the source electrode comprises at least two sub source electrodes and the drain electrode comprises at least two sub drain electrodes; and the sub source electrodes and the sub drain electrodes constitute at least two parallel sub-switches, each of which comprises a sub source electrode and a sub drain electrode, and the sub source electrode and the sub drain electrode are electrically connected to the active layer through the via holes in the etching barrier layer, respectively. The present disclosure further discloses a method of manufacturing a thin film transistor, an array substrate and a display apparatus. The present disclosure employs a multi-channel design with which the DGS problem due to an incomplete active layer is solved by using a plurality of parallel sub-switches, ensuring the normal operation of the pixel and thus increasing yield and useful life of product. |
| US09634029B2 |
Thin film transistor substrate and display device having same
A thin film transistor (TFT) substrate includes a substrate which is a flexible substrate, and a TFT structure disposed on the substrate and including a gate layer, a gate insulator layer, a first channel island and a second channel island. The gate layer is disposed on the substrate and including a first gate electrode and a second gate electrode electrically connected to each other. The first and second gate electrodes are parts of the same TFT structure. The gate insulator layer covers the first and second gate electrodes. The first and second channel islands are disposed on the gate insulator layer and respectively correspond to the first and second gate electrodes. The source and drain layer is disposed on the gate insulator layer and next to the first and second channel islands, wherein the source and drain layer partially covers top surfaces of the first and second channel islands. |
| US09634022B2 |
Three dimensional semiconductor device
A semiconductor device includes alternately stacked conductive layers and the insulating layers, an opening passing through the conductive layers and insulating layers, a first semiconductor layer formed in the opening, a second semiconductor layer formed in the first semiconductor layer, a capping layer formed in the opening and disposed over the first semiconductor layer and the second semiconductor layer, and a liner layer interposed between the first semiconductor layer and the second semiconductor layer and protruding through the capping layer relative to the first semiconductor layer and the second semiconductor layer. |
| US09634020B1 |
Method of making embedded memory device with silicon-on-insulator substrate
A method of forming a semiconductor device with memory cells and logic devices on the same silicon-on-insulator substrate. The method includes providing a substrate that includes silicon, a first insulation layer directly over the silicon, and a silicon layer directly over the first insulation layer. Silicon is epitaxially grown on the silicon layer in a first (memory) area of the substrate and not in a second (logic device) area of the substrate such that the silicon layer is thicker in the first area of the substrate relative to the second area of the substrate. Memory cells are formed in the first area of the substrate, and logic devices are formed in the second area of the substrate. |
| US09634019B1 |
Non-volatile split gate memory cells with integrated high K metal gate, and method of making same
A method of forming a pair of memory cells that includes forming a polysilicon layer over and insulated from a semiconductor substrate, forming a pair of conductive control gates over and insulated from the polysilicon layer, forming first and second insulation layers extending along inner and outer side surfaces of the control gates, removing portions of the polysilicon layer adjacent the outer side surfaces of the control gates, forming an HKMG layer on the structure and removing portions thereof between the control gates, removing a portion of the polysilicon layer adjacent the inner side surfaces of the control gates, forming a source region in the substrate adjacent the inner side surfaces of the control gates, forming a conductive erase gate over and insulated from the source region, forming conductive word line gates laterally adjacent to the control gates, and forming drain regions in the substrate adjacent the word line gates. |
| US09634017B1 |
Semiconductor structure including a nonvolatile memory cell and method for the formation thereof
A semiconductor structure includes a nonvolatile memory cell including a first nonvolatile bit storage element and a second nonvolatile bit storage element which have a common source region provided in a semiconductor material and a common control gate structure. Each nonvolatile bit storage element includes a drain region, a channel region, a select gate structure, a floating gate structure and an erase gate structure. The channel region has a select gate side portion and a floating gate side portion. The select gate structure is provided at the select gate side portion of the channel region and the floating gate structure is provided at the floating gate side portion of the channel region. The erase gate structure is provided above the select gate structure and adjacent the floating gate structure. The control gate structure extends above the floating gate structures of the first and second nonvolatile bit storage elements. |
| US09634015B2 |
Antifuse-type one time programming memory cell and array structure with same
An antifuse-type one time programming memory cell has following structures. A first doped region, a second doped region, a third doped region and a fourth doped region are formed in a well region. A gate oxide layer covers a surface of the well region. A first gate is formed on the gate oxide layer and spanned over the first doped region and the second doped region. The first gate is connected with a word line. A second gate is formed on the gate oxide layer and spanned over the third doped region and the fourth doped region. The second gate is connected with the word line. A third gate is formed on the gate oxide layer and spanned over the second doped region and the third doped region. The third gate is connected with an antifuse control line. |
| US09634013B2 |
Contact for semiconductor fabrication
A semiconductor device includes a substrate, a fin structure on the substrate, the fin structure comprising a doped region, a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region, and a conductive plug that contacts the doped region and a top of the gate. |
| US09634010B2 |
Field effect transistor device spacers
A method for forming field effect transistors comprises forming a first dummy gate stack over a first fin, forming a second dummy gate stack over a second fin, depositing a first layer of spacer material on the first dummy gate stack, the first fin, the second dummy gate stack, and the second fin, patterning a first masking layer on the first dummy gate stack and the first fin, etching to remove portions of the first layer of spacer material and form a spacer adjacent to the second dummy gate stack, removing the first masking layer, epitaxially growing a silicon material on the second fin, depositing a layer of oxide material on the first layer of spacer material, the first epitaxial material and the second dummy gate stack, and depositing a second layer of spacer material on the layer of oxide material. |
| US09634004B2 |
Forming reliable contacts on tight semiconductor pitch
Semiconductor devices include a passivating layer over a pair of fins. A barrier extends through the passivating layer and between the pair of fins and that electrically isolates the fins. Electrical contacts are formed through the passivating layer to the fins. The electrical contacts directly contact sidewalls of the barrier. |
| US09634001B2 |
System and methods for converting planar design to FinFET design
A FinFET structure layout includes a semiconductor substrate comprising a plurality of FinFET active areas, and a plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a gate having a gate length parallel to the semiconductor substrate and perpendicular to length of the plurality of fins within each FinFET active area of the plurality of FinFET active areas. The FinFET structure layout further includes a plurality of metal features connecting a source region or a drain region of a portion of the plurality of FinFET active areas to a plurality of contacts. The plurality of metal features includes a plurality of metal lines parallel to a FinFET channel direction and a plurality of metal lines parallel to a FinFET channel width direction. |
| US09634000B2 |
Partially isolated fin-shaped field effect transistors
A transistor device and a method for forming a fin-shaped field effect transistor (FinFET) device, with the channel portion of the fins on buried silicon oxide, while the source and drain portions of the fins on silicon. An example method includes receiving a wafer with a silicon layer electrically isolated from a silicon substrate by a buried oxide (BOX) layer. The BOX layer is in physical contact with the silicon layer and the silicon substrate. The method further comprises implanting a well in the silicon substrate and forming vertical sources and drains over the well between dummy gates. The vertical sources and drains extend through the BOX layer, fins, and a portion of the dummy gates. |
| US09633999B1 |
Method and structure for semiconductor mid-end-of-line (MEOL) process
A method of forming a semiconductor device provides a precursor that includes a substrate having first and second regions, wherein the first region includes an insulator and the second region includes source, drain, and channel regions of a transistor. The precursor further includes gate stacks over the insulator, and gate stacks over the channel regions. The precursor further includes a first dielectric layer over the gate stacks. The method further includes partially recessing the first dielectric layer; forming a second dielectric layer over the recessed first dielectric layer; and forming a contact etch stop (CES) layer over the second dielectric layer. In an embodiment, the method further includes forming gate via holes over the gate stacks, forming source and drain (S/D) via holes over the S/D regions, and forming vias in the gate via holes and S/D via holes. |
| US09633993B1 |
Bipolar SCR
A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second polarity different from the first polarity; a collector region having the first polarity and lying under the base region; an anode region having the second polarity; a first sinker region having the first polarity and contacting the collector region, wherein the anode region is between the first sinker region and the base region; and a second sinker region having the first polarity and contacting the collector region, the second sinker region lying between the anode region and the base region, wherein an extension of the anode region extends under a portion of the second sinker region. |
| US09633989B2 |
ESD protection device
An ESD protection device includes a zener diode, and a series circuit of diodes and a series circuit of diodes that are connected in parallel with the zener diode. At the connection point between the diodes, an Al electrode film is formed on the surface of a Si substrate, and at the connection point between diodes, an Al electrode film is formed on the surface of the Si substrate. The diodes are formed on the surface of the Si substrate, and the diodes are formed in the thickness direction of the Si substrate. The Si substrate has a longitudinal direction and a shorter direction orthogonal to the longitudinal direction in planar view, and the Al electrode films are formed respectively at both ends in the shorter direction of the Si substrate. Thus, provided is an ESD protection device which suppresses the ESL, and keeps the clamp voltage low. |
| US09633987B2 |
Integrated circuit cell library for multiple patterning
A method is disclosed for defining a multiple patterned cell layout for use in an integrated circuit design. A layout is defined for a level of a cell in accordance with a dynamic array architecture so as to include a number of layout features. The number of layout features are linear-shaped and commonly oriented. The layout is split into a number of sub-layouts for the level of the cell. Each of the number of layout features in the layout is allocated to any one of the number of sub-layouts. Also, the layout is split such that each sub-layout is independently fabricatable. The sub-layouts for the level of the cell are stored on a computer readable medium. |
| US09633985B2 |
First-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and processing method thereof
A first-etched and later-packaged three-dimensional system-in-package normal chip stack package structure and a processing method for manufacturing the same are provided. The structure includes: a die pad (1); a lead (2); a chip (4) provided on a top surface of the die pad (1) by a conductive or non-conductive adhesive material (3); a metal wire (5) via which a top surface of the chip (4) is connected to a top surface of the lead (2); a conductive pillar (6) provided on the surface of the lead (2); and a molding material (7). |
| US09633981B2 |
Systems and methods for bonding semiconductor elements
A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element, wherein the surfaces of each of the plurality of first conductive structures and the plurality of second conductive structures include aluminum; and (b) ultrasonically bonding ones of the first conductive structures to respective ones of the second conductive structures. |
| US09633977B1 |
Integrated device comprising flexible connector between integrated circuit (IC) packages
Some features pertain to an integrated device that include a first integrated circuit (IC) package comprising a first laminated substrate, a flexible connector coupled to the first laminated substrate, and a second integrated circuit (IC) package comprising a second laminated substrate. The second laminated substrate is coupled to the flexible connector. The flexible connector includes a dielectric layer and an interconnect. The dielectric layer and the interconnect substantially extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer and the interconnect of the flexible connector, contiguously extend into the first laminated substrate and the second laminated substrate. In some implementations, the dielectric layer extends into a substantial portion of the first laminated substrate. In some implementations, the dielectric layer includes polyimide (PI) layer. |
| US09633974B2 |
System in package fan out stacking architecture and process flow
Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL. |
| US09633973B2 |
Semiconductor package
A semiconductor package is provided comprising a package substrate having an opening located in a central region thereof and a circuit pattern provided adjacent to the opening. A first semiconductor chip is located on the package substrate and includes first bonding pads. A pair of second semiconductor chips are spaced apart from each other across the opening and mounted between the package substrate and the first semiconductor chip. Each of the second semiconductor chips includes a second bonding pad. A connection element is further provided to electrically connect the second bonding pad to a corresponding one of the first bonding pads. |
| US09633970B2 |
IGBT device and method for packaging whole-wafer IGBT chip
An IGBT device and a method for packaging a whole-wafer IGBT chip. The IGBT device comprises: an entire wafer IGBT chip, the upper surface thereof comprising a central gate connection zone and a plurality of emitter connection zones surrounding the central gate connection zone, and the lower surface thereof comprising a collecting zone, wherein the emitter connection zones located on the surface of a failure cellular zone of the chip are thinned; a collector washer which is fixed on the lower surface of the chip, and an emitter washer which is fixed on the upper surface of the chip; a collector electrode which is electrically contacted with the collector washer, and an emitter electrode which is electrically contacted with the emitter washer; and a gate leading wire which is connected to the central gate connection zone. |
| US09633969B2 |
Semiconductor device, semiconductor chip, and method of manufacturing semiconductor device
A semiconductor device includes a semiconductor chip including first to fourth pads, and first and second switches. The first switch includes first and second nodes coupled to the first and second pads and sends from the second node a current larger than a threshold flowing in from the first node. The second switch includes third and fourth nodes coupled to the third and fourth pads and sends from the fourth node a current larger than a threshold flowing in from the third node. The third and fourth nodes are not coupled to any nodes of high and low potentials of any circuit which receives the potentials to operate. A first wire is coupled to the first pad and the first conductor, and a second wire is coupled to the second pad and the second conductor. |
| US09633968B2 |
Microelectronic packages having cavities for receiving microelectronic elements
Packaged microelectronic elements are provided which include a dielectric element, a cavity, a plurality of chip contacts and a plurality of package contacts, and microelectronic elements having a plurality of bond pads connected to the chip contacts. |
| US09633967B2 |
Semiconductor module
To provide a semiconductor module that has high reliability of electric connection by a solder and is inexpensive. A joint surface of an electrode jointing portion that is opposed to a surface to be jointed of a gate electrode of a bare-chip FET and a joint surface of a substrate jointing portion that is opposed to a surface to be jointed of another wiring pattern include an outgas releasing mechanism that makes outgas generated from a molten solder during solder jointing of a metal plate connector be released from solders interposed between the joint surfaces and the surfaces to be jointed. |
| US09633958B2 |
Bonding pad surface damage reduction in a formation of digital pattern generator
A method of fabricating a Digital pattern generator (DPG) device is disclosed. The method includes forming an etch-stop-layer (ESL) over a bonding pad in a first region over a substrate, forming a pixel well in the second region over the substrate, forming an anti-charging layer over the bonding pad and along sidewalls of the pixel well. The bonding pad is covered by the ESL during the forming of the anti-charging layer over the bonding pad. The method also includes removing the anti-charging layer over the bonding pad. Therefore, after removing the anti-charging layer over the bonding pad, the bonding pad remains covered by the ESL. |
| US09633956B2 |
RF switch on high resistive substrate
A device includes a semiconductor substrate of a first conductivity type, and a deep well region in the semiconductor substrate, wherein the deep well region is of a second conductivity type opposite to the first conductivity type. The device further includes a well region of the first conductivity type over the deep well region. The semiconductor substrate has a top portion overlying the well region, and a bottom portion underlying the deep well region, wherein the top portion and the bottom portion are of the first conductivity type, and have a high resistivity. A gate dielectric is over the semiconductor substrate. A gate electrode is over the gate dielectric. A source region and a drain region extend into the top portion of the semiconductor substrate. The source region, the drain region, the gate dielectric, and the gate electrode form a Radio Frequency (RF) switch. |
| US09633954B2 |
Methods of manufacturing an integrated circuit having stress tuning layer
Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 μm, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component. |
| US09633944B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method thereof are provided. A semiconductor device includes a stack structure including conductive layers stacked in a step shape, a first interlayer insulating layer formed over the stack structure, the first interlayer insulating layer including contact holes with a uniform depth, which expose the conductive layers, lower contact plugs formed in the contact holes, the lower contact plugs being respectively contacted with the conductive layers, and lower contact pads respectively connected to the contact plugs. |
| US09633943B2 |
Method and structure for forming on-chip anti-fuse with reduced breakdown voltage
A fully depleted field effect transistor (FET) and an anti-fuse structure are provided on a same chip. The fully depleted FET and the anti-fuse structure share a same high dielectric (k) constant dielectric material. The anti-fuse structure contains a faceted epitaxial doped semiconductor material as a bottom electrode, a high k dielectric material portion, and a gate electrode material portion as a top electrode. The sharp corners of the faceted epitaxial doped semiconductor material cause electric field concentration, which aid in the reduction of the breakdown voltage of the anti-fuse structure. |
| US09633939B2 |
Semiconductor package and manufacturing method thereof
A semiconductor package and a method of manufacturing a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a cover layer that enhances reliability of the semiconductor packages. |
| US09633934B2 |
Semicondutor device and method of manufacture
A semiconductor device and method for providing an enhanced removal of heat from a semiconductor die within an integrated fan out package on package configuration is presented. In an embodiment a metal layer is formed on a backside of the semiconductor die, and the semiconductor die along and through vias are encapsulated. Portions of the metal layer are exposed and a thermal die is connected to remove heat from the semiconductor die. |
| US09633932B2 |
Lead frame package having discharge hole and method of manufacturing the same
An electronic package structure includes a substrate having a plurality of conductive leads. A discharge hole is disposed to extend through the substrate. An electronic chip is electrically connected to the plurality of conductive leads. A case is connected to the substrate and defines a cavity between the substrate and an upper of the case. The discharge hole and the electronic chip are disposed within the cavity, and the discharge hole is open to the outside in the electronic package structure. The discharge hole is configured to discharge air pressure that forms during the assembly process thereby improving the reliability of the electronic package structure. |
| US09633930B2 |
Method of forming through-hole in silicon substrate, method of forming electrical connection element penetrating silicon substrate and semiconductor device manufactured thereby
The present invention herein relates to a method of forming a through-hole in a silicon substrate. The present invention herein also relates to a method of forming an electrical connection element which penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. More particularly, the present invention herein relates to a method of forming in a silicon substrate a through-hole capable of reducing roughness in a side wall of the through-hole and exhibiting low permittivity, by alternatingly laminating cationic and anionic polymer on the through-hole that has a dent on the side wall to form a porous elastic layer, and also relates to a method of forming an electrical connection that penetrates through the silicon substrate, and to a semiconductor device manufactured thereby. |
| US09633928B2 |
Through-silicon via access device for integrated circuits
A through-silicon via access device (TSVAD) for establishing an electrical connection to a through-silicon via (TSV) located in a planar stack of semiconductor chips is disclosed. The TSVAD may include a switching circuit, having a conductive pad terminal, a TSV terminal, an input terminal coupled to a sending logic circuit, an output terminal coupled to a receiving logic circuit, and logic devices to, in response to control signals, couple the TSV terminal to the conductive pad terminal, in one configuration, and couple the TSV terminal to another terminal in another configuration. The TSVAD may also include a control circuit to generate control signals to cause an input selection circuit to drive a signal from the sending logic circuit onto the input terminal, and to cause an output selection circuit to drive a logic signal from the output terminal to the receiving logic circuit. |
| US09633925B1 |
Visualization of alignment marks on a chip covered by a pre-applied underfill
Structures and methods for improving the visualization of alignment marks on an underfill-covered chip. A feature is formed on a chip, and an underfill material is applied to the chip at a wafer level so that the feature is covered the feature. The feature includes a first structural element comprised of a first material and a second structural element comprised of a second material that is electrochemically dissimilar from the first material to provide a galvanic cell effect. Filler particles in the underfill material are caused by the galvanic cell effect to distribute with a first density in a first region over the first structural element and a second region of a second density over the second structural element. The first density in the first region is less than the second density in the second region such that the first region has a lower opacity than the second region. |
| US09633922B2 |
Sealing epoxy resin composition, hardened product, and semiconductor device
A sealing epoxy resin composition contains a phosphonium salt shown in Formula (1), an epoxy resin, a hardening agent, and an inorganic filler. In Formula (1), R1-R3 each represent an aryl group having 6 to 12 carbon atoms, R4 represents an alkyl group having 1 to 4 carbon atoms, R6 and R8 each represent either a carboxyl group or a hydroxyl group, R5 and R7 each represent either hydrogen or an alkyl group having 1 to 4 carbon atoms, R9 and R11 represent hydrogen, R10 represents either a carboxyl group or a hydroxyl group, and the relation of r≦1 is satisfied. |
| US09633921B2 |
Semiconductor encapsulation resin composition and semiconductor device comprised of cured product of the semiconductor encapsulation resin composition
Provided is a semiconductor encapsulation resin composition exhibiting an insignificant heat decomposition when left under a high temperature of 200 to 250° C. for a long period of time; and a superior reliability and adhesion to a Cu LF and Ag plating under a high-temperature and high-humidity environment. The composition comprises: (A) a cyanate ester compound having not less than two cyanato groups in one molecule; (B) a phenolic compound; (C) at least one epoxy resin; (D) a copolymer obtained by a hydrosilylation reaction of an alkenyl group-containing epoxy compound and an organopolysiloxane; and (E) at least one compound selected from a tetraphenylborate salt of a tetra-substituted phosphonium compound and a tetraphenylborate salt. A molar ratio of phenolic hydroxyl groups in (B) to cyanato groups in (A) is 0.08 to 0.25, and a molar ratio of epoxy groups in (C) and (D) to cyanato groups in (A) is 0.04 to 0.25. |
| US09633918B2 |
Semiconductor device
A semiconductor device includes an insulating substrate, a semiconductor element secured to a top surface of the insulating substrate, a case formed of a resin and having a frame portion surrounding the semiconductor element, a metal support located above the insulating substrate and having an end secured to the frame portion, a holding-down portion extending downward from the metal support so as to prevent upwardly convex bending of the insulating substrate, and an adhesive bonding the insulating substrate and the case together. |
| US09633914B2 |
Split ball grid array pad for multi-chip modules
A multi-chip module and method of fabricating a multi-chip module. The multi-chip module includes: a substrate having a top surface and a bottom surface and containing multiple wiring layers, first pads on the top surface of the substrate and second pads on the bottom surface of the substrate; a first active component attached to a first group of the first pads and a second active component attached to a second group of the first pads; wherein at least one pad of the second pads is a split pad having a first section and a non-contiguous second section separated by a gap, the first section connected by a first wire of the multiple wires to a pad of the first group of first pads and the second section is connected by a second wire of the multiple wires to a pad of the second group of first pads. |
| US09633913B2 |
Method of evaluating epitaxial wafer
The method of evaluating an epitaxial wafer includes performing evaluation of an epitaxial wafer by detecting, as a light point defect, an abnormal substance selected from the group consisting of a defect and a surface deposit of an epitaxial wafer to be evaluated with a surface inspection apparatus including two types of incidence systems with different incidence angles and two types of light receiving systems with different light receiving angles, based on two types of measurement results. |
| US09633912B2 |
Complementary heterogeneous MOSFET using global SiGe substrate and hard-mask memorized germanium dilution for nFET
A method includes providing a substrate that underlies a layer of SiGe; forming a plurality of fins in the layer of SiGe. Each formed fin has a fin shape and fin location preserving hard mask layer on a top surface. The method also includes depositing Si on a first subset of the set of fins in what will be an nFET area; performing a Si—Ge inter-mixing process on the first subset of fins to reduce a concentration of Ge in the first subset while producing a Si—Ge intermix layer; removing the Si—Ge intermix layer leaving the first subset of fins having the reduced concentration of Ge, and forming a second subset of fins in what will be a pFET area. The second subset is also formed from the layer of SiGe and has a greater percentage of Ge than a percentage of Ge in the first subset of fins. |
| US09633909B2 |
Process for integrated circuit fabrication including a liner silicide with low contact resistance
An integrated circuit includes a substrate supporting a transistor having a source region and a drain region. A high dopant concentration delta-doped layer is present on the source region and drain region of the transistor. A set of contacts extend through a pre-metal dielectric layer covering the transistor. A silicide region is provided at a bottom of the set of contacts. The silicide region is formed by a salicidation reaction between a metal present at the bottom of the contact and the high dopant concentration delta-doped layer on the source region and drain region of the transistor. |
| US09633906B2 |
Gate structure cut after formation of epitaxial active regions
A gate structure straddling a plurality of semiconductor material portions is formed. Source regions and drain regions are formed in the plurality of semiconductor material portions, and a gate spacer laterally surrounding the gate structure is formed. Epitaxial active regions are formed from the source and drain regions by a selective epitaxy process. The assembly of the gate structure and the gate spacer is cut into multiple portions employing a cut mask and an etch to form multiple gate assemblies. Each gate assembly includes a gate structure portion and two disjoined gate spacer portions laterally spaced by the gate structure portion. Portions of the epitaxial active regions can be removed from around sidewalls of the gate spacers to prevent electrical shorts among the epitaxial active regions. A dielectric spacer or a dielectric liner may be employed to limit areas in which metal semiconductor alloys are formed. |
| US09633898B2 |
Etching liquid, etching method, and method of manufacturing solder bump
An etching liquid which can selectively remove only a copper layer in an etching process of a multilayer structure including a cobalt layer and the copper layer is disclosed. The etching liquid is an etching liquid for etching the copper layer in the multilayer structure including the copper layer and the cobalt layer. This etching liquid includes at least one acid selected from a group consisting of citric acid, oxalic acid, malic acid, and malonic acid, and hydrogen peroxide, the etching liquid having pH in a range of 4.3 to 5.5. |
| US09633897B2 |
Air-gap forming techniques for interconnect structures
The present disclosure relates to a method of forming an interconnect structure. In some embodiments, the method is performed by forming a trench within a first dielectric layer and forming sacrificial spacers along sidewalls of the trench. The trench is filled with a conductive material, and the sacrificial spacers are removed after the trench has been filled with the conductive material. A second dielectric layer is formed over the first dielectric layer to leave an air-gap in a region from which the sacrificial spacers were removed. |
| US09633894B2 |
Semiconductor structure with airgap
A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap. |
| US09633890B2 |
Device for treating surfaces of wafer-shaped articles and gripping pin for use in the device
A device for processing wafer-shaped articles comprises a rotary chuck having a series of pins adapted to hold a wafer shaped article on the rotary chuck. Each of the pins comprises a cylindrical body and a projecting gripping portion formed integrally therewith. The cylindrical body and gripping portion are made from a ceramic material. The gripping portion comprises cylindrical surfaces having a common generatrix with surfaces of the cylindrical body. |
| US09633889B2 |
Substrate support with integrated vacuum and edge purge conduits
Substrate supports are provided herein, In some embodiments, a substrate support includes a first plate; a plurality of vacuum passages disposed through the first plate; a plurality of vertical passages formed partially into the first plate; a plurality of horizontal passages disposed in the first plate, each of the plurality of horizontal passages beginning proximate a perimeter of the first plate and terminating proximate one of the plurality of vertical passages such that the horizontal passages and the vertical passages are in fluid communication; a second plate coupled to the first plate at an interface; an elongate shaft having a vacuum line and an edge purge line internal to the shaft; a vacuum channel formed at the interface fluidly coupling the vacuum line to the plurality of vacuum passages; and an edge purge channel formed at the interface fluidly coupling the edge purge line to the plurality of vertical passages. |
| US09633888B2 |
Semiconductor manufacturing device and method of manufacturing semiconductor chip
Provided is a semiconductor manufacturing device including an expanding unit that expands a holding member having an adhesive layer on which a substrate in a state of being diced into plural semiconductor chips is held, a detection unit that detects an adhesive state between one of the semiconductor chips and the holding member, in a state in which the holding member is expanded, and a pickup unit that picks up the semiconductor chip by changing an operation relevant to pickup of the semiconductor chip based on the detected adhesive state. |
| US09633886B2 |
Hybrid thermal electrostatic clamp
An electrostatic clamp having improved temperature uniformity is disclosed. The electrostatic clamp includes an LED array mounted along an annular ring so as to illuminate the outer edge of the workpiece. The LEDs in the LED array may emit light at a wavelength readily absorbed by the workpiece, such as between 0.4 μm and 1.0 μm. The center portion of the workpiece is heated using conductive heating provided by the heated electrostatic clamp. The outer portion of the workpiece is heated by light energy from the LED array. The LED array may be disposed on the base of the electrostatic clamp, or may be disposed on a separate ring. The diameter of the upper dielectric layer of the electrostatic clamp may be modified to accommodate the LED array. |
| US09633881B2 |
Automatic handling buffer for bare stocker
A buffer station for automatic material handling system can provide throughput improvement. Further, by storing to-be-accessed workpieces in the buffer stations of an equipment, the operation of the facility is not interrupted when the equipment is down. The buffer station can be incorporated in a stocker, such as bare wafer stocker. |
| US09633878B1 |
Conveyor apparatus and method for transporting leadframe
A conveyor apparatus for a leadframe includes a track defining a longitudinally extending passage through which the leadframe travels. A magnetic clamping system and a plurality of first guide magnets are provided on the track. A gripping device is provided for securing to the leadframe. At least one clamping magnet and a plurality of second guide magnets are secured to the gripping device. The first and second guide magnets cooperate to move the gripping device in a first direction along the length of the passage. The magnetic clamping system and the at least one clamping magnet cooperate to selectively move the gripping device in a second direction perpendicular to the first direction between a first condition spaced from the track to a second condition magnetically fixed to the track. |
| US09633873B2 |
Electronic device
An electronic device includes: a wiring substrate; a plurality of device chips that are flip-chip mounted on an upper surface of the wiring substrate through bumps, have gaps which expose the bumps between the device chips and the upper surface of the wiring substrate, and include at least one device chip that has a substrate having a thermal expansion coefficient more than a thermal expansion coefficient of the wiring substrate; a junction substrate that is joined to the plurality of device chips, and has a thermal expansion coefficient equal to or less than the thermal expansion coefficient of the substrate included in the at least one device chip; and a sealer that covers the junction substrate, and seals the plurality of device chips. |
| US09633872B2 |
Integrated circuit package with active interposer
An integrated circuit package may include a substrate and an interposer. The interposer is disposed over the substrate. The interposer may include embedded switching elements that may be used to receive different power supply signals. An integrated circuit with multiple logic blocks is disposed over the substrate. The switching elements embedded in the interposer may be used to select a power supply signal from the power supply signals and may be used to provide at least one circuit block in the integrated circuit with a selected power supply signal. |
| US09633867B2 |
Method and apparatus for anisotropic tungsten etching
Methods for anisotropically etching a tungsten-containing material (such as doped or undoped tungsten metal) include cyclic treatment of tungsten surface with Cl2 plasma and with oxygen-containing radicals. Treatment with chlorine plasma is performed while the substrate is electrically biased resulting in predominant etching of horizontal surfaces on the substrate. Treatment with oxygen-containing radicals passivates the surface of the substrate to etching, and protects the vertical surfaces of the substrate, such as sidewalls of recessed features, from etching. Treatment with Cl2 plasma and with oxygen-containing radicals can be repeated in order to remove a desired amount of material. Anisotropic etching can be performed selectively in a presence of dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride. |
| US09633865B2 |
Low-stain polishing composition
The invention is an aqueous composition useful for chemical mechanical polishing of a patterned semiconductor wafer containing a copper interconnect metal. The aqueous composition includes an oxidizer, an inhibitor for the copper interconnect metal, 0.001 to 15 weight percent of a water soluble modified cellulose, non-saccaride water soluble polymer, 0 to 15 complexing agent for the copper interconnect metal, 0 to 15 weight percent phosphorus compound, 0.05 to 20 weight percent of an acid compound that is capable of complexing copper ions, and water; and the solution has an acidic pH. |
| US09633860B2 |
Semiconductor structure with resist protective oxide on isolation structure and method of manufacturing the same
A semiconductor structure includes an isolation structure, a gate stack, a spacer and a patterned resist protective oxide. The isolation structure is formed in a semiconductor substrate, and electrically isolates device regions of the semiconductor substrate. The gate stack is located on the isolation structure. The spacer is formed along a sidewall of the gate stack on the isolation structure. The patterned resist protective oxide is located on the isolation structure and covers a sidewall of the spacer such that the spacer is interposed between the patterned resist protective oxide and the gate stack. |
| US09633857B1 |
Semiconductor structure including a trench capping layer and method for the formation thereof
A semiconductor structure includes a trench isolation structure, a trench capping layer, a gate structure and a sidewall spacer. The trench isolation structure includes a first electrically insulating material. The trench capping layer is provided over the trench isolation structure. The trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The gate structure includes a gate insulation layer including a high-k material and a gate electrode over the gate insulation layer. The gate structure has a first portion over the trench capping layer. The sidewall spacer is provided adjacent the gate structure. A portion of the sidewall spacer is provided on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer. |
| US09633851B2 |
Semiconductor device including small pitch patterns
A method is provided for fabricating small pitch patterns. The method includes providing a semiconductor substrate, and forming a target material layer having a first region and a second region on the semiconductor substrate. The method also includes forming a plurality of discrete first sacrificial layers on the first region of the target material layer and a plurality of discrete second sacrificial layers on the second region of the target material layer, and forming first sidewall spacers on both sides of the discrete first sacrificial layers and the discrete second sacrificial layers. Further, the method includes removing the first sacrificial layers and the second sacrificial layers, and forming second sidewall spacers. Further, the method also includes forming discrete repeating patterns in the first region of the target material layer and a continuous pattern in the second region of the target material layer. |
| US09633844B2 |
Method for forming low temperature polysilicon thin film
Embodiments of the present invention provide a method for forming a low temperature polysilicon thin film. The method for forming the low temperature polysilicon thin film can include: depositing a buffer layer and an amorphous silicon layer on a substrate in this order; heating the amorphous silicon layer; performing an excimer laser annealing process on the amorphous silicon layer to form a polysilicon layer; oxidizing partially the polysilicon layer so as to form an oxidation portion at an upper portion of the polysilicon layer; and removing the oxidation portion of the polysilicon layer to form a polysilicon thin film. |
| US09633842B2 |
Metal induced nanocrystallization of amorphous semiconductor quantum dots
A method of forming crystallized semiconductor particles includes: forming amorphous semiconductor particles in a vacuumed aggregation chamber; transporting the amorphous semiconductor particles formed in the vacuumed aggregation chamber to a vacuumed deposition chamber within which a substrate is held; and applying a vapor of a metal catalyst to the amorphous semi-conductor particles while still in transit to the substrate in the vacuumed deposition chamber to induce crystallization of at least portion of the amorphous semiconductor particles via the metal catalyst in the transit, thereby depositing the crystallized semiconductor particles with the metal catalyst attached thereto onto the substrate. |
| US09633839B2 |
Methods for depositing dielectric films via physical vapor deposition processes
In some embodiments a method of processing a substrate disposed atop a substrate support in a physical vapor deposition process chamber includes: (a) depositing a dielectric layer to a first thickness atop a first surface of the substrate via a physical vapor deposition process; (b) providing a first plasma forming gas to a processing region of the physical vapor deposition process chamber, wherein the first plasma forming gas comprises hydrogen but not carbon; (c) providing a first amount of bias power to a substrate support to form a first plasma from the first plasma forming gas within the processing region of the physical vapor deposition process chamber; (d) exposing the dielectric layer to the first plasma; and (e) repeating (a)-(d) to deposit the dielectric film to a final thickness. |
| US09633834B2 |
Photolithographic method for forming a coating layer
A method for forming a coating layer includes spraying coating material having a first flowability onto a substrate; performing a first spin coating process with a first spin speed to form an initial coating layer; and performing a first baking process to the initial coating layer to form a first material layer having a second flowability and a second material layer having a third flowability. The third flowability is less than the first flowability but larger than the second flowability, which is less than the first flowability. Further, the method includes performing a second spin coating process with a second spin speed to drive the coating material in the second material layer flowing on the surface of the first material layer to form a third material layer with a uniform thickness, and performing a second baking process to form a final coating layer on the substrate. |
| US09633829B2 |
Discharge lamp
A discharge lamp includes an emitter other than thorium, which is added to a cathode in a luminous tube. Early depletion of the emitter due to excessive vaporization of the emitter from the cathode is prevented, while achieving stable lighting even at the start-up of the lighting. A main body part (31) of the cathode (3) is made from a high-melting-point metal material that contains no thorium, and a front end part (32) thereof is made from a high-melting-point metal material that contains an emitter (other than thorium). A sintered compact (34), which contains an emitter (other than thorium) at a concentration higher than the emitter contained in the front end part (32), is buried in a sealed space (33) that is formed within the main body part (31) and/or the front end part (32). The sintered compact (34) abuts against the front end part (32). |
| US09633826B1 |
Mass spectrometer with movable ionization chamber
The ionization chamber of the mass spectrometer is movable between the maintenance position for performing maintenance of the mass spectrometer unit and the analysis position for performing sample analysis, using a shielding plate synchronized with the motion of the ionization chamber where the shielding plate closes part of the aperture of the predetermined region when the ionization chamber is in the analysis position, whereas the shielding plate opens part of the aperture of the predetermined region when the ionization chamber is in the maintenance position so that connection tubes may pass through the part of the aperture of the predetermined region. |
| US09633824B2 |
Target for PVD sputtering system
Embodiments of apparatus for physical vapor deposition are provided. In some embodiments, a target assembly for use in a substrate processing system to process a substrate includes a plate having a first side and an opposing second side, wherein the second side comprises a target supporting surface extending from the second side in a direction normal to the second side, wherein the target supporting surface has a first diameter and is bounded by a first edge; and a target having a first side bonded to the target supporting surface, wherein a diameter of the target is greater than the first diameter of the target supporting surface. |
| US09633823B2 |
Plasma emission monitor and process gas delivery system
A gas manifold for delivery gas to a sputtering chamber is provided with ports to accommodate plasma emission monitors to monitor plasma information in the sputtering chamber to provide feedback control. The collimators of the plasma emission monitors is exposed to gas flow and thus coating of the monitor is greatly reduced. |
| US09633822B2 |
Gas nozzle, plasma apparatus using the same, and method for manufacturing gas nozzle
[Object] To provide a gas nozzle which meets a requirement to suppress the fall of particles.[Solution] A gas nozzle 4 according to an aspect of the present invention includes a columnar main body 13 formed of a ceramic sintered body provided with a through-hole 12 formed therein through which a gas flows, an exhaust port 15 of the through-hole 12 for the gas is formed in one end surface S1 of the main body 13, and the mean width of the profile elements (Rsm) of the one end surface S1 is 5 times or more the average crystalline grain diameter of the ceramic sintered body. |
| US09633816B2 |
Electron beam microscope with improved imaging gas and method of use
Charged particle beam imaging and measurement systems are provided using gas amplification with an improved imaging gas. The system includes a charged particle beam source for directing a charged particle beam to work piece, a focusing lens for focusing the charged particles onto the work piece, and an electrode for accelerating secondary electrons generated from the work piece irradiation by the charged practice beam, or another gas cascade detection scheme. The gas imaging is performed in a high pressure scanning electron microscope (HPSEM) chamber for enclosing the improved imaging gas including CH3CH2OH (ethanol) vapor. The electrode accelerates the secondary electrons though the CH3CH2OH to ionize the CH3CH2OH through ionization cascade to amplify the number of secondary electrons for detection. An optimal configuration is provided for use of the improved imaging gas, and techniques are provided to conduct imaging studies of organic liquids and solvents, and other CH3CH2OH-based processes. |
| US09633814B2 |
X-ray CT apparatus
X-ray CT apparatus is provided in which the photon energy distribution of X-rays to be radiated is flattened. X-ray CT apparatus includes an X-ray tube, a detector, a data acquisition system, a tube voltage generator, and a grid controller. The X-ray tube radiates X-rays onto a subject. The detector includes multiple detection elements for detecting photons forming the X-rays. The data acquisition system counts the number of the detected photons to acquire projection data based on the counted photons. The tube voltage generator applies the tube voltage to the X-ray tube while changing the tube voltage of the X-ray tube in a predetermined cycle. A tube current controller decreases the tube current upon an increase in the tube voltage, and increases the tube current upon a decrease in the tube voltage. Thus, the photon energy distribution of the X-rays radiated from the X-ray tube is flattened. |
| US09633813B2 |
Ion source using heated cathode and electromagnetic confinement
An ion source for use in a radiation generator tube includes a back passive cathode electrode, a passive anode electrode downstream of the back passive cathode electrode, a magnet adjacent the passive anode electrode, and a front passive cathode electrode downstream of the passive anode electrode. The front passive cathode electrode and the back passive cathode electrode define an ionization region therebetween. At least one ohmically heated cathode is configured to emit electrons into the ionization region. The back passive cathode electrode and the passive anode electrode, and the front passive cathode electrode and the passive anode electrode, have respective voltage differences therebetween, and the magnet generating a magnetic field, such that a Penning-type trap is produced to confine the electrons to the ionization region. At least some of the electrons in the ionization region interact with an ionizable gas to create ions. |
| US09633808B2 |
Electrical interruption apparatus with wear indicator
An improved electrical interruption apparatus provides an improved wear indicator that is configured to depict an amount of wear that has been experienced by a set of separable contacts of a vacuum interrupter. At an easily visible location on a drive rod of the circuit interruption apparatus, the wear indicator indicates the extent to which the set of contacts have degraded. The wear indicator is attached to a spring-loaded over-travel mechanism that engages together the set of electrical contacts. |
| US09633806B2 |
Switching arrangement
A switching configuration includes a first switching contact set having a rated current contact piece and an arcing contact piece. The arcing contact piece and the rated current contact piece of the first switching contact set are movable relative to one another through a transmission mechanism. The arcing contact piece is supported by a support element on a contact carrier of the rated current contact piece. The transmission mechanism has a transmission mechanism chassis which is supported, particularly directly, on the contact carrier. |
| US09633803B2 |
Keyboard backlight module with improved light guide structure
A keyboard backlight module includes a backlight device including a reflective layer, a light shielding layer and a light guide layer sandwiched between the reflective layer and the light shielding layer and carrying a set of key switches on the top surface thereof, a light source mounted between the reflective layer and the light shielding layer, and high-refractive index scatter points prepared from a mixture containing a colored light-transmissive ink and high-refractive index particles at a predetermined ratio and mounted in the top side and/or bottom side of the light guide layer for refracting light toward the key switches to enhance illumination brightness. |
| US09633801B2 |
Touch device and fabrication method thereof
A touch device including a touch panel is provided. The touch panel includes a substrate having a touching surface and a bonding surface opposite to the touching surface, and further having a viewable area and a non-viewable area surrounding the viewable area. A colorful decoration layer is disposed on the bonding surface of the substrate and at the non-viewable area. The colorful decoration layer has a gradient side adjacent to the viewable area. A planarization layer completely covers the gradient side of the colorful decoration layer and the bonding surface of the substrate. A touch sensing layer is disposed on the planarization layer and extended from the viewable area to the non-viewable area. Further, a method for fabricating a touch device is provided. |
| US09633797B2 |
Conductive salt for lithium-based energy stores
The invention relates to the use of lithium-2-pentafluoroethoxy-1,1,2,2-tetrafluoro-ethanesulfonate as a conductive salt in lithium-based energy stores and to electrolytes containing lithium-2-pentafluoroethoxy-1,1,2,2-tetrafluoro-ethanesulfonate. |
| US09633795B2 |
Electronic component and method for manufacturing electronic component
An electronic component that includes a resistive element. A Ni concentration of a resistive thin film of the resistive element at a side where there is a connection interface with a connection electrode is higher than the concentration of Ni at the side opposite to the interface. |
| US09633782B2 |
Wireless power transmitter
An automatic tuning assist circuit is coupled with a transmission antenna. Multiple switches SW and a first auxiliary capacitor CA are arranged between a first terminal and a second terminal of the automatic tuning assist circuit. A first control unit is configured to switch on and off the multiple switches SW in synchronization with a driving voltage VDRV. A power supply is configured to apply the driving voltage VDRV across a series circuit that comprises the transmission antenna and the automatic tuning assist circuit. |
| US09633779B2 |
Composite electronic component and board having the same
A composite electronic component may include: a composite body including a capacitor and an inductor coupled to each other, the capacitor having a ceramic body in which dielectric layers and internal electrodes facing each other with the dielectric layers interposed therebetween are stacked, and the inductor having a magnetic body in which magnetic layers having conductive patterns are stacked; an input terminal disposed on a first end surface of the composite body; an output terminal including a first output terminal disposed on a second end surface of the composite body and a second output terminal disposed on any one or more of upper and lower surfaces and a second side surface of the capacitor; and a ground terminal disposed on any one or more of the upper and lower surfaces and a first side surface of the capacitor and connected to the internal electrodes. |
| US09633769B2 |
Magnetic refrigeration material
Provided is a magnetic refrigeration material which has a Curie temperature near room temperature or higher, and provides refrigeration performance well over that of conventional materials when subjected to a field change up to 2 Tesla, which is assumed to be achievable with a permanent magnet. The magnetic refrigeration material is of a composition represented by the formula La1-fREf(Fe1-a-b-c-d-eSiaCObXcYdZe)13 (RE: at least one of rare earth elements including Sc and Y and excluding La; X: Ga and/or Al; Y: at least one of Ge, Sn, B, and C; Z: at least one of Ti, V, Cr, Mn, Ni, Cu, Zn, and Zr; 0.03≦a≦0.17, 0.003≦b≦0.06, 0.02≦c≦0.10, 0≦d≦0.04, 0≦e≦0.04, 0≦f≦0.50), and has Tc of not lower than 220 K and not higher than 276 K, and the maximum (−ΔSmax) of magnetic entropy change (−ΔSM) of the material when subjected to a field change up to 2 Tesla is not less than 5 J/kgK. |
| US09633766B2 |
Energy efficient conductors with reduced thermal knee points and the method of manufacture thereof
The present invention relates to electrical conductors for electrical transmission and distribution with pre-stress conditioning of the strength member so that the conductive materials of aluminum, aluminum alloys, copper, copper alloys, or copper micro-alloys are mostly tension free or under compressive stress in the conductor, while the strength member is under tensile stress prior to conductor stringing, resulting in a lower thermal knee point in the conductor. |
| US09633765B2 |
Coaxial cable device having a helical outer conductor and method for effecting weld connectivity
A jumper cable having an end prepared for connecting to a coupling assembly. The prepared end includes an inner conductor, an outer conductor having a helical outer surface contour, and a dielectric core disposed between the inner and outer conductors. A weld washer: (i) threadably engages the helical outer surface contour of the outer conductor, (iii) receives a deformed edge of the outer conductor through an opening in the washer, and (iv) is penetration welded to deformed edge of the outer conductor. Operationally, the face of the weld washer augments the flow of electrical current to electrically ground the outer conductor to the coaxial cable connector. |
| US09633762B2 |
Cable
Provided is a cable enabling to reduce leakage flux and to restrict an increase of high-frequency resistance. A magnetic shield is provided to enable to reduce leakage of magnetic flux to an outside, and two first conductive wires and two second conductive wires having different phases from each other are adjacent to each other and arranged annularly to enable to disperse the magnetic flux, to restrict a proximity effect, and to restrict an increase of high-frequency resistance. |
| US09633760B2 |
Water stopping structure for insulation-coated wire and wire harness
A water blocking structure for an insulation-coated wire includes a heat-shrinkable tubular protective member that is closed at one end by a stopper and that accommodates an intermediate portion of an insulation-coated wire, and a resin material that is accommodated in the protective member and that penetrates the intermediate portion of the insulation-coated wire. Slit portions are formed in a coating of the insulation-coated wire within the protective member, the slit portions extending in a direction that crosses the axis of the insulation-coated wire on opposite sides of the intermediate portion with respect to a radial direction, and a water blocking agent penetrates the intermediate portion via these slit portions. |
| US09633758B2 |
Wrapped textile sleeve with bonded closure mechanism NAD method of construction thereof
A wrapped textile sleeve for protecting an elongate member and method of construction thereof is provided. The sleeve includes an inner layer having opposite inner edges extending lengthwise between opposite inner ends. The opposite inner edges are laterally spaced from one another by an inner width. The sleeve further includes an outer layer having opposite outer edges extending lengthwise between opposite outer ends. The opposite outer edges are laterally spaced from one another by an outer width. An adhesive intermediate layer is sandwiched between the inner layer and the outer layer, wherein a melted portion of the adhesive intermediate bonds the inner layer to the outer layer. The adhesive intermediate layer extends beyond at least one of the inner edges to provide an exposed region of the adhesive intermediate layer. The exposed region is bonded to the outer layer and maintains the outer layer in a wrapped, tubular configuration. |
| US09633755B2 |
Conductive composition, conductive member, conductive member production method, touch panel, and solar cell
The conductive composition contains at least (a) conductive metal fibers, and (b) at least one compound selected from a compound represented by the following Formula (1), a compound represented by the following Formula (2), and a compound having a partial structure represented by the following Formula (3). Each of R1 and R2 independently represents a hydrogen atom, an alkyl group, an alkenyl group, an aryl group, an acyl group, an aryloxycarbonyl group, an alkoxycarbonyl group, or a carbamoyl group. Each of R3, R4, R5, R6, R8, R9, R10, and R11 independently represents an alkyl group having 1 to 4 carbon atoms, and R7 represents a hydrogen atom or a substituent. R12 represents an alkyl group, an alkoxy group, an acyl group, or a hydrogen atom. * represents a bond. |
| US09633750B2 |
Semiconductor device for performing repair operations
A semiconductor device includes a fuse block configured to store repair information corresponding to a fail address, and output fuse data in a boot-up operation; a dummy mat formed in a predetermined region of a cell array, and configured to store the fuse data in the boot-up operation; and a repair latch block configured to store the fuse data in the boot-up operation, wherein the fuse data stored in the dummy mat are updated to and stored in the repair latch block in a refresh operation. |
| US09633748B2 |
Multi-channel testing
Apparatus and methods can include an interface chip that can include a test channel to couple to a memory tester, a memory channel controller to couple with a plurality of memory arrays via a plurality of memory channels, and a test circuit coupled between the test channel and the channel controller, the test circuit to provide first and second test clock information to the memory channel controller. In certain examples, the test circuit can operate to receive multiple commands and to propagate the multiple commands to groups of memory channels substantially simultaneously in order to test cross-channel interference using the multi-channel memory. Additional apparatus and methods are disclosed. |
| US09633745B2 |
Semiconductor memory device
A semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation. |
| US09633741B1 |
Semiconductor memory device
An embodiment comprises: a plurality of stacked bodies, each of the stacked bodies including a plurality of control gate electrodes stacked in a first direction, the stacked bodies extending in a second direction intersecting the first direction; an insulating isolation layer disposed between a pair of the stacked bodies adjacent in a third direction intersecting the first direction and the second direction, the insulating isolation layer extending in the second direction; a plurality of semiconductor layers, each of the semiconductor layers extending in the first direction and having its side surface covered by the plurality of control gate electrodes, the semiconductor layers being disposed in a plurality of columns in one of the plurality of stacked bodies; a memory cell disposed between the control gate electrode and the semiconductor layer, the memory cell including a charge accumulation layer; a plurality of bit lines each connected to one end of the semiconductor layer, the bit lines extending in the third direction; and a control circuit being configured to control the control gate electrode and the bit line. The control circuit, during a read operation, applies a first voltage to a first bit line connected to the semiconductor layer positioned in a first column of the plurality of columns, thereby reading a first one of the memory cells connected to the first bit line, and applies a second voltage different from the first voltage to a second bit line connected to the semiconductor layer positioned in a second column which is at a position more distant from the insulating isolation layer than the first column is, thereby reading a second one of the memory cells connected to the second bit line. |
| US09633738B1 |
Accelerated physical secure erase
A storage system includes a controller that is configured to make host data inaccessible. To do so, the controller may control power control circuitry to supply pulses to storage locations storing host data. The pulses may include flash write pulses but no erase pulses, or a combination of flash write pulses and erase pulses. If erase pulses are supplied, the number of the erase pulses may be less than the number supplied for performance of a default erase operation. |
| US09633734B1 |
Driving circuit for non-volatile memory
A driving circuit includes a first driver, a switching circuit and a second driver. The first driver receives and input signal and an inverted input signal, and generates a driving signal. The switching circuit receives the driving signal and a first mode signal. Moreover, an output signal is outputted from an output terminal. The second driver is connected with the output terminal. |
| US09633733B2 |
Method, apparatus and device for data processing for determining a predetermined state of a memory
A method for data processing is suggested including: (i) transforming electrical variables for each cell of a data bit of a memory into a time domain; and (ii) determining a predetermined state by comparing the transformed electrical variables of at least two data bits. |
| US09633723B2 |
High operating speed resistive random access memory
Providing for resistive random access memory (RRAM) having high read speeds is described herein. By way of example, a RRAM memory can be powered at one terminal by a bitline, and connected at another terminal to a gate of a transistor having a low gate capacitance (relative to a capacitance of the bitline). With this arrangement, a signal applied at the bitline can quickly switch the transistor gate, in response to the RRAM memory being in a conductive state. A sensing circuit configured to measure the transistor can detect a change in current, voltage, etc., of the transistor and determine a state of the RRAM memory from the measurement. Moreover, this measurement can occur very quickly due to the low capacitance of the transistor gate, greatly improving the read speed of RRAM. |
| US09633722B2 |
Semiconductor device and method for driving the same
Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain. |
| US09633720B2 |
Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a first memory cell, a second memory cell, and a third memory cell, a first word line coupled to the first memory cell, the second memory cell, and the third memory cell, a first bit line coupled to the first memory cell, a second bit line coupled to the second memory cell, and a third bit line coupled to the third memory cell. A first voltage, a second voltage, and a third voltage are sequentially applied to the first word line, and a fourth voltage is applied to the first bit line when the first voltage is applied to the first word line, applied to the second bit line when the second voltage is applied to the first word line, and applied to the third bit line when the third voltage is applied to the first word line. |
| US09633715B2 |
Semiconductor device capable of attaining ground state in an ising model
It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells. |
| US09633714B2 |
Methods for bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling devices
Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled to the sense amplifiers. By coupling and decoupling voltage from the digit lines, the time interval between refresh operations can be increased. |
| US09633713B2 |
Memory device command receiving and decoding methods
Methods are disclosed. In an embodiment of one such method, a method of receiving command signals, the method comprises receiving command signals in combination with a signal provided to a memory address node at a first clock edge and a second clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge and the second clock edge of the clock signal, represents memory commands. |
| US09633706B1 |
Voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation
A voltage self-boosting circuit for generating a boosted voltage for driving a word line write in a memory array for a memory write operation is provided. A voltage generation circuit(s) is configured to generate a read voltage for a memory read operation and a write voltage for a memory write operation based on a predefined supply voltage. For the memory write operation, a delay circuit delays the delay circuit enable signal by a predetermined delay to generate the output voltage control signal. Accordingly, the voltage generation circuit(s) generates boosted voltage that drives the write voltage to a selected word line(s). For the memory read operation, the voltage generation circuit(s) does not generate the boosted voltage and thus drives the read voltage to the selected word line(s). Hence, it is possible to reduce power consumption and timing delay during the memory read operation or the memory write operation. |
| US09633704B2 |
Read methods of memory devices using bit line sharing
A program method of a nonvolatile memory device includes loading first word line data to be stored in first memory cells connected to a first word line and second word line data to be stored in second memory cells connected to a second word line; setting up upper bit lines according to the first word line data; turning off bit line sharing transistors after the upper bit lines are set up; setting up lower bit lines according to the second word line data; performing a first program operation on the first memory cells using the upper bit lines; turning on the bit line sharing transistors; and performing a second program operation on the second memory cells using the lower bit lines. The bit line sharing transistors electrically connect the upper bit lines and the lower bit lines in response to a bit line sharing signal. |
| US09633703B2 |
Semiconductor memory sensing architecture
A circuit arrangement and method of reading the logic state of a memory cell in an array of semiconductor memory cells. A data memory cell selected from the array drives a current on a first data bit line in a read operation. A reference memory cell corresponding to the memory cell is activated after the memory cell is selected, the reference memory cell driving a current through the reference data line at a greater rate than that of the corresponding memory cell regardless of the logic state of the memory cell. A sense amplifier connected to the data line and a reference data line determines the logic state of the selected memory cell. A delay circuit activates the reference memory cell after the memory cell is selected and enables the sense amplifier after the reference memory cell has been activated. The circuit arrangement further has a latch connected to an output of the sense amplifier, the latch capturing the output from the sense amplifier when the sense amplifier determines the logic state of the selected memory cell and sending a signal to the sense amplifier to disable itself. |
| US09633700B2 |
Power on reset circuit and semiconductor memory device including the same
Provided herein is a power on reset circuit including a voltage dividing unit suitable for dividing an external power supply voltage according to a resistance ratio to output a divided voltage, a signal generating unit suitable for outputting a power on reset signal when the divided voltage has a set level or higher, and a resistance adjusting unit suitable for adjusting the resistance ratio of the voltage dividing unit in response to the power on reset signal. |
| US09633699B2 |
Data storage control device
A data storage control device controls a memory card which, including a non-volatile rewritable memory, operates using an external power supply. A DC/DC converter generates, by having a power supply of a +B voltage, a card operating voltage for operating the memory card. When delayed ACC is completed after an accessory power supply of a vehicle is turned off, a main microcomputer, a shutdown signal control unit, and a transistor set a shutdown terminal of the DC/DC converter to a low level by setting a main control signal input terminal to a high level and, thereby, stops operation of the DC/DC converter. This inhibits the occurrence of a case in which, after the accessory power supply of the vehicle is turned off, the circuit supplying power to the memory card affects other devices mounted in the vehicle. |
| US09633698B2 |
Dynamic control of signaling power based on an error rate
Writing to and reading from dynamic random access memory (DRAM) by a system on chip (SoC) over a multiphase multilane memory bus has power consumption optimized based on bit error rate (BER) and one or more thresholds. The bit error rate (BER) may be measured and used to control parameters to achieve optimal balance between power consumption and accuracy. The bit error rate (BER) measurement, purposely adding jitter, and checking against the thresholds is performed during normal mission-mode operation with live traffic. Error detection may cover every memory data transaction that has a block of binary data. |
| US09633695B2 |
Automatic generation of video from structured content
Apparatus for generation of playable media from structured data, comprises a structured data reading unit for reading in of content of a first structure, a transformation unit for transforming said content into a second structure, said transformation comprising incorporating media play instructions, and a rendering unit for rendering content from the second structure using said media play instructions to generate playable media from the content. |
| US09633690B2 |
Cycle-slip resilient iterative data storage read channel architecture
In one embodiment, a system for cycle-slip resilient iterative read channel operation includes a processor and logic integrated with and/or executable by the processor. The logic is configured to, in an iterative process until a maximum number of iterations has been reached or a valid codeword is produced, execute cycle-slip detection on signal samples to detect one or more cycle-slip events. Also, the logic is configured to selectively alter a timing estimate driving a phase-locked loop (PLL) during any time interval determined to experience a cycle slip in a first pass as indicated by one or more cycle-slip pointers. Additionally, the logic is configured to generate a set of decisions provided by a detector and generate a set of decisions provided by a decoder. Moreover, the logic is configured to output decoding information relating to the signal samples in response to a decoding algorithm producing a valid codeword. |
| US09633688B2 |
Reproducing device
A reproducing device (100) includes (i) an optical pickup (6) for irradiating, with reproduction light, an optical disk (1) which is a super-resolution medium, (ii) an RF signal processing circuit (9) for converting, into a reproduction signal, light which reflected off optical disk (1), (iii) an i-MLSE detecting section (141) for evaluating quality of the reproduction signal, and (iv) a spherical aberration correcting section (142) for correcting a spherical aberration by using a result of evaluation of the quality of the reproduction signal. |
| US09633681B1 |
High-rate skew estimation
In one embodiment, a method includes computing more than one skew estimate within each timing-based servo (TBS) frame. Each skew estimate is related to an estimated position of a magnetic tape read head in relation to a magnetic tape medium. In another embodiment, a system includes a hardware processor and logic integrated with and/or executable by the hardware processor. The logic is configured to cause the hardware processor to compute an initial skew estimate based on longitudinal position (LPOS) sync-pattern detection flags detected using servo channels which process at least two readback signals, with the proviso that the LPOS sync-pattern detection flags are only used to compute the initial skew estimate. The logic is also configured to compute more than one skew estimate within each TBS frame thereafter, each skew estimate being related to an estimated position of a magnetic tape read head in relation to a magnetic tape medium. |
| US09633677B2 |
Near field transducer having an adhesion layer coupled thereto
A system, according to one embodiment, includes a near field transducer; an adhesion layer on a media facing side of the near field transducer, the adhesion layer comprising Ni and Cr; and a protective layer on a media facing side of the adhesion layer. Other systems and methods are described in additional embodiments. |
| US09633672B1 |
Method and device for suppressing ambient noise in a speech signal generated at a microphone of the device
The present disclosure relates to a mobile communication device and a method of controlling a mobile communication device to suppress ambient noise in a speech signal generated at a microphone of the mobile communication device. A primary microphone configured to receive speech and ambient noise and generate a primary speech signal corresponding to the speech and the ambient noise that is received. An accelerometer configured to detect vibrations of the mobile communication device when the speech and the ambient noise are received at the microphone and to generate a signal corresponding to the vibrations that are detected. A processor is operably coupled to the microphone and the accelerometer and configured to generate, using signal processing, a noise suppressed speech signal based on the primary speech signal and the signal received from the accelerometer. |
| US09633670B2 |
Dual stage noise reduction architecture for desired signal extraction
Systems and methods are described to reduce undesired audio. An adaptive noise cancellation unit receives a main signal and a reference signal. The main signal has a main signal-to-noise ratio; the reference signal has a reference signal-to-noise ratio. The reference signal-to-noise ratio is less than the main signal-to-noise-ratio. The adaptive noise cancellation unit reduces undesired audio from the main signal. An output signal from the adaptive noise cancellation unit is input to a single channel noise cancellation unit. The single channel noise cancellation unit further reduces undesired audio from the output signal to provide mostly desired audio. A filter control creates a control signal from the main signal and the reference signal to control filtering in the adaptive noise cancellation unit and to control filtering in the single channel noise cancellation unit. |
| US09633669B2 |
Smart circular audio buffer
An audio buffer is used to capture audio in anticipation of a user command to do so. Sensors and processor activity may be monitored, looking for indicia suggesting that the user command may be forthcoming. Upon detecting such indicia, a circular buffer is activated. Audio correction may be applied to the audio stored in the circular buffer. After receiving the user command instructing the device to process or record audio, at least a portion of the audio that was stored in the buffer before the command is combined with audio received after the command. The combined audio may then be processed, transmitted or stored. |
| US09633662B2 |
Frame loss recovering method, and audio decoding method and device using same
The present invention relates to a frame loss recovering method, an audio decoding method, and an apparatus using the method. A method of recovering a frame loss of an audio signal according to the present invention includes: grouping transform coefficients of at least one frame into a predetermined number of bands among previous frames of a current frame; deriving an attenuation constant according to a tonality of the bands; and recovering transform coefficients of the current frame by applying the attenuation constant to the previous frame of the current frame. |
| US09633659B1 |
Method and apparatus for voice enrolling an electronic computing device
A method and apparatus for voice enrolling an electronic computing device includes a networked server configured to receive voice data over a first communication connection from a first electronic computing device, wherein the voice data comprises a user-specific launch phrase spoken by a user. The networked server is further configured to receive an indication of a second electronic computing device to voice enroll and to initiate voice enrollment of the second electronic computing device over a second communication connection using the voice data. |
| US09633656B2 |
Device registration process from second display
Apparatus and methods to implement a technique for using a second display with a network-enabled television. In one implementation, this feature allows the user to conveniently register and manage their IPTV device directly from a second display device instead of going to a separate registration website. A typical current situation requires the user to either leave the living room for the PC which is inconvenient or perform the registration directly on the IPTV which often has a poor input interface. The second display could be a smart phone that can often be found beside the user, or a laptop or tablet PC, a desktop PC, or the like. After registration, certain convenient follow-up features can be implemented, such as directly selecting the device for browsing, or inheritance of configurations of other available devices for the newly-registered device. |
| US09633650B2 |
System and method of automated model adaptation
Methods, systems, and computer readable media for automated transcription model adaptation includes obtaining audio data from a plurality of audio files. The audio data is transcribed to produce at least one audio file transcription which represents a plurality of transcription alternatives for each audio file. Speech analytics are applied to each audio file transcription. A best transcription is selected from the plurality of transcription alternatives for each audio file. Statistics from the selected best transcription are calculated. An adapted model is created from the calculated statistics. |
| US09633644B2 |
Vehicle vibration and noise reduction system
Provided is a vehicle vibration and noise reduction system that allows the stiffness of the suspension system to be varied while ensuring a favorable noise canceling performance under all conditions. A variable elastic member (4) is incorporated in a vehicle suspension system, and a noise control unit (56) causes a canceling sound to be emitted from a loudspeaker (32) according to a reference signal obtained from a strain sensor (31) provided on the variable elastic member and an error signal obtained from a noise detection unit (33) for detecting noises in the passenger compartment of the vehicle. The noise control unit is configured to change a noise canceling property of the noise control unit depending on the elastic modulus of the variable elastic member. |
| US09633643B1 |
Bell for a bicycle
A bell for a bicycle comprises a mounting bracket for securing the bell to a bicycle handle bar, a striker moveably attached to the mounting bracket, and an arcuate shaped ringer supported outwardly and spaced from the mounting bracket by suspension means that allow the ringer to reverberate when struck by the striker. |
| US09633641B2 |
Grid based user interference for chord presentation on a touch screen device
Improvisation or playing along with a musical group or with a song is enjoyable to people and musicians of all ability levels. However, it is easy to play notes which do not harmonize with other notes and pitches which are being played. Provided herein is a method, computer program product and electronic device for assigning a set of pitches to a plurality of cells of an electronic device having a touch screen input device. The method may include the steps of obtaining an input chord, disassembling the chord into at least one base note and a plurality of individual voices, arranging a predetermined number of voices of the chord according to at least one predefined rule, and assigning at least one set of pitches to a plurality of cells of an electronic device, said set of pitches corresponding to the base note and arranged predetermined number of voices of the chord. The present method allows a musician to freely play along without the possibility of playing an errant note as the user does not control the actual pitch associated with the cells being indicated by a user on the touch screen. |