最新美国发明专利第2017-03-21期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09602428B2	Method and apparatus for locality sensitive hash-based load balancing A method in a computing device for locality sensitive load balancing between servers includes receiving a packet and querying a plurality of Bloom filters, using keys based upon a plurality of header field values of the packet, to generate a plurality of candidate servers. A subset of the candidate servers were generated due to false positive matches occurring from some of the plurality of Bloom filters. One server of the plurality of servers is identified as the destination for the packet based upon identifying the subset of candidate servers within an entry of a false positive table. Each false positive table entry identifies, for a flow of packets, servers that are falsely included in sets of candidate servers generated by the plurality of Bloom filters for packets of that flow. The packet is transmitted to the first server.
US09602426B2	Dynamic allocation of resources while considering resource reservations Described herein are technologies relating to computing resource allocation among multiple tenants. Each tenant may have a respective absolute reservation for rate-based computing resources, which is independent of computing resource reservations of other tenants. The multiple tenants vie for the rate-based computing resources, and tasks are scheduled based upon which tenants submit the tasks and the resource reservations of such tenants.
US09602425B2	Zero sign-on authentication A authenticating system and process for authenticating user devices to a access a media service where access to certain portions of the media service may be limited according to a gateway or other device used by a user device to facilitate interfacing a user with the media service. The authentication may be achieved without directly assessing a trustworthiness of the user devices, and optionally, without requiring a user thereof to complete a sign-on operation.
US09602424B1	Connection balancing using attempt counts at distributed storage systems A connection request from a client is received at an access subsystem node of a distributed storage service. The connection request includes an attempt count parameter indicative of a number of times an establishment of a connection on behalf of the client has been attempted. A workload threshold level based on the attempt count parameter is identified for use in an acceptance decision for the connection request. In response to a determination that a local workload metric of the access subsystem node is below the workload threshold level, the connection is accepted.
US09602422B2	Implementing fixed points in network state updates using generation numbers Some embodiments provide a novel network control system that provides publications for managing different slices (e.g., logical and/or physical entities) of a network. The publications are published from publisher controllers in the network control system to subscriber controllers. The network control system uses publications with generation numbers and buffered subscribers to implement the fixed points in order to help maintain a consistent network state. The information published with a publication is useful for resolving conflicts in the network control system when multiple publisher controllers provide conflicting inputs to a subscriber controller.
US09602415B2	Flow based network service insertion Techniques are provided to generate and store a network graph database comprising information that indicates a service node topology, and virtual or physical network services available at each node in a network. A service request is received for services to be performed on packets traversing the network between at least first and second endpoints. A subset of the network graph database is determined that can provide the services requested in the service request. A service chain and service chain identifier is generated for the service based on the network graph database subset. A flow path is established through the service chain by flow programming network paths between the first and second endpoints using the service chain identifier.
US09602410B2	Method, device, and system for processing acknowledgement packet Embodiments of the present application disclose a method, a device, and a system for processing an acknowledgement packet, and relate to the field of communications technologies. A sending period and a data volume threshold are set on a data transmission device, and the data volume threshold is used to control acknowledgement packets sent by the data transmission device to a data sending end within each sending period, so that a total data volume that is reflected by all the sent acknowledgement packets as having been acknowledged by a data receiving end is within the data volume threshold. Thereby a problem of sending a large quantity of packets by the data receiving end is solved.
US09602409B2	Apparatus and method for multilateral one-way communication An apparatus and a method for multilateral one-way communication are provided. The apparatus includes a one-way input module unit, detachably mounted to a plurality of slots formed in a rail, for receiving data from an external transmission host and for transmitting the received data to an internal network through one-way communication; a one-way output module unit, mounted detachably to the plurality of slots formed in the rail, for transferring data of interest to an internal network through one-way communication, and transmitting data of interest to an external reception host, and a two-way module unit, mounted detachably to the plurality of slots formed in the rail, for performing data communication between the transmission host and the reception host in a bidirectional mode.
US09602408B2	General input/output architecture, protocol and related methods to implement flow control An enhanced general input/output communication architecture, protocol and related methods are presented.
US09602403B2	Method and apparatus for transmitting and receiving packet in broadcasting system A method and an apparatus for transmitting and receiving packets in a broadcasting system are provided. The present disclosure allocates a padding size field by using padding octets, and thus can increase transmission efficiency. Also, the present disclosure does not restrict the number of padding octets while maintaining compatibility with existing disclosures, and thus can carry out as much padding as desired and as necessary. In addition, the present disclosure variably allocates the padding size field depending on the number P of padding octets, and thus can increase header efficiency. Furthermore, since the number of padded octets in a header is immediately known, the size of an actual payload is known in advance, and thus rapid transmission is possible.
US09602393B2	Unregistered multicast packet forwarding to multicast router ports In one embodiment, a system includes a switching processor and switching logic integrated with and/or executable by the switching processor. The switching logic is configured to install a Multicast Control (MC) table on the switching processor, the MC table facilitating management of switching across a virtual local area network (VLAN) via the switching processor. The switching logic is also configured to install a multicast router flood entry on the MC table at least partially in response to detecting that at least one multicast router is communicatively coupled to a port of the system, and receive at least one multicast packet at the switching processor. Moreover, the switching logic is configured to send the at least one multicast packet to a received multicast packet destination at least partially in response to determining the received multicast packet destination based at least in part on the multicast router flood entry.
US09602390B2	Apparatus and method for determining optimum routing in a communication network A node device receives first data communicated between the node device and adjacent node devices. The node device calculates a link cost between the node device and each of the adjacent node devices, based on the first data, and corrects the link cost using a first cost depending on communication performance of the each adjacent node device. The node device stores, in association with the each adjacent node device, a first integrated link-cost value obtained by adding the corrected link cost to a second integrated link-cost value that is obtained by summing up link costs along a communication route from a destination node device serving as a final destination of second data to the each adjacent node device. The node device transmits, to the adjacent node devices, the first data including the second integrated link-cost value and a second cost depending on communication performance of the node device.
US09602381B1	Real time adaptive monitoring This disclosure describes systems and methods for dynamically and automatically adapting the level of data logging that occurs within a network of nodes, identifying causes of exceptions that occur within the network and resolving those causes to ensure that the network continues operating efficiently. A monitoring service may automatically increase/decrease data logging of various nodes within the network as it progresses through levels of a network searching for a node that is the source of a cause of an exception. Once identified, the monitoring service may process the logged data and either automatically resolve the cause of the exception or provide information to an operator for resolution.
US09602380B2	Context-aware dynamic policy selection for load balancing behavior Dynamically updating load balancing policies based on operations, administration, maintenance, and provisioning (OAMP) data generated by a load balancing network may provide increased load balancing performance. As an example, an existing set of load-balancing policies can be dynamically modified based on OAMP data generated by load balancers and/or network elements. As another example, new load-balancing policies can be dynamically created based on the OAMP data. As yet another example, an updated set of load-balancing policies can be selected from a pool of policies based on OAMP data. Dynamically updating load balancing policies can be achieved using information model processing frameworks, such as the next generation directory enabled networks (DEN-ng) model.
US09602377B2	Network latency estimation for mobile devices Embodiments calculate an estimated latency between computing devices. A latency service aggregates latency records defining latency measurements and corresponding latency factors from a plurality of computing devices. From the aggregated latency records, the latency service defines relationships between the latency measurements and the corresponding latency factors. Responsive to a request for an estimated latency from a mobile computing device, the latency service applies the defined relationships to estimate the latency based on the latency factors associated with the received request. In some embodiments, the estimated latency includes three portions: a first latency value representing the latency from the mobile computing device to a cell site, a second latency value representing the latency from the cell site to an access point, and a third latency value representing the latency from the access point to a destination computing device.
US09602374B2	Systems and methods for collecting and analyzing data to determine link quality and stability in layer two networks A method and network element include receiving, at a receiver node, at least one of sender timestamps and sequence numbers in continuity check (CC) frames sent by a sender node; determining receiver timestamps at the receiver node; detecting instability based on one or more of the at least one of sender timestamps and sequence numbers and the receiver timestamps; and performing a remedial action based on the detecting instability. The CC frames can include Bidirectional Forwarding Detection (BFD) or Continuity Check Message (CCM) frames which are regularly transmitted in a session, but do not currently include timestamps or sequence numbers.
US09602370B2	Determining overall network health and stability A network health analyzer that analyzes health of a computer network may be implemented in accordance with an embodiment of the present invention. A network profile including an issue profile and one or more benchmarks appropriate for the network is determined. A set of numeric measures that is common to all issues in the issue profile is established. The network health analyzer collects data points pertaining to the operation of the network. Based on the data points, numeric values corresponding to the numeric measures may be calculated. In turn, health indexes for all issues in the issue profile may be determined. Based on these health indexes for the issues, an overall health rating may be determined.
US09602367B2	System, method, and computer program product for creating a header detail record A system, method, computer program product and computer processor-implemented method of generating a header detail record (HDR) for a hypertext transport protocol (HTTP) data browsing user accessing network resources, may include: receiving, by at least one computer processor, packet data from at least one probe tapping into at least one network element of a data network of a communications services provider, said packet data comprising: header data, and payload data; analyzing said packet data comprising: extracting at least one header detail record (HDR) from said header data and said payload data for all said packet data, and creating said at least one header detail record (HDR).
US09602359B2	Methods, systems, and computer program product for providing graphical cross connectivity and dynamic configurability Disclosed are methods, systems, and articles of manufactures for graphical cross connectivity and dynamic configurability for interconnection between inputs and outputs of a device. Various implementations identify instructions from a user interface to graphically display various view modes that include a global view mode showing all active connections between inputs and outputs or one or more program modes showing all active connections for identified input(s) or identified output(s). Some implementations also provide user interface functions to dynamically query, control, or configure the device and the connectivity between the inputs and the outputs based at least in part upon various view modes of the connectivity of the device.
US09602355B2	Network interface with adjustable rate A method, system, and computer-readable medium for a network interface with adjustable rate are disclosed. For example, one method involves receiving a request to activate a virtual lane of an interface, where the request is received by a first node. The interface is configured to facilitate data communication between the first node and a second node, and the interface includes a plurality of virtual lanes that include at least one active virtual lane, and at least one inactive virtual lane. The method also involves, in response to receiving the request, negotiating with the second node to select an additional virtual lane from the at least one inactive virtual lane. The method involves activating the additional virtual lane. After the activating, the first node and the second node are configured to use the active virtual lane(s) and the additional virtual lane for data communication.
US09602347B2	Method, system and program for browser to switch IE kernel The present invention discloses a method, a system and a program for a browser to switch an IE Kernel which may be able to solve the problems of compatibility and adaptability of the browser kernel. The method comprises: generating a first IE kernel file and a second IE kernel file, and import them into a browser client; the browser process determining a currently adapted IE kernel version according to Uniform Resource Locator (URL) information submitted by a user; if the currently adapted IE kernel version is the first IE kernel, the browser process being redirected to a corresponding location to load the first IE kernel file; if the currently adapted IE kernel version is the second IE kernel, the browser process being redirected to a corresponding location to load the second IE kernel file.
US09602346B1	Configuration data handling in wireless communication devices Enhanced handling of device configuration data in wireless communication devices is provided herein. In one example, a method is presented that includes receiving data transferred by a device management node for incorporation into a node of a configuration data tree that stores device configuration data for the wireless communication device. The method also includes identifying the data as unable to be incorporated into the configuration data tree, and transferring a rejection notice for delivery to the device management node. The method also includes receiving a node addition instruction and responsively creating a new data tree that is populated with at least one blank node and is linked to a root node shared with the configuration data tree. The method also includes receiving again the data transferred by the device management node and responsively incorporating the data into the blank node of the new data tree.
US09602344B1	Automated establishment of access to remote services A software application designed to operate within an enterprise system is modified to operate properly within a system of a third-party provider. In one embodiment, a site manager obtains pertinent information about the software application from the source systems that make up the enterprise system and provides it to a cloud manager, and the cloud manager uses the information to generate a modified version of the software application for use on the cloud provider. The modification may include operations such as driver injection, file system mounting customization, customization of hostname-to-network address mappings, and boot image creation. Secure connections may also be established between the enterprise system and third-party provider to allow the application running on the third-party provider to access the services of the enterprise system.
US09602341B1	Secure multi-tenant virtual control server operation in a cloud environment using API provider In a system that separates the control (management) layer from the data layer of a distributed storage system, an application programming interface (API) provider is presented that manages storage awareness of the virtual control servers with at least one virtual array and underlying physical arrays. The system described herein advantageously enables multi-tenant support to provide individual and/or isolated access to shared storage resources among multiple tenants and offers improved scalability and operations in a cloud deployment.
US09602340B2	Performance monitoring Real-time data is extracted from a log file for at least one monitored process on each of a plurality of servers. For each monitored process, extracted real-time data is inserted into object variables of an object. The object variable data is processed to generate performance statistics for the monitored processes and to determine whether to trigger an alarm. A database is updated with object variable data and performance statistics when an event associated with a monitored process takes place. Historical performance statistics from the database are compared with current performance statistics to determine a performance trend.
US09602338B2	System and method for network packet event characterization and analysis A computer implemented method for network monitoring includes providing network packet event characterization and analysis for network monitoring that includes supporting summarization and characterization of network packet traces collected across multiple processing elements of different types in a virtual network, including a trace slicing to organize individual packet events into path-based trace slices, a trace characterization to extract at least 2 types of feature matrix describing those trace slices, and a trace analysis to cluster, rank and query packet traces based on metrics of the feature matrix.
US09602337B2	Event and alert analysis in a distributed processing system Methods, apparatuses, and computer program products for event and alert analysis are provided. Embodiments include a local event analyzer embedded in an alert analyzer receiving events from an event queue. Embodiments also include the local event analyzer creating, based on the received events and local event analysis rules specific to the alert analyzer, a temporary alert for the alert analyzer. Embodiments also include the alert analyzer analyzing the temporary alert based on alert analysis rules.
US09602331B2	Shared interface among multiple compute units Providing a shared interface among a plurality of compute units is disclosed. A plurality of compute units is determined and a shared interface for the plurality of compute units is provided, wherein incoming traffic is received by any of the plurality of compute units. Also, the packet is received at the shared interface for a plurality of compute units. The packet is encapsulated using a first header, wherein the first header specifies one of the plurality of compute units, and wherein the one of the plurality of compute units is selected independent of an interface address associated with the shared interface.
US09602326B2	Apparatus and method for transmitting signal, apparatus and method for receiving signal An apparatus for transmitting a signal in accordance with an embodiment of the present invention includes a mapper configured to map a modulation symbol to a bit signal by referencing the constellation. The constellation includes a plurality of blocks, and each block includes constellation points, each of which has in-phase (I) axis component value and quadrature-phase (Q) axis component value whose difference from the I axis or Q axis component value of a reference point of the block is a first difference value or a second difference value.
US09602322B2	Transmission and reception of discovery signals over a radio frequency spectrum band Techniques are described for wireless communication. A first method includes receiving a first orthogonal frequency division multiplexing (OFDM) symbol including a plurality of reference signals (RSs) over a radio frequency spectrum band. The first method may also include receiving a second OFDM symbol including a first synchronization signal over the radio frequency spectrum band. A second method includes transmitting a first OFDM symbol including a plurality of RSs over an radio frequency spectrum band. The second method may also include transmitting a second OFDM symbol including a first synchronization signal over the radio frequency spectrum band. In each method, a first portion of the first OFDM symbol includes a higher density of the RSs than a remaining portion of the first OFDM symbol, and when included, the second OFDM symbol may be adjacent in time to the first OFDM symbol.
US09602321B2	Broadcast signal transmitting apparatus, broadcast signal receiving apparatus, broadcast signal transmitting method, and broadcast signal receiving method Disclosed herein is a method of receiving a broadcast signal. The method comprises receiving the broadcast signal; an Orthogonal Frequency Division Multiplexing (OFDM) demodulating on the received broadcast signal; parsing at least one signal frame from the demodulated broadcast signal to extract service data or service component data; converting the service data or service component data into bits; decoding the converted bits; and outputting a data stream comprising the decoded bits.
US09602317B1	Apparatus and method for combining currents from passive equalizer in sense amplifier An apparatus configured to apply equalization to an input data signal and detect data based on the equalized data signal. The apparatus includes a passive equalizer comprising a first signal path configured to generate a first signal based on an input signal, and a second signal path configured to generate a second signal by filtering the input signal. The apparatus further includes a sense amplifier having an input circuit configured to generate a third signal related to a combination of the first and second signals, and a data detection circuit configured to generate data based on the third signal. The data detection circuit may be configured as a strong-arm latch. The third signal may be a differential current signal including positive and negative current components. The strong-arm latch generating data based on whether the positive current component is greater than the negative current component.
US09602310B2	Associating system requests with SMS user responses A messaging system can initiate a communication with one or more users through via cell phone text messages, for example using the short message service protocol. These systems often need a way to correlate user responses with system requests or queries. This problem can present challenges because the email mailbox metaphor used by cell phone user interfaces generally allows users to reply to any previously sent messages, but no message context is automatically supplied. A system that may send multiple messages to a user needs a mechanism by which the system can correlate a user-sent response to one of potentially many system-sent requests or queries. Context correlation to resolve ambiguities can be based on one or more of a dialog-based solution, a token-based solution and a keyword-based solution.
US09602306B2	Method, system and apparatus for efficient multilayer optical networking The method comprising: receiving, a controller (106), traffic packets from a device, each one of said traffic packets including a VLAN tag indicating a destination of a second device; analyzing, by a first monitoring unit (101) during a period of time, the bytes content of said received packets and reporting said analysis to said controller (106); receiving, said controller (106), said plurality of different subcarriers to be used for said sending; adding, by a tag unit (102), an embedded S-VLAN tag to said analyzed packets identifying to which subcarrier and to which sliceable bandwidth variable transponder (105) each tagged traffic packets per destination is going to be sent; sending said S-VLAN tagged traffic packets to a switch (104), the latter forwarding them to a given port of said identified sliceable bandwidth variable transponder (105) for sending them via different sub-carriers to its corresponding destination, said plurality of different sub-carriers following a same or different path.
US09602304B2	Data transfer device system, network system, and method of changing configuration of network system To improve fault tolerance of a ring network, provided is a data transfer device system belonging to a ring network system. The data transfer device system includes a plurality of data transfer devices; the plurality of data transfer devices including a first data transfer device and a second data transfer device connected with the first data transfer device; the first data transfer device having a first ring port; and the second data transfer device having a second ring port. The first data transfer device controls whether to permit the first ring port and the second ring port to transfer data based on a state of the network system, an attribute of the first data transfer device in the data transfer device system, and an attribute of the data transfer device system in the network system.
US09602303B2	Identifying nodes in a ring network Methods and systems for determining a token master on a ring network are provided in which possession of an arbitration token permits a blade participating in the ring network to transmit a packet. According to one embodiment, when an event at a blade represents expiration of a timeout period for receipt of the token, a new token is transmitted onto the ring network. When the event represents receipt of the token, then the priority of the originating blade is compared that of the first blade. When the originating blade is higher priority, the token is transmitted to the next blade. When the originating blade is lower priority, the first blade is set as the originating blade and the token is transmitted to the next blade. When the priorities are equal, the blade becomes responsible for periodically transmitting a discovery marker onto the ring network to facilitate topology discovery.
US09602301B2	System and method for commissioning wireless building system devices A building commissioning system includes a controller and an electronic database for storing a building layout that includes desired locations for devices to be mounted in a building. The system includes a portable wireless unit with a display for use by an installer. The display on the portable wireless unit shows a graphical representation of the building layout for an area selected by an installer to illustrate desired locations for devices, such as lighting fixtures and wall switches, to be installed in the building. Upon installing a device at the desired location, an installer obtains a unique identifier for the installed device that is matched with the corresponding installed location. The unique identifier and the installed location are sent to the controller for storage in the electronic database. The stored device and location information enable a user to control or adjust device operations.
US09602300B2	Smart device-based home network system and control method therefor A smart device-based home network system including: a plurality of peripheral devices; a smart device in which a home network application is installed; a video phone for receiving and processing information on a peripheral device, transmitted from the corresponding peripheral device, and then transmitting the information to a push server in a push manner; and the push server for transmitting, to all smart devices included in the information, a wake-up signal together with the information on the peripheral device on the basis of the processed information on the peripheral device, transmitted from the video phone.
US09602298B2	Methods and apparatuses for determining a type of control field Systems, method and apparatus of managing wireless communication are described herein.
US09602297B2	Establishment of reliable multicast/broadcast in a wireless network Various example embodiments are disclosed relating to the establishment of reliable multicast/broadcast sessions in a wireless network. According to an example embodiment, an apparatus may be configured to receive, from a wireless recipient station, a request to establish a reliable multicast/broadcast session with the recipient station. The apparatus may be further configured to transmit, to the recipient station, a response to the request to establish the reliable multicast /broadcast session. The response may include one or more retransmission fields describing a retransmission of data for the requested reliable multicast/broadcast session. For example, the request may include a retransmission multicast address to be used for retransmission of data for the multicast/broadcast session.
US09602295B1	Audio conferencing server for the internet An audio conferencing server that facilitates free form multi-party conversations between computer users. The audio conferencing server includes gateway elements, mixing elements, and a control element. A method for using the audio conferencing system to facilitate free form multi-party conversations between computer users, particularly in a three-dimensional virtual world using an audio conferencing server.
US09602294B1	Rendezvous point link resiliency for bidirectional protocol independent multicast (PIM-BIDIR) Techniques provide rendezvous point link (RPL) resiliency for bidirectional protocol independent multicast (PIM-BIDIR) in a computer network. According to the techniques, when two or more RPL partitions have a same RPL subnet, routers on the RPL subnet are configured to elect an active RPL partition that will function as a RPL. The routers on any inactive RPL partitions may then treat the inactive RPL partitions as regular links in the RPL subnet and build a route to the active RPL partition. In some examples, the network is configured to include the two or more RPL partitions with the same RPL subnet as Anycast RPLs in the network. In other examples, the routers on the RPL subnet are configured to detect when an original RPL is separated into the two or more RPL partitions due to a failure of the original RPL.
US09602289B2	Steganographic embedding of executable code A method for digital immunity includes identifying a call graph of an executable entity, and mapping nodes of the call graph to a cipher table of obscured information, such that each node based on invariants in the executable entity. A cipher table maintains associations between the invariants and the obscured information. Construction of an obscured information item, such as a executable set of instructions or a program, involves extracting, from the cipher table, ordered portions of the obscured information, in which the ordered portions have a sequence based on the ordering of the invariants, and ensuring that the obscured information matches a predetermined ordering corresponding to acceptable operation, such as by execution of the instructions represented by the obscured information, or steganographic target program (to distinguish from the executable entity being evaluated). The unmodified nature of the executable entity is assured by successful execution of the steganographic target program.
US09602287B2	Method and system for signed stateless data transfer According to some embodiments, a method and system provides receiving a first request for service from a client during a communication session by a server, providing a response to the first request to the client, the response to the first request including state information specific to the first request and a memory of the server; clearing the server memory of the state information specific to the first request; receiving, by the server, a second request for service from the client during the communication session, the second request including the state information specific to the first request; and restoring a state of the server memory based on the state information specific to the first request received in the second request.
US09602282B2	Secure software and hardware association technique Authenticated hardware and authenticated software are cryptographically associated using symmetric and asymmetric cryptography. Cryptographically binding the hardware and software ensures that original equipment manufacturer (OEM) hardware will only run OEM software. Cryptographically binding the hardware and software protects the OEM binary code so it will only run on the OEM hardware and cannot be replicated or altered to operate on unauthorized hardware. In one embodiment, critical security information associated with the equipment is loaded from a memory at startup time. The critical security information is stored in the memory, in encrypted form, using a unique secret value. The secret value is used to retrieve a chip encryption key and one or more image authentication keys that can be used to associate program code with an original equipment manufacturer. These keys are used to authenticate the program code.
US09602280B2	System and method for content encryption in a key/value store System and method embodiments are provided for content encryption in a key/value store. The embodiments include encrypting both the key and value of client data blocks for storage so that the data can be retrieved reliability without compromising the key. An embodiment method includes obtaining a key from a data block comprising the key and a value, encrypting the key using a deterministic encryption algorithm with an encryption key to map the key to a cypher text in a one-to-one mapping, and encrypting the value using a second encryption algorithm to randomly map the value to a second cypher text. Encrypting both the key and the value provides more protection to the client data instead of encrypting only the value and leaving the key vulnerable without encryption. The encrypted key can also be protected from unauthorized access and from the owner of the database or the storage system.
US09602278B2	Encryption device, cipher-text comparison system, cipher-text comparison method, and cipher-text comparison program An encryption device calculates a derived key by taking a document as a numerical value and corresponding identifier as input values and generates a cipher-text-by-identifier acquired by encrypting the document through a calculation taking the documents as input values, and a comparison unit generates relative values used for a greater-than-and-less-than comparison assessment between the plain text and another plain text through a calculation using a second hash function taking the derived key and plain text as input values, generates a relative value cipher-text through a calculation taking the derived key, the identifier, and the relative value as input values, generates a character string constituted with the cipher-text-by- identifier and the relative value cipher-text as a cipher-text, restores the relative values corresponding to the different cipher-texts through calculations using the second hash function, and performs a greater-than-and-less-than assessment on the encrypted different plain texts.
US09602276B2	Method and apparatus for virtual pairing with a group of semi-connected devices One feature provides a method for a client node to establish a session key with a group node by obtaining an epoch identity value associated with a current epoch, wherein obtaining the epoch identity value includes one of computing the epoch identity value based on a node real time or negotiating the epoch identity value with the group node, computing a restricted key using a shared secret key, the epoch identity value, and a group node identity associated with the group node, and executing a session key establishment protocol with the group node to derive the session key using the restricted key as a master key in the session key establishment protocol. The session key may be established between the group node and the client node even though communications between the group node and the central node is only intermittently available during the current epoch.
US09602263B2	ACK/NACK transmission method in wireless access system and apparatus therefor An ACK/NACK (acknowledgement/negative-ACK) transmission method in a wireless access system that supports device-to-device communication and an apparatus therefor are disclosed. Specifically, a method for transmitting ACK/NACK in a wireless access system that supports the device-to-device communication comprises the steps of: receiving first data in a first sub-frame, receiving second data from a base station in a second subframe, and when data transmission and reception through the device-to-device communication carried out in a third sub-frame for transmitting the ACK/NACK information on the first data, transmitting, to the base station in a fourth sub-frame, a grouped ACK/NACK information including the ACK/NACK information on the first data and the ACK/NACK information on the second data.
US09602256B2	Method and apparatus for mobile terminal to switch base station The present invention provides a method including receiving, by a terminal, a switching command is large. The method includes: acquiring designated channel resource information from channel resources used by a source base station; acquiring information of a relevant base station using a designated channel resource except the source base station; sending indication signaling to the relevant base station according to the information of the relevant base station, where the indication signaling carries the designated channel resource information, the indication signaling is used to instruct the relevant base station to stop using the designated channel resource when the mobile terminal switches to a target base station; sending a switching request message to the target base station; and sending the switching command to the mobile terminal through the designated channel resource.
US09602255B2	System and method for data channel transmission and reception A method for operating a communications controller includes allocating a number of resource blocks to an enhanced physical downlink shared channel (ePDSCH), and identifying a starting point for the resource blocks of the ePDSCH, the starting point located within a control region of a subframe. The method also includes signaling to a user equipment (UE) the starting point of the resource blocks and the number of resource blocks allocated to the ePDSCH.
US09602254B2	Component carrier allocation method and device, and computer storage medium with improved communication quality of UE moving at high speed in cell Disclosed are a method, device, and a computer storage medium for component carrier allocation. The method includes that when it is determined that a component carrier which has a frequency exceeding a preset threshold exists in component carriers which are available to be allocated currently in a cell, a FDM of UE in the cell is updated according to the coverage of the component carrier which has a frequency exceeding the preset threshold; and frequency domain priority is determined according to the updated FDM, and the component carrier which has a frequency exceeding the preset threshold is allocated for the UE in the cell according to the frequency domain priority.
US09602253B2	Method and apparatus for making HARQs in carrier aggregation systems The present invention relates to a method and system for making a hybrid automatic repeat requests (HARQ) in a carrier aggregation system. The method receives downlink data through a first subframe of a first carrier, transmits acknowledgement/negative-acknowledgement (ACK/NACK) for the downlink data through a second subframe of a second carrier, and re-receives the downlink data through a third subframe of the first carrier, wherein the first carrier only includes the downlink subframes, and the second carrier includes the uplink subframes and the downlink subframes.
US09602252B2	Wireless communications terminal, base station device, and resource allocation method The purpose of the present invention is to avoid ACK/NACK collision in a system in which E-PDCCH control information is transmitted, increase the utilization efficiency of ACK/NACK resources, and suppress unnecessary PUSCH band reduction. A wireless communications terminal having a configuration comprising: a reception unit that receives control signals including ACK/NACK indexes, via an expanded physical downlink control channel; a control unit that determines, on the basis of the ACK/NACK indexes, whether to use a dynamically allocated dynamic ACK/NACK resource or a specified resource specified beforehand, to send downlink data ACK/NACK signals; and a transmission unit that sends the ACK/NACK signals using the dynamic ACK/NACK resource or the specified resource, as determined.
US09602251B2	Devices for reconfiguring uplink and downlink allocations in time domain duplexing wireless systems A User Equipment (UE) for reconfiguring uplink and downlink (UL-DL) allocations is described. The UE includes a processor and instructions stored in memory that is in electronic communication with the processor. The UE determines whether at least one subframe is convertible over a default Time Domain Duplexing (TDD) UL-DL configuration. If at least one subframe is convertible, then the UE determines a first reference UL-DL configuration and a second reference UL-DL configuration. The UE also sends any hybrid automatic repeat request acknowledgement (HARQ-ACK) information corresponding to a Physical Downlink Shared Channel (PDSCH) based on the first reference configuration. The UE further determines a Physical Uplink Shared Channel (PUSCH) schedule based on the second reference UL-DL configuration. The UE additionally receives any hybrid automatic repeat request acknowledgement (HARQ-ACK) information corresponding to a Physical Uplink Shared Channel (PUSCH) based on the second reference UL-DL configuration.
US09602248B2	Method of transmitting and receiving ARQ feedback information A method for transmitting and receiving ARQ feedback information in a wireless communication system is disclosed. A method for allowing a mobile station to transmit an ARQ feedback in a broadband wireless access system includes receiving an ARQ block and an ARQ feedback polling from the base station, wherein the ARQ feedback polling requests the mobile station to transmit ARQ feedback information indicating whether the ARQ block is successfully received, receiving a first uplink resource for transmitting the ARQ feedback from the base station, and determining whether the received ARQ block is successfully received. The first uplink resource has a minimum size capable of being allocated to the ARQ feedback information.
US09602247B2	Method and device for retransmission Embodiments related to retransmission in a communication system are described and depicted. In one embodiment, a retransmission entity repeats a transmission of a data transfer unit by the device after a predetermined number of other transmitted data transfer units has been transmitted. The retransmission entity may also determine whether a measure for a time period since the first transmission of the data transfer unit by the device has exceeded a predetermined threshold and to provide a final transmission of the data transfer unit based on the determining that the measure for the time period has exceeded the predetermined threshold.
US09602245B2	Transmitting apparatus and interleaving method thereof A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to perform a low-density parity check (LDPC) encoding on input bits using a parity check matrix to generate an LDPC codeword comprising information word bits and parity bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
US09602244B2	Low density parity check encoder having length of 16200 and code rate of 4/15, and low density parity check encoding method using the same A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword having a length of 16200 and a code rate of 4/15. The second memory is initialized to 0. The processor generates the LDPC codeword corresponding to information bits by performing accumulation with respect to the second memory using a sequence corresponding to a parity check matrix (PCM).
US09602243B2	Low density parity check encoder, and low density parity check encoding method using the same A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).
US09602240B1	Method and system for symbol level interference cancellation at a receiver for multiuser detection Methods and systems of symbol level interference cancellation at a receiver for multiuser detection is provided. In an embodiment, the method includes performing an interference cancellation based decoding for a plurality of users through a plurality of iterations for generating a plurality of soft bit estimates for each of the users during each of the iterations. Each of the iterations involves sequential cancellation of each of the user signals for performing interference cancellation based decoding for each subsequent user other than a first user. The method also includes re-using the generated plurality of soft bit estimates for performing each subsequent iteration of the interference cancellation based decoding of the plurality of users. A plurality of soft bit estimates associated with each user generated during an (N−1)th iteration is re-used during an Nth iteration for the user, N being a whole number with a minimum value of 2.
US09602239B2	Receiver for wireless communications networks A receiver receiving in a cell at least first and second data streams included in at least first and second signals. The receiver includes: a first estimating unit configured to receive the first and second signals and provide an estimate of first data on the first data stream; a regenerating unit configured to provide a regenerated first data stream based on the first data estimate and attenuation of first radio channels transmitting the first data stream; a second estimating unit configured to provide an estimate of second data on the second data stream based on the regenerated first data stream, on the first and second signals, on attenuation of second radio channels transmitting the second data stream, and on inter/intra-cell interference; and first and second extractions units configured to extract first and second information within the first and second data based on the estimates of the first and second data.
US09602238B2	Decoding method and apparatus Embodiments of the present invention provide a decoding method and apparatus. The method includes: acquiring a demodulation signal; acquiring a first decoding signal, where the first decoding signal is a signal fed back after the ith M-ary differential decoding processing is performed on the demodulation signal, and i is an integer greater than or equal to 0; and performing M-ary differential decoding processing on the demodulation signal according to the first decoding signal, to obtain a second decoding signal. The first decoding signal that is fed back is added and input to a decoder.
US09602237B2	Sideband parity handling An inbound sideband interface is provided to receive a message over a first sideband link, and parity logic is provided to calculate a parity bit for the message. Further, an outbound sideband interface is provided to forward the message to another device over a second sideband link. The second sideband link includes a plurality of data wires and a parity bit wire. The message is forwarded over at least some of the data wires and the parity bit is sent to the other device over the parity bit wire to correspond with the message.
US09602236B2	Computing system with decoding adjustment mechanism and method of operation thereof A computing system includes: an inter-device interface configured to receive a receiver signal for representing a serving signal; a communication unit, coupled to the inter-device interface, configured to: calculate a decoding result based on decoding the receiver signal, generate a parity portion adjustment for adjusting the decoding result, generate a systematic portion adjustment for adjusting the decoding result, and apply the parity portion adjustment and the systematic portion adjustment to the decoding result for determining the serving signal from the receiver signal.
US09602235B2	Code block segmentation and configuration for concatenated turbo and RS coding A method for performing code block segmentation for wireless transmission using concatenated forward error correction encoding includes receiving a transport block of data for transmission having a transport block size, along with one or more parameters that define a target code rate. A number N of inner code blocks needed to transmit the transport block is determined. A number M—outer code blocks may be calculated based on the number of inner code blocks and on encoding parameters for the outer code blocks. The transport block may then be segmented and encoded according to the calculated encoding parameters.
US09602231B2	OFDM signal processing method and apparatus The invention provides a reception method and apparatus which provides a series of frequency shifts and filtering operations to sideband signals (lower, upper, and middle), to enable detection if the central part of a signal is analog or digital, and to enable effective co-channel interference compensation. The invention enables (H)IBOC signals for example to be processed with a narrower bandwidth and therefore a lower processing clock speed and complexity is made possible compared to the conventional (H)IBOC-signal processing approach.
US09602226B2	Distributed spectrum analyzer and method of spectrum analysis applying same A distributed spectrum analyzer and a method of spectrum analysis applying same. The spectrum analyzer adopts a separate design. A radio frequency receiver receives a signal, performs frequency conversion processing and AD conversion on the received signal, and sends the converted digital signal to a host. In such a structure, by a digital optical module, the radio frequency receiver is connected to a corresponding digital optical module on the host through an optical fiber, so as to implement a bidirectional data transmission. The host performs general control of the system as well as signal processing and spectrum analysis. Therefore, a multi-interface design is applied to the host of the spectrum analyzer, so as to support simultaneous access and control for a plurality of radio frequency receivers, thereby conveniently implementing multi-port measurement extension.
US09602221B2	Wireless ultrasonic data transmission for explosive environments A system for data transmission for an explosive environment comprises an ultrasonic transmitter coupled to a Class 1 device disposed inside an explosive risk zone and adapted to generate an electric signal in response to a predetermined condition, the ultrasonic transmitter being configured to generate and transmit an ultrasonic signal in response to receiving the electric signal, an ultrasonic receiver disposed outside the explosive risk zone configured to receive the ultrasonic signal, and an uplink communication device adapted to communicate an alert to a remote operator in response to the ultrasonic receiver receiving the ultrasonic signal.
US09602220B2	Quantum repeater network system The disclosure concerns quantum repeater network system that does not need any matter qubit. According to the quantum repeater network system for performing quantum communication between one transmitter/receiver and the other transmitter/receiver via transmission repeaters and reception repeaters, each of the transmission repeaters prepares quantum systems in an irreducibly entangled state, each of the quantum systems being associated with a reception repeater as a transmission destination, and transmits, to the associated reception repeater, each of the quantum systems in the irreducibly entangled state together with a quantum system entangled with the quantum system.
US09602218B2	Directly modulated laser with dispersion compensation Systems and methods for using a dispersion compensation circuit to directly modulate a laser. Techniques include calibrating a varactor bias point in a dispersion compensation circuit during manufacturing, but positioning the dispersion compensation circuit between a first attenuator and a second attenuator. Each attenuator, capable of reducing power of an input signal, may be adjustable so that the attenuation provided by each attenuator may be adjusted. The ratio of attenuation between attenuators may be adjusted based on either chirp of a laser or fiber length, and a varactor bias point may be adjusted by the other one of the chirp of the laser or fiber length. Thus, both chirp and fiber length may serve as a basis for adjusting attenuation between attenuators having a dispersion compensation circuit positioned between them.
US09602216B2	Reflective light-emitting device for a WDM PON optical access network, the device including a light source with an optical gain medium A reflective light-emitting device is provided for a WDM PON optical access network. The device includes a light source with an optical gain medium. The light-emitting device includes a light source with an optical gain medium, of wavelength that is self-seeding during a go-and-return passage of light between the optical gain medium and an optical reflective component defining the laser cavity. The optical reflective component is made up of an optical amplifier associated reflective optical connection to a polarizing device so that the polarization axis of the reflected light is the same as the polarization axis of the emitted light.
US09602214B2	Signal transmission method and device The present invention provides a signal transmission method and device. The device includes: a transmitting device, configured to transmit a first signal to an opposite terminal; and a receiving device, configured to receive a second signal transmitted by the opposite terminal, where a frequency of the first signal is different from a frequency of the second signal, and the frequency of the first signal and/or the frequency of the second signal are/is in a frequency band of visible light. The present invention resolves a problem in a related technology that poor reliability of uplink and downlink signal transmission is caused when signals of a same frequency are used for uplink and downlink transmission, and provides a beneficial effect of improving reliability of uplink and downlink signal transmission.
US09602211B2	Distributed antenna system A distributed antenna system includes a headend device for generating a downlink transmission signal by combining a plurality of downlink RF signals in different frequency bands, received from a plurality of base stations, and converting the downlink transmission signal into a downlink optical signal, a main remote device for receiving the downlink optical signal from the headend device, converting the downlink optical signal into the downlink transmission signal, and amplifying the plurality of downlink RF signals included in the downlink transmission signal, and a sub-remote device for receiving the downlink transmission signal distributed from the main remote device, and amplifying the plurality of downlink RF signals included in the received downlink transmission signal.
US09602203B2	Methods and systems for identification and communication using free space optical systems including wearable systems Methods and systems are provided for identifying entities and communicating using lightweight and wearable free space optical systems. A variety of optical and electronic elements are used to enable communications and identification in an environment where identification and communication must be accomplished to address a variety of constraints. Such constraints can include frequency congested environments or environments in which communication should be done using non radio frequency (RF) systems. Embodiments include converting data into optical signals that are transmitted using a laser which are received by optical receivers and converted into audio output.
US09602201B2	Optical multiplexing device and method of generating optical OFDM signal An optical multiplexing includes: a monitor configured to detect power of an optical component including a frequency component of a cross point between spectra of a first sub-carrier signal and a second sub-carrier signal; and a controller configured to control a modulation timing of a data symbol of the second sub-carrier signal according to the power detected by the monitor, wherein the second sub-carrier signal is multiplexed to a carrier to be adjacent to the first sub-carrier signal multiplexed to the carrier so as to generate an optical Orthogonal Frequency Divisional Multiplexing (OFDM) signal in which an interference between the first and second sub-carrier signals is suppressed.
US09602198B2	Using fractional fourier transform nonlinear effects in optical fiber link monitoring methods The present invention proposes a method for monitoring the nonlinear effect of an optical fiber link by fractional Fourier transformation, FRFT, by calculating an optimal fractional order of the FRFT of the frequency-domain signal propagating through an optical fiber link, calculating the chromatic dispersion of an optical fiber link based on the optimal fractional order, compensating for chromatic dispersion to the signal, calculating an optimal fractional order of the FRFT for the time-domain signal following the compensation for chromatic dispersion, calculating the time-domain chirp caused by the nonlinear effect of an optical fiber link based on the optimal fractional order, and monitoring the nonlinear effect of an optical fiber link based on the absolute value of the calculated time-domain chirp. The method can be used for quantitatively monitoring the nonlinear effect of an optical fiber link in an optical fiber communication system consisting of different types of optical fibers.
US09602190B2	Low latency global communication through wireless networks Embodiments describe a communication system optimized for low latency and includes one or more high altitude platforms disposed at intervals in data communication with each other forming a communication path and at least two network centers separated from each other by a predetermined distance, where the high altitude platforms receive data signals from the network centers, travel along a communication path between the network centers, forming a data relay and transferring the data signals along the communication path. Additional embodiments may include intervals that are at different altitudes or different distances and/or provide one or more high altitude platforms that comprise at least one of satellites, high altitude balloons, or unmanned aerial vehicles.
US09602189B2	Method and system for estimating a path-length difference of a target signal transmitted by a spacecraft or aircraft A method and system for estimating a path-length difference between two paths followed by a target signal transmitted by a spacecraft or aircraft to a first receiving antenna and a second receiving antenna of a receiving base, respectively. A useful-phase difference is measured between signals that correspond to the target signal received by the first receiving antenna and second receiving antenna. The path-length difference is estimated in accordance with the useful-phase difference measurements. The measurement of the useful-phase difference comprises either correlating the signals received by the first receiving antenna and second receiving antenna, respectively, with a reference target signal, or analyzing the signals received by the first receiving antenna and second receiving antenna, respectively, using an FFT or a PLL.
US09602188B2	Support system A support system (1) for traffic support of ships (20a, 20b, 21a, 21b), having AIS ship reception units for receiving AIS radio signals containing ship traffic data, is characterized in that at least one flight object (2) is provided, comprising at least one AIS flight transmission unit (3), which is designed to transmit AIS radio signals containing ship traffic data inside an AIS transmission range (10) in such a manner that the transmitted AIS radio signals can be received by the ships (20a, 20b, 21a, 21b) located inside the AIS transmission range (10) by means of their respective AIS ship reception units.
US09602187B2	Aircraft flight data delivery and management system with emergency mode An automated aircraft flight data and delivery management system and method operates in a normal state and a demand state. The demand state may be self-initiated or manually-initiated, and may be triggered during situations which include but are not limited to situations when the aircraft is in a potential or confirmed emergency situation. Data transmission increases in intensity when the system is in a demand state.
US09602185B2	Communication terminal, communication control apparatus, communication system, communication control method, and program Provided a communication terminal configured to provide a tethering function controls permission of communication of a different apparatus using the tethering function provided by the communication terminal, based on at least one of attribute information of the different apparatus, a communication destination of the different apparatus, and information on an interface of a network to which the communication terminal is connected, in accordance with a control policy stored in a storage unit in advance.
US09602182B2	Baseband processing apparatus in radio communication system and radio communication A baseband processing apparatus in a radio communication system, a radio communication system, and a baseband processing method. The apparatus includes a first unit and a second unit that implement different baseband processing functions, where the second unit is configured to generate a precoding matrix of a downlink coordinated multipoint transmission and reception (CoMP) user, generate precoding control information according to the precoding matrix, and send the precoding control information to the first unit; and the first unit is configured to receive the precoding control information sent by the second unit, and perform downlink joint baseband processing on downlink CoMP user data in downlink user data according to the precoding control information, so as to generate jointly sent baseband data for radio sending. The technical solutions can reduce transmission bandwidth between baseband processing units and obtain a system capacity gain at the same time.
US09602181B2	Implementing codebook subset restrictions in wireless communication systems In MU-MIMO scenarios, a transmitting node (700) receives feedback on a feedback channel from a receiving node (1200) regarding a channel between the transmitting and receiving nodes (700, 1200). The feedback also includes preferences of the receiving node (1200). However, the feedback may not always be useful. For example, the receiving node (1200) may indicate a preferred rank in the feedback that the transmitting node (700) cannot accommodate. To address such issues, mechanisms for the transmitting node (700) to convey its preferences to the receiving node (1200) are proposed. The receiving node (1200), with such knowledge, can provide more useful feedback information to the transmitting node (700).
US09602179B2	Base station apparatus and transmission method The present disclosure provides a method of generating codebook in a wireless communication system with multiple antenna arrays, as well as a wireless communication system, base station and terminal using the codebook for communication. The method comprises steps of: providing a basic codebook which contains multiple pre-coding matrices; and assigning phase offsets to certain pre-coding matrices in the basic codebook to form a codebook with phase offset. The feedback overhead from a client to a base station side is reduced and a good precision of feedback for multi-antenna array is kept by applying the method of generating codebook and using the generated codebook in the wireless communication system, base station and terminal.
US09602177B2	Method and apparatus for efficient feedback in a wireless communication system supporting multiple antennas A method and apparatus for performing effective feedback in a wireless communication system supporting multiple antennas. A method for transmitting CSI of downlink transmission via uplink in a wireless communication system includes transmitting a joint-coded rank indicator (RI) and a first wideband (WB) precoding matrix indicator (PMI) at a first subframe, and transmitting a wideband channel quality indicator (WB CQI) and a second WB PMI at a second subframe. A user equipment (UE) preferred precoding matrix is indicated by a combination of the first PMI and the second PMI. If the RI is Rank-1 or Rank-2, the first PMI indicates one of subsets each having 8 indexes from among 16 indexes of the first PMI of a precoding codebook.
US09602172B2	User identification and location determination in control applications A system in which a portable electronic device communicates with an external device to determine a location. Upon determining its location, the portable electronic device transmits this information as well as identifying information to a control processor. The control processor controls one or more controllable devices according to the location and identifying information. The portable electronic device may determine the location via NFC tag or via one or more RF beacons transmitting information according to the Bluetooth 4.0 protocol.
US09602169B2	Communication apparatus, control method, and storage medium for transferring power A communication apparatus includes first communication means having a first communication function for wirelessly communicating with a partner apparatus, and second communication means having an electric power supply function for wirelessly supplying electric power to the partner apparatus and a second communication function for wirelessly communicating with the partner apparatus. The second communication function is for transmitting specific data sequence to the partner apparatus in response to reception of specific data from the partner apparatus, and the electric power supply function is for supplying electric power to the partner apparatus in a case of receiving from the partner apparatus, with the first communication means, a signal indicating that the partner apparatus has received the data sequence.
US09602166B2	Configuration method of a multimedia system A configuration method of a multimedia system comprising a first device and at least one adjacent device having a mechanism to communicate with the first device. The first device comprises a mechanism to read/write data from/to an NFC data carrier. The method comprises a set-up phase and an exploitation phase.
US09602163B2	Wireless device detection and communication apparatus and system A method for effecting a near field communication, including the steps of positioning a first device at a close proximity to a second device, wherein the close proximity is suitable for the near field communication; and sending a first effectively carrierless signal from the first device to the second device.
US09602159B2	Communication channel identification in a power line communication network In one embodiment, a device in a network receives a message from a neighboring device that identifies the electrical phase on which the message was sent. Crosstalk is identified between the device and the neighboring device by determining that the message was received on a different electrical phase than the phase on which the message was sent. One or more distinct communication channels between the device and the neighboring device are identified based on the identified crosstalk with each communication channel including or more electrical phases.
US09602158B2	Methods for estimation and interference suppression for signal processing A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel symbol estimates. An interference canceller is configured for cancelling interference from at least one of the plurality of received signals for producing at least one interference-cancelled signal.
US09602153B2	Radio receiving apparatus for receiving frequency-modulated radio signal A radio receiving apparatus includes: a radio receiving circuit that frequency-converts a radio signal frequency-modulated with a baseband signal into an intermediate frequency signal; a frequency component detecting circuit that samples the intermediate frequency signal using an over-sampling frequency that is variable and detects a plurality of frequency components in the intermediate frequency signal; and a control circuit that detects a data rate of the baseband signal that is included in the intermediate frequency signal, detects a signal level of the intermediate frequency signal, and determines and sets the over-sampling frequency for the frequency component detecting circuit in accordance with the data rate of the baseband signal and the signal level of the intermediate frequency signal.
US09602150B1	Wireless device A distortion compensation unit compensates distortion in the amplifier by using a distortion compensation coefficient that is in accordance with a power value of a signal before amplification in the amplifier. An updating unit updates, on the basis of the signal before amplification in the amplifier and a signal after amplification in the amplifier, the distortion compensation coefficient. An extracting unit extracts, at a predetermined number of measurement periods, when the power value of the signal before amplification in the amplifier is equal to or greater than a threshold, the distortion compensation coefficient that is in accordance with the power value. A first calculating unit calculates, by using an average value of the extracted distortion compensation coefficients, an amount of variation in the distortion compensation coefficient. A determination unit determines, on the basis of the calculated amount of variation in the distortion compensation coefficient, whether the amplifier is degraded.
US09602147B2	Switch module Impedance mismatching by a matching circuit provided on a signal line which connects a first common terminal and a second common terminal is eliminated so as to significantly reduce insertion loss of a switch module. Therefore, it is possible to provide a switch module which has a simple configuration without the need for connection of a matching circuit to antenna terminals to which antennas are respectively connected, and is able to selectively connect any one of the antennas and any one of communication systems.
US09602146B2	RF front end architecture RF front end circuitry includes mid/high-band switching circuitry and a carrier-aggregation diplexer. The mid/high-band switching circuitry is configured to receive and selectively route mid-band and high-band signals between a mid/high-band output port and a number of mid/high-band transceiver ports. The carrier-aggregation diplexer is coupled to a first one of the mid/high-band transceiver ports. Further, the carrier-aggregation diplexer is configured to pass mid-band signals between a mid-band diplexer port and the first one of the mid/high-band transceiver ports while attenuating other signals, and pass high-band signals between a high-band diplexer port and the first one of the mid/high-band transceiver ports while attenuating other signals.
US09602144B2	Method and apparatus for processing multiple wireless communication services The present invention is related to a method and apparatus for processing multiple wireless communication services in a receiver. A receiver receives more than one wireless communication service simultaneously via a wireless interface. Each service is transmitted via a different carrier frequency band. The multiple received carrier signals are down-converted to an intermediate frequency (IF) band using a mixer and a local oscillator (LO). The LO frequencies are set such that the down-converted IF bands of the multiple services are fallen into a single IF band.
US09602142B2	Transmission apparatus including encoder, reception apparatus including decoder, and associated methods An encoder and decoder using LDPC-CC which avoid lowering the transmission efficiency of information while not deteriorating error correction performance, even at termination; and an encoding method of the same. A termination sequence length determining unit determines the sequence length of a termination sequence transmitted added to the end of an information sequence, according to the information length (information size) and encoding rate of the information sequence. A parity calculation unit carries out LDPC-CC coding on the information sequence and the known-information sequence necessary for generating a termination sequence of the determined termination sequence length, and calculates a parity sequence.
US09602140B1	Data recovery using frame matching and erasure windowing The disclosure is related to systems and methods of data recovery using frame matching and erasure windowing. Aspects involve using frame matching in conjunction with erasure windowing to overcome data corruption in a set of data to allow recovery of the set of data. When a synchronization mark indicating the position of a set of data in a superset of data is corrupted, frame matching in conjunction with erasure windowing are used to enable recovery of the set of data by applying one or more frame windows and one or more erasure windows to data including the set of data to recover the set of data.
US09602133B1	System and method for boost floor mitigation A method for boost floor mitigation during a decoding operation performed by a decoder is disclosed herein. The method includes: monitoring for a floor error condition while performing the decoding operation; if a floor error condition has been detected, then: clearing a feedback delay memory in the decoder; downscaling main memory values in the decoder; applying a gain in low-rank columns; and continuing to perform the decoding operation.
US09602130B2	System and method for matching a regular expression or combination of characters A system and method for comparing a character from a search space simultaneously to each of a set of search characters. The set of search characters may correspond to a regular expression. In one embodiment, the search space character is encoded to a short binary presentation (e.g., to an 8-bit representation), which is then converted to a long binary representation one bit of which is set, at a first position in the long binary representation corresponding to the value of the short representation. Each character of the set of search characters is similarly encoded and converted to a respective long binary representation. If the bit in one of the long binary representations corresponding to the set of search characters is set, it indicates that the search character matches the corresponding character of the set of search characters.
US09602126B2	Sigma-delta analog-to-digital converter The present invention is related to a sigma-delta analog-to-digital converter (ADC). It further relates to a method for designing and manufacturing a sigma-delta ADC, and to a digital control loop comprising the same. According to the present invention, part of the filtering function required for noise-shaping is implemented in the feedback path. By suitably distributing the poles over the forward and feedback paths, stable operation can be achieved while offering low latency.
US09602124B2	A/D conversion device having level shifter circuit An A/D conversion device includes: a level shifter circuit configured to level-shift an analog voltage of an input voltage signal to generate a conversion signal; an A/D converter configured to A/D-convert a voltage of the conversion signal supplied from the level shifter circuit. The level shifter circuit subtracts an instantaneous voltage value of the input voltage signal from a reference voltage so as to output a signal value as the conversion signal.
US09602119B1	Gain calibration by applying a portion of an input voltage to voltage associated with a capacitor array Various aspects facilitate gain adjustment associated with an analog to digital converter. A capacitor array comprises a plurality binary-weighted capacitors and generates an output voltage received by a comparator based on an input voltage and a reference voltage. A gain calibration component receives the input voltage and applies a modified input voltage that corresponds to a portion of the input voltage to the output voltage generated by the capacitor array component.
US09602116B1	Interleaved successive approximation register analog to digital converter In an example, the present invention provides an analog to digital converter device for a high speed data transmission from 1 GS-s to 100 GS-s, although there can be other variations. In an example, the device has an input receiver device coupled to a transimpedance amplifier. In an example, the transimpedance amplifier is coupled to an input stream of data at 10 GHz to 100 GHz, or other variations.
US09602115B1	Method and apparatus for multi-rate clock generation A method and device for generating a multi-rate clock signal using a ring voltage-controlled oscillator based phase-locked loop is provided. The device includes a delay line having a length extending beyond a predetermined length required for operation of the phase-locked loop. The device further includes a tap tuning logic circuit coupled to the delay line. The delay line receives an input signal and a tuning voltage from the phase frequency detector, charge pump and loop filter circuits and generates a plurality of tapped output signals. The plurality of tapped output signals is received by the integrated digital multi-rate clock generator configured to create a plurality of clock signals.
US09602111B1	Delay locked loop (DLL) locked to a programmable phase An asynchronous digital logic is used to provide a pulse. A pulse train is filtered to determine an analog measurement based at least in part on the duty cycle of the pulse. The analog measurement is compared with a tunable reference associated with a programmable locked delay for the DLL. A digital code is sequenced based at least in part on the comparison. A digitally controlled delay line is programmed based at least in part on the digital code.
US09602107B2	Reset selection cell to mitigate initialization time A circuit includes a state capture device to capture a logic state of a reset selection cell in response to a logic state input. A cell reset node defines a reset state of the reset selection cell. A selection device passes the captured logic state from the state capture device or the reset state from the cell reset node to an output of the reset selection cell based on a state of a control input to the selection device.
US09602102B2	Magnetic logic device, magnetic logic circuit, and magnetic memory One embodiment provides a magnetic logic device including: a first conductive thin wire; a second conductive thin wire; and a third conductive thin wire that electrically connects the first conductive thin wire and the second conductive thin wire. The first to third conductive thin wires commonly includes: a first non-magnetic metal layer; a second non-magnetic metal layer; and a magnetic metal layer sandwiched between the first non-magnetic metal layer and the second non-magnetic metal layer.
US09602099B2	Adaptive duo-gate MOSFET An adaptive duo-gate MOSFET includes a trench MOSFET and an adaptive element. The trench MOSFET includes a source, a drain, a first gate, a second gate, and a dielectric layer between the first and second gates. Herein, the first gate may generate charge-coupling in blocking operation, and the second gate may form channel in the trench MOSFET when in conduction operation. The adaptive element is electrically coupled to the first gate, the second gate, and the source respectively. When a potential difference between the second gate and the source is larger than a predetermined value, the first gate and the source are electrically disconnected and then the first gate and the second gate are electrically connected. After a predetermined time, the first gate and the second gate are electrically disconnected and then the first gate and the source are electrically connected.
US09602098B2	RF switch with bypass topology An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in a bypass mode. Embodiments of the invention allow for both a single switch in the series input path while still having the ability to isolate the bypass path from an input matching network. In both modes, the circuit simultaneously exhibits low input insertion loss (and thus a low noise factor) and high bypass mode isolation.
US09602097B2	System and method having a first and a second operating mode for driving an electronic switch An electronic switch is connected in series with a load dependent on an input signal. The electronic switch is operated in a first operation mode for a first time period after a signal level of the input signal has changed from an off-level to an on-level. The first operation mode includes driving the electronic switch dependent on a voltage across the load and dependent on a temperature of the electronic switch. The electronic switch is operated in a second operation mode after the first time period. The second operation mode includes driving the electronic switch dependent on the temperature according to a hysteresis curve.
US09602095B2	Multiplexer circuit, computer-readable recording medium having stored therein program for designing multiplexer circuit, and apparatus for designing multiplexer circuit In a multiplexer circuit which loads N data segments (N is an integer of N
US09602094B2	Decoding circuit and method of decoding signal A decoding circuit may include a section information generation unit suitable for generating section information corresponding to a section in which an input signal has a first value, a period information generation unit suitable for generating period information corresponding to a period of the input signal, a reference information generation unit suitable for generating reference information by dividing a value of the period information by a given value, and a comparison unit suitable for determining a logic value of the input signal by comparing the section information with the reference information.
US09602091B1	Low phase shift, high frequency attenuator A wideband RF attenuator circuit that has a reduced impact on the phase of an applied signal when switched between an attenuation state and a non-attenuating reference or bypass state. A low phase shift attenuation at high RF frequencies can be achieved by utilizing a switched signal path attenuator topology with multiple distributed transmission line elements per signal path to provide broadband operation, distribute parasitic influences, and improve isolation to achieve higher attenuation at higher frequencies while still maintaining low phase shift operational characteristics. In an alternative embodiment, extension to even higher frequencies can be achieved by utilizing a quarter-wave transmission line element at the signal interfaces of each signal path, thereby improving insertion loss and power handling.
US09602087B2	Linear transformer driver for pulse generation with fifth harmonic A linear transformer driver includes at least one ferrite ring positioned to accept a load. The linear transformer driver also includes a first, second, and third power delivery module. The first power delivery module sends a first energy in the form of a first pulse to the load. The second power delivery module sends a second energy in the form of a second pulse to the load. The third power delivery module sends a third energy in the form of a third pulse to the load. The linear transformer driver is configured to form a flat-top pulse by the superposition of the first, second, and third pulses. The first, second, and third pulses have different frequencies.
US09602081B2	Method and apparatus for utilizing modulation based audio correlation technique for maintaining dynamic FM station list in single tuner variant and assisting alternate frequency switching methodology in single tuner and dual tuner variants A method of operating a single-tuner radio includes tuning into a first frequency. A pause in a first signal associated with the first frequency is detected. Tuning is switched from the first frequency to a second frequency during the pause. Fieldstrength, multipath, adjacent channel energy, frequency offset and FM modulation for the second frequency are measured. Tuning is switched from the second frequency to the first frequency. Tuning is switched from the first frequency to the second frequency dependent upon the measuring step.
US09602077B2	Surface acoustic wave device having selectable electrode elements Described embodiments include a surface acoustic wave device, method, and apparatus. The device includes a piezoelectric substrate and a configurable electrode assembly. The configurable electrode assembly includes a plurality of spaced-apart elongated electrode elements electromechanically coupled with the piezoelectric substrate. The assembly includes a first signal bus crossing each of the plurality of electrode elements and electrically isolated therefrom. The assembly includes a first matrix of addressable switches. Each addressable switch of the first matrix configured to electrically couple a respective electrode element of the plurality of electrode elements with the first signal bus. The assembly includes a second signal bus crossing each of the plurality of electrode elements and electrically isolated therefrom. The assembly includes a second matrix of addressable switches. Each addressable switch of the second matrix configured to electrically couple a respective electrode element of the plurality of electrode elements with the second signal bus.
US09602076B1	Resonators with balancing capacitor Embodiments provide a solidly-mounted bulk acoustic wave (BAW) resonator and method of making same. In embodiments, the BAW resonator may include a first resonator and a second resonator that are coupled with one another via a top electrode layer. A capacitive element may be included in the BAW resonator in parallel with the first resonator. Other embodiments may be described and claimed.
US09602072B1	Compact impedance tuner A new slide screw impedance tuner structure uses a circular slabline, eccentrically rotating disc probes and a rotating carriage allowing reducing the linear size of the tuner by a factor of 3. The slabline lies flat on the bench table surface and the disc probe rotates at the end of a rotating arm, which acts as a mobile carriage, forming a planetary configuration. The rotation of the arm controls the phase of GAMMA and the rotation of the disc-probe controls its amplitude.
US09602071B2	Filter with electrostatic discharge protection An electronic device is disclosed that includes a power distribution network, a first resonant network, a second resonant network, and a third resonant network. The power distribution network is configured transmit a voltage. The first resonant network is coupled to a first terminal of the power distribution network, and is configured to provide a first electrostatic discharge (ESD) protection to the power distribution network. The second resonant network is coupled to a second terminal of the power distribution network, and is configured to provide a second ESD protection to the power distribution network. The third resonant network coupled between the first terminal and the second terminal of the power distribution network, and the first resonant network, the second resonant network, and the third resonant network are configured to filter an AC signal from the power distribution network.
US09602069B2	Programmable impedance network in an amplifier The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
US09602065B2	Semiconductor device In a semiconductor device, received signals of different frequency bands are input selectively to low noise amplifiers. A plurality of primary inductors are coupled between differential output nodes of the respective low noise amplifiers. A secondary inductor is provided commonly for the primary inductors, and magnetically coupled to the primary inductors. A demodulator converts a received signal transmitted from one of the primary inductors to the secondary inductor by electromagnetic induction, into a signal of a low frequency.
US09602063B2	Variable impedance match and variable harmonic terminations for different modes and frequency bands An amplifier with switchable and tunable harmonic terminations and a variable impedance matching network is presented. The amplifier can adapt to different modes and different frequency bands of operation by appropriate switching and/or tuning of the harmonic terminations and/or the variable impedance matching network.
US09602061B2	Distributed amplifier A distributed amplifier includes a plurality of transistors, a first line connecting gate electrodes of the transistors to each other, and a second line connecting drain electrodes of the transistors to each other, wherein the first line and the second line are electromagnetically coupled to each other at a position situated between immediately adjacent transistors among the plurality of transistors.
US09602059B2	Amplifier topology for envelope tracking An amplifier has an input port for receiving an input signal and an envelope port for receiving an envelope signal indicative of an envelope of the input signal, and an output port for delivering an amplified signal. The amplifier has a first transistor and a second transistor. A first biasing circuit is coupled to the envelope port and is arranged to generate a first bias voltage dependent on the envelope signal. A summing stage is coupled to the input port for receiving the input signal, to the first biasing circuit for receiving the first bias voltage, and to the gate of the first transistor. A second biasing circuit is coupled between the envelope port and the gate of the second transistor, and is arranged to generate a second bias voltage dependent on the envelope signal.
US09602056B2	Amplifier with base current reuse An RF amplifier module that has a plurality of amplifiers wherein at least one of the amplifiers is powered via an envelope tracking module. The biasing input of at least one of the amplifiers is provided to the first amplifier to power the first amplifier to reduce power consumption. The first amplifier may also be powered via fixed biasing to provide greater stability of the module.
US09602054B2	System and method for reconfigurable phase shifter and mixer An analog circuit for generating a periodic signal at a selected phase, including one or more phase interpolators that receive orthogonal differential RF signals and a pair of differential gain signals. The differential in-phase RF signal is applied at respective gates of tail transistors, and a first differential gain signal is applied across gates of a transistor pair coupled to each of the tail transistors. The quadrature-phase RF signal and a second differential gain signal is similarly applied to another quad of transistors (i.e., pair of transistor pairs) and associated tail transistors. A load connected to the one transistor in each pair receives the output signal, at a phase corresponding to a ratio of the first and second gain signals. The gain signals may be DC or AC, which allows configuration of the circuit as a phase shifter or an upconversion mixer, and the load may be presented by a transform in which the phase also depends on the relative coupling from the in-phase and quadrature-phase sides of the phase interpolator.
US09602049B2	Operating point control circuit device for series-connected photovoltaic cells or other electric sources In a circuit device controlling an operating point of each of two or more series-connected photovoltaic cells or other power supply cells in a module, the output voltage of the module can be boosted without reducing the generated electric power. The operating point control circuit device includes capacitors connected in parallel to the respective series-connected cells, switching elements connected in parallel to the respective series-connected cells through an inductor, an additional capacitor connected in series to the capacitor row, and an additional switching element connected in series to the switching element row. The switching elements are controlled to shut off electrical conduction between the corresponding terminals connected thereto in the same predetermined cycle and in mutually different periods so as to always establish a condition that one switching element is in the non-conductive state and the others are is in the conductive state.
US09602047B2	Self-tracking solar concentrator device A device for self-tracking a light source, including a focusing optical device configured to focus incoming light to a focal spot, an adaptive device configured to reflect the light of the focal spot and arranged to provide for a phase change at an area of the focal spot of the incoming light to generate a reflected light, and a light guide located between the focusing optical device and the adaptive device, the light guide configured to capture the reflected light of the adaptive device.
US09602046B2	Photovoltaic device The present invention is premised upon an improved photovoltaic device (“PV device”), more particularly to an improved photovoltaic device with a multilayered photovoltaic cell assembly and a body portion joined at an interface region and including an intermediate layer, at least one interconnecting structural member, relieving feature, unique component geometry, or any combination thereof.
US09602045B2	System, apparatus, and method for monitoring a subsea flow device A system, apparatus, and method are provided for monitoring a subsea flow device such as a subsea flowline. The apparatus generally includes a thermoelectric device that is adapted to generate electric power from a thermal potential between the subsea flow device and the surrounding seawater. A sensor that is powered by the thermoelectric device is adapted to monitor one or more characteristics of the flow device, such as temperature or strain, and provide a communication that is indicative of the characteristic. The communication may be a radiation output or an acoustic output.
US09602044B2	Travelling wave motor pre-driver using high resolution PWM generators A motor driver combination for controlling a travelling wave motor includes a pre-driver including a microcontroller unit (MCU) chip including a plurality of high-resolution pulse width modulation (HRPWM) generators providing a frequency resolution better than ten Hz. A digital bus is for transferring digital words received from a controller in a servo and velocity control block to the HRPWM generators, where the digital words provide travelling wave motor operating performance information from the motor during its operation. A clock oscillator providing an accuracy of at least eighty (80) parts per million (ppm) is coupled to or provided by the MCU chip for each of the high-resolution PWM generators. A motor driver includes a plurality of power drivers for providing phased outputs for driving the travelling wave motor including a plurality of inputs coupled to outputs of the plurality of HRPWM generators. The travelling wave motor can be an ultrasonic motor.
US09602043B2	Magnet management in electric machines A magnet management method of controlling a ferrite-type permanent magnet electrical machine includes receiving and/or estimating the temperature permanent magnets; determining if that temperature is below a predetermined temperature; and if so, then: selectively heating the magnets in order to prevent demagnetization and/or derating the machine. A similar method provides for controlling magnetization level by analyzing flux or magnetization level. Controllers that employ various methods are disclosed. The present invention has been described in terms of specific embodiment(s), and it is recognized that equivalents, alternatives, and modifications, aside from those expressly stated, are possible and within the scope of the appending claims.
US09602042B2	Method of controlling rotational speed of impeller A load current value I of a motor rotationally driving an impeller is read out when the impeller is rotated at a predetermined set rotational speed X0, and the rotational speed of the impeller is increased so that the load current value I becomes equal to or larger than a threshold value I0 when it is determined that the load current value I is smaller than the predetermined threshold value I0.
US09602036B2	Motor speed curve control circuit and moter thereof The present disclosure illustrates a motor speed curve control circuit. The motor speed curve control circuit is configured for adjusting a speed of a motor according to a motor speed curve. The motor speed curve control circuit comprises a divider resistor module, an analog-to-digital converter and an arithmetic unit. The resistor module is configured for generating at least one turning-point voltage. The turning-point voltage is used to adjust a slope of the motor speed curve. The analog-to-digital converter converts the turning-point voltage to digital form. The arithmetic unit sets a speed associated with the turning-point voltage corresponding to a first preset duty cycle in the motor speed curve, such that the motor speed curve becomes linear. The arithmetic unit generates a second pulse width modulation signal according to the adjusted motor speed curve and a first pulse width modulation signal to drive the motor.
US09602029B2	Method for operating and apparatus for activating a rotating, brushless electrical machine A method for operating a brushless, rotating electrical machine, including at least three phase windings, each of which has a first phase winding terminal and a second phase winding terminal. The phase windings are connected to each other, in particular the particular second phase winding terminals are connected to a shared star point, and phase-width-modulated voltage signals being applied separately to each individual phase winding, and at least one selected phase winding being at least temporarily connected to a constant electrical potential. To minimize switching operations and to reduce the alternating current component of the current source, the pulses of the pulse-width-modulated signals applied to the remaining phase windings are at least temporarily phase-shifted with respect to each other during the period in which the selected phase winding is connected to a constant electrical potential.
US09602025B2	Multiphase power converter circuit and method A multiphase power converter circuit includes at least two single phase power converter circuits. Each single phase power converter circuit includes at least one converter series circuit with a number of converter units. The converter series circuit is configured to output a series circuit output current. A synchronization circuit is configured to generate at least one synchronization signal. At least one of the converter units is configured to generate an output current such that at least one of a frequency and a phase of the output current is dependent on the synchronization signal.
US09602022B2	Electrical device for use with a multiway switch system Electrical devices, methods of operating an electrical device for use with a multiway switch system, and methods for connecting an electrical device with a load device and a multiway switch system for controlling the load device are described. In one embodiment, an electrical device for use with a multiway switch system includes an alternating current (AC) power interface configured to connect to at least one of a live wire and a neutral wire of an AC power supply, a load regulator module configured to regulate a load device that is connected to the neutral wire of the AC power supply, an output power interface configured to connect to the multiway switch system and to output a voltage to a switch of the multiway switch system, and a microcontroller module configured to control the load regulator module in response to a switching of the multiway switch system.
US09602020B2	Power conversion device A power conversion device includes a half bridge type inverter circuit that includes semiconductor elements, and a DC capacitor and that is connected to a positive side bus of the AC power supply, a smoothing capacitor, a semiconductor element that is connected between the semiconductor element and a positive side of the smoothing capacitor, and a semiconductor element that is connected between the semiconductor element and a negative side of the smoothing capacitor, in which turning-on and turning-off of the semiconductor element are controlled so that a DC voltage of the DC capacitor tracks a target voltage, and turning-on and turning-off of the semiconductor elements are controlled so that a DC voltage of the smoothing capacitor tracks a target voltage and thus an input power factor from the AC power supply is adjusted.
US09602015B2	Communication method and apparatus using modulation of post-conduction oscillation frequency in switching converters A communication method and apparatus that uses modulation of post-conduction oscillation frequency in switching converters is provided. The apparatus may include a converter having a magnetic element having a primary winding and a secondary winding, a first switch, a control circuit configured to repeatedly activate the first switch to couple an input voltage source to the primary winding to store electrical energy in the magnetic element, and a diode coupled to the secondary winding, said diode configured to couple the secondary winding to a load to deliver the electrical energy stored in the magnetic element, and a communication apparatus having a second switch, a first modulator capacitor coupled to the secondary winding, a first transmitter configured to activate the second switch in accordance with a first input signal, and a first receiver configured to detect a post-conduction oscillation frequency of a voltage signal at the primary or secondary windings.
US09602013B2	Controller for a switch mode power converter A controller for controlling a power supply includes a feedback signal generator to generate a feedback signal representative of an output current in response to an output sense signal. A state selector circuit receives the feedback signal and outputs a digital state signal to set an operational state of a switch of the power supply. The state selector circuit adjusts the digital state signal in response to feedback information at an end of a feedback period. A driver circuit receives the digital state signal and generates a drive signal in response to the digital state signal. The drive signal drives switching of the switch in accordance with the operational state of the switch.
US09602012B2	Apparatus and method for controlling switching power supply An output voltage error detection unit outputs an auxiliary winding voltage generated across an auxiliary winding having the same number of turns as a secondary winding a certain period after a secondary conduction period starts. A correction amount calculation unit calculates a secondary voltage drop caused by a secondary current flowing in the conduction period based on a primary current flowing when the conduction period starts and outputs a calculation result as a correction amount. A reference voltage generation unit generates a reference voltage by adding the correction amount to the output voltage. A control unit generates a feedback signal to minimize the error between the auxiliary winding voltage obtained after a certain delay period and the reference voltage. A PWM signal generation unit controls a PWM signal based on the feedback signal, adjusts switching of the switching element, and maintains the output voltage at a constant level.
US09602009B1	Low voltage, closed loop controlled energy storage circuit An energy storage circuit for use with a power converter includes a base capacitor coupled between an input bus and a ground potential, and an adjust capacitor. A switching device is coupled in series with the adjust capacitor between the input bus and the ground potential. A voltage regulator coupled between a control terminal of the switching device and ground. The voltage regulator has an input coupled to the second internal node, wherein when the power switch is turned on a signal at the second internal node is representative of a fluctuating input voltage. The voltage regulator is activated when the fluctuating input voltage is in a crest region, thereby turning the switching device off and disengaging the adjust capacitor. The voltage regulator is deactivated when the fluctuating input voltage is in a valley region, thereby turning the switching device on and engaging the adjust capacitor.
US09602004B2	Efficient control circuit for buck-boost converters and control method thereof A controller used in a buck-boost converter includes a logic control circuit, a pulse width increasing circuit, a pulse width decreasing circuit, a first driving circuit and a second driving circuit. The pulse width increasing circuit generates a sum control signal based on a logic control signal generated by the logic control circuit. The pulse width increasing circuit increases the pulse width of the logic control signal by a first value to generate the pulse width of the sum control signal. The pulse width decreasing circuit generates a difference control signal based on the logic control signal. The pulse width decreasing circuit decreases the pulse width of the logic control signal by a second value to generate the pulse width of the difference control signal. The first and second driving circuit respectively generates driving signals based on the sum control signal and the difference control signal.
US09602003B2	Voltage regulator, semiconductor device, and voltage generation method for voltage regulator A voltage regulator includes: a drive voltage generating part for generating a drive voltage and then apply the drive voltage to a drive line; an output transistor for outputting a voltage corresponding to a voltage value of the drive line as the internal source voltage; and a compulsory drive circuit including a capacitor element configured to receive the source voltage at one end, a first switching element for receiving a ground voltage and applying the ground voltage to the other end of the capacitor element by being set in an ON state over a period in which the selected operational mode is the standby mode, and a second switching element that connects the other end of the capacitor element to the drive line only for a predetermined period in an ON state when the operational mode transitions from the standby mode to the active mode.
US09602002B2	Switching power supply device A switching power supply device includes a slope compensation circuit configured to start slope compensation for suppressing subharmonic oscillation in accordance with a timing signal from an oscillation circuit. The oscillation circuit is provided with a first circuit, which generates a signal of a fundamental oscillation frequency, and a second circuit, which applies logic processing to the signal of the fundamental oscillation frequency to form the timing signal. Thus, it is possible to provide a switching power supply device in which a variation in a start timing of slope compensation can be suppressed.
US09601999B2	Dynamic switch scaling for switched-mode power converters Techniques for optimizing the trade-off between minimizing switching losses and minimizing conduction losses in a buck converter. In an aspect, each of a high-side switch and a low-side switch may be implemented as a plurality of parallel-coupled transistors, each transistor having an independently controllable gate voltage, allowing adjustment of the effective transistor size. In response to the target voltage of the buck converter corresponding to a relatively high voltage range, more high-side switch transistors and fewer low-side switch transistors may be selected. Similarly, in response to the target voltage corresponding to a relatively low voltage range, more low-side switch transistors and fewer high-side switch transistors may be selected. In an aspect, the techniques may be applied during a pulse-frequency modulation mode.
US09601998B2	Hybrid regulator including a buck converter and a switched capacitor converter The present disclosure includes a feedback system that can control hybrid regulator topologies that have multiple converters or regulators connected in series. The hybrid regulator can include at least two regulators: a switched inductor regulator and a switched-capacitor regulator. The disclosed embodiments of the feedback system can simplify feedback design for the hybrid regulator that can include multiple converter stages. These disclosed embodiments can control the feedback to improve the efficiency of a hybrid regulator.
US09601993B2	Boosting circuit of charge pump type and boosting method A boosting circuit of charge pump type includes: charging portion for applying an input voltage to a first capacitor; double boosting portion for applying the input voltage to a second capacitor and applying a sum of the input voltage and a voltage across the first capacitor to an output capacitor in a first predetermined period after start of a boosting operation; and triple boosting portion for repeating in order, after end of the first predetermined period, a step of applying the sum of the input voltage and the voltage across the first capacitor to the second capacitor and a step of applying a sum of the voltage across the first capacitor and a voltage across the second capacitor to the output capacitor.
US09601990B2	High efficiency PFC power converter A power factor correction (PFC) power converter is disclosed that converts AC input power to DC output power. A single stage of the PFC power converter performs both the DC-DC power conversion and the power factor correction for the power converter. The disclosed PFC power converters are efficient in energy conversion and have a power factor of 0.9-1.0. Further, the disclosed PFC power converters can be implemented in both low and high power applications above 75 W.
US09601989B2	Intelligent pulse control circuit The instant disclosure provides an intelligent pulse control circuit used for a power supply. The intelligent pulse control circuit comprises a control unit, a buffer unit, a comparing unit and a switch unit. The buffer receives a loading signal. The comparing unit is coupled to the buffer unit, receives the loading signal generated according to the current of the output loading, and compares the loading signal and the feedback signal to generate a control signal. The switch unit is controlled by the control signal of the comparing unit to provide a turn-off signal. When the output loading is light load, the switch unit controls the control unit to disable the PFC stage and the PWM stage according to the turn-off signal. Accordingly, the intelligent pulse control circuit can reduce the power consumption when the output loading is light load.
US09601981B2	Linear actuator A linear actuator that is configured to be extended/contracted by relatively displacing a first tube and a second tube in an axial direction, includes a rod that is provided inside the first tube, a plurality of permanent magnets that are held in the rod so as to be arranged in the axial direction; a stopper that is provided on a tip-end portion of the rod, a coil that is provided inside the second tube so as to face the permanent magnets, and a stopper receiving portion that is provided on the second tube so as to face the stopper, wherein the relative displacement between the first tube and the second tube in the extension direction is restricted by bringing an extension-direction-side end surface of the stopper into contact with the stopper receiving portion at a fully extended position.
US09601976B2	Method for injection molding rotor magnets A method and assembly for forming a rotor include forming a rotor core having a plurality of voids and placing the formed rotor core into a die cavity. The method includes moving a plurality of support shoes to define an outer diameter of the die cavity, and injecting at least one of the plurality of voids with a magnetic slurry. At least one permanent magnet is formed from the magnetic slurry by applying pressure to the rotor core and the magnetic slurry within the die cavity and by applying a magnetic field to align the magnetic slurry. After forming the at least one permanent magnet within the rotor core, the plurality of support shoes are retracted and the rotor core removed with the at least one permanent magnet formed therein.
US09601973B2	Process for interconnection of electronic power modules of a rotary electrical machine, and assembly of interconnected power modules obtained by means of this process A method for interconnecting electronic power modules of a polyphase rotary electric machine. The power modules are disposed in open cavities of a heat sink and comprise substrates on which are provided MOSFETs of a synchronous rectifier bridge and integrated control circuits. The method comprises the production of: a planar connector (6) including at least one layer of conductive traces (64); a plurality of interconnection elements (512) arranged in multiple geometric formations and ultrasonically welded or brazed (S2) directly to the substrates (51) and/or the MOSFETs; and openings (65) in the planar connector (6) allowing the free passage of the upper ends (5120) of the connection elements (512) and a mechanical contact with the conductive traces (64). The electrical connections are obtained by means of laser (8) transmission welding (S1) or electric resistance welding.
US09601968B2	Anti-tilt electromagnetic motor and lens device using the same The disclosure provides an anti-tilt electromagnetic motor, including a flame, a support base, a contact assembly, a drive assembly, and an elastic assembly. The support base is arranged movably relative to the frame along an axis. The contact assembly is disposed between the frame and the support base and directly contacts the frame and the support base. The drive assembly is configured to drive the support base to move. The elastic assembly is configured to provide a pre-loading force so as to enable the contact assembly to be compressed by the frame and the support base simultaneously.
US09601965B2	Systems and methods for isolating a conduit enclosure for an explosion proof motor An enclosure system for isolating a conduit enclosure for an explosion proof motor is provided. The enclosure system includes a stator enclosure defining a first enclosure opening. The enclosure system also includes a conduit enclosure coupled to the stator enclosure. The conduit enclosure comprises at least one side wall, a rear wall coupled to the side wall, and an interior cavity. The rear wall defines a first entry port having a first volume. The enclosure system further includes at least one electrical lead. The at least one electrical lead extends through the first enclosure opening, through the first entry port, and into the interior cavity. The at least one electrical lead occupies a portion of the first volume and leaves a remaining volume. The enclosure system also includes sealing compound. The sealing compound is coupled with the first entry port such that substantially all of the remaining volume is occupied.
US09601964B2	In-line flow mixer A flow-conditioning system includes a pump, process tubing coupling the pump to a source of multiple component process fluid, and an in-line flow-mixing device positioned in the process tubing upstream of the pump. A system includes a well disposed below a body of water and providing a source of multiple component fluid, a pump disposed in and exposed to the water, process tubing coupling the pump to the well, and an in-line flow-mixing device positioned in the process tubing upstream of the pump.
US09601963B2	Motor waterproof structure A motor waterproof structure includes a stator assembly, a casing and a cover body. The casing has a receiving space formed with an open side. A circuit board is disposed in the receiving space. The cover body is disposed on the open side of the receiving space to cover the circuit board. The motor waterproof structure serves to effectively protect the circuit board from being short-circuited and burned out in a humid environment.
US09601960B2	Rotating electrical machine with biased bobbin An electrical machine includes a back-yoke engagement portion including a convex portion for a back yoke portion formed on an outer-diameter surface of a pair of back yoke-side coil retaining pieces and a shoe engagement portion including a convex portion for a shoe portion. By the convex portion for the back yoke portion and the convex portion for the shoe portion, the back yoke-side coil retaining pieces and shoe-side coil retaining pieces are biased toward a stator core.
US09601958B2	Stator portion and motor A stator portion includes a stator and a bus bar member. The stator includes three coil groups, each coil group includes two or more coils defined by a single conducting wire including a jumper wire. The bus bar member includes three first bus bars to which end portions on one side of the conducting wires of the three coil groups are connected, each of which includes an external connection terminal, a second bus bar defining a neutral point to which end portions on the other side of the conducting wires are connected, and a resin holder which retains the three first bus bars and the second bus bar. The three first bus bars and the second bus bar overlap only in a radial direction centered on the central axis or an axial direction, and the maximum number of bus bars which overlap is 2.
US09601957B2	Compact multiphase wave winding of a high specific torque electric machine The invention is the compact multiphase wave winding of a high specific torque electric machineThe invention is the compact multiphase wave winding (6) of the electric machine. Winding (6) is filling the slots (5) of the stator ferromagnetic core (3) and comprise one or multiple layers (40). Winding (6) fills the slots (5). Winding comprise N or a multiple on N conductors (8), where N represents the number of winding phases. Conductor (8) comprises or is assembled by parallel straight segments (10) and winding overhangs (11). Between the two straight segments (10) of one conductor (8) there are N teeth (4) and N−1 slots (5) or N+1 teeth (4) and N slots (5). Straight segments are connected by winding overhangs which shape in tangential axial plane differs for less than one sixth of magnetic period (7) from ellipse shape with one axis equal to half of magnetic period (7) and other axis length between half and three quarters of magnetic period (7) length.
US09601955B2	Rotor comprising pole shoes with cooling channels The present invention relates to a rotor for a rotary electric machine, extending along a longitudinal axis, including: projecting poles having pole shoes, and at least one internal cooling channel extending axially along at least one pole shoe.
US09601954B2	Rotor of an electric machine, and electric machine A rotor of an electric machine includes a rotor lamination stack connected to a rotor shaft for conjoint rotation therewith. The rotor lamination stack extends from a first axial face of the rotor lamination stack to a second axial face when viewed in the direction of an axis of rotation of the rotor lamination stack. The rotor lamination stack has bores distributed around the axis of rotation and extending from the first axial face to the second axial face when viewed in the direction of the axis of rotation. A tie rod which protrudes from the axial faces when viewed in the direction of the axis of rotation is inserted into each bore. Fastening elements are attached to the tied rods at both axial faces so that the rotor laminations of the rotor lamination stack are pressed together. The tie rods are cast in the bores by a casting material.
US09601952B2	Magnet embedded rotor and method of manufacturing the magnet embedded rotor A magnet embedded rotor configured to provide an improved magnetization ratio of the field permanent magnets is provided. The magnet embedded rotor includes a first annular core in which first permanent magnets are embedded, and a second annular core in which second permanent magnets, which are independent from the first permanent magnets, are embedded. The magnet embedded rotor has a structure in which the second annular core is fitted onto the outer periphery of the first annular core. The first permanent magnets and the second permanent magnets constitute field permanent magnets.
US09601946B2	Wireless power transmitter, wireless power receiver and wireless power transmission method Disclosed is a wireless power transmitter for wirelessly transmitting a power to a wireless power receiver. The wireless power transmitter includes a transmitting unit for transmitting a power supplied from a power source to the wireless power receiver using resonance, and a detecting unit for measuring an input impedance seen to the transmitting unit at the power source to detect a variation of an output impedance of the wireless power receiver by using the measured input impedance.
US09601945B2	Emergency back-up power system for traction elevators An emergency power supply for a traction elevator system utilizes a microprocessor-based control arrangement with pulse-width modulator technology to create an efficient, cost-effective back-up power system for a traction elevator. The microprocessor-based control arrangement is used to sense a power loss, or any type of irregularity in the power supply. Upon sensing some type of power malfunction, the microprocessor-based control arrangement disconnects the elevator system from the main power source and then generates a control signal to initiate the supply of back-up power. Once the elevator electrical system has been recharged and stabilized, the elevator control system will sense that recovery has occurred and will then provide an appropriate speed and direction command to the traction motor drive system.
US09601937B2	Power supply method, power supply device, and base station A method includes receiving currents supplied by a power generation apparatus, distributing the currents supplied by the power generation apparatus to a load and a lithium ion battery to ensure normal running of the load and enable the lithium ion battery to be charged. After the lithium ion battery is fully charge, the currents supplied by the power generation apparatus are distributed to the lead acid battery so that the lead acid battery is charged.
US09601931B2	Device and method for the monitoring and balancing of a multi-cell energy storage stack The present disclosure relates to a device for monitoring and balancing the cell voltages of at least two energy storage cells, which are electrically connected in series, of a multi-cell energy storage stack having at least one energy storage element, a voltage measuring unit, a first combinatorial circuit that is connected to each energy storage cell and the voltage measuring unit, a second combinatorial circuit that is connected to the energy storage element, the voltage measuring unit, and the first combinatorial circuit, and controls a control unit, which is connected to the voltage measuring unit and the first and second combinatorial circuit.
US09601930B2	Power transmitting device having device discovery and power transfer capabilities A wireless power transfer system is described that includes a power station and a chargeable device. The power station transmits discovery beacons in order to detect a chargeable device within its vicinity using any available communication protocols and/or standards. Once a device is discovered, the power station can perform coil selection with the device in order to select preferred coils for power transfer. In addition, the chargeable device is capable of detecting the beacon signal and providing a response to notify the power station of its presence. The chargeable device is capable of performing its own coil selection for further optimization and includes various assistance functionality to aid a user in optimizing a connection with the power station.
US09601928B2	Device for collecting energy wirelessly A device for collecting energy has first, second and third capacitive plates, each spaced from, substantially parallel to, and electromagnetically coupled to each other. An inductor is coupled between two of the plates, and a load resistance is inductively coupled to the inductor for drawing energy from electromagnetic field excitation between the plates. In a further embodiment, the inductor includes a first inductor coupled in series with a second inductor, and the load resistance is inductively coupled to the second inductor for drawing energy from electromagnetic field excitation between the plates, and the device further includes a first capacitor coupled in parallel with and spaced apart from the first inductor, and a second capacitor coupled between the first and second capacitive plates. In a still further embodiment, energy is collected by a coaxial transmission feed line.
US09601927B2	Electronic control device A first output voltage of a constant-voltage power supply is applied as a reference voltage of a multi-channel A-to-D converter and a monitor signal obtained by smoothing the first output voltage by a first power-supply filter is inputted as an input signal voltage. A micro-processor periodically writes digital conversion data of the monitor signal into shift registers to calculate a maximum deviation using a maximum value and a minimum value of the latest predetermined number of data, and determines a power-supply abnormality when the maximum deviation exceeds a predetermined threshold value.
US09601925B2	Stable subsea electric power transmission to run subsea high speed motors The invention provides a subsea pressure boosting system feasible for operation at subsea step out lengths above 40 km and by control merely from a dry topside or onshore location. The system is distinctive in that it comprises: at least one subsea power step out cable, arranged from a near end at a dry location onshore or topsides to one or more subsea loads such as subsea pumps or subsea compressors at a far end, at the near end at least one source for electric power is connected and the cable is dimensioned for operation at a frequency different from the operation frequency of the connected subsea loads in order to handle the Ferranti effect and electric losses, and at least one passive electric frequency transformer, operatively connected between the subsea step out cable far end and the subsea loads, said transformer is located in a pressure vessel and transforms the operation frequency of the subsea step out cable to a frequency feasible for operation of the connected loads.
US09601919B2	Time delay with control voltage sensing A method is provided for controlling operation of an air conditioning unit. The method comprises supplying line voltage to activate a motor configured to operate the air conditioning unit, and monitoring a supply of control voltage in order to control operation of the air conditioning unit, the supply of control voltage being derived from line voltage. In response to detecting a control voltage below a predetermined threshold and/or by a predetermined percentage, a time delay is initiated. The method further comprises deactivating the motor if a predetermined increase in control voltage is not detected before the time delay expires.
US09601915B2	Electronic safety shutoff with dual redundancy Electronic safety shutoff with dual redundancy is provided for use in combination with an electronic device to prevent fire, explosion, electrocution or shock. In one embodiment, four sensors, including two smoke sensors and two temperature sensors provide input to the logic gate circuit. The logic gate circuit determines the output signal to maintain power or interrupt power. Any combination of two or more sensors triggering will activate a power interrupting signal by the logic gate circuit, thereby activating an emergency power shutoff.
US09601914B2	Cable and flexible conduit gland assembly A cable and flexible conduit gland assembly includes a mounting member mounted in a predetermined object, one or multiple connection members, an outer cap, and one packing device and one or multiple auxiliary clamping sleeves mounted in the mounting member between the connection members and the outer cap and compressible by the outer cap and the connection members to wrap about the periphery of an inserted cable and to provide multiple packing effects. Thus, the cable and flexible conduit gland assembly has high IP rating, and is practical for dynamic mechanical application, or application in a deep-water environment or high explosive atmosphere.
US09601910B2	Riser glove, enclosure glove and strain releasing connectors A riser glove for shielding and/or sealing cables extending from a riser conduit includes a wrist portion sized for a sealing fit over the riser conduit, and a plurality of finger portions extending from the wrist portion. The finger portions taper from a widest section adjacent the wrist portion to a narrowest section at distal ends thereof. The finger portions include incremental indicators along lengths thereof corresponding to different cable gauges, respectively.
US09601907B2	System and method for thermal protection for a universal load control cabinet A universal load control module may include a power supply that operates over a wide voltage range, a microcontroller, and one or more functional control blocks. A functional control block may include a dimmer circuit for controlling a lighting load that provides reverse phase cut mode dimming, forward phase cut mode dimming, and hybrid phase cut mode dimming, as well as thermal protection. One or more universal control modules may be housed in a cabinet that include a cabinet control module. The cabinet may include additional thermal protection measures.
US09601903B2	Horizontal cavity surface emitting laser device A horizontal cavity surface emitting laser device includes an active layer configured to generate light to be emitted in one direction along the one surface of a semiconductor substrate and in another direction opposite to the one direction. The device also includes a rear distributed Bragg reflector unit configured to reflect the light. The rear distributed Bragg reflector unit includes a waveguide layer configured to guide light and a distributed Bragg reflector configured to reflect the light in the waveguide layer. The device further includes an optical component configured to guide, in a direction different from the one direction and the other direction, the light emitted from an end of the rear distributed Bragg reflector unit in the one direction. The device further includes a front reflecting mirror configured to reflect the light emitted from the active layer in the other direction toward another surface side of the semiconductor substrate.
US09601895B2	Ultra fast semiconductor laser A laser system includes first and second mirrors, a semiconductor laser and a high frequency pulse generator. The semiconductor laser generates optical power within an optical cavity and reflects the optical power between the first mirror and second mirrors. The optical power has a frequency of foriginal-laser. The high frequency pulse generator generates a high frequency pulse with a rise time greater than an optical cycle of the optical power within the optical cavity and directly impinges the high frequency pulse on the optical power within the optical cavity. Impinging the high frequency pulse on the optical power within the optical cavity causes a frequency shift of the optical power to generate a final laser frequency that is greater than foriginal-laser as well as beyond a frequency band of the second mirror to cause a final laser to be emitted past the second mirror and from the semiconductor laser.
US09601893B2	Laser apparatus There may be provided a laser apparatus including: an optical resonator including an output coupler; a laser chamber containing a laser medium and disposed in an optical path inside the optical resonator; a pair of discharge electrodes disposed inside the laser chamber; an electrode gap varying section configured to vary a gap between the discharge electrodes; a laser beam measurement section disposed in an optical path of a laser beam outputted from the output coupler, the laser beam resulting from electric discharge between the discharge electrodes; and a controller configured to control the gap between the discharge electrodes through activating the electrode gap varying section, based on a beam parameter of the laser beam measured by the laser beam measurement section.
US09601892B2	Method and system for managing thermally sensitive optical devices Two or more lasers or other temperature sensitive optical devices can be disposed in an operating environment, for example in a common enclosure exposed to the environment. The environment can have a temperature that fluctuates, for example in connection with random events, weather, seasons, etc. Each laser's temperature can track the temperature of the environment in steps, with each laser following a distinct temperature track. The lasers can alternate outputting light into a wavelength division multiplexing channel. For example, during one timeframe, one laser can provide an optical communication signal having a wavelength complying with a wavelength division multiplexing criterion. During another timeframe, the other laser can provide an optical signal having substantially the same wavelength. Operating a laser at an elevated temperature can shorten laser lifetime. To mitigate temperature induced failure, a replacement laser can be engaged when a failure predictor, precursor, or indicator meets a threshold.
US09601886B1	Communication plugs and components thereof The present invention generally relates to the field of network communication, and more specifically, to the field of communication plugs used in network connectivity. In an embodiment, the present invention is a communication connector that includes: a housing; a printed circuit board (PCB) assembly positioned inside of the housing, the PCB assembly including a first PCB and a second PCB, the PCB assembly further including a plurality of vias, each of the vias extending at least partially through both of the first PCB and the second PCB; and a plurality of plug contacts, each of the plug contacts including an interface section and a base section, the base section being positioned inside one of the vias.
US09601885B2	GG45 plug with hinging load bar A communication plug is described. The communication plug can have a load bar, a housing, and a divider. The load bar has a first half with first conductor receiving apertures and a second half with second conductor receiving apertures with a hinge connecting the first half and the second half. The load bar folds around the divider and then is inserted into the housing.
US09601882B2	Combined audio jack and mobile electronic device enclosure Enclosures for electronic devices are provided. These enclosures can be integrally formed with a full or partial receptacle connector shell for receiving electrical connectors such as audio connectors or plugs. For example, an enclosure made from a polymer can be integrally formed with an audio jack shell in an injection molding process. As another example, an enclosure can be integrally formed with one or more full or partial walls of an audio jack shell to form a single piece of polymer or metal and the remaining walls of the audio jack shell can be overmolded or assembled to the polymer or metal walls of the audio jack and proximate portions of the enclosure to form a full or complete audio jack shell.
US09601880B2	Cable assemblies and associated systems and methods Cable assemblies, methods and systems are provided that generally include a first patch cord, a second patch cord and a third patch cord that are removably positioned within a housing for packaging and payout thereof. The first patch cord includes a first elongated cord and a first connector mounted with respect to one end of the first elongated cord. The second patch cord generally includes a second elongated cord and a second connector mounted with respect to one end of the second elongated cord. The third patch cord generally includes a third elongated cord and a third connector mounted with respect to one end of the third elongated cord. The patch cord assemblies generally include a first coupler element for detachably securing the first patch cord relative to the second patch cord. A second coupler element is provided for detachably securing the second patch cord relative to the third patch cord.
US09601878B2	Communication module and communication module connector A communication module is further miniaturized to achieve an improvement in the mounting density of the communication module. A communication module includes a plug connector connected to a receptacle connector, and the plug connector has an insertion projection inserted into an insertion recess provided on the receptacle connector. The insertion projection has a board insertion portion into which an insertion end portion of a module board incorporated in the communication module is inserted formed therein, the insertion end portion is inserted into the board insertion portion, and first electrodes formed on the plug connector are electrically connected to the module board.
US09601877B2	Connector housing A connector housing is provided and includes a single sheet of material having a top wall, a pair of side walls, rear end wall, a bottom wall, and a pair of partition members. The bottom wall includes a first bottom wall portion integrally connected with one of the pair of side walls, a second bottom wall portion integrally connected with the other of the pair of side walls, and a third bottom wall portion separated from and assembled to the first and second bottom wall portions. The pair of partition members is disposed between the top wall and the bottom wall to divide an inner receiving space that is defined by the top wall, the pair of side walls and the bottom wall into three insertion ports.
US09601872B2	Anti-interference high-definition multimedia interface The present application relates to high-definition multimedia interface, particularly to a new anti-interference high-definition multimedia interface. The interface comprises a male connector and a female connector. The male connector includes a male outer plastic housing, a shield stretch rear housing and a male plastic cable clamp. The female connector includes a female outer plastic housing, an outer shield grounding housing, an inner shield grounding iron housing, a female insulator, a female signal terminal and a female plastic rear plug. The male outer plastic housing and the shield stretch rear housing together form an inner cavity after connecting to each other, in which the male terminal assembly will be received. The female outer plastic housing and the outer shield grounding housing together form an inner cavity after connecting to each other, in which the female terminal assembly is received.
US09601869B2	Connector This connector is provided with a male connector part (10) including male terminals (11), and a female connector part including female terminals. The male connector pan (10) and a second connector part are fitted together in a fixed fitting direction, and the male terminals (11) and the female terminals are connected. At least one of the outer peripheral surfaces (12a, 23a) of the male connector part (10) and the female connector part has, provided thereto, a plurality of front-alignment indicators (16a, 16b, 16c, 26a, 26b, 26c) which have an appearance that changes in accordance with the rotational angle of the viewing direction. At least one of the front-alignment indicators (16a, 16b 16c, 26a, 26b, 26c) can be seen in cases in which the at least one of the outer peripheral surfaces (12a, 23a) is viewed from a direction at rotational angle.
US09601864B2	Charging connector and method of mounting the same A charging connector for charging a battery in a vehicle has a housing (51) mounted to a vehicle. A tower (60) is in the housing (51) and has at least one accommodating chamber (64) for accommodating at least one terminal fitting (80). The tower (60) is inserted into a mating hole (52) of the housing (51). A seal (70) is between the tower (60) and the housing (51). The accommodating chamber (64) has a fitting (64a) at a rear end for fitting the terminal fitting (80) and an exposed portion (64b) at a front end for exposing a leading contact (82) of the terminal fitting (80) to be contacted with a mating terminal fitting of a mating charging connector on a charging cable. The tower (60) can be assembled and disassembled from the housing (51) with the terminal fitting(s) (80) mounted within the accommodating chamber(s) (64) of the tower (60).
US09601863B2	Device connector with reinforcing ribs A device connector includes a housing (20) with terminal supporting portions (30) projecting through a mounting hole (2) in a case (1) of a device. A flange (25) protrudes on the outer periphery of the housing (20) and faces a surface (2A) of the case (1) outward of the mounting hole (2). A surface packing (15) is mounted on the front surface of the flange (25) and is compressed between the front surface of the flange (25) and the case (1). A reinforcing portion (28) includes circumferentially spaced ribs (27) on the rear surface of the flange (25) and aligned in a front-back direction. A metal bracket (60) is fit externally fit on the housing (20). The bracket (60) presses the rear surface of the reinforcing portion (28) over the entire circumference and is bolt-fastened to an outer surface of the case (1).
US09601862B2	Charge connector A charge connector includes a connector case and a connector body. The connector case includes a pair of case split members to be coupled together. The connector body is housed in the connector case and includes charge terminals connected with electric wires and housed in a connector housing. The connector housing is provided with rotation direction regulation projections. The case split members are provided with rotation direction regulation holes that engage with the rotation direction regulation projections. The case split member is provided with a temporarily holding portion for holding the connector housing at a temporarily housed position. The connector housing is provided with a temporarily held portion at which the temporarily holding portion is locked.
US09601861B2	Charging connector connecting device A charging connector connecting device includes a cover that is movable between a closed position at which a connecting portion is closed and an open position at which the connecting portion is opened so that a second charging connector can be connected to the connecting portion; an elastic member that applies a biasing force to the cover so that the cover is positioned at an initial position between the closed position and the open position; and a pressing member configured to move with insertion of a first charging connector into the connecting portion so as to press the cover positioned at the initial position to thereby move the cover to the closed position.
US09601859B2	Terminal fitting A terminal fitting (20) has a main body (30) with a bottom wall (31), first and second facing walls (32, 33) extending from opposite sides of the bottom wall (31), an inner ceiling wall (34) extending from an extending end (33A) of the first facing wall (33) toward the second facing wall (32) and an outer ceiling wall (35) extending from an extending end (32A) of the second facing wall (33) toward the second facing wall (33) along an outer surface (34A) of the inner ceiling wall (34). A stabilizer (36) is formed by folding a projecting piece (37) standing up from the outer ceiling wall (35) toward the extending end (33A) of the first facing wall (33). A tip (37D) of the projecting piece (37) can contact the first facing wall (33) and the inner ceiling wall (34) in a recess (38) formed on a corner therebetween.
US09601856B2	Connecting device for a switchgear apparatus A connecting-device for a switchgear apparatus, includes: tulip-cluster-portions for electrically engaging with a contact-stud-element; a mounting-end-part for the mechanical connection to a pole-terminal, and conductive-transmitting-portions for transmitting electrical current from the contact-stud-element to the pole-terminal, each of the conductive-transmitting-portions extending from the respective tulip-cluster-portion to a respective base-portion of the mounting-end-part. The tulip-cluster-portions with the respective conductive-transmitting-portions and with the respective base-portions are integral with one other so as to define respective single-piece-portions.
US09601853B2	Printed wiring board and connector connecting the wiring board A printed wiring board (1) includes: a base substrate (3); a plurality of pads (15a, 17a) for electrical connection that are disposed at one surface side of the base substrate (3) and at a connection end portion (13) to be connected with another electronic component (50); wirings (9, 11) that are connected with the pads (15a, 17a); and engageable parts (28, 29) that are formed at side edge parts of the connection end portion (13) and are to be engaged with engagement parts (58) of the other electronic component (50) in the direction of disconnection. The wirings (9, 11) are disposed at the other surface side of the base substrate (3). The flexible printed wiring board (1) further includes reinforcement layers (31, 32) that are disposed at the one surface side of the base substrate (3) and at a frontward side with respect to the engageable parts (28, 29) when viewed in the direction of connection with the other electronic component, and that are formed integrally with the pads (15a).
US09601843B2	Actuating element and connecting terminal The invention relates to an actuating element (1) for actuating a clamping spring (8) of a connecting terminal, comprising: an actuating finger (2) which has an actuating surface (7) with which the actuating finger (2) presses onto a clamping limb (9) of the clamping spring (8) during actuation of the clamping spring (8); and a cover element (3) which forms an extension of the actuating finger (2) in the longitudinal direction of the actuating finger (2), the cover element (3) being laterally molded on the actuating finger (2).
US09601842B2	Connecting unit having a column with a plurality of planar elastic fins extending from the column The present invention discloses a matable and dematable electrical connecting structure characterized by comprising: a female coupling member having a first connecting portion; a male coupling member having a second connecting portion; and a connecting unit coupling the female coupling member and the male coupling member and electrically connecting the first and second connecting portions, wherein the connecting unit includes an inner conductive material which is electrically connected to the first connecting portion and is provided on the inner wall of an insert hole formed in the female connecting member, a column including a conductive material which is electrically connected to the second connecting portion, protruding from the male connecting member, and can be inserted in the insert hole, and one or more elastic pin including a surface of a conductive material which is extending in an outward direction from the column and elastically contacting the inner conductive material.
US09601839B2	Crimping terminal A crimping terminal includes a conductor crimping portion having a U-shaped cross section. The conductor crimping portion includes a base plate portion and a pair of conductor caulking pieces. On an inner surface of the conductor crimping portion, a conductor is disposed, being exposed to a distal end of an aluminum electric wire. The pair of conductor caulking pieces, extending upwardly from both side edges in a longitudinal direction of the base plate portion, are bent inwardly so as to wrap the conductor of the aluminum electric wire to caulk the conductor such that the conductor is in close contact with the inner surface of the base plate portion. On the inner surface of the conductor crimping portion, a protruding indent is provided so as to extend continuously.
US09601838B2	Splice for gathering ends of electric wire bundle A splice for gathering ends of an electrical wire bundle, capable of maintaining a welded portion at the center in a cap member regardless of the number of wires in the electrical wire bundle; protecting the welded portion from vibrations and impacts; and of being versatile so as to be used in multiple wire bundles. The splice includes: an electrical wire portion (10) having a wire core splice portion (14) in which wire cores (13) are welded together; a cushioning member (20) covering an outer circumferential face of the electrical wire portion (10); a protective cap (30) accommodating an end portion of the electrical wire portion (10) and fixes the electrical wire portion (10) via the wire core splice portion (14); and a cover tape (40) wound around the protective cap (30), a portion of the cushioning member (20) exposed from the protective cap (30), and the electrical wire bundle.
US09601834B2	Wide angle planar antenna assembly Exemplary embodiments, the present disclosure are related to an antenna system including radiating elements and reflectors. The reflectors can be disposed with respect to the radiating elements to reflect radiation from the radiating elements to generate a coverage area that exceeds the coverage area generated by the radiating elements without the reflectors.
US09601827B2	Array-fed reflector antenna device and method of controlling this device Beam direction controlling unit includes a relative position determining unit that determines a relative position between a reflector antenna and an array antenna by controlling a driver, e.g., driving unit, a drive controlling unit, such that a range on the array antenna onto which a parallel light beam from a desired beam direction is projected is a range in which element antennas are arranged, an excitation element selector that selects, as element antennas to be excited, element antennas onto which the parallel light beam is projected at the determined relative position, an excitation amplitude phase determining unit that sets an excitation amplitude phase of the selected element antennas, and sets the excitation amplitude phase to an excitation amplitude phase controller, e.g., an amplitude controller, a phase shifter, and an excitation amplitude phase controlling unit, and a transmitter/receiver connecting unit that connects the selected element antennas to a transmitter/receiver.
US09601822B2	Antenna for satellite communication An antenna for satellite communication includes; a signal transmitting and receiving unit for receiving or transmitting a signal from/to the satellite; a driving unit for rotating the signal transmitting and receiving unit so as to enable the signal transmitting and receiving unit to track the satellite; an anti-vibration unit provided inside the posts for elastically supporting the signal transmitting and receiving unit or the driving unit. Therefore, by providing the anti-vibration unit inside the posts, it is possible to increase availability for a circumferential space of the posts and to simplify the structure of the anti-vibration unit.
US09601818B2	Microwave circuit A microwave circuit with which cracks in substrates can be suppressed and which can reduce the size of module including the microwave circuit is provided. The microwave circuit includes a multilayer first substrate, a second substrate that opposes the first substrate, a plurality of first electrically conductive members that electrically connect a first layer of the first substrate and the second substrate to each other, a plurality of second electrically conductive members that electrically connect the first layer of the first substrate and another layer of the first substrate to each other and each of the plurality of second electrically conductive members has a smaller diameter than that of each of the first electrically conductive members, and transmission lines that connect the first electrically conductive members and the second electrically conductive members. In the microwave circuit, the plurality of first electrically conductive members and the plurality of second electrically conductive members are alternately disposed along an end portion of the first substrate.
US09601817B2	30 GHz IMUX dielectric filter having dielectrics inserted into receiving spaces and having a horizontal orientation A dielectric filter includes a receiving member with a plurality of receiving spaces and a cover. The cover is arranged to cover the receiving spaces in the receiving member. Each receiving space of the plurality of receiving spaces includes a rectangular cavity with a dielectric.
US09601813B2	Battery pack A battery pack includes a battery cell having an electrode tab and a protective circuit module electrically connected to the electrode tab. The protective circuit module has a first surface in an assembling direction of the electrode tab and a second surface opposite the first surface. The electrode tab is separated from the first surface. Therefore, the battery pack has an improved connection structure between the battery cell and the protective circuit module, and short circuits can be prevented or substantially prevented.
US09601811B2	Nonaqueous electrolyte secondary cell Provided is a nonaqueous electrolyte secondary cell including: a case; an element housed in the case, including at least a positive electrode member, a negative electrode member and a separator; and an electrolyte solution poured into the case, wherein when in the state of the case being installed, in the direction perpendicular to the liquid surface of the electrolyte solution, the length between the highest position and the lowest position of the element is represented by L1 and the length between the liquid surface and the lowest position of the element is represented by L2, the ratio calculated with the formula L2/L1×100 is 10% or more and 100% or less.
US09601810B2	Method for manufacturing lithium ion cells A method for manufacturing lithium ion cells includes the steps of: 1) coating a collector roll along an unreeling direction thereof to form one or more strip coated areas, two side edges of the coated area each being provided with an uncoated area to form tabs thereon; 2) compacting the coated collector roll and obtaining a compacted collector roll; 3) cutting the compacted collector roll into anode plates/cathode plates having different sizes each having a tab and rounded corners; 4) recombining an anode plate/a cathode plate with a separator; cutting the separator after recombination to form rounded corners at a position corresponding to the rounded corners of the anode plate/cathode plate and further obtain a mono-cell or a half-cell having different sizes; 5) stacking the mono-cells and half-cells into a step preliminary cell; and 6) hot pressing the stacked preliminary cell to form a whole lithium ion cell via bonding of the anode plates/cathode plates with the separator.
US09601808B2	Nonaqueous electrolytic solution containing glycol sulfate derivative and fluoroethylene carbonate and lithium ion secondary battery containing the same A nonaqueous electrolytic solution includes a cyclic carbonate and a chain carbonate, and contains a glycol sulfate derivative represented by formula (I) below and fluoroethylene carbonate: [wherein each of R1 and R2 independently represents at least one selected from the group consisting of a hydrogen atom and a hydrocarbon group having 1 to 5 carbon atoms].
US09601805B2	Process for producing non-flammable quasi-solid electrolyte and electrolyte-separator for lithium battery applications A process for producing a separator-electrolyte layer for use in a lithium battery, comprising: (a) providing a porous separator; (b) providing a quasi-solid electrolyte containing a lithium salt dissolved in a first liquid solvent up to a first concentration no less than 3 M; and (c) coating or impregnating the separator with the electrolyte to obtain the separator-electrolyte layer with a final concentration≧the first concentration so that the electrolyte exhibits a vapor pressure less than 0.01 kPa when measured at 20° C., a vapor pressure less than 60% of that of the first liquid solvent alone, a flash point at least 20 degrees Celsius higher than a flash point of the first liquid solvent alone, a flash point higher than 150° C., or no detectable flash point. A battery using such a separator-electrolyte is non-flammable and safe, has a long cycle life, high capacity, and high energy density.
US09601804B2	Gel polymer electrolyte, lithium battery including gel polymer electrolyte, and method of preparing gel polymer electrolyte A gel polymer electrolyte including: an organic solvent; a lithium salt that reacts with residual water contained in the organic solvent to produce at least one material selected from the group consisting of a protonic acid and a Lewis acid; and a polymer that is generated by polymerizing at least one monomer selected from the group consisting of monomers represented by Formulae 1 to 3 below: wherein in Formulae 1 to 3, R1 to R31 are the same as defined in the detailed description section of the specification.
US09601795B2	Process for production of scandia-stabilized zirconia sheet, scandia-stabilized zirconia sheet obtained by the process, and scandia-stabilized zirconia sintered powder The present invention relates to a method of producing a scandia-stabilized zirconia sheet. The method includes the steps of: (1) pulverizing a scandia-stabilized zirconia sintered body to obtain a sintered scandia-stabilized zirconia powder having an average particle diameter (De), determined by a transmission electron microscope, in the range of 0.3-1.5 μm, and an average particle diameter (Dr), determined by a laser scattering method, in the range of 0.3-3.0 μm, where a ratio of Dr/De is at least 1.0-2.5; (2) preparing a slurry containing the sintered scandia-stabilized zirconia powder and an unsintered zirconia powder, where a percentage of the sintered scandia-stabilized zirconia powder to a sum of the sintered scandia-stabilized zirconia powder and the unsintered zirconia powder in the slurry is at least 2 mass % and at most 40 mass %; (3) molding the slurry into a green sheet; and (4) sintering the green sheet.
US09601793B2	Electrolyte film—electrode assembly An electrolyte membrane-electrode assembly comprises a polymer electrolyte membrane; a cathode catalyst layer and a cathode gas diffusion layer including a cathode micro porous layer and a cathode gas diffusion layer substrate, arranged in order on one side of the polymer electrolyte membrane, and an anode catalyst layer and an anode gas diffusion layer including an anode micro porous layer and an anode gas diffusion layer substrate, arranged in order on the other side of the polymer electrolyte membrane. A relative gas diffusion coefficient of the anode micro porous layer is smaller than a relative gas diffusion coefficient of the cathode micro porous layer by an amount equal to or greater than 0.05[−].
US09601790B2	Fuel cell system and control method of fuel cell system In a fuel cell system which executes a stop process of stopping an output from a fuel cell when a required power generation amount for the fuel cell is smaller than a predetermined power generation amount and supplies oxidant during a stop process period, fuel gas is intermittently supplied to a fuel electrode at a basic supply interval, which is set in advance and at which carbon dioxide is not generated in an oxidant electrode, during the stop process period.
US09601789B2	Self-pumping membraneless fuel cell The present invention is directed to a device, and method of operation, for a fuel cell which uses bubble-based pumping to self-pump the fuel to the anode, and a single, common channel separating the anode from the cathode through which a mixed fuel and electrolyte flow. The fuel cell includes a single channel having two of its sides formed by the anode and the cathode, each having a suitable catalyst. A bubble generating region is formed in the anode and cathode reaction area of the channel. A one-way valve is located upstream of the bubble generating region. A vent for venting bubbles is disposed over a portion of the channel downstream of the bubble generating region. The fuel cell may be advantageously used to build miniature fuel cells for miniature electronic devices, or scaled to build larger fuel cells for larger electronic devices.
US09601786B2	Leakproofing device for fuel cell, unit and fuel cell comprising such a device Leakproofing device for a fuel cell intended to be interposed between an Electrodes Membrane Assembly and a polar or bipolar plate of a fuel cell unit, the device consisting of a rigid frame and of a leakproofing seal integral with the frame, the frame furnished with the leakproofing seal defining a plurality of apertures through the device, the apertures being delimited by the leakproofing seal.
US09601784B1	Supported Ni—M materials for electrooxidation of hydrazine A supported bi-metallic non-platinum catalyst that is capable of oxidizing hydrazine to produce, as by-products of energy production, nitrogen, water, and zero or near-zero levels of ammonia is described. The catalyst is suitable for use in fuel cells, particularly those that utilizes an anion-exchange membrane and a liquid fuel such as hydrazine.
US09601781B2	Secondary battery and method for manufacturing secondary battery A secondary battery has an electrode laminated body and a collector member. The laminated body is formed of a laminated electrode sheet. The collector member is bonded to a collector foil laminated portion of the electrode sheet not formed with an active material layer. The collector foil laminated portion and the collector member are bonded at overlapped portions by resistance welding using electrodes. When a pressure welding direction is a projection direction, an area ratio (Yd)/(Xd) is 1.2-4, in which Xd is a projection area of a surface of the electrode made contact with the collector foil laminated portion and Yd is a projection area of a surface of the electrode made contact with the collector member.
US09601780B2	Multilayer conductive film, current collector using same, battery and bipolar battery A multilayer conductive film includes a layer 1 including a conductive material containing a polymer material 1 having an alicyclic structure and conductive particles 1 and a layer 2 including a material having durability against positive electrode potential. The multilayer conductive film has stability in an equilibrium potential environment in a negative electrode and stability in an equilibrium potential environment in a positive electrode, has low electric resistance per unit area in the thickness direction, and has excellent barrier properties for a solvent of an electrolytic solution. A battery including a current collector employing the multilayer conductive film can achieve both weight reduction and durability.
US09601777B2	Anode for lithium secondary battery, method for manufacturing same, and lithium secondary battery including same Disclosed is an anode for a lithium secondary battery, including a carbon-based anode active material, a binder and a conductive polymer, wherein the conductive polymer is in fiber form. A lithium secondary battery including the anode is also provided. As the anode for a lithium secondary battery includes a conductive polymer in fiber form, poor conductivity, which is a problem with a carbon-based anode active material, can be overcome, and the anode can be easily manufactured.
US09601773B2	Anode materials for lithium-ion batteries The current disclosure relates to an anode material with the general formula MySb-M′Ox—C, where M and M′ are metals and M′Ox—C forms a matrix containing MySb. It also relates to an anode material with the general formula MySn-M′Cx—C, where M and M′ are metals and M′Cx—C forms a matrix containing MySn. It further relates to an anode material with the general formula Mo3Sb7—C, where —C forms a matrix containing Mo3Sb7. The disclosure also relates to an anode material with the general formula MySb-M′Cx—C, where M and M′ are metals and M′Cx—C forms a matrix containing MySb. Other embodiments of this disclosure relate to anodes or rechargeable batteries containing these materials as well as methods of making these materials using ball-milling techniques and furnace heating.
US09601769B2	Active material, nonaqueous electrolyte battery, and battery pack According to one embodiment, there is provided an active material. The active material contains a composite oxide represented by a following general formula: the general formula: Lix(Nb1−yTay)2−zTi1+0.5zM0.5zO7, in which 0≦x≦5, 0≦y≦1, and 0
US09601761B2	Composite cathode active material, method of preparing the composite cathode active material, and cathode and lithium battery each including the composite cathode active material A composite cathode active material, a method of preparing the composite cathode active material, a cathode including the composite cathode active material, and a lithium battery including the cathode. The composite cathode active material includes a lithium intercalatable material; and a garnet oxide, wherein an amount of the garnet oxide is about 1.9 wt % or less, based on a total weight of the composite cathode active material.
US09601760B2	Negative electrode active material for lithium secondary battery and lithium secondary battery comprising the same Provided is a negative electrode active material comprising (a) a core including a carbon-based material, and (b) an organic polymer coating layer formed of a polymer compound having a content of a fluorine component of 50 wt % or more on a surface of the core.
US09601756B2	Lithium secondary battery of high energy density with improved energy property High energy density lithium secondary batteries are disclosed herein. In some embodiments, a high energy density lithium secondary battery includes a cathode, an anode, and a separator. The cathode includes a first cathode active material having a layered structure and a second cathode active material having a spinel structure, wherein the amount of the first cathode active material is between 40 and 100 wt % based on the total weight of the cathode active materials. The anode includes crystalline graphite and amorphous carbon as anode active materials, wherein the amount of the crystalline graphite is between 40 and 100 wt % based on the total weight of the anode active materials.
US09601752B2	Positive active material for lithium secondary battery, precursor of positive active material, electrode for lithium secondary battery and lithium secondary battery Provided is a positive active material for a lithium secondary battery includes a lithium transition metal composite oxide having an α-NaFeO2-type crystal structure and represented by the composition formula of Li1+αMe1−αO2 (Me is a transition metal including Co, Ni and Mn and α>0). The positive active material contains Na in an amount of 900 ppm or more and 16000 ppm or less, or K in an amount of 1200 ppm or more and 18000 ppm or less.
US09601750B2	Surface-treated electrode active material, method of surface treating electrode active material, electrode, and lithium secondary battery A surface-treated electrode active material, a method of surface treating an electrode active material, an electrode, and a lithium secondary battery. The surface-treated electrode active material includes a surface metal oxide layer having higher degree of reduction of a metal than that of a bulk metal oxide layer. The method includes: forming a mixture by adding an untreated electrode active material comprising a metal oxide, and at least one of a basic material and a reducing material to a solvent; and stirring the mixture.
US09601749B2	Electrode for battery, nonaqueous electrolyte battery, and battery pack According to one embodiment, there is provided an electrode for battery. The electrode includes a current collector and an active material layer provided on the current collector. The active material layer includes a first powder of a monoclinic titanium dioxide compound and a second powder a monoclinic titanium dioxide compound. The first powder has a minor-axis average dimension of primary particles in the range from 0.5 μm to 5 μm and a major-axis average dimension of primary particles in the range from 0.5 μm to 20 μm. The second powder has a minor-axis average dimension of primary particles in the range from 0.01 μm to 0.3 μm and a major-axis average dimension of primary particles in the range from 0.5 μm to 1 μm.
US09601734B2	Battery In general, according to one embodiment, there is provided a battery. This battery includes a container, a lid, a gas-relief vent, an electrode group, an intermediate lead, and a terminal lead. The gas-relief vent is provided in the lid. The intermediate lead includes a first lead-joint part, an electrode-group-joint part, and a leg part. The leg part connects the first lead-joint part and the electrode-group-joint part to each other. The first lead-joint part and the electrode-group-joint part are located on planes different from each other.
US09601733B2	Battery pack of electric vehicle, electric vehicle chassis and method for replacing battery modules Provided are systems and methods for configuring battery packs in electric vehicles. A battery pack may include a plurality of battery modules, a support part, and at least one opening provided on the support part. The support part may be provided with a bottom for supporting the plurality of battery modules, sides, a top, and an accommodation space formed by the bottom, the sides, and the top for accommodating the plurality of battery modules. The opening provided on the bottom of the support part may enable the plurality of battery modules to be passed through the at least one opening and be detachably mounted to the bottom of the support part so as to be supported by the bottom.
US09601731B2	Battery case The present invention relates to a battery case for a vehicle, and more particularly to a battery case for effectively lowering or raising the temperature of a battery module consisting of a plurality of batteries used in a vehicle or mechanical apparatus. According to the present invention, a battery case includes: a lower frame with an upper open part; a lower plate fixed to the lower frame for holding the battery module thereon, the lower plate being formed lengthwise with an inlet hole, an outlet hole, and a heat exchange hole; an inner upper frame with an upper surface having a terminal through-hole for enclosing the battery module; a front frame attached to an open front of the inner upper frame for holding a suction fan at the lower part thereof; an outer upper frame with an upper surface having a terminal through-hole for enclosing the inner upper frame and the front frame; a rear plate attached to the rear of the outer upper frame for holding an exhaust fan; and a guide partition wall arranged in the side of the inner upper frame so as to closely contact the battery module, characterized in that the guide partition wall guides the cooling (heating) air sucked by the suction fan along a zigzag path from the lower part of the side of the battery module to the upper part thereof to the exhaust fan.
US09601729B2	Battery pack for power tool A power-tool battery pack usable as a power supply of a power tool and capable of slidably attaching to and detaching from a tool main body of the power tool includes a battery main body and a case that houses the battery main body. The battery main body includes a female terminal having inner sides configured to electrically connect to and sandwich a male terminal slidably attachable to the battery pack. The case includes a case main body and a case-cover part. The case-cover part has an opening for receiving the male terminal and sandwiching-wall parts for sandwiching the female terminal from outer sides of the female terminal. The female terminal and the sandwiching-wall parts are configured such that, at least when the female terminal sandwiches the male terminal, parts of the female terminal facing the sandwiching-wall parts are caused to touch the sandwiching-wall parts.
US09601727B2	Battery pack A battery pack is disclosed. In one aspect, the battery pack includes a battery cell comprising first and second sides opposing each other, a first cell holder coupled to the first side of the battery cell and a second cell holder coupled to the second side of the battery cell. The battery pack further includes a first protection circuit module (PCM) holder coupled to a surface of the first cell holder and a second PCM holder coupled to a surface of the second cell holder and combined with the first PCM holder. According to one embodiment, the battery pack can facilitate combination and assembly of battery cells and a protection circuit module.
US09601724B2	Packaging material for lithium ion battery A packaging material for a lithium ion battery includes at least a first adhesive layer, a metal foil layer, a corrosion prevention-treated layer, a second adhesive layer, and a sealant layer which are sequentially laminated on one surface of a base material layer. The thickness of the base material layer is 15 to 40 μm.
US09601723B2	Electrochemical device with crimp ring closure and method Electrochemical device and method. The electrochemical device has an electrochemical module and an enclosure configured to enclose the electrochemical module. The enclosure has an electrically conductive first housing portion forming a first rim and an electrically conductive second housing portion forming a second rim, the first housing portion and the second housing portion, when the first rim of the first housing portion substantially abuts the second rim of the second housing portion, forming, at least in part, a volume configured to enclose the electrochemical device. The enclosure further has a substantially non-conductive grommet positioned between the first rim and the second rim, and a crimp ring engaging the first rim and the second rim, the crimp ring being configured to secure the first housing portion with respect to the second housing portion. The grommet is further positioned between the crimp ring and the first rim and the second rim.
US09601720B2	Organic light emitting diode display An organic light emitting diode display includes a plurality of switches, a plurality of organic light emitting diodes respectively connected to the switches, and a polarization layer on the organic light emitting diodes. The polarization layer includes a light blocking area and a plurality of color filters. The light blocking area has a plurality of openings respectively exposing the organic light emitting diodes. The color filters respectively fill the openings. A first dot opening includes a first red opening, a first green opening, and a first blue opening elongated in a first direction. A second dot opening includes a second red opening, a second green opening, and a second blue opening elongated in a second direction crossing the first direction.
US09601719B2	Light source having an outsource device The invention relates to a light source (1) comprising a light generating unit (2) like an organic light emitting diode and an outcoupling device (3) for coupling light out of the light generating unit in an outcoupling direction (4). The outcoupling device comprises a first region (5) for facing the light generating unit, a second region (7) having a refractive index being smaller than the refractive index of the first region, and a structured intermediate region (6) between the first region and the second region. The first region is optically homogenous and has a thickness in the outcoupling direction being larger than a coherence length of the light, thereby reducing generally possible wavelength dependent interference effects and, thus, a corresponding degradation of the outcoupling efficiency. The outcoupling efficiency can therefore be increased.
US09601717B2	Organic light emitting display apparatus An organic light-emitting display (OLED) device includes: a pixel area defined by a plurality of pixels on a flexible substrate; a non-pixel area around the pixel area; a gate driver in the non-pixel area; a structure in the non-pixel area configured to surround the pixel area; a first encapsulation layer covering the plurality of pixels, the gate driver and the structure; and a particle cover layer covering the pixel area and suppressed from being excessively spread by the structure.
US09601716B2	Shorts prevention in organic light-emitting diodes An organic light emitting diode comprising a first electrode layer, a second electrode layer, a stack of functional layers, including an organic light-emitting layer, sandwiched between said first electrode layer and said second electrode layer, and an passivation layer arranged adjacent to said first electrode layer is disclosed. The passivation layer reacts with the first electrode layer to form an oxide at a reaction temperature that is induced by an evolving short circuit between the first electrode layer and the second electrode layer. The passivation layer is unreactive at temperatures lower than the reaction temperature.
US09601712B2	Light emitting device and method of manufacturing the same A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material. Further, reaction between electrodes of the light emitting elements (cathodes or anodes) and the sealing materials can be prevented by covering the electrodes with a transparent protective layer, for example, CaF2, MgF2, or BaF2.
US09601705B2	Material for organic electroluminescence element and organic electroluminescence element using the same, and method for manufacturing organic electroluminescence element A material for organic electroluminescence element, including: a phosphorescent compound; and a discotic liquid-crystalline host compound, wherein the phosphorescent compound has an aspect ratio of molecule core diameter to molecule core thickness (molecule core diameter/molecule core thickness) of at least 3, and wherein a size ratio of the molecular radius of the phosphorescent compound to the molecular radius of the discotic liquid-crystalline host compound (molecular radius of the phosphorescent compound/molecular radius of the discotic liquid-crystalline host compound) is 0.8 to 1.2.
US09601696B2	Electroluminescent composition and electric device with high brightness The present invention is to provide a composition that can provide an electroluminescent device emitting light with high brightness. The present invention provides following: a composition including a polymer compound comprising one or more structural unit(s) selected from the group consisting of a structural unit represented by Formula (1), a structural unit represented by Formula (3), a structural unit represented by Formula (5), a structural unit represented by Formula (16), a structural unit represented by Formula (18), a structural unit represented by Formula (20), and a structural unit represented by Formula (22) and an ionic compound represented by Formula (23); an organic film and an electric device comprising the composition.
US09601692B1	Hetero-switching layer in a RRAM device and method A semiconductor device includes first electrodes disposed upon a substrate, wherein each first electrode comprises a metal containing material, switching devices disposed overlying the first electrodes, wherein each switching device comprises a first switching material, a second switching material, and an active metal, wherein the first switching material is disposed overlying and contacting the first electrodes, wherein the second switching material is disposed overlying and contacting the first switching material, wherein the active metal is disposed overlying and contacting the second switching material, wherein the first switching material is characterized by a first switching voltage, wherein the second switching material is characterized by a second switching voltage greater than the first switching voltage; and second electrodes disposed above the switching devices, comprising the metal material, and wherein each of the second electrodes is electrically coupled to the active metal material of the switching devices.
US09601689B2	Memory device According to one embodiment, a memory device includes a plug, a variable resistance film provided on the plug, and an electrode provided on the variable resistance film. The variable resistance film includes, a first portion having a superlattice structure, and a second portion having an amorphous structure.
US09601688B2	Method of manufacturing magnetoresistive element and method of processing magnetoresistive film In a case where reactive ion etching using a gas containing an oxygen atom is used for etching or a magnetoresistive element, a magnetic film becomes damaged due to oxidation. Such damage to the element by the oxidation becomes a factor which causes deterioration in element properties. In the etching of the magnetoresistive element according to one embodiment of the present invention, a magnetoresistive film is subjected to ion beam etching and thereafter to reactive ion etching. A side deposition formed by the ion beam etching coats a sidewall of the magnetoresistive film and reduces damage by the oxygen atom during the later reactive ion etching. Also, a time during which the element is exposed to plasma of the gas containing the oxygen atom can be reduced.
US09601687B2	Dual interface free layer with amorphous cap layer for perpendicular magnetic tunnel junction A magnetic tunnel junction (MTJ) and methods for fabricating a MTJ are described. An MTJ includes a fixed layer and a barrier layer on the fixed layer. Such an MTJ also includes a free layer interfacing with the barrier layer. The free layer has a crystal structure in accordance with the barrier layer. The MTJ further includes an amorphous capping layer interfacing with the free layer.
US09601686B1	Magnetoresistive structures with stressed layer A method of making a magnetoresistive structure is disclosed. The method includes forming a pillar structure including a magnetic tunnel junction on a substrate that includes a first electrode, depositing a stressed layer onto a pillar structure sidewall, and depositing a second electrode above the magnetic tunnel junction.
US09601684B2	Piezoelectric element and piezoelectric vibrator having the same Disclosed are a piezoelectric element and a piezoelectric vibrator having the same. The piezoelectric element and the piezoelectric vibrator having the same in accordance with an embodiment of the present invention include: a piezoelectric material formed by laminating a plurality of ceramic layers with one another; internal electrodes formed, respectively, on surfaces of the ceramic layers; and a pair of cover layers formed, respectively, above and below the piezoelectric material in order to protect the internal electrodes, and at least one of the cover layers includes: a plurality of crystal grains; and crack inhibiting particles disposed at boundaries between the plurality of crystal grains and configured to inhibit a crack from spreading in the cover layers.
US09601681B2	High temperature superconducting films and methods for modifying and creating same Operational characteristics of an high temperature superconducting (“HTS”) film comprised of an HTS material may be improved by depositing a modifying material onto appropriate surfaces of the HTS film to create a modified HTS film. In some implementations of the invention, the HTS film may be in the form of a “c-film.” In some implementations of the invention, the HTS film may be in the form of an “a-b film,” an “a-film” or a “b-film.” The modified HTS film has improved operational characteristics over the HTS film alone or without the modifying material. Such operational characteristics may include operating in a superconducting state at increased temperatures, carrying additional electrical charge, operating with improved magnetic properties, operating with improved mechanic properties or other improved operational characteristics. In some implementations of the invention, the HTS material is a mixed-valence copper-oxide perovskite, such as, but not limited to YBCO. In some implementations of the invention, the modifying material is a conductive material that bonds easily to oxygen, such as, but not limited to, chromium.
US09601674B2	Light-emitting device A light-emitting device, including a substrate; a plurality of light-emitting units formed on the substrate, wherein the plurality of light-emitting units include a first light-emitting unit; a second light-emitting unit; and a group of light-emitting units formed between the first light-emitting unit and the second light-emitting unit, wherein each of the plurality of light-emitting unit includes a first-type semiconductor layer, a second-type semiconductor layer and an active layer formed between the first-type semiconductor layer and the second-type semiconductor layer; a plurality of electrical connections formed on the plurality of light-emitting units, electrically connecting each two of the light-emitting units adjacent; a first pad formed on the first light-emitting unit; a second pad and a third pad formed on the second light-emitting unit; wherein one of the plurality of electrical connection connects and extends from the second pad.
US09601672B2	High brightness LED package Light sources are disclosed utilizing LED dies that have a light emitting surface. A patterned low refractive index layer that can support total internal reflection within the LED die is provided in optical contact with a first portion of the emitting surface. In optical contact with a second portion of the emitting surface is an input surface of an optical element. The refractive index of the low index layer is below both that of the optical element and the LED die. The optical element can have a variety of shapes and sizes.
US09601671B2	Optical systems fabricated by printing-based assembly Provided are optical devices and systems fabricated, at least in part, via printing-based assembly and integration of device components. In specific embodiments the present invention provides light emitting systems, light collecting systems, light sensing systems and photovoltaic systems comprising printable semiconductor elements, including large area, high performance macroelectronic devices. Optical systems of the present invention comprise semiconductor elements assembled, organized and/or integrated with other device components via printing techniques that exhibit performance characteristics and functionality comparable to single crystalline semiconductor based devices fabricated using conventional high temperature processing methods. Optical systems of the present invention have device geometries and configurations, such as form factors, component densities, and component positions, accessed by printing that provide a range of useful device functionalities. Optical systems of the present invention include devices and device arrays exhibiting a range of useful physical and mechanical properties including flexibility, shapeability, conformability and stretchablity.
US09601670B2	Method to form primary optic with variable shapes and/or geometries without a substrate A submount-free light emitter package with primary optic and method of fabricating the same are disclosed, these packages and methods comprising a light emitter with an optic. The optic may have a shape, which includes a portion that is wider at a point further from the light emitter than a point which is closer. The method includes a light emitter disposed on a carrier surface with at least one structure at least partially surrounding the light emitter. The encapsulant is over the light emitter forming a primary optic. The intermediate element at least partially defines the shape of the primary optic.
US09601667B2	Light-emitting device A light-emitting device is provided. The light-emitting device comprises: a light-emitting stack having an active layer; an electrode structure on the light-emitting stack and comprising a first electrode and an extension electrode protruding from the first electrode toward an edge of the light-emitting device in a first extending direction; a transparent insulating layer between the light-emitting stack and the electrode structure, wherein the transparent insulating layer comprises a first part and an extension part protruding from the first part toward the edge of the light-emitting device in a second extending direction; wherein a surface area of a surface of the first electrode distal from the transparent insulating layer is smaller than a surface area of a surface of the transparent insulating layer distal from the light-emitting stack, the first electrode is right above the first part, and a part of the extension electrode is right above the extension part.
US09601658B2	Solid state lighting devices without converter materials and associated methods of manufacturing Solid state lighting devices that can produce white light without a phosphor are disclosed herein. In one embodiment, a solid state lighting device includes a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The active region includes a first sub-region having a first center wavelength and a second sub-region having a second center wavelength different from the first center wavelength.
US09601653B2	Na dosing control method A method includes placing at least two substrates on a substrate carrier at a distance from one another, placing the substrate carrier in a reaction chamber, depositing a precursor on the at least two substrates, and performing a first annealing process on the at least two substrates. The at least two substrates include a first content of a first material. The distance between the at least two substrates is based on the first content of the first material and at least one processing parameter. The disclosed method advantageously provides for improved Na-dosing control.
US09601648B2	Method of manufacturing pattern using trench structure and pattern manufactured thereby, and method of manufacturing solar battery using the manufacturing method and solar battery manufactured thereby The present disclosure provides a method of manufacturing a pattern including: forming a trench structure on a substrate using an inkjet method; filling an interior portion of the trench structure with a filler; and removing the trench structure, and a pattern manufactured using the same, and a method of manufacturing a solar battery using the method of manufacturing a pattern and a solar battery manufactured using the same.
US09601647B2	Converting infrared light into broadband visible light at high efficiency using lanthanide-sensitized oxides The present invention includes upconversion materials such as lanthanide-sensitized oxides that are useful for converting low-energy photons into high-energy photons. Because silicon-based solar cells have an intrinsic optical band-gap of 1.1 eV, low-energy photons having a wavelength longer than 1100 nm, e.g., infrared photons, cannot be absorbed by the solar cell and used for photovoltaic energy conversion. Only those photons that have an energy equal to or greater than the solar cell's band gap, e.g., visible photons, can be absorbed and used for photovoltaic energy conversion. The oxides described herein transform photons having an energy less than the energy of a solar cell's band gap into photons having an energy equal to or greater than the energy of the band gap. When these oxides are incorporated into a solar cell, they provide more photons for photovoltaic energy conversion than otherwise would be available in their absence. Nearly 10% of the infrared photons incident on these oxides are upconverted into visible photons. This upconversion efficiency is more than twice as large as the upconversion efficiency for NaYF4-based upconversion materials. The solar radiation energy conversion efficiency of a silicon-based solar cell will increase by 1.8% or greater by including the oxides described herein because they allow the solar cell to absorb and use are larger portion of the solar spectrum for photovoltaic energy conversion.
US09601643B2	Photoelectric conversion element A photoelectric conversion element includes a superlattice semiconductor layer including barrier sub-layers and quantum sub-layers (quantum dot sub-layers) alternately stacked and also includes a wavelength conversion layer containing a wavelength conversion material converting the wavelength of incident light. The wavelength conversion layer converts incident light into light with a wavelength corresponding to an optical transition from a quantum level of the conduction band of the superlattice semiconductor layer to a continuum level of the conduction band.
US09601642B1	CZTSe-based thin film and method for preparing the same, and solar cell using the same The present invention relates to a CZTSe-based composite thin film, a method for preparing the CZTSe-based composite thin film, a solar cell using the CZTSe-based composite thin film, and a method for preparing the solar cell using the CZTSe-based composite thin film.
US09601633B2	Semiconductor device An oxide semiconductor layer in which “safe” traps exist exhibits two kinds of modes in photoresponse characteristics. By using the oxide semiconductor layer, a transistor in which light deterioration is suppressed to the minimum and the electric characteristics are stable can be achieved. The oxide semiconductor layer exhibiting two kinds of modes in photoresponse characteristics has a photoelectric current value of 1 pA to 10 nA inclusive. When the average time τ1 until which carriers are captured by the “safe” traps is large enough, there are two kinds of modes in photoresponse characteristics, that is, a region where the current value falls rapidly and a region where the current value falls gradually, in the result of a change in photoelectric current over time.
US09601632B2	Semiconductor device and method for fabricating the same The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.
US09601630B2	Transistors incorporating metal quantum dots into doped source and drain regions Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the energy gap of the semiconductor crystal. In a first example, the quantum dots are incorporated into ion-doped source and drain regions. In a second example, the quantum dots are incorporated into epitaxially doped source and drain regions.
US09601624B2	SOI based FINFET with strained source-drain regions A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).
US09601622B2	Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.
US09601621B1	Semiconductor device including dual spacer and uniform epitaxial buffer interface of embedded SiGe source/drain A semiconductor device includes at least one semiconductor fin on an upper surface of a semiconductor substrate. The semiconductor fin includes a channel region formed of a first semiconductor material interposed between opposing embedded source/drain regions formed of a second semiconductor material different from the first semiconductor material. At least one gate stack is formed on the upper surface of the semiconductor substrate and wraps around the channel region. The embedded source/drain regions have a symmetrical shape and a uniform embedded interface.
US09601618B2	Semiconductor device A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and that extends in a first direction with a first insulating film around the fin-shaped semiconductor layer. A pillar-shaped semiconductor layer resides on the fin-shaped semiconductor layer. A width of the bottom of the pillar-shaped semiconductor layer is equal to a width of the top of the fin-shaped semiconductor layer. A gate insulating film is around the pillar-shaped semiconductor layer and a metal gate electrode is around the gate insulating film. A metal gate line is connected to the metal gate electrode, and a nitride film is on an entire top surface of the metal gate electrode and the metal gate line, except at a bottom of a contact.
US09601617B2	Fabrication of a transistor including a tunneling layer In a particular embodiment, an apparatus includes an electron tunnel structure. The electron tunnel structure includes a tunneling layer, a channel layer, a source layer, and a drain layer. The tunneling layer and the channel layer are positioned between the source layer and the drain layer. The transistor device further includes a high-k dielectric layer adjacent to the electron tunnel structure.
US09601609B2	Semiconductor device Characteristics of a semiconductor device are improved.A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, a gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.
US09601607B2	Dual mode transistor A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.
US09601604B2	Current switching transistor An electronic device and a method of fabricating an electronic device are disclosed. The device includes a body of semiconductor material, and a conductive material defining at least three conducting contacts to form respective terminals. The semiconductor material and the conducting contacts overlap at least partially to define the device, so that the electrical characteristics of the device between any pair of terminals correspond to those of a varistor. The body of semiconductor material may be a layer deposited by printing or coating. The varistor characteristics between each pair of terminals enable switching of an electrical current between one terminal and any two other terminals in such a manner that when there is a positive current into a first terminal, there is a negligible current through a second terminal at which a positive potential is applied and a positive current out of a third terminal which is held at a negative potential with respect to the second terminal. When there is a negative current outwards of the first terminal, there is a positive current into the second terminal and a negligible current through the third terminal.
US09601603B2	Method for manufacturing semiconductor device As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
US09601601B2	Method for manufacturing transistor A hydrogen barrier layer is selectively provided over an oxide semiconductor layer including hydrogen and hydrogen is selectively desorbed from a given region in the oxide semiconductor layer by conducting oxidation treatment, so that regions with different conductivities are formed in the oxide semiconductor layer. After that, a channel formation region, a source region, and a drain region can be formed with the use of the regions with different conductivities formed in the oxide semiconductor layer.
US09601598B2	Method of manufacturing a fin-like field effect transistor (FinFET) device A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary FinFET device includes a semiconductor substrate; a fin structure disposed over the semiconductor substrate; and a gate structure disposed over a portion of the fin structure. The gate structure traverses the fin structure and separates a source region and a drain region of the fin structure, the source and drain region defining a channel therebetween. The source and drain region of the fin structure include a strained source and drain feature. The strained source feature and the strained drain feature each include: a first portion having a first width and a first depth; and a second portion disposed below the first portion, the second portion having a second width and a second depth. The first width is greater than the second width, and the first depth is less than the second depth.
US09601597B2	Substantially planar electronic devices and circuits A method of manufacturing a substantially planar electronic device is disclosed. The method employs a resist having three different thicknesses used for defining different structures in a single masking step. Exemplary structures are substantially planar transistors having side-gates and diodes.
US09601580B2	Semiconductor device A semiconductor device includes a first transistor having a first conductivity type SiC layer, a second conductivity type SiC well region, a first conductivity type SiC first source region, a first conductivity type SiC first drain region, and a first gate electrode provided on the well region sandwiched between the first source region and the first drain region. The device includes a second transistor having a second conductivity type SiC second source region, a second conductivity type SiC second drain region provided on the SiC layer, and a second gate electrode provided on the SiC layer sandwiched between the second source region and the second drain region. There is an angle between a direction of a channel forming portion of first transistor and that of the second transistor. The device includes an element isolation region having a bottom positioned in the SiC layer.
US09601570B1	Structure for reduced source and drain contact to gate stack capacitance A structure of a semiconductor device is described. A device structure including a gate structure, a source region and a drain region is disposed on a first surface of a substrate. Contact holes are etched through the source and drain regions and through a first portion of the substrate. The contact holes are filled with a conductive material to produce contact studs coupled to the source and drain regions. A second portion of the substrate is removed. A surface of the contact studs is exposed through a second surface of the substrate opposite to the gate structure for connection to a wiring layer disposed over the second surface of the substrate.
US09601566B2	Semiconductor device and method for manufacturing the same A method for manufacturing a fin structure. The method includes: forming a first semiconductor layer and a second semiconductor layer sequentially on a substrate; patterning the second and first semiconductor layers to form an initial fin; selectively etching the first semiconductor layer of the initial fin so that the first semiconductor layer has a lateral recess; forming an isolation layer having a portion that fills the lateral recess, wherein the isolation layer, except the portion that fills the lateral recess, has a top surface lower than a top surface of the first semiconductor layer but higher than a bottom surface of the first semiconductor layer, and thus defines a fin above the isolation layer; and forming a gate stack intersecting the fin on the isolation layer.
US09601558B2	OLED backplate structure The present invention provides an OLED backplate structure. Multiple auxiliary conducting layers contacting the cathode are provided under the cathode of the OLED, which can diminish the electrical resistance of the cathode to enhance the conductivity of the cathode and to even the in plane voltages. The uniformity of the OLED display can be improved to prevent the uneven brightness issue and to decrease the thickness of the cathode for saving the production cost.
US09601555B2	Organic light emitting device and method for manufacturing the same Disclosed is an organic light emitting device (OLED) that may include a first electrode on a substrate, the first electrode having a pattern of a plurality of cells, with each cell defined with an emitting area and a non-emitting area; a second electrode facing the first electrode; an organic layer between the first electrode and the second electrode; a short-circuit preventing layer contacting at least a portion of the first electrode; and an auxiliary electrode on the short-circuit preventing layer in the non-emitting area of each cell, wherein an aperture ratio of the short-circuit preventing layer and the auxiliary electrode in each cell is 30% or more.
US09601552B2	Organic light emitting display panel and method of manufacturing the same An organic light emitting display panel and associated methods, the panel including a substrate; an organic light emitting diode (OLED) on the substrate; and an encapsulation member to separate the OLED from an external environment, wherein the OLED includes a first electrode on the substrate; a pixel defining layer exposing the first electrode and including a flat planar surface and an inclined planar surface extending from the flat planar surface such that the inclined planar surface overlaps an edge of the first electrode; an organic layer, the organic layer including a first region on the first electrode and a second region on the inclined planar surface; and a second electrode on the organic layer, and wherein, in the second region, a thickness of the organic layer is decreased along a direction extending away from the first region.
US09601551B2	Organic light emitting display An organic light emitting display includes a data driving unit connected to data lines, a scan driving unit connected to scan lines, and a display panel having pixel groups arranged in a region where the data lines and scan lines intersect. A pixel group includes a first pixel unit having a first organic light emitting diode configured to emit light of a first color and a second pixel unit having a second organic light emitting diode configured to emit light of second color. The first pixel unit further includes an organic light emitting diode configured to emit light of a third color and the second pixel unit further includes an organic light emitting diode configured to emit light of the third color.
US09601547B2	Solid-state image pickup device and electronic apparatus A solid-state image pickup device includes at least two stacked first and second photoelectric conversion sections in each of a plurality of pixels. Sensitivity of the first photoelectric conversion section to a light incident angle is equivalent to sensitivity of the second photoelectric conversion section to a light incident angle, for each of the pixels.
US09601544B2	Three-dimensional magnetic memory element The disclosed technology relates to a magnetic memory device. In one aspect, the device includes a first electrode comprising a conductive pillar formed over the substrate and elongated in a vertical direction crossing a lateral surface of the substrate. The device additionally includes a second electrode extending in a lateral direction crossing the first direction, where the second electrode intersects the first electrode. The device additionally includes a magnetic tunnel junction (MTJ) formed at an intersection between the first electrode and the second electrode, where the MTJ continuously surrounds the first electrode. The MTJ includes a reference layer continuously surrounding the pillar of the first electrode, a free layer continuously surrounding the free layer, and a dielectric tunnel barrier interposed between the reference layer and the free layer.
US09601539B2	Solid-state imaging device, method of manufacturing the same, and electronic equipment A solid state imaging device including a semiconductor layer comprising a plurality of photodiodes, a first antireflection film located over a first surface of the semiconductor layer, a second antireflection film located over the first antireflection film, a light shielding layer having side surfaces which are adjacent to at least one of first and the second antireflection film.
US09601535B2	Semiconducator image sensor having color filters formed over a high-K dielectric grid The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface, a plurality of sensor elements disposed at the front surface of the substrate. Each of the plurality of sensor elements is operable to sense radiation projected towards the back surface of the substrate. The image sensor also includes a high-k dielectric grid disposed over the back surface of the substrate. The high-k dielectric grid has a high-k dielectric trench and sidewalls. The image sensor also includes a color filter and a microlens disposed over the high-k dielectric grid.
US09601534B2	Solid state image sensor, method of manufacturing solid state image sensor, and image capturing system The present invention provides a solid state image sensor including a pixel array having a plurality of pixels arranged therein, each of the plurality of pixels including a photoelectric conversion device and a microlens configured to guide incident light to the photoelectric conversion device, the microlens having a lower surface, on an exit side of the incident light, which has a convex shape with respect to the photoelectric conversion device, with a vertex of the convex shape shifting from a center position of the microlens to a central side of the pixel array.
US09601533B2	Solid-state imaging apparatus, method of manufacturing the same, and camera A method of manufacturing a solid-state imaging apparatus, comprising preparing a semiconductor substrate including a photoelectric conversion portion and a structure which includes an insulating member formed on the photoelectric conversion portion and a wiring pattern formed in the insulating member, forming a film made of SiC and/or SiCN on the structure, forming an opening immediately above the photoelectric conversion portion by removing part of the film and part of the insulating member, and depositing a member in the opening and on the film, and forming a light-guide portion by polishing the member so as to expose the film.
US09601528B2	Manufacturing method of array substrate The present invention provides a manufacturing method of an array substrate, comprising steps of: forming a gate and a gate line on a substrate; forming a gate insulating layer on the gate and the gate line; forming a pixel electrode on the gate insulating layer; and forming a first connecting via in a portion of the gate insulating layer in a non-display region and corresponding to the gate line, wherein the first connecting via is configured to connect a scanning signal trace to the gate line.
US09601525B2	Semiconductor device Solved is a problem of attenuation of output amplitude due to a threshold value of a TFT when manufacturing a circuit with TFTs of a single polarity. In a capacitor (105), a charge equivalent to a threshold value of a TFT (104) is stored. When a signal is inputted thereto, the threshold value stored in the capacitor (105) is added to a potential of the input signal. The thus obtained potential is applied to a gate electrode of a TFT (101). Therefore, it is possible to obtain the output having a normal amplitude from an output terminal (Out) without causing the amplitude attenuation in the TFT (101).
US09601524B2	Display device and method of manufacturing the same A display device is disclosed. In one aspect, the device includes a plurality of pixels. Each of the pixels includes a first thin-film transistor (TFT) formed over a substrate and comprising gate electrode, a source electrode, and a drain electrode. Each pixel also includes a storage capacitor formed over the substrate, wherein the storage capacitor includes first and second electrodes, and a dielectric layer interposed between the first and second electrodes. The first electrode, the dielectric layer, and the second electrode have substantially the same pattern.
US09601515B2	Semiconductor device and manufacturing method thereof A high reliability semiconductor display device is provided. A semiconductor layer in the semiconductor display device has a channel forming region, an LDD region, a source region, and a drain region, and the LDD region overlaps a first gate electrode, sandwiching a gate insulating film.
US09601513B1	Subsurface wires of integrated chip and methods of forming Various embodiments include methods and integrated circuit structures. One method includes masking a structure with a mask to cover at least a portion of the structure under the mask, selectively implanting a material through a semiconductor layer and into a buried insulator layer forming an implant region. The implant region is substantially parallel to and below an upper surface of the structure. The method may also include masking an additional portion of the structure; etching a set of access ports though the semiconductor layer and partially through the insulator layer into the implant region; etching at least one tunnel below the upper surface of the structure in the implant region using the set of access; and depositing a conductor into the at least one tunnel and the set of access ports.
US09601509B1	Semiconductor device having slit between stacks and manufacturing method of the same The present disclosure may provide a semiconductor device having a three-dimensional memory device with improved performance and reliability. The device may include a pipe gate having a pipe channel film embedded in the pipe gate. The device may include source-side channel and drain-side channel films coupled respectively to both ends of the pipe channel film. The device may include interlayer insulation films and conductive patterns alternately stacked and disposed over the pipe gate, the alternately stacked interlayer insulation films and conductive patterns surrounding the source-side channel film and the drain-side channel film. The device may include a slit disposed between the drain-side channel film and the source-side channel film and dividing the alternately stacked interlayer insulation films and conductive patterns into a source-side stack and a drain-side stack, the slit having a round shape at a bottom of the slit adjacent to the pipe gate.
US09601505B2	Semiconductor device A semiconductor device includes a first selection gate insulating film surrounding a first pillar-shaped semiconductor layer, a first selection gate surrounding the first selection gate insulating film, a first bit line connected to the first pillar-shaped semiconductor layer, a layer including a first charge storage layer which surrounds a second pillar-shaped semiconductor layer, a first control gate surrounding the layer, a layer including a second charge storage layer which surrounds the second pillar-shaped semiconductor layer, a second control gate surrounding the layer, a first lower-portion internal line connecting the first and second pillar-shaped semiconductor layers, a layer including a third charge storage layer, a third control gate, a layer including a fourth charge storage layer, a fourth control gate, a second selection gate insulating film, a second selection gate, a first source line, and a second lower-portion internal line.
US09601504B2	Semiconductor device and method of manufacturing the same A semiconductor device according to an embodiment of the invention includes a pipe channel layer including a first portion and a second portion protruding from the first portion, first channel pillars protruding from the second portion of the pipe channel layer, and second channel pillars protruding from the first portion of the pipe channel layer.
US09601503B2	Nonvolatile semiconductor memory device and method for manufacturing same A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
US09601502B2	Multiheight contact via structures for a multilevel interconnect structure A recessed region can be formed on a semiconductor substrate, and peripheral semiconductor devices can be formed on a recessed horizontal surface of the semiconductor substrate. An alternating stack of insulating layers and sacrificial material layers are formed over the semiconductor substrate, and memory stack structures are formed therethrough. Contact openings extending to sacrificial material layers located at different depths can be formed by sequentially exposing a greater number of openings in a mask layer by iterative alternation of trimming of a slimming layer over the mask layer and an anisotropic etch that recesses pre-existing contact openings by one level. Electrically conductive via structures extending to electrically conductive electrodes located at different level can be provided with self-aligned insulating liners.
US09601497B1	Static random access memory and method of manufacturing the same A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second pull-down transistor, and first and second pass-gate transistors. A first buried contact electrically connects a drain region of the first pull-up transistor and gate electrodes of the second pull-up transistor and the second pull-down transistor, and includes a first metal layer formed in a region confined by spacers of a first gate layer and a first electrically conductive path formed at a level below the spacers. A second buried contact electrically connects a drain region of the second pull-up transistor and gate electrodes of the first pull-up transistor and the first pull-down transistor, and includes a second metal layer formed in a region confined by spacers of a second gate layer and a second electrically conductive path formed at the level below the spacers.
US09601496B2	Semiconductor device having sacrificial layer pattern with concave sidewalls and method fabricating the same In a method of fabricating a semiconductor device, sacrificial layer patterns are formed by leaving portions of sacrificial layers, instead of completely removing the sacrificial layers. Thus, the reliability of the semiconductor device may be increased, and the process of manufacturing the same may be simplified.
US09601495B2	Three-dimensional semiconductor device with co-fabricated adjacent capacitor A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by isolation material, each fin including a source region, a drain region and a channel region therebetween, a first gate and spacers over a portion of each fin, and a second gate and spacers, the second gate encompassing a common end portion of each fin. The first gate and corresponding source and drain regions act as an access transistor, and the second gate and common end portion(s) of the fin(s) act as a storage capacitor, and a top surface of the second gate acts as a plate for the storage capacitor, when multiple cells are arranged in an array.
US09601492B1	FinFET devices and methods of forming the same FinFET devices and methods of forming the same are disclosed. One of the FinFET devices includes a substrate, multiple gates and an insulating wall. The substrate is provided with multiple fins extending in a first direction. The multiple gates extending in a second direction different from the first direction are provided respectively across the fins. Two of the adjacent gates are arranged end to end. The insulating wall extending in the first direction is located between the facing ends of the adjacent gates and is in physical contact with a gate dielectric material of each of the adjacent gates.
US09601490B2	FinFET work function metal formation An improved method and structure for fabrication of replacement metal gate (RMG) field effect transistors is disclosed. P-type field effect transistor (PFET) gate cavities are protected while N work function metals are deposited in N-type field effect transistor (NFET) gate cavities.
US09601483B2	Semiconductor device A semiconductor device according to an embodiment includes a normally-off transistor having a first drain, a first source electrically connected to a source terminal, and a first gate electrically connected to a gate terminal, a normally-on transistor having a second gate, a second source electrically connected to the first drain, and a second drain electrically connected to a voltage terminal, a first capacitor provided between the gate terminal and the second gate, a first diode having a first anode electrically connected to the first capacitor and the second gate, and a first cathode electrically connected to the first source, a coil component provided between the voltage terminal and the second drain, and a second diode having a second anode electrically connected to the first drain and the second source, and a second cathode electrically connected to the coil component and the voltage terminal.
US09601479B2	Protection circuit, circuit employing same, and associated method of operation A buffer or voltage protection circuit, a circuit including same, and an associated method of operation are disclosed. In one example embodiment, the integrated circuit includes a first input terminal, a first circuit portion having a second input terminal, and a second circuit portion. The second circuit portion includes a transistor device having first, second, and third ports, where the first and second ports are respectively electrically coupled to the first input terminal and second input terminal, respectively. Additionally, the second circuit portion also includes a diode-type device that is electrically coupled between the third port and either a power source or a power input terminal, and a buffer/driver circuit and a capacitor coupled in series between the third and second ports. The second circuit portion operates to prevent the second input terminal from being exposed to an undesirably-high voltage level.
US09601478B2	Oxide definition (OD) gradient reduced semiconductor device An integrated circuit (IC) semiconductor device has a high oxide definition (OD) density region, a low OD density region adjacent to the high OD density region, and dummy cells in the high OD density region and the low OD density region to smooth a density gradient between the high OD density region and the low OD density region.
US09601477B2	Integrated circuit having spare circuit cells Aspects of the disclosure include an integrated circuit that includes a plurality of functional circuit cells and a plurality of inactive spare functional circuit cells. Ones of the functional circuit cells respectively includes a set of first electrically interconnected transistors that define a first logic component and a first power rail configured to carry a first supply voltage. Ones of the inactive spare functional circuit cells respectively includes a set of second electrically interconnected transistors configured to define a second logic component and a second power rail configured to carry the first supply voltage. The set of electrically interconnected transistors is interconnected through a second set of conductive lines formed in the first conductive layer. The set of second electrically interconnected transistors is electrically disconnected from the second power rail.
US09601474B2	Electrically stackable semiconductor wafer and chip packages A wafer-leveled chip packaging method, comprising the steps of: providing a wafer; attaching at least one first chip to the wafer; forming a first insulating layer on the wafer; forming a plurality of first conductive vias penetrating the first insulating layer, wherein parts of the first conductive vias are electrically connected with the first chip; forming a conductive pattern layer on the surface of the first insulating layer wherein the conductive pattern layer is electrically connected with the first conductive vias; forming a plurality of through holes penetrating the wafer; filling a second insulating layer in the through holes; and forming a plurality of second conductive vias in the second insulating layer, wherein the second conductive vias are electrically connected with the first conductive vias.
US09601469B2	Package-on-package modules, electronic systems including the same, and memory cards including the same Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package includes a lower substrate and a lower chip disposed over a top surface of the lower substrate. The upper package includes an upper substrate, a plurality of upper chips disposed over a top surface of the upper substrate, and an upper molding member disposed over the plurality of upper chips. The upper molding member is divided into at least two parts which are separated from each other by a trench. Related memory cards and related electronic systems are also provided.
US09601462B2	Semiconductor device and method of forming UBM structure on back surface of TSV semiconductor wafer A semiconductor device has a plurality of conductive vias formed through the semiconductor die with a first insulating layer around the conductive vias. A recess is formed in the first insulating layer around the conductive vias by LDA. A portion of the semiconductor wafer is removed by LDA after forming the recess in the first insulating layer so that the conductive vias extend above a surface of the semiconductor wafer. The first insulating layer extends to the surface of the semiconductor wafer or above the surface of the semiconductor wafer. A second insulating layer is formed over the surface of the semiconductor wafer and conductive vias. A first portion of the second insulating layer is removed by LDA, while leaving a second portion of the second insulating layer over the surface of the semiconductor wafer around the conductive vias. An electroless plated bump is formed over the conductive vias.
US09601458B2	Stacked semiconductor package including connections electrically connecting first and second semiconductor packages A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.
US09601447B2	Semiconductor device including plural semiconductor chips stacked on substrate A semiconductor chip at least includes a row of first electrode pad group, which includes at least one first independent electrode pad and multiple first common electrode pads. The interval between the first independent electrode pad and an electrode pad adjacent thereto is defined as “first pitch”, and the interval between adjacent electrode pads making up the multiple first common electrode pads is defined as “second pitch”. The first pitch is determined to be larger than the second pitch.
US09601446B2	Method of fabricating a bond pad structure A method of forming a bond pad structure is provided. The method includes forming a first conductive layer over a substrate and depositing a first dielectric layer over the first conductive layer. The first dielectric layer is patterned to form a contiguous planar path substantially parallel to a top surface of the substrate. Patterning the first dielectric layer includes defining a dielectric region of the first dielectric layer surrounded by a portion of the contiguous planar path, and forming a first via hole in the dielectric region. The contiguous planar path and the via hole are filled with a conductive material. The conductive material in the contiguous planar path forms a second conductive layer, and the contiguous planar path extends from a first lateral side wall of the second conductive layer to a second lateral sidewall of the second conductive layer. A bond pad is formed over the second conductive layer, and the bond pad is electrically connected to the second conductive layer.
US09601443B2	Test structure for seal ring quality monitor A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
US09601438B2	Semiconductor device and method for manufacturing the same According to one embodiment, there is disclosed a semiconductor device which has a wiring substrate, a semiconductor element mounted on the wiring substrate, a molding resin which seals the semiconductor element, and a shield layer provided on the molding resin, wherein the molding resin has a marking portion by laser irradiation on a surface, and the shield layer is provided on the molding resin having the marking portion.
US09601435B2	Semiconductor package with embedded components and method of making the same A semiconductor package may include a lower substrate with one or more electronic components attached to a surface thereof and an upper substrate with one or more cavities wherein the upper substrate is attached to the lower substrate at a plurality of connection points with the one or more electronic components fitting within a single cavity or a separate cavity for each component that allow the overall form factor of the semiconductor package to remain smaller. The plurality of connection points provide a mechanical and electrical connection between the upper and lower substrate and may include solder joints there between as well as conductive filler particles that create an adhesive reinforcement matrix when compressed for assembly.
US09601434B2	Semiconductor device and method of forming openings through insulating layer over encapsulant for enhanced adhesion of interconnect structure A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A first insulating layer is formed over a portion of the encapsulant within an interconnect site outside a footprint of the semiconductor die. An opening is formed through the first insulating layer within the interconnect site to expose the encapsulant. The opening can be ring-shaped or vias around the interconnect site and within a central region of the interconnect site to expose the encapsulant. A first conductive layer is formed over the first insulating layer to follow a contour of the first insulating layer. A second conductive layer is formed over the first conductive layer and exposed encapsulant. A second insulating layer is formed over the second conductive layer. A bump is formed over the second conductive layer in the interconnect site.
US09601430B2	Semiconductor device structure and method for forming the same A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate. The semiconductor device structure includes a dielectric layer positioned on the semiconductor substrate. The dielectric layer has a first recess. The semiconductor device structure includes a conductive structure filling the first recess. The conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer is positioned over an inner wall and a bottom of the first recess. The first conductive layer has a second recess in the first recess. The second conductive layer fills the second recess. The first conductive layer and the second conductive layer include cobalt. The second conductive layer further includes at least one of sulfur, chlorine, boron, phosphorus, or nitrogen.
US09601429B2	Semiconductor device, electronic component, and electronic device including memory cell comprising first transistor, second transistor and capacitor A highly reliable semiconductor device. In a configuration where a precharged source line is discharged to a bit line by establishing electrical continuity between the source line and the bit line through a transistor to read a potential retained at a gate of the transistor, the potential of the bit line is switched in accordance with a change in potential of the source line due to the discharge. With this configuration, the voltage between the source and drain of the transistor can be kept lower than a predetermined voltage by discharge. Accordingly, the source-drain voltage of the transistor can be kept lower than its breakdown voltage, so that the semiconductor device can have high reliability.
US09601427B2	Semiconductor device including plural types of resistors and manufacturing method of the semiconductor device A semiconductor device (1) includes a first metal wiring layer (11) formed on a substrate (10), an interlayer insulating film (12) formed on the first metal wiring layer (11), a second metal wiring layer (23) formed on the interlayer insulating film (12), a first resistor including a first resistance metal film (14a) formed between the first metal wiring layer (11) and the second metal wiring layer (23), a first insulating film (15a) formed on the first resistance metal film (14a), and a second resistance metal film (16a) formed on the first insulating film (15a), and a second resistor including a first resistance metal film (14b) formed between the first metal wiring layer (11) and the second metal wiring layer (23), a first insulating film (15b) formed on the first resistance metal film (14b), and a second resistance metal film (16b) formed on the first insulating film (15b).
US09601424B2	Interposer and methods of forming and testing an interposer A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.
US09601423B1	Under die surface mounted electrical elements A laminate includes a buildup layer having a top and a bottom and a solder mask contacting the top. The laminate also includes a circuit element disposed on the top of the buildup layer and at least partially covered by the solder mask, the circuit element including a first via formed therein that allows for a power signal provided to an underside of the circuit element to be provided to a first connection on a top of the circuit element.
US09601418B2	Stacked half-bridge package According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source.
US09601415B2	Method of manufacturing semiconductor device and semiconductor device In a method of manufacturing a semiconductor device according to an embodiment, a lead frame is provided, the lead frame having a trench part formed thereon so as to communicate bottom surfaces of a first lead and a second lead, which are coupled to each other between device regions adjacent to each other. Then, after a part of a coupling part between the first and second leads is cut by using a first blade, metal wastes formed inside the trench part are removed. Then, after the metal wastes are removed, a metal film is formed on exposed surfaces of the first and second leads by a plating method, and then, a remaining part of the coupling part between the first and second leads is cut by using a second blade. At this time, the cutting is performed so that the second blade does not contact the trench part.
US09601413B2	Cavity package with die attach pad A cavity package is provided. The package can include a metal leadframe and a substrate attached to an interposer formed as part of the leadframe. The substrate typically has a coefficient of thermal expansion matched to the coefficient of thermal expansion of a semiconductor device to be affixed to the substrate. The semiconductor device is typically attached to an exposed top surface of the substrate. The cavity package also includes a plastic portion molded to the leadframe forming a substrate cavity. The substrate cavity allows access to the exposed top surface of the substrate for affixing the semiconductor device. The cavity package also include a connective element for grounding a lid through an electrical path from the lid to the interposer.
US09601412B2	Three-dimensional package structure The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral surface. The conductive pattern disposed on the top surface of the first conductive element. A second conductive element is disposed on the conductive pattern. The first conductive element is electrically connected to the conductive pattern, and the second conductive element is electrically connected to the conductive pattern. In one embodiment, the shielding layer is a portion of the patterned conductive layer.
US09601411B2	Semiconductor structure A semiconductor structure and a method for fabricating the same are provided. The semiconductor structure includes a wafer substrate having a top surface and a bottom surface, and a conductive pillar in the wafer substrate defined by a deep trench insulator through the top surface and the bottom surface of the wafer substrate. The method for fabricating the semiconductor structure includes following steps. A deep trench is formed from a top surface of a wafer substrate to define a conductive region in the wafer substrate. The conductive region is doped with a dopant. The deep trench is filled with an insulation material to form a deep trench insulator. And the wafer substrate is thinned from a bottom surface of the wafer substrate to expose the deep trench insulator and isolate the conductive region to form a conductive pillar.
US09601410B2	Semiconductor device and method A semiconductor device and method are provided which utilizes a single mask to form openings for both a through substrate via as well as for a through dielectric via. In an embodiment a contact etch stop layer is deposited over and between a first semiconductor device and a second semiconductor device. A dielectric material is deposited over the contact etch stop layer between the first semiconductor device and the second semiconductor device. The different materials of the contact etch stop layer and the dielectric material is utilized such that a single mask may be used to form a through substrate via through the first semiconductor device and also to form a through dielectric via through the dielectric material.
US09601405B2	Semiconductor package with an enhanced thermal pad A semiconductor package having a substrate, a thermal pad, and a semiconductor die is disclosed. The thermal pad may have a heat conductive body extending through the substrate. The semiconductor die may be disposed on the thermal pad and in thermal communication with the thermal pad. The thermal pad of the semiconductor package may also have an interlock structure. The interlock structure may provide a mechanical interlock between the thermal pad and the substrate. In addition, a wireless communication device is also disclosed.
US09601403B2	Electronic package and fabrication method thereof An electronic package is provided, which includes: a first circuit structure; at least first electronic element disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; a first encapsulant encapsulating the first electronic element and the first conductive element; and a second circuit structure formed on the first encapsulant and electrically connected to the first conductive element. By directly disposing the electronic element having high I/O functionality on the circuit structure, the invention eliminates the need of a packaging substrate having a core layer and thus reduces the thickness of the electronic package. The invention further provides a method for fabricating the electronic package.
US09601402B2	Package apparatus and manufacturing method thereof A package apparatus comprises a first wiring layer, a metal layer, a conductive pillar layer, a passive component, a first molding compound layer, a second wiring layer, and a protection layer. The first wiring layer has a first surface and a second surface opposite to each other. The metal layer is disposed on the first surface of the first wiring layer. The conductive pillar layer is disposed on the second surface of the first wiring layer. The passive component is disposed on the second surface of the first wiring layer. The first molding compound layer is disposed within a part of the zone of the first wiring layer and the conductive pillar layer. The second wiring layer is disposed on the first molding compound layer and one end of the conductive pillar layer. The protection layer is disposed on the first molding compound layer and the second wiring layer.
US09601393B2	Selecting one or more parameters for inspection of a wafer Computer-implemented methods, computer-readable media, and systems for selecting one or more parameters for inspection of a wafer are provided.
US09601391B2	Mechanical stress measurement during thin-film fabrication A method and system are provided for determining mechanical stress experienced by a film during fabrication thereof on a substrate positioned in a vacuum deposition chamber. The substrate's first surface is disposed to have the film deposited thereon and the substrate's opposing second surface is a specular reflective surface. A portion of the substrate is supported. An optical displacement sensor is positioned in the vacuum deposition chamber in a spaced-apart relationship with respect to a portion of the substrate's second surface. During film deposition on the substrate's first surface, displacement of the portion of the substrate's second surface is measured using the optical displacement sensor. The measured displacement is indicative of a radius of curvature of the substrate, and the radius of curvature is indicative of mechanical stress being experienced by the film.
US09601390B2	Silicon germanium fin formation via condensation A method of forming a finFET device comprises forming a fin in a silicon layer of a substrate, forming a hardmask layer on a top surface of the fin, forming an insulating layer over the fin and the hardmask layer, removing a portion of the insulating layer to expose a portion of the hardmask layer, removing the exposed portion of the hardmask layer to form a cavity that exposes a portion of the silicon layer of the fin, epitaxially growing a silicon germanium (SiGe) material on exposed portions of the silicon layer of the fin in the cavity, and annealing the grown SiGe to drive germanium atoms into the silicon layer of the fin.
US09601384B2	Method of forming a semiconductor device comprising first and second nitride layers A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.
US09601380B2	Fin end spacer for preventing merger of raised active regions After formation of gate structures over semiconductor fins and prior to formation of raised active regions, a directional ion beam is employed to form a dielectric material portion on end walls of semiconductor fins that are perpendicular to the lengthwise direction of the semiconductor fins. The angle of the directional ion beam is selected to be with a vertical plane including the lengthwise direction of the semiconductor fins, thereby avoiding formation of the dielectric material portion on lengthwise sidewalls of the semiconductor fins. Selective epitaxy of semiconductor material is performed to grow raised active regions from sidewall surfaces of the semiconductor fins. Optionally, horizontal portions of the dielectric material portion may be removed prior to the selective epitaxy process. Further, the dielectric material portion may optionally be removed after the selective epitaxy process.
US09601378B2	Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same A method of forming a semiconductor structure includes providing a semiconductor substrate, forming at least one precursor semiconductor fin from the semiconductor substrate, etching through at least a portion of the at least one precursor semiconductor fin to form at least one patterned precursor semiconductor fin having a gap therein. The at least one patterned precursor semiconductor fin includes a first vertical surface and a second vertical surface with the gap therebetween. In addition, the method further includes forming a semiconductor material in the gap of the at least one patterned precursor semiconductor fin, in which the first vertical surface and the second vertical surface laterally surround the semiconductor material, and transforming the at least one patterned precursor semiconductor fin into at least one semiconductor fin including the semiconductor material therein.
US09601376B2	Semiconductor device and method of manufacturing a semiconductor device having a glass piece and a single-crystalline semiconductor portion A semiconductor device includes a glass piece and an active semiconductor element formed in a single-crystalline semiconductor portion. The single-crystalline semiconductor portion has a working surface, a rear side surface opposite to the working surface and an edge surface connecting the working and rear side surfaces. The glass piece has a portion extending along and in direct contact with the edge surface of the single-crystalline semiconductor portion.
US09601374B2	Semiconductor die assembly A semiconductor die assembly having a solderball wirebonded to a substrate. As an example, the semiconductor die assembly may include the solderball attached to a bond pad on a face surface of a memory die. A non-face surface of the memory die can be attached to the substrate. A wire can be wirebonded to the solderball at a first end of the wire and connected to the substrate at a second end of the wire.
US09601373B2	Semiconductor device and method for manufacturing the same A method for manufacturing a semiconductor device is provided. The method includes the following operations: (i) forming a transistor having a source, a drain and a gate on a semiconductor substrate; (ii) forming a conductive contact located on and in contact with at least one of the source and the drain; and (iii) forming a capacitor having a first electrode and a second electrode on the semiconductor substrate, in which at least one of the first and second electrodes is formed using front-end-of line (FEOL) processes or middle-end-of line (MEOL) processes.
US09601370B2	Nonvolatile semiconductor memory device and method of manufacturing the same The memory cell array includes a memory string and a select transistor. The memory string includes plural memory cells connected in series, the memory string being formed to extend in a first direction as a lengthwise direction. The select transistor is connected to one end of the memory string. In the wiring section, a conductive layer and an interlayer insulating layer are laminated alternately to form plural layers. The conductive layer functions as a gate electrode of the memory cells and the select transistor. One select transistor includes plural conductive layers, and the plural conductive layers are connected in common by a common first contact. The plurality of the conductive layers and the first contact include a barrier metal formed in a periphery thereof. The plurality of the conductive layers and the first contact are in contact without the barrier metal therebetween at a boundary thereof.
US09601366B2	Trench formation for dielectric filled cut region A method for forming a gate cut region includes forming a tapered profile gate line trench through a hard mask, a dummy layer and a dummy dielectric formed on a substrate, forming a dummy gate dielectric and a dummy gate conductor in the trench and planarizing a top surface to reach the hard mask. The dummy gate conductor is patterned to form a cut trench in a cut region. The dummy gate conductor is recessed, and the cut trench is filled with a first dielectric material. The dummy layer is removed and spacers are formed. A gate line is opened up and the dummy gate conductor is removed from the gate line trench. A gate dielectric and conductor are deposited, and a gate cap layer provides a second dielectric that is coupled to the first dielectric material in the cut trench to form a cut last structure.
US09601363B2	Thin substrate electrostatic chuck system and method In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate attached to an electrically insulating carrier; and an AC power supply electrically coupled to the electrostatic chuck.
US09601362B2	High speed substrate aligner apparatus A substrate aligner providing minimal substrate transporter extend and retract motions to quickly align substrate without back side damage while increasing the throughput of substrate processing. In one embodiment, the aligner having an inverted chuck connected to a frame with a substrate transfer system capable of transferring substrate from chuck to transporter without rotationally repositioning substrate. The inverted chuck eliminates aligner obstruction of substrate fiducials and along with the transfer system, allows transporter to remain within the frame during alignment. In another embodiment, the aligner has a rotatable sensor head connected to a frame and a substrate support with transparent rest pads for supporting the substrate during alignment so transporter can remain within the frame during alignment. Substrate alignment is performed independent of fiducial placement on support pads. In other embodiments the substrate support employs a buffer system for buffering substrate inside the apparatus allowing for fast swapping of substrates.
US09601357B2	Substrate processing device and substrate processing method A substrate processing apparatus and method includes, a plate that has a size equal to or larger than a principal face of the substrate, and has a horizontal and flat liquid holding face opposing the principal face of the substrate from below. A processing liquid supply unit supplies a processing liquid to the liquid holding face. A control unit controls the processing liquid supply unit and a movement unit to supply the processing liquid to the liquid holding face to form a processing liquid film, a contact step of bringing the principal face of the substrate and the liquid holding face close to each other to bring the principal face of the substrate into contact with the processing liquid film, and a liquid contact maintenance step of maintaining the processing liquid in contact with the principal face of the substrate.
US09601353B2	Packages with molding structures and methods of forming the same A method includes molding a device die in a molding material, wherein a metal pillar of the device die is exposed through a surface of the molding material. A substrate is adhered to the molding material. The substrate includes a redistribution layer that further includes redistribution lines. A plating is performed to fill a through-opening in the substrate to form a through-via. The through-via is plated on the metal pillar of the device die. An electrical connector is formed to electrically couple to the through-via.
US09601350B2	Bonding-substrate fabrication method, bonding substrate, substrate bonding method, bonding-substrate fabrication apparatus, and substrate assembly [Problem] To provide a substrate bonding technique having a wide range of application. [Solution] A silicon thin film is formed on a bonding surface, and the interface with the substrate is surface-treated using energetic particles/metal particles.
US09601349B2	Etching method The invention is directed to a method for patterning a material layer. The method comprises steps of providing a material layer having a first hard mask layer and a second hard mask layer successively formed thereon and then patterning the second hard mask layer. Thereafter, an etching process is performed to pattern the first hard mask layer by using the patterned second hard mask layer as a mask, and the etching process is performed with a power of about 1000 W. Next, the material layer is patterned by using the patterned first hard mask layer as a mask.
US09601343B2	Semiconductor device manufacturing method In a semiconductor device manufacturing method, on a film to be processed, a mask material film is formed which has pattern openings for a plurality of contact patterns and connection openings for connecting adjacent pattern openings in such a manner that the connection between them is constricted in the middle. Then, a sidewall film is formed on the sidewalls of the individual openings in the mask material film, thereby not only making the diameter of the pattern openings smaller but also separating adjacent pattern openings. Then, the film to be processed is selectively etched with the mask material film and sidewall film as a mask, thereby making contact holes.
US09601341B2	Method of etching A method of etching a feature in a substrate includes forming a mask structure over the substrate, the mask structure defining at least one re-entrant opening, etching the substrate through the opening to form the feature using a cyclic etch and deposition process, and removing the mask.
US09601340B2	Electronic device having quantum dots and method of manufacturing the same Provided are electronic devices having quantum dots and methods of manufacturing the same. An electronic device includes a first nanorod, a quantum dot disposed on an upper surface of the first nanorod, and a second nanorod that covers a lateral surface of the first nanorod and the quantum dot. The first nanorod and the second nanorod are of opposite types.
US09601337B2	Manufacturing method of graphene modulated high-K oxide and metal gate MOS device A manufacturing method of a graphene modulated high-k oxide and metal gate Ge-based MOS device, which comprises the following steps: 1) introducing a graphene thin film on a Ge-based substrate; 2) conducting fluorination treatment to the graphene thin film to form fluorinated graphene; 3) activating the surface of the fluorinated graphene by adopting ozone plasmas, and then forming a high-k gate dielectric on the surface of the fluorinated graphene through an atomic layer deposition technology; and 4) forming a metal electrode on the surface of the high-k gate dielectric. Since the present invention utilizes the graphene as a passivation layer to inhibit the formation of unstable oxide GeOx on the surface of the Ge-based substrate and to stop mutual diffusion between the gate dielectric and the Ge-based substrate, the interface property between Ge and the high-k gate dielectric layer is improved. The fluorinated graphene can enable the graphene to become a high-quality insulator on the basis of keeping the excellent property of the graphene, so that the influence thereof on the electrical property of the Ge-based device is reduced. By adopting the ozone plasmas to treat the Ge-based graphene and then by adopting the atomic layer deposition technology, an ultrathin Hf-based high-k gate dielectric layer can be obtained.
US09601336B2	Trench field-effect device and method of fabricating same The present invention provides a method of fabricating a trench field-effect device. The method includes: providing a substrate including an epitaxial layer formed on a semiconductor substrate of the substrate and a trench formed in the epitaxial layer; forming a sacrificial dielectric layer on a bottom and a sidewall of the trench; forming a heavily-doped polysilicon region at the bottom, and removing part of the sacrificial dielectric layer not covered by the heavily-doped polysilicon region to expose an epitaxial layer of the sidewall; and oxidizing the heavily-doped polysilicon region and the epitaxial layer simultaneously and forming a thick oxide layer and a trench sidewall gate dielectric layer synchronously on the bottom and the sidewall, respectively; wherein thickness of the thick oxide layer is greater than that of the trench sidewall gate dielectric layer. The method is simple, and figure of merit of the fabricated trench field-effect device is reduced.
US09601331B2	Pattern forming method and manufacturing method of semiconductor device A pattern forming method includes forming a spin on dielectric film on a substrate, washing the spin on dielectric film by using a washing liquid, drying a surface of the spin on dielectric film after the washing, forming a photosensitive film on the dried coating type insulation film, emitting energy rays to a predetermined position of the photosensitive film in order to form a latent image on the photosensitive film, developing the photosensitive film in order to form a photosensitive film pattern which corresponds to the latent image, and processing the spin on dielectric film with the photosensitive film pattern serving as a mask.
US09601330B2	Plasma processing device, and plasma processing method To provide a plasma processing device and a plasma processing method capable of generating plasma stably and efficiently and processing the entire desired treated region of a substrate efficiently for a short period of time.
US09601324B2	Method of making wafer assembly A method including bonding a process wafer having integrated circuits and a carrier wafer having at least one alignment mark to form a wafer assembly. The method further includes aligning the wafer assembly using the at least one alignment mark of the carrier wafer.
US09601321B2	Mass spectrometer and method A measurement state in a mass spectrometer device is determined so that the measurement method for the next round of measurement can be automatically determined. The mass spectrometer device (1) is provided with: a first calculation unit (6) that calculates the total amount of ion in a mass spectrum; a second calculation unit (6) that calculates the half-value width of a representative peak selected from peaks appearing in the mass spectrum; and a control unit (7) that determines the measurement method for use in the next round of measurement on the basis of the total amount of ion and the half-value width of the representative peak.
US09601319B1	Systems and methods for eliminating flourine residue in a substrate processing chamber using a plasma-based process A method for operating a substrate processing chamber includes after performing a process using a fluorine-based gas in the substrate processing chamber: a) during a first predetermined period, supplying a gas mixture to the substrate processing chamber including one or more gases selected from a group consisting of molecular oxygen, molecular nitrogen, nitric oxide and nitrous oxide and supplying RF power to strike plasma in the substrate processing chamber; b) during a second predetermined period after the first predetermined period, supplying molecular hydrogen gas and RF power to the substrate processing chamber; c) repeating a) and b) one or more times; d) purging the substrate processing chamber with molecular nitrogen gas; e) increasing chamber pressure; f) evacuating the substrate processing chamber; and g) repeating d), e) and f) one or more times.
US09601317B2	Cold plasma sanitizing device A cold plasma jet hand sanitizer and method of use are provided. A pair of opposing two-dimensional arrays of atmospheric pressure cold plasma jets is used to create a sterilizing volume. Any object placed into that volume will have its surface sterilized. The opposing arrays of plasma jets are operated electrically 180 degrees out of phase so that the opposing arrays of plasma jets essentially fire into each other in the absence of an intervening object, or directly impinge on the surface of an intervening object.
US09601313B2	Automated TEM sample preparation Techniques are described that facilitate automated extraction of lamellae and attaching the lamellae to sample grids for viewing on transmission electron microscopes. Some embodiments of the invention involve the use of machine vision to determine the positions of the lamella, the probe, and/or the TEM grid to guide the attachment of the probe to the lamella and the attachment of the lamella to the TEM grid. Techniques that facilitate the use of machine vision include shaping a probe tip so that its position can be readily recognized by image recognition software. Image subtraction techniques can be used to determine the position of the lamellae attached to the probe for moving the lamella to the TEM grid for attachment. In some embodiments, reference structures are milled on the probe or on the lamella to facilitate image recognition.
US09601312B2	Source for selectively providing positively or negatively charged particles for a focusing column A single column charged particle source with user selectable configurations operates in ion-mode for FIB operations or electron mode for SEM operations. Equipped with an x-ray detector, energy dispersive x-ray spectroscopy analysis is possible. A user can selectively configure the source to prepare a sample in the ion-mode or FIB mode then essentially flip a switch selecting electron-mode or SEM mode and analyze the sample using EDS or other types of analysis.
US09601306B2	Sample micromotion mechanism, method of using the same, and charged particle device A sample micromotion mechanism adapted to minimize an influence of a disturbance and adjust a sample drift rapidly and with high accuracy, and designed so as to be a compact, easy-to-place sample micromotion mechanism of a side-entry type that suppresses the occurrence of the sample drift and generates/displays high-resolution monitoring images and precisely drawn patterns. A charged particle device employing the sample micromotion mechanism operates followed by deformation which causes a strain. A strain measuring unit measures such strain. The sample micromotion mechanism imparts micromotion so as to reduce the strain in accordance with the measured strain value, thereby reducing deformation of the sample micromotion mechanism.
US09601304B2	Aberration correction apparatus, device having the same, and method for correcting aberration of charged particles According to embodiments of the present invention, an aberration correction apparatus is provided. The aberration correction apparatus includes an aberration correction unit including a first conductive element, and a second conductive element arranged rotationally symmetrical about the first conductive element, wherein the aberration correction unit is arranged to propagate an annular beam having charged particles in between the first conductive element and the second conductive element such that propagation of the annular beam through the aberration correction unit is rotationally symmetrical about the first conductive element, and wherein the aberration correction unit is configured to generate, between the first conductive element and the second conductive element, a magnetic field force and an electric field force directed in opposite directions and superimposed on each other to act on the charged particles to change a trajectory of the charged particles, and an annular aperture optically coupled to the aberration correction unit.
US09601301B2	Non-intrusive measurement of a wafer DC self-bias in semiconductor processing equipment A direct (DC) voltage is applied to an electrode at a voltage value to clamp a workpiece to an electrostatic chuck in a processing chamber. The electrode is embedded into the electrostatic chuck. An electrostatic chuck current through the electrode at the DC voltage is measured. A DC self bias induced on the workpiece by a plasma is determined based on the electrostatic chuck current and the applied voltage.
US09601299B2	Photocathode including silicon substrate with boron layer A photocathode is formed on a monocrystalline silicon substrate having opposing illuminated (top) and output (bottom) surfaces. To prevent oxidation of the silicon, a thin (e.g., 1-5 nm) boron layer is disposed directly on the output surface using a process that minimizes oxidation and defects, and a low work-function material layer is then formed over the boron layer to enhance the emission of photoelectrons. The low work-function material includes an alkali metal (e.g., cesium) or an alkali metal oxide. An optional second boron layer is formed on the illuminated (top) surface, and an optional anti-reflective material layer is formed on the boron layer to enhance entry of photons into the silicon substrate. An optional external potential is generated between the opposing illuminated (top) and output (bottom) surfaces. The photocathode forms part of novel sensors and inspection systems.
US09601298B2	Electron gun supporting member and electron gun apparatus An electron gun supporting member includes an insulating supporting member configured such that its one end is connected to a predetermined member having a ground potential and other end is connected to a high-voltage electrode to which a high potential being a negative high potential for emitting electrons from an electron source is applied, so as to support the high-voltage electrode, and a metal film formed in a partial region, which contacts neither the high-voltage electrode nor the predetermined member, on the outer surface of the insulating supporting member.
US09601297B2	High voltage compact fuse assembly with magnetic arc deflection Fuse assemblies in the form of fuse blocks and fuse holders include embedded permanent magnet arc suppression features that facilitate higher voltage operation of fusible circuit protection without increasing the size of the fuse assemblies. The embedded magnets apply an external magnetic field upon an overcurrent protection fuse and produce an arc deflection force to enhance arc quenching capability of the fuse without increasing its form factor.
US09601295B2	Breaker tripping mechanisms, circuit breakers, systems, and methods of using same Embodiments provide tripping unit of a circuit breaker. The tripping unit includes a magnet, a bimetal member extending alongside of the magnet, and an armature pivotable on the magnet, wherein the armature having an engagement portion engageable with the bimetal member at a moveable end of the bimetal member. Circuit breakers including triggering mechanisms and tripping units are also disclosed, as are low-profile, electronic circuit breakers including a maximum transverse width (Wt) limited to occupy only a single standard breaker panelboard location. System and methods are provided, as are other aspects.
US09601291B2	Actuator for circuit breaker and method for manufacturing the same The present disclosure may fix the second yoke without using an upper cover and a lower cover, thereby having an effect of simplifying the entire structure, and reducing the fabrication cost, and decreasing the fabrication time.
US09601288B2	Apparatus for floor cleaning, with improved key Apparatus for floor cleaning, having a cavity that opens on the dashboard, a plurality of mechanically similar interchangeable keys, and suitable to be inserted completely into and operate with said cavity, two or more Hall-effect sensors arranged outside said cavity, at least one first key containing at least one magnet, and at least one second key including at least one respective second magnet, which are in functional correspondence with respective predefined sensors.Said magnets do not interfere with sensors to which they are not geometrically connected, and for this purpose they are aligned on a same straight line, and the insertion of said keys causes a movement of said magnets toward the respective sensors with a motion orthogonal to said straight line.
US09601286B2	Assembly of a handheld electronic device Several mechanical features of an electronic device are provided. In some embodiments, the electronic device may include a bezel coupled to a housing. The bezel may include one or more snaps extending into the electronic device which may be operative to engage a cantilever spring extending from the inner surface of the housing. In some embodiments, the electronic device may include a window that is formed by coupling an outer layer to an inner layer that is larger than the outer layer. In some embodiments, the electronic device may include a chassis for supporting the window. In some embodiments, the electronic device may include a grounding clip for simultaneously grounding the bezel, the housing and a circuit board. In some embodiments, the electronic device may include a switch that includes a button molded into a base using a double shot process. In some embodiments, the electronic device may include a switch supporting bracket that includes a slot operative to receive a pin of the bezel. In some embodiments, the housing of the electronic device may be manufactured using a forging process.
US09601274B2	Capacitor module with temperature sensor In a capacitor module, a capacitor, a seal member that seals the capacitor, an electronic element electrically connected to the capacitor, a temperature sensor that measures a temperature around the capacitor, and a wire member electrically connected to the temperature sensor are provided. A holder holds at least the electronic element, the temperature sensor, and the wire member. The holder is fixed to the seal member while the temperature sensor is located between the electronic element and at least part of the capacitor via the seal member.
US09601268B2	Wirelessly powered devices A circuit for delivering power to a load from a wireless power supply comprises an inductor coil for placing in the electromagnetic field of an inductor coil of a supply and a switchable capacitor bank with capacitors switchable at least between a series and a parallel configuration. The voltage across the capacitor bank is used as a feedback control parameter for controlling the capacitor bank switching. A voltage regulator is used to supply the load with a constant voltage power supply derived from the capacitor bank output.
US09601267B2	Wireless power transmitter with a plurality of magnetic oscillators A power transmitter is configured to wirelessly transfer power to at least one power receiver. The power transmitter includes at least one excitation circuit configured to generate a time-varying first magnetic field in response to a time-varying electric current flowing through the at least one excitation circuit. The time-varying first magnetic field has an excitation frequency. The power transmitter further includes a plurality of magnetic oscillators. Each magnetic oscillator of the plurality of magnetic oscillators has a mechanical resonant frequency substantially equal to the excitation frequency. The plurality of magnetic oscillators is configured to generate a time-varying second magnetic field in response to the first magnetic field.
US09601260B2	Method of manufacturing an electromagnetic induction device and an electromagnetic induction device A method of manufacturing an electromagnetic induction device with On-Load Tap Changer. The method includes: a) providing an electromagnetic core with windings, b) suspending an OLTC insulation barrier from the electromagnetic induction device by a suspension, wherein the OLTC interface barrier arrangement is arranged to act as a barrier between an electromagnetic core housing and an OLTC, and wherein the OLTC interface barrier arrangement is provided with a first set of electrical connections arranged to be connected to the windings and a second set of electrical connections arranged to be connected to the OLTC, c) connecting the first set of electrical connections to the windings, and d) subjecting the windings and the OLTC interface barrier arrangement to a drying process.
US09601257B2	Wind-on core manufacturing method for split core configurations A method provides a portion of a transformer by forming a core by providing transformer core material, cutting individual laminations and bending them into generally C-shaped members, stacking some members to define a first core portion having a main leg and two opposing end legs, stacking other members to define a second core portion having a main leg and two opposing end legs, arranging the main legs in a back-to-back manner to define the core having a core leg defined by the two main legs, and opposing core yokes, defined by the end legs. Conductive material is wound directly around the core leg to form a primary winding and secondary winding in any order of arrangement, thus providing a first transformer portion. The transformer portion may be part of a single transformer or, when second and third transformer portions are provided, as part of a three-phase transformer.
US09601255B2	Amorphous core transformer In an amorphous core transformer, an amorphous core is constructed such that, when a plurality of kinds of amorphous magnetic strips having different widths are arranged in abutting relation and laminated, the amorphous magnetic strips are alternated in arrangement for lamination so that abutting surfaces of the arranged and laminated amorphous magnetic strips are displaced with respect to one another. Thus, hours of wrapping work are drastically reduced and working efficiency is improved.
US09601252B2	Electromagnetic drive device and method of manufacturing electromagnetic drive device Deformation is depressed where cover and connectors are integrally formed from a resin. A core body includes first and second body portions coupled to each other in the axial direction. The first body portion has a tubular shape extending in the axial direction, and a space surrounded by the inner peripheral surface thereof forms a housing space for a member that slides in the axial direction along the inner peripheral surface. The second body portion's outer peripheral surface and a bobbin body portion inner peripheral surface contact each other, and the first body portion outer peripheral surface and a target end portion inner peripheral surface, which is the bobbin body portion's end portion on the side in a direction from the second body portion toward the first body portion in the axial direction, are spaced from each other in at least a part of the region in the circumferential direction.
US09601248B2	Calcined ferrite, sintered ferrite magnet and its production method A method comprising the steps of mixing raw material powders to a composition comprising metal elements of Ca, La, Sr, Ba, Fe and Co, whose atomic ratios are represented by the general formula of Ca1-x-yLax(Sry′Ba1-y′)yFe2n-zCoz, wherein 1−x−y, x and y are values in a region defined by a coordinate a: (0.470, 0.297, 0.233), a coordinate b: (0.300, 0.392, 0.308), a coordinate c: (0.300, 0.300, 0.400), a coordinate d: (0.400, 0.200, 0.400) and a coordinate e: (0.470, 0.200, 0.330) in a ternary diagram of x, y, and 1−x−y, y′ and z, and n representing a molar ratio meet 0.5≦y′≦1, 0.2≦z<0.25, and 5.2
US09601245B2	Magnetoelectric effect material and method for manufacturing same The invention provides the Magnetoelectric Effect Material consisted of a single isotope, the alloy of isotopes, or the compound of isotopes. The invention applies enrichment and purification to increase the isotope abundance, to create the density of nuclear exciton by irradiation, and therefore increase the magnetoelectric effect of the crystal of single isotope, the alloy crystal of isotopes and the compound crystal of isotopes. The invention provides the manufacturing method including the selection rules of isotopes, the fabrication processes and the structure of composite materials. The invention belongs to the area of the nuclear science and the improvement of material character. The invention using the transition of entangled multiple photons to achieve the delocalized nuclear exciton. The mix of selected isotopes adjusts the decay lifetime of nuclear exciton and the irradiation efficiency to generate the nuclear exciton.
US09601243B2	Contact element for varistor The invention relates to a contact for a varistor (VAR), comprising a first feed element (ZL1) which is suitable for connecting to a supply network, and a plurality of electrical connection points (V1, V2 . . . VN) which are at a distance from one another and are suitable for making multiple connections to a pole of said varistor (VAR). The plurality of electrical connection points (V1, V2, . . . VN) and the first feed element (ZL1) are electrically interconnected, and the plurality of electrical connection points (V1, V2, . . . VN) are each designed with fuse elements (F1, F2, . . . FN) such that local shorting of one part of the varistor (VAR) can be achieved by disconnecting the local electrical connection point (n) (V1, V2, . . . VN) in question.
US09601241B2	Cable clamp A cable clamping unit for clamping an electrical cable including first and second mating units for clamping around the cable, each of the mating units including a soft sleeve for engaging the cable, the sleeves being at least semi permanently attached to a corresponding mating unit. A cable clamp includes a busbar securing portion for securing the cable clamp to a busbar, a first mating unit including a first cable locating formation, at least two securing nuts, each including a threaded portion for engaging a respective attachment bolts and also engaging at least two respective securing bolts, and a second mating unit including a second cable locating formation and adapted to engage the first mating unit thereby to securely clamp an electrical cable located between respective first and second locating formations of the first and second mating units.
US09601230B2	Oleic and medium chain length triglyceride based, low viscosity, high flash point dielectric fluids A dielectric fluid comprising in weight percent based on the weight of the composition: A. 30 to 70% C18:1 fatty acids; B. 10 to 55% of a mixture of C8 and C10 fatty acids in which the mixture comprises 50 to 70 wt %, based on the weight of the mixture, of C8 fatty acids; C. No more than 13% polyunsaturated fatty acids; and D. No more than 7% of saturated fatty acids of which each contains at least 12 carbon atoms.
US09601228B2	Silicon oxide based high capacity anode materials for lithium ion batteries Silicon oxide based materials, including composites with various electrical conductive compositions, are formulated into desirable anodes. The anodes can be effectively combined into lithium ion batteries with high capacity cathode materials. In some formulations, supplemental lithium can be used to stabilize cycling as well as to reduce effects of first cycle irreversible capacity loss. Batteries are described with surprisingly good cycling properties with good specific capacities with respect to both cathode active weights and anode active weights.
US09601225B2	Multiple-cavity vapor cell structure for micro-fabricated atomic clocks, magnetometers, and other devices An apparatus includes a vapor cell having multiple cavities fluidly connected by one or more channels. At least one of the cavities is configured to receive a first material able to dissociate into one or more gases that are contained within the vapor cell. At least one of the cavities is configured to receive a second material able to absorb at least a portion of the one or more gases. The vapor cell could include a first cavity configured to receive the first material and a second cavity fluidly connected to the first cavity by at least one first channel, where the second cavity is configured to receive the gas(es). The vapor cell could also include a third cavity fluidly connected to at least one of the first and second cavities by at least one second channel, where the third cavity is configured to receive the second material.
US09601222B2	Emergency fluid source for harsh environments The present invention takes the form of an apparatus or system that provides an alternate source of the pneumatic fluid to a system inside containment of a nuclear powerplant. An embodiment of the present invention may provide a nearly radiation-proof and nearly leak-proof, pneumatic fluid supply for some systems of the nuclear powerplant. These systems may include, but is not limited to, actuators, valves, and the like. An embodiment of the present invention may comprise a device that may propel an object with a sufficient force to puncture a seal of a pressure vessel. The released pneumatic fluid may be ported to an actuator, valve, or the like, for immediate operation of a system of the nuclear powerplant. Alternately, in an embodiment of the present invention, the pneumatic fluid may be used to resupply a depleted accumulator, or the like.
US09601212B2	Storage device and information processing method A storage device and an information processing method are provided. The storage device has a first power supply unit and at least one first storage cell. The at least one first storage cell stores first data which are associated with a number of charges within the first storage cell. The first power supply unit is electrically connected to the at least one first storage cell. The storage device further has a first control unit configured for controlling the first power supply unit to supply power to the at least one first storage cell according to a predetermined policy, so that the number of charges within the first storage cell satisfies a first preset condition.
US09601211B1	Semiconductor memory device A semiconductor memory device may include a memory cell array, two or more global word lines, and two or more path circuits. The two or more global word lines may be coupled to word lines in parallel. At least one of the two or more path circuits may be coupled between portions of each word line portions of each word line. Each path circuit may couple one of the global word lines to one of the word lines.
US09601209B2	Voltage generator and semiconductor memory device A voltage generator includes a first trim unit and a second trim unit. The first trim unit generates a first voltage variable depending on temperature variation and a second voltage invariable irrespective of the temperature variation based on a power supply voltage, and performs a first trim operation by changing a level of the second voltage. The level of the second voltage at a first temperature becomes substantially the same as a level of the first voltage at the first temperature based on the first trim operation. The second trim unit generates an output voltage based on the power supply voltage, the first and second voltages, a reference voltage and a feedback voltage, and performs a second trim operation by adjusting variation of the output voltage depending on the temperature variation based on a result of the first trim operation.
US09601208B2	Nonvolatile memory device and driving method thereof According to example embodiments, a nonvolatile memory device includes a plurality of strings having a plurality of serially-connected selection transistors and a plurality of memory cells connected in series to one end of the serially-connected selection transistors. A control logic is configured to perform a program operation for setting a threshold voltage of at least one of the serially-connected selection transistors.
US09601207B2	Semiconductor memory device and method of operating the same A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.
US09601202B2	Low voltage difference operated EEPROM and operating method thereof The present invention discloses a low voltage difference-operated EEPROM and an operating method thereof, wherein at least one transistor structure is formed in a semiconductor substrate and each includes a first electric-conduction gate. Same type ions are implanted into a region of the semiconductor substrate, which is near interfaces of a source, a drain and the first electric-conduction gate, or ion-doped regions of the source and the drain, to increase the ion concentration thereof, whereby to reduce the voltage differences required for writing and erasing. The present invention also discloses an operating method for the low voltage difference-operated EEPROM, in addition to the EEPROM with a single gate transistor structure, the present invention also applies to the EEPROM with a single floating gate transistor structure.
US09601195B2	Voltage control for crosspoint memory structures The present disclosure provides a memory cell that includes a resistive memory element disposed between a first conductor and a second conductor, the first conductor and the second conductor configured to activate the resistive memory element. The memory cell also includes a diode disposed in parallel with the memory element between the first conductor and the second conductor.
US09601193B1	Cross point memory control The present disclosure relates to phase change memory control. An apparatus includes a memory controller. The memory controller includes a word line (WL) control module and a bit line (BL) control module. The memory controller is to determine a WL address based, at least in part, on a received memory address. The memory controller is further to determine a BL address. The apparatus further includes a parameter selection module to select a value of a control parameter based, at least in part, on at least one of the WL address and/or the BL address.
US09601191B2	Exploiting phase-change memory write asymmetries to accelerate write To improve the write performance of PCM, the disclosed technology, in certain embodiments, provides a new write scheme, referred to herein as two-stage-write, which leverages the speed and power asymmetries of writing a zero bit and a one bit. Writing a data block to PCM is divided into two separated stages, i.e., write-0 stage and write-1 stage. Without violating power constraints, during the write-0 stage, all zero bits in this data block are written to PCM at an accelerated speed; during the write-1 stage, all one bits are written to PCM, with more bits being written concurrently. In certain embodiments, the disclosed technology provides a new coding scheme to improve the speed of the write-1 stage by further increasing the number of bits that can be written to PCM in parallel.
US09601188B1	Method, apparatus and system for targeted healing of stability failures through bias temperature instability We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; a row decoder configured to authorize or deauthorize a write voltage to each word line through the word line driver, wherein the write voltage is selected from an operational write voltage or a first write voltage; and a control line configured to provide an operational write voltage or a first write voltage to each word line authorized by the row decoder, wherein the first write voltage is greater than an operational write voltage.
US09601187B1	Method, apparatus, and system for global healing of stability-limited die through bias temperature instability We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; and a control line configured to provide an operational write voltage or a first write voltage to each word line through the word line driver. By virtue of BTI, application of the first write voltage may lead to improved stability of data desired to be read from one or more cells of the device.
US09601186B2	Bit line precharging circuit, static RAM, electronic device, and static ram bit line precharging method A bit line precharging circuit includes a first switch that connects a bit line to a first power source, a second switch that connects the bit line to a second power source whose voltage value is higher than voltage value of the first power source, and a control circuit including a delay element and configured to bring the second switch into conduction after a delay time by the delay element after bringing the first switch into conduction at the time of precharge of the bit line.
US09601185B2	Integrated CMOS circuit having first and second circuit parts An integrated circuit includes first and second circuit parts that may be arranged close to one another in a single semiconducting substrate. The circuit may use a deep doping well for reducing digital noise, and may implement a sleep mode for reducing power consumption. This circuit may have a random access memory, and may be a radio communication system-on-chip device. The integrated circuit may advantageously be used within a mobile communication apparatus.
US09601184B2	Semiconductor memory and method for operating the same A semiconductor memory may include: a storage unit suitable for storing a minimum operation interval between row command operations, a detection unit suitable for detecting whether row command signals inputted for the row command operations are activated at the minimum operation interval, a latching unit suitable for generating flag signals by latching the row command signals, and a shifting unit suitable for shifting the flag signals based on the minimum operation interval in response to an output signal of the detection unit, and generating an internal row command signals.
US09601179B2	Semiconductor memory device, method of performing a refresh for semiconductor memory device and refresh counter in semiconductor memory device A semiconductor memory device may include a memory cell array, a first decoder and a second decoder. The memory cell array includes a plurality of memory cell rows. The first decoder is configured to select a first number of memory cell rows of the plurality of memory cell rows based on a selected refresh row address of a set of row addresses. The second decoder is configured to select a second number of memory cell rows of the plurality of memory cell rows based on the selected refresh row address. A total number of the first number and the second number is varied in response to the selected refresh row address.
US09601178B2	Memory device and semiconductor device To provide a memory device which operates at high speed or a memory device in which the frequency of refresh operations is reduced. In a cell array, a potential is supplied from a driver circuit to a wiring connected to a memory cell. The cell array is provided over the driver circuit. Each of memory cells included in the cell array includes a switching element, and a capacitor in which supply, holding, and discharge of electric charge are controlled by the switching element. Further, a channel formation region of the transistor used as the switching element includes a semiconductor whose band gap is wider than that of silicon and whose intrinsic carrier density is lower than that of silicon.
US09601177B2	Data retention control circuit, data writing method, data reading method, method of testing characteristics of ferroelectric storage device, and semiconductor chip A data retention control circuit includes a data retention part having first and second logic circuits, a ferroelectric storage part having first and second ferroelectric device parts, first and second transmission control parts, and a test voltage supply control part. The first transmission control part has first and second transmission control circuits controlling first and second logic signals to the first and second ferroelectric device parts, respectively. The second transmission control part has third and fourth transmission control circuits controlling transmission of first and second storage data from the first and second ferroelectric device part to the second and first logic circuits, respectively. The test voltage supply control part has first and second test voltage supply control circuits controlling supplies of first and second test voltages to the second and first logic circuit, respectively.
US09601176B2	Nonvolatile memory According to one embodiment, a nonvolatile memory includes a memory cell, a write circuit generating a write current to change the memory cell from a first resistance value to a second resistance value, a first current generating circuit generating a first current based on the write current flowing through the memory cell, a second current generating circuit generating a second current based on the write current flowing through the memory cell, a hold circuit holding a first value generated based on the second current when the memory cell stores the first resistance value, a comparator comparing the first value with a second value generated based on a change of the first current while the memory cell changes from the first resistance value to the second resistance value, and a write current control circuit cutting off the write current based on a result of comparison of the comparator.
US09601172B2	Address aligner and memory device including the same An address aligner includes a command address providing unit, an alignment signal providing unit and an alignment unit. The command address providing unit outputs a sync command address signal by delaying a command address signal in synchronization with a first clock signal. The sync command address signal is synchronized with the first clock signal. The alignment signal providing unit outputs alignment clock signals by delaying a chip select signal in synchronization with a second clock signal. The alignment clock signals are synchronized with the second clock signal. The alignment unit outputs a plurality of addresses in synchronization with the alignment clock signals. The plurality of addresses is included in the sync command address signal. If the address aligner according to example embodiments is used, the operation speed of the memory device may be increased by aligning a plurality of addresses in synchronization with the alignment clock signal that is generated based on a chip select signal.
US09601170B1	Apparatuses and methods for adjusting a delay of a command signal path Apparatuses and methods related to adjusting a delay of a command signal path are disclosed. An example apparatus includes: a command input buffer that receives command signals and further provides buffered command signals; a command decoder coupled to the command input buffer, that decodes the buffered command signals responsive to a first clock signal and further provides a decoded command signal; and a command extension circuit coupled to the command decoder, which receives the decoded command signal, the first clock signal and a second clock signal having a first delay relative to the first clock signal, and further provides a command extension signal having a pulse width longer than the pulse width of the decoded command signal.
US09601167B1	Semiconductor device having dual-gate transistors and calibration circuitry Disclosed are various embodiments related to dual-gate transistors and associated calibration circuitry. In one embodiment, dual-gate transistors may be configured in a sense amplifier arrangement, and calibration circuitry can be used to adjust an input offset of the sense amplifier. In another embodiment, a reference level voltage utilized in an amplifier with dual-gate transistors can be adjusted during a calibration sequence, and may be substantially unchanged from its nominal value outside of the calibration sequence. In another embodiment, a calibration sequence can be utilized to determine circuit results from a circuit including dual-gate transistors, and to adjust control gates to more closely coincide with expected or desired results. In yet another embodiment, a semiconductor memory device can include a memory array with amplifiers that include dual-gate transistors, as well as associated calibration circuitry.
US09601165B1	Sense amplifier Embodiments include a sense amplifier circuit including first and second paths that may be selectively coupled to a memory cell or a reference cell as part of a two-phase read process. The sense amplifier may include a biasing circuit to provide an adaptive bias voltage to a transistor of the first and/or second path to cause the transistor to provide a voltage across the memory cell and/or reference cell that is substantially constant across process corners. Additionally, or alternatively, the sense amplifier may include a DC-coupled regenerative latch circuit to generate a digital output signal based on a voltage difference between nodes of the first and second paths at or near the end of the second phase. Additionally, or alternatively, trimmable offset resistors may adjust a resistance value provided to the sense amplifier by the memory cell and/or reference cells. Other embodiments may be described and claimed.
US09601164B2	Array structure of single-ploy nonvolatile memory An array structure of a single-poly nonvolatile memory includes a first MTP section and a first OTP section. The first MTP section includes a plurality of MTP cells and the first OTP section includes a plurality of OTP cells. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The first OTP section is connected to a second word line, a second source line and the plurality of bit lines shared with the first MTP section.
US09601161B2	Metallically sealed, wrapped hard disk drives and related methods Hard disk drives of the invention are wrapped in wraps for enhanced sealing of the hard disk drive. Wrapped hard disk drives of the invention comprise: an enclosed hard disk drive housing comprising a base and a cover enclosed around internal components for facilitating reading and recording of data at a desired location on at least one disk contained within the housing; and a wrap wrapped and metallically sealed around the enclosed hard disk drive housing in an at least partially overlapping manner to form the wrapped hard disk drive and prevent undesired migration therethrough such that a sealed environment exists within the wrapped hard disk drive.
US09601160B2	Efficient multichannel data format using variable-length headers In one embodiment, a computer-implemented method includes writing a data set to a first write section of a magnetic medium and rewriting at least some of the data set as rewritten CWI-4 sets to a rewrite section of the magnetic medium. The data set includes a plurality of sub data sets, each sub data set including a data array organized in rows and columns. Each row of the data array includes four interleaved C1 codewords (a CWI-4). A first portion of the data set is stored as CWI-4 sets to the first write section of the magnetic medium with first headers. Each rewritten CWI-4 set is stored to the rewrite section of the magnetic medium as a number of rewritten CWI-4s having corresponding rewrite headers. Also, a length of any one of the rewrite headers is greater than a length of any one of the first headers.
US09601159B2	Remotely controlled audio and video recording system A remotely controlled audio and video recording system (RAVRS) that includes a remote control unit (RCU) and an audio and video recorder (AVR). The AVR, which is located near a speaker's podium, is remotely controlled by an individual operating the RCU. The RAVRS allows the individual to selectively select and “mark” certain passages of a specific lecture for later retrieval.
US09601157B2	Methods and apparatus for remote motion graphics authoring Network-accessible services that provide post-production digital compositing and motion graphics authoring to users who provide their own core content, which the services supplement via a user-driven interface through the inclusion of digital still images, artwork, video, sound, and/or other supplemental content selected by the user. In one embodiment, following selection and sequencing of the various core and supplemental content components, the services automatically generate and make available to a user a finished product that integrates core and supplemental content. To simplify the compositing task, a series of pre-formatted motion graphics video templates may be made available. The end product provided by aspects of the present invention may be a professional-quality ensemble motion graphics video production that may be delivered in any popular format, such as AVI, JPEG, MPEG4 and the like to the customer and or to selected recipients via download or common carrier.
US09601152B2	Additional overshoot current HDD write driver circuit A hard disk drive write drive method and integrated circuit that provide a configurable overshoot current based on the length of the pattern in the write current signal that is being written to the hard disk by the write driver. The hard disk write driver adds a first overshoot current to all patterns in the write current signal and adds an additional second overshoot current to patterns in the write current signal shorter than a first duration. The hard disk drive write driver utilizes an H-bridge circuit configured to add the first overshoot current and the additional second overshoot current to the write current signal. The H-bridge circuit is comprised of four switching elements that are configured to generate a first overshoot current for all pattern transitions of the write current signal and generate a second overshoot current for pattern transitions shorter than the first duration.
US09601149B1	Media library including storage media retrieval assembly A retrieval assembly (22) for moving storage media (16) within a media library (10), the media library (10) including a rack assembly (20) having a first rack (20A) and a spaced apart second rack (20B), comprises a picker system (32), an assembly base (30), a first mover (28A), a second mover (28B), and a control system (26). The picker system (32) selectively engages the storage media (16). The assembly base (30) supports the picker system (32). The first mover (28A) is secured to the assembly base (30), and selectively moves along the first rack (20A). The second mover (28B) is also secured to the assembly base (30), and selectively moves along the second rack (20B). The second mover (28B) is spaced apart from the first mover (28A). The control system (26) controls independent movement of the first mover (28A) and the second mover (28B) to position the assembly base (30) relative to the storage media (16).
US09601148B2	Robotic safety stop for automated storage library A safety stop mechanism for an automated storage library in which a connector has first and second ends. The first end is configured to contact a door of the automated storage library when the door is in at least a first position. A safety stop is connected to the second end of the connector and adapted to move from a down position to an up position. The safety stop is in the down position when the door is in the first position allowing for travel of the robotic accessor over the safety stop.
US09601146B2	Magnetic tape An aspect of the present invention relates to a magnetic tape comprising a magnetic layer comprising ferromagnetic powder and binder on a nonmagnetic support, wherein ΔSFD in a longitudinal direction of the magnetic tape as calculated with Equation 1 ranges from 0.35 to 1.50: ΔSFD=SFD25° C.−SFD−190° C. Equation 1 wherein, in Equation 1, SFD25° C. denotes a switching field distribution SFD as measured in the longitudinal direction of the magnetic tape in an environment with a temperature of 25° C., and SFD−190° C. denotes a switching field distribution SFD as measured in the longitudinal direction of the magnetic tape in an environment with a temperature of −190° C.
US09601144B1	Heat-assisted magnetic recording (HAMR) disk drive with disk having multiple continuous magnetic recording layers A heat-assisted magnetic recording (HAMR) disk drive has a disk with at least two independent data layers (RL1 and RL2), each data layer storing an independent data stream. At a high laser power both RL1 and RL2 are heated to above their respective Curie temperatures and a first data stream is recorded in both RL1 and RL2. At a lower laser power only upper RL2 is heated to above its Curie temperature and a second data stream is recorded only in RL2. The data layers are separated by a nonmagnetic spacer layer (SL) that prevents lower RL1 from being heated to above its Curie temperature at low laser power. The first and second data streams are typically asynchronous. Recorded data is read back from both data streams simultaneously as a composite readback signal. A joint Viterbi detector detects the asynchronous data streams simultaneously from the composite readback signal.
US09601143B1	Disturbance observer with energy reducing filter Disturbance rejection in a closed loop multi-actuator system. In some embodiments, a first disturbance observer (DOB) circuit is configured to inject a first disturbance rejection signal into an input control signal of a first stage of a multi-stage actuator. A second DOB circuit is configured to concurrently inject a second disturbance rejection signal into an input control signal of a second stage of the multi-stage actuator. Each of the first and second DOB circuits includes a band pass filter and an energy reducing filter. In some embodiments, the energy reducing filter has at least one notch filter and at least one anti-notch filter. In other embodiments, the energy reducing filter is a low-pass filter (LPF).
US09601142B1	Magnetic recording tracks with consolidated timing fields and no inter-sector gaps Method and apparatus for storing and retrieving user data from magnetic recording tracks in a data storage device. In some embodiments, a rotatable data recording medium has a circumferentially extending data track formed from spaced apart embedded servo wedges that extend radially across a recording surface of the medium to define intervening data wedges between each adjacent pair of the servo wedges. Each data wedge along the data track has only a single timing field at a beginning portion of the data wedge immediately adjacent a first servo wedge, followed by a plurality of data sectors that extend across the data wedge to an end portion of the data wedge immediately adjacent a second servo wedge. No inter-sector gaps are provided between the respective data sectors and no additional timing fields are provided between the first and second servo wedges.
US09601134B2	Magnetic writer having multiple gaps with more uniform magnetic fields across the gaps A magnetic device according to one embodiment includes a source of flux and a magnetic yoke coupled to the source of flux. The source of flux includes a thin film coil having multiple turns. The magnetic yoke has a pole with two or more gaps, wherein the coil turns have a non-uniform placement in the magnetic yoke for creating a higher magnetic field at one of the gaps than another of the gaps during writing. A magnetic device according to another embodiment includes a source of flux. A geometry of the magnetic pole near or at one of the gaps is different than a geometry of the magnetic pole near or at another of the gaps to help equalize fields formed at the gaps when the source of flux is generating flux.
US09601133B2	Vector noise cancellation Techniques are provided for vector noise cancellation. Different value combinations for a plurality of weighting factors may be established for a plurality of selection regions. Each value combination for the plurality of weighting factors may correspond to a different combination of a set of input signals. One or more characteristics of input signals may be used to select a particular selection region. A particular value combination of the set of weighting factors may be chosen to attenuate or amplify the input signals to generate one or more output signals.
US09601131B2	Sound processing device and method A sound processing device is provided. The sound processing device includes a microphone array and a post filtering module. The microphone array includes microphones aiming to different directions and configured for receiving sound signals. The post filtering module is configured for receiving the sound signals from the microphone array, filtering the sound signals to generate groups of filtered signals each corresponding to one of the sound signals, wherein each of the filtered signals within a group corresponds to one of different frequency bands, generating band signals each based on a comparison of an intensity of one of the filtered signals that corresponds to the same one of the frequency bands in each group of the filtered signals and a noise intensity correlation between the frequency bands and adding the band signals to generate an output sound signal.
US09601130B2	Method for processing speech signals using an ensemble of speech enhancement procedures A method processes an acoustic signal that is a mixture of a target signal and interfering signals by first enhancing the acoustic signal by a set of enhancement procedures to produce a set of initial enhanced signals. Then, an ensemble learning procedure is applied to the acoustic signal and the set of initial enhancement signals to produce features of the acoustic signal.
US09601127B2	Social music system and method with continuous, real-time pitch correction of vocal performance and dry vocal capture for subsequent re-rendering based on selectively applicable vocal effect(s) schedule(s) Vocal musical performances may be captured and, in some cases or embodiments, pitch-corrected and/or processed in accord with a user selectable vocal effects schedule for mixing and rendering with backing tracks in ways that create compelling user experiences. In some cases, the vocal performances of individual users are captured on mobile devices in the context of a karaoke-style presentation of lyrics in correspondence with audible renderings of a backing track. Such performances can be pitch-corrected in real-time at the mobile device in accord with pitch correction settings. Vocal effects schedules may also be selectively applied to such performances. In these ways, even amateur user/performers with imperfect pitch are encouraged to take a shot at “stardom” and/or take part in a game play, social network or vocal achievement application architecture that facilitates musical collaboration on a global scale and/or, in some cases or embodiments, to initiate revenue generating in-application transactions.
US09601125B2	Systems and methods of performing noise modulation and gain adjustment A method includes receiving a first value of a mixing factor. The first value corresponds to a first portion of an audio signal received at an audio encoder. The method includes receiving a second value of the mixing factor. The second value corresponds to a second portion of the audio signal. The method also includes generating a third value of the mixing factor at least partially based on the first value and the second value and mixing an excitation signal with modulated noise based on the third value. Another method includes determining a first set of spectral frequency values corresponding to an audio signal and determining a second set of spectral frequency values that approximates the first set of spectral frequency values. A gain value corresponding to at least a portion of the audio signal is adjusted based on a difference between the first set and the second set.
US09601121B1	Override vocoder capacity operating point allocation Embodiments disclosed herein provide systems and methods for override vocoder capacity operating point (COP) allocation. In a particular embodiment, a method provides determining a communication load on a wireless access node. Based on the communication load, the method provides allocating a first COP for a vocoder, wherein the vocoder is used on voice communications exchanged with the wireless access node. The method further provides determining a frame error rate of a wireless communication link between a wireless communication device and the wireless access node. If the frame error rate indicates that a COP of the wireless communication link should be lower than the first COP, the method provides allocating an override COP to the COP of the wireless communication link based on the frame error rate.
US09601116B2	Recognizing speech in the presence of additional audio The technology described in this document can be embodied in a computer-implemented method that includes receiving, at a processing system, a first signal including an output of a speaker device and an additional audio signal. The method also includes determining, by the processing system, based at least in part on a model trained to identify the output of the speaker device, that the additional audio signal corresponds to an utterance of a user. The method further includes initiating a reduction in an audio output level of the speaker device based on determining that the additional audio signal corresponds to the utterance of the user.
US09601115B2	Conversational agent with a particular spoken style of speech Methods, systems, and apparatus, including computer programs encoded on computer storage media, for handing off a user conversation between computer-implemented agents. One of the methods includes receiving, by a computer-implemented agent specific to a user device, a digital representation of speech encoding an utterance, determining, by the computer-implemented agent, that the utterance specifies a requirement to establish a communication with another computer-implemented agent, and establishing, by the computer-implemented agent, a communication between the other computer-implemented agent and the user device.
US09601113B2	System, device and method for processing interlaced multimodal user input A device, method and system are provided for interpreting and executing operations based on multimodal input received at a computing device. The multimodal input can include one or more verbal and non-verbal inputs, such as a combination of speech and gesture inputs received substantially concurrently via suitable user interface means provided on the computing device. One or more target objects is identified from the non-verbal input, and text is recognized from the verbal input. An interaction object is generated using the recognized text and identified target objects, and thus comprises a natural language expression with embedded target objects. The interaction object is then processed to identify one or more operations to be executed.
US09601111B2	Methods and systems for adapting speech systems Methods and systems are provided for adapting a speech system. In one example a method includes: processing a spoken command with one or more models of one or more model types to achieve model results; evaluating a frequency of the model results; and selectively updating the one or more models of the one or more model types based on the evaluating.
US09601110B2	Unsupervised training method for an N-gram language model based upon recognition reliability A computer-based, unsupervised training method for an N-gram language model includes reading, by a computer, recognition results obtained as a result of speech recognition of speech data; acquiring, by the computer, a reliability for each of the read recognition results; referring, by the computer, to the recognition result and the acquired reliability to select an N-gram entry; and training, by the computer, the N-gram language model about selected one of more of the N-gram entries using all recognition results.
US09601107B2	Speech recognition system, recognition dictionary registration system, and acoustic model identifier series generation apparatus When it is determined that sound data is unrecognizable through a speech recognition process by a first speech recognition unit (3), the same sound data as the sound data inputted to the first speech recognition unit (3) is transmitted to a second server device (60) and a first server device (70). Recognition data is generated which is formed of a character string that is a speech recognition result by the second server device (60) with respect to the sound data, and an acoustic model identifier series generated by a first acoustic model identifier series generation unit (27) of the first server (70) based on the sound data, and the generated recognition data is registered in a first recognition dictionary (3b) of the first speech recognition unit (3).
US09601106B2	Prosody editing apparatus and method According to one embodiment, a prosody editing apparatus includes a storage, a first selection unit, a search unit, a normalization unit, a mapping unit, a display, a second selection unit, a restoring unit and a replacing unit. The search unit searches the storage for one or more second prosodic patterns corresponding to attribute information that matches attribute information of the selected phrase. The mapping maps each of the normalized second prosodic patterns on a low-dimensional space. The restoring unit restores a restored prosodic pattern according to the selected coordinates. The replacing unit replaces prosody of synthetic speech generated based on the selected phrase by the restored prosodic pattern.
US09601103B2	Methods and devices for generating high-amplitude and high-frequency focused ultrasound with light-absorbing materials A high-frequency light-generated focused ultrasound (LGFU) device is provided. The device has a source of light energy, such as a laser, and an optoacoustic lens comprising a concave composite layer with a plurality of light absorbing particles that absorbs laser energy, e.g., carbon nanotubes, and a polymeric material that rapidly expands upon exposure to heat, e.g., polydimethylsiloxane. The laser energy is directed to the optoacoustic lens and thus can generate high-frequency (e.g., ≧10 MHz) and high-amplitude pressure output (e.g., ≧10 MPa) focused ultrasound. The disclosure also provides methods of making such new arcuate optoacoustic lenses, as well as methods for generating and using the high-frequency and high-amplitude ultrasound, including for surgery, like lithotripsy and ablation.
US09601100B1	Magnetic pickup with external tone shaper A magnetic pickup system comprising a magnetic pickup and a ferromagnetic tone shaper without electrical connections that is magnetically coupled and separately mounted from the pickup on a musical instrument with ferromagnetic strings.
US09601096B2	Cymbal holder with slotted threads and plunger A clutch for use in a hi-hat percussion assembly is disclosed. The clutch can included a threaded bolt that includes slots, and a nut that includes an indexing means such as a plunger. An elastic holding means can be used to exert pressure on the indexing means, such as when the indexing means is rigid, for example. The plunger can be configured to engage a slot upon rotation of the nut to lock the nut into place. While in a locked position, unwanted displacement of the nut, including rotational displacement that may be caused by forceful and rapid movements of a drummer, can be reduced, prevented, and/or eliminated. Using a force greater than that required to simply turn the nut while in an unlocked position, the nut can be rotated to disengage the plunger from the slot and return the nut to an unlocked position.
US09601086B1	Defining a projector display region Defining a display region for a projector display. An image of a camera's view of a display region is accessed. The image is displayed on a graphical user interface. The image has a first set of coordinates. The image and a reference canvas that is displayed on said graphical user interface is integrated. The integration comprises overlaying a portion of the reference canvas on the image. The reference canvas has a second set of coordinates. One of the first set of coordinates and the second set of coordinates represents a mesh of movable control points being movable from a first location to a second location on the graphical user interface. The first set of coordinates are mapped to the second set of coordinates, thereby generating a pointwise correspondence mapping between coordinate points of the reference canvas and coordinate points of the image.
US09601084B2	Array substrate and display panel The present invention provides an array substrate and a display panel. The array substrate comprises a base substrate comprising a first surface and a second surface which is opposite to the first surface, and a pixel circuit arranged on the first surface of the base substrate, wherein the array substrate further comprises a driving circuit, which is arranged on the second surface of the base substrate and is in signal connection with the pixel circuit. The present invention further provides a display panel comprising the array substrate. In the present invention, the driving circuit provides an electrical drive signal required for display to the pixel circuit, and both the driving circuit and the pixel circuit are integrated on the base substrate of the array substrate, thereby improving the degree of integration of the array substrate and reducing the total volume of the display panel.
US09601082B2	Display substrate and driving method thereof and display device The invention discloses a display substrate and a driving method thereof, and a display device. The display substrate includes a plurality of rows or columns of pixel units, wherein each row or column of pixel units include first pixel units and second pixel units which are arranged alternately, one first pixel unit and one second pixel unit are composed of three sub-pixels, and wherein the first pixel unit includes a first sub-pixel and a second sub-pixel, the second pixel unit includes the second sub-pixel and a third sub-pixel, and the first, second and third sub-pixels are arranged in turn. In the invention, three sub-pixels form two pixel units, thus the number of the sub-pixels needed to form a certain number of pixel units is decreased, and the manufacturing process is simplified and the defective rate of product is decreased.
US09601080B1	Systems and methods for virtually weighted user input elements for performing critical actions In an example implementation of the disclosed technology, a method includes receiving an indication of a gesture of an input object moving, at a rate of movement, from a first location of a presence-sensitive input device toward a second location of the presence-sensitive input device. The method also includes, responsive to determining that the rate of movement does not exceed a predetermined rate of movement, outputting, for display, a visual indicator moving from a first location of a display toward a second location of the display. The method also includes, responsive to determining that the rate of movement exceeds the predetermined rate of movement, outputting, for display, the visual indicator moving at a rate of movement that does not exceed the predetermined rate of movement.
US09601078B2	Electronic device and image data output processing method An electronic device includes an image data acquisition part configured to acquire image data, and an image output processor configured to output image data to an external display device, wherein, when an interrupt event occurs while the image output processor outputs image data to the external display device, the image output processor selects or refuses a plurality of information relating to an interrupt event based on at least one of the attribute of an interrupt event and the attribute of the external display device, thus outputting the selected information to the external display device.
US09601075B2	Display panel, method of manufacturing the display panel and display apparatus A display panel includes a plurality of pixels disposed in an active area and arranged substantially in a matrix form including a pixel row and a pixel column, a first gate line disposed adjacent to a first side n of the pixel row and connected to a first pixel in the pixel row, a second gate line disposed adjacent to a second side of the pixel row and connected to a second pixel in the pixel row, a plurality of data lines crossing the first and second gate lines, where the pixels in a pair of adjacent pixel columns are connected to a same data line, and a blocking pattern which overlaps a pixel column disposed in an end portion of the active area.
US09601072B2	Liquid crystal display device of increased holding capacitance There is provided a liquid crystal display device that enables increasing the capacitance between a pixel electrode and a common electrode without bringing about a significant decrease in the pixel aperture ratio. An In-Plane Switching LCD device in which a drain signal is supplied from one drain signal line to two pixel columns is configured such that there is a section having no drain signal line between adjacent pixels and a source electrode which is connected to a pixel electrode of a thin-film transistor extends into a contiguous pixel region that does not serve as an effective pixel region to provide one electrode of a capacitive element. A common electrode is formed in each pixel and the one electrode of the capacitive element is laid overlapping the common electrode with an insulation film intervening therebetween.
US09601065B2	Display panel driver setting method, display panel driver, and display apparatus including the same When a plurality of display panel drivers is set to a state in conformity to given specifications, setting data indicative of details of the setting is stored in a memory. One of the display panel drivers supplies a first signal indicating that the setting data is in a readout condition to the memory and other display panel drivers. In response to the first signal, the memory reads and provides the setting data on the first line. The one display panel driver fetches the setting data on the first line to perform the setting based on the setting data. The other display panel drivers fetch the setting data from the first line in response to the first signal to perform the setting based on the setting data.
US09601063B2	Device for controlling display apparatus, method for controlling display apparatus, display apparatus, and electronic equipment A device for controlling a display apparatus includes: an image acquiring portion that acquires first image data containing a tone value of each pixel; a parameter acquiring portion that acquires a parameter for determining a tone used to display an image, from among the tones of the pixel that change in a discrete manner; and a tone reducing portion that determines, in a case of reducing the number of tones to a number of tones smaller than that of the first image data, each tone value after the reduction of the number of tones, according to the parameter acquired by the parameter acquiring portion, and generates second image data in which the number of tones in the first image data acquired by the image acquiring portion has been reduced based on the determined tone value.
US09601056B2	Pixel and organic light emitting display device using the same A pixel includes an organic light emitting diode (OLED) having a cathode electrode coupled to a second power supply, a pixel circuit configured to control an amount of current supplied to the OLED to correspond to a previous data signal, and a driver configured to store a present data signal supplied from a data line and to supply the previous data signal to the pixel circuit. The OLED, pixel circuit, and driver may be controlled by signals in a frame that includes first through fourth periods, the second power supply may be set to a first voltage in the first and second periods and to a second voltage in the third and fourth periods, and the first voltage may be a voltage at which the OLED does not emit light and the second voltage may be a voltage at which the OLED emits light.
US09601053B2	Pixel unit of organic electroluminescent display A pixel unit of an organic electroluminescent display having a light emitting area and a transparent area is provided. The pixel unit includes a scan line, a data line, a control element electrically connected to the scan line and the data line, a power line electrically connected to the control element and an organic light-emitting diode disposed inside the light emitting area and electrically connected to the power line and the control element. The power line includes a main portion and a plurality of branch portions connected to the main portion. The branch portions are disposed inside the transparent area and electrically independent from the data line. A width of each of the branch portions is identical to a minimum line width of the data line.
US09601052B2	Pixel circuit of organic light-emitting display A pixel of an OLED display is disclosed. A gate voltage of a driving transistor can be precisely adjusted using a second gate electrode that can supply DC power easily securing an operation range of an OLED. Further, by only adding one power line that can precisely adjust a gate voltage of a driving transistor to an OLED display, an operation range of the OLED can be easily secured and thus a drain current can be reduced without increasing a channel length of the driving transistor resulting in a narrower pixel area. According to various embodiments, the pixel can secure an operation range of the OLED by reducing a magnitude of a drain current by adjusting a gate voltage of a driving transistor.
US09601047B2	Method for dimming electroluminescent display A method for controlling an electroluminescent display to produce first and second images for display wherein the second image has reduced luminance to reduce burn-in on the display, includes providing the electroluminescent (EL) display having a plurality of EL emitters, the luminance of the light produced by each EL emitter being responsive to a respective drive signal; receiving a respective input image signal for each EL emitter for each of a plurality of frames; transforming the input image signals for a first frame to provide a plurality of first drive signals to produce an image on the display; and transforming the input image signals for a second frame to a plurality of second drive signals using a dimming transform that operates on the input image signals for each frame to provide a peak frame luminance value for the second frame wherein the dimming transform includes an exponential function.
US09601044B2	Display apparatus with pixel elements that display a selection of colors A display apparatus is provided that includes an array of pixel elements, a control arrangement, and a drive mechanism. Each array can display a selection of colors. Each pixel element is mounted at one end of an individual support member. Each support member can be displaced in forwards and reverse directions, and is hollow and has a longitudinally extending series of projections on an interior surface thereof. The control arrangement is operable to control the color that is displayed by each individual pixel element. The drive mechanism includes a gear which is engaged with the projections, and a motor for rotating the gear. Rotation of the gear causes longitudinal movement of the support member with respect to the drive mechanism.
US09601038B2	Reflective decorative assembly The present invention is an assembly and method for providing a reflective decoration assembly that includes a frame having a pair of opposing frame edges and a plurality of first frame supports, where each frame support is arranged in a plane with at least two other first frame supports, is arranged in a plane defined by the pair of opposing frame edges, has a portion between the pair of opposing frame edges, and is substantially parallel to at least one other first frame support. The reflective decoration assembly also features a plurality of second frame supports, each being arranged in an intersecting configuration with at least two of the first frame supports. Disc attachment posts have a first end attached to the frame and a second end separated from the first end, the second end having a disc retaining head thereat.
US09601036B2	Roof parapet mounted adjustable bracket for hanging a graphic sign panel Disclosed is a roof parapet mounted adjustable bracket for hanging a sign panel. The adjustable bracket is able to fit a variety of widths of parapets and allows a user to change a sign without removing the bracket from a parapet.
US09601030B2	System and method for performing virtual surgery A method and system are presented for performing virtual surgery simulations. The computer system includes a processor and a memory. The method includes receiving user input from a user via a user interface. The user input includes input representing surgical operations or non-surgical invasive procedures. The method also includes processing the user input and utilizing the input to generate or modify a computational model. The method also includes running simulations using the computational model in accordance with the user input. After running the simulations, the method further includes determining results from the simulations. The results correspond to probable effects or outcomes of performing real life surgical operations or non-surgical invasive procedures corresponding to the user input. Last, the method includes presenting the results to the user via the user interface.
US09601029B2	Method of presenting a piece of music to a user of an electronic device A method of presenting music to a user of an electronic device comprises the step of providing score data representing the musical score of the piece of music in a graphical representation, audio data representing a recording of the piece of music, and music data representing one or more parts of parts of the piece of music in a digital format such as MIDI or MusicXML. The music data representing a part of the music that has been selected by the user is transformed into part sound signals using a sound generator. The part sound signals and audio sound signals are merged so as to obtain a merged sound signal in which the piece of music as represented by the music data file and by the audio data file are synchronized. Finally, and simultaneously, the sound of the piece of music using the merged sound signal is played audibly, the musical score is displayed on a display, and a sub-portion of the musical score corresponding to a passage of the piece of music which is presently audible is highlighted on the display.
US09601025B2	Method and system for automatic tool position determination for minimally-invasive surgery training The present invention may be embodied as a method of minimally-invasive surgery (“MIS”) training using a video of an MIS comprising the steps of providing a processor, a display, and a first input device. The method comprises the step of processing the video using the processor to determine a location of the first surgical tool in each of the frames, determining whether the configuration of the first input device substantially corresponds to the location of the first surgical tool in each frame of the video while the video is displayed. The present invention may be embodied as a system for MIS training. The system comprises a processor, a communication device, and a first input device in communication with the processor. The processor is programmed perform any or all of the described disclosed methods.
US09601020B2	Collision determination device A collision determination device determines the possibility of collision between a host vehicle and the other object on the basis of a shortest arrival time calculated by a shortest arrival time calculation unit and a passage time at each point of the host vehicle acquired by a vehicle route candidate acquisition unit. In this way, even if a locus to be taken by the other object is not generated, the shortest arrival time at which the other object can arrive at each point of the route candidate of the host vehicle with a predetermined first displacement is calculated, thereby determining the possibility of collision between the host vehicle and the other object. Therefore, it is possible to reduce a computational load for determining collision and to accurately determine collision between the host vehicle and the other object.
US09601012B2	Remote operated safety attendant A remote operated safety attendant having a substantially pyramidic housing made of high impact material such as manufactured dense fiber. A two sided sign is mounted to a shaft positioned within the housing and connected to a drive motor and a remote signal receiver. A remote signal sender is used to send signals to the receiver to selectively actuate the drive mechanism which rotates to alternately display the opposed sides of the sign. The device meets requisite traffic safety requirements and allows an operator to remotely control the device to remain out of the pathway of vehicles that they are controlling through the signaling device.
US09601004B2	System and method for estimating energy consumption based on readings from an AMI network A method and system for estimating energy consumption of a utility population includes organizing the utility population comprising energy consumers into a plurality of groups. Next, a distribution of energy consumption against the plurality of groups may be calculated. Subsequently, statistically representative groups based on the energy distribution and the plurality of groups may be determined. Data is then collected from the statistically representative groups at predefined intervals from a communications network. Energy consumption of the utility population may then be estimated based on the data collected from the statistically representative groups. The communications network comprises an advanced metering infrastructure (AMI) network.
US09601003B2	Sensor and control systems for electrical machines A system for detecting sensor failure and/or operating with a failed sensor in an electrical machine includes an electrical machine, three or more sensors configured to connect to the electrical machine, and a sensor module operatively connected to each sensor to receive sensor signals from the sensors. The sensor module includes a failure detection module operatively connected to each sensor and configured to determine if each sensor is a failed sensor or a functioning sensor. The sensor module also includes a virtual sensor module operatively connected to the failure detection module and configured to output simulated sensor signals for the failed sensor, wherein the sensor module is configured to output the sensor signals for each functioning sensor. The system includes a control module operatively connected to the sensor module and the electrical machine to receive sensor signals and simulated sensor signals to control operation of the electrical machine.
US09601001B2	Systems and methods for handling trigger events Systems and methods for using multi-criteria state machines to manage alarming states and pre-alarming states of a hazard detection system are described herein. The multi-criteria state machines can include one or more sensor state machines that can control the alarming states and one or more system state machines that can control the pre-alarming states. Each state machine can transition among any one of its states based on sensor data values, hush events, and transition conditions. The transition conditions can define how a state machine transitions from one state to another. The hazard detection system can use a dual processor arrangement to execute the multi-criteria state machines according to various embodiments. The dual processor arrangement can enable the hazard detection system to manage the alarming and pre-alarming states in a manner that promotes minimal power usage while simultaneously promoting reliability in hazard detection and alarming functionality.
US09600996B2	Devices and methods for providing mobile cellular beacons Methods and devices are disclosed for providing audible, visual, and tactile alerts detectable by first responders in a geographic region impacted by a mass casualty event, such as a natural disaster or a terrorist attack. In certain aspects, an electronic device of an individual trapped within a damaged structure may establish wireless communications with a mobile cellular site and may receive a request to generate an alert audible to first responders. In response to the request, the electronic device may identify first device settings corresponding to the audible alert, and generate the audible alert in accordance with the obtained first device settings. In certain aspects, the audible alert may enable first responders to identify locations of victims trapped within structures damaged by the mass casualty event.
US09600995B2	Wearable electronic device to provide injury response Embodiments are generally directed to a wearable electronic device providing injury response. A wearable electronic device may include an injury detection unit that includes one or more sensors, and a central computing unit to receive sensor data from the one or more sensors to detect one or more injuries or potential injuries based at least in part on the received sensor data. The wearable electronic device further includes an injury response unit to provide a response to the one or more injuries or potential injuries.
US09600994B2	Portable monitoring devices and methods of operating the same In one aspect of the disclosed implementations, a device includes one or more motion sensors for sensing motion of the device and providing activity data indicative of the sensed motion. The device also includes one or more processors for monitoring the activity data, and receiving or generating annotation data for annotating the activity data with one or more markers or indicators to define one or more characteristics of an activity session. The device also includes one or more feedback devices for providing feedback, a notice, or an indication to a user based on the monitoring. The device further includes a portable housing that encloses at least portions of the motion sensors, the processors and the feedback devices.
US09600989B2	Detector unit with multiple integrated sensing systems and visually pleasing housing According to one embodiment, a multi-sensing hazard detector for detecting potential dangers may include a back plate and a front casing that is coupled with the back plate to define a housing. A circuit board and a plurality of components may be positioned within the housing. The circuit board may be communicatively coupled with the components. The components may include, among other components, an alarm device, an occupancy sensor, and a smoke chamber. The alarm device may be activatable upon the detection of a potential hazard to warn an occupant of a potential danger, the occupancy sensor may be configured to detect the presence and/or movement of objects external to the hazard detector, and the smoke chamber may be configured to detect the presence of smoke to cause a triggering of the alarm device. The housing may comprise a volume of less than 1024 cubic centimeters.
US09600987B2	Automated, remotely-verified alarm system with intrusion and video surveillance and digitial video recording An automated self-monitored alarm verification solution including at least a premises portion, a server portion, and an end user device portion. Alarm verification includes capturing by an image capture device at least one image in response to a detection event, and transmitting a first data signal including the image to a local signal processing device. The signal processing device transmits a second signal including at least a portion of the image to a remote hosted server according to at least a first set of predetermined parameters. After receiving the second signal, the server transmits a third signal including at least a portion of the image from the hosted server to a user device. Using the user device, a user views the image and indicates a validity status of the alarm based at least in part on the content of the image.
US09600986B2	Signalling system A signalling system comprises a first data signal source (10, 14), a first data signal receiver (12, 16) and a cable 18 comprising two or more wire pairs ({1,2}, {3,6}, {4,5}, {7,8}) coupling the first data signal source to the first data signal receiver. A portion of each wire pair is wound around a magnetic core (28). A further winding (30) is wound around the core (28). A further signal source (24) is coupled to the further winding (30) and a further receiver (36, 26) is coupled to the wires to receive the further signal. The windings around the core apply the further signal to the wire pairs as a common-mode signal. This allows the further signal to be transmitted to the further receiver without affecting the signal transmitted between the source (10, 14) and the receiver (12, 16) and with only minor modification of the cable (18).
US09600971B2	Second player electronic wagering system A wagering apparatus enables play of that game on an underlying electronic gaming apparatus. The apparatus includes: a) a first player position and input controls at the first player position; b) the processor is in communication with the first player input controls; c) a first player seat at each first player position; d) a second player input control associated with the player seat more distal from the gaming apparatus than the first player seat; e) the second player input control in communication with the processor and having second player input controls that enable wagering on any wagering game on the gaming apparatus; and f) the processor configured to accept wagers from both the first player input controls and the second player input controls and to resolve wagers from the first player input controls and the second player input controls based upon game outcomes on the gaming apparatus.
US09600969B2	Method and system for varying the take-out or rake rate on wagers placed in a wagering pool In a method of wagering, one or more primary bettors place wagers having an applicable base take-out or rake rate, and thus yielding a base payout for winning wagers. One or more secondary bettors may place wagers having an applicable modified take-out or rake rate (preferably lower than the base take-out or rake rate), thus yielding a higher payout for winning wagers than the base payout. The wagering may occur relative to card games such as poker, or other types of games or events, including sports betting. Bets may be placed with a host, such as a casino or track, or an off-track entity.
US09600967B2	Gaming system, gaming device and method for providing a progressive award including a quantity of free spins A slot machine issues a percentage of one or more progressive awards based upon any wager level (“Percentage Progressive”). In a preferred embodiment of the present invention, the Percentage Progressive concept operates as follows: The game displays the total progressive award amount; The player sets the wager; The game displays a Percentage Progressive value based upon the wager level; The player presses the spin button; The reels to spin and stop; The player collects credits for any winning combinations appearing on the reels, including pay table and progressive awards. In the event of a progressive award, the player receives the Percentage Progressive value*total progressive award amount. The preferred embodiment of the present invention, therefore, allows players to participate in progressive awards at any wager level.
US09600965B2	Method and apparatus for providing secondary gaming machine functionality A modified gaming machine includes a plurality of gaming machine peripheral devices for use in implementing one or more games to a player, and a master gaming controller configured to implement primary gaming machine functionality, including generating and transmitting information to the plurality of gaming machine peripherals. The modified gaming machine further comprises a secondary controller interposed between one or more of the plurality of gaming machine peripheral devices and the master gaming controller, whereby the secondary controller may forward information generated by the master gaming controller to the gaming machine peripheral devices and transmit secondary information to the peripheral devices.
US09600963B2	Gaming machine, gaming system, and gaming method presenting games with artificially intelligent players A gaming machine, system, and method for conducting a wagering game utilizing artificially intelligent players. A game is initiated by accepting a wager from a bettor at a gaming machine, displaying a plurality of artificially intelligent player profiles as potential players of a game at the gaming machine, and designating a matchup of at least two of the players for playing the game at the gaming machine. The bettor designates a selected player from the at least two players playing the game. The game is presented at the gaming machine. The RNG is utilized just for randomizing game pieces for playing the game. The artificially intelligent players determine the game play decisions. The game outcome between the artificially intelligent players is determined and wagers are paid out or collected according to the game outcome.
US09600957B2	Gaming system, gaming device and method for displaying multiple concurrent games using dynamic focal points The gaming system disclosed herein changes the focal point of a display device at different points in time to assist the player in focusing on different simultaneously or concurrently played games at different points in time. Specifically, the gaming system displays a plurality of simultaneously or concurrently played games on a display device. In response to a designated event occurring in association with a specific one of the plurality of simultaneously or concurrently played games, the gaming system changes the focal point of the display device to draw the player's focus or attention to that specific one of the simultaneously or concurrently played games. Put differently, the gaming system dynamically allocates and/or indicates different portions of a display device to different simultaneously or concurrently played games at different points in time to account for different events occurring in such simultaneously or concurrently played games.
US09600953B2	Authentication apparatus and method An authentication apparatus operative to determine the authenticity of an item comprising a film substrate responsive to detection that a portion of said item located in a measuring region of said apparatus has a predetermined birefringence characteristic, said apparatus comprising: an item detection arrangement operative to determine if at least a portion of an item is located in a measuring region of said authentication apparatus; and an optically-based birefringence measuring apparatus, wherein said authentication apparatus is operative to compare a measured birefringence characteristic with a predetermined birefringence characteristic and to produce an authenticity signal indicative of authenticity or otherwise of said item based upon said comparison, said apparatus further comprising a control means operative to control output of said authenticity signal from said apparatus responsive to determination, by said item detection arrangement, of presence or otherwise of said at least a portion of said item in said measuring region.
US09600951B2	Security element for marking or identifying objects and living beings A security element for marking, authenticating or identifying objects or living beings, such as people, animals or plants is provided that includes one or more layers of materials that are arranged next to or on top of each other or that overlap, which have security markings. At least one layer of the security element has, at least regionally, a crackle pattern in form of tears or cracks, nicks, wear areas or shrinkages and possible impurities, which can be scanned and detected together or separately as security features. A method for producing such a security element and to a use thereof for authenticating a person or an object, or for authorizing, triggering, continuing, carrying out and ending an action is also provided.
US09600949B2	Wireless key management for authentication Disclosed are methods, and devices for wireless key management for authentication. One method includes receiving a lock identifier from a locking device; determining that the lock identifier is associated with a user profile, wherein a user profile is authenticated and encrypted by a server using a lock key that is stored by the server and the locking device, and wherein the user profile comprises a user key; transmitting the user profile; decrypting the user profile using the lock key; transmitting a security code; generating an encrypted command comprising the security code and encrypted using the user key; transmitting the command; validating the command. Validating the command can include decrypting using the user key; determining whether the security code is valid; and authenticating using the user key; and initiating, in response to validating, an action of the locking device as specified by the command.
US09600948B2	Keyless entry apparatus A keyless entry apparatus includes: a vehicle-side device provided in a vehicle, the device including a vehicle-side transmitter that transmits a request signal and a vehicle-side receiver that receives an answer signal; and a mobile device including a mobile device receiver that receives the request signal and a mobile device transmitter that transmits the answer signal in accordance with the request signal. The vehicle-side device includes at least one modulator that modulates the request signal, the mobile device includes at least one demodulator that demodulates the request signal in accordance with the corresponding at least one modulator, and the request signal includes a signal modulated by the at least one modulator. Switching between modulation methods for the request signal is performed at at least one timing.
US09600947B2	Lock system, in particular for a motor vehicle A lock system including a first device which has at least two states and is embodied as a control device, and an associated second device which is embodied in the manner of an electronic key, an ID signal generator, a chip card or the like. The two devices have transmitters and/or receivers for, in particular, electromagnetic signals. In particular, at least one of the signals transmitted between the second device and the first device is an encoded operating signal for authenticating the second device, with the result that after positive evaluation of the transmitted operating signal in the case of an authorized second device it is possible to bring about a change in the state of the first device.
US09600944B1	Aircraft aerodynamic audit system for enhanced fuel efficiency An aerodynamic audit system is provided for performing an audit process of an aircraft using a computing device via a network. An inspection module inspects at least a portion of the aircraft for locating and measuring any aerodynamic defects present by generating an inspection list having a predetermined inspection path. A display device displays the inspection path and accepts a measurement of any located aerodynamic defect. A fuel penalty estimation module calculates an estimated fuel penalty of the aerodynamic defect based on the measurement of the corresponding aerodynamic defect. A defect correction analysis module analyzes the aerodynamic defect based on a cost and benefit assessment. A findings collection module generates an audit report based on the inspection and analysis of the aerodynamic defect. A database stores data associated with the aerodynamic defect and the corresponding fuel penalty based on the cost and benefit assessment.
US09600940B2	Method and systems for processing 3D graphic objects at a content processor after identifying a change of the object Method and systems for processing at least one three-dimensional (3D) graphic object include: identifying a change of 3D graphic objects, creating a message, assigning a unique identifier; and forwarding the message and the unique identifier to a scene engine. The change is made by an authoring tool. The message is embedded with change information corresponding to the change. The scene engine functions can be performed by the same or a different computing device as the computing device performing the authoring tool.
US09600934B2	Augmented-reality range-of-motion therapy system and method of operation thereof A server to perform a selected therapy on a user. The server may include a processor which may obtain activity information (AI) including information related to one or more of augmented-reality (AR) activity information, AR anatomical feature information, and range-of-motion (ROM) information; obtain user information including information related to one or more of the anatomy and physiology of the user; determine expected range-of-motion (EROM) information in accordance with the AI and the user information; track selected body parts (SBPs) of the user corresponding with the AR anatomical feature information; and/or render one or more augmented-reality limbs (ARLs) in relation with one or more corresponding SBPs of the user on a display of the system.
US09600931B2	Information processing device and program There is provided an information processing device including a control unit that controls generation of image information of three-dimensional space based on position information indicating a position of a terminal device and orientation information indicating an orientation of the terminal device, and an obtaining unit that obtains a request for a change related to the generation of the image information. The control unit controls the generation in a manner that first image information of the three-dimensional space corresponding to the position and the orientation is generated, and when obtaining the request, the control unit controls the generation in a manner that second image information of the three-dimensional space corresponding to the position, the orientation, and the change is generated.
US09600925B2	Calibration of multiple rigid bodies in a virtual reality system A virtual reality (VR) console receives slow calibration data from an imaging device and fast calibration data from an inertial measurement unit on a VR headset including a front and a rear rigid body. The slow calibration data includes an image where only the locators on the rear rigid body are visible. An observed position is determined from the slow calibration data and a predicted position is determined from the fast calibration data. If a difference between the observed position and the predicted position is greater than a threshold value, the predicted position is adjusted by a temporary offset until the difference is less than the threshold value. The temporary offset is removed by re-calibrating the rear rigid body to the front rigid body once locators on both the front and rear rigid body are visible in an image in the slow calibration data.
US09600920B2	Method and apparatus for creating animation message A method for creating an animation message includes generating input information containing information regarding input time and input coordinates according to input order of drawing information input through a touch screen; dividing an image containing the drawing information and background information into a plurality of blocks; creating an animation message by mapping the input information to the plurality of blocks so that the drawing information can be sequentially reproduced according to the input order; allocating a parity bit per pre-set block range of the animation message in order to detect an error occurring in the animation message; and transmitting the created animation message.
US09600917B2	Image processing device An image processing device may judge whether to execute a first type of enlarging process or a second type of enlarging process based on M lines of letter strings in an original image, in a case of judging to execute the first type of enlarging process, generate a first type of processed image data indicating a first type of processed image by executing the first type of enlarging process, and in a case of judging to execute the second type of enlarging process, generate a second type of processed image data indicating a second type of processed image by executing the second type of enlarging process. A layout of the plurality of letters in the second type of processed image is different from a layout of the plurality of letters in the first type of processed image.
US09600915B2	Cross-platform data visualizations using common descriptions The present invention extends to methods, systems, and computer program products for cross-platform data visualizations using common descriptions. Embodiments of the invention provide mechanisms for simplifying software development and enhanced code reliability. A user interface, along with interactive and dynamic characteristics, can be described (programmatically and/or declaratively) independently of any specific device platform. User interface qualities can be described using a generic scene graph structure with attached behaviors. The generic scene graph can then be used to drive the user interface on any number of different computing platforms using platform specific (e.g., rendering, gesture recognition, etc.) sub-systems. Platform specific sub-systems can vary based on technologies that are used by the platform specific sub-systems. For example, rendering sub-systems can vary based on the technology used to render graphical data, such as, for example, Open GL, XAML, Direct X, Quartz, etc.
US09600914B2	Layered two-dimensional projection generation and display An imaging system (10) generates a layered reconstructed radiograph (LRR) (66) of a subject. The system (10) takes as input a three-dimensional (3D) or higher dimensional data set (68) of the object, e.g. data produced by an image scanner (12). At least one processor (32) is programmed to define a set of two-dimensional (2D) projection images and associated view windows (60, 62, 64) corresponding to a set of voxel value (tissue) types with corresponding voxel value specification (50); determine the contribution of each processed voxel along each of a plurality of rays (72) through the 3D data set (68) to one of the predetermined voxel value (tissue) types in accordance with each voxel value with respect to the voxel value selection specification (50); and concurrently generate a 2D projection image corresponding to each of the voxel value specifications and related image view windows (60, 62, 64) based on the processed voxel values satisfying the corresponding voxel value specification (50). Each image is colorized differently and corresponding pixels in the images are aligned. An LRR (66) is generated by layering the aligned, colorized images and displaying as a multi-channel color image, e.g. an RGB image.
US09600912B2	Spatially corrected nuclear image reconstruction A medical imaging system (5) includes one or more processors and a display device (36). The one or more processors are programmed to receive (60) a first image (10) contrasting regions of tissue with a distinct radiotracer accumulation probability and generate (64) a constraint map (20) based on the regions of tissue with the distinct radiotracer accumulation probability. The one or more processors are programmed to reconstruct (70) a second image (44) with redistribution of a measured radiotracer based on the constraint map (20) and acquired image raw data (23) registered to the constraint map. The display device (36) displays the reconstructed second image.
US09600908B2	System and method for color paint selection and acquisition A method for paint color recommendation. The method obtains measures of an environment to be painted and trains a learned model to input data received from customers including data representing each customer's initial color paint and pigment selection, and one or more of: a customer perceptual, a customer context, and environment measure (P/C/E data) to generate a sparse matrix. One or more paint vendors may then use the generated sparse matrix to determine a color pigment recommendation from a pigments color space for a customer. From a user selected color/pigment, and using the learned model, the method maps the selection, together with the user's P/C/E data back to the color/pigments space. User feedback representing a degree of satisfaction that the recommended color pigment applied to the user environment has matched the user's initial color paint and color pigment selection is elicited.
US09600902B2	Image processing apparatus, image processing method, program and imaging apparatus An image processing apparatus with at least one circuit provided to perform a process of determining a candidate color region including at least a partial region in an image using color information of an input image signal, prompt a user to select an extraction color region in case a plurality of color regions are determined as the candidate color region, and perform image processing on at least one of the extraction color region of the input image signal and the remaining region of the input image signal excluding the extraction color region, to obtain an output image signal.
US09600900B2	Systems to measure yaw, spin and muzzle velocity of projectiles, improve fire control fidelity, and reduce shot-to-shot dispersion in both conventional and air-bursting programmable projectiles Systems to measure muzzle exit conditions of for ammunition improve fire control solutions and reduce shot-to-shot dispersion in both conventional and air-burst programmable ammunition. A first system measures muzzle velocity and, when firing “post-shot” programmable ammunition, the system calculates a unique time-of-flight optimized for the actual muzzle velocity and transmits the time to detonate signal by using either optically or radio-frequency signals that represent an optimized time of burst to a projectile. A second system measures muzzle velocity coupled to a ballistic calculator and, when used with ammunition having ferrous characteristics, the force is applied to exiting ammunition to slow or increase the muzzle velocity to a consistent, standardized target velocity. The systems are separately or in combination incorporated into kits that readily improve the performance of weapon systems.
US09600899B2	Methods and apparatuses for detecting anomalies in the compressed sensing domain A measurement vector of compressive measurements is received. The measurement vector may be derived by applying a sensing matrix to a source signal. At least one first feature vector is generated from the measurement vector. The first feature vector is an estimate of a second feature vector. The second feature vector is a feature vector that corresponds to a translation of the source signal. An anomaly is detected to in the source signal based on the first feature vector.
US09600893B2	Image processing device, method, and medium for discriminating a type of input image using non-common regions The invention provides an image processing device, an image processing method, and an image processing program capable of correctly discriminating a type of a test object, even when similar model images have been registered. The image processing device includes: a hardware that holds a feature amount obtained from model images of a plurality of reference objects belonging to mutually different types; a region determination module that determines a non-common region as a region indicating a feature amount different from those of other objects, within a model image of each object; and a discrimination module that discriminates which type an object included in an input image belongs to, by using a feature amount corresponding to a non-common region of the object out of feature amounts of objects.
US09600891B2	Web based fast query visualization of time-varying multi-variate vessel flow field by using uniform partition strategy A method for visualizing flow data from computation fluid dynamics (CFD) applications in 2-dimensions (2D) includes receiving a 3-dimensional (3D) image volume from a CFD simulation of fluids flowing through vessels in a patient that is a snapshot of a fluid flow in the vessels at a certain time, subdividing the 3D image volume into 3D data blocks, minimizing a sum over a matrix of energy interactions defined for each pair of data blocks in the 3D image volume, where the minimization preserves a local shape of the vessels, where minimizing the sum over the matrix of energy interactions is performed on a graphics processing unit (GPU), and using the minimized energy interaction matrix to display on a monitor a 2D sketch of the 3D image volume, where the 2D sketch is displayed in real-time with respect to the time scale of the CFD simulation.
US09600888B2	Image processing device, image processing method, and program A plurality of processes for emphasizing a stereoscopic effect of an image is supposed and a plurality of stereoscopic effect emphasis processes is integrated in a mode suitable for the image.An image processing device is provided with a stereoscopic effect emphasis processing unit and an integration processing unit. The stereoscopic effect emphasis processing unit executes a plurality of stereoscopic effect emphasis processes on an input image. The integration processing unit integrates results of a plurality of stereoscopic effect emphasis processes according to an integration coefficient used when a plurality of stereoscopic effect emphasis processes is integrated obtained by analyzing the input image. This may be further provided with an image analyzing unit which analyzes the input image to generate the integration coefficient used when a plurality of stereoscopic effect emphasis processes is integrated.
US09600885B2	Temporal anatomical target tagging in angiograms An image processing apparatus and method take as input a pre-op reference image (OP) and a stream (A) of angiographic images (A1-A3). Based on multiple pre-defined regions of interest (ROIa-c) in the pre-op reference image (PO), the angiographic image best showing when displayed a respective one of the regions of interest (ROIa-c) is detected from among the stream (A) of angiographic images (A1-A3). The detected angiographic image is associated with the region of interest to form an associative data structure (DS). A graphical user interface (GUI) is generated that allows based on the associative data structure (DS) to retrieve the associated angiography upon a user selecting any one of the regions of interest (ROIa-c) on the graphical user interface (GUI).
US09600882B2	Multi-study medical image navigation A medical image navigation system (2) includes a viewport module (4), a proximity module (26), a visualization module (28) and a matching module (34). The viewport module (4) navigates a plurality of image slices of a study and based on input from at least one input device selects at least one image which is displayed and any annotations associated with the selected at least one image on a display device. The proximity module (26) for the selected image slice returns at least one proximate annotation, if available. The visualization module (28) for the returned at least one proximate annotation visualizes the at least one proximate annotation which is displayed by the viewport module on the selected at least one image. A matching module (34) retrieves for display an image slice in one study which corresponds to a displayed image slice from another study.
US09600881B2	Methods, systems and computer readable storage media storing instructions for imaging and determining information associated with regions of the brain Methods, systems and computer-readable storage mediums relate to imaging techniques of a region, for example, the brain, with magnetization transfer contrast (MTC°) effects with less specific absorption rate (SAR). The methods, systems and computer-readable storage mediums may include acquiring MR image data from at least one magnetic resonance (MR) scan that includes a pre-pulse signal and a pulse sequence. The pre-pulse signal may be less than 500°, e.g., from about 150° to 425°, and the pulse-sequence may be a gradient echo based sequence. The methods, systems and computer-readable storage mediums may include generating information associated with an image of at least one region of a subject. The information may include quantitative or qualitative information of a region of a brain. The quantitative information may include volume information, contrast to noise ratio information, number of voxels, as well as other information.
US09600880B2	Method and system for qualifying a surgical clip applier A method and system for qualifying a surgical clip applier with surgical clips are proposed. After successive firing operations of the surgical clip applier, an image capture unit captures sampling images associated respectively with angularly equidistant radial recesses in a rotatable clip-receiving disk for receiving anything fired from the surgical clip applier. Upon determining that each sampling image contains an individual target image portion showing a single fired surgical clip, a processing unit verifies the qualification of the surgical clip applier based on a predetermined specification and characteristic parameters obtained respectively from the individual target image portions and associated respectively with the surgical clips, which are received respectively in the radial recesses.

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