| Document | Document Title |
|---|---|
| US09577772B2 |
Measuring device and measuring method for dynamically measuring carrier aggregation signals
A measuring device for measuring a response of a device under test to a carrier aggregation signal is provided. The measuring device comprises a signal generator configured to generate the carrier aggregation signal, which comprises a first carrier signal and/or a second carrier signal. The measuring device comprises a control unit configured to control the signal generator to user-selectably, individually and dynamically, activate and deactivate the carrier signals within the carrier aggregation signal. |
| US09577769B2 |
Built-in self-test technique for detection of imperfectly connected antenna in OFDM transceivers
An OFDM communication transceiver, which is configured to test its connection with an antenna circuit unit, has a receiver chain and an emitting chain. The receiver chain includes a time-to-frequency transform unit and the emitting chain includes a frequency-to-time transform unit. The transceiver further includes means for disconnecting the receiver chain to the antenna circuit unit, means for providing a stimulus as input to the emitting chain, means for reintroducing the signal at the output of the emitting chain as an input of the receiving chain, means for determining a circuit resonance frequency, Fr, and a quality factor, Q, of a transfer function computed from the output of the time-to-frequency transform unit, and means for deciding about the connection of said antenna circuit unit according to the resonance frequency and the quality factor. |
| US09577766B2 |
Grid-controlled X-ray source and space X-ray communication system and method
The disclosure relates to a grid-controlled X-ray source, a space X-ray communication system and a space X-ray communication method. The structure of the grid-controlled X-ray source is: one end of the filament is grounded and the other end is connected with the anode of a power supply, the thermionic cathode is located at the side of the filament and the emergence hole thereof faces the filament, the modulation grid is an electrode plate with a small hole which faces the emergence hole of the thermionic cathode, the electronic beam focusing electrode is located on the two sides of the small hole of the modulation grid to form a focusing channel facing the small hole, an electronic beam is focused by the electronic beam focusing electrode and then transmitted to the metallic target anode, wherein the transmitting surface of the metallic target anode faces the outlet of the focusing channel and the other surface is connected with the anode of the power supply, and the output window is located on an reflection path of the electronic beam which is from the metallic target anode. The disclosure solves the technical problems that the signal-to-noise ratio of communication is low, the error rate error rate of communication is high and the speed of communication is low when an X ray is used for implementing communication in the conventional art, and has the advantages of long communication distance and the low error rate of communication. |
| US09577765B2 |
Article storage facility and method of operating same
A main controller controls carry in operations and carry out operations of articles to or from an article storage rack using article transport devices by causing a control command to be transmitted from a first optical communication device that is associated with each article transport device to a second optical communication device provided to each article transport device. The main controller is configured to perform a temporally-divided light-emission control in which a plurality of the first optical communication devices are caused to emit light in a temporally divided manner such that there is only one first optical communication device that emits light in any one time period among the first optical communication devices that are located close to one another in the vertical direction. |
| US09577760B2 |
Pulsed light communication key
A Universal Serial Bus (USB) key may include an optical transceiver having a USB interface for engagement to an electronic device such as a laptop computer or other USB-configured device. The USB key may include a converter or buffering, isolation, modulation or amplification circuitry. The USB key sends and receives data signals which may be carried upon an optical transmission as generated by an LED light source which in turn is in communication with a host device such as a network processor. The USB key may also include operational amplifiers (op-amps) and transistor amplifiers. |
| US09577754B2 |
Nonradiative communication terminal and communication system using visible light for communication
A nonradiative communication terminal and a communication system which use visible light for communication are provided. The nonradiative communication terminal includes a visible light emission module, a visible light reception module, and a central processing unit. The visible light emission module and the visible light reception module are connected with the central processing unit. By using visible light to communicate with other visible light communication terminals, the advantages, such as nonradiation, saving frequency resources, stability and reliability in communication performance, low-cost communication, and high transmission speed are achieved. |
| US09577752B1 |
Wirelessly powered passive optical power meter
Systems and apparatus for a wirelessly-powered passive optical power meter device. In one aspect, an optical power meter device comprises a power circuit connected to one or more antennas, the circuit including an RF to DC converter that generates a DC power signal that provides a DC power source for the optical power meter from an RF signal received by the one or more antennas, a photodetector that generates a power measurement signal that measures the power of the optical input signal, and a communication circuit that is connected to the one or more antennas, the photodetector, and the power circuit that when powered by the DC power source generates a modulation signal that is responsive to the power measurement signal and that causes the one of the one or more antennas to convey the power measurement signal to a reader device that is transmitting the RF signal. |
| US09577750B2 |
Multifunctional micro sensor system
A measurement device relates to a Halios system for measuring an optical transmission path, in which at least one receiver and a compensation transmitter are optically separated from each other by an optical barrier in such a matter that a direct irradiation of said receiver by said compensation transmitter is not possible. Said compensation transmitter and a transmitter are of the same type and/or have at least a common electric optical working point in an optical working point. Said optical barrier has a compensation path, characterized by a compensation window, which attenuates the light of the compensation transmitter before it hits the receiver in such a manner that the compensation transmitter and said transmitter are operated at least in an optical working point by a controller in said identical electro-optical working point. |
| US09577743B2 |
Communications system having a secure credentials storage device
The invention relates to a communication system comprising a terminal (10), a first device (1) adapted to exchange data with said terminal (10), a second device (2) adapted to exchange data with said terminal (10), characterized in that it comprises means for pairing said first (1) and second (2) devices so as said second device (2) exchanges data with said terminal (10) through said first device (1). |
| US09577740B2 |
Radio communication system and communication method
A communication system includes a plurality of DeNBs (base stations) and a plurality of RNs (relay nodes), wherein each RN has a radio connection with a DeNB. Each DeNB acquires time resource configuration applied between another base station and a relay node connected with said another base station. |
| US09577739B2 |
Communication devices, mobile terminal, in a cooperative communication system
A communication device that is capable of communicating with a mobile terminal in cooperation with another communication device, and is capable of communicating with the mobile terminal via the other communication device. This communication device characteristically includes: a mode selecting unit configured to select one of a cooperative communication mode and a relayed communication mode, the cooperative communication mode being for transmitting notification information to the mobile terminal, the notification information being for causing the other communication device to perform a cooperative communication, the relayed communication mode being for causing the other communication device to relay notification information to the mobile terminal; and a mode information transmitting unit configured to transmit mode information to the other communication device, the mode information indicating a result from the mode selecting unit. |
| US09577737B2 |
Antenna apparatus and method for beam forming thereof
Provided is an antenna apparatus equipped with a single RF chain. The antenna apparatus includes: a combiner configured to divide omnidirectional space into N sectors to perform a sector sweep, combine a reception signal received via the single RF chain for each sector and calculate a gain of a composite signal; a comparator configured to determine a gain magnitude of the composite signal; and a controller configured to perform a beam-forming according to a comparison result of the gain magnitude of the comparator. |
| US09577735B2 |
Method for transmitting a signal in multi-antenna communication system
A multi-input multi-output (MIMO) system considers either reliability for each antenna or a time/frequency location, and transmits a signal at an unequal ratio for each antenna according to the consideration result. The method for use in the MIMO system including multiple antennas includes processing a signal according to an unequal ratio transmission scheme employing the multiple antennas at an unequal ratio, and transmitting the processed signal via the multiple antennas. |
| US09577731B1 |
Radio frequency communication with antenna index coding
The inventors have recognized that in RF communication systems, by switching between transmit antennas of an RF transmitter on a sub-symbol basis (antenna index coding), and/or by adaptively determining how often antenna switching occurs (adaptive antenna hopping), an increased amount of data may be wirelessly transmitted to an RF receiver without significantly increasing energy consumption. The inventors have determined that in certain systems, such as ZigBee, data symbols consist of elementary waveform patterns, and that such waveform patterns for transmit antennas may be stored by an RF receiver for later determining transmit antennas for data symbols. The inventors have also determined that the invention may be applied in the frequency domain, such as to OFDM, by storing subcarrier waveform patterns for particular transmit antennas and later determining transmit antennas for subcarriers of data symbols. |
| US09577727B2 |
Enforcing station fairness with MU-MIMO deployments
A non-transitory computer readable medium including instructions which, when executed by one or more hardware processors, causes performance of operations. The operations include: obtaining a first pathloss value for a first data transmitted between a first device and a second device; receiving, at a first component of the first device, a second data to be transmitted to the second device; based at least on the first pathloss value: selecting a first subset of the second data for transmission from the first component to a second component of the first device, where the second component is configured for causing transmission of the first subset of the second data to the second device; transmitting, during a first period of time from the first component to the second component, the first subset of the second data. |
| US09577719B2 |
Wireless device and near-field wireless communication method
The data to be supposed to be processed by a microcontroller unit (MCU) of the near-field wireless communication module in a wireless device is processed by a digital signal processor (DSP) of the module instead of the MCU in order to expedite processing of commands. |
| US09577718B2 |
Systems and methods for inductively coupled communications
A method for inductively coupled communications is described. The method includes generating a retransmitted modulated signal that is stronger than a received signal from a first device. The method also includes generating a suppressed carrier signal from the retransmitted modulated signal for retransmission to the first device. The method further includes filtering a superimposed signal of the suppressed carrier signal on the received signal to attenuate modulation sidebands. The method additionally includes synchronizing to the first device based on the filtered signal. |
| US09577716B2 |
Avoiding NFC communication collisions between accessories and user equipment
An accessory for a user equipment (UE) includes a housing and a near field communication (NFC) circuit. The housing is slid on the UE to become attached in a stored position relative to the UE. The NFC circuit is attached at a location on the housing and configured to become powered by inductive coupling to signals emitted by another NFC circuit within the UE to temporarily operate to transmit data to the other NFC circuit within the UE as the accessory NFC circuit passes over the other UE NFC circuit while the housing is being slid on the UE before reaching the stored position relative to the UE. While the housing is in the stored position relative to the UE, the NFC circuit may be configured to be inhibited from transmitting data to the other NFC circuit within the UE irrespective of whether the other NFC circuit within the UE is emitting signals to attempt to provide inductive coupling to the NFC circuit. |
| US09577711B2 |
Display device, method of operating a display device, and computer program product
There is provided a display device comprising a processing unit, a display unit coupled to the processing unit and a near field communication unit coupled to the processing unit, wherein said processing unit is arranged to synchronize display messages to be displayed by the display unit with corresponding near field communication messages to be stored in the near field communication unit. Furthermore, a corresponding method of operating a display device is conceived. Furthermore, a corresponding computer program product is provided. |
| US09577703B2 |
System and method for low density spreading modulation detection
In one embodiment, a method for blindly detecting low density activity includes receiving, by a first node from a second node, a signal and executing a joint message passing algorithm (JMPA) on the signal, where executing the JMPA includes jointly producing a decoded signal and an activity list in accordance with the decoded signal, and calculating a plurality of a priori probabilities in accordance with a plurality of log likelihood ratios (LLRs) corresponding to the signal and a plurality of decoded LLRs. |
| US09577701B2 |
Reconfigurable communication device and method
A communication device includes a transmitter operable to couple to a plurality of transceivers via a plurality of transmission channels, transmit payload data via the plurality of transmission channels, and obtain monitored transmission conditions for one or more transmission channels in the plurality of transmission channels. During operation, the transmitter is further operable to generate reconfiguration request signals resultant from processing the monitored transmission conditions and transmit the reconfiguration request signals on transmission channels in the plurality of transmission channels. |
| US09577700B2 |
Radio with asymmetrical directional antenna sub-arrays
An intelligent backhaul radio that has an advanced antenna system for use in PTP or PMP topologies. The antenna system provides a significant diversity benefit. Antenna configurations are disclosed that provide for increased transmitter to receiver isolation, adaptive polarization and MIMO transmission equalization. Adaptive optimization of transmission parameters based upon side information provided in the form of metric feedback from a far end receiver utilizing the antenna system is also disclosed. |
| US09577699B2 |
Dual antenna topology for bluetooth and IEEE 802.11 wireless local area network devices
A method includes determining that an antenna shared between a Bluetooth transceiver and a WLAN transceiver is available to the WLAN transceiver based on an activity signal associated with the Bluetooth transceiver. Access to the shared antenna is provided to the WLAN transceiver based on the determination, and the WLAN transceiver is configured to use diversity in transacting WLAN signals via a plurality of antennas, including the shared antenna. Access to the shared antenna is transferred from the WLAN transceiver to the Bluetooth transceiver based on the activity signal. |
| US09577694B1 |
Support structure to enable use of tablet computer by persons with limited manual dexterity
A system and method provide a stable support for a portable electronic device such as a tablet computer, a personal digital assistant, a smartphone, or the like. The system includes a support structure that rests on a table, a tray or other platform positioned proximate to a person using the portable electronic device. The support structure has a non-skid base positioned on the platform and has an upper surface positioned at a selected angle with respect to the base. The upper surface includes a recess that receives a configuration frame (or insert). The configuration frame includes an opening to receive and retain the portable electronic device. The configuration frame is rotatable to at least two positions to orient the portable electronic device in at least two orientations (e.g., portrait and landscape) with respect to the person. In certain embodiments, the presentation angle of the upper surface is variable. |
| US09577693B2 |
Bluetooth headset and wristwatch including the same
A wristwatch includes a watch body having a display part on an upper surface thereof and having a seating part at an outline part of the display part, and a Bluetooth headset including a sound output unit that outputs sound information received from a master terminal, having a shape corresponding to an outline part of the display part to surround the display part, seated in the seating part, and installed to be attached to and detached from the watch body, the Bluetooth headset being a slaver terminal of the master terminal that functions as a body case or a bezel of the watch body. |
| US09577691B2 |
Front end circuit
A front end circuit includes a switch including a common terminal and a plurality of individual terminals, in which at least two kinds of reception signals of different frequency bands are input to the common terminal, and in which one of the at least two kinds of reception signals is output to an individual terminal selected from the plurality of individual terminals, and in which a non-selected terminal is grounded, and a balun including a first terminal and a second terminal defining unbalanced ports as well as a third terminal and a fourth terminal defining balanced ports. The first individual terminal of the switch is indirectly connected to the first terminal of the balun and the second individual terminal of the switch is indirectly connected to the second terminal of the balun. The at least two kinds of reception signals are output in a balanced mode from the third terminal and the fourth terminal of the balun. |
| US09577689B2 |
Apparatus and methods for wide bandwidth analog-to-digital conversion of quadrature receive signals
Apparatus and methods for analog-to-digital conversion of quadrature receive signals are provided herein. In certain implementations, a transceiver system includes at least a first pair of analog-to-digital converters (ADCs) associated with a first quadrature receiver channel and a second pair of ADCs associated with a second quadrature receiver channel. The first and second pairs of ADCs can provide analog-to-digital conversion of the same receive signal, but can have different noise profiles relative to one another, such as a low pass noise profile and a band pass noise profile. The transceiver system can further include a reconstruction filter for combining the outputs of at least the first and second pairs of ADCs to generate output signals associated with a lower overall noise profile relative to that of either pair of ADCs alone. |
| US09577687B2 |
Multiple interferer cancellation for communications systems
An interference cancellation system (ICS) may be used with a communication system to prevent or minimize interference from one or more sources. The ICS may receive radio RF signals comprised of one or more signals of interest (SOI) and multiple interfering signals. The ICS may use a sample of the interfering signals to cancel the interfering signals from the SOI. The multiple interfering signals may be converted into a single optical signal for cancellation. One or more optical cancellation paths may be used for interference cancellation. Each optical cancellation path may include an optical attenuator and/or an optical delay to achieve phase shifts and/or delays for interference cancellation. |
| US09577685B1 |
Pre-distortion calibration
A system includes baseband circuitry and a transmitter. The electrical behavior of the transmitter may cause distortion effects in the transmit output of the transmitter during transmissions based on input signals from the baseband circuitry. The baseband circuitry may reference a calibration evaluation function for multiple transmit variables to pre-distort the input signal to compensate for the distortion effect. Pre-distortion calibration logic may generate the evaluation function using a one-dimensional calibration technique. The evaluation function may facilitate the baseband accessing calibration data without necessarily relying on a look-up table. In some cases, a one-dimensional calibration for multiple transmit variables may use fewer calibration points than a similarly accurate multi-dimensional calibration. |
| US09577682B2 |
Adaptive forward error correction (FEC) system and method
In a network for reliable transfer of packets from a transmitter to a receiver using an Internet Protocol (IP), a system for packet recovery comprising a detection block (detector) for packet loss detection and a probe device (probe) for Forward Error Correction (FEC) packets transmission, wherein the detector includes means for sending a missing packet report to the probe upon detecting a missing packet, wherein the probe includes means for storing received packets, sending FEC packets and adapting a size of the FEC packets to an error rate computed from the missing packet reports, wherein the size of FEC packets is made larger or smaller responsive to the error rate increasing or decreasing, respectively, and wherein the probe is located close to the transmitter for reliable packets reception and the detector is located close to the receiver for reliably detecting loss of packets in a receiver's surroundings. |
| US09577681B2 |
Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 256-symbol mapping, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping. |
| US09577679B2 |
Transmitting apparatus and signal processing method thereof
A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding, an interleaver configured to interleave the LDPC codeword, and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver performs interleaving by dividing the LDPC codeword into a plurality of groups, rearranging an order of the plurality of groups in group units, and dividing the plurality of rearranged groups based on a modulation order according to the modulation method. |
| US09577675B1 |
System and method for encoding user data with low-density parity-check codes with flexible redundant parity check matrix structures
A system including a first module, a second module and a third module. The first module is configured to generate a first parity check matrix. The second module is configured to append an appended matrix to the first parity check matrix to generate a resultant parity check matrix. The appended matrix includes additional elements. The third module is configured to receive user data and encode the user data based on the resultant parity check matrix. |
| US09577672B2 |
Low density parity-check code decoder and decoding method thereof
The present disclosure illustrates a low density parity-check code decoder adapted for decoding coding data having bit nodes and check nodes. The decoder includes a calculation module and a memory. The calculation module includes k calculation units and n shift units, and the memory includes n memory units. The memory is coupled to the calculation module. Each shift unit is one-to-many coupled to the k calculation units. The n memory units are coupled to the n shift units. The calculation module operatively divides the coding data into n first-bit-strings. The ith calculation unit operatively generates a second-bit-string by calculating ith bits of the n first-bit-strings. The jth shift unit operatively generates a third-bit-string upon receiving jth bits of the k second-bit-strings, and shifts the third-bit-string. The memory units are configured for storing the n shifted third-bit-strings respectively. |
| US09577666B2 |
Method and system
A method includes: setting a first and a second storage regions; first creating a first compression code of a compression target data in a file using a identifier indicating the data in the first storage region when a predetermined first consistency between the compression target data and the data in the first storage region is detected; comparing the compression target data with data in the second storage region when the predetermined first consistency between the compression target data and the data in the first storage region is not detected, the compression target data being moved to the second storage region after the comparing; and storing the compression target data into the first storage region associated with a identifier indicating the data in the first storage region when a predetermined second consistency between the compression target data and the data in the second storage region is detected. |
| US09577657B1 |
Delta sigma patterns for calibrating a digital-to-analog converter
A digital to analog converter (DAC) maps a digital word to an analog output. The DAC bits may have amplitude and timing errors. These errors (or sometimes referred herein as “non-idealities”) result in distortion and degradation of the dynamic range in DACs. To reduce these negative effects, delta-sigma patterns can be provided to two bit cells, a reference bit cell and a bit cell under calibration, to perform, e.g., amplitude calibration and timing skew calibration. Delta-sigma patterns are particularly advantageous over square wave signals, which cannot be scaled to perform amplitude calibration between bit cells having different bit weights and are limited in frequency to integer fractions of the sampling clock. |
| US09577655B2 |
Method and system for time interleaved analog-to-digital converter timing mismatch estimation and compensation
Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is aliased onto a desired signal by a timing offset in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal. A decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals. A multiplier may be configured to cancel the blocker signal utilizing the determined complex coupling coefficients. |
| US09577652B2 |
Atomic resonance transition device, atomic oscillator, electronic apparatus, and moving object
An atomic resonance transition device includes a gas cell having an internal space that seals an alkali metal, a light emitter that emits excitation light containing a resonance light pair that causes the alkali metal to resonate toward the alkali metal, and a magnetic field generator that applies a magnetic field to the alkali metal. The excitation light diverges in a width direction in the internal space as the light travels from a side where the excitation light is incident toward a side where the excitation light exits, and the magnetic field from the magnetic field generator has a portion where the intensity of the magnetic field increases in the internal space with distance from the side where the excitation light is incident toward the side where the excitation light exits. |
| US09577648B2 |
Semiconductor device and method for accurate clock domain synchronization over a wide frequency range
A clock synchronization circuit has a clock sync detector. A first variable delay circuit is coupled to a first input of the clock sync detector. A controller is coupled to a digital output of the clock sync detector and a control input of the first variable delay circuit. A first clock signal is coupled to the first variable delay circuit. A second clock signal is coupled to a second input of the clock sync detector. The clock sync detector includes a first flip-flop and a first delay element coupled between the first variable delay circuit and a data input of the first flip-flop. A second variable delay circuit is coupled to a second input of the clock sync detector. A multiplexer is coupled between the first variable delay circuit and the first input of the clock sync detector. An offset compensation calibrates the clock sync detector. |
| US09577647B2 |
Systems and methods for temperature compensated oscillators having low noise
A voltage controlled oscillator arrangement is disclosed. The arrangement includes a voltage controlled oscillator and a bypass component. The voltage controlled oscillator has an output and a tuning port. The output provides an output signal at an operating frequency. The tuning port is configured to select the operating frequency according to an applied voltage. The voltage controlled oscillator has active portions and inactive portions. During the active portions, the output signal is at a non-zero value. The bypass component is configured to apply a bypass compensating signal to the tuning port during the active portions of the voltage controlled oscillator. The bypass compensating signal compensates for an oscillator temperature of the voltage controlled oscillator. |
| US09577646B1 |
Fractional phase locked loop (PLL) architecture
In one embodiment, method for frequency division comprises propagating a modulus signal up a chain of cascaded divider stages from a last one of the divider stages to a first one of the divider stages, and, for each of the divider stages, generating a respective local load signal when the modulus signal propagates out of the divider stage. The method also comprises, for each of the divider stages, inputting one or more respective control bits to the divider stage based on the respective local load signal, the one or more respective control bits setting a divider value of the divider stage. |
| US09577644B2 |
Reconfigurable logic architecture
According to one general aspect, an apparatus may include a plurality of stacked integrated circuit dies. The dies may include a memory cell die configured to store data in a random access fashion. The dies may also include a look-up table die comprising a random access memory array that, in turn, includes a reconfigurable look-up table. The reconfigurable look-up table may be configured to perform a logic function. The reconfigurable look-up table may include a plurality of random access memory cells configured to store a look-up table to perform a logic function, and a local row decoder configured to activate one or more rows of memory cells based upon a set of input signals. The look-up table stored in the plurality of memory cells may be configured to be dynamically altered via a memory write operation to the random access memory array. |
| US09577641B2 |
Spin transfer torque based memory elements for programmable device arrays
Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory. |
| US09577640B1 |
Flexible, space-efficient I/O circuitry for integrated circuits
Flexible, space-efficient I/O architectures for integrated circuits simplify circuit design and shorten design times. In one aspect, cells for power supply pads are eliminated, in part by locating ESD circuitry for these pads underneath the pads themselves, leaving only signal I/O buffers. Pads coupled to the signal I/O buffers may be defined as either signal I/O pads or power supply pads in accordance with customization circuitry. Customization circuitry also provides for flexible bank architectures, where signal I/O buffers within a bank share power supply requirements that may be different from another bank. The number of banks and the number of signal I/O buffers belonging to each bank is flexibly defined. In other aspects, ESD circuitry is provided at corners of the IC layout and optionally within selected I/O slots. Decap circuitry is provided at an outer edge of the IC layout and is scalable in order to meet different requirements. |
| US09577639B1 |
Source separated cell
A MOS device includes a first MOS transistor having a first MOS transistor source, a first MOS transistor drain, and a first MOS transistor gate. The MOS device also includes a second MOS transistor having a second MOS transistor source, a second MOS transistor drain, and a second MOS transistor gate. The second MOS transistor source and the first MOS transistor source are coupled to a first voltage source. The MOS device includes a third MOS transistor having a third MOS transistor gate, the third MOS transistor gate between the first MOS transistor source and the third MOS transistor source, the third MOS transistor further having a third MOS transistor source and a third MOS transistor drain, the third MOS transistor source being coupled to the first MOS transistor source, the third MOS transistor drain being coupled to the second MOS transistor source, the third MOS transistor gate floating. |
| US09577636B1 |
Substate bias voltage generation circuits and methods to control leakage in semiconductor memory device
A semiconductor device may be provided. The semiconductor device may include a first switching control signal generation circuit configured to generate a first switching control signal which is enabled in synchronization with a time when a first delay period has passed from a time when a power-down mode is entered. The semiconductor device may include a second switching control signal generation circuit configured to generate a second switching control signal which is enabled during a period from a time when a read operation mode or a write operation mode is entered to a time when a second delay period has passed. |
| US09577635B2 |
Clock-gating cell with low area, low power, and low setup time
A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock. |
| US09577631B2 |
Single pole multi-throw switch
A single-pole multi-throw switch includes a set of selection switches. The set of selection switches includes a set of primary switches, a first set and a second set of secondary switches. The primary set of switches includes a plurality of primary transistors coupled in series for transmitting radio frequency signals. The first set of secondary switches is coupled to the primary set of switches and includes a plurality of first secondary transistors coupled in series for transmitting the radio frequency signals when the primary transistors and the first secondary transistors are turned on. The second set of secondary switches is coupled to the primary set of switches and includes a plurality of second secondary transistors coupled in series for transmitting the radio frequency signals when the primary transistors and the second secondary transistors are turned on. |
| US09577630B2 |
Adaptive system controlled power supply transient filter
An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on reset and the variable power supply filter. The control logic is configured to activate the variable power supply filter based on a core domain of the electronic device being active. |
| US09577623B2 |
Capacitive parametric zero crossing detector device, circuit and method
A capacitive parametric zero crossing detection circuit has a nonlinear voltage controlled capacitive device coupled to an input voltage to convert a zero crossing current pulse into zero crossing voltage signal. |
| US09577620B2 |
Printed circuit arrangement and method of forming the same
In various embodiments, a printed circuit arrangement may be provided. The printed circuit arrangement may include a processor circuit. The printed circuit arrangement may further include a printed main circuit arrangement in electrical connection with a first input node of the processor circuit. The printed main circuit arrangement may be configured to receive at least one input signal and generate a main circuit signal based on the at least one input signal after a first delay from receiving the at least one input signal. The printed circuit arrangement may further include a printed reference circuit arrangement in electrical connection with a second input node of the processor circuit. The printed reference circuit arrangement may be configured to receive a further input signal, may have a second delay and may be configured such that the second delay adapts to the first delay. |
| US09577615B1 |
Circuits for and methods of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking
A circuit for reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is described. The circuit also comprises a plurality of circuit elements that enable the routing of data generated at outputs of the circuit elements; a plurality of register circuits that store data at outputs of the plurality of circuit elements; a clock circuit routing a clock signal to clock inputs of the plurality of register circuits; and a pulsed-controlled register circuit coupled to an output of a circuit element and generating a pulsed output coupled to a clock input of a register of the pulse-controlled register circuit; wherein the pulsed output is coupled to the clock input of the register to enable the pulse-controlled register circuit to store data at a time that is different than an edge of the clock signal. A method of reducing duty-cycle distortion in an integrated circuit implementing dual-edge clocking is also described. |
| US09577613B2 |
Dual loop voltage regulator based on inverter amplifier and voltage regulating method thereof
A voltage regulator includes a pass element, a buffer, and an error amplifier. The voltage regulator further includes a fast push-pull driver that has an inverter type amplification structure, is connected between a power output and a control input of the pass element, and reduces positive and negative peaks of the power output at a speed faster than a speed of a main feedback loop. |
| US09577611B2 |
Controlling clock input buffers
An integrated circuit may have a clock input pin coupled to a buffer (24). The buffer may supply a clock signal (28) to an integrated circuit chip such as the memory. To conserve power, the buffer is powered down. When ready for use, the buffer is quickly powered back up. In one embodiment, in response to a predetermined number of toggles Of the clock signal, the buffer is automatically powered up. |
| US09577608B2 |
Discrete time lowpass filter
A discrete time (DT) lowpass filter having various advantages is described. In an exemplary design, the DT lowpass filter includes a decimating DT filter (which may include a passive DT FIR filter and/or a passive DT IIR filter) and an active DT filter. The decimating DT filter receives a first DT signal at a first sample rate, filters and decimates the first DT signal by a factor of N, and provides a second DT signal at a second sample rate lower than the first sample rate. N may be greater than one. The active DT filter filters the second DT signal and provides a third DT signal at the second sample rate. A sampler samples a continuous time signal and provides the first DT signal. The sampler may further double the voltage of the first DT signal relative to the voltage of the continuous time signal. |
| US09577603B2 |
Solidly mounted acoustic resonator having multiple lateral features
A solidly mounted resonator (SMR) includes an acoustic resonator on a substrate, the acoustic resonator having multiple acoustic impedance layers having different acoustic impedances, respectively. The SMR further includes a bottom electrode on a top acoustic impedance layer of the plurality of acoustic impedance layers, a piezoelectric layer on the bottom electrode, a top electrode on the piezoelectric layer, and multiple lateral features on a surface of the top electrode. The lateral features include multiple stepped structures. |
| US09577601B2 |
Broadcast serial bus termination
A subsea broadcast serial bus system includes a broadcast serial bus having a first signal line and a second signal line. One or more nodes are connected in parallel to the first signal line and the second signal line of the broadcast serial bus. Each node connects the first signal line to the second signal line via a node impedance. A subsea node connected to the broadcast serial bus includes an adjustable impedance that may be adjusted based on the number of nodes connected to the broadcast serial bus. |
| US09577600B2 |
Variable load for reflection-type phase shifters
Methods and systems for phase shifting include a hybrid quadrature coupler having an input, an output, and two termination loads. Each termination load includes multiple terminations, each termination having a varactor; and one or more transmission lines separating the terminations. A control module is configured to determine a phase shift and gain to apply to the input and to independently control a capacitance of each varactor such that the output of the hybrid quadrature coupler is shifted by the determined phase shift relative to the input with the determined gain. |
| US09577599B2 |
Production-process-optimized filter device
A filter device for filtering electrical currents or electromagnetic interference, particularly common-mode interference. The filter device has a soft-magnetic core with a passage, a printed circuit board with a plurality of electronic components, and a holding section. The holding section of the printed circuit board can be put through the core passage wherein the passage is designed such that the holding section and the electronic components arranged on the holding section can be put through the passage. |
| US09577595B2 |
Sound processing apparatus, sound processing method, and program
The present technique relates to a sound processing apparatus, a sound processing method, and a program which are configured to obtain higher quality sound. In order to obtain an objective characteristic, the sound processing apparatus previously holds a characteristic of the sound processing apparatus, generates an inverse characteristic filter of the characteristic of the sound processing apparatus, and generates a correction filter from the obtained filter and a filter having the objective characteristic. The sound processing apparatus uses the generated correction filter to subject a sound signal to be reproduced to filter processing, and reproduces sound based on the obtained sound signal. Therefore, a characteristic to be originally obtained can be achieved. The present technique can be applied to the sound processing apparatus. |
| US09577591B2 |
Multistage differential power amplifier having interstage power limiter
A differential power amplifier has at least an input stage and an output stage. A first output stage amplifier is configured to receive a first portion of a differential signal from the input stage at a first output stage input and provide a first amplified signal at a first output stage output. The second output stage amplifier is configured to receive a second portion of the differential signal from the input stage at a second output stage input and provide a second amplified signal at a second output stage output. Power limiter circuitry is connected to the first and/or output stage inputs and is configured to limit a power level of the differential signal prior to being received at the output stage, such that the differential power amplifier and associated filters are not damaged, while the nominal performance of the differential power amplifier at rated power is not significantly affected. |
| US09577585B2 |
Ultra wideband doherty amplifier
A Doherty amplifier for amplifying an input signal to an output signal, the Doherty amplifier comprising: a main amplifier for receiving a first signal and for amplifying the first signal to generate a first amplified signal; a first peak amplifier for receiving a second signal and for generating a second amplified signal, the first peak amplifier only operating when the second signal has reached a first threshold power, the first and second signal split from the input signal; and output circuitry to combine the first and second amplified signals to generate an output signal having an operating bandwidth, the output circuitry comprising inductors arranged in the format of a branch line coupler, the inductors coupled to the output parasitic capacitances of the main and peak amplifier. |
| US09577584B2 |
Amplifier circuit and method
A first amplifier is coupled to an output node via a first line having first and second portions. A second amplifier is coupled to the output node via a second line having first and second portions. An auxiliary amplifier is coupled via an auxiliary line network to a first intersection between the first and second portions of the first line, and to a second intersection between the first and second portions of the second line. For each of the first and second lines, the first and second portions have a higher-impedance portion and a lower-impedance portion whose combined length is a half wavelength. Lengths of the respective first portions of the first and second lines sum to half a wavelength, and the lengths of the respective second portions of the first and second lines sum to half a wavelength. |
| US09577582B2 |
Method of reducing power dissipation in a switching amplifier and circuit implementing such method
A method is for reducing power dissipation in a switching amplifier. The method may include comparing a load current with a ripple current and, if the load current is greater than the ripple current, then detecting a first potential value at a first output terminal of the switching amplifier, detecting a second potential value at a second output terminal of the switching amplifier, detecting a third potential value between first and the second terminals of a first capacitor, and coupling the first terminal of the first capacitor to one of the first output terminal and the second output terminal. The second terminal of the first capacitor may be coupled to a reference voltage, the first output terminal, or the second output terminal based upon whether the first potential value or the second potential value is equal to the third potential value. |
| US09577576B1 |
Biased passive mixer
Certain aspects of the present disclosure provide techniques and circuits for frequency mixing signals. One example circuit generally includes a transformer comprising a primary winding and a secondary winding, the transformer configured to generate a signal across the secondary winding based on a signal at an input node coupled to the primary winding, and a first mixer coupled to the secondary winding of the transformer and configured to convert a frequency of the signal across the secondary winding. In certain aspects, the circuit also includes a biasing circuit having an output coupled to a tap of the secondary winding and configured to generate a biasing voltage by applying an offset voltage to a common-mode voltage of the first mixer and apply the biasing voltage to the tap of the secondary winding to bias the first mixer. |
| US09577574B2 |
Resonator, resonator device, oscillator, electronic apparatus, and moving object
A resonator includes: a resonator element including a quartz crystal substrate that includes a first area performing a thickness-shear vibration and a second area with a thickness thinner than the first area and located around the first area; and a base substrate to which the second area of the resonator element on one edge side thereof is attached via a bonding material. The quartz crystal substrate has a major surface that is a surface including an X-axis and a Z′-axis, and has a thickness in a direction along a Y′-axis. The resonator satisfies the relation: 1.5×λ≦Xp where Xp is the maximum length of an area of the second area where the bonding material is bonded along the X-axis in a plan view and λ is the wavelength of a flexural vibration occurring in the quartz crystal substrate. |
| US09577570B2 |
Drive system for a vehicle trailer maneuvering drive
Disclosed are drive systems for a vehicle trailer maneuvering drives, some embodiments having a motor unit and a voltage source for supplying the motor unit, wherein the motor unit comprises a brushed electric motor with motor shaft and a motor controller that may include a speed detection unit for detecting the speed of the motor shaft and a control and regulating unit for the motor, for its voltage supply. |
| US09577569B2 |
Motor control system of electric vehicle and controlling method for motor control system of electric vehicle and electric vehicle
A motor control system of an electric vehicle, a controlling method for the motor control system and an electric vehicle are provided. The motor control system includes: an IGBT module, connected with a motor of the electric vehicle; a detection module, configured to detect a motor speed; a drive module, configured to drive IGBTs in the IGBT module to turn on or off so as to control the motor to work or stop working; a first control module; a second control module communicated with the first control module; and a channel selection module, configured to select a channel of the second control module when the first control module has a fault. When the second control module is selected, it sends a second control signal to the drive module according to the motor speed at a predetermined time before the first control module has the fault, so as to control the motor to stop working. |
| US09577566B2 |
Motor driving circuit
A motor driving circuit is provided, which selects a Hall sensor or a Sensor-less controller to achieve the phase commutation of a magnetic pole of a motor through a hall positive terminal and a hall negative terminal of a hall control device. When the hall positive terminal and the hall negative terminal receive a first hall signal and a second hall signal generated by the Hall sensor, the motor driving circuit selects the Hall sensor and then accordingly drives the motor. When the hall positive terminal and the hall negative terminal are floating, or one of them receives a high-voltage, the motor driving circuit selects the sensor-less controller and then accordingly drives the motor. Accordingly, the motor driving circuit can select different sensing devices to achieve the phase commutation of the magnetic pole of the motor according to the motor characteristics. |
| US09577564B2 |
Drive system with energy store and method for operating a drive system
A drive system with energy store and method for operating a drive system, an inverter powering an electric motor, the inverter being supplied from a unipolar DC-link voltage, an energy store being connected in parallel to the inverter, in particular, a film capacitor being connected in parallel to the inverter, the DC-link voltage being generated by a DC/DC converter which is supplied from an AC/DC converter, especially a rectifier, in particular, an electric current being able to be supplied to the DC link by the DC/DC converter. |
| US09577562B2 |
Method and apparatus for back electromotive force (EMF) position sensing in a cryocooler or other system having electromagnetic actuators
A method includes driving a component in an electromagnetic actuator back and forth during one or more cycles of the actuator, where the actuator includes a voice coil. The method also includes identifying a back electromotive force (EMF) voltage of the voice coil during at least one of the one or more cycles. The method further includes determining whether a stroke of the component is substantially centered using the back EMF voltage of the voice coil. In addition, the method includes, based on the determination, adjusting one or more drive signals for the voice coil during one or more additional cycles of the actuator. Determining whether the stroke of the component is centered could include determining whether the back EMF voltage of the voice coil is substantially maximized or determining whether times between extremes in the back EMF voltage are substantially equal. |
| US09577559B2 |
Apparatus and method for controlling power generation of vehicle
An apparatus for controlling power generation of a vehicle includes an alternator for generating electricity using an engine torque. A controller is configured to calculate a difference between a first duty value and a second duty value and to transmit a control signal based on the difference. The first duty value is an output duty value of the alternator before reaching a predetermined time, and the second duty value is a current output duty value of the alternator. A regulator gradually increases the amount of power generated by the alternator during a delay time based on the control signal received from the controller. |
| US09577558B2 |
Power management system having automatic calibration
A power management system having automatic calibration is disclosed. The power management system may have an alternator and an electronic control unit. The electronic control unit may be configured to determine a reference voltage based on at least one measured operating condition of the alternator. The reference voltage may correspond to an overloading threshold of the alternator. The electronic control unit may be further configured to monitor a voltage of the alternator and, when the monitored voltage is less than the reference voltage, perform a corrective action to increase a power output of the alternator. |
| US09577556B2 |
System and method for starting a motor
A motor controller coupled to a motor is provided. The motor controller is configured to transmit a first instruction to the motor to perform a first start attempt utilizing at least one parameter in a first set of parameters. The motor controller is additionally configured to receive feedback associated with the first start attempt from the motor, and transmit, in response to the feedback, a second instruction to the motor to perform a second start attempt utilizing at least one parameter in a second set of parameters, wherein the second set of parameters differ from the first set of parameters. |
| US09577555B2 |
Methods of estimating a position of a rotor in a motor under transient and systems thereof
At least one example embodiment discloses a method of estimating a position of a rotor in a motor. The method includes obtaining a current regulation quality index based on a current command and a measured current, determining an estimated position of the rotor based on the current regulation quality index and position estimation data and controlling the motor based on the estimated position of the rotor. |
| US09577553B2 |
Drive arrangement the motor-operated adjustment of an adjusting element in a motor vehicle
The invention relates to a drive arrangement for the motor-operated adjustment of an adjusting element in a motor vehicle, wherein the drive arrangement comprises two electrical drives having in each case a drive motor and a control device, wherein in the assembled state the drives act in the same manner on the adjusting element and are embodied in an essentially identical manner apart from deviations that are a result of tolerances, wherein the control device influences the two drive motors by a pulse width modulation voltage (“PWM” voltage). It is proposed that the control device influences the two drive motors by PWM voltages having PWM switching frequencies that vary continuously during the adjustment process in such a manner that the PWM switching frequencies that are allocated to the two drive motors are different from each other at least for periods of time. |
| US09577550B2 |
Vibration actuator having improved torque
Provided is a vibration actuator including: an electromechanical transduction member that transduces electric power to a mechanical vibration; a transmission member that transmits the vibration from the electromechanical transduction member as a driving force; and an abutting portion that abuts on the transmission member and moves relative to the transmission member in response to the driving force. One of the transmission member and the abutting portion includes pores in its surface contacting the abutting portion or the transmission member at an area occupancy of 2% or higher. In this vibration actuator, the average area of the pores may be 3 μm2 or larger. The other of the transmission member and the abutting portion may include iron in its surface contacting the one. |
| US09577548B2 |
Power conversion for distributed DC source array
Embodiments related to the conversion of DC power to AC power are disclosed. For example, one disclosed embodiment provides a power conversion system, comprising a plurality of direct current (DC) power sources, a plurality of power output circuits connected to one another in a parallel arrangement, each power output circuit being connected to a corresponding DC power source to receive power from the corresponding DC power source and to selectively discharge power received from the corresponding DC power source, a power combiner configured to combine power received from the plurality of power output circuits to form a combined power signal, an output stage configured to convert the combined power signal into an AC signal or a DC signal, and a controller in electrical communication with each power outlet circuit and the power combiner to control the output of power by the power converter. |
| US09577547B2 |
Power conversion device
A power conversion device converts three-phase AC power into DC power by two-arm PWM modulation control and includes a main circuit that is constituted by a plurality of switching elements that are bridge-connected therein; a voltage-command generation unit that generates a voltage command value for the main circuit; a current detection unit that detects at least one of output currents of the main circuit; a power-factor calculation unit that calculates a power factor on the basis of the output current and the voltage command value; a carrier-signal generation unit that generates a carrier signal of a frequency corresponding to the power factor; and a PWM-signal generation unit 6 that compares the voltage command value and the carrier signal to generate a PWM signal that executes switching control on the switching elements. |
| US09577534B2 |
Power converter and air conditioner
Malfunctions of a switching device included in a power factor corrector are reduced when an instantaneous voltage drop or an instantaneous power failure occurs. If the instantaneous voltage drop or the instantaneous power failure occurs in an AC power source while the power factor corrector is performing a power factor correction operation by boosting an input voltage, an instantaneous power failure controller turns off the switching device included in the power factor corrector so that the power factor correction operation stops. When the commercial power source recovers, too, the power factor corrector suspends the power factor correction operation. |
| US09577533B2 |
Control circuit for an interleaved switching power supply
In one embodiment, a control circuit configured for an interleaved switching power supply having first and second voltage conversion circuits, can include: a feedback compensation signal generation circuit that generates a feedback compensation signal; a first power switch control circuit that activates a first on signal when a first voltage signal that represents an inductor current of the first voltage conversion circuit is less than the feedback compensation signal, a first power switch of the first voltage conversion circuit being turned on based on the first on signal, and turned off after a predetermined time; and a second power switch control circuit that activates a second on signal after half of a switching period from a rising edge of the first on signal, and a second power switch control signal to turn on a second power switch of the second voltage conversion circuit based on the second on signal. |
| US09577532B2 |
Switching regulator circuits and methods
A switching regulator circuit can include multiple switching regulator stages coupled to an output. A first switching regulator stage may be operated at a different frequency than a second switching regulator stage. In some cases, one switching regulator stage is operated at a different duty cycle. The switching regulator circuit may also include multiple switching regulator stages that cancel ripple at an output node. |
| US09577525B2 |
Adaptive dead time control
A dead time detector detects when a dead time occurs in a switching regulator comprising a high-side switch and a low-side switch and generates an output signal based on a duration of the dead time. A first circuit generates a first turn-on signal to turn on the high-side switch and a first turn-off signal to turn off the low-side switch based on the output signal in response to a first edge of a pulse width modulated pulse. A second circuit generates a second turn-on signal to turn on the low-side switch and a second turn-off signal to turn off the high-side switch based on the output signal in response to a second edge of the pulse width modulated pulse. A controller generates drive signals to drive the high-side and low-side switches based on the first and second turn-on and turn-off signals. |
| US09577522B2 |
Pre-filtering in a power supply control circuit
A hybrid power supply circuit includes a digital circuit, a digital-to-analog converter circuit, and an analog compensator circuit (analog control circuit). According to one configuration, the digital circuit includes a digital pre-filter that substantially matches settings of analog filter circuitry present in the analog compensator circuit. During operation, the digital circuit receives control input indicating how to control a magnitude of an output voltage produced by the power supply circuit. The digital circuit passes the received through the digital pre-filter to produce a (filtered) digital reference voltage. The digital-to-analog converter circuit converts the received digital reference voltage into an analog reference voltage (a filtered rendition of the received control input). The analog compensator circuit receives and uses the digitally pre-filtered analog reference voltage as a basis to control the magnitude of the output voltage produced by the power supply circuit. |
| US09577521B2 |
Average current control for a switched power converter
A circuit for controlling a switch in a power converter in which peak current is regulated to achieve a specified average current through a load. Control logic is operable to monitor a voltage across a sensing resistor such that when the voltage across the sensing resistor reaches or exceeds a threshold value, the control logic generates a signal that causes a switch to be turned OFF. |
| US09577519B2 |
Enhanced peak current mode DC-DC power converter
Apparatus and methods are provided for feedback circuitry in a power converter, the feedback circuitry including a first resistor coupled to a first node between a high switch and a low switch, a first capacitor in series with the first resistor, the first capacitor coupled to a second node, a first comparator having a positive terminal connected between the first resistor and the first capacitor and a negative terminal connected to a third node, the first comparator configured to compare a voltage at the positive terminal to a voltage at the negative terminal, wherein the feedback circuitry is configured to generate a ramp waveform at the positive terminal of the first comparator, an amplitude of the ramp waveform based on a time constant of the first resistor and the first capacitor. |
| US09577518B2 |
Voltage control method and apparatus for achieving and maintaining a targeted voltage on a load
The present invention discloses a voltage control method. First, the load voltage of the load is divided to generate a feedback voltage. Then, an absolute value of a periodic triangular wave signal is retrieved to generate a positive feedback signal, which and the feedback voltage are then combined to produce a sum signal. The sum signal is then compared with a target voltage and when the sum signal is less than the target voltage, a control signal is generated and thus the load voltage is updated and stabilized using an input voltage. In an alternative method, the feedback voltage and the periodic triangular wave signal are combined to generate a sum signal, which is compared with the target voltage. When sum signal is less than the target voltage, a control signal is generated and thus the load voltage is for updated and stabilized using an input voltage. |
| US09577517B2 |
Startup clamp circuit for non-complimentary differential pair in DCDC converter system
A DCDC converter includes a transconductance amplifier, a comparator, a current driving component, an output impedance, a switch, a clamp resistor and a p-channel FET. The transconductance amplifier outputs a transconductance current and a switch control signal. The comparator has a two n-channel FET inputs forming a differential pair and outputs a compared signal. The current driving component generates an output current based on the compared signal. The output impedance component generates an output DC voltage based on the output current. The switch is between the two n-channel FETs and can open and close based on the switch control signal. The clamp resistor is arranged in series with the switch. The p-channel FET is in series with the clamp resistor and is controlled by the output DC voltage. |
| US09577516B1 |
Apparatus for controlled overshoot in a RF generator
A radio-frequency (RF) generator is provided that produces a controlled overshoot. One embodiment includes a RF power amplifier and a direct-current (DC) power supply that includes a primary DC power supply, an auxiliary DC power supply, a half-bridge circuit, and a control circuit. The half-bridge circuit, in a first switching state, electrically connects, in series, the auxiliary DC power supply with the primary DC power supply and, in a second switching state, electrically disconnects the auxiliary DC power supply from the primary DC power supply. The control circuit places the half-bridge circuit in the first switching state for a first period of time and places the half-bridge circuit in the second switching state for a second period of time to produce a controlled overshoot in the power produced by the RF generator throughout the first period of time. |
| US09577515B2 |
Controller for generating jitters in a quasi resonant mode and method for generating jitters in a quasi resonant mode
A controller for generating jitters in a quasi resonant mode includes a feedback pin, a voltage generation unit, a pulse generator, and a comparator. The feedback pin is used for receiving a feedback voltage from a secondary side of a power converter. The voltage generation unit is used for generating a first voltage according to the feedback voltage and a pulse. The pulse generator is used for generating the pulse when a control signal controlling a power switch of a primary side of the power converter is enabled. The comparator is used for controlling enabling and disabling of a switching signal according to the first voltage and a variable reference voltage. The variable reference voltage is monotonously swung within a predetermined range according to a digital signal. |
| US09577513B2 |
Method for operating a power factor correction circuit
A method for operating a power factor correction circuit is provided which may include the steps of providing a plurality of N switched-mode converter circuits each comprising an nth inductor, where N is at least 2, starting a switching pulse for the nth switched-mode converter circuit when the following conditions are fulfilled: the nth inductor of the nth switched-mode converter circuit has a predefined magnetization state; and a predefined time period has elapsed since the start of a switching pulse for an mth switched-mode converter circuit, where m=n−1 in case n>1 and m=N in case n=1. The predefined time period is a predefined fraction of the time period from the start of a previous switching pulse for the nth switched-mode converter circuit to a time when the nth inductor of the nth switched-mode converter circuit has the predefined magnetization state. |
| US09577512B2 |
Current zero-cross detection device, signal acquisition circuit, and circuit system
Disclosed are a current zero-cross detection device, zero-cross current signal acquisition circuit and totem pole bridgeless circuit system. The current zero-cross detection device includes a current transformer, first sampling switch, second sampling switch, sampling resister, comparator. The current transformer includes a primary winding and a secondary winding; the primary winding is connected to a circuit to be detected; two ends of the secondary winding are connected respectively to drain electrodes of the first and second sampling switches; source electrodes of first and second sampling switches are connected to ground; two ends of the sampling resistor are connected respectively to the drain electrode and source electrode of the second sampling switch; the negative input end of the comparator is connected to the drain electrode of the second sampling switch, its positive input end is connected to a reference voltage; the first and second sampling switches are in ON or OFF state. |
| US09577511B2 |
PFC DC/AC/DC power converter with reduced power loss
A second control circuit is configured to switch a pulse signal to a level which turns off a second switching transistor when a coil current that flows through a primary winding reaches a predetermined threshold current. The second control circuit is configured to start a switching operation when a power supply for an electronic device is turned on, to set the threshold current to a first value when an intermediate voltage is higher than a predetermined level, and to set the threshold current to a second value that is lower than the first value when the intermediate voltage is lower than a predetermined level. A first control circuit is configured to start a switching operation upon receiving an instruction from a microcontroller to start operating. |
| US09577510B2 |
Inverter device
An inverter device includes an inverter circuit, which has switching elements in a bridge connection, a capacitor, which is connected in parallel to the input side of the inverter circuit, a control device, which controls the inverter circuit, a temperature detector, which detects the temperature of the capacitor, a degree-of-deterioration determiner, which determines the degree of deterioration of the capacitor, and a warm-up controller. When the temperature of the capacitor detected by the temperature detector is lower than a prescribed temperature, the warm-up controller controls the switching elements of the inverter circuit to supply a direct current set based on the degree of deterioration and the temperature of the capacitor to the coil of an electric motor connected to the output side of the inverter circuit. |
| US09577509B2 |
Emulated peak current limit scheme for switching regulator
An apparatus comprises a switching circuit, an error amplifier circuit, a current threshold circuit, and an over-current detection circuit. The switching circuit provides a switching duty cycle that includes a charge portion and a discharge portion. The error amplifier circuit generates an error signal representative of a difference between a target voltage value and a voltage at an output of the voltage regulator circuit. The switching circuit adjusts the switching duty cycle to regulate the voltage at the output using the error signal and a reference waveform signal. The current threshold circuit generates an adaptive peak current limit threshold. The over-current detection circuit generates an over-current signal when the reference waveform signal satisfies the adaptive peak current limit threshold during the charging portion of the switching cycle. The switching circuit interrupts one or more switching cycles when the reference waveform signal satisfies the adaptive peak current limit threshold. |
| US09577504B2 |
Cryogen supply and return device for use with cryogen rotating electric machine and superconducting rotating electric machine with cryogen supply and return device
Provided is a cryogen supply and return apparatus and a superconducting rotating electric machine, comprising stationary and rotatable members arranged out of contact with each other, preventing an increase of maintenance cost or a temperature increase of the cryogen which would be caused by contacts of the members. A cylinder 20 has on its outer peripheral surface ring-like recesses or grooves regularly or irregularly spaced in the longitudinal direction or spiral recesses or grooves continuously or discontinuously extending in the peripheral direction, to resist helium gas flowing through a cylindrical space between the cylinder 20 and the inner tube 14b of the second double tube member and, as a result, to control a leakage of the helium gas from the cylindrical space. |
| US09577502B2 |
Transverse flux permanent magnet rotatory device
A transverse flux motor (10) includes a housing (20), a stator (50), and a rotor (30) external to the stator (50) and installed onto the housing. The stator (50) includes a stator sub-assembly including at least one pair of stator core elements (52), each having multiple stator pole teeth (56) circumferentially offset from pole teeth of the other stator core element in the pair. The rotor (30) includes a rotor body (32) made of a single piece part or multiple rotor body laminas (36). The rotor body (32) includes multiple magnetic flux retention features (40) for positioning first magnets (34). Two adjacent magnetic flux retention features (48) define a second magnet retention feature (47) for positioning a second magnet (45) that form a substantially U-shape together with two neighboring first magnets with the same magnetic poles facing each other. |
| US09577500B2 |
Rotary continuous permanent magnet motor
A rotary magnetic motor having a rotor configured to magnetically interact with a stator to obtain rotation of the rotor about its axis. The stator has a magnetic structure of a generally involute shape around the axis of rotation. The stator magnetic structure has a plurality of permanent magnets defining a first magnetic face of a first polarity. The rotor has a magnetic structure of a generally circular shape around the axis and inside the stator magnetic structure. The rotor has a plurality of permanent magnets defining a second magnetic face of a second polarity. The magnetic attraction and repulsing of the aligned magnetic faces with a progressively narrowing radial gap, resulting from the involute shape, rotate the rotor inside the stator. A magnetic pulse mechanism discharges a magnetic pulse of the first polarity to provide an additional pull to continue the rotation of the rotor through its full cycle. |
| US09577493B2 |
Motor and electronics cooling system for a high power cordless nailer
A battery powered tool includes a housing containing a motor assembly. A fan positioned in the housing is rotated by the motor assembly. The fan has a circular ring/body and further has multiple fan blades directly connected to the circular ring body. The circular ring/body defines a concave shaped surface having the fan blades directly connected to the concave shaped surface. A housing cover includes: first and second extending walls; a slot created between the first and second extending walls; and multiple air intake vents all positioned in a lower housing zone separated from an upper housing zone by the slot. An electronics module is positioned in the housing proximate to the housing cover lower housing zone such that air entering the intake vents passes only through the lower housing zone and past the electronics module to cool the electronics module before entering the fan. |
| US09577491B2 |
Starter motor including a removable solenoid tower
An electric machine includes a housing having an outer surface and an inner surface defining an interior zone. A solenoid mounting section is provided on the housing. The solenoid mounting section includes a shift lever opening that extends from the outer surface through the inner surface. A solenoid tower is mounted to the housing. The solenoid tower extends from a first end detachably coupled to the solenoid mounting section to a second end configured to receive a solenoid. The first end includes an opening that registers with the shift lever opening. At least one of the solenoid mounting section and the solenoid tower includes a seal. |
| US09577489B2 |
Motor with sealed controller housing
An electric motor is provided. The motor is mountable to a machine. The motor includes a rotor rotatable about an axis, a stator, a housing, and a fastener. The housing includes a first endshield and a controller can, with the stator being positioned axially between the endshield and the can. The fastener extends through and interconnects the first endshield, the stator, and the can. The fastener projects axially beyond at least one of the first endshield and the can for connection to the machine. |
| US09577485B2 |
Armature winding of rotating electrical machine
According to one embodiment, there is provided a 3-phase 2-pole 2-layer armature winding, housed in 72 slots provided in a laminated iron core, a winding of each phase including six parallel circuits separated into two phase belts. Upper coil pieces of first and fourth parallel circuits are placed at 3rd, 4th, 7th, and 12th positions, and lower coil pieces of the first and fourth parallel circuits are placed at 1st, 6th, 9th, and 10th positions, upper and lower coil pieces of second and fifth parallel circuits are placed at 2nd, 5th, 8th, and 11th positions, and upper coil pieces of third and six parallel circuits are placed at 1st, 6th, 9th, and 10th positions, and lower coil pieces of the third and six parallel circuits are placed at 3rd, 4th, 7th, and 12th positions, from the center of a pole. |
| US09577484B2 |
Variable magnetomotive force rotary electric machine and control device for variable magnetomotive force rotary electric machine
A rotary electric machine includes a stator and a rotor. The rotor has at least one permanent magnet arranged in a d-axis magnetic path. The rotor includes a magnetic gap part located between the permanent magnet arranged in the d-axis magnetic path of one pole and an adjacent magnet with a different polarity, such that a d-axis magnetic flux forms a d-axis bypass passing through an area other than the permanent magnet. The d-axis bypass provides a magnetic resistance in a d-axis direction that is set below a magnetic resistance in a q-axis direction that is orthogonal to the d-axis resistance. |
| US09577474B2 |
Demodulator for wireless power transmitter
A demodulator is mounted on a wireless power transmitter that conforms to the Qi standard, and demodulates an amplitude modulated signal superimposed on a coil current ICOIL that flows through a primary coil of a transmission antenna, or otherwise on a coil voltage across both ends of the primary coil. Multiple demodulating units are each configured to have respectively different configurations, to operate in parallel, to extract a demodulated component from the coil current ICOIL or otherwise from the coil voltage, and to generate baseband signals as demodulated signals. A signal processing unit employs a baseband signal that is correctly received, from among the multiple baseband signals generated by the multiple demodulating units, based on an error detection result obtained using a checksum. |
| US09577470B2 |
Electrical and/or electronic supply circuit and method for providing a supply voltage
An electrical and/or electronic supply circuit, which serves to provide a first or a second, essentially constant value of a supply voltage, which supply voltage serves to operate an operating electronics. The supply circuit serves to output the first value of the supply voltage when the supply voltage is derived from a first voltage source, and the supply circuit serves to output the second value of the supply voltage when the supply voltage is derived from a second voltage source. |
| US09577466B2 |
Wireless charging system and method for controlling the same
A wireless charging system for a vehicle may include: a power transmitter having a plurality of transmitting coils; and a controller configured to measure a current and a voltage of each of the plurality of transmitting coils and to apply charging power only to a subset of the plurality of transmitting coils based on a magnitude of the measured current and voltage of each of the plurality of transmitting coils. |
| US09577460B2 |
Wireless charging device and control method thereof
There are provided a wireless charging device and a control method thereof, the wireless charging device including: a receiving module receiving power from the outside in a magnetic induction scheme or a magnetic resonance scheme to thereby charge a battery; and an input signal determining unit receiving an input signal from the outside and determining characteristics of the input signal, wherein the receiving module includes a reception controlling unit controlling the receiving module to be operated in the magnetic induction scheme or the magnetic resonance scheme according to the characteristics of the input signal received from the input signal determining unit. |
| US09577456B2 |
Battery device, control method, and electric vehicle
This technology relates to a battery device, a control method, and an electric vehicle capable of providing a highly secure anti-theft function. A battery outputs DC power through a power line, a reader/writer communicates by outputting a high-frequency signal through the power line to read authentication information of an electronic device when the electronic device is connected to the battery through the power line, a microcomputer stores the read authentication information and controls the battery when first connection to the electronic device is performed, and performs an authentication process of the electronic device based on the read authentication information and the authentication information stored in the first connection and controls the battery according to a result of the authentication process of the electronic device when second or subsequent connection to the electronic device is performed. This technology may be applied to the battery device mounted on a power-assisted bicycle, for example. |
| US09577450B2 |
Charger for hand-held power tool, power tool system and method of charging a power tool battery
A charger for a hand-held power tool includes a power source interface, a charger base and a charging cradle rotatably supported on the charger base. The rotatable charging cradle includes at least two charging output terminals electrically connected to the power source interface. A power tool system includes the charger and the hand-held power tool. A method of charging the power tool system includes contacting charging input terminals of the power tool with the charging output terminals, rotating the charging cradle and the power tool relative to the charging base and supplying charging current to at least one battery cell while the charging cradle and the power tool are allowed to freely swing relative to the charging base. |
| US09577448B2 |
Integration of wireless charging unit in a wireless device
Described herein are techniques related to one or more systems, apparatuses, methods, etc. for implementing a wireless charging and a wireless connectivity in a device. |
| US09577440B2 |
Inductive power source and charging system
A portable inductive power source, power device, or unit, for use in powering or charging electrical, electronic, battery-operated, mobile, and other devices is disclosed herein. In accordance with an embodiment the system comprises a pad or similar base unit that contains a primary, which creates an alternating magnetic field by means of applying an alternating current to a winding, coil, or any type of current carrying wire. A receiver comprises a means for receiving the energy from the alternating magnetic field from the pad and transferring it to a mobile or other device. In some embodiments the receiver can also comprise electronic components or logic to set the voltage and current to the appropriate levels required by the mobile device, or to communicate information or data to and from the pad. Embodiments may also incorporate efficiency measures that improve the efficiency of power transfer between the charger and receiver. |
| US09577439B2 |
Power relaying apparatus, power transmission system and method for manufacturing power relaying apparatus
Disclosed herein is a power relaying apparatus provided between: a power supplying apparatus including a power supplying resonance device and a power supplying power supply section for supplying an AC current to the power supplying resonance device; and a power receiving apparatus having a power receiving resonance device for receiving a power from the power supplying apparatus by adoption of a resonance method, the power relaying apparatus including a power relaying resonance device resonating between the power supplying resonance device and the power receiving resonance device, wherein the power relaying resonance device is fixed at a predetermined position by making use of an insulation member. |
| US09577438B2 |
Wireless power system
The present disclosure relates wireless power transfer. In some embodiments, DC power is received through one or more inductors and switched to provide alternating current through a TX coil with a pair of power FETs coupled between opposite sides of the TX coil and ground such that current flows through one of the pair of FETs at a time. In some embodiments, the pair of FETs can be driven in adaptive resonant mode to operate at a resonance. In some embodiments, the pair of FETs are driven at a particular frequency. |
| US09577433B2 |
Energy supply network for an aircraft or spacecraft, method for supplying electrical loads with energy, and aircraft or spacecraft
An energy supply network for an aircraft or spacecraft, comprising at least one energy generating device for generating electrical energy, comprising at least two energy control devices, at least one of which is coupled directly to at least one of the energy generating devices and which are adapted each to provide a controlled supply voltage so as to supply electrical loads located in the aircraft with energy, and comprising a high-voltage direct current transmission device, which couples the at least two energy control devices to one another by means of high-voltage direct current transmission. Further, a method for supplying energy, and an aircraft or spacecraft. |
| US09577425B1 |
Systems and methods for controlling power switching converters for photovoltaic panels
A photovoltaic (PV) system has a plurality of PV panels that convert solar energy into electrical energy. Each PV panel is coupled to a respective switching power converter. A parameter (e.g., voltage or current) of a combined current signal from each of the switching power converters is sensed, and a controller controls the duty cycle of each switching power converter in order to maximize the sensed parameter. In this regard, the controller adjusts the duty cycles of the power switching converters in groups while the duty cycles of other power switching converters are held constant in order to set the duty cycles for maximum power transfer, thereby accounting for variations in the power output by each PV panel. |
| US09577422B1 |
Ground wire fault circuit interrupter
A grounding wire fault circuit interrupter for an electrical machine includes a chassis ground wire, a sensor, and a logic circuit. The chassis ground wire is configured to be electronically connected to a structure of the electrical machine such that the structure of the electrical machine is further electrically connected to one or more power lines that provide electrical power to the electrical machine. The sensor is electronically connected to the chassis ground wire. The logic circuit is electronically connected to the sensor. The sensor is configured to detect current leaks within the electrical machine by sensing electrical power on the chassis ground wire, and the logic circuit is configured to interrupt the flow of electrical power to the electrical machine when the sensor detects a current leak. |
| US09577421B2 |
System and method for isolating ground faults in a wind turbine
The present subject matter is directed to a system and method for operating a wind turbine connected to a power grid. The method includes receiving, via a controller, one or more current feedback signals from one or more electric current sensors of the wind turbine. Another step includes determining, via the controller, if a ground fault is occurring in the wind turbine based on the current feedback signals. In response to detecting a ground fault, the method includes tripping one or more electrical components of the wind turbine and electrically de-coupling the wind turbine from the power grid. |
| US09577415B1 |
Communications interface system for landscape control systems
A communications interface system includes a housing and one or more removable components. The removable components can include one or more removable communications module configured to facilitate communication between the interface system and one or more other communications or control systems. A facepack can be removably coupled with the housing. The facepack can include one or more displays and/or user input structures. |
| US09577412B2 |
Switchgear housing including a floating exhaust flap assembly
A switchgear housing assembly includes a first switchgear housing including a cable compartment portion and a circuit breaker portion, a busbar portion, and a second switchgear housing a cable compartment section, a busbar section, and a circuit breaker section. An exhaust duct is arranged between the first and second switchgear housings. The exhaust duct is selectively fluidically exposed to at least one of the cable compartment portion, cable compartment section, the circuit breaker portion, and the circuit breaker section. A floating flap assembly is operatively associated with at least one of the first and second switchgear housings. The floating flap assembly includes a floating flap member. The floating flap member is selectively slideable between a closed position and an open position in response to a pressure rise in one of the cable compartment portion, cable compartment section, circuit breaker portion, and circuit breaker section. |
| US09577410B2 |
Optical functional integrated unit and method for manufacturing thereof
It is provided that an optical functional integrated unit and a method for manufacturing thereof in which a positive optical device and a passive optical device including a silicon waveguide can be readily integrated. An optical functional integrated unit includes a semiconductor optical amplifier, a photonics device, a mounting board, pedestals and. The pedestals and are provided on the mounting board. The semiconductor optical amplifier is mounted on the pedestal and outputs a light from an active layer. The photonics device is mounted on the pedestal. The photonics device includes silicon waveguide to which the light output from the semiconductor optical amplifier is guided. |
| US09577398B2 |
Assisting tool for connector
The assisting tool for a connector includes a mounting member able to be mounted in a first housing having a first connector able to mate with a second connector in a second housing, and an operating member able to rotate with respect to the mounting member. Here, the operating member has a lever portion, the operating member is mounted in the first housing, and the lever portion contacts the second housing and applies pressure to the second housing in the direction releasing the mated first connector and second connector when the operating member is rotated while the first connector is mated with the second connector. |
| US09577397B2 |
Method of manufacturing a shell assembly for an electrical connector
Methods are provided for manufacturing a shell assembly for an electrical connector. First and second shells of a shell assembly may be formed from metal sheets via a stamping process. The stamping process may produce a number of first shells attached to a section of metal sheet remaining after the stamping process—a guide rail—with the front end opening of the first shell being oriented at 90 degrees relative to the guide rail. A second shell may be formed and severed from a metal sheet as a result of the stamping process. One end of the first shells may be exposed after the stamping process such that the second shells may be assembled over the exposed end of the first shells to form a shell assembly. Additional operations can be performed on the shell assembly. |
| US09577393B2 |
Connector for wearable device
An electrical connector comprises an insulative housing, a positioning member and a plurality of first terminals. The insulative housing has a tongue. The positioning member is embedded in the tongue and has a main body. The plurality of first terminals are held by the main body of the positioning member and embedded in the insulative housing. The tongue exposes a flat plate-like contact portion of each first terminal. |
| US09577392B2 |
USB type-C connector module
A USB Type-C connector module includes a circuit board, a configuration-channel (CC) chip and a plurality of conductive terminals electrically connected with the circuit board. One end of the circuit board has a tongue, which a plurality of golden-fingers are arranged at two sides thereon. A USB Type-C connector is constituted by the tongue and the golden-fingers. CC golden-fingers of the USB Type-C connector are electrically connected to the CC chip for accepting a CC operation. Power golden-fingers of the USB Type-C connector are electrically connected to a power control chip of an external mainboard through the plurality of conductive terminals for receiving power. Data golden-fingers of the USB Type-C connector are electrically connected to a PCH of the external mainboard for transmitting data. |
| US09577391B2 |
Coaxial cable continuity device
A jumper sleeve configured to be installed on an outer side of a male F-connector to facilitate easy connection of and maintain ground continuity across the male F-connector and a female F-connector. In one embodiment, a conductive element is installed on an inner surface of the jumper sleeve and conductively engages an outer surface of the male F-connector to maintain ground continuity across the male and female F-connectors. |
| US09577389B2 |
Systems and methods for modular shock proof electrical outlets
Systems and methods for providing electrical power from an electrical outlet. In some embodiments, an electrical outlet for providing high voltage power to a device includes power input terminals for connection to a high voltage power source, and at least one power output socket configured to receive a plug configured to receive high voltage power. The outlet may also include a shock-proof circuit connected to the at least one power output socket, a communication circuit configured, and a processor coupled to the communication circuit and the shock-proof circuit, the processor and the shock-proof circuit collectively configured to determine when to provide high voltage power to the at least one power output socket based on a sensed condition, and the processor and the communication circuit collectively configured to communicate information relating to an operation aspect of the electrical outlet with a remote computing device. |
| US09577385B1 |
Electrical connector for connecting a cable
An electrical connector used for mating a mating connector includes an insulating body having multiple terminal slots in communication with an insertion space, multiple terminals, an insulating block. Each terminal slot has at least one side wall from which a depressed portion is depressed, the depressed portion is laterally in communication with the terminal slot. Each terminal has a connection portion connected to a contact portion and a soldering portion, a stopping portion protrudes from the connection portion and is located at the depressed portion. The insulating block is insert molded at a back end of the insulating body. A protruding portion protrudes from a front end of the insulating block and enters the depressed portion. The stopping portion is stopped in front of the protruding portion. |
| US09577383B2 |
Telecommunications device
The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack. |
| US09577381B2 |
Electrical connector
An electrical connector includes an insulation body and a contact. The insulation body includes a first side and a second side positioned opposite to the first side. The contact is received in the insulation body and includes a first elastic gripping portion adjacent to the first side of the insulation body and a second elastic gripping portion adjacent to the second side of the insulation body. |
| US09577375B2 |
Connector alignment assembly
A connector alignment assembly comprises a support member having a surface from which an array of male connector pins extend outwardly, each male connector pin having a base region proximate the surface of the support member and a tip region proximate the end of each male connector pin. Guide posts extend from the surface in the direction of the array of male connector pins and compression mechanisms, one associated with each of the guide posts. The compression mechanisms are adapted to transition from the uncompressed position to a compressed position. An alignment plate has guide holes which engage with the guide posts to position the alignment plate in a spaced relationship from the surface of the support member. The alignment plate has an array of male connector pin holes which engage with the array of male connector pins. |
| US09577374B1 |
Textile connector for an electronic textile having a snap fastener with contacts
A textile connector for an electronic textile includes a snap fastener having first and second snap segments configured to be snap fastened together such that the electronic textile is mechanically secured therebetween. A first contact is held by the snap fastener. The first contact is configured to be electrically connected to a first conductor of the electronic textile to define a first signal line. A second contact is held by the snap fastener. The second contact is configured to be electrically connected to a second conductor of the electronic textile to define a second signal line. The first and second signal lines transmit different data signals from the electronic textile to an electronic component mounted to the electronic textile. |
| US09577370B2 |
High-speed connector with electrical ground bridge
A high-speed electrical connector includes an insulating case, several signal terminals, several grounding terminals, an electrical bridge, and several resilient conductive buffers mounted in the insulating case. Each of the signal and grounding terminals has a fixing segment and a swing segment swingable with respect to the fixing segment. The electrical bridge corresponds to two of the grounding terminals. The conductive buffers are disposed on the electrical bridge and are respectively arranged in the swing paths of the swing segments. Each conductive buffer is configured to transform from an initial state to a deformation state by pressing. Each swing segment can swing to press the corresponding conductive buffer, causing the corresponding conductive buffer to be in the deformation state, thereby establishing an electrical connection path between the electrical bridge and the corresponding grounding terminals. In one example, the buffer can be formed of elastomer mixed with conductive particles. |
| US09577365B1 |
Holding frame for holding plug connector modules
Disclosed is a holding frame for holding plug connector modules, in particular for installation in plug connector casings and/or for screwing onto wall surfaces. In order to allow improved handling and more reliable populating and assembly of the holding frame having frame halves. The holding frame has an elastic fixing element adapted to releaseably fix the frame halves in a plug-in state and a holding state. At least a restoring force of the elastic fixing element must be overcome in order to release the fixing and/or to switch between the plug-in state and the holding state. |
| US09577362B1 |
Electrical connector assembly
An electrical connector assembly that includes a first connector component that has a housing supporting at least one first exposed contact at an interface surface thereof and has a body portion for terminating a first cable. A second connector component is adapted to slidably receive the first component such that the components are mated and unmated in the same direction. The second component includes a housing supporting at least one second exposed contact at an interface surface thereof and has a body portion for terminating a second cable. When the first component is received in the second component, the components are mated such that the first exposed contact engages the second exposed contact, thereby forming a first electrical connection therebetween and a longitudinal axis of the first cable is spaced from and substantially parallel to a longitudinal axis of the second cable. |
| US09577359B2 |
Printed circuit board centering beam
A card edge connector including electrical contacts; and a housing having the electrical contacts connected thereto. The housing comprises a card edge receiving slot, and a beam extending at least partially across a width of the card edge receiving slot. An open space is provided between the beam and a bottom of the card edge receiving slot. |
| US09577353B2 |
Mains power wire connection assembly and connection method
A mains power wire connection assembly (100) using a button to push a first wire and a second wire to move toward the direction of clamping slots, and the inner walls of the clamping slots puncture the first wire and second wires and clamp the same. The button and the insulation body are locked and fixed with respect to each other. |
| US09577352B2 |
Electrical connectors and related methods
Electrical connectors including a cable clamp (e.g., having a first clamp portion, a second clamp portion, and a hinge coupled to the first and second clamp portions such that the first and second clamp portions are movable relative to each other between an open position and a closed position in which the first and second clamp portions define a cable passageway), and a piercing conductor configured to place a fixture wire into electrical communication with an electrical cable disposed within the cable passageway. In at least some of these electrical connectors, a longitudinal axis of the cable passageway is substantially aligned with a longitudinal axis of the cable clamp when the first and second clamp portions are in the closed position. In at least some of these electrical connectors, at least one of the clamp portions comprises a flexible sidewall that at least partially defines the cable passageway. |
| US09577351B2 |
Spring loaded insulation piercing electrical connector
An electrical connector includes first and second pads. The first pad includes first and second grooves and the second pad includes third fourth grooves. A first insulation displacing contact extends from the first groove to the second groove. A second insulation displacing contact extends from the third groove to the fourth groove. The first and second pads are connected by a mechanical fastener. When the first and second pads are connected the first groove aligns with the third groove and the second groove aligns with the fourth groove. |
| US09577347B2 |
Antenna structure of a circular-polarized antenna for a vehicle
A turnstile antenna has two dipoles which have a galvanic contact at the crossing point. The dipoles are arranged in a geometrically asymmetrical manner with respect to the crossing point. The turnstile antenna can be arranged either in a free space or over a metal plate. |
| US09577346B2 |
Vertical multiple-input multiple-output wireless antennas
High gain, multi-pattern multiple-input multiple-output (MIMO) antenna systems are disclosed. These systems provide for multiple-polarization and omnidirectional coverage using multiple radios, which may be tuned to the same frequency. The MIMO antenna systems may include multiple high-gain beams arranged (or capable of being arranged) to provide for omnidirectional coverage. These systems provide for increased data throughput and reduced interference without sacrificing the benefits related to size and manageability of an associated access point. |
| US09577339B2 |
Antenna device and electronic device
According to one embodiment, an antenna device includes a first antenna, a second antenna, a third antenna, a capacitor element, a high-frequency cable, and a base member. The first antenna includes a folded-type monopole element. The second antenna includes a monopole element. The third antenna includes a passive element. The capacitor element is between a feeding point and a stub in a backward-path portion of the first antenna. The high-frequency cable is connected to the feeding point. The base member is formed of a dielectric material and has first, second, and third surfaces located to extend in different directions. The first, second, and third antenna are located at the first, second, and third surfaces. |
| US09577335B2 |
Antenna
An antenna includes antenna coil having a magnetic-material core and a coil conductor. The antenna coil is arranged toward a side of a planar conductor, such as a circuit board. Of the coil conductor, a first conductor part close to a first main face of the magnetic-material core and a second conductor part close to a second main face of the magnetic-material core are provided such that the first conductor part is not over the second conductor part in view from a line in a direction normal to the first main face or the second main face of the magnetic-material core. In addition, a coil axis of the coil conductor is orthogonal to the side of the planar conductor. |
| US09577329B2 |
Ultra-broadband antenna with capacitively coupled ground leg
An antenna including a ground plane, a broadband radiating element mounted on the ground plane and including a feed point, the feed point having a first impedance, a feed for feeding the broadband radiating element at the feed point, the feed having a second impedance and a ground leg extending between the broadband radiating element and the ground plane for impedance matching the first impedance to the second impedance, the ground leg being capacitively coupled to the broadband radiating element. |
| US09577328B2 |
Beam forming system having linear samplers
A frequency conversion circuit having a plurality of N signal channels, each being fed an input signal and a train of pluses having a period T and a duty cycle T/N. Each channel includes: a sampler coupled the input signal and being responsive to sampling signals; and a controllable time delay for producing the train of sampling signals in response to the train of pulses, the time delay imparting a time delay to the pulses in accordance with a time delay command signal fed to the time delay. Each one of the sampling signals is produced by the time delay in each one of the channels with the period T and the duty cycle T/N with the sampling signals in one of the trains of the sampling signals being delayed with respect to the sampling signals in another one of the trains the sampling signals a time T/N. |
| US09577326B2 |
Device for decoupling antennas mounted on an aircraft
A high-impedance passive device to radio-electrically decouple two antennas operating at least partially within a common frequency band and arranged on a surface of the carrier structure. A substrate of the device has a flexible dielectric material layer having a predetermined thickness with patches of conductive material arranged on its surface and a layer to attach the device onto the surface of the carrier structure. The patches having predetermined shape and arrangement. The body of the substrate separates the dielectric layer from the surface of the carrier structure. The substrate thickness is determined based on the size, number, and arrangement of the patches, and further it is based on the aerodynamic constraints imposed on the device. The device having an impedance to cause the desired decoupling in the common frequency band. |
| US09577323B2 |
Radome—reflector assembly mechanism
In one embodiment, a radome-reflector assembly for, e.g., a microwave antenna, has (i) two semi-circular rims that receive the peripheries of the radome and the reflector and (ii) fixed and adjustable clamps that secure the ends of the rims together. The rims are designed with slanted inner surfaces that engage the periphery of the reflector, such that, when the adjustable clamp is tightened circumferentially, the periphery of the reflector is forced laterally to abut other rim structure to form a metal-to-metal RF seal between the reflector and the rims. Certain assemblies with low profiles and low circumferential forces can be assembled without special tooling using plastic clamps and still achieve good RF seals. |
| US09577320B2 |
Antenna assembly and wireless communication device employing same
An antenna assembly includes an elastic piece, a connecting portion, a first radiating portion, and a second radiating. The connecting portion is coupled to the base board and includes a feeding point and a ground point. The first radiating portion is electrically connected to the feeding point and the elastic piece. The second radiating portion is electrically connected to the ground point and spaced from the first radiating portion. The first radiating portion, the elastic piece, and the second radiating portion are configured to operate at a first frequency band; the first radiating portion and the elastic piece generate a frequency-doubled effect to operate at a second frequency band. A wireless communication device employing the antenna assembly is also provided. |
| US09577319B2 |
Housing and electronic device using same
A housing includes a conductive metal base, a number of metal patterns, and a number of insulating fillers. The metal patterns are formed on the base and spaced from each other. Each of the plurality of insulating filler is situated between two adjacent metal patterns of the plurality of metal patterns. |
| US09577313B2 |
Pedestal for tracking antenna
There is provided a three-axes pedestal for stabilizing the pointing of a mobile tracking antenna. The pedestal comprises a base support with an azimuth axis support having a centerline defining a first axis or azimuth axis, and a first frame being rotatably mounted on the azimuth axis support to rotate about the first axis, where the first frame may hold at least part of a first horizontal linear bearing assembly. The pedestal further comprises a second frame with a lower frame part, which may be slidably interconnected to the first frame via the first horizontal linear bearing assembly. The first linear bearing assembly may include dampers or suspension members for dampening linear slide movement of the second frame along the first linear bearing assembly and thereby for dampening the relative movement of the second frame to the first frame. The pedestal also comprises a third frame interconnected to an upper part of the second frame, where the third frame holds a cross-elevation axis support with a centerline defining a second axis or cross-elevation axis. Furthermore, the pedestal comprises a fourth frame being rotatably mounted on the cross-elevation axis support of the third frame to rotate about the second axis, where the fourth frame holds an elevation axis support with a centerline defining a third axis or elevation axis. The pedestal also comprises a fifth frame supporting the tracking antenna, which fifth frame is rotatably mounted on the elevation axis support of the fourth frame to rotate about the third axis. The upper part of the second frame may hold a second linear bearing assembly, with the third frame being interconnected to the second frame via the second linear bearing assembly, and with the second linear bearing assembly providing a direction of linear slide movement and an axis of rotation for the third frame, thereby providing an axis of rotation for the second axis in a plane perpendicular to the direction of linear slide movement provided by the second linear bearing assembly. |
| US09577309B2 |
High-frequency wave transmitting device including a connecting portion for connecting a waveguide to an antenna
To reduce electromagnetic wave transmission loss, a connecting portion is provided on the end portion of a waveguide. A connecting portion has a first half and a second half, each made of a dielectric material. An antenna formed on a printed circuit board is interposed between the first half and the second half. The connecting portion has conductive portions and. The conductive portions have a shape corresponding to the cross-section of the conductive portion of the waveguide in cross-section orthogonal to the direction in which the circuit board extends, and surround the first half and the second half. |
| US09577307B2 |
Guided-wave transmission device and methods for use therewith
Aspects of the subject disclosure may include, for example, a transmission device that includes a transmitter that generates a first electromagnetic wave to convey data, the first electromagnetic wave having at least one carrier frequency and corresponding wavelength. A coupler couples the first electromagnetic wave to a transmission medium having at least one inner portion surrounded by a dielectric material, the dielectric material having an outer surface and a corresponding circumference, wherein the coupling of the first electromagnetic wave to the transmission medium forms a second electromagnetic wave that is guided to propagate along the outer surface of the dielectric material via at least one guided-wave mode that can include an asymmetric mode, wherein the at least one carrier frequency is within a microwave or millimeter-wave frequency band and wherein the at least one corresponding wavelength is less than the circumference of the transmission medium. Other embodiments are disclosed. |
| US09577306B2 |
Guided-wave transmission device and methods for use therewith
Aspects of the subject disclosure may include, for example, a transmission device that includes a transmitter that generates a first electromagnetic wave to convey data, the first electromagnetic wave having at least one carrier frequency and corresponding wavelength. A coupler couples the first electromagnetic wave to a transmission medium having at least one inner portion surrounded by a dielectric material, the dielectric material having an outer surface and a corresponding circumference, wherein the coupling of the first electromagnetic wave to the transmission medium forms a second electromagnetic wave that is guided to propagate along the outer surface of the dielectric material via at least one guided-wave mode that can include an asymmetric mode, wherein the at least one carrier frequency is within a microwave or millimeter-wave frequency band and wherein the at least one corresponding wavelength is less than the circumference of the transmission medium. Other embodiments are disclosed. |
| US09577303B2 |
Microwave attenuator module
An attenuator module having a substrate; a attenuator disposed on one surface of the substrate, the attenuator having an input terminal at one end of the attenuator and an output terminal at an opposite end of the attenuator; an electrical conductor disposed on an opposite surface of the substrate; and an electrically conductive via passing from the output terminal through the substrate to the electrical conductor disposed on the opposite surface of the substrate. |
| US09577299B2 |
Air cell
An air cell includes a positive electrode and a negative electrode, and an outer frame member located at outer peripheries of the positive electrode and the negative electrode. The positive electrode and the outer frame member are integrally joined together. An assembled battery includes a plurality of air cells, the air cells being stacked on top of each other. This configuration can increase mechanical strength and improve sealing performance for an electrolysis solution in the positive electrode. In addition, a reduction in thickness of the entire air cell can be achieved so that the assembled battery suitable for use in a vehicle can be provided. |
| US09577298B2 |
High efficiency iron electrode and additives for use in rechargeable iron-based batteries
An iron electrode and a method of manufacturing an iron electrode for use in an iron-based rechargeable battery are disclosed. In one embodiment, the iron electrode includes carbonyl iron powder and one of a metal sulfide additive or metal oxide additive selected from the group of metals consisting of bismuth, lead, mercury, indium, gallium, and tin for suppressing hydrogen evolution at the iron electrode during charging of the iron-based rechargeable battery. An iron-air rechargeable battery including an iron electrode comprising carbonyl iron is also disclosed, as is an iron-air battery wherein at least one of the iron electrode and the electrolyte includes an organosulfur additive. |
| US09577296B2 |
Electric vehicle battery with series and parallel fluid flow
A fluid cooled series/parallel battery pack is provided with a fluid flow system. A plurality of prismatic battery cells are arranged in parallel in two or more rows. Fluid flows in a series flow configuration from an upstream row of batteries to a downstream row of batteries. A bypass passageway provides additional fluid flow to an inner plenum located between the rows of batteries to reduce pressure drop and provide more uniform temperatures within the rows of battery cells. |
| US09577295B2 |
Battery system and temperature controlling unit thereof
A battery system may include a plurality of unit batteries each having a panel shape and stacked in series. The system may also include a plurality of heat conduction plates each having a panel shape and inserted between the unit batteries such that a first part of each respective heat conduction plate is inserted between opposing faces of corresponding unit batteries, with upper and lower faces of each respective heat conduction plate being in contact with the opposing faces of the corresponding unit batteries, and a second part of each respective heat conduction plate is exposed to an outside of the stacked unit batteries. The system may further include at least one heat pipe thermally coupling the plurality of heat conduction plates by successively penetrating the exposed second parts of the heat conduction plates, with an end of the heat pipe being thermally coupled to a heat radiator after penetrating a last heat conduction plate. |
| US09577294B2 |
Manufacturing method for secondary battery
A method of manufacturing for a secondary battery. The secondary battery is configured to include an electrode group in a battery package. The electrode group includes a positive electrode, a negative electrode, and a separator. The manufacturing method includes: (a) measuring a first voltage drop amount of the secondary battery with the passage of time in a state in which a compression force in a direction parallel to a lamination direction of the electrode group is applied to the electrode group via the battery package; (b) measuring a second voltage drop amount of the secondary battery with the passage of time in a state in which the compression force is released; and (c) detecting a small short circuit of the secondary battery by comparing the first voltage drop amount and the second voltage drop amount. |
| US09577292B2 |
Electronic device and battery pack
An electronic device includes a storing unit which is provided on a battery pack and which retains power information of the battery pack, an acquiring unit which is provided in the main unit and which acquires the power information of the battery pack from the storing unit, and a control unit which is provided in the main unit and which controls the operation of the main unit based on the power information of the battery pack. |
| US09577290B2 |
Nonaqueous solvent, nonaqueous electrolyte, and power storage device
A power storage device using an organic solvent as a nonaqueous solvent for a nonaqueous electrolyte, in which a CV charging period in CCCV charging can be prevented from being extended and which has high performance, can be provided. The power storage device includes a positive electrode, a negative electrode, and a nonaqueous electrolyte. The nonaqueous electrolyte includes an ionic liquid including an alicyclic quaternary ammonium cation having one or more substituents and a counter anion to the alicyclic quaternary ammonium cation, a cyclic ester, and an alkali metal salt. In particular, in the power storage device, the ionic liquid content is greater than or equal to 70 wt % and less than 100 wt % per unit weight of the ionic liquid and the cyclic ester in the nonaqueous electrolyte, or greater than or equal to 50 wt % and less than 80 wt % per unit weight of the nonaqueous electrolyte. |
| US09577287B2 |
Galvanic cells and components therefor
The present invention provides an electrolyte component containing one or more salts including lithium bis(oxalate)borate (LiBOB), a solvent, propylene carbonate (PC) and a crystallizable polymer wherein said LiBOB is present as a weight percentage of 0.5% or more, said propylene carbonate is present as a weight percentage of between 5% and 90% and the crystallizable polymer is present at a weight percentage of greater than 1%. It also provides a galvanic cell formed from the above and a process for forming same. |
| US09577286B2 |
Method of producing solid state lithium battery module
The invention provides a method of producing a solid state lithium battery module in which the occurrence of short circuit caused by dendrites is suppressed. The invention solves this problem by providing a method of producing a solid state lithium battery module, including steps of: a pressing step of pressing a sulfide glass having an ion conductor containing a Li element, a P element, and a S element, and forming a solid electrolyte layer; and a restraining step of restraining a solid state lithium battery including the solid electrolyte layer, using restraining member, wherein, in the pressing step, the solid electrolyte layer is formed such that the average pore radius obtained by a mercury intrusion method is R (μm), and in the restraining step, the solid state lithium battery is restrained such that when the confining pressure is designated as P(MPa), the relationship: P≦−5900R+74 is satisfied. |
| US09577283B2 |
Energy storage battery
A redox flow battery is described, mainly including a charge/discharge cell, a cathode electrolyte tank, and an anode electrolyte tank. The inside of the charge/discharge cell is divided into a cathode cell and an anode cell by a diaphragm. A collector plate and a cathode are contained in the cathode cell. An aqueous solution containing a Mn-polyethyleneimine complex is supplied from the cathode electrolyte tank to the cathode through a supply pipe. Thereby, an energy storage battery that has durability sufficient for practical applications in a wide range of fields can be provided. |
| US09577282B2 |
Redox flow battery
A redox flow battery. A metal-ligand coordination compound including an aromatic ligand that contains an electron withdrawing group is used as the catholyte and/or the anolyte so that a redox flow battery having high energy density and excellent charge/discharge efficiency may be provided. |
| US09577281B1 |
Method of making a fuel cell device
Two active cell structures are prepared each comprising anode/electrolyte/cathode layers, each anode and cathode layer having embedded spaced-apart physical structures therein. Two interconnect sublayers are prepared, each comprising a layer of non-conductive material with holes formed therein and a conductor layer formed on one surface. The sublayers are placed together with the conductor layers in contact and with the holes offset to form an interconnect layer, which is then stacked between the two active cell structures. The multi-layer stack is laminated together and the anode layer of one active cell structure and the cathode layer of the other active cell structure fill the adjacent holes in the interconnect layer. The physical structures are pulled out to reveal embedded gas passages, and the multi-layer stack is sintered to form two active cells connected in series by the interconnect layer. |
| US09577278B2 |
Hybrid membranes containing titanium dioxide doped with fluorine
Hybrid membranes based on crystalline titanium dioxide containing fluorine atoms within the crystalline lattice comprising atoms of titanium and oxygen are described; these hybrid membranes are particularly suitable for the production of fuel cells and electrolysers. A process for producing the aforesaid hybrid membranes is also described. |
| US09577273B2 |
Fluidic interface module for a fuel cell system
Purge valves that are manually turned ON but are automatically or electrically turned OFF as the fuel cell's production of electricity reaches a predetermined level, e.g., steady state or thereabout are disclosed. The purge valve may be opened at system start-up, or may be opened at system shut-down so that the purge valve is armed and the fuel cell system is purged at the next start-up. Also disclosed is an integrated fluidic interface module that contains various fluidic components including one of these purge valves. The integrated fluidic interface module can operate passively or without being actively controlled by a processor. Methods of operating a fuel cell system, wherein the fuel cell system is purged at system start-up, are also disclosed. The purging automatically stops when the anode plenum is fully purged and replaced with fuel. |
| US09577271B2 |
Fuel cell system and its control method
A fuel cell system includes; a fuel cell which generates electricity by using a fuel gas and an oxidant gas as reaction gases; current control means which controls current of a fuel cell; voltage control means which controls voltage of the fuel cell; and heat value control means which calculates a heat value required by the fuel cell system and decides a target current value of the current control means and a target voltage value of the voltage control means so as to generate the calculated necessary heat amount, thereby controlling the heat value. Thus, it is possible to supply a heat required for the fuel cell system without increasing the size of the fuel cell system. |
| US09577266B2 |
Negative grid for battery
A method for producing a negative grid for a battery which includes providing a strip of battery grid material and performing a punching operation on the battery grid material to remove material and form a grid. The punching operation produces a negative battery grid having a plurality of grid wires bounded by a frame. The battery grid includes a top frame member. A first side frame member is coupled to the top frame member at a first end thereof. A second side frame member is coupled to the top frame member at a second end thereof. A bottom frame member is spaced apart from the top frame member and coupled to the first side frame member and the second side frame member. The negative grid does not include exposed wire ends that may puncture a polymeric separator when the negative grid is provided within the separator. |
| US09577265B2 |
Thin film lithium ion battery
A thin film lithium ion battery includes a cathode electrode, an anode electrode, and a solid electrolyte layer. The solid electrolyte layer is sandwiched between the cathode electrode and the anode electrode. At least one of the cathode electrode and the anode electrode includes a current collector. The current collector is a carbon nanotube layer consisting of a plurality of carbon nanotubes. |
| US09577263B2 |
Anode active material-containing slurry, anode using the slurry and electrochemical device comprising the anode
The present disclosure relates to an anode active material-containing slurry, an anode using the slurry, and an electrochemical device comprising the anode. More specifically, the present disclosure relates to a slurry comprising an anode active material; a polymer binder comprising styrene butadiene rubber and potassium polyacrylate; a conductive material; and a dispersing medium, an anode using the slurry, and an electrochemical device comprising the anode. The anode active material-containing slurry according to one aspect of the present disclosure can relieve the volume expansion of an anode active material by the intercalation and disintercalation of lithium during cycles of electrochemical devices to improve the durability of an anode active material layer, thereby enhancing the life characteristics of the electrochemical devices, and can form an anode active material layer having a high peeling force even though potassium polyacrylate with a relatively lower weight-average molecular weight is used. |
| US09577262B2 |
Positive electrode material for lithium ion secondary cell and lithium ion secondary cell
A positive electrode material for a lithium ion secondary cell, includes: a binding agent in which an active material formed from a lithium metal oxide are dispersed together with barium titanate and conductive carbon. |
| US09577261B2 |
Lithium ion secondary battery and method for manufacturing the same
A lithium ion secondary battery includes a positive electrode, a negative electrode, and an electrolyte provided between the positive electrode and the negative electrode. The positive electrode includes a positive electrode current collector and a positive electrode active material layer over the positive electrode current collector. The positive electrode active material layer includes a plurality of lithium-containing composite oxides each of which is expressed by LiMPO4 (M is one or more of Fe (II), Mn (II), Co (II), and Ni (II)) that is a general formula. The lithium-containing composite oxide is a flat single crystal particle in which the length in the b-axis direction is shorter than each of the lengths in the a-axis direction and the c-axis direction. The lithium-containing composite oxide is provided over the positive electrode current collector so that the b-axis of the single crystal particle intersects with the surface of the positive electrode current collector. |
| US09577260B2 |
Ultra-lightweight energy storage material
Disclosed are compositions containing a formula of LixTiyV1Bz wherein x, y, and z are real numbers greater than zero. In certain embodiments, x is not greater than 7, and y is not greater than 6, or a combination thereof. The composition may be a microporous aerogel, a mesoporous aerogel, a crystalline structure, or a combination thereof. In certain embodiments, the composition may be an aerogel, and a surface of the aerogel comprises microcrystals, nanocrystals or a combination thereof. The compositions have very low densities. Also disclosed are methods to produce the composition and use of the composition in energy storage devices. |
| US09577258B2 |
Method of preparing composite cathode active material, composite cathode active material, and cathode and lithium battery containing the composite cathode active material
Provided are a method of preparing a cathode active material, a composite cathode active material, and a cathode and a lithium battery containing the composite cathode active material. The method includes mixing a transition metal source and a reducing agent to prepare a cathode active material precursor; and mixing and calcining the cathode active material precursor to prepare a lithium transition metal oxide, wherein a supplied amount of the reducing agent is about 0.003 mole/hr or less with respect to 1 mole/hr of a supplied amount of the transition metal source. |
| US09577255B2 |
Negative electrode active material for non-aqueous electrolyte rechargeable battery, method of fabricating the same, and non-aqueous electrolyte rechargeable battery including the same
A camera module is disclosed, the camera module including a PCB (Printed Circuit Board), a base arranged at an upper surface of the PCB, a holder member arranged at an upper surface of the base and formed with a plurality of magnet reception portions, a surface of which facing the base is opened, and a plurality of magnets coupled to the magnet reception portions, wherein the base is formed with a protrusion configured to support a bottom surface of the magnet by being protrusively formed at a position corresponding to an opening of the magnet reception portions. |
| US09577253B2 |
Positive-electrode materials: methods for their preparation and use in lithium secondary batteries
A positive-electrode material for a lithium secondary battery which includes a lithium oxide compound or a complex oxide as reactive substance. The material also includes at least one type of carbon material, and optionally a binder. A first type of carbon material is provided as a coating on the reactive substance particles surface. A second type of carbon material is carbon black. And a third type of carbon material is a fibrous carbon material a mixture of at least two types of fibrous carbon material different in fiber diameter and/or fiber length. Also, a method for preparing the material as well as lithium secondary batteries including the material. |
| US09577249B2 |
Cathode material for lithium secondary battery, and method of producing said cathode material
A cathode material for a lithium secondary battery, including fibrous carbon and a plurality of cathode active material particles bonded to a surface of the fibrous carbon. The cathode active material particles are composed of olivine-type LiMPO4 where M represents one or more kinds of elements selected from Fe, Mn, Ni, and Co. Also disclosed is a method of producing the cathode material and a lithium secondary battery. |
| US09577246B2 |
Negative electrode active material, negative electrode for nonaqueous electrolyte secondary battery, and nonaqueous electrolyte secondary battery
Provided is a negative electrode active material containing SiOx and carbonaceous particles containing graphite and having both good discharge capacity and good electric conductivity. Also provided is a negative electrode using the negative electrode active material and a nonaqueous electrolyte secondary battery. When the carbonaceous particles have an average particle diameter D50 of α (μm) and a BET specific surface area of β (m2/g), the α and the β satisfy the following Formulae (1) and (2). β≦−(12/18)α+12 (1) 5≦α≦15 (2). |
| US09577243B2 |
Use of expanded graphite in lithium/sulphur batteries
The present invention relates to a solid composite for use in the cathode of a lithium-sulphur electric current producing cell wherein the solid composite comprises 1 to 75 wt.-% of expanded graphite, 25 to 99 wt.-% of sulphur, 0 to 50 wt.-% of one or more further conductive agents other than expanded graphite, and 0 to 50 wt.-% one or more binder, based on the total amount of the solid composite, a lithium-sulphur electric current producing cell comprising (i) a cathode comprising the solid composite, (ii) an anode and (iii) an electrolyte interposed between said cathode and said anode, and a process for preparing the solid composite comprising the steps (I) preparing a slurry comprising sulphur, expanded graphite, and optionally further components in a liquid medium by dispersing the sulphur, the expanded graphite, and optionally the further components in the liquid medium; (II) casting the slurry provided in step (I) on a substrate or placing the slurry provided in step (I) into a mold; and (III) removing some or all of the liquid medium from the slurry cast in step (II) to form a solid composite. |
| US09577242B2 |
Internal header flow divider for uniform electrolyte distribution
The present disclosure details header flow divider designs and methods of electrolyte distribution. Internal header flow dividers may include multiple flow channels and may be built into flow frames. Flow channels within internal header flow dividers may divide evenly multiple times in order to form multiple flow channel paths and provide a uniform distribution of electrolytes throughout electrode sheets within electrochemical cells. Furthermore, uniform electrolyte distribution across electrode sheets may not only enhance battery performance, but also prevent zinc dendrites that may be formed in electrode sheets. The prevention of zinc dendrite growth in electrode sheets may increase operating lifetime of flow batteries. The disclosed internal header flow dividers may also be included within end caps of electrochemical cells. |
| US09577236B2 |
Multi-region battery separators
Disclosed is a battery separator, comprising two fiber regions comprising glass fibers, and a middle fiber region disposed between them comprising larger average diameter fibers and specified amounts of silica, or fine fibers, or both; and processes for making the separator. Also disclosed is a battery separator, comprising a fiber region and either one or two silica-containing region(s) adjacent thereto, each of the regions containing a specified amount of silica; and processes for making the separator. Such separators are useful, e.g., in lead-acid batteries. |
| US09577234B2 |
Separator material for forming a separator for a lead-acid accumulator
The invention relates to a separator material (6) for forming a separator for a lead-acid accumulator, especially in the form of unfinished rolled product, and a method for the production thereof. The inventive separator material (6) comprises a first layer in the form of a microporous film (1) and at least one second layer in the form of a planar fleece material (7). At least one face of the microporous film (1), which is made of a thermoplastic material, is provided with a number of protrusions (2, 2′) defining an area with an increased film thickness on a basic film sheet. The fleece material (7) is welded to the film (1) by means of ultrasonic welding in such a way that the planar fleece material (7) is located at least at the level of the surface of the basic film sheet without invading the same in the area of the welded joints (8). |
| US09577231B2 |
Lithium ion battery module
A lithium-ion battery module includes a housing having a plurality of partitions configured to define a plurality of compartments within a housing. The battery module also includes a lithium-ion cell element provided in each of the compartments of the housing. The battery module further includes a cover coupled to the housing and configured to route electrolyte into each of the compartments. The cover is also configured to seal the compartments of the housing. |
| US09577229B2 |
Secondary battery
A secondary battery includes an electrode assembly including a first electrode plate including a first electrode non-coating portion on which an active material of the first electrode plate is not coated, a second electrode plate including a second electrode non-coating portion on which an active material of the second electrode plate is not coated, and a separator between the first and second electrode plates; a collector electrically connected to an electrode non-coating portion of the first and second electrode non-coating portions, the collector including an insulation part at an insulation region of the collector adjacent the first and second electrode plates; and a case accommodating the electrode assembly and the collector. |
| US09577226B2 |
Rechargeable battery with buffer sheet between electrode assembly and battery case
A rechargeable battery includes an electrode assembly in a battery case, and a buffer sheet between the electrode assembly and the battery case, the buffer sheet contacting the electrode assembly and the battery case. |
| US09577222B2 |
Light-emitting device having multi-thickness transparent conductive layers
To provide a novel light-emitting device with high productivity, the light-emitting device includes a first light-emitting element, a second light-emitting element, and a third light-emitting element. In the first light-emitting element, a first lower electrode, a first transparent conductive layer, a first light-emitting layer, a second light-emitting layer, and an upper electrode are stacked in this order. In the second light-emitting element, a second lower electrode, a second transparent conductive layer, the first light-emitting layer, the second light-emitting layer, and the upper electrode are stacked in this order. In the third light-emitting element, a third lower electrode, a third transparent conductive layer, the second light-emitting layer, and the upper electrode are stacked in this order. The first transparent conductive layer includes a first region. The second transparent conductive layer includes a second region as thick as the third transparent conductive layer. The first region is thicker than the second region. |
| US09577221B2 |
Three stack hybrid white OLED for enhanced efficiency and lifetime
OLEDs containing a stacked hybrid architecture including a phosphorescent organic emissive unit and two fluorescent organic emissive units are disclosed. The stacked hybrid architecture includes a plurality of electrodes and a hybrid emissive stacked disposed between at least two of the electrodes. The stack contains at least three emissive units and at least two charge generation layers. At least one of the three emissive units is a phosphorescent organic emissive unit and at least two of the three emissive units are fluorescent organic emissive units. More specifically, the two fluorescent organic emissive units may be blue organic emissive units that emit light from the same or different color regions. |
| US09577219B2 |
Light-emitting module, light-emitting device, method of manufacturing the light-emitting module, and method of manufacturing the light-emitting device
A highly reliable light-emitting module including an organic EL element or a light-emitting device using a highly reliable light-emitting module including an organic EL element is provided. Alternatively, a method of manufacturing a highly reliable light-emitting module including an organic EL element, or a method of manufacturing a light-emitting device using a highly reliable light-emitting module including an organic EL element is provided. The light-emitting module has a structure in which a light-emitting element formed over a first substrate and a viscous material layer are sealed in a space between the first substrate and a second substrate which face each other, with a sealing material surrounding the light-emitting element. The viscous material layer is provided between the light-emitting element and the second substrate and includes a non-solid material and a drying agent which reacts with or adsorbs an impurity. |
| US09577215B2 |
Display device with glass frit sealing portion
A display device includes: a substrate on which a display is formed; an encapsulation portion covering the substrate; and a sealing portion arranged between the substrate and the encapsulation portion and surrounding the display, wherein at least one power wire passes between the substrate and the encapsulation portion, and wherein a metal layer is formed between the sealing portion and the at least one power wire. |
| US09577209B2 |
Light-emitting device and manufacturing method thereof, lighting device, and display device
The present invention focuses on a structure in which an auxiliary wiring for increasing the conductivity of an upper electrode is provided on the substrate side. The conductive auxiliary wiring of a light-emitting device is provided over a substrate, and an upper portion of the auxiliary wiring protrudes in a direction parallel to the substrate. Further, an EL layer formed in a region including a lower electrode layer and the auxiliary wiring is physically divided by the auxiliary wiring. An upper electrode layer formed in a manner similar to that of the lower electrode layer may be electrically connected to at least part of a side surface of the auxiliary wiring. Such an auxiliary wiring may be used in a lighting device and a display device. |
| US09577207B2 |
Organic light emitting display device with insulating part and method of manufacturing the same
Disclosed is an organic light emitting display device. The organic light emitting display device includes a substrate, a pixel electrode disposed on the substrate, an organic emission layer disposed on the pixel electrode, a common electrode including a metal layer disposed on the organic emission layer, a conductive organic layer disposed on the metal layer, and a first metal oxide layer disposed on the conductive organic layer, and an insulating part formed in a part of an area of a surface of the metal layer which is exposed to a foreign material. The insulating part insulates the pixel electrode from the common electrode. |
| US09577196B2 |
Optoelectronics integration by transfer process
A method for fabricating an optoelectronic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at the adhesion layer by mechanically yielding the adhesion layer. A conductive layer is applied to the material layer on a side opposite the release tape to form a transfer substrate. The transfer substrate is transferred to a target substrate to join the target substrate to the conductive layer of the transfer substrate. The release tape is removed from the material layer to form a top emission optoelectronic device. |
| US09577192B2 |
Method for forming a metal cap in a semiconductor memory device
Exemplary embodiments of the present invention are directed towards a method for fabricating a semiconductor memory device comprising selectively depositing a material to form a cap above a recessed cell structure in order to prevent degradation of components inside the cell structure in oxidative or corrosive environments. |
| US09577186B2 |
Non-volatile resistive oxide memory cells and methods of forming non-volatile resistive oxide memory cells
A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. The first conductive electrode has an elevationally outermost surface and opposing laterally outermost edges at the elevationally outermost surface in one planar cross section. Multi-resistive state metal oxide-comprising material is formed over the first conductive electrode. Conductive material is deposited over the multi-resistive state metal oxide-comprising material. A second conductive electrode of the memory cell which comprises the conductive material is received over the multi-resistive state metal oxide-comprising material. The forming thereof includes etching through the conductive material to form opposing laterally outermost conductive edges of said conductive material in the one planar cross section at the conclusion of said etching which are received laterally outward of the opposing laterally outermost edges of the first conductive electrode in the one planar cross section. |
| US09577183B2 |
Methods of manufacturing a magnetoresistive random access memory device
In a method of manufacturing a MRAM device, a lower electrode is formed on a substrate. A first magnetic layer, a tunnel barrier layer, and a second magnetic layer are sequentially formed on the lower electrode layer. An etching mask is formed on the second magnetic layer. An ion beam etching process in which a first ion beam and a second ion beam are simultaneously emitted onto the substrate is performed to form a MTJ structure including a first magnetic layer pattern, a tunnel layer pattern, and a second magnetic layer pattern from the first magnetic layer, the tunnel barrier layer, and the second magnetic layer, respectively, the MTJ structure has no by-products remaining after the ion beam etching process is performed. |
| US09577180B2 |
Electrostatically controlled magnetic logic device
A magnetic logic cell includes a first electrode portion, a magnetic portion arranged on the first electrode, the magnetic portion including an anti-ferromagnetic material or a ferrimagnetic material, a dielectric portion arranged on the magnetic portion, and a second electrode portion arranged on the dielectric portion. |
| US09577177B1 |
System and method for fabricating super conducting circuitry on both sides of an ultra-thin layer
A method of fabricating circuitry in a wafer includes depositing a superconducting metal on a silicon on insulator wafer having a handle wafer, coating the wafer with a sacrificial layer and bonding the wafer to a thermally oxide silicon wafer with a first epoxy. The method includes flipping the wafer, thinning the flipped wafer by removing a handle wafer, etching a buried oxide layer, depositing a superconducting layer, bonding the wafer to a thermally oxidized silicon wafer having a handle wafer using an epoxy, flipping the wafer again, thinning the flipped wafer, etching a buried oxide layer from the wafer and etching the sacrificial layer from the wafer. The result is a wafer having superconductive circuitry on both sides of an ultra-thin silicon layer. |
| US09577174B2 |
CVD nanocrystalline silicon thermoelectric material
A process for forming a doped nc-Si thin film thermoelectric material. A nc-Si thin film is slowly deposited on a substrate, either by hot-wire CVD (HWCVD) with a controlled H2:SiH4 ratio R=6-10 or by plasma-enhanced (PECVD) with a controlled R=80-100, followed by ion implantation of an n- or p-type dopant and a final annealing step to activate the implanted dopants and to remove amorphous regions. A doped nc-Si thin film thermoelectric material so formed has both a controllable grain size of from a few tens of nm to 3 nm and a controllable dopant distribution and thus can be configured to provide a thermoelectric material having predetermined desired thermal and/or electrical properties. A final annealing step is used to activate the dopants and remove any residual amorphous regions. |
| US09577167B2 |
Semiconductor light emitting device
A semiconductor light emitting device including a plurality of light emitting elements can be miniaturized while enabling to emit light with high luminance. The semiconductor light emitting device can include a mounting substrate, and a plurality of semiconductor light emitting elements mounted on the mounting substrate side by side, each of the semiconductor light emitting elements having a semiconductor structure layer that can include a first semiconductor layer of a first conductivity type, an active layer, and a second semiconductor layer of a second conductivity type opposite to the first conductivity type, which are layered in that order. Each of the semiconductor light emitting elements can have a resonator constituted by end surfaces of the semiconductor structure layer opposite to each other, and also has a recessed portion recessed from the surface of the second semiconductor layer toward the active layer. |
| US09577166B2 |
Light emitting device package and lighting system including the same
Provided are a light emitting device package and a lighting system including the light emitting device package. The light emitting device package includes a package body, at least one electrode on the package body, a light emitting device on the package body, a reflective structure around the light emitting device on the package body and a lens on the light emitting device and the electrode. |
| US09577158B2 |
Phosphor sheet-forming resin composition
A phosphor sheet-forming resin composition uses a low-cost resin material having high light fastness and low visible light absorption and is capable of providing a phosphor sheet at low cost with deterioration of a phosphor due to moisture being suppressed. The phosphor sheet-forming resin composition contains a film-forming resin composition and a powdery phosphor that emits fluorescence when irradiated with excitation light. The film-forming resin composition contains a hydrogenated styrene-based copolymer, and uses a sulfide-based phosphor as the phosphor. Examples of the hydrogenated styrene-based copolymer include hydrogenated products of styrene-ethylene-butylene-styrene block copolymers. CaS:Eu is used as a preferred sulfide-based phosphor. |
| US09577157B2 |
Light emitting diode chip having distributed Bragg reflector and method of fabricating the same
A light-emitting diode package, including a package body and leads, the package body including a mounting surface, a light-emitting structure disposed on the mounting surface, the light-emitting structure including an active layer disposed between a first conductive-type semiconductor layer and a second conductive-type semiconductor layer, a phosphor layer disposed on the light-emitting structure, and a distributed Bragg reflector disposed between the light-emitting structure and the mounting surface. The distributed Bragg reflector includes a first distributed Bragg reflector and a second distributed Bragg reflector, and an optical thickness of material layers within the first distributed Bragg reflector is greater than an optical thickness of material layers within the second distributed Bragg reflector. |
| US09577155B2 |
Light emitting device
A light emitting device includes at least one layer below or above a reflective layer to prevent delamination of the reflective layer from a layer below and/or above the reflective layer. |
| US09577154B2 |
Light emitting chip
A light emitting chip includes a light emitting unit, a eutectic layer and a surface passivation layer. The eutectic layer has a first surface and a second surface opposite to each other. The light emitting chip connects to the first surface of the eutectic layer. The surface passivation layer covers the second surface of the eutectic layer. A material of the surface passivation layer includes at least a metal of an oxidation potential from −0.2 volts to −1.8 volts. |
| US09577150B2 |
Light emitting device and light emitting device package
Disclosed are a light emitting device and a light emitting device package. The light emitting device includes a light emitting structure including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer, an adhesive layer contacting a top surface of the first conductive semiconductor layer, a first electrode contacting a top surface of the first conductive semiconductor and a top surface of the adhesive layer, and a second electrode contacting the second conductive semiconductor layer, wherein the adhesive layer contacting the first electrode is spaced apart from the second electrode. |
| US09577148B2 |
Light emitting diode element and method of manufacturing the same
An n-type GaN layer made of n-type gallium nitride (GaN) is formed on a sapphire substrate. A plurality of island-phased layered structures are formed in random sizes between the n-type GaN layer and a p-type GaN layer that is made of p-type GaN. Each of the layered structures is configured by stacking multiple AlN layers made of aluminum nitride (AlN) and multiple InGaN layers made of indium gallium nitride (InGaN) on an AlN base layer. The respective layered structures emit lights of different wavelengths. This accordingly allows for emission of light in a wider wavelength range. |
| US09577147B2 |
Light emitting device package and manufacturing method thereof
A light emitting device (LED) package and a manufacturing method thereof are provided. The LED package includes an LED including a first electrode pad and a second electrode pad disposed on one surface thereof; a bonding insulating pattern layer configured to expose the first electrode pad and the second electrode pad; a substrate including a via hole bored from a first surface to a second surface and a wiring metal layer formed on an inner surface of the via hole to extend to a part of the second surface; and a bonding metal pattern layer bonded to the wiring metal layer exposed through the via hole at the first surface of the substrate and also bonded to the first electrode pad and the second electrode pad. |
| US09577144B2 |
Ultraviolet light-emitting device
Disclosed is an ultraviolet light-emitting device. The light-emitting device includes: an n-type contact layer including a GaN layer; a p-type contact layer including an AlGaN or AlInGaN layer; and an active region of multiple quantum well structure positioned between the n-type contact layer and the p-type contact layer. In addition, the active region of multiple quantum well structure includes a GaN or InGaN layer with a thickness less than 2 nm, radiating an ultraviolet ray with a peak wavelength of 340 nm to 360 nm. |
| US09577142B2 |
Process for forming semiconductor laser diode implemented with sampled grating
A method to produce a semiconductor laser diode (LD) including a sampled grating (SG) is disclosed. The method prepares various resist patterns each including grating regions and space regions alternately arranged along an optical axis. The grating regions and the space region in respective cavity types have total widths same with the others but the grating regions in respective types has widths different from others. After the formation of the grating patterns based on the resist patterns, only one of the grating patterns is used for subsequent processes. |
| US09577138B2 |
Solar cell and manufacturing method thereof
A solar cell is formed to have a silicon semiconductor substrate of a first conductive type; an emitter layer having a second conductive type opposite the first conductive type and formed on a first surface of the silicon semiconductor substrate; a back surface field layer having the first conductive type and formed on a second surface of the silicon semiconductor substrate opposite to the first surface; and wherein the emitter layer includes at least a first shallow doping area and the back surface field layer includes at least a second shallow doping area, and wherein a thickness of the first shallow doping area of the emitter layer is different from a thickness of the second shallow doping area of the back surface field layer. |
| US09577136B2 |
Semiconductor light-receiving element and method for manufacturing same
The present invention pertains to a semiconductor light-receiving element and a method for manufacturing the same, enabling operation in a wide wavelength bandwidth and achieving fast response and high response efficiency. A PIN type photodiode made by sequentially layering on top of the substrate a Si layer of a first conductivity type, a non-doped Ge layer and a Ge layer of a second conductivity type that is the opposite type of the first conductivity type and a Ge current-blocking mechanism is provided in at least part of the periphery of the PIN type photodiode. |
| US09577134B2 |
Solar cell emitter region fabrication using self-aligned implant and cap
Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described. In an example, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions. |
| US09577132B2 |
Solar cell module
A solar cell module includes a plurality of solar cells each including a substrate, an emitter region positioned at a back surface of the substrate, first electrodes electrically connected to the emitter region, second electrodes electrically connected to the substrate, a first current collector positioned at ends of the first electrodes, and a second current collector at ends of the second electrodes, and a first connector connecting a first current collector of a first solar cell of the plurality of solar cells to a second current collector of a second solar cell adjacent to the first solar cell. The first current collector of the first solar cell and the second current collector of the second solar cell each have a different polarity. |
| US09577131B2 |
Concentrator photovoltaic module, concentrator photovoltaic panel, and flexible printed circuit for concentrator photovoltaic module
A concentrator photovoltaic module including: a flexible printed circuit provided in contact with a bottom surface of a housing; and a primary concentrating portion formed by a plurality of lens elements being arranged, each lens element concentrating sunlight, wherein the flexible printed circuit includes: an insulating base material and a conductive pattern; a plurality of power generating elements provided on the pattern, so as to correspond to the lens elements, respectively; a cover lay as a covering layer having insulating property and a low water absorption not higher than a predetermined value, the cover lay covering and sealing a conductive portion including the pattern on the insulating base material; and an adhesive layer having insulating property and a low water absorption not higher than the predetermined value, the adhesive layer bonding the insulating base material and the covering layer together. |
| US09577127B1 |
Composite material for fluorescent quantum dot micro-nano packaging
A composite material for fluorescent quantum dot micro-nano packaging. The composite material comprises fluorescent quantum dots, a mesoporous particle material having a nanometer lattice structure, and a barrier layer, wherein the fluorescent quantum dots are distributed in the mesoporous particle material, and the barrier layer is coated on the outer surface of the mesoporous particle material. In the composite material according to the invention, the quantum dot aggregation can be effectively retarded, with the barrier layer coated on the surface the water-oxygen micromolecule erosion is prevented, the compatibility and stability of the composite fluorescent particles is improved, and the service life of the composite material for fluorescent quantum dot micro-nano packaging is thus greatly improved. |
| US09577126B2 |
Solar cell emitter region fabrication using ion implantation
Methods of fabricating solar cell emitter regions using ion implantation, and resulting solar cells, are described. In an example, a back contact solar cell includes a crystalline silicon substrate having a light-receiving surface and a back surface. A first polycrystalline silicon emitter region is disposed above the crystalline silicon substrate. The first polycrystalline silicon emitter region is doped with dopant impurity species of a first conductivity type and further includes ancillary impurity species different from the dopant impurity species of the first conductivity type. A second polycrystalline silicon emitter region is disposed above the crystalline silicon substrate and is adjacent to but separated from the first polycrystalline silicon emitter region. The second polycrystalline silicon emitter region is doped with dopant impurity species of a second, opposite, conductivity type. First and second conductive contact structures are electrically connected to the first and second polycrystalline silicon emitter regions, respectively. |
| US09577125B2 |
Colloidal semiconducting structure
The present invention is based on a unique design of a novel structure, which incorporates two quantum dots of a different bandgap separated by a tunneling barrier. Upconversion is expected to occur by the sequential absorption of two photons. In broad terms, the first photon excites an electron-hole pair via intraband absorption in the lower bandgap dot, leaving a confined hole and a relatively delocalized electron. The second absorbed photon can lead, either directly or indirectly, to further excitation of the hole, enabling it to then cross the barrier layer. This, in turn, is followed by radiative recombination with the delocalized electron. |
| US09577123B2 |
Nanostructure and optical device having nanostructure
Provided are nanostructures and optical devices having the nanostructures. The nanostructure may include a carbon nanomaterial layer, a nanopattern formed on the carbon nanomaterial layer, and a metal layer formed on a surface of the nanopattern. The nanostructure may be formed in a ring shape, and the metal layer may include a plurality of metal layers formed of different metals. |
| US09577122B2 |
Conductive paste-forming electrode, solar cell manufacturing method and solar cell
A conductive paste is provided which can form electrodes in crystalline silicon solar cells at low cost while ensuring that the electrodes exhibit low contact resistance with respect to both p-type and n-type impurity diffusion layers. The conductive paste for forming a solar cell electrode includes a silver powder, a glass frit, an additive particle and an organic vehicle, the glass frit having a glass transition point of 150 to 440° C., the additive particle including an alloy material containing 20 to 98 mass % aluminum, the conductive paste including the additive particle in an amount of 2 to 30 parts by weight with respect to 100 parts by weight of the silver powder. |
| US09577121B2 |
Tetra-lateral position sensing detector
The present invention is directed to a position sensing detector made of a photodiode having a semi insulating substrate layer; a buffered layer that is formed directly atop the semi-insulating substrate layer, an absorption layer that is formed directly atop the buffered layer substrate layer, a cap layer that is formed directly atop the absorption layer, a plurality of cathode electrodes electrically coupled to the buffered layer or directly to the cap layer, and at least one anode electrode electrically coupled to a p-type region in the cap layer. The position sensing detector has a photo-response non-uniformity of less than 2% and a position detection error of less than 10 μm across the active area. |
| US09577119B2 |
Solar module with a plug-in device
A solar module with a front side surface and a rear side surface, has a front side encapsulation element which forms the front side surface of the solar module, a multiplicity of solar cells which are connected electrically to one another, a rear side encapsulation element which forms the rear side surface of the solar module with a rear side surface plane and has a polymer plastic film, and at least one plug-in device connecting to a complementary structure. The plug-in device is at least partially laminated into the rear side encapsulation element, in the region of an overlapping section, wherein the rear site encapsulation element has an opening and the plug-in device is arranged at least partially in the opening. The plug-in device projects beyond the rear side surface plane of the solar module by a maximum of 15 mm. |
| US09577114B2 |
Transistors, methods of forming transistors and display devices having transistors
A transistor, a display device, and associated methods, the transistor including a substrate; an active layer pattern disposed on the substrate, the active layer pattern including silicon and graphene; a gate insulating layer disposed on the active layer pattern; a gate electrode disposed on the gate insulating layer; an insulating interlayer covering the active layer pattern and the gate electrode; and a source electrode and a drain electrode in contact with the active layer pattern. |
| US09577111B2 |
Method of fabricating thin film transistor
A method of fabricating a thin film transistor including following steps is provided. Sequentially form a semiconductor layer, a metal layer and an auxiliary layer on a substrate. Perform a crystallization process to transform the semiconductor layer into an active layer after the metal layer and the auxiliary layer are disposed on the semiconductor layer. After the active layer is formed, pattern the metal layer to form a source and a drain. Form a gate insulator and a gate. The gate insulator is disposed between the gate and the source and drain. |
| US09577109B2 |
Transparent conducting film and preparation method thereof
There are provided a transparent conductive film and a method for preparing the same. The transparent conductive film of the present application comprises a compound having a crystalline structure and represented by Chemical Formula 1 and thus can be applied as a technology substituting for conventional ITO conductive films. |
| US09577107B2 |
Oxide semiconductor film and method for forming oxide semiconductor film
To improve crystallinity of an oxide semiconductor. To provide a crystalline oxide semiconductor film in which a crystallized region extends to the interface with a base or the vicinity of the interface, and to provide a method for forming the oxide semiconductor film. An oxide semiconductor film containing indium, gallium, and zinc is formed, and the oxide semiconductor film is irradiated with an energy beam, thereby being heated. Note that the oxide semiconductor film includes a c-axis aligned crystal region or microcrystal. |
| US09577101B2 |
Source/drain regions for fin field effect transistors and methods of forming same
A method for forming a semiconductor device includes forming a fin extending upwards from a semiconductor substrate and forming a sacrificial layer on sidewalls of a portion of the fin. The method further includes forming a spacer layer over the sacrificial layer and recessing the portion of the fin past a bottom surface of the sacrificial layer. The recessing forms a trench disposed between sidewall portions of the spacer layer. At least a portion of the sacrificial layer is removed, and a source/drain region is formed in the trench. |
| US09577099B2 |
Diamond shaped source drain epitaxy with underlying buffer layer
A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy. |
| US09577096B2 |
Salicide formation on replacement metal gate finFet devices
A fin field effect transistor (finFET) device and a method of fabricating a finFET are described. The method includes forming a replacement gate stack on a substrate between inside walls of sidewall spacers, epitaxially growing a raised source drain (RSD) on the substrate adjacent to outside walls of the sidewall spacers, and forming a silicide above the RSD and along the outside walls of the sidewall spacers. The method also includes depositing and polishing a contact metal above portions of the replacement gate stack and the RSD, the contact metal contacting the silicide along the outside walls of the sidewall spacers adjacent to the portions of the replacement gate stack. |
| US09577094B2 |
Low cost demos transistor with improved CHC immunity
An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate. |
| US09577091B2 |
Vertical transistor and manufacturing method thereof
A vertical transistor and a manufacturing method thereof are provided herein. The manufacturing method includes forming a first patterned conductive layer on a substrate; forming a patterned metal oxide layer on the first patterned conductive layer, in which the patterned metal oxide layer includes a first patterned insulator layer, a second patterned insulator layer, and a second patterned conductive layer; forming a semiconductor layer; and forming a third patterned conductive layer. The first patterned insulator layer, the second patterned insulator layer, and the second patterned conductive layer are made by using a single metal oxide material. The oxygen concentration of the second patterned conductive layer is different from the oxygen concentrations of the first patterned insulator layer and the second patterned insulator layer. |
| US09577089B2 |
Structures and methods of fabricating dual gate devices
First polysilicon (poly-1) is deposited into deep trenches that have been formed in a substrate. A first polysilicon polishing process is performed to planarize the exposed surfaces of the poly-1 so that the surfaces are flush with adjacent surfaces. Then, shallow trenches are formed in the substrate between the deep trenches, and second polysilicon (poly-2) is deposited into the shallow trenches. A second polysilicon polishing process is performed to planarize the exposed surface of the poly-2 so that the surface is flush with adjacent surfaces. Metal contacts to the poly-1 and the poly-2 are then formed. |
| US09577085B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device may include interlayer insulating layers stacked in a first direction and separated from each other, word lines formed between the interlayer insulating layers, and sacrificial insulating layers formed between the interlayer insulating layers so that the sacrificial insulating layers are arranged at layers where the word lines are formed. The semiconductor device may also include cell contact plugs each including a first pillar portion passing through at least one of the interlayer insulating layers and the sacrificial insulating layers in the first direction, and a first protruding portion protruding from a sidewall of the first pillar portion and contacting a sidewall of one of the word lines, wherein the cell contact plugs have different depths. |
| US09577083B1 |
Embedded hydrogen inhibitors for semiconductor field effect transistors
A field effect transistor (FET) device including a substrate and a plurality of semiconductor layers provided on the substrate, where a top semiconductor layer is a heavily doped cap layer and another one of the semiconductor layers directly below the cap layer is a Schottky barrier layer, and where a gate recess is formed through the cap layer and into the Schottky barrier layer. The FET device also includes a gate terminal having a titanium layer, an inhibitor layer provided on the titanium layer and a gold layer provided on the inhibitor layer, where the gate terminal is formed in the recess so that the titanium layer is in contact with the Schottky barrier layer, and where the inhibitor layer is effective for preventing hydrogen gas from being dissociated into hydrogen atoms so as to reduce or prevent hydrogen poisoning of the FET device. |
| US09577073B2 |
Method of forming a silicon-carbide device with a shielded gate
A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed. |
| US09577072B2 |
Termination design for high voltage device
The present disclosure describes a termination structure for a high voltage semiconductor transistor device. The termination structure is composed of at least two termination zones and an electrical disconnection between the body layer and the edge of the device. A first zone is configured to spread the electric field within the device. A second zone is configured to smoothly bring the electric field back up to the top surface of the device. The electrical disconnection prevents the device from short circuiting the edge of the device. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. |
| US09577070B2 |
Gate spacers and methods of forming
Methods and structures for forming devices, such as transistors, are discussed. A method embodiment includes forming a gate spacer along a sidewall of a gate stack on a substrate; passivating at least a portion of an exterior surface of the gate spacer; and epitaxially growing a material in the substrate proximate the gate spacer while the at least the portion of the exterior surface of the gate spacer remains passivated. The passivating can include using at least one of a thermal treatment, a plasma treatment, or a thermal treatment. |
| US09577067B2 |
Metal gate and manufuacturing process thereof
Some embodiments of the present disclosure provide a semiconductor device including a semiconductive substrate, a metal gate including a metallic layer proximal to the semiconductive substrate. A dielectric layer surrounds the metal gate. The dielectric layer includes a first surface facing the semiconductive substrate and a second surface opposite to the first surface. A sidewall spacer surrounds the metallic layer with a greater longitudinal height. The sidewall spacer is disposed between the metallic layer and the dielectric layer. An etch stop layer over the metal gate comprises a surface substantially coplanar with the second surface of the dielectric layer. The etch stop layer has a higher resistance to etchant than the dielectric layer. A portion of the etch stop layer is over the sidewall spacer. |
| US09577065B2 |
Back-end transistors with highly doped low-temperature contacts
A back end of line device and method for fabricating a transistor device include a substrate having an insulating layer formed thereon and a channel layer formed on the insulating layer. A gate structure is formed on the channel layer. Dopants are implanted into an upper portion of the channel layer on opposite sides of the gate structure to form shallow source and drain regions using a low temperature implantation process. An epitaxial layer is selectively grown on the shallow source and drain regions to form raised regions above the channel layer and against the gate structure using a low temperature plasma enhanced chemical vapor deposition process, wherein low temperature is less than about 400 degrees Celsius. |
| US09577060B2 |
Piezoresistive resonator with multi-gate transistor
An embodiment includes a first nonplanar transistor including a first fin that includes first source and drain nodes, and a first channel between the first source and drain nodes; a second nonplanar transistor including a second fin that includes second source and drain nodes, and a second channel between the second source and drain nodes; a nonplanar gate on the first fin between the first source and drain nodes and on the second fin between the second source and drain nodes; and first insulation included between the gate and the first fin and second insulation between the gate and the second fin; wherein the gate mechanically resonates at a first frequency when at least one of the gate and the first fin is actuated with alternating current (AC) to produce periodic forces on the gate. Other embodiments are described herein. |
| US09577054B2 |
Semiconductor device with varied electrodes
A semiconductor device comprises an element region and a terminal region that surrounds the element region. The semiconductor device includes a first semiconductor region having a first conductivity type and a second semiconductor region having a second conductivity type and provided on the first semiconductor region. A third semiconductor region having the first conductivity type is provided on the second semiconductor region. A first electrode is electrically connected to the first semiconductor region. A second electrode is electrically connected to the third semiconductor region. A third and a fourth electrode are disposed in the element region. A distance from the first electrode to the third electrode is less than a distance from the first electrode to the fourth electrode. |
| US09577053B2 |
Zener diode having an adjustable breakdown voltage
The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region. |
| US09577041B2 |
Method for fabricating a transistor device with a tuned dopant profile
A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as boron. Different transistor devices with similar boron implants may be fabricated with different peak locations and heights for their respective dopant profiles by tailoring the carbon implant energy to effect tuned dopant profiles for the boron. |
| US09577040B2 |
FinFET conformal junction and high epi surface dopant concentration method and device
A method of forming a source/drain region with an abrupt, vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a gate electrode over and perpendicular to a semiconductor fin; forming first spacers on opposite sides of the gate electrode; forming second spacers on opposite sides of the fin; forming a cavity in the fin adjacent the first spacers, between the second spacers; partially epitaxially growing source/drain regions in each cavity; implanting a first dopant into the partially grown source/drain regions with an optional RTA thereafter; epitaxially growing a remainder of the source/drain regions in the cavities, in situ doped with a second dopant; and implanting a third dopant in the source/drain regions. |
| US09577039B2 |
Transistor structure with reduced parasitic side wall characteristics
A MOS transistor structure for matched operation in weak-inversion or sub-threshold range (e.g. input-pair of operational amplifier, comparator, and/or current-mirror) is disclosed. The transistor structure may include a well region of any impurity type in a substrate (SOI is included). The well-region can even be represented by the substrate itself. At least one transistor is located in the well region, whereby the active channel-region of the transistor is independent from lateral isolation interfaces between GOX (gate oxide) and FOX (field oxide; including STI-shallow trench isolation). |
| US09577038B1 |
Structure and method to minimize junction capacitance in nano sheets
A method of making a semiconductor device includes forming a nanosheet stack including a first layer and a second layer; patterning a gate stack on the nanosheet stack; forming a first spacer along a sidewall of the gate stack; removing an endwall portion of the nanosheet stack that extends beyond the first spacer such that a portion of the second layer is exposed from a sidewall of the first spacer; depositing a second spacer along a sidewall of the first spacer; recessing the substrate beneath the second spacer to form an isolation region; depositing an oxide on the gate stack and within the isolation region and partially recessing the oxide; removing a portion of the second spacer such that the portion of the second layer is exposed; and growing an epitaxial layer on the portion of the second layer that is exposed to form a source/drain over the isolation region. |
| US09577036B1 |
FinFET isolation structure and method for fabricating the same
A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap. |
| US09577035B2 |
Isolated through silicon vias in RF technologies
Disclosed are a structure for providing electrical isolation in a semiconductor substrate and an associated method for the structure's fabrication. The structure includes a deep trench isolation loop having a first depth disposed in the semiconductor substrate. A dielectric material is disposed in the deep trench isolation loop and one or more through silicon vias (TSVs), having a second depth, are disposed in the semiconductor substrate and within a perimeter of the deep trench isolation loop. A portion of the semiconductor substrate surrounding the deep trench isolation loop may be doped. A metallic filler may be disposed within the one or more TSVs and the metallic filler may be in direct electrical contact with the semiconductor substrate. |
| US09577032B2 |
Semiconductor device
A groove for air ventilation is formed in a rib with a substantially rectangular ring shape which is provided so as to surround a concave portion provided in a rear surface of a semiconductor chip. The groove is provided in each side or at each corner of the rib so as to traverse the rib from the inner circumference to the outer circumference of the rib. The depth of the groove is equal to or less than the depth of the concave portion provided in the rear surface of the chip. In this way, it is possible to reliably solder a semiconductor device, in which the concave portion is provided in the rear surface of the semiconductor chip and the rib is provided in the outer circumference of the concave portion, to a base substrate, without generating a void in a drain electrode provided in the concave portion. |
| US09577031B2 |
Semiconductor structure and method for forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate; and a plurality of convex structures formed on a surface of the substrate and arranged in a longitudinal direction of the substrate, each convex structure having a top surface, a bottom surface located on the surface of the substrate, a first end surface and a second end surface parallel to each other, and a front side surface and a rear side surface parallel to each other, in which the rear side surface of one of two adjacent convex structures and the front side surface of the other are located on a same plane to allow the plurality of convex structures to form a zigzag structure. |
| US09577029B2 |
Metal-insulator-metal capacitor structure and method for manufacturing the same
A metal-insulator-metal (MIM) capacitor structure and a method for manufacturing the same. The method includes a step hereinafter. A 5-layered dual-dielectric structure is provided on a substrate. The 5-layered dual-dielectric structure includes a bottom metal layer, a first dielectric layer, an intermediate metal layer, a second dielectric layer and a top metal layer in order. The first dielectric layer and the second dielectric layer have different thicknesses. |
| US09577027B2 |
Semiconductor device and process of making the same
A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is disposed on a surface of the substrate. The first patterned metal layer is disposed on the seed layer and has a first thickness. The first patterned metal layer includes a first part and a second part. The dielectric layer is disposed on the first part of the first patterned metal layer. The second metal layer is disposed on the dielectric layer and has a second thickness, where the first thickness is greater than the second thickness. The first part of the first patterned metal layer, the dielectric layer and the second metal layer form a capacitor. The first part of the first patterned metal layer is a lower electrode of the capacitor, and the second part of the first patterned metal layer is an inductor. |
| US09577026B2 |
MIM capacitor and method of forming the same
According to an exemplary embodiment, a method of forming a MIM capacitor is provided. The method includes the following operations: providing a first metal layer; providing a dielectric layer over the first metal layer; providing a second metal layer over the dielectric layer; etching the second metal layer to define the metal-insulator-metal capacitor; and oxidizing a sidewall of the second metal layer. According to an exemplary embodiment, a MIM capacitor is provided. The MIM capacitor includes a first metal layer; a dielectric layer over the first metal layer; a second metal layer over the dielectric layer; and an oxidized portion in proximity to the second metal layer and made of oxidized second metal layer. |
| US09577025B2 |
Metal-insulator-metal (MIM) capacitor in redistribution layer (RDL) of an integrated device
Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor. |
| US09577023B2 |
Metal wires of a stacked inductor
A method including forming a first metal wire in a first dielectric layer, the first metal wire including a first vertical side opposite from a second vertical side; and forming a second metal wire in a second dielectric layer above the first dielectric layer, the second metal wire including a third vertical side opposite from a fourth vertical side, where the first vertical side is laterally offset from the third vertical side by a first predetermined distance, and the second vertical side is laterally offset from the fourth vertical side by a second predetermined distance, where the first metal wire and the second metal wire are in direct contact with one another. |
| US09577020B2 |
Organic light-emitting display device
An organic light-emitting display device includes a first substrate and a second substrate that face each other; an organic light-emitting device that is disposed between the first and second substrates and includes a pixel electrode separately formed in each pixel, a common electrode facing the pixel electrode, and an organic light-emitting layer disposed between the pixel electrode and the common electrode; and an electrode unit and at least one wiring unit that are disposed between the first substrate and the second substrate, the electrode unit including at least one thin-film transistor for transmitting a light-emitting signal to the pixel electrode and at least one capacitor, wherein an optical property modification layer obtained by modifying an optical property of at least one of the electrode unit and the wiring unit is formed on a surface of the at least one of the electrode unit and the wiring unit. |
| US09577018B2 |
Display unit and electronic apparatus
There are provided a display unit and an electronic apparatus that are capable of preventing color mixture in adjacent color pixels, and improving color reproducibility and chromaticity viewing angle. The display unit includes: a drive substrate having a plurality of pixels with a partition therebetween; and a first light shielding film provided on the partition. |
| US09577006B2 |
Solid-state imaging device and electronic apparatus
A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4×n pixels (where, n is a positive integer), respectively, in horizontal and vertical directions. |
| US09577004B2 |
Imaging apparatus, imaging system and manufacturing method of imaging apparatus
One embodiment according to the present disclosure is an imaging apparatus including pixels. The pixel includes a junction type field effect transistor (JFET) provided in a semiconductor substrate. The JFET includes a gate region and a channel region. An orthogonal projection of the gate region onto a plane parallel to a surface of the semiconductor substrate intersects an orthogonal projection of the channel region onto the plane. Each of a source-side portion of the orthogonal projection of the channel region and a drain-side portion of the orthogonal projection of the channel region protrudes out of the orthogonal projection of the gate region. |
| US09576999B2 |
Backside structure and methods for BSI image sensors
BSI image sensors and methods. In an embodiment, a substrate is provided having a sensor array and a periphery region and having a front side and a back side surface; a bottom anti-reflective coating (BARC) is formed over the back side to a first thickness, over the sensor array region and the periphery region; forming a first dielectric layer over the BARC; a metal shield is formed; selectively removing the metal shield from over the sensor array region; selectively removing the first dielectric layer from over the sensor array region, wherein a portion of the first thickness of the BARC is also removed and a remainder of the first thickness of the BARC remains during the process of selectively removing the first dielectric layer; forming a second dielectric layer over the remainder of the BARC and over the metal shield; and forming a passivation layer over the second dielectric layer. |
| US09576997B2 |
Imager module for a camera having an optically transparent, flexible coupling element and manufacturing method for such an imager module
An imager module for a camera includes: a lens holder; a lens system which is accommodated in the lens holder and has a lens mount and at least one lens accommodated in the lens mount; and an image sensor; a rear lens area being formed between the image sensor and the at least one lens of the lens system; and an optically transparent, flexible coupling element provided in the rear lens area. |
| US09576994B2 |
Imaging device and electronic device
An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes an eighth transistor. Variation in threshold voltage of an amplifier transistor (the fifth transistor) included in the first circuit can be compensated. |
| US09576989B2 |
Array substrate and the method for making the same, and display device
An array substrate and the method for making the same, and a display device are provided. The method includes step 1, forming a pattern comprising a gate electrode and a gate line on a substrate, and providing photoresist at a position reserved for a first via hole above the gate line in a non-display area; step 2, forming a pattern of functional layers of a thin film transistor (TFT) and a data line on the substrate after the above step; step 3, forming a pattern comprising a first pixel electrode on the substrate after the above steps, and then forming a passivation layer; step 4, removing the photoresist provided above the position reserved for the first via hole and film layer thereabove from the substrate after the above steps, so as to form the first via hole. |
| US09576988B2 |
Supporting device, method for manufacturing thin film transistor array substrate and method for manufacturing liquid crystal display
A supporting device includes a main body and a ring-shaped glue layer. The main body includes a top surface and a bottom surface opposite to the top surface. The top surface defines a first groove. The first groove is substantially ring-shaped. The glue layer is arranged in the top surface and surrounds the first groove. A plurality of glass-frits is distributed in the glue layer. |
| US09576987B2 |
Display substrate and method of manufacturing the display substrate
A display substrate includes a substrate having a first region and a second region, a conductive pattern is provided in the first region of the substrate and includes a first conductive pattern and a second conductive pattern, the first conductive pattern has a gate electrode and a source electrode, the second conductive pattern has a source electrode and a drain electrode, an insulation layer pattern is positioned on the conductive pattern and exposes an outer sidewall of the conductive pattern, an organic layer is provided in the first region and the second region of the substrate and covers the insulation layer pattern, and a pixel electrode is provided on the organic layer and is electrically connected to the drain electrode through a contact hole in the organic layer. |
| US09576979B2 |
Preventing strained fin relaxation by sealing fin ends
A semiconductor structure includes a first strained fin portion and a second strained fin portion, a pair of inactive inner gate structures upon respective strained fin portions, and spacers upon outer sidewalls surfaces of the inactive inner gate structures, upon the inner sidewall surfaces of the inactive inner gate structures, and upon the first strained fin portion and the second strained fin portion end surfaces. The first strained fin portion and the second strained fin portion end surfaces are coplanar with respective inner sidewall surfaces of the inactive inner gate structures. The spacer formed upon the end surfaces limits relaxation of the first strained fin portion and the second strained fin portion and limits shorting between the first strained fin portion and the second strained fin portion. |
| US09576975B2 |
Monolithic three-dimensional NAND strings and methods of fabrication thereof
A vertically repeating stack of a unit layer stack is formed over a substrate. The unit layer stack includes a sacrificial material layer, a lower silicon oxide material layer, a first silicon oxide material layer, and an upper silicon oxide material layer. A memory opening can be formed through the vertically repeating stack, and a layer stack including a blocking dielectric layer, a memory material layer, a tunneling dielectric, and a semiconductor channel can be formed in the memory opening. The sacrificial material layers are replaced with electrically conductive layers. The first silicon oxide material layer can be removed to form backside recesses. Optionally, portions of the memory material layer can be removed to from discrete charge storage regions. The backside recesses can be filled with a low-k dielectric material and/or can include cavities within a dielectric material to provide reduced coupling between electrically conductive layers. |
| US09576974B2 |
Manufacturing method of semiconductor device
A method of manufacturing a semiconductor device includes forming on a lower structure, a first stack structure in which first material layers and second material layers are alternately stacked, forming, on the first stack structure, a second stack structure in which third material layers and fourth material layers are alternately stacked, forming preliminary holes penetrating the second stack structure, forming a fifth material layer covering the preliminary holes on the second stack structure to define a first air-gap inside the preliminary holes, and forming through holes connected to the preliminary holes by penetrating from the fifth material layer overlapping the preliminary holes to the first stack structure. |
| US09576972B2 |
Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method of a semiconductor device thereof are provided. The manufacturing method includes the following steps. Two stacked structures are formed a substrate. Each of the stacked structures includes a plurality of gate layers, a plurality of gate insulating layers and a top insulating layer. A charge trapping structure and a channel layer are formed. The charge trapping structure includes a plurality of first dielectric layers and a plurality of second dielectric layers. Part of each of first dielectric layers is etched and part of each of second dielectric layers is etched to expose part of the channel layer. A landing pad layer is formed on the first dielectric layers and the second dielectric layers to connect the channel layer. |
| US09576970B2 |
Three-dimensional semiconductor memory device
A semiconductor device includes a first source layer; at least one of a second source layer, the second source layer formed substantially in the first source layer; a plurality of conductive layers stacked substantially over the first source layer; channel layers that pass through the plurality of conductive layers and couple to the second source layer; and at least one of a third source layer, the third source layer formed substantially in the second source layer, wherein the third source layer passes through the second source layer and is coupled to the first source layer. |
| US09576968B2 |
Semiconductor memory device with a three-dimensional stacked memory cell structure
A semiconductor memory device comprises: a semiconductor substrate; a plurality of memory units provided on the semiconductor substrate and each including a plurality of memory cells that are stacked; and a plurality of bit lines formed above each of a plurality of the memory units aligned in a column direction, an alignment pitch in a row direction of the plurality of bit lines being less than an alignment pitch in the row direction of the memory units, and an end of each of the memory units aligned in the column direction being connected to one of the plurality of bit lines formed above the plurality of the memory units aligned in the column direction. |
| US09576967B1 |
Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings
Memory openings and support openings are formed through an alternating stack of insulating layers and spacer material layers over a semiconductor substrate. Deposition of a semiconductor material in the support openings during formation of epitaxial channel portions in the memory openings is prevented by Portions of the semiconductor substrate that underlie the support openings are converted into impurity-doped semiconductor material portions. During selective growth of epitaxial channel portions from the semiconductor substrate within the memory openings, growth of a semiconductor material in the support openings is suppressed due to the impurity species in the impurity-doped semiconductor material portions. Memory stack structures and support pillar structures are subsequently formed over the epitaxial channel portions and in the support openings, respectively. The support pillar structures are formed with an outermost dielectric layer to prevent a leakage path to electrically conductive layers to be subsequently formed. |
| US09576957B2 |
Self-aligned source/drain contacts
A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts. |
| US09576951B2 |
Devices formed from a non-polar plane of a crystalline material and method of making the same
Materials, methods, structures and device including the same can provide a semiconductor device such as an LED using an active region corresponding to a non-polar face or surface of III-V semiconductor crystalline material. In some embodiments, an active diode region contains more non-polar III-V material oriented to a non-polar plane than III-V material oriented to a polar plane. In other embodiments, a bottom region contains more non-polar m-plane or a-plane surface area GaN than polar c-plane surface area GaN facing an active region. |
| US09576950B1 |
Contacts to transition metal dichalcogenide and manufacturing methods thereof
A device includes a transition metal dichalcogenide layer having a first edge with a zigzag atomic configuration. A metallic material has a portion overlapping the transition metal dichalcogenide layer. The metallic material has a second edge contacting the first edge of the transition metal dichalcogenide layer. |
| US09576948B2 |
Semiconductor device
A semiconductor device includes a first and second transistor. Each of the first and the second transistors includes a well of a first conductivity type, a band-shaped region provided on the well, a drain region of a second conductivity type provided on the well, and a gate electrode. The band-shaped region, the drain region and the gate electrode extend in a first direction. The band-shaped region includes a back gate region of the first conductivity type and a source region of the second conductivity type. The back gate region and the source region are arranged alternately along the first direction in the band-shaped region. A ratio of a length of the source region to a length of the back gate region along the first direction of the first transistor is greater than the ratio of the second transistor. |
| US09576946B2 |
Semiconductor device and method of manufacturing same
A method of manufacturing a semiconductor device, comprising: providing a substrate; forming a first trough structure, which comprises at least a first sidewall, on the substrate; forming a first doping layer on the first sidewall; covering the first doping layer and a part of a surface of the substrate by a photoresist; forming a second trough structure, which comprises at least a second sidewall, on a part of the substrate which is not covered by the photoresist; removing the photoresist; forming an insulation layer on the substrate, the first trough structure, and the second trough structure; forming a conductive layer on the substrate, the first trough structure, and the second trough structure; and removing parts of the insulation layer and the conductive layer outside the first trough structure and the second trough structure to expose a surface of the first doping layer at the opening of the first trough structure. |
| US09576943B2 |
Apparatuses and methods of communicating differential serial signals including charge injection
Apparatuses and methods are disclosed, including an apparatus that includes a differential driver with charge injection pre-emphasis. One such apparatus includes a pre-emphasis circuit and an output stage circuit. The pre-emphasis circuit is configured to receive differential serial signals, and buffer the differential serial signals to provide buffered differential serial signals. The output stage circuit is configured to receive the buffered differential serial signals and drive the buffered differential serial signals onto differential communication paths. The pre-emphasis circuit is configured to selectively inject charge onto the differential communication paths to assist with a signal transition on at least one of the differential communication paths. Additional embodiments are disclosed. |
| US09576940B2 |
Light emitting device and LCD backlight using the same
The present invention provides a light emitting device which comprises blue and red light emitting diode (LED) chips and at least one phosphor for emitting green light by means of light emitted from the blue LED chip, and an LCD backlight including the light emitting device. According to the light emitting device of the present invention, uniform white light can be implemented and both high luminance and wider color reproduction range can also be obtained. Accordingly, an LCD backlight for uniform light distribution on an LCD as well as low power consumption and high durability can be manufactured using the light emitting device. |
| US09576935B2 |
Method for fabricating a semiconductor package and semiconductor package
A method for fabricating semiconductor packages includes providing a first substrate having an aperture, providing a first semiconductor chip, connecting the first semiconductor chip to the first substrate, filling the aperture with a first insulating material and encapsulating the semiconductor chip with a second insulating material to create a first encapsulation body. |
| US09576933B1 |
Fan-out wafer level packaging and manufacturing method thereof
A fan-out wafer-level-package (FOWLP) is provided. The FOWLP includes a redistribution layer (RDL) comprising a dielectric layer and a first metal layer; a passive device in the first metal layer; a first passivation layer covering a top surface of the RDL; a second passivation layer covering a bottom surface of the RDL; a chip mounted on the first passivation layer; a molding compound around the chip and on the first passivation layer; a via opening penetrating through the second passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a terminal of the chip; a contact opening in the second passivation layer; and a second metal layer in the via opening and the contact opening to electrically connect one electrode of the passive device with the terminal of the chip. |
| US09576932B2 |
Universal surface-mount semiconductor package
In the fabrication of semiconductor packages, a leadframe is formed by masking and etching a metal sheet from both sides, and a plastic block is formed over a plurality of dice attached to die pads in the leadframe. A laser beam is used to form individual plastic capsules for each package, and a second laser beam is used to singulate the packages by severing the metal conductors, tie bars and rails between the packages. A wide variety of different types of packages, from gull-wing footed packages to leadless packages, with either exposed or isolated die pads, may be fabricated merely by varying the patterns of the openings in the mask layers and the width of the plastic trenches created by the first laser beam. |
| US09576930B2 |
Thermally conductive structure for heat dissipation in semiconductor packages
A method of forming a semiconductor package includes providing a substrate, wherein the substrate has at least one chip attached on an upper surface of the substrate. An insulating barrier layer is deposited above the substrate, wherein the at least one chip is at least partially embedded within the insulating barrier layer. A thermally conductive layer is formed over the insulating barrier layer to at least partially encapsulate the at least one chip. |
| US09576929B1 |
Multi-strike process for bonding
A method includes performing a first strike process to strike a metal bump of a first package component against a metal pad of a second package component. A first one of the metal bump and the metal pad includes copper. A second one of the metal bump and the metal pad includes aluminum. The method further includes performing a second strike process to strike the metal bump against the metal pad. An annealing is performed to bond the metal bump on the metal pad. |
| US09576927B2 |
Bonding tool cooling apparatus and method for cooling bonding tool
A bonding tool cooling apparatus (10) provided in the vicinity of a bonding stage, including a frame (12); a cooling member (16) including a ground plate (14) having a ground surface (14a) on which a front edge surface of a bonding tool (61) is grounded, and a heat radiation fin (15) attached to an opposite surface of the ground plate (14) to the ground surface (14a), wherein the cooling member (16) is supported on the frame (12) by a support mechanism (200) so that the cooling member (16) is rotatable about two axes, i.e., an X axis extending along the ground surface (14a) and a Y axis extending along the ground surface (14a). Bonding tool cooling time can be thereby reduced. |
| US09576926B2 |
Pad structure design in fan-out package
A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors underlying and electrically coupled to the plurality of redistribution lines. The plurality of non-solder electrical connectors includes a corner electrical connector. The corner electrical connector is elongated. An electrical connector is farther away from the corner than the corner electrical connector, wherein the electrical connector is non-elongated. |
| US09576925B2 |
Semiconductor device having a cylindrical shaped conductive portion
A semiconductor device includes a first conductive portion, a second conductive portion, a first layer, and a second layer. The first conductive portion includes a first end portion and a first extending portion. The first extending portion extends in a first direction. The length of the first extending portion in a second direction is shorter than a length of at least a part of the first end portion in the second direction. The first layer includes multiple semiconductor chips, multiple passive chip components, and a resin. The first extending portion includes a first portion and a second portion. The first layer is provided around the first portion. The first layer expands along a first plane. The first plane intersects the first direction. The second layer includes a first multilayer wiring. The second layer expands along a second plane intersecting the first direction. |
| US09576922B2 |
Silver alloying post-chip join
A method of forming a stacked surface arrangement for semiconductor devices includes joining a first surface to a second surface with a solder bump, the solder bump including a substantially pure first metal; depositing nanoparticles of a second metal onto a surface of the solder bump; performing an annealing operation to form a film of the second metal on the surface of the solder bump; and performing a reflow or a second annealing operation to transform the solder bump from the substantially pure first metal to an alloy of the first metal and the second metal. |
| US09576920B2 |
Moisture barrier for semiconductor structures with stress relief
A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer. |
| US09576917B1 |
Embedded die in panel method and structure
Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first carrier, forming a first dielectric layer on the first redistribution layers and carrier, forming a mask pattern on the first dielectric layer exposing a portion of the first dielectric layer, forming a second dielectric layer on the exposed portion of the first dielectric layer, forming vias in the first and second dielectric layers, and forming second redistribution layers on the second dielectric layer. The mask pattern may be removed forming a die cavity defined by the second dielectric layer. A second layered structure coupled to the first layered structure may be formed comprising a second carrier, a third dielectric layer, third and fourth redistribution layers on opposite surfaces of the third dielectric layer, and a semiconductor die. |
| US09576915B2 |
IC-package interconnect for millimeter wave systems
Consistent with an example embodiment, a System on Chip (SoC) device operates in millimeter wave frequencies. The SoC device comprises, a silicon device having at least one differential pair pad, the at least one differential pair pad having a shunt inductor coupled thereon. A parasitic capacitance on at least one differential pair pads is tuned out by resonance of the shunt inductor. A package has a redistribution layer (RDL), with an array of contact areas to which the silicon device is mounted and then encapsulated. A connection corresponds to the at least one differential pair pad and the connection is located about an outer row or column of the array of contact areas. |
| US09576914B2 |
Inducing device variation for security applications
A Physical Unclonable Function (PUF) semiconductor device includes a semiconductor substrate, and regions, with implant regions and covered regions, in the semiconductor substrate. A hardmask covers a first covered region and a second covered. The first implant region having a first concentration of ions, and at least one second implant region having a second concentration that is less than the first concentration. First and second FETs are formed on the regions. The first and second FETs have a voltage threshold mismatch with respect to one another based on the first region and the at least one second region. |
| US09576911B2 |
Radio frequency module including segmented conductive ground plane
A radio frequency (RF) module comprises an electrical reference, or ground, plane to which one or more RF devices disposed on the module are electrically coupled, and may be disposed beneath the RF devices. The reference plane may be segmented as to form one or more segments of the reference plane that are at least partially electrically isolated from surrounding segments or devices. A module may have a plurality of devices disposed thereon, wherein separate, at least partially isolated reference planes, correspond to different devices of the module. The reference plane may be etched or cut to achieve such segmentation. |
| US09576906B2 |
Methods related to a sputtered titanium tungsten layer formed over a copper interconnect stack structure
Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor, with the stack including a barrier, a copper (Cu) layer disposed over the barrier, and a first titanium (Ti) layer disposed over the Cu layer. The metalized structure can further include a sputtered titanium tungsten (TiW) layer disposed over the first Ti layer. The barrier can include an assembly of titanium nitride (TiN) and Ti layers. The metalized structure can further include a second Ti layer disposed over the sputtered TiW layer. |
| US09576902B2 |
Semiconductor device including landing pad
A semiconductor device includes conductive lines spaced from a substrate, and an insulating spacer structure between the conductive lines and defining a contact hole. The insulating spacer structure is adjacent a side wall of at least one of the conductive lines. The device also includes an insulating pattern on the conductive lines and insulating spacer structure, and another insulating pattern defining a landing pad hole connected to the contact hole. A contact plug is formed in the contact hole and connects to the active area. A landing pad is formed in the landing pad hole and connects to the contact plug. The landing pad vertically overlaps one of the pair of conductive line structures. |
| US09576900B2 |
Switched power stage with integrated passive components
A scalable switching regulator architecture has an integrated inductor. In some embodiments an area and current drive capability of switches of the switching regulator is matched with an inductor built within an area above the switches. In some embodiments the combined switches and inductor are constructed as a unit cell and can be combined to form larger elements as required for higher current drive capability and multiphase operation. |
| US09576899B2 |
Electrical fuse with high off resistance
Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region. |
| US09576893B2 |
Semiconductor structure and semiconductor fabricating process for the same
A semiconductor structure and a fabricating process for the same are provided. The semiconductor fabricating process includes providing a first dielectric layer, a transitional layer formed on the first dielectric layer, and a conductive fill penetrated through the transitional layer and into the first dielectric layer; removing the transitional layer; and forming a second dielectric layer over the conductive fill and the first dielectric layer. |
| US09576891B1 |
Isolation device
An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality of metal layers disposed on the substrate. The plurality of metal layers have a topmost metal layer disposed furthest away from the substrate and a first interconnect metal layer formed nearest to the substrate. The first interconnect metal layer is disposed at a first distance away from the substrate, whereas the topmost metal layer is disposed at an isolation distance away from a first adjacent metal layer formed nearest to the topmost metal layer. A portion of the topmost metal layer forms a first plate. The first plate is configured to transmit the first signal from the first circuit to a second plate that is connected to the second circuit, but electrically isolated from the first plate. |
| US09576887B2 |
Semiconductor package including conductive carrier coupled power switches
In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain. |
| US09576884B2 |
Low profile leaded semiconductor package
In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the vertical side surface of the plastic body. The result is a package with a minimal footprint that is suitable for the technique known as “wave soldering” that is used in relatively low-cost printed circuit board assembly factories. Methods of fabricating the package are disclosed. |
| US09576881B2 |
Semiconductor device
According to one embodiment, a semiconductor device includes: a semiconductor substrate, the semiconductor substrate having first and second surfaces; conductive regions extending in a direction from the first surface side toward the second surface side of the semiconductor substrate, the conductive regions including first and second vias; a first semiconductor region surrounding a part of each of the conductive regions on the second surface side of the semiconductor substrate, a portion other than a front surface of the first semiconductor region being surrounded by the semiconductor substrate; a first electrode provided on the second surface side; second electrodes provided on the first surface side, one of the second electrodes being in contact with one of the conductive regions; and an insulating film provided between each of the conductive regions and the semiconductor substrate, and between each of the conductive regions and the first semiconductor region. |
| US09576879B2 |
Heat-dissipation structure and electronic device using the same
A heat-dissipation structure includes a first carbon nanotube layer and a thermal interface material layer. The first carbon nanotube layer and the thermal interface material layer are stacked on each other. The first carbon nanotube layer includes at least one first carbon nanotube paper, and the density of the first carbon nanotube paper ranges from about 0.3 g/cm3 to about 1.4 g/cm3. An electronic device applying the heat-dissipation structure is also disclosed. |
| US09576877B2 |
Electronic component, electronic device, method of manufacturing mounted member, and method of manufacturing electronic component
A frame member includes a first portion, a second portion, and a third portion located between the first portion and the second portion, and wherein the lengths of the first portion and the second portion in a circumferential direction are longer than the length of the third portion in the circumferential direction, and a Young's modulus of the third portion is lower than the Young's moduli of the first portion and the second portion. |
| US09576875B2 |
Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements
A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall. |
| US09576872B2 |
Semiconductor devices and methods for manufacturing semiconductor devices
A method includes arranging multiple semiconductor chips over a first carrier and depositing a first material layer over surfaces of the multiple semiconductor chips, wherein depositing the first material layer includes a vapor deposition, and wherein the first material layer includes at least one of an organic material and a polymer. |
| US09576870B2 |
Module package and production method
The invention relates to a module package which comprises a module substrate 1, a chip 2, 3 applied using the flip chip process, and an encapsulation layer 8, and to a method for producing same. The chip 2, 3 has component structures on the top side 13, 14 thereof. Said top said 13, 14 faces the module carrier 1, wherein a gap 4, 5 is formed between the top side 13, 14 of the chip and the module carrier 1. A filler is added to the encapsulation layer 8. The encapsulation layer 8 partly fills underneath the chip 2, 3, wherein at most the part of the chip 2, 3, on which no component structures are present, is underfilled, and at a minimum the material of the encapsulation layer 8 completely encloses the sides of the chip 2, 3. |
| US09576868B2 |
Semiconductor device and method for reduced bias temperature instability (BTI) in silicon carbide devices
A system includes a silicon carbide (SiC) semiconductor device and a hermetically sealed packaging enclosing the SiC semiconductor device. The hermetically sealed packaging is configured to maintain a particular atmosphere near the SiC semiconductor device. Further, the particular atmosphere limits a shift in a threshold voltage of the SiC semiconductor device to less than 1 V during operation. |
| US09576865B2 |
Film for semiconductor package, semiconductor package using film and display device including the same
A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film. |
| US09576863B2 |
Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness
Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips. |
| US09576860B2 |
Method and apparatus providing inline photoluminescence analysis of a photovoltaic device
A method and apparatus are disclosed which use a photoluminescent light intensity signature to characterize a processed photovoltaic substrate. |
| US09576859B2 |
Semiconductor device and method for fabricating the same
A method for fabricating a semiconductor device comprises: Firstly, a semiconductor fin comprising a first sub-fin and a second sub-fin protruding from a surface of a substrate is provided. An isolation structure having an opening extending therein is then provided in the semiconductor fin to electrically isolate the first sub-fin and the second sub-fin. Subsequently, a first dummy structure disposed on the first isolation structure and having at least one metal layer entirely overlapping on the first isolation structure along a long axis of the semiconductor fin is formed, wherein the metal layer laterally conformally extends downwards into the opening and extends upwards beyond the first isolation structure along the long axis of the semiconductor fin, so as to form a stepped structure overlapping on sidewalls and a bottom of the opening, a portion of the first sub-fin and a portion of the second sub-fin. |
| US09576857B1 |
Method and structure for SRB elastic relaxation
A method of forming SRB finFET fins first with a cut mask that is perpendicular to the subsequent fin direction and then with a cut mask that is parallel to the fin direction and the resulting device are provided. Embodiments include forming a SiGe SRB on a substrate; forming a Si layer over the SRB; forming an NFET channel and a SiGe PFET channel in the Si layer; forming cuts through the NFET and PFET channels, respectively, and the SRB down to the substrate, the cuts formed on opposite ends of the substrate and perpendicular to the NFET and PFET channels; forming fins in the SRB and the NFET and PFET channels, the fins formed perpendicular to the cuts; forming a cut between the NFET and PFET channels, the cut formed parallel to the fins; filling the cut with oxide; and recessing the oxide down to the SRB. |
| US09576851B2 |
Interconnect structure and methods of making same
A method of manufacturing a semiconductor interconnect structure may include forming a low-k dielectric layer over a substrate and forming an opening in the low-k dielectric layer, where the opening exposes a portion of the substrate. The method may also include filling the opening with a copper alloy and forming a copper-containing layer over the copper alloy and the low-k dielectric layer. An etch rate of the copper-containing layer may be greater than an etch rate of the copper alloy. The method may additionally include patterning the copper-containing layer to form interconnect features over the low-k dielectric layer and the copper alloy. |
| US09576846B2 |
Methods for manufacturing a data storage device
Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches. |
| US09576841B2 |
Semiconductor device and manufacturing method
A semiconductor device includes a first-conductivity-type semiconductor layer including an active region in which a transistor having impurity regions is formed and a marginal region surrounding the active region, a second-conductivity-type channel layer formed between the active region and the marginal region and forming a front surface of the semiconductor layer, at least one gate trench formed in the active region to extend from the front surface of the semiconductor layer through the channel layer, a gate insulation film formed on an inner surface of the gate trench, a gate electrode formed inside the gate insulation film in the gate trench, and at least one isolation trench arranged between the active region and the marginal region to surround the active region and extending from the front surface of the semiconductor layer through the channel layer, the isolation trench having a depth equal to that of the gate trench. |
| US09576838B2 |
Devices for methodologies related to wafer carriers
Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a wafer carrier can be configured as a plate to allow bonding of a wafer thereto to provide support for the wafer during some processing operations. Upon completion of such operations, the processed wafer can be separated from the support plate so as to allow further processing. Various devices and methodologies related to such wafer carriers for efficient handling of wafers are disclosed. |
| US09576821B2 |
Package structures including a capacitor and methods of forming the same
A package includes a die, an encapsulant, and a capacitor. The package has a package first side and a package second side. The die has a die first side corresponding to the package first side, and has a die second side corresponding to the package second side. The die first side is opposite the die second side. The encapsulant surrounds the die. The capacitor includes a first plate and a second plate in the encapsulant, and opposing surfaces of the first plate and the second plate extend in a direction from the package first side to the package second side. The external conductive connectors are attached to at least one of the package first side and the package second side. |
| US09576816B2 |
Method for roughness improvement and selectivity enhancement during arc layer etch using hydrogen
A method of patterning a silicon containing ARC (anti-reflective coating) layer underlying a patterned layer is described that includes establishing a flow of a process gas to a plasma processing system, selecting a process condition that increases an etch selectivity of the silicon containing ARC layer relative to the patterned layer, igniting plasma from the process gas using a plasma source in accordance with the process condition, and exposing the substrate to the plasma to extend the feature pattern of the patterned layer into the silicon containing ARC layer. The process gas includes a first gaseous molecular constituent composed of C, F and optionally H, a second gaseous molecular constituent composed of C, F, and optionally H, and a third gaseous molecular constituent containing atomic hydrogen, diatomic hydrogen, or a CxHy-containing gas, wherein x and y are real numbers greater than zero. |
| US09576812B2 |
Partial etch memorization via flash addition
Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives. |
| US09576794B2 |
Cyclical deposition of germanium
In some aspects, methods for forming a germanium thin film using a cyclical deposition process are provided. In some embodiments, the germanium thin film is formed on a substrate in a reaction chamber, and the process includes one or more deposition cycles of alternately and sequentially contacting the substrate with a vapor phase germanium precursor and a nitrogen reactant. In some embodiments, the process is repeated until a germanium thin film of desired thickness has been formed. |
| US09576792B2 |
Deposition of SiN
Methods and precursors for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. In some embodiments, deposited silicon nitride can be treated with a plasma treatment. The plasma treatment can be a nitrogen plasma treatment. In some embodiments the silicon precursors for depositing the silicon nitride comprise an iodine ligand. The silicon nitride films may have a relatively uniform etch rate for both vertical and the horizontal portions when deposited onto three-dimensional structures such as FinFETS or other types of multiple gate FETs. In some embodiments, various silicon nitride films of the present disclosure have an etch rate of less than half the thermal oxide removal rate with diluted HF (0.5%). In some embodiments, a method for depositing silicon nitride films comprises a multi-step plasma treatment. |
| US09576791B2 |
Semiconductor devices including semiconductor structures and methods of fabricating the same
Semiconductor devices and methods for fabricating semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure. An electrically semi-insulating passivation layer overlies the semiconductor structure. An electrically substantially fully insulating passivation layer overlies the electrically semi-insulating passivation layer. |
| US09576790B2 |
Deposition of boron and carbon containing materials
Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B, C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. One or more of the boron and carbon containing films can have a thickness of less than about 30 angstroms. Methods of doping a semiconductor substrate are provided. Doping a semiconductor substrate can include depositing a boron and carbon film over the semiconductor substrate by exposing the substrate to a vapor phase boron precursor at a process temperature of about 300° C. to about 450° C., where the boron precursor includes boron, carbon and hydrogen, and annealing the boron and carbon film at a temperature of about 800° C. to about 1200° C. |
| US09576788B2 |
Cleaning high aspect ratio vias
A method of removing an amorphous silicon/silicon oxide film stack from vias is described. The method may involve a remote plasma comprising fluorine and a local plasma comprising fluorine and a nitrogen-and-hydrogen-containing precursor unexcited in the remote plasma to remove the silicon oxide. The method may then involve a local plasma of inert species to potentially remove any thin carbon layer (leftover from the photoresist) and to treat the amorphous silicon layer in preparation for removal. The method may then involve removal of the treated amorphous silicon layer with several options possibly within the same substrate processing region. The bottom of the vias may then possess exposed single crystal silicon which is conducive to epitaxial single crystal silicon film growth. The methods presented herein may be particularly well suited for 3d NAND (e.g. VNAND) device formation. |
| US09576786B2 |
Intelligent radio-controlled plasma light
The user of plasma light technology and remote lighting control techniques may enable a single master controller to control a large number of lighting fixtures. Multiple lighting fixtures may be equipped with control applications. Each control application may control the radio frequency driver of a lighting fixture that drives the plasma bulbs of the lighting fixture to produce light output for growing plants. The master controlled may execute on one or more computing devices. The master controller may send input instructions to the control applications of the lighting fixtures via a network. The instructions may be implemented by the control applications to command the radio frequency drivers to regulate a spectral distribution and/or intensity of the light output of the lighting fixtures. |
| US09576785B2 |
Electrodeless single CW laser driven xenon lamp
An ignition facilitated electrodeless sealed high intensity illumination device is disclosed. The device is configured to receive a laser beam from a continuous wave (CW) laser light source. A sealed chamber is configured to contain an ionizable medium. The chamber has an ingress window disposed within a wall of a chamber interior surface configured to admit the laser beam into the chamber, a plasma sustaining region, and a high intensity light egress window configured to emit high intensity light from the chamber. A path of the CW laser beam from the laser light source through the ingress window to a focal region within the chamber is direct. The ingress window is configured to focus the laser beam to within a predetermined volume, and the plasma is configured to be ignited by the CW laser beam, optionally by heating of a non-electrode ignition agent located entirely within the chamber. |
| US09576783B2 |
Time-of-flight mass spectrometers with cassini reflector
The invention relates to embodiments of high-resolution time-of-flight (TOF) mass spectrometers with special reflectors. The invention provides reflectors with ideal energy and solid angle focusing, based on Cassini ion traps, and proposes that a section of the flight path of the TOF mass spectrometers takes the form of a Cassini reflector. It is particularly favorable to make the ions fly through this Cassini reflector in a TOF mass spectrometer at relatively low energies, with kinetic energies of below one or two kiloelectronvolts. This results in a long, mass-dispersive passage time in addition to the time of flight of the other flight paths, without increasing the energy spread, angular spread or temporal distribution width of ions of the same mass. It is also possible to place several Cassini reflectors in series in order to extend the mass-dispersive time of flight. Several TOF mass spectrometers for axial as well as orthogonal ion injection with Cassini reflectors are presented. |
| US09576780B2 |
Mass spectrometer with timing determination based on a signal intensity in a chromatogram
A mass spectrometer including chromatogram creation means for creating a chromatogram showing changes over time in an ion intensity within a predetermined mass range based on the MS analysis results, and timing determination means for determining a timing to perform MS/MS analysis based on the chromatogram. The timing determination means determines, as a timing to perform MS/MS analysis, a point in time at which a signal intensity in the chromatogram reaches a predetermined upper limit after exceeding a predetermined lower limit or a point in time at which a signal intensity in the chromatogram reaches a top of a peak without reaching the upper limit after exceeding the lower limit. It is thus possible to collect precursor ions at a timing at which the signal intensity of a peak originating from sample components is highest between the upper limit and lower limit, thereby obtaining a high quality MS/MS spectrum. |
| US09576778B2 |
Data processing for multiplexed spectrometry
Multiplexed spectrometry, such as multiplexed ion mobility spectrometry (IMS), time-of-flight mass spectrometry (TOFMS), or hybrid IM-TOFMS, is carried out on a sample, and the resulting measurement data are deconvoluted. Noise may be removed from the measurement data prior to deconvolution. Alternatively or additionally, noise may be removed from the deconvoluted data. |
| US09576777B2 |
Multi-dimensional survey scans for improved data dependent acquisitions
A method of analyzing ions is disclosed comprising performing an initial multi-dimensional survey scan comprising separating parent ions according to a first physico-chemical property (e.g. ion mobility) and then separating the parent ions according to a second physico-chemical property (e.g. mass to charge ratio). A plurality of parent ions of interest are then determined from the initial multi-dimensional survey scan. Once parent ions of interest have been determined, the plurality of parent ions of interest are sequentially selected based upon the first and second physico-chemical properties during a single cycle of separation. The parent ions of interest may then be fragmented and corresponding fragment ions may then be mass analyzed. |
| US09576775B2 |
Plasma generating device
The invention relates to a plasma generation device comprising a plurality of plasma modules for generating a plasma. Each plasma module has a module housing with at least one gas inlet for supplying a process gas. Furthermore, a discharge device for generating the plasma from the process gas and a plasma outlet are provided. The plasma generation device has at least two plasma modules for generating a plasma. Each plasma module has at least one gas outlet for some of the process gas, wherein the at least one gas outlet of at least one plasma module issues into a respective gas inlet of another plasma module. |
| US09576772B1 |
CAD-assisted TEM prep recipe creation
An improved process workflow and apparatus for S/TEM sample preparation and analysis is provided. Preferred embodiments provide improved methods for an automated recipe TEM sample creation, especially for small geometry TEM lamellae, employing CAD data to automatically align various stages of sample preparation. The process automatically verifies and aligns the position of FIB-created fiducials by masking off portions of acquired images, and then comparing them to synthesized images from CAD data. SEM beam positions are verified by comparison to images synthesized from CAD data. FIB beam position is also verified by comparison to already-aligned SEM images, or by synthesizing an FIB image from CAD using techniques for simulating FIB images. The automatic alignment techniques herein allow creation of sample lamellas at specified locations without operator intervention. |
| US09576765B2 |
Electron beam emitter with increased electron transmission efficiency
An electron beam emitter comprises an electron emission source capable of emitting electrons; a vacuum chamber containing the electron emission source; and a transmission window that keeps airtightness of the vacuum chamber and is capable of transmitting the electrons from the electron emission source. The transmission window includes a foil that transmits the electrons and a grid that does not transmit the electrons. The electron emission source includes an emission portion that emits the electrons and a non-emission portion that does not emit the electrons. The emission portion has a lower work function than the non-emission portion. The non-emission portion is prepared so as to prevent the electrons from reaching the grid. |
| US09576763B2 |
Removable device for an electronic trip unit, power supply method of such a device and assembly comprising an electronic trip unit and one such removable device
The removable device (20) according to the invention is designed to be connected to an electronic trip unit (10). The trip unit (10) comprises an internal electrical power supply bus (55) and the device (20) is adapted to be supplied with electrical energy via the internal electrical power supply bus (55). The device (20) comprises a withdrawal member (68) for withdrawing electrical energy on the internal electrical power supply bus (55). The trip unit (10) includes a switched-mode power supply (54) capable of delivering a power supply signal (S1). The withdrawal member (68) comprises detection means for detecting each rising edge of the power supply signal (S1), and the electrical energy of the power supply signal (S1) is withdrawn as of the detection of a rising edge. |
| US09576761B2 |
Circuit breaker crossbar assembly
A circuit breaker crossbar assembly includes a crossbar having a first and second segment, the first and second segment each operatively coupled to a respective moveable contact arm assembly. Also included is a coupling segment disposed between the first and second segment, the crossbar and the coupling segment rotatable about an axis. Further included is at least one support assembly operatively coupled to the coupling segment. The support assembly includes a bushing coupled to the coupling segment and rotatable with the crossbar and the coupling segment. The support assembly also includes a support bracket configured for affixation to a stationary structure and disposed adjacent to the bushing, the bushing rotatable relative to the support bracket. The support assembly further includes a fixing bracket engaged with the support bracket and disposed adjacent to the bushing, the bushing rotatable relative to the fixing bracket. |
| US09576760B2 |
Contact device
An electromagnet device is configured to generate a magnetic attractive force between a stationary core and a movable core when electricity is applied to a coil, so that the movable core is moved in a direction for coming into contact with the stationary core, and a movable shaft is moved in a direction in which a first end face of the movable shaft separates from a movable terminal. After the movable contact comes in contact with the fixed contact, the movable core moves further in a direction for coming into contact with the stationary core. A yoke made of a magnetic body is disposed between the movable terminal and the first end of the movable shaft. |
| US09576757B2 |
Circuit interrupters with air trap regions in fluid reservoirs
Circuit interrupting devices, power distribution switchgear assemblies, and pole units for power distribution are provided. A circuit interrupting device includes a solid insulation housing, a disconnect, a window, and an insulating fluid. The solid insulation housing defines a first external opening and a first cavity extending into the solid insulation housing from the first external opening. The disconnect has a moving contact in selective engagement with a stationary contact in the first cavity. The window is secured to the solid insulation housing at the first external opening. The insulating fluid is disposed within the first cavity. The window, the solid insulation housing, or a combination thereof is configured to form a trap region that is in fluid communication with the first cavity and is configured to trap air bubbles in the insulating fluid. |
| US09576756B2 |
Switch control apparatus for electric plant
A switch control apparatus for electric plants includes a box-like body which is adapted to be anchored to a fixed o movable part of an electric plant and has a closing panel with at least one passage therethrough, at least one contact unit which is accommodated in the box-like body at the passage and is adapted to be electrically connected to at least one respective electric circuit of the plant for selective open/close control thereof, at least one actuator which is adapted to interact with the contact unit for the latter to ensure selective opening/closing of the respective circuits, an anchor system for anchoring the contact unit to the actuator. The anchor system includes a container member which is adapted to enclose and contain the contact unit and to be anchored to the closing panel in the box-like body for stably securing the contact unit on the actuator. |
| US09576754B2 |
Lockout devices for electrical control switches
Electrical switch lockout devices for selectively maintaining a position of an electrical switch on an electrical switch base are described. The electrical switch lockout devices include a base adapter configured to be fitted around the electrical switch base, a housing that is moveable between an engaged position and a disengaged position, and a locking mechanism. The housing includes walls, an opening on one side of the housing, a first lateral lip disposed on a first edge of the opening, and a second lateral lip disposed a second edge of the opening. The first lateral lip and the second lateral lip are configured to engage and disengage with the base adapter in the engaged and disengaged positions, respectively. |
| US09576753B2 |
Moveable contact arm releases latch plate engagement in a circuit breaker
A contact system of a circuit breaker includes a fixed contact. The contact system also includes a moveable contact arm assembly comprising at least one moveable contact arm having a moveable contact thereon, the moveable contact arm moveable to define a closed condition and a blow open condition. The contact system further includes a carrier assembly operatively coupled to the moveable contact arm. The contact system yet further includes a latch plate operatively coupled to the carrier assembly. The contact system also includes a trip shaft operatively coupled to the carrier assembly, the trip shaft having a non-circular region defining an engagement surface disposed in contact with the latch plate in the closed condition. The contact system further includes a biasing portion of the moveable contact arm configured to rotate the trip shaft out of engagement with the latch plate and into the blow open condition. |
| US09576751B1 |
Motorized vacuum isolation switch
Methods, systems, devices for a motorized isolation switch including a switch enclosure with a set of fixed insulated floating input line connectors and output load connectors movably fixed to the rear panel, a removable contactor bucket insertable into the isolation switch enclosure with mating movable insulated line terminals and load terminals and a set of insulated circuit interrupters, a motorized rack and pinion assembly connected to a base of the switch enclosure, coupled for moving a contactor pan connectable to the contactor bucket along a stationary rack gear along the base of the switch enclosure between and switch open position and a switch closed position, an insulating grounding block with ground connectors, the contactor bucket with corresponding movable ground terminals to mate with the insulated ground connectors in the switch open position, and ancillary controls for communicating with remotely located controls to electrically control the operation. |
| US09576750B2 |
Conductor guide member for a circuit breaker terminal assembly
A conductor guide member for a circuit breaker terminal assembly includes a body having at least one conductor guide surface configured and disposed to facilitate alignment between at least one terminal connection member of the terminal assembly and at least one conductor. The at least one conductor guide surface gradually slopes from a first end to a second end. The second end defines a recess. |
| US09576737B2 |
Parallel capacitor and high frequency semiconductor device
Certain embodiments provide a parallel capacitor including a substrate configured by a dielectric, upper electrodes, and a lower electrode. The upper electrodes are provided in an upper electrode region on a surface of the substrate. The lower electrode is provided on an entire surface of a lower electrode region including a region corresponding to the upper electrode region of an underside of the substrate, the lower electrode region being wider than the region. A single-operation capacity of each capacitor on both ends is smaller than the single-operation capacity of a capacitor in a center portion. The capacitors on the both ends are configured by the upper electrodes arranged on both ends of the substrate, the lower electrode, and the substrate. The capacitor in the center portion is configured by the upper electrode arranged in a center portion of the substrate, the lower electrode, and the substrate. |
| US09576735B2 |
Vertical capacitors with spaced conductive lines
A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines. |
| US09576726B2 |
Electronic equipment, module, and system
An electronic equipment is provided with an antenna including a coil, a load, a power feeding unit for feeding power received by the antenna to the load, a communication unit for communicating with the outside world via the antenna, a switching circuit installed between the antenna and the communication unit, and a switching control unit for controlling ON/OFF of the switching circuit according to power to be received by the antenna. |
| US09576724B2 |
Integrated sound shield for air core reactor
An air core power reactor (10) having a noise mitigating sound shield (40). In one embodiment the sound shield includes a plurality of sound absorbing panels (42p) configured for positioning about an outermost reactor layer (12′) so that the panels reduce radiation of acoustic energy when the reactor coil layers carry current. One or more flexible members (48) are attached along the first side of each sound absorbing panel for contact with the outermost reactor layer. Sound barrier material (44) is positioned along the second side of each panel. When the flexible members are attached to a panel and the panel is installed about the outermost first layer of the reactor, the flexible members are positioned against the outermost first layer and the flexible members provide a gap between the first side of the panel and the outermost first layer of the reactor. |
| US09576720B2 |
Transformer
A transformer (900) comprising a primary-side auxiliary winding (976, wherein in use the primary-side auxiliary winding (976) is configured such that a first electric potential distribution is induced in the primary-side auxiliary winding (976); and a secondary-side auxiliary winding (982) configured such that a second electric potential distribution is induced in the secondary-side auxiliary winding (982). The primary-side auxiliary winding (976) is physically located between (a) a main pair of windings; and (b) the second-side auxiliary winding (982). A first portion of the secondary-side auxiliary winding (982) is positioned adjacent to a shield-portion of the primary-side auxiliary winding (976) such that the first electric potential distribution matches the second electric potential distribution: (1) along the respective lengths of the first portion of the secondary-side auxiliary winding (982) and the shield-portion of the primary-side auxiliary winding (975); and (2) over a frequency range that is greater than a particular threshold frequency. |
| US09576717B2 |
Planar transformer
A multi-layered printed circuit board, PCB, includes first windings for a first side of a planar magnetic transformer and second windings for a second side of the planar magnetic transformer. The PCB further includes conductive layers configured as the first windings, conductive layers configured as the second windings, and layers of an isolation material. Each layer of the isolation material is arranged between two conductive layers to provide electrical isolation between the two conductive layers. A group of two or more adjacent conductive layers are all conductive layers of the first windings and are all arranged between two conductive layers of the second windings. The thickness of the isolation material between the group of adjacent conductive layers of the first windings is less than the thickness of the isolation material between a conductive layer of the second windings and a conductive layer of the first windings. |
| US09576716B2 |
Common mode choke and integrated connector module automation optimization
The subject disclosure relates improved common mode choke (CMC) and integrated connector module (ICM) designs for Ethernet applications. Some aspects provide an improved CMC component, including an upper chassis element having a first plurality of comb structures vertically protruding from an edge of the upper chassis element, and a lower chassis element comprising a second plurality of comb structures vertically protruding from an edge of the lower chassis element, the second plurality of comb structures configured to interlock with the first plurality of comb structures to form an enclosure when the upper chassis element is mechanically coupled with the lower chassis element. |
| US09576711B2 |
Coil component and board having the same
There are provided a coil component and a board having the same. The coil component includes: a magnetic body including a substrate having two cores, first and second coil parts disposed on one surface of the substrate and wound in the same direction, and third and fourth coil parts disposed on the other surface of the substrate to be spaced apart from each other; and first to fourth external electrodes disposed on outer surfaces of the magnetic body and connected to the first to fourth coil parts. |
| US09576702B2 |
Flexible armored cable
An armored cable features a core and an armor generally surrounding the core and having an inner diameter. The armor has a thickness of 0.001 to 0.100 times the inner diameter of the armor. In addition, the armor has corrugations with a pitch of 0.050 to 1.000 times the inner diameter of the armor. The armor has a corrugation depth of 0.010 to 0.400 times the inner diameter of the armor. |
| US09576701B2 |
High-voltage wire wiring structure in vehicle
A high-voltage wiring structure in a vehicle includes an extending member extending in an extending direction which is a longitudinal direction or a width direction of the vehicle, a plurality of bulkheads respectively provided at a plurality of portions of the extending member in the extending direction, a high-voltage wire extended from a battery for driving the vehicle, and a pipe, in which the high-voltage wire is inserted, and which is surrounded by the extending member. A plurality of portions of the pipe in a longitudinal direction of the pipe are respectively fixed to the bulkheads by welding. |
| US09576700B2 |
Binding tape member and wire harness
A binding tape member and a wire harness having a binding tape member configured to having the same function of conventional wire harnesses without the need for corrugated tube, pre-wrapping or post wrapping. The binding tape member has a tape member body that covers a group of electrical lines by being wrapped around the group of electrical lines. The tape body has a trapezoidal upper surface portion with an upper side and a lower side that correspond to the tape width end edges and a trapezoidal lower surface portion facing a direction opposite to the trapezoidal upper surface portion are alternatingly arranged in the tape length direction. Also, in a trapezoidal upper surface portion and a trapezoidal lower surface portion that are adjacent to each other, sides thereof in the tape length direction are connected to each other in an integrated manner by a rectangular side wall portion. |
| US09576698B2 |
Methods for forming polyimide-carbon nanotube composite film, and polyimide-carbon nanotube composite films formed thereof
A method for forming a polyimide-carbon nanotube composite film on a substrate is provided. The method comprises: suspending carbon nanotubes in a solution comprising a poly(amic acid) and a suitable solvent; casting the solution onto a substrate to form a layer on the substrate; and heating the layer to convert the poly(amic acid) into a polyimide to form the polyimide-carbon nanotube composite film. A polyimide-carbon nanotube composite film and an electronic device comprising the polyimide-carbon nanotube composite film are also provided. |
| US09576695B2 |
Graphene-based laminate including doped polymer layer
A graphene-based laminate including a doped polymer layer is disclosed. The graphene-based laminate may include a substrate; a graphene layer disposed on the substrate and including at least one layer; and a doped polymer layer disposed on at least one surface of the graphene layer and including an organic dopant. |
| US09576694B2 |
Applications for alliform carbon
This invention relates to novel applications for alliform carbon, useful in conductors and energy storage devices, including electrical double layer capacitor devices and articles incorporating such conductors and devices. Said alliform carbon particles are in the range of 2 to about 20 percent by weight, relative to the weight of the entire electrode. Said novel applications include supercapacitors and associated electrode devices, batteries, bandages and wound healing, and thin-film devices, including display devices. |
| US09576691B2 |
Techniques for on-demand production of medical isotopes such as Mo-99/Tc-99m and radioactive iodine isotopes including I-131
A system for radioisotope production uses fast-neutron-caused fission of depleted or naturally occurring uranium targets in an irradiation chamber. Fast fission can be enhanced by having neutrons encountering the target undergo scattering or reflection to increase each neutron's probability of causing fission (n, f) reactions in U-238. The U-238 can be deployed as one or more layers sandwiched between layers of neutron-reflecting material, or as rods surrounded by neutron-reflecting material. The gaseous fission products can be withdrawn from the irradiation chamber on a continuous basis, and the radioactive iodine isotopes (including I-131) extracted. |
| US09576689B2 |
Critical heat flux prediction device, critical heat flux prediction method and safety evaluation system
A critical heat flux prediction device, a critical heat flux prediction method, a safety evaluation system, and a core monitoring system using the safety evaluation system can predict critical heat flux in a core of a reactor with a high degree of accuracy by obtaining a correlation plot distribution representing a relation of critical heat flux on a thermal equilibrium quality based on experimental data, approximating a correlation plot distribution through a logistic function that is a model function in which critical heat flux is expressed by a function of a thermal equilibrium quality, and obtaining a critical heat flux correlation of critical heat flux and a thermal equilibrium quality. |
| US09576673B2 |
Sensing multiple reference levels in non-volatile storage elements
Disclosed herein are techniques for sensing multiple reference levels in non-volatile storage elements without changing the voltage on the selected word line. One aspect includes determining a first condition of a selected non-volatile storage element with respect to a first reference level based on whether a sensing transistor conducts in response to a sense voltage on a sense node. Then, a voltage on the source terminal of the sensing transistor is modified after determining the first condition with respect to the first reference level. A second condition of the selected non-volatile storage element is then determined with respect to a second reference level based on whether the sensing transistor conducts in response to the sense voltage on the sense node. This allows two different reference levels to be efficiently sensed. Dynamic power is saved due low capacitance of the sensing transistor relative to the sense node. |
| US09576670B1 |
Method and system for managing a writing cycle of a data in a EEPROM memory cell
An operation for writing at least one datum in at least one memory cell of the electrically erasable and programmable read-only memory type comprises at least one step of erasing or of programming of the cell by a corresponding erasing or programming pulse. The correct or incorrect conducting of the writing operation is checked by an analysis of the form of the erasing or programming pulse during the corresponding erasing or programming step. The result of this analysis is representative of the writing operation being conducted correctly or incorrectly. |
| US09576668B2 |
Semiconductor device and operating method thereof
The semiconductor device includes a memory block including programmed pages and non-programmed pages, a peripheral circuit configured to perform a read operation of the memory block, and a control circuit configured to control the peripheral circuit so that a read voltage is applied to a word line coupled to a selected page among the pages for the read operation, a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation, and a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation. |
| US09576658B2 |
Systems, and devices, and methods for programming a resistive memory cell
Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that comprises a quenching period having different portions. The memory cell may have more than two possible programmed states, where each programmed state of the memory cell includes a different fraction of amorphous material. A memory element may be melted and then quenched. The fraction of amorphous material, and thus the programmed state, may be controlled by selecting one of multiple quenching periods for the programming pulse. |
| US09576652B1 |
Resistive random access memory apparatus with forward and reverse reading modes
The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line selecting switch, a first pull down switch and a second pull down switch. The first bit line selecting switch is coupled between a first bit line and a sense amplifier. The first source line selecting switch is coupled between a source line and the sense amplifier. The first and second pull down switches are respectively coupled to the bit line and source line. When a reading operation is operated, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary. |
| US09576648B2 |
Method and apparatus for decoding memory
A thin-film memory may include a thin-film transistor-free address decoder in conjunction with thin-film memory elements to yield an all-thin-film memory. Such a thin-film memory excludes all single-crystal electronic devices and may be formed, for example, on a low-cost substrate, such as fiberglass, glass or ceramic. The memory may be configured for operation with an external memory controller. |
| US09576646B2 |
SRAM cell with dynamic split ground and split wordline
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters. |
| US09576645B2 |
Three dimensional dual-port bit cell and method of using same
A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch. |
| US09576641B2 |
Semiconductor device verifying signal supplied from outside
Disclosed herein is a semiconductor device that includes an access control circuit generating an internal command based on a verification result signal and an external command. The external command indicates at least one of a first command that enables the access control circuit to access a first circuit and a second command that enables the access control circuit not to access the first circuit or enables the access control circuit to maintain a current state of the first circuit. The access control circuit, when the verification result signal indicates a first logic level, generates the internal command based on the external command. The access control circuit, when the verification result signal indicates a second logic level, generates the internal command that corresponds to a second command even if the external command indicates a first command. |
| US09576640B2 |
Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system
A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information. |
| US09576636B1 |
Magnetic memory having ROM-like storage and method therefore
A magnetoresistive memory device that stores data in the reference portion of spin-torque memory cells provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, along with techniques for recovering data stored in the reference portions of memory cells. |
| US09576632B2 |
Magnetic storage device
A magnetic storage device of one embodiment includes a first and second magnetoresistive effect elements. The first magnetoresistive element includes a first magnetic layer having a first coercivity, a second magnetic layer having a second coercivity higher than the first coercivity, and a third magnetic layer having a third coercivity higher than the second coercivity. Magnetization orientations of the second and third magnetic layers are antiparallel. The second magnetoresistive effect element includes a fourth magnetic layer having a fourth coercivity, a fifth magnetic layer having a fifth coercivity higher than the fourth coercivity, and a sixth magnetic layer having a sixth coercivity higher than the fifth coercivity. Magnetization orientations of the fifth and sixth magnetic layers are parallel. |
| US09576629B2 |
Memory device and memory system including the same, and operation method of memory device
A memory device includes a memory cell array having a plurality of memory cells, a storage unit suitable for storing a fail address corresponding to a fail memory cell in the memory cell array, an available storage capacity determination unit suitable for generating available capacity information indicating an available storage capacity in the storage unit, and an output circuit suitable for outputting the available capacity information. |
| US09576628B1 |
Semiconductor device
A semiconductor device may include a driving control signal generation circuit configured to generate a driving control signal by determining whether a corresponding operation is a gapless read operation, according to a read strobe signal. The semiconductor device may also include a power driving circuit configured to drive a supply voltage to a power supply voltage in response to the driving control signal, and a read control signal generation circuit configured to generate a read control signal for controlling a read operation from the read strobe signal in response to the supply voltage. |
| US09576627B2 |
Semiconductor device, semiconductor system, and method for use in operating the same based on operation mode information
A semiconductor device includes a flag signal generating circuit, a reference voltage generating circuit, and a first buffer. The flag signal generating circuit generates a flag signal based on an internal command and a training control code which are extracted from an external signal. The reference voltage generating circuit receives a set code based on the flag signal, an input control code and an output control code, and generates a reference voltage whose level is set based on the set code. The first buffer buffers the external signal based on the reference voltage to generate an internal signal, and generates a calibration code from the internal signal based on the flag signal to output the calibration code. |
| US09576626B2 |
Nonvolatile memory device and storage device having the same
A nonvolatile memory device includes a data path; and a FIFO memory including a plurality of registers connected to the data path. The plurality of registers sequentially receive data from the data path in response to data path input clocks and sequentially output the received data to an input/output pad in response to data path output clocks. The data path output clocks are clocks that are generated by delaying the data path input clocks as long as a delay time. |
| US09576623B2 |
Sense amplifier and semiconductor memory device employing the same
The present disclosure herein relates to a sense amplifier and a semiconductor memory device employing the same. The sense amplifier includes an inverter including a pull-up transistor and a pull-down transistor, and a switching unit configured to change a connection relationship between the pull-up transistor and the pull-down transistor according to whether an input terminal of the inverter is precharged or a signal applied to the input terminal is sensed. |
| US09576622B2 |
Reading data from a memory cell
In response to a write operation to a memory cell that causes a data line of the memory cell to have a first voltage direction, causing the data line to have a second voltage direction opposite the first voltage direction. |
| US09576621B2 |
Read-current and word line delay path tracking for sense amplifier enable timing
A static random-access memory (SRAM) in an integrated circuit with circuitry for timing the enabling of sense amplifiers. The memory includes read/write SRAM cells, along with word-line tracking transistors arranged in one or more rows along a side of the read/write cells, and read-tracking transistors arranged in a column along a side of the read/write cells. A reference word line extends over the word-line tracking transistors, with its far end from the driver connected to pass transistors in the read-tracking transistors. The read-tracking transistors are preset to a known data state that, when accessed responsive to the reference word line, discharges a reference bit line, which in turn drives a sense amplifier enable signal. |
| US09576620B2 |
Semiconductor apparatus and operating method thereof
A semiconductor apparatus including a register input selection block configured to serially receive input data and output the input data in parallel as first and second data sets, or receive register selection output signals and output the register selection output signals as the first and second data sets, in response to a shift control signal and a capture control signal; a first data register configured to receive and store the first data set and output stored data as first register output signals; a second data register configured to receive and store the first and second data sets and output stored data as second register output signals; a register output selection block configured to output ones of the first and second register output signals as the register selection output signals; and a data output selection block configured to serially output one of the first and second data sets as output data. |
| US09576618B2 |
Memory devices, memory device operational methods, and memory device implementation methods
Memory devices, memory device operational methods, and memory device implementation methods are described. According to one arrangement, a memory device includes memory circuitry configured to store data in a plurality of different data states, temperature sensor circuitry configured to sense a temperature of the memory device and to generate an initial temperature output which is indicative of the temperature of the memory device, and conversion circuitry coupled with the temperature sensor circuitry and configured to convert the initial temperature output into a converted temperature output which is indicative of the temperature of the memory device at a selected one of a plurality of possible different temperature resolutions, and wherein the converted temperature output is utilized by the memory circuitry to implement at least one operation with respect to storage of the data. |
| US09576616B2 |
Non-volatile memory with overwrite capability and low write amplification
Providing for a non-volatile memory architecture having write and overwrite capabilities providing low write amplification to a storage system is described herein. By way of example, a memory array is disclosed comprising blocks and sub-blocks of two-terminal memory cells. The two-terminal memory cells can be directly overwritten in some embodiments, facilitating a write amplification value as low as one. Furthermore, the memory array can have an input-output multiplexer configuration, reducing sneak path currents of the memory architecture during memory operations. |
| US09576613B2 |
Semiconductor device
A semiconductor device may include a semiconductor substrate; a test circuit array region; a pad region on the semiconductor substrate and at at least a first side of the test circuit array region and outside of the test circuit array region, transistors arranged in the test circuit array region in a first direction and a second direction perpendicular to the first direction, source lines spaced apart from each other in the second direction, each of the source lines extending in the first direction and electrically connected to corresponding source electrodes of the transistors, and drain lines spaced apart from each other in the second direction, each of the drain lines extending in the first direction and electrically connected to drain electrodes of the transistors. |
| US09576606B1 |
Long latency interface protocol
A storage controller interface includes, on a disk controller side of the storage controller interface, a first transceiver circuit configured to transfer a first block of user data to a read channel during a write operation, and a gate transmit circuit configured to, subsequent to the first block of user data being transferred, assert a gate signal to flush the first block of user data from the read channel. The storage controller interface further includes, on a read channel side of the storage controller interface, a second transceiver circuit configured to receive the first block of user data, a gate receive circuit configured to receive the gate signal, and a write fault transceiver circuit configured to selectively assert a write fault signal if the gate transmit circuit does not assert the gate signal subsequent to the first block of user data being transferred to the read channel. |
| US09576603B2 |
Suspension board with circuit
A suspension board with circuit includes a first layer having electrically conductive properties, a second layer having insulation properties and formed at one side in a thickness direction of the first layer, a third layer having electrically conductive properties and formed at one side in the thickness direction of the second layer, and a fourth layer having insulation properties and formed at one side in the thickness direction of the third layer. The first layer includes an electronic component connecting terminal for being electrically connected to an electronic component. The second layer includes a first opening portion passing through in the thickness direction. The third layer includes a first conductive circuit having a magnetic head, and a second conductive circuit. The fourth layer and the second layer are formed with a second opening portion. |
| US09576594B1 |
Detection of open write heads and/or cables in tape drives
A computer-implemented method, according to one embodiment, includes: receiving a first output signal from a write driver, the write driver having an operating voltage applied thereto, receiving a second output signal from a comparator circuit, the comparator circuit having a reference voltage applied thereto, comparing a voltage of the first output signal with a voltage of the second output signal, and detecting a high resistance condition in response to determining that the voltage of the first output signal is less than the voltage of the second output signal. According to the present embodiment, the high resistance condition indicates open and/or partially open circuitry in the write driver. Moreover, the operating voltage is equal to the reference voltage. Other systems, methods, and computer program products are described in additional embodiments. |
| US09576592B2 |
Communication system and terminal device
A communication system according to the present invention includes a plurality of terminal devices that are able to communicate mutually. Each of the terminal devices includes a voice input conversion device, a voice transmitting device, a voice receiving device, and a voice reproducing device. When there is a plurality of voice signals which has not been completed reproduction, the voice reproducing device reproduces after arranging the voice signals so that respective voices corresponding to the respective voice signals do not overlap. |
| US09576589B2 |
Harmonic feature processing for reducing noise
Devices, systems and methods are disclosed for reducing noise in input data by performing a hysteresis operation followed by a lateral excitation smoothing operation. For example, an audio signal may be represented as a sequence of feature vectors. A row of the sequence of feature vectors may, for example, be associated with the same harmonic of the audio signal at different points in time. To determine portions of the row that correspond to the harmonic being present, the system may compare an amplitude to a low threshold and a high threshold and select a series of data points that are above the low threshold and include at least one data point above the high threshold. The system may iteratively perform a spreading technique, spreading a center value of a center data point in a kernel to neighboring data points in the kernel, to further reduce noise. |
| US09576587B2 |
Example-based cross-modal denoising
A method for cross-modal signal denoising, the method comprising using at least one hardware processor for: providing a first multi-modal signal comprising at least two relatively clear modalities; correlating features exhibited simultaneously in the at least two relatively clear modalities of the first multi-modal signal; providing a second multi-modal signal comprising at least one relatively noisy modality and at least one relatively clear modality; and denoising the at least one relatively noisy modality of the second multi-modal signal by associating between (a) features exhibited in the at least one relatively noisy modality of the second multi-modal signal and (b) the features of the first multi-modal signal. |
| US09576586B2 |
Audio coding device, audio coding method, and audio codec device
An audio coding device includes a memory; and a processor configured to execute a plurality of instructions stored in the memory, the instructions comprising: selecting a main lobe among a plurality of lobes detected from a frequency signal configuring an audio signal on a basis of bandwidth and power of the lobes; and coding the audio signal in such a manner that a first amount of bits per a unit frequency domain allocated to coding of the frequency signal of the main lobe is larger than a second amount of bits per the unit frequency domain allocated to the coding of the frequency signal of a side lobe as a lobe other than the main lobe. |
| US09576585B2 |
Method and apparatus for normalized audio playback of media with and without embedded loudness metadata of new media devices
A decoder device for decoding a bitstream so as to produce therefrom an audio output signal, the bitstream having audio data and optionally loudness metadata containing a reference loudness value, wherein a gain control device has a reference loudness decoder configured to create a loudness value, wherein the loudness value is the reference loudness value in case that the reference loudness value is present in the bitstream; wherein the gain control device has a gain calculator configured to calculate a gain value based on the loudness value and based on a volume control value, which is provided by an external user interface allowing a user to control the volume control value, and a loudness processor configured to control the loudness of the audio output signal based on the gain value. |
| US09576581B2 |
Metatagging of captions
A method for the real-time metatagging and captioning of an event. The method for the real-time metatagging and captioning of an event may include embedding metatag information in a caption file provided by a captioner. The embedded metatag information may allow a user to access additional information via the text of the captioned event. The metatag information may be embedded using a captioning device that creates both the text code and embeds the metatag code. |
| US09576579B1 |
Method and apparatus of providing semi-automated classifier adaptation for natural language processing
Example embodiments of the present invention may include a method that provides transcribing spoken utterances occurring during a call and assigning each of the spoken utterances with a corresponding set of first classifications. The method may also include determining a confidence rating associated with each of the spoken utterances and the assigned set of first classifications, and performing at least one of reclassifying the spoken utterances with new classifications based on at least one additional classification operation, and adding the assigned first classifications and the corresponding plurality of spoken utterances to a training data set. |
| US09576574B2 |
Context-sensitive handling of interruptions by intelligent digital assistant
Methods and systems related to intelligent interruption handling by digital assistants are disclosed. In some embodiments, a first information provision process is initiated in response to a first speech input. The first information provision process comprises preparing a first response and a second response to the first speech input. After or concurrent with the provision of the first response to the user, but before provision of the second response to the user, an event operable to initiate a second information provision process is detected. The second information provision process is initiated in response to detecting the event. The second information provision process comprises preparing a third response to the event. A relative urgency between the second response and the third response is determined. One of the second response and the third response is provided to the user in an order based on the determined relative urgency. |
| US09576572B2 |
Methods and nodes for enabling and producing input to an application
Methods and nodes for enabling and producing input generated by speech of a user, to an application. When the application has been activated (2:1), an application node (200) detects (2:2) a current context of the user and selects (2:3), from a set of predefined contexts (204a), a predefined context that matches the detected current context. The application node (200) then provides (2:4) keywords associated with the selected predefined context to a speech recognition node (202). When receiving (2:5) speech from the user, the speech recognition node (202) is able to recognize (2:6) any of the keyword in the speech. The recognized keyword is then used (2:7) as input to the application. |
| US09576567B2 |
Ergonomic tubular anechoic chambers for use with a communication device and related methods
Disclosed, in general, are devices that provide a substantially sound-tight chamber over a sound source while absorbing fields of sounds from the sound source. In general, the devices feature: an anechoic chamber that is configured to receive a sound source in a substantially sound-tight manner; and an anechoic channel that is in fluid communication with the ambient atmosphere. The anechoic chamber is adapted to capture air containing sound energy generated by the sound source, and distribute the air about an internal surface area on the inside of the chamber, wherein the internal surface area is sufficiently large to dampen or otherwise absorb the sound energy. Preferably, the air is directed from the anechoic chamber through an anechoic channel extending therefrom to the ambient to further dampen or absorb the sound energy. In one configuration, the outer wall of the apparatus is configured to reflect ambient sounds. |
| US09576563B2 |
Tank drum tuning structure
A percussion instrument, specifically a tank drum having tongues that form playing parts and including a ground clearance in its body, and a tuning structure which by changing the center of gravity of the tank drum, enables its tuning. A magnet is placed under the tongues. A channel is provided on the tongues enabling the magnet to be moved back and forth with the help of a key. |
| US09576561B2 |
Pick for stringed musical instruments
A pick for use with stringed musical instruments is disclosed. In some embodiments the pick is characterized by a roughened texture on the front and back substantially planar surfaces of the narrowed bottom portion of a substantially teardrop shaped body for the purpose of altering the tonal properties produced as it moves against strings that are strummed or picked. In further embodiments the roughened textured picking portion is combined with a separate second picking portion that is substantially smooth and useable to produce a conventional sound. |
| US09576558B2 |
Capacitive sensing during non-display update times
Embodiments of the invention generally provide an input device with display screens that periodically update (refresh) the screen by selectively driving common electrodes corresponding to pixels in a display line. In general, the input devices drive each electrode until each display line (and each pixel) of a display frame is updated. In addition to updating the display, the input device may perform capacitive sensing using the display screen as a proximity sensing area. To do this, the input device may interleave periods of capacitive sensing between periods of updating the display based on a display frame. For example, the input device may update the first half of display lines of the display screen, pause display updating, perform capacitive sensing, and finish updating the rest of the display lines. Further still, the input device may use common electrodes for both updating the display and performing capacitive sensing. |
| US09576557B2 |
Distributed blanking for touch optimization
Embodiments of the invention generally provide an input device with display screens that periodically update (refresh) the screen by selectively driving common electrodes corresponding to pixels in a display line. In general, the input devices drive each electrode until each display line (and each pixel) of a display frame is updated. In addition to updating the display, the input device may perform capacitive sensing using the display screen as a proximity sensing area. To do this, the input device may interleave periods of capacitive sensing between periods of updating the display based on a display frame. For example, the input device may update the first half of display lines of the display screen, pause display updating, perform capacitive sensing, and finish updating the rest of the display lines. Further still, the input device may use common electrodes for both updating the display and performing capacitive sensing. |
| US09576554B2 |
Determining a dominant color of an image based on pixel components
A digital magazine server determines a dominant color present in an image using a clustering algorithm. Color components of each pixel in the image are identified used to generate vectors associated with each pixel. Based on the vectors associated with the pixels, clusters including one or more pixels are generated using a clustering algorithm (e.g., k-means). The digital magazine server generates a characteristic vector for each cluster based on the vectors included in the cluster and selects a set of clusters based on their characteristic vectors. A centroid identifying the dominant color of the image is determined from the characteristic vectors of clusters in the set. |
| US09576551B2 |
Method and apparatus for gesture interaction with a photo-active painted surface
A method and apparatus for gesture interaction with an image displayed on a painted wall is described. The method may include capturing image data of the image displayed on the painted wall and a user motion performed relative to the image. The method may also include analyzing the captured image data to determine a sequence of one or more physical movements of the user relative to the image displayed on the painted wall. The method may also include determining, based on the analysis, that the user motion is indicative of a gesture associated with the image displayed on the painted wall, and controlling a connected system in response to the gesture. |
| US09576543B2 |
Shift register, gate driving unit and display device performing scanning sequence control
Provided are a shift register, a gate driving unit and a display device. By disposing a scanning sequence control circuit configured to control output sequence of a first gate signal and a second gate signal according to the received first and second scanning sequence control signals, a first control circuit and a second control circuit in the shift register unit, it may settle a Vertical mura problem in the prior art and may improve an image quality of the display device. |
| US09576542B1 |
Using display components for light sensing
This disclosure relates to, among other things, devices, systems, methods, computer-readable media, techniques, and methodologies that utilize and/or incorporate display components capable of being configured to detect light. |
| US09576541B2 |
Vision inspection apparatus and method of compensating gamma defect and mura defect thereof
A vision inspection apparatus includes a first luminance profile generator configured to generate a plurality of first luminance profiles corresponding to the plurality of reference grayscales, a gamma corrector configured to calculate a gamma correction value of the display apparatus using the plurality of first luminance profiles corresponding to the plurality of reference grayscales, and a second luminance profile generator configured to apply the gamma correction value to each of the plurality of first luminance profiles and to generate a plurality of second luminance profiles corresponding to the plurality of reference grayscales. |
| US09576539B2 |
Light source apparatus and method for controlling same
A light source apparatus includes a light source, a detection unit configured to detect light emitted by the light source, a determination unit configured to determine a target brightness, and a control unit configured to periodically perform control of light emission from the light source, wherein the control unit divides one period of the control into a first period during which the light source is caused to emit light that is to be detected by the detection unit and a second period during which the light source is caused to emit light at the target brightness, and during the first period, drives the light source using a driving signal with a value smaller than a value during the second period, and the detection unit detects light emitted by the light source during the first period. |
| US09576535B2 |
Pixel and organic light emitting display using the same
A pixel includes an organic light emitting diode, a first driver and a second driver. The second driver controls an amount of current supplied from a first power source to the organic light emitting diode, corresponding to a previous data signal. The first driver stores a current data signal supplied from a data line and supplies the previous data signal to the second driver. In the pixel, the second driver includes a sixth transistor coupled between an initialization power source and a first node coupled to a gate electrode of a first transistor, the sixth transistor being configured to turn on when a first control signal is supplied; and a seventh transistor coupled between the first power source and a second node commonly coupled to the first and second drivers, the seventh transistor being configured to turn on when the first control signal is supplied. |
| US09576531B2 |
Display device and driving method thereof
A display device includes a pixel unit including scan lines, data lines crossing the scan lines, and pixels connected to the scan lines and the data lines; a timing control unit configured to receive first data from an outside; a conversion unit configured to receive the first data from the timing control unit, to extract luminance components of the first data corresponding to the pixels to determine luminance distribution of the first data, to divide the luminance distribution into a plurality of luminance distribution ranges, and to convert the first data into second data by regulating an input gray level of the first data based on a conversion equation corresponding to a variation between data of the luminance distribution ranges; and a data drive unit configured to receive the second data from the conversion unit and to provide the second data to the data lines. |
| US09576530B2 |
Electro-optical device
An optoelectronic device includes a first transistor, a second transistor, and a control circuit. The first transistor is electrically connected between a power supply and a light-emitting element, has a gate to receive a gray scale voltage, and supplies the light-emitting element with a driving current corresponding to the gray scale voltage. The second transistor has a gate electrically connected to an electrode of the light-emitting element and a source or drain electrically connected to a circuit including a voltmeter. The control circuit reads a measurement value of the voltmeter when the gate of the first transistor receives the gray scale voltage, and corrects a next gray scale voltage applied to the gate of the first transistor based on the measurement value. |
| US09576529B2 |
Driving circuit for a display panel and liquid crystal display device using the same
A driving circuit is provided to reduce threshold voltage shifting of a driving switch thereof, and includes a capacitor, a pre-charging switch, a scanning switch, a driving switch, three stabilizing switches, and a light emitting device. A gate electrode of the pre-charging switch receives a first control signal, a drain electrode thereof receives a second control signal, and a source electrode thereof is connected to the capacitor, so as to pre-charge the capacitor to switch on the driving switch. The capacitor then discharges through the driving switch. When the driving circuit reaches a stable state, the driving switch drives the light emitting device to emit light. |
| US09576528B2 |
Display unit, method of manufacturing the same, and electronic apparatus
A method of manufacturing a display unit in which the method includes: forming a transistor on a substrate, in which a first direction to be scanned by an ion implantation apparatus intersects with a second direction to be scanned by an Excimer Laser Anneal apparatus; and forming a display element. |
| US09576521B2 |
Drive device and drive method for vacuum fluorescent display
Provided are a drive device and drive method for a vacuum fluorescent display that can suppress brightness variations in display images and improve display quality. A drive device for a vacuum fluorescent display is provided with a positive electrode unit in which a plurality of positive electrodes to which a phosphor is applied are disposed in a matrix shape and a negative electrode filament that discharges electrons toward the positive electrode unit. The device is provided with: a first magnetic field generating means that generates a first magnetic field perpendicular to the direction in which the positive electrode unit and the negative electrode filament face each other and that can periodically switch polarity; and a second magnetic field generating means that generates a second magnetic field that is perpendicular to the direction in which the positive electrode unit and the negative electrode filament face each other and crosses the first magnetic field and that can periodically switch polarity. |
| US09576519B2 |
Display method and display device
The invention provides a display method and a display device. The display method in the invention is applicable to a display panel comprising multiple rows of sub-pixels, each row of sub-pixels are formed of sub-pixels of various colors which are alternately and circularly arranged, the sub-pixels in each row are arranged in the same order, and in column direction, sub-pixels of the same color are not adjacent, wherein the display method comprises steps of: S1, generating a primary image based on image information, the primary image is formed of virtual pixels arranged in a matrix, each virtual pixel is formed of sub-pixels of different colors and size of the virtual pixel is the same as that of the sub-pixel of the display panel; S2, calculating a display component of each sub-pixel by using primary components of sampling virtual sub-pixels of the sub-pixel. |
| US09576517B2 |
Shift register
A shift register includes a plurality of shift register circuits. Each of the shift register circuits includes a first switch, an input circuit, a pull-down circuit and a ripple reduction circuit. The first switch is used to output a scanning signal of the shift register circuit according to voltage levels of a node and a clock signal. The input circuit is used to pull up the voltage level of the node according to a scanning signal of a previous shift register circuit. The pull-down circuit is used to pull down the voltage levels of the node and the scanning signal of the shift register circuit according to a scanning signal of a following shift register circuit. The ripple reduction circuit is used to suppress ripples on the voltage levels of the node and the scanning signal caused by the coupling effect of the clock signal. |
| US09576515B2 |
Bright dot detection method and display panel
A bright dot detection method adapted to be used in a display panel including a plurality of gate lines, a plurality of source lines and a bright dot detection module. The plurality of gate lines and the plurality of sources line are interlaced thereby forming a plurality of pixels. The bright dot detection method includes: driving the plurality of pixels through enabling the plurality of gate lines simultaneously, thereby forming a first bright line in a first direction; and driving the plurality of pixels through enabling the plurality of gate lines sequentially and providing a control signal to the bright dot detection module, thereby forming a second bright line in a second direction, wherein a bright dot is positioned where the first and second bright lines meet with each other. A display panel is also disclosed. |
| US09576509B2 |
Merchandise labeling
A unitary sheet-like merchandise labeling article that has a labeling tag flatly conjoined along a unifying flat bond zone with a flexible elastic layer that extends away from the tag and includes an elastic fastening loop. The loop sides that define the loop are wider than the thickness of the elastic layer. Further, the flexible elastic layer that extends away from the tag has a thickness greater than the thickness of the tag and has a dispersion zone adjacent the unifying flat bond zone. The dispersion zone allows dissipation of elastic loop in-line stretching forces sufficiently to reduce transmission of such forces into the bond zone. |
| US09576508B2 |
Label and related method
A label and related method of manufacture that includes a fabric made of yarn. The yarn includes a fiber that has been recycled, that is recyclable, that is organic, that is biodegradable, and/or that can be derived from a material that is known to be environmentally friendly. |
| US09576505B2 |
Reorganizing display of a railway timetable diagram
A method and apparatus for reorganizing display of a railway timetable diagram. A method of reorganizing the display of a railway timetable diagram, including: generating a relational graph by using a multiple of stations in the railway timetable diagram and correlations between the stations; partitioning the relational graph according to a partition rule, where the partition rule reduces lines crossing in at least one page and/or section in at least one page in a reorganized railway timetable diagram, where the lines representing an association between respective stations along a path in the reorganized railway timetable diagram; and displaying a reorganized railway timetable diagram based on a result of the partitioning. An apparatus for reorganizing the display of a railway timetable diagram. |
| US09576504B2 |
Mechanical model of the cardiovascular system and method of demonstrating the physiology of the cardiovascular system
A hydraulic model of the cardiovascular system for illustrating a plurality of physiological concepts and relationships including arterial compliance, venous compliance, and peripheral resistance, said model comprising: a.) a cardiac subsystem for moving a fluid in a singular direction in a closed hydraulic system; b.) an arterial subsystem for modeling arterial compliance, the arterial subsystem fluidically coupled with the cardiac subsystem to receive the fluid discharged from the cardiac subsystem; c.) a peripheral resistance subsystem for modeling peripheral resistance, the peripheral resistance subsystem fluidically coupled with the arterial subsystem to receive the fluid discharged from arterial subsystem; d.) a peripheral venous (PV) subsystem for modeling peripheral venous compliance and for modeling a peripheral venous pump (PVP), the peripheral venous subsystem fluidically coupled with the peripheral resistance subsystem to receive the fluid discharged from the at least one downstream conduit; and e.) a central venous (CV) subsystem for modeling central venous compliance and for modeling a thoracic pump (TP), the CV subsystem fluidically coupled with the PV subsystem to receive the fluid discharged from the PV subsystem and to pass the fluid to the cardiac subsystem to complete the cardiovascular cycle. |
| US09576502B2 |
Universal AED training adapter
A training adapter (28) for an automated external defibrillator (AED) (10) which provides for safe training use of any AED. The training adapter includes a circuit which ensures that any defibrillation voltage/current is shunted away from the trainee, training electrodes (26), and patient simulation equipment. The training adapter simultaneously provides to the AED a simulated patient ECG signal which causes the AED to operate as if an actual cardiac rescue were occurring, thus heightening the realism of the training experience. |
| US09576500B2 |
Training supporting apparatus and system for supporting training of walking and/or running
A training supporting system has a training supporting apparatus and an exercise form analyzing apparatus, the both apparatuses being connected to each other through a communication network. The training supporting apparatus is worn on the arm of a user and measures acceleration rates of motion of the user's body where the apparatus is fitted on, at least in the three directions along X-, Y- and Z-axes, while the user is walking or running. Receiving the measured acceleration rates from the training supporting apparatus through the communication network, the exercise form analyzing apparatus analyzes an exercise form including balance between arm swing and foot landing, and sends back the analysis result of the exercise form to the training supporting apparatus through the communication network. |
| US09576497B2 |
Chord playing attachment
A chord playing attachment and related method is disclosed. The chord playing attachment may be attached to a guitar or similar stringed instrument, and the user may use the chord playing attachment to learn to play the instrument. Unlike other chord playing attachments, the present invention discloses a design that does not function as a capo, which allows the user play chords in standard keys. The present invention also discloses tabs that may be removed or swapped by the user to allow the user to play some chords by pressing the strings directly and some by pressing a finger pad. The present invention encourages novices to learn to play the instrument in stages and eventually remove the invention entirely. A companion teaching manual is also disclosed. |
| US09576496B2 |
Flight training system
The present invention provides a system for training a subject to recognize the onset of hypoxia, the system including (i) a flight simulation system, and (ii) a hypoxia induction system, wherein the flight simulation system is operably linked to the hypoxia induction system. The system provides a tool for pilot training to a pilot, allowing for the delivery of standardized training programs where the tasks required for the operation of an aircraft are able to be coordinated with an induction of hypoxia in the subject. Such a system is also able to provide an assessment tool to demonstrate when a pilot has had sufficient training in recognizing the effects of hypoxia. |
| US09576493B2 |
Unmanned aerial vehicle communication, monitoring, and traffic management
A computer-implemented method of communicating with an unmanned aerial vehicle includes transmitting a first message via a communications transmitter of a lighting assembly for receipt by an unmanned aerial vehicle. The first message includes an identifier associated with the lighting assembly, and the lighting assembly is located within a proximity of a roadway. The method also includes receiving a second message from the unmanned aerial vehicle via a communications receiver of the lighting assembly. The second message includes an identifier associated with the unmanned aerial vehicle. The method further includes transmitting a third message via the communications transmitter of the lighting assembly for receipt by the unmanned aerial vehicle. The third message includes an indication of an altitude at which the unmanned aerial vehicle should fly. |
| US09576491B1 |
School child tracking system
A system for tracking school buses and school children to enhance the security and safety of schoolchildren and provide real-time information about the location of students and buses to teachers and administrators and parents. The system utilizes GPS components to determine a location of the school buses and biometric scanning technology to determine the identity of the students. The system transmits location and student identity data to a Main Station using a radio network component. Parents and school teacher and administrators can access the data to monitor. |
| US09576489B2 |
Apparatus and method for providing safe driving information
Provided are an apparatus and method for providing safe driving information. The method includes building a database including group information obtained by grouping driving environment information and driving situation information according to attributes of the driving environment information and the driving situation information, and provision forms and provision timings of safe driving information determined according to conditions in groups; collecting driving environment information, driving situation information, obstacle information, and information on a driver's line of sight in real time; determining a provision form and a provision timing of safe driving information based on the collected information and the database; and providing the safe driving information according to the determined provision form and timing. |
| US09576482B2 |
Management of moving objects
A system comprising a plurality of mobile object servers respectively assigned to a plurality of regions in a geographic space, the plurality of mobile object servers including at least one mobile object server including a mobile object agent assigned to a moving object in the assigned region; and a plurality of event servers operable to manage events occurring in the geographic space; wherein each mobile object server is operable to transfer the mobile object agent to one of the plurality of mobile object servers assigned to a neighboring region in response to the moving object moving to the neighboring region, and execute the mobile object agent to collect information of events from at least one event server, and provide the moving object with information that assists the moving object with traveling in the geographic space. |
| US09576481B2 |
Method and system for intelligent traffic jam detection
Disclosed is a method, apparatus, system and computer program configured to process traffic data and provide relevant information to a driver of a vehicle. A method that is disclosed includes receiving probe data from mobile probes; deriving, from the received probe data, an approximate traffic jam shape and traffic jam area; determining when and at what point a vehicle enters the traffic jam area, and an estimated trajectory of the vehicle within the traffic jam area; and based on the step of determining, generating and sending a message to the vehicle informing the vehicle of at least an estimated time when the vehicle will exit the traffic jam area. |
| US09576478B2 |
Apparatus and associated methods for designating a traffic lane
An apparatus comprising: at least one processor; and at least one memory including computer program code, the at least one memory and the computer program code configured to, with the at least one processor, cause the apparatus to perform at least the following: based on received traveller data, the traveller data representing polled traveller usage of a particular traffic lane, designating the particular traffic lane as a restricted-use lane, the designation for use in subsequent navigation guidance. |
| US09576475B2 |
Wireless-enabled tension meter
A wireless-enabled tension meter is disclosed. The wireless-enabled tension meter can include a pulley arrangement through which a portion of a guiding member is routed for use during a pull of conductor through a conduit network. A tension force is exerted on the guiding member during the pull as the guiding member is pulled through the pulley arrangement. The wireless-enabled tension meter can also include a sensor for measuring the tension force, a wireless network interface, and a control module for performing operations. The operations performed by the control module can include capturing data corresponding to the tension force and causing the wireless network interface to send the data to a wireless communication device. |
| US09576472B2 |
Real-time monitoring and dissemination of energy consumption and production data
A facility comprising systems, methods, and techniques for collecting data indicative of energy consumption and/or energy production by energy systems and devices and providing the data to interested users and devices in real-time is described. The facility may comprise an energy gateway device coupled to one or more monitored devices, one or more energy data extraction servers, and one or more client computers. The energy gateway devices and energy data extraction servers are coupled to a network and are configured to collect energy consumption and/or energy production data from one or more devices and provide an indication of the collected data in real-time or near real-time. The facility may collect current energy consumption or production rates, predicted energy consumption or production levels over a future period of time, and/or amounts of energy that has been consumed or produced by the device over a previous period of time. |
| US09576471B2 |
Radio frequency remote controller device, integrated circuit and method for selecting at least one device to be controlled
A radio frequency (RF) remote controller device comprises radio frequency (RF) circuitry operably coupled to an antenna arrangement and arranged to transmit and receive RF signals to and from controllable devices. The RF remote controller device further comprises signal process logic operably coupled to the RF circuitry and to a user interface. The antenna arrangement is arranged to comprise a directivity characteristic. The signal processing logic upon receipt of a command input from the user interface, is arranged to: determine at least one link quality value that is at least partly dependent upon the directivity characteristic for the at least one controllable device; and select the controllable device for remote controlling based on the determined at least one link quality value. |
| US09576468B2 |
Human motion feature extraction in personal emergency response systems and methods
A non-wearable Personal Emergency Response System (PERS) architecture is provided, having a synthetic aperture antenna based RF interferometer followed by two-stage human state classifier and abnormal states pattern recognition. Systems and methods transmit ultra-wide band radio frequency signals at, and receive echo signals from, the environment, process the received echo signals to yield a range-bin-based slow signal that is spatio-temporally characterized over multiple spatial range bins and multiple temporal sub-frames, respectively, and derive from the slow signal a Doppler signature and a range-time energy signature as motion characteristics of human(s) in the environment and optionally also derive location data as movement characteristics thereof. The decision process is carried out based on the instantaneous human state (local decision) followed by abnormal states patterns recognition (global decision). |
| US09576467B2 |
Emergency detection device, emergency detection system, recording medium, and method therefor
The emergency detection system includes a position information acquisition section, a presumption section, a determination section, and a notification section. The position information acquisition section acquires position information that indicates temporal changes of current positions of a plurality of portable terminals obtained using a GPS. The presumption section presumes a point of emergency occurrence on the basis of the position information acquired by the position information acquisition section. The determination section examines whether or not the point presumed by the presumption section corresponds to an exclusion area, and determines that the point presumed by the presumption section is the point of the emergency occurrence in the case where the point does not correspond to the exclusion area. The notification section notifies the point of the emergency occurrence, which is determined by the determination section, to terminals at a preset destination of the notification. |
| US09576466B2 |
Backup contact for security/safety monitoring system
A method includes receiving an indication that an event has occurred in a physical space being monitored by a monitoring device that includes a plurality of sensors. In response to the indication, the method includes sending one or more primary notifications of the event over a computer-based network to each of one or more persons primarily associated with the physical space being monitored. If, after a designated amount of time, none of the primary notifications have been viewed by any of the persons primarily associated with the physical space being monitored, the method includes sending a backup notification of the event over the computer-based network to one or more persons designated as backup contacts. The backup notification is logically associated with information that the one or more backup contacts can access about the event. The logical association can be embodied by a link (e.g., a hyperlink) in the backup notification. |
| US09576465B1 |
System and method for identifying stolen wireless devices
A first antenna configured to receive a signal from each of a plurality of devices. A library contains at least one unique identifier for at least one target device. A second antenna is used to geolocate the target device once the first antenna locates it in the vicinity of the system. A processor is coupled to the first antenna to receive the signal from the plurality of devices and extract the unique identifier from the signal. The processor compares the unique identifier from the signal to the unique identifiers in the library. Upon a match, the second antenna is used to locate the target device. |
| US09576461B2 |
Primary tag and a secondary tag for communication with each other, and a system comprising a primary tag and one or more secondary tags
Various embodiments relate to tags, methods of using tags, systems, and methods of using systems. Various embodiments may be suitable for identifying a human or an animal. Various embodiments may provide mother-infant matching and cot-infant matching for both single and multiple births; monitoring of the location, movement, and status of the tags; detection of tampering and unauthorized removal of infant tags; and organizing of tags. |
| US09576459B2 |
Evacuation guidance notification device and system
The present invention relates to an evacuation guidance notification system that can detect a fire, can provide notification, can provide guidance on an evacuation route, and can re-ensure a field of vision. The evacuation guidance notification system includes an evacuation guidance notification device installed on a banister post at an edge of a staircase, and the evacuation guidance notification device includes a device housing including a display window, a speaker, a beam output unit, an LED unit, a sensor unit, a control unit, a power unit, a communication unit, and an evacuation direction guidance unit. Furthermore, the device housing constituting part of the evacuation guidance notification device may further include a communication unit configured to communicate with the outside and a control room composed of a computer for controlling the evacuation guidance notification device, and the control room may remotely control the evacuation guidance notification device via the communication unit. |
| US09576458B2 |
Aspirating smoke detectors
Improvements in and Relating to Aspirating Smoke Detectors Disclosed is an aspirating smoke detection system comprising: at least two different types of detector; and a processor operable to receive signals from the at least two different types of detector, and to determine an alarm status, wherein the alarm status is one of: an all clear status; a critical status; and a status intermediate between the all clear status and the critical status. |
| US09576457B1 |
Identification system and method of use
A marking and identification system and method includes a dispersing device configured to disperse marker therefrom when in an activated mode. An activating device is configured to arm the dispersing device from an inactivated mode wherein the dispensing device does not disperse marker to the activated mode. A triggering device is configured to operate the dispersing device and disperse marker when in the activated mode. The marker can be identified at a later time to positively identify a person that triggered the marking and identification system. |
| US09576456B2 |
Solar battery-driven object detection system
A reception unit 2 of a detection unit 3 includes a transmitter 30 that transmits a reception (detection) level of an infrared beam to a transmission unit 1, and a demand signal output unit 26 that transmits to the transmission unit 1 a demand signal M, demanding to control the intensity of the infrared beam to be transmitted so that the reception level matches a predetermined value. The transmission unit 1 includes an infrared ray (detection beam) intensity control unit 15 that controls, upon receipt of the demand signal M, the intensity of the infrared beam to be transmitted so that the reception level matches the predetermined value. A power source unit 31 is a solar battery unit including a solar panel and a charging medium that stores power from the solar panel. |
| US09576453B2 |
Consumer removable tag housing assembly for attachment to a bottle neck
An electronic tag housing assembly is attachable to the extending neck of a bottle having an undercut thereabout. The tag housing includes an annular wall having a central opening for insertion over the extending bottle neck. At least one electronic tag is supported in the housing. The housing has a plurality of resilient fingers extending into the aperture for engagement with undercut on the bottle neck for securing the housing thereto. The housing further includes a portion of the annular wall having a location of reduced thickness for effecting severing of the annular wall thereat so as to remove the housing from the bottle neck. |
| US09576452B2 |
Programmable security system and method for protecting merchandise
A programmable security system and method for protecting an item of merchandise includes a programming station, a programmable key and a security system. The programming station generates a security code and communicates the security code to a memory of the programmable key. The programmable key initially communicates the security code to a memory of the security device and subsequently operates the security device upon a matching of the security code in the memory of the security device with the security code in the memory of the programmable key. The programmable key may also transfer power via electrical contacts or inductive transfer from an internal battery to the security device to operate a lock mechanism. The security code may be communicated by wireless infrared (IR) systems, electrical contacts or inductive transfer. A timer inactivates the programmable key and/or the security device after a predetermine period of time. A counter inactivates the programmable key after a predetermined maximum number of activations. |
| US09576450B2 |
Security wrap with breakable conductors
A security wrap (20) for protecting an electronic component includes a substrate (22) having a first side and a second side opposite to each other. A security screen (26) is disposed over the first side of the substrate (22) and includes a pair of screen terminals (48) and a frangible and electrically conductive path (46) between the pair of screen terminals (48). A layer of adhesive (30) is over the first side of the substrate (22) and bonds the first side of the substrate (22) to the electronic component with the security screen (26) sandwiched there between. |
| US09576449B2 |
Door and window contact systems and methods that include time of flight sensors
Systems and methods that address the gap, security, and robustness limitations of known door and window contact systems and methods without increasing the overall cost thereof are provided. A system can include a time of flight sensor for mounting in or on a first portion of a window unit or a door unit and a microcontroller unit in communication with the time of flight sensor. The sensor can measure a time for a signal to travel from the sensor to a second portion of the window unit or the door unit and back to the sensor, the sensor can transmit the measured time to the microcontroller unit, and the microcontroller unit can use the measured time to make a security determination. |
| US09576447B1 |
Communicating information to a user
A method and device for providing information to a user are provided. The method includes providing at least one user indicator device in operable communication with the user for providing non-visual and non-verbal communications to the user, and enabling information to be received by the user indicator device from a remote source. The method further includes communicating information to the user via the user indicator device in a non-visual and non-verbal way that may be substantially indicative of at least one instruction for the user so the user can operate in one or more environments in conformance with the information provided. |
| US09576440B2 |
Gaming machine with carryover feature units associated with particular symbols
In a gaming machine having virtual reels, certain symbols are modified to identify feature units associated with that particular symbol. The feature units carry over for multiple games until extinguished by being used. If a symbol having one or more feature units is involved in a winning combination, the function associated with its feature units, such as an award multiplier, is applied to the player's award. The symbols adjacent to a winning combination of symbols, or the symbols in the winning combination, may be augmented with a feature unit. A symbol accumulating a certain number of feature units may become a wild symbol. By continuing to accumulate feature units over many games, the symbols progressively become more valuable, and the player is incentivized to keep playing the machine. When the player cashes out, the feature units are extinguished. |
| US09576436B2 |
Card selection game with feature
A gaming machine and method are disclosed. A selected symbol is displayed in a non-revealed manner, for example on a display, a player having nominated at least one characteristic of the symbol. If the selected symbol is revealed to have the nominated characteristic a prize is awarded to the player, and if the symbol is revealed to be a special symbol a game controller awards the player a feature outcome that comprises a plurality of bonus plays of a feature game that includes at least one special symbol. Progression to the next bonus play in the plurality of bonus plays is dependent on selection of the special symbol. |
| US09576434B2 |
Implementing computer activity-based challenges
A computer activity-based challenge may be posted by a computer system to a social network associated with a user of the computer system. A notification may be received from the social network by the computer system indicating acceptance of the challenge for each subscriber of the social network who accepts the challenge. A result obtained by each subscriber who accepted the challenge may be recorded by the computer system after receiving the result from the social network. In some implementations a value associated with the challenge may be updated using dynamic scoring. |
| US09576432B2 |
Gaming machine and gaming method
A game is executed in a normal round, in a first-type free round, and in a second-type free round. The normal round is executed with a first symbol set including a plurality of symbols. The first-type free round is executed with a second symbol set that includes at least one first symbol in addition to the symbols in the first symbol set. The second-type free round is executed with a third symbol set that includes at least one second symbol in addition to the symbols in the first symbol set, the at least one second symbol being different from the at least one first symbol. |
| US09576423B2 |
Gaming system and method of gaming
A method of populating symbol spaces on a gaming device includes providing a plurality of designated spaces arranged to display a plurality of symbols, wherein one of the designated spaces is populated with a symbol from the plurality of symbols by moving the symbol from an initial location, to a final location within the designated space, wherein the game outcome is at least partly dependent on the final location of the symbol. |
| US09576419B2 |
Merchandiser
The present application and the resultant patent provide a merchandiser. The merchandiser may include an ambient compartment with at least one ambient product therein, a temperature controlled compartment with at least one temperature controlled product therein, and a rotary internal transport system within the temperature controlled compartment so as to dispense a temperature controlled product in response to an ambient product being placed therein. |
| US09576418B2 |
Item dispensing apparatus
Various embodiments of the present invention are directed to a dispenser configured for storing one or more items and dispensing the stored items to authorized users. According to various embodiments, the dispenser generally includes a housing defining an interior portion dimensioned to receive a plurality of items and an access assembly configured to prevent unauthorized user access to the interior portion of the dispenser while providing selective access to certain items in response to input received from an authorized user. According to various embodiments, the access assembly comprises a pair of flexible barriers coupled to a sliding door assembly, which includes one or more lockable access doors. Together, the door assembly and flexible barriers prevent access to the interior of the dispenser when in a locked configuration and permit access to certain items when in an unlocked configuration. |
| US09576412B2 |
Network-assisted remote access portal
A computing system contains a processor that is configured to receive, with the user interface, a registered access code and access permissions from a remote user of a property having a property location. The registered access code may be configured to provide access to the property. The access permissions may include a predefined access period that the access code is valid to provide access to the property. The processor may further be configured to receive a provided access code of a local user of the property in response to a user location of the local user being near the property location, match the provided access code with the registered access code, and grant or deny access to the property based in part on the provided access code matching the registered access code and being received within the predefined access period. |
| US09576411B2 |
Apparatus and method for providing security keypad through shift of keypad
An apparatus and method for providing a security keypad are provided. The apparatus for providing a security keypad includes a coordinate generation unit, a keypad output unit, and a key value processing unit. The coordinate generation unit computes a displacement by which a security keypad is to be shifted, and rearranges at least some of keys included in the security keypad by shifting the at least some keys so that the central axis of the security keypad is translated by the displacement. The keypad output unit displays the rearranged security keypad to a user. The key value processing unit processes key values in response to the user's input to the rearranged security keypad, and transfers the processed key values to an application for which the rearranged, security keypad is used. |
| US09576408B2 |
Battery powered trainable remote garage door opener module
A remote garage door opener module for after-market assembly into a vehicle for transmitting signals to a garage door opener includes a bezel positionable against a headliner of the vehicle along an interior surface thereof in a position over a hole in the headliner. The module further includes a housing enclosing a power source and electronic circuitry for transmitting the signals. The housing extends away from a first side of the bezel and is positionable at least partially through the hole in the headliner. The module further includes a button exposed at a second side of the bezel and coupled to the electronic circuitry and a mounting element selectively engageable with the headliner adjacent the hole and coupled with one of the housing or the bezel for coupling the module with the headliner. |
| US09576403B2 |
Method and apparatus for fusion of images
A method and an apparatus for improving a main image by fusing the richer information contained in a secondary image are described. A 3D structure of objects contained in the secondary image is retrieved and a parallax-corrected version of the secondary image is generated using the 3D structure. For this purpose a camera pose for which a projection of the 3D structure of the objects contained in the secondary image best resembles the perspective in the main image is determined and the parallax-corrected version of the secondary image is synthesized based on the determined camera pose. The parallax-corrected version of the secondary image is then fused with the main image. |
| US09576397B2 |
Reducing latency in an augmented-reality display
Disclosed are methods and systems for generating display pixel data so as to reduce latency when rendering a representation of a graphic on a display, such as for augmented-reality applications. The method comprises: receiving a set of display pixel coordinate-pairs at the graphics processing unit; applying a transform matrix to the set of display pixel coordinate-pairs to obtain a set of graphic pixel coordinate-pairs, the transform matrix calculated using orientation data received from an external reference; retrieving a set of graphic pixel data associated with the set of graphic pixel coordinate-pairs; and, determining a set of display pixel data based on the retrieved set of graphic pixel data. |
| US09576394B1 |
Leveraging a multitude of dynamic camera footage to enable a user positional virtual camera
A virtual camera within a volumetric model of a real world environment during an event occurring within the real world environment can be identified. The virtual camera can be associated with at least one of a location and an orientation within the real world environment. A virtual stream for the virtual camera can be constructed. The field of view of the stream can include video obtained from two cameras present within the real world environment and video not captured by a camera within the real world environment. The video field point of view can correspond to at least one of the location and orientation of the virtual camera. The virtual stream of the virtual camera can be presented within an interface of computing device responsive to the constructing. |
| US09576391B2 |
Tomography apparatus and method of reconstructing a tomography image by the tomography apparatus
A tomography apparatus includes a data acquirer which acquires a first image which corresponds to a first time point and a second image which corresponds to a second time point by performing a tomography scan on an object; an image reconstructor which acquires first information which relates to a relationship between a motion amount of the object and the time based on a motion amount between the first image and the second image, predicts a third image which corresponds to a third time point between the first and second time points based on the first information, corrects the first information by using the predicted third image and measured data which corresponds to the third time point, and reconstructs the third image by using the corrected first information; and a display which displays the reconstructed third image. |
| US09576390B2 |
Visualization of volumetric ultrasound images
Various embodiments include systems and methods for adaptive visualization enhancement in volumetric ultrasound images. One or more structures may be determined or identified to be visually enhanced in the volumetric ultrasound images, and one or more visualization changes may be determined, for each of the one or more structures to be visually enhanced. Rendering adjustments required to achieve each of the one or more visualization changes, for each of the one or more structures to be visually enhanced, may then be determined; and the rendering adjustments may be applied during volume rendering of the volumetric ultrasound images. |
| US09576383B2 |
Interactive chart authoring through chart merging
A first chart and a second chart are parsed to determine one or more measures, dimensions, and filters visualized in the first chart and the second chart. The number of measures, dimensions, and filters visualized in the first chart and the second chart are calculated. It is determined how many of the number of measures, dimensions, and filters visualized in the first chart and the second chart are the same. One or more merge rules corresponding to the number of measures, dimensions, and filters visualized in the first chart and to the number of measures, dimensions, and filters visualized in the second chart that aren't the same as measures, dimensions, and filters visualized in the first chart are obtained, and one or more merge permutations are derived based on the obtained merge rules. The first chart and the second chart are merged in accordance with one of the merge permutations. |
| US09576381B2 |
Method and device for simplifying space data
A method and a device for simplifying space data are provided, and the method includes: an original coordinate point of original space data is transformed into a view coordinate point of a view window according to predetermined view control parameters; the view coordinate point is analyzed that whether it accords with a simplification condition; the original coordinate point corresponding to the view coordinate point that accords with the simplification is simplified according to an analysis result. The method for simplifying space data transforms the original coordinate point of original space data into the view coordinate point of the view window and performs analysis processing, which can ensure that not only the space relation of each simplified space data of random complex itself is displayed correctly, but also the space relations between all the simplified space data are displayed correctly. |
| US09576376B2 |
Interactive method of locating a mirror line for use in determining asymmetry of an image
A method and apparatus are provided for locating a mirror line for conducting a mirror analysis of an image by reflecting extracted image content from a portion of the image on one side of the mirror line and overlaying this reflected image content onto the corresponding portion of the image on the opposing side of the mirror line. The extracted image content that is reflected onto the corresponding portion of the image on the opposite side of the mirror line is continuously updated in real-time as the user manipulates the location or orientation of the mirror line. |
| US09576373B2 |
Geospatial imaging system providing segmentation and classification features and related methods
A geospatial imaging system may include a geospatial data storage device configured to store a geospatial dataset including geospatial data points. A processor may cooperate with the geospatial data storage device to determine segments within the geospatial dataset, with each segment including neighboring geospatial data points within the geospatial dataset sharing a common geometric characteristic from among different geometric characteristics. The processor may further determine border geospatial data points of adjacent segments, compare the border geospatial data points of the adjacent segments to determine bare earth segments having respective heights below those of the border geospatial data points of adjacent segments, and classify geospatial data points within each bare earth segment as bare earth geospatial data points. |
| US09576366B2 |
Tracking system and tracking method using the same
A tracking system and method using the same is disclosed which is capable of minimizing a restriction of surgical space by achieving a lightweight of the system as well as a reduction of a manufacturing cost through calculating a three-dimensional coordinates of each of makers using one image forming unit. In the tracking system and method using the same, lights emitted from the markers are transferred to one image forming unit through two optical paths, an image sensor of the image forming unit forms two images (direct image and reflection image) of the two optical paths of the markers, and therefore, the system and method using the same has an effect of reducing a manufacturing cost of the tracking system with small and lightweight, and relatively low restriction of surgical space comparing with conventional tracking system since it is possible to calculate a spatial position and direction of the markers attached on a target by using one image forming unit. |
| US09576358B2 |
Individual-characteristic prediction system, individual-characteristic prediction method, and recording medium
An individual-characteristic prediction system obtains three-dimensional information from brain images of a subject. Further, the individual-characteristic prediction system detects characteristic values of each part of the cerebrum of the subject, and compares the detected characteristic values with stored information prepared in advance to thereby search out stored information having characteristic values similar to the detected characteristic values. Further, the individual-characteristic prediction system predicts abilities or qualities of the subject based on information about abilities or qualities of a brain having the searched out characteristic values. |
| US09576356B2 |
Region clustering forest for analyzing medical imaging data
Systems and methods for training a region clustering forest include receiving a set of medical training images for a population of patients. A set of image patches is extracted from each image in the set of medical training images. A plurality of region clustering trees are generated each minimizing a loss function based on respective randomly selected subsets of the set of image patches to train the region clustering forest. Each of the plurality of region clustering trees cluster image patches at a plurality of leaf nodes and the loss function measures a compactness of the cluster of image patches at each leaf node in each of the plurality of region clustering trees. |
| US09576355B2 |
System and method of monitoring and confirming medication dosage
A medication monitoring system including a patient information unit having a processor, a memory and a patient monitoring unit and a program executing in the memory executing the steps of communicatively coupling a first device with a second device, transmitting live images from the first device to the second device, analyzing the content of the live images to identify at least one biometric attribute of a user in the image and at least one bar code on a container in the image, determining whether the bar code is associated with at least one biometric attribute, and notifying the user whether to consume the contents of the container based on the association of the bar code with the biometric attribute. |
| US09576352B2 |
Method to determine skin-layer thickness in high pressure die castings
A quantitative metallographic method to measure skin layer thickness in high pressure die cast aluminum components. Because the faster-cooling skin layer region exhibits a higher volume fraction of eutectic phases than that of a slower-cooling inner region, measurements showing such higher eutectic phases can be used to quantify such layer thickness. An image at various thicknesses of a location of interest in a cast component sample is first obtained using an image analyzer, from which eutectic volume fractions within each of the received images may be determined. Comparisons of the determined volume fractions can be made against a known or predicted quantity for a particular alloy composition, and then correlated to the skin layer thickness via differences between the received or measured quantities and those of the known standard. |
| US09576351B1 |
Style transfer for headshot portraits
Techniques are disclosed for automatically transferring a style of at least two reference images to an input image. The resulting transformation of the input image matches the visual styles of the reference images without changing the identity of the subject of the input image. Each image is decomposed into levels of detail with corresponding energy levels and a residual. A style transfer operation is performed at each energy level and residual using the reference image that most closely matches the input image at each energy level. The transformations of each level of detail and the residual of the input image are aggregated to generate an output image having the styles of the reference images. In some cases, the transformations are performed on the foreground of the input image, and the background can be transformed by an amount that is proportional to the aggregated transformations of the foreground. |
| US09576350B2 |
Medical image processing apparatus, X-ray diagnostic apparatus, medical image processing method and X-ray diagnostic method
According to one embodiment, a medical image processing apparatus includes a subtraction image acquisition part, a threshold processing part, an image processing part and an image operation part. The subtraction image acquisition part is configured to acquire subtraction image data between X-ray contrast image data and X-ray non-contrast image data of an object. The threshold processing part is configured to perform threshold processing of the subtraction image data or image data generated based on the subtraction image data. The image processing part is configured to perform image processing of image data after the threshold processing. The image operation part is configured to generate image data for a display by an image operation between the subtraction image data and image data after the image processing. |
| US09576348B2 |
Facilitating text identification and editing in images
Facilitating text identification and editing in images in which in one or more embodiments, a user selection of a location in an area of text in an image is received. Given the location, a region of interest that includes text (including the location of the user selection) in the image is determined. Distortion resulting from a surface in the image on which the text is situated being at some angle other than parallel to the image capture plane is also corrected. One or more fonts and font sizes of the text in the region of interest are also detected. Various actions can be taken on the text in the region of interest (e.g., editing the text and/or identifying the text). |
| US09576339B2 |
Mobile terminal, display device and controlling method thereof
A display device including an interface unit configured to be connected to a mobile terminal having a first display unit displaying a mobile screen image; a second display unit for displaying a monitor window having two orientation directions; and a controller configured to display the monitor window in a first orientation direction for displaying a monitor screen image corresponding to the mobile screen image on the second display unit; receive a user command relating to a modification of the mobile screen image; transmit a control signal relating to the user command to the mobile terminal; and display a modified monitor screen image in response to the user command on a second orientation direction of the monitor window. |
| US09576338B2 |
Method for increasing resolutions of depth images
A resolution of a low resolution depth image is increased by applying joint geodesic upsampling to a high resolution image to obtain a geodesic distance map. Depths in the low resolution depth image are interpolated using the geodesic distance map to obtain a high resolution depth image. The high resolution image can be a gray scale or color image, or a binary boundary map. The low resolution depth image can be acquired by any type of depth sensor. |
| US09576336B2 |
Display method and display device
A display method for displaying an image on a transparent display component of a display device includes receiving a display content, determining a background resolution of the image, selecting one of background images as a first background image based on the display content and the background resolution, performing image processing on the first background image to generate a second background image, adding the display content to the second background image to generate the image, and displaying the image on the transparent display component. |
| US09576332B1 |
Systems and methods for remote graphics processing unit service
Aspects of the present disclosure involve systems and methods for providing remote graphics processing unit (GPU) availability to one or more computing components of a data center. In particular, the present disclosure provides the remote location of one or more GPUs within a computing environment for use by one or more computing devices within the computing environment. Thus, each computing device may utilize the remotely located GPUs to perform the tasks of the computing device associated with a GPU, without the need for the GPU to be located within the computing device itself or within the same rack of the computing device. In this manner, one or more GPUs of a computing environment may provide GPU services to any number of computing devices, even though the GPUs are remote from the computing devices. |
| US09576328B2 |
Information processing apparatus, information processing method, and non-transitory computer readable medium
An information processing apparatus includes a configuration information acquiring unit, an operation information acquiring unit, an estimating unit, and a first power calculator. The configuration information acquiring unit acquires configuration information representing a configuration of a device. The operation information acquiring unit acquires operation information representing an operation state of the device. The estimating unit estimates a first device maximum power and a first device minimum power in accordance with the configuration information, the first device maximum power being a maximum power consumed by the device, the first device minimum power being a minimum power consumed by the device. The first power calculator calculates a first power consumed by the device, in accordance with the first device maximum power, the first device minimum power, and the operation information. |
| US09576327B2 |
Managing time-substitutable electricity usage using dynamic controls
A predictive-control approach allows an electricity provider to monitor and proactively manage peak and off-peak residential intra-day electricity usage in an emerging smart energy grid using time-dependent dynamic pricing incentives. The daily load is modeled as time-shifted, but cost-differentiated and substitutable, copies of the continuously-consumed electricity resource, and a consumer-choice prediction model is constructed to forecast the corresponding intra-day shares of total daily load according to this model. This is embedded within an optimization framework for managing the daily electricity usage. A series of transformations are employed, including the reformulation-linearization technique (RLT) to obtain a Mixed-Integer Programming (MIP) model representation of the resulting nonlinear optimization problem. In addition, various regulatory and pricing constraints are incorporated in conjunction with the specified profit and capacity utilization objectives. |
| US09576326B2 |
Identification of a propagator-type leader in a social network
Techniques for identification of a propagator-type leader in a social network are described. According to various embodiments, a specific content item posted by a particular actor of a plurality of actors and interactions by other actors of the plurality of actors with the specific content item are identified. A leadership score associated with the particular actor is calculated, the leadership score indicating a propensity of the particular actor to spread information among the plurality of actors of the online social network service. The particular actor is then classified as an information propagator among the plurality of actors of the online social network service, based on the calculated leadership score. |
| US09576324B2 |
Penalty and interest assessment detail display
Systems and methods are provided for displaying tax penalty and interest assessment calculation details on demand, in real time. In some embodiments, a method includes receiving a request for a penalty and interest assessment value and determining if the request includes a request for calculation details. When the request includes a request for calculation details, the penalty and interest assessment value is calculated using data received with the request. One or more calculation details are populated based on the calculation of the penalty and interest assessment. The method includes displaying the calculated penalty and interest assessment value and the calculation details. |
| US09576323B2 |
System for facilitating multi-channel purchase of FSA eligible items
In a database that is associated with the retailer POS system, inventory is flagged as being FSA-eligible and a retailer POS system is programmed to support FSA debit card auto-adjudication, i.e., the retailer POS system is IIAS certified. The FSA-eligible information that is stored in the retailer POS database is also used to flag for a customer FSA-eligible items presented to the user online, e.g., in an online catalog. When an FSA-eligible item is purchased on-line or at a retailer POS, the FSA debit card information is captured and the purchase transaction is processed by the retailer POS system so the customer has easy access to FSA purchases via either channel. |
| US09576319B2 |
Methods and systems of four-valued Monte Carlo simulation for financial modeling
Automatic trading environments with their high degree of automation have become the backbone of modern financial markets. The ability to process orders and manage risk in these systems while maintaining a low latency between participants is crucial for the safety and liquidity of these markets. The disclosed system describes a four valued Monte Carlo simulation for the stochastic modeling of risk and syntactic pattern matching techniques to facilitate the design of these systems. The system is a self-compiling, machine independent system capable of dividing, scaling and communicating multiple-asset instruments efficiently in a parallel environment. The system also allows for the integration of computerized financial heuristics on financial instruments and user interfaces for creating trading strategies to monitor and hedge risk over a trading desk for financial institutions. |
| US09576317B2 |
Collaborative system for online search
A collaborative real estate search is described. Overlay data including indications of properties for sale within a geographic area are provided to a first user device. The overlay data are capable of being overlaid on a map of the geographic area on a user interface. Selections of some of the properties for sale are received from the first user device and a list of those properties is stored within a folder associated with the first user. The system enables a second user device—associated with a second user who is associated with the first user—to access the list of the properties selected by the user. This includes enabling the second user device to cause information regarding the properties to be stored within the folder. The information is made available for display on a user interface of the first user device. |
| US09576314B2 |
Adapting legacy endpoints to modern APIs
Example methods and systems are directed to adapting legacy endpoints to modern application protocol interfaces (APIs). A legacy endpoint may provide a powerful and complex API. A modern application may desire access to the legacy endpoint. One or more layers may be added between the modern application and the legacy endpoint. Each layer may provide a different API. These layers of APIs may transform the interface from a powerful and complex interface to a more limited but simpler and easier to use interface. In some example embodiments, a proxy layer, an adapter layer, a facade layer, and a service layer may be used. |
| US09576313B2 |
Recommendation systems and methods using interest correlation
A search technology generates recommendations with minimal user data and participation, and provides better interpretation of user data, such as popularity, thus obtaining breadth and quality in recommendations. It is sensitive to the semantic content of natural language terms and lets users briefly describe the intended recipient (i.e., interests, eccentricities, previously successful gifts). Based on that input, the recommendation software system and method determines the meaning of the entered terms and creatively discover connections to gift recommendations from the vast array of possibilities. The user may then make a selection from these recommendations. The search/recommendation engine allows the user to find gifts through connections that are not limited to previously available information on the Internet. Thus, interests can be connected to buying behavior by relating terms to respective items. |
| US09576311B2 |
Footcare product dispensing kiosk
A kiosk apparatus that may select for a person a recommended footcare product based on pressure measurements collected from pressures sensors or calculated biomechanical data estimates. Pressure measurements and calculated biomechanical data estimates may be used to determine if a foot is unshod on the pressure sensor and also group a person into a classified subgroup. The pressure measurement and calculated biomechanical data estimates may also be used to select a recommended footcare product. |
| US09576310B2 |
Normalizing universal product codes
The current disclosure extends to normalizing UPCs so the normalized UPCs can be readily compared against each other and used for item lookups in a local cache. Embodiments of the present disclosure include a UPC cache on a user's mobile device, such as a smartphone. In such embodiments, a UPC that is normalized following processes set forth in the present disclosure may act as a cache key for related product information stored in the cache. By conducting item lookups in a local cache, requests for that data can be served faster than if the data were stored on a remote server. |
| US09576306B2 |
Devices, systems and methods for identifying and/or billing an individual in a vehicle
Devices, systems, and methods are disclosed for identifying a driver versus a passenger within a smart vehicle. This involves a determination of the relative positions of the wireless communication devices within the smart vehicle using near-field communication (NFC) or GPS, AGPS, etc. The wireless communication device detected closest to the driver seat is assumed to be the device owned by the driver. Once identified, the driver can be billed for tolls and other road services, based on the location of the smart vehicle. For instance, as the smart vehicle approaches a toll, a notification can be sent to all of the wireless communication devices. A response from a particular wireless communication device will result in the corresponding user's account being billed for the toll. Further, the smart vehicle can communicate with near-field transceivers placed, for instance, alongside a High-Occupancy Vehicle (HOV) lane. A driver of the vehicle can be billed, fined, or ticketed based upon a determination of an absence of passengers in the smart vehicle. |
| US09576305B2 |
Detecting competitive product reviews
One embodiment provides a system for recommending products. The system may include a search engine to retrieve, from a collection of product reviews, product review results using at least two input product names. The system may also include a template builder to build comparative sentence templates to define relationships between at least two product names, in which each comparative sentence template has a weight as a function of the defined relationship, and the search engine extracts one or more snippets matching at least one of the comparative sentence templates within each product review result. The system may further include a review ranking device to rank the product review search results based on the one or more extracted snippets, in which each snippet has a same weight as its matched comparative sentence template. |
| US09576302B2 |
System and method for dynamic generation of video content
An automated system method for dynamically generating a composite video clip by a computer. In some embodiments of the invention, a template may be provided including at least one digital media asset and one or more placeholders, each placeholder associated with a respective dynamic content object and a respective layout. The system and method may extract from one or more websites, for example, e-commerce sites, data items corresponding to each of the dynamic content objects, and generated a composite video clip including the media asset, wherein the dynamic content objects are replaced with respective extracted data and presented in association with the media asset based on their respective layouts. |
| US09576300B2 |
System and method for wireless software download and remote transaction settlement
A portable computer in a store can be carried past a kiosk and wirelessly receive from the kiosk demonstration versions of software, along with an ID of the store. Later, after using the demonstration version, the user can access a Web server and purchase a full version of the software. During the transaction, the store ID is provided to the server, which can then credit the particular store at which the demonstration version was obtained with a sale. |
| US09576294B2 |
System and method for providing coupon-less discounts based on a user broadcasted message
The systems and methods provide an offer to a user that may be accepted by the user through an action by the user. The action may be, for example, a broadcast through a social media channel. The parameters of the offer may defined that the broadcast comprise an offer identifier and may require that a user take subsequent action to fulfill the offer. The systems and methods may also be configured to monitor one or more broadcast channels, identify the source of a broadcast, identify transaction accounts associated with the source, evaluate transaction data associated with the transaction account, and provide benefits to the source and/or the transaction account. |
| US09576291B2 |
Method and system for detection of a fuel card usage exception
Determining a fuel card usage exception with the use of a computer that receives fuel card transaction data responsive to a fuel purchase event. The fuel card transaction data identifies a quantity of fuel purchased for a vehicle using a fuel card. In addition, the computer receives first fuel level data and second fuel level data of the vehicle that identifies a quantity of fuel present in a fuel tank of the vehicle prior to a fuel purchase event and after a fuel purchase event respectively. The computer can determine an exception associated with the fuel purchase event based on the fuel card transaction data, the first fuel level data, and the second fuel level data. Responsive to detecting an exception associated with the fuel purchase event, the computer may generate an alert and transmit the alert for presentation by a computing device of a user. |
| US09576287B1 |
Payment event feed
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for processing payment events. One of the systems includes one or more processing engines configured to periodically retrieve information from a payment event feed that comprises a list of payment events in an order, and a server configured to perform a sequence of steps for a payment transaction, the sequence of steps including receiving a request for authorization of the payment transaction from a merchant, receiving an indication that the payment transaction has been authorized, and sending authorization to the merchant for the payment transaction without receiving acknowledgment that the one or more transaction processing engines have received the request for authorization, wherein the server is configured to record completion of each step in the sequence of steps as a payment event in the list of payment events to generate the payment event feed. |
| US09576285B2 |
One gesture, one blink, and one-touch payment and buying using haptic control via messaging and calling multimedia system on mobile and wearable device, currency token interface, point of sale device, and electronic payment card
Methods and systems for messaging, calling, and one blink, one-touch, and one gesture payments and buying via mobile and wearable devices are disclosed. An exemplary system comprises a database in communication with a processor, the processor configured to provide a haptic control associated with the system. The haptic control is shown on a display of a mobile and wearable device overlapping other visual elements. The haptic control provides mode selection elements associated with a payment, messaging, and calling modes. The processor receives a selection of the payment mode via the mode selection elements from a user. Upon the selection, context is extracted from the display. Based on the context, a payment transaction type which the user intends to perform is determined. The payment transaction type includes a payment receiving transaction and a payment sending transaction. Based on the determining, a transaction request is sent to a financial institution using the extraction. |
| US09576284B2 |
Social proximity payments
An application or App on a payer's mobile device is used to discover people known to the user and who are in close proximity to the user at the time of a payment request. Discovery can be through searching contact lists and/or social networks of the payer and/or through the payer device discovering contacts around the payer and then searching the payer's contact or social network list to see if there are any matches. These people are then shown to the user on the user device, such as with a photo, icon, name, and/or email address. The user selects desired ones, which causes requests to be sent to the selected people, such as through text, voice, or email, to the respective devices. The selected people can then easily confirm or authorize a payment be sent to the user or to a payee. |
| US09576276B2 |
Context-informed summarization of communications
A method and computer program product for context-informed summarization is described. A method may comprise determining, via a computing device, a context of a communication. The method may further comprise determining, via the computing device, a summarization attribute for the communication based upon, at least in part, the context of the communication. The method may also comprise creating a summary of the communication based upon, at least in part, the summarization attribute. |
| US09576269B2 |
Document management systems and methods
A method for managing documents in a computer implemented document management system, includes: creating a document profile that is associated with a document and includes fields of attributes of the document; and creating a link in the document profile to a file type that is not created within the document management system. |
| US09576267B2 |
System and method for taking an inventory of containers for liquid
A computer based system for taking the physical inventory of liquids dispensed in full and partially full containers. A database stores images of containers and their associated volumes. The containers to be inventoried are identified by a user and input to a computer at a graphical user interface (GUI) input/output. A computer causes the display of an image of the container and a sliding level indicator at the GUI. The level indicator is slidable along the image. The computer calculates a volume of liquid remaining in the container as a function of the position of the level indicator along the image of the container. |
| US09576266B2 |
Material harmonization disposition system for electronic inventories
A material harmonization disposition system is provided to harmonize disparate material databases by identifying volumes of common database inventory parts and operating as a database authorizing tool for declaring and recording common inventory parts in categorized manner for disposition. |