| Document | Document Title |
|---|---|
| US09559890B2 |
Routing device as a command client
A routing device determines data associating commands with devices connected to a local area network (LAN). The routing device receives a request for execution of a particular command and identifies a particular device to execute the particular command based on the command data. The routing device generates an instruction message that causes the particular device to execute the particular command, and the routing device forwards the instruction message to the particular device via the LAN. The request may be received via a wide area network (WAN), and the request may include an address for the routing device on the WAN. When generating the instruction message, the routing device may replace, in the request, the address for the routing device with an address associated with the particular device. The instruction message may further include parameters associated with execution of the particular command by the particular device. |
| US09559885B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
Disclosed is a method for transmitting broadcast signals, including: formatting input streams to a plurality of data pipes (DPs), wherein the formatting comprises allocating data packets to a payload of a baseband frame (BBF), and adding a header indicating a format of the payload of the baseband frame, and the header comprises at least one of first control information and second control information. |
| US09559883B2 |
Power efficient digital wireless transmitter and method of operation thereof
A digital wireless transmitter and a method of transmitting a high-power modulated RF signal using a digital wireless transmitter are provided. In one embodiment, the transmitter includes: a digital system-on-a-chip configured to receive a complex digital input signal and having: an all-digital phase-locked loop and digital pulse modulator configured to modulate a phase and frequency modulation signal based on the complex digital input signal to yield a modulated complex signal, a driver configured to generate a pulse-position-modulated and pulse-width-modulated pulse train based on an instantaneous phase and amplitude of the modulated complex signal and a power supply modulation control block configured to develop an amplitude modulation control signal based on the complex digital input signal that defines a non-constant-envelope for an output signal of the transmitter. |
| US09559882B2 |
Apparatus and methods for flexible provision of control data in large data structures
Methods and apparatus for the flexible provision of control data within large data structures. In one exemplary embodiment, DisplayPort is modified from its existing 8B/10B line coding to 128B/130B (or 128B/132B). In one embodiment, the 128B/130B (or 128B/132B) block includes: sixteen (16) eight (8) bit command or data symbols and a two (2) bit (or four (4) bit) synchronization header. The synchronization header may provide a fixed reference to the next command symbol (for example, the symbol immediately following the synchronization header). In one variant, each command symbol is split into a first and a second portion, where the first portion identifies a control function (control symbol), and the second portion provides a reference to the next command symbol. |
| US09559881B2 |
Transceiver system with reduced latency uncertainty
A transceiver system with reduced latency uncertainty is described. In one implementation, the transceiver system has a word aligner latency uncertainty of zero. In another implementation, the transceiver system has a receiver-to-transmitter transfer latency uncertainty of zero. In yet another implementation, the transceiver system has a word aligner latency uncertainty of zero and a receiver-to-transmitter transfer latency uncertainty of zero. In one specific implementation, the receiver-to-transmitter transfer latency uncertainty is eliminated by using the transmitter parallel clock as a feedback signal in the transmitter phase locked loop (PLL). In one implementation, this is achieved by optionally making the transmitter divider, which generates the transmitter parallel clock, part of the feedback path of the transmitter PLL. In one implementation, the word aligner latency uncertainty is eliminated by using a bit slipper to slip bits in such a way so that the total delay due to the word alignment and bit slipping is constant for all phases of the recovered clock. This allows for having a fixed and known latency between the receipt and transmission of bits for all phases of parallelization by the deserializer. In one specific implementation, the total delay due to the bit shifting by the word aligner and the bit slipping by the bit slipper is zero since the bit slipper slips bits so as to compensate for the bit shifting that was performed by the word aligner. |
| US09559878B2 |
Phase adjustment circuit for clock and data recovery circuit
Described are phase adjustment circuits for clock and data recovery circuits (CDRs). Systems and apparatuses may include an input to receive a serial data signal, an edge data tap to sample transition edges in the serial data signal for generating a data edge detection signal, a CDR circuit including a phase detector to receive the serial data signal and the data edge detection signal, and to output a phase lead/lag signal indicating the phase difference between the serial data signal and the data edge detection signal, and a phase adjustment circuit to generate phase lead/lag adjustment data. The CDR circuit is to output a recovered clock signal based, at least in part, on the phase lead/lag signal adjusted by the phase lead/lag adjustment data. |
| US09559872B2 |
Signal transmission system
A signal transmission system includes a transmitter configured to encode a transmission signal to generate 2N (N: integer larger than or equal to two) binary signals among which a number of 0s and a number of 1s are equal to each other, and to transmit the 2N binary signals, 2N signal lines configured to transmit the 2N binary signals, respectively, and a receiver configured to detect a bit pattern among a plurality of possible bit patterns of the 2N binary signals in response to a plurality of differential components between 2N received signals received through the 2N signal lines, and to decode the detected bit pattern. |
| US09559868B2 |
Apparatus and methods for bandwidth saving and on-demand data delivery for a mobile device
A method for reducing data bandwidth usage in wireless communication comprises receiving a request from the a mobile device to provide the an e-mail message; sending a request to the an e-mail server for delivery of the e-mail message; analyzing the e-mail message delivered from the e-mail server to determine if a size of the e-mail message is above a threshold value, and if not expanding the e-mail content to be above the threshold value; acknowledging to the mobile device the existence of the e-mail message and its respective size; and delivering to the mobile device header content of the e-mail content, thereby only a small fraction of the data corresponding to the e-mail message is actually delivered to the mobile device. |
| US09559867B2 |
Contact group dynamics in networked communication devices
A communications terminal (200) including a user interface communicably coupled to a controller is configured to form a group of contacts. In one embodiment, the terminal displays only contacts having at least two attributes in common. In another embodiment, the terminal displays a group of contacts having a social relationship with at least two degrees of social separation relative to a user associated with the group. In another embodiment, a group of contacts is formed upon initiation of an application at the terminal, wherein all contacts in the group are associated with terminals running the same application and are also engaged in a common activity. |
| US09559866B2 |
Systems and methods for load balancing in cellular networks and wireless local area networks
Network operators are striving to find ways to provide stable video services amid a rapid increase in video data traffic. In order to provide stable video services with constrained network resources, network operators attempted to deploy multiple communication networks in parallel. However, network operators failed to effectively balance data traffic across parallel communication networks. This disclosure provides systems and methods for effectively balancing data traffic across parallel communication networks. |
| US09559864B1 |
Method and system for managing wireless devices using short-range wireless communication
A wireless device includes a self-activation client that allows a user to activate a communication service for that wireless device and for one or more other wireless devices. The communication service may use a long-range type of wireless communication, such as 1×RTT CDMA, EV-DO, GSM, or IEEE 802.16 (WiMAX) communication. During the activation process, the wireless device communicates with a device management server using the long-range type of wireless communication but communicates with the one or more other wireless devices using a short-range type of wireless communication, such as IEEE 802.11 (WiFi), Bluetooth, or infrared communication. After the communication service has been activated, the wireless device may subsequently communicate with the device management server in order to manage the communication service for itself and/or for one or more other wireless devices (e.g., to receive updates or to make changes). |
| US09559860B2 |
Method and apparatus for monitoring activity of an electronic device
An apparatus and method for monitoring activity of a device. The method includes associating one or more monitoring devices with an electronic device. Rules that have been established to define acceptable content that can be accessed by the electronic device are accessed. Requested content, which is requested by the electronic device, is identified. The requested content is compared to the established rules. An alert condition is generated when the requested content violates the established rules. An alert signal is provided to the one or more monitoring devices based on the alert condition. |
| US09559859B2 |
Home hub
In one embodiment, transmitting, from a first computing device, a private-home-network-discovery message that comprises a first identifier corresponding to a private-home-networking system, receiving, at the first computing device, one or more content-response messages from a second computing device that collectively comprise a second identifier corresponding to the second computing device, a third identifier corresponding to the private-home-networking system, and information corresponding to content stored on the second computing device, and storing, at the first computing device, the second and third identifiers and the information received in the one or more content response messages for access by one or more applications hosted on the first computing device, one of the applications being associated with administering the private-home-networking system. |
| US09559855B2 |
System and method for providing multicast delivery in a network environment
A method is provided in one example and includes receiving signaling data associated with a request for a multicast channel, the request includes an Internet protocol version 6 (IPv6) source and an IPv6 group address. The method may also include identifying an Internet protocol version 4 (IPv4) source and an IPv4 group address to be mapped to the IPv6 source and the IPv6 group address. The signaling data can be converted from a first protocol to a second protocol. The converted signaling data can be communicated to a network element. In more particular embodiments, the network element is an IP edge router configured to join the multicast channel and stream data in response to receiving the converted signaling data. The IP edge router can be configured to perform an encapsulation operation to transport IPv6 multicast packets within an IPv4 multicast channel. |
| US09559850B2 |
Component management via secure communications
Technologies are generally described for establishing secure communications to manage components of a control system. In some examples, upon receiving a request from a component to join a cluster of components, a class and instance of the component may be verified to authorize the component. A command to be transmitted from the component to another component of the cluster may be marked with a signature, where restrictions may be placed on a type of command that a particular class of component may transmit to one or more other classes of components. Based on the signature, a secure communication path between the components may be established by creating an encrypted virtual private network (VPN). The command may then be transmitted from the component to the other component through the secure communication path. |
| US09559849B1 |
Service-to-service digital path tracing
A service receives from a sender service a digital message and a corresponding trace, which includes an ordered set of digital signatures of one or more services that participated in causing the service to receive the digital message. The trace may further specify an ordering of the one or more services, which may be generated according to the order of participation of these one or more services. The service may compare the received trace to recorded message paths to determine whether the ordering specified within the trace is valid. If the ordering is valid, the service may use one or more digital certificates to further verify the digital signatures included within the trace. If the service determines that these digital signatures are also valid, the service may process the message. |
| US09559845B2 |
Systems, methods and apparatuses for the secure transmission of media content
The systems, methods and apparatuses described herein permit encrypted media content to be displayed by a display device under control of a local device. The local device may comprise a computer processor to control playing of the encrypted media content and a first communication interface to transmit an association encryption envelope and, according to the control, the encrypted media content. The display device may comprise a second communication interface coupled to the first interface to receive the encrypted media content and the association encryption envelope, a decryption engine to decrypt the association encryption envelope using a private key of the display device to recover a symmetric encryption key used to encrypt the encrypted media content and decrypt the encrypted media content using the recovered symmetric encryption key, and a decoder to decode the decrypted media content for display on a display screen according to the control. |
| US09559833B1 |
Frequency synchronization for a near field communication (NFC) device
A first near field communication (NFC) device is disclosed that synchronizes a first carrier wave of the first NFC device to a second carrier wave of a second NFC device. The first NFC device observes a magnetic field having the first carrier wave modulated with information corresponding to the first NFC device and the second carrier wave modulated with information corresponding to the second NFC device. The first NFC device isolates the information corresponding to the second NFC device from the combined sequence of information to determine a frequency error and/or a phase error between the carrier waves. Finally, the first NFC device adjusts the frequency of the first carrier wave in accordance with the first frequency error and/or the phase of the first carrier wave in accordance with the first phase error to synchronize the carrier waves. |
| US09559829B2 |
Signaling for flexible carrier aggregation
Flexible carrier aggregation is provided for a radio communications system. A capability is determined to communicate over a radio interface using multiple radio frequency component carriers. Each of the multiple component carriers is configurable with one or more control channels in a first mode of operation and with no control channels in a second mode of operation. Configuration information for one of the multiple radio frequency component carriers is signaled to indicate at least one of the component carriers is configured to operate in a selected one of the first mode of operation and the second mode of operation so that a network radio node and a user equipment radio node can communicate using the selected mode of operation. |
| US09559827B2 |
Methods and arrangements for managing reporting of channel quality
A wireless device (105) for managing reporting of channel quality is configured to communicate with a mobile radio communication network (102). The wireless device (105) identifies (404) there being no downlink activity between the wireless device (105) and the mobile radio communication network (102). The wireless device (105) reduces (406), in response to the identification, a level of channel quality reporting when there is no downlink activity. In a multi Radio Access Bearer (RAB) scenario this supports reduction of a higher drop rate of multi-RAB, e.g. speech and data, compared to e.g. stand-alone speech RAB. |
| US09559824B2 |
Method and apparatus for extending control signalling in an LTE network
A method for a wireless network node to support an extended control signaling is provided. The method comprises configuring a control signaling message over extended control symbols on a layer 1 (L1) downlink control channel, the control signaling message encoded over an increased aggregation of control channel elements (CCEs) in a time domain; placing the controlling signaling message in a designated set of subframes on the L1 downlink control channel; indicating a support for the extended control signaling to one or more UEs; indicating to the one or more UEs a position of the designated set of the subframes in a spare field of the Master Information Block (MIB); and transmitting the control signaling message to the one or more UEs over the L1 downlink control channel. |
| US09559823B2 |
Method and apparatus for allocating a control channel resource of a relay node in a backhaul subframe
A method and apparatus for allocating control channels of a relay is provided. The method includes generating resource block assignment information related to resource blocks allocated to the relay; transmitting resource information comprising the resource block assignment information; and transmitting a control channel according to the resource information. |
| US09559815B1 |
Generation of OFDM symbols
A method for generating a modified orthogonal frequency division multiplexing (OFDM) symbol, the method may include generating, for each pair of FDR error and outer OFDM symbol constellation sample that belong to a same sub-carrier, a modified OFDM symbol constellation sample thereby providing multiple modified OFDM symbol constellation samples; and calculating the modified OFDM symbol; wherein the calculating of the modified OFDM symbol comprises performing a frequency domain to time domain conversion of (a) the multiple modified OFDM symbol constellation samples and (b) unmodified OFDM symbol constellation samples. |
| US09559813B2 |
Method for transmitting control information and apparatus for same
A method and a user equipment for transmitting uplink control information in a wireless communication system supporting carrier aggregation and operating in time division duplex (TDD) are discussed, the user equipment being configured with a first component carrier (CC) and a second CC having different uplink-downlink configurations, the user equipment being configured to transmit a hybrid automatic repeat request-acknowledgement (HARQ-ACK) response based on channel selection. The method according to an embodiment includes determining and transmitting HARQ-ACK bits. When a value W is 1 or 2, one or more HARQ-ACK bits for the first CC are determined based on min (M1, W) and one or more HARQ-ACK bits for the second CC are determined based on min (M2, W). Min (A, B) represents a smallest number, M1 represents a number of downlink subframes, and M2 represents a number of downlink subframes. |
| US09559811B2 |
Apparatus for transmitting broadcast signals, apparatus for receiving broadcast signals, method for transmitting broadcast signals and method for receiving broadcast signals
The present invention provides a method of transmitting broadcast signals. The method includes, encoding, by an encoder, PLP (Physical Layer Pipe) data; time interleaving, by a time interleaver, the encoded PLP data; frame mapping, by a framer, the time interleaved PLP data onto at least one signal frames; frequency interleaving, by a frequency interleaver, data in the at least one signal frames; and waveform modulating, by a waveform module, the frequency interleaved data in the at least one signal frame and transmitting, by the waveform module, broadcast signals having the modulated data, wherein the frequency interleaving is conducted according to an interleaving mode, wherein the interleaving mode is determined based on a FFT (Fast Fourier Transform) size. |
| US09559810B2 |
Methods and arrangements for a check sequence
According to various aspects of the present disclosure, medium access control (MAC) sublayer logic of a device or a system may generate and implement a preamble structure of a data unit including a signal field which includes a four-bit cyclic redundancy check sequence providing a Hamming distance of two. The signal field portion of the preamble structure may include information related to a plurality of physical layer parameters used for wireless communication of the data unit. The preamble structure may be stored on a machine-accessible medium. The preamble may be generated by a data unit builder of the device, which may further receive a frame including a data payload, and encapsulate the frame with the preamble portion to generate the data unit. A transmitter coupled with the data unit builder may then wirelessly transmit the data unit using an antenna array. |
| US09559804B2 |
Connected vehicles adaptive security signing and verification methodology and node filtering
We introduce a connected vehicles adaptive security signing and verification methodology. We also introduce an adaptive node filtering at receiver, using noise levels and received signal strength. This invention addresses two important pillars in connected vehicle technology and autonomous cars: The first one is related to the security 1609.2 format and its main two functions: signing and verification. The second one explains how the noise level and signal strength can be used to filter undesired connected nodes. In this presentation, we provide various examples and variations on these topics. |
| US09559796B1 |
Location sensitive, public security advisory system and method
A location sensitive, public security advisory system and method that communicates with the service subscriber app running on mobile devices, and utilizes the real-time location information to present comprehensive subscriber status information in a given area of interest to security agents. This system can also identify zones at different security status and direct the apps on the mobile devices to display textual alerts and visual geographical zone alerts on the map and blueprint of the area of interest. The system can also provide escape route advice to the subscribers textually or visually on the app's map. |
| US09559794B2 |
Apparatus and method for detecting signals
A signal detection apparatus includes a signal reception unit, an Analog to Digital (A/D) signal processing unit, and a user interface unit. The signal reception unit receives an external signal. The A/D signal processing unit determines whether the received signal is an abnormal signal based on a plurality of signal profiles having different signal characteristics, and obtains the abnormal signal if, as a result of the determination, it is determined that the received signal is the abnormal signal. The user interface unit displays the abnormal signal. |
| US09559789B2 |
Control device update
A system and method for updating IR signal information remotely for control devices are disclosed. |
| US09559788B2 |
Systems and methods for communicating data through an electromagnetic barrier
An electromagnetic barrier includes a first surface and a second surface. A first transducer is coupled to the first surface. A second transducer is coupled to the second surface such that a signal is transmittable between the first transducer and the second transducer without physically penetrating the electromagnetic barrier. |
| US09559783B2 |
Optical receiver and method for controlling optical receiver, optical receiver, method for controlling optical receiver, and method for receiving light
In an optical receiver which is compatible with a plurality of signal channels, it is difficult to receive signals properly because a variation in receiving light sensitivity of a photoelectric conversion unit occurs between a plurality of signal channels, therefore, an optical receiver according to an exemplary aspect of the invention includes an optical processing circuit processing input signal light to have been input and outputting a plurality of output signal light beams; and a plurality of photoelectric conversion means for receiving the plurality of output signal light beams respectively and outputting electric signals, wherein the photoelectric conversion means includes an avalanche photodiode which can control a multiplication factor of an output current as the electric signal by means of an applied voltage; and the avalanche photodiode operates with a driving voltage by which the output currents in the plurality of photoelectric conversion means become almost the same. |
| US09559782B2 |
Optical receiver for multimode communications
An optical receiver (20) for multimode communications comprises: a mode demultiplexer (21) having an input connected to a multimode link (22) and a plurality of output lines (231-234), wherein the mode demultiplexer is adapted to couple each of the modal components of the optical signal substantially into a selected one of the output lines, a plurality of coherent optical detectors (251-254) respectively connected to the output lines to produce a set of electrical digital signals each comprising an in-phase component and a quadrature-phase component, a plurality of independently adjustable optical delay devices (241-244) arranged on the output lines to impart a selected delay to each of the corresponding modal components, and a signal processing device (26) adapted to process the digital signals to recover the independent modulations of the respective modal components by inverting a mode-mixing characteristic of the multimode link. |
| US09559778B2 |
Optical dispersion compensation in the electrical domain in an optical communications system
Optical dispersion imposed on a communications signal conveyed through an optical communications system is compensated by modulating the communications signal in the electrical domain. A compensation function is determined that substantially mitigates the chromatic dispersion. The communications signal is then modulated in the electrical domain using the compensation function. In preferred embodiments, compensation is implemented in the transmitter, using a look-up-table and digital-to-analog converter to generate an electrical predistorted signal. The electrical predistorted signal is then used to modulate an optical source to generate a corresponding predistorted optical signal for transmission through the optical communications system. |
| US09559774B1 |
Bi-directional data and signal channels in optical interconnects
In one embodiment, the present teachings provide for an efficient means to implement bidirectional data and signal channels in optical interconnects. Each optical interconnect channel may include two pairs of emitters and detectors that are imaged onto each other. Many such bidirectional optical channels may be simultaneously interconnected in dense two-dimensional arrays. The send or receive state of each bidirectional optical channel may be directly set in some embodiments by an electronic control signal. In other bidirectional optical channel embodiments, the send/receive state may be controlled locally and autonomously as derived from the output of the local detector. |
| US09559772B2 |
Method and system for achieving communication between mobile device and electronic device
A method and a system for achieving communication between a mobile device and an electronic device are disclosed. The system includes a mobile device, having a lighting unit, which modulates light beams therefrom with a message signal by a communicating mode; a light beam receiver, connected to or embedded in an electronic device, for receiving the modulated light beams and transforming the modulated light beams into an electric signal; and a demodulator, equipped in the electronic device, for demodulating the electric signal to get the message signal. Light beams are used as media to transmit signal from the mobile device to the electronic device. |
| US09559770B2 |
WSON restoration
Dynamic restoration involves routing and bandwidth assignment of an unplanned restoration path in a wavelength switched optical network (20), having regeneration nodes (60), nodes each having a ROADM (62) having drop paths and add paths. An electrical switch (68) provides configurable regeneration capacity by coupling selected drop paths to selected add paths. Some of the configurable regeneration capacity is kept for unplanned restoration paths. A PCE determines (120) routing and bandwidth assignments for an unplanned restoration path for the traffic flow to avoid a fault, and sends (130) configuration messages to the nodes to set up the unplanned restoration path dynamically and to configure the electrical switch to provide regeneration on the path. Keeping some reconfigurable regeneration capacity enables much longer unplanned paths to be found to avoid faults, and enables wavelength conversion if needed. Thus the reliability of finding at least one path avoiding the fault can be increased. |
| US09559769B2 |
Communication systems
A transmission method for use in a wireless communication system is provided. The system includes a source apparatus, a destination apparatus and an intermediate apparatus, where the source apparatus and destination apparatus are arranged to transmit and receive information via the intermediate apparatus, and where at least the source apparatus is arranged to perform a network entry process in order to connect to the system. The includes, in the intermediate apparatus, determining whether the source apparatus has initiated a network entry process with the intermediate apparatus and if so, notifying the destination apparatus thereof while continuing to conduct the network entry process with the source apparatus. The method also includes, in the destination apparatus, responding to said notification with a return message to the intermediate apparatus, said return message being used to facilitate completion of the network entry process. |
| US09559766B2 |
Dynamic point to point mobile network including intermediate device aspects system and method
A computationally implemented system and method that is designed to, but is not limited to: electronically receiving one or more communication network relay related transmissions at least in part associated with one or more first portions of mobile operating system operated intermediate electronic communication device functionality related at least in part to communication network relay functionality of a mobile operating system operated intermediate electronic communication device as one or more standby communication network relays upon activation thereof for use by one or more origination electronic communication devices to communicate at least in part with one or more destination electronic communication devices, the mobile operating system operated intermediate electronic communication device functionality including second portions related at least in part to mobile electronic communication device functionality. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure. |
| US09559763B2 |
Method and arrangement for polarization control in a communication system
Controlling the polarization state of signals to be transmitted from a MIMO capable radio base station node to a plurality of user equipment, which radio base station node comprises a precoder unit connecting a first and a second virtual antenna port to a respective first and second transmit antenna port, by the steps of controlling a relative phase between transmitted signals from the first and second transmit antenna port to provide a predetermined pair of orthogonal polarization states for signals transmitted on the first and second virtual antenna ports, and interchanging the polarization states of the first and second virtual antenna ports, to provide transmitted polarized signals with alternating polarization states. |
| US09559759B2 |
System and method for massive MIMO communication
A system and method of adjusting an equivalent channel for a downlink in a multiple-antenna communication system is disclosed herein. The system includes at least one user device and a base station having a plurality of analog RF chains, each analog RF chain having a plurality of antennas. The method comprises the base station obtaining equivalent channel information and adjusting the phases of the antennas in order to modify equivalent channel gains from the analog RF chains to the at least one user device, based on the equivalent channel information. |
| US09559756B2 |
Antenna system optimized for SISO and MIMO operation
An active antenna system and algorithm is described that provides for improved performance from LTE communication systems operating in Category 1 mode, where one antenna is used. For the LTE SISO case (category 1), a modal antenna capable of generating multiple radiation patterns will provide improved throughput due to improved resistance to fading. Modal (Null Steering) antenna technology is implemented in a multi-antenna system to provide for single and multiple antenna operation wherein one or more antennas have two or more radiation modes. An algorithm has been developed that determines when to switch from SISO to MIMO operation. |
| US09559752B1 |
Switching signal polarity of a network device plug for use in a powerline communication network
A network device may include a plug that couples with a socket to couple the network device to a PLC network. A position of the plug may be interchanged when the plug is coupled with the socket. In one example, the network device may determine a coupling orientation of the plug that indicates the position of the plug with respect to the socket. The plug includes a first plug terminal, a second plug terminal, a first ground plug terminal, and a second ground plug terminal. The network device may select a signal polarity for the plug based, at least in part, on the coupling orientation. The signal polarity indicates over which of the plug terminals data is to be transmitted for communication over the PLC network. |
| US09559751B2 |
Communication system, transmission apparatus, line control apparatus, line state monitoring method and non-transitory computer readable medium storing program
A communication system includes a radio transmission apparatus that terminates a radio communication line, a radio transmission apparatus that terminates a radio communication line, and a line control apparatus that performs data communication with the radio transmission apparatuses. The radio transmission apparatuses and monitor the line states of the radio communication lines and notify the line control apparatus of the line states. The line control apparatus controls data to be output to the radio transmission apparatuses and according to the line states. |
| US09559745B2 |
Dedicated shunt switch with improved ground
Antenna tuning switch circuitry includes an input port, a shunt switch, control circuitry, and an integrated ground. The shunt switch is coupled between the input port and the integrated ground. The control circuitry includes a control signal input port, a switch driver output port coupled to the shunt switch, and a ground connection port coupled to the integrated ground. The shunt switches, the RF input ports, the control circuitry, and the integrated ground are monolithically integrated on a single semiconductor die. The antenna tuning switch circuitry is adapted to selectively couple the input port to the integrated ground in order to alter one or more operating parameters of an attached antenna. By monolithically integrating the shunt switch together with the control circuitry and the integrated ground, the ON state impedance and the parasitic OFF state impedance of the antenna tuning switch circuitry can be significantly improved. |
| US09559744B2 |
System and method for TDD/TMA with hybrid bypass switch of receiving amplifier
Various embodiments disclosed herein relate to a circuit for connecting a transceiver input/output to an antenna, the circuit including one or more of the following: a transceiver port; an antenna port; a reception path disposed between the transceiver port and the antenna port; a first amplifier configured to amplify a signal on the reception path when the circuit is configured according to a normal operation mode; and a first hybrid coupler configured to establish a bypass path around the first amplifier when the circuit is configured according to a bypass operation mode. |
| US09559740B2 |
Mobile terminal case and mobile terminal
There is disclosed a polio case including a back cover coupled to a rear surface of a mobile terminal, a quick cover connected to a predetermined portion of the back cover, to cover a front surface of the mobile terminal, a touch unit provided in an inner portion of the quick cover, the touch unit formed of a conductive material, wherein a touch sensor provided in the front surface of the mobile terminal contacts with the touch unit, when the quick cover is closed, and capacity of the touch sensor changes. The polio case may provide the display unit with a screen matching a shape of the quick cover. |
| US09559739B2 |
Protective cases for mobile electronic communication devices
A protective case for a mobile electronic communication device having a user input interface includes a front cover configured to couple with a rear cover to define a volume for receiving the mobile electronic communication device, the front cover having an aperture aligned with the user input interface when the mobile electronic communication device is received in the volume; a transparent membrane provided between the front cover and the rear cover to be disposed over the user input interface when the mobile electronic communication device is received in the volume; and a compressible member arranged between the front cover and the membrane and separate from the front cover, the transparent membrane configured to provide a seal between the transparent membrane and the front cover when the mobile electronic communication device is received in the volume and the front cover is coupled to the rear cover. |
| US09559737B2 |
Telecommunications chip card
The invention provides for a telecommunications chip card for logging into a mobile a digital cellular mobile telecommunications network (107). The telecommunications chip card comprises a chip card reader interface for communicating with a mobile telephone device, a chip card processor means, and a secure memory means (302) for storing programs for execution by the chip card processor means. The secure memory means contains a program (304). The program causes the chip card processor means to: perform (200) a first cryptographic mutual authentication between the telecommunications chip card and a terminal device (502), receive (214) a configuration message (400, 402, 404, 406, 408, 410, 524) via the chip card reader interface, store the (216) configuration message in the secure memory means, and delete (218) the program from the secure memory means. |
| US09559736B2 |
Auto-selection method for modeling secondary-path estimation filter for active noise control system
An active noise control system and associated auto-selection method for modeling a secondary path for the active noise control system are provided. The method includes the steps of: receiving a reference signal; filtering the reference signal with a secondary-path estimation filter to obtain a filtered reference signal, wherein the secondary path estimation filter is determined from a plurality of candidate secondary-path estimation filters; filtering the reference signal with an adaptive filter to provide a compensation signal; sensing a residual noise signal at a listening position of the active noise control system; and adapting filter coefficients of the adaptive filter according to the residual noise signal and the filtered reference signal. |
| US09559735B2 |
Switching resonator filter circuits and methods
The present disclosure includes switching resonant filter circuits and methods. In one embodiment, a circuit includes a plurality of resonant switching circuits arranged in a three (3) or four (4) element PI network. In one embodiment, an undesired signal frequency is applied to two resonant switching circuits and a carrier frequency of an RF signal is applied to the other two resonant switching networks so that the network attenuates the undesired signal frequency and passes the carrier frequency. In another embodiment, the resonant switching circuits are configurable to shift a peak impedance so that undesired signals may be attenuated. |
| US09559732B2 |
Wireless apparatus
A wireless apparatus including: an amplification circuit configured to generate a second signal by amplifying power of a first signal, a calculation circuit configured to calculate a deviation amount of phase deviation of the second signal from the first signal, and a correction circuit configured to correct the phase deviation using a correction method that is selected from a plurality of correction methods based on the deviation amount, the plurality of correction methods among which each power consumption is higher as each correction amount corresponding to each power consumption is greater. |
| US09559730B2 |
Multiplexer
A multiplexer is disclosed configured between a transceiving antenna and a receiving channel and a transmitting channel; the transceiving antenna, the receiving channel and the transmitting channel are shared by signals of at least two modes. The multiplexer includes a combiner module, transmitting filter modules, receiving filter modules and amplifier modules in one-to-one correspondence with the signals of various modes. The multiplexer addresses the problem of how multi-mode signals share a transmitting channel, a receiving channel and a transceiving antenna. |
| US09559729B2 |
Same-band combiner using dual-bandpass channel filters
Various embodiments relate to an apparatus and related method for transmission and reception of a plurality of a carrier signals comprising one or more dual-band channels through a same-band combiner. A device such as a base station may include a same-band combiner that comprises a plurality of dual-bandpass filters and a combining element to transmit and receive the carrier signal. Each of the dual-bandpass filters may transmit and receive a channel, with each dual-bandpass filter including separate reception and transmission passbands for the separate frequencies in the dual-band channel. The combining element may separate and combine the one or more dual-band channels, with each of the dual-bandpass filters connected in parallel processing separate dual-band channels. |
| US09559728B2 |
Systems and methods for providing resilience to LTE signaling interference in WiFi
Systems and methods presented herein enhance WiFi communications in a RF band where conflicting LTE signaling exists. In one embodiment, a system includes a processor operable to detect the WiFi communications between a UE and a wireless access point of a WiFi network, to identify errors in the WiFi communications, and to determine a periodicity of the errors based on the LTE signaling structure. The system also includes an encoder communicatively coupled to the processor and operable to encode the WiFi communications with error correction, and to change the error correction based on the periodicity of the errors in the WiFi communications. |
| US09559727B1 |
Stopping rules for turbo product codes
Row decoding is performed on row codewords in an array in order to produce a row decoded array that includes row decoded column codewords. Column decoding is performed on the row decoded column codewords in order to produce a row and column decoded array that includes row and column decoded row codewords and row and column decoded column codewords. The number of row and column decoded row codewords that are not in a row codebook is determined and the number of row and column decoded column codewords that are not in a column codebook are determined. If the number not in the row codebook equals 0 and the number not in the column codebook equals 1, at least a data portion of the row and column decoded array is output. |
| US09559724B2 |
Method and device for processing received data
A method and device for decoding a plurality of packets of same data. Each packet is encoded using a product code. An encoded packet comprises data blocks is organized into rows and columns. Each of the rows and columns has a respective error detecting code. For a data packet, Erroneous row and column data are detected by their associated error detecting code. In the data packet, a potentially erroneous data block belonging to a row and a column of data blocks both having been detected as erroneous is detected. In another data packet of the same data, a non-erroneous data block corresponding to the identified potentially erroneous data block is determined. The data block is determined as non-erroneous if it belongs to at least one row or column of data having been detected as non-erroneous. The identified potentially erroneous block is replaced with the determined non-erroneous block. |
| US09559723B2 |
Transmitting apparatus, receiving apparatus, and controls method thereof
Provided are apparatuses and methods for generating and transmitting transmission frames of information data. A transmitting apparatus includes: a stream processor configured to generate a plurality of baseband frames; a frame generator configured to generate, from the plurality of baseband frames, a plurality of transmission frames which includes information data commonly provided to a fixed device and a mobile device, first parities to be used for signal processing at the fixed device, and second parities to be used for signal processing at the mobile device; and a transmitter configured to transmit the plurality of transmission frames. |
| US09559722B1 |
Network devices and methods of generating low-density parity-check codes and performing corresponding encoding of data
A network device including a matrix generating module, an encoding module and a transceiver. The matrix generating module is configured to generate or access a code base matrix, wherein the code base matrix has a corresponding code rate of 7/8. The matrix generating module is also configured to, based on the code base matrix, generate a resultant matrix of a low-density parity-check code. The resultant matrix includes sub-matrices. Each of the sub-matrices is generated based on a respective element in the code base matrix. The resultant matrix has a code length of 648 or 1296. The encoding module is configured to encode data based on the resultant matrix. The transceiver is configured to transmit the encoded data. |
| US09559719B1 |
Single amplifer bi-quad sigma-delta modulator
Some embodiments include apparatus and methods using a first stage including an integrator, a second stage coupled to the first stage, the second stage including an amplifier, a first capacitor, and a second capacitor coupled in series with the first capacitor between an input node and an output node of the amplifier, a quantizer coupled to the output node of the amplifier, and a feedback path coupled to an output node of the quantizer and to the first and second stages, the feedback path including a digital-to-analog converter (DAC), the DAC including an input node coupled to the output node of the quantizer and an output node coupled to the input node of the amplifier. |
| US09559716B1 |
AD converter, AD convert apparatus, and AD convert method
A processing speed can be improved while the accuracy of AD conversion is enhanced. An AD converter includes: a higher-order DAC that samples an analog input signal and performs DA conversion corresponding to higher-order bits of a digital output signal; an extension DAC that performs DA conversion to positive and negative polarities on an extension bit for expanding bits of the higher-order DAC; a lower-order DAC that performs DA conversion corresponding to lower-order bits of the digital output signal; a comparator that compares a comparison reference voltage with output voltages of the higher-order DAC, the extension DAC, and the lower-order DAC; and a successive approximation logic that controls successive approximation performed by the higher-order DAC, the extension DAC, and the lower-order DAC based on a comparison result of the comparator and generates the digital output signal. |
| US09559713B1 |
Dynamic tracking nonlinearity correction
An analog-to-digital converter (ADC) is used for dynamic tracking nonlinearity correction. The correction employs an analog sampling technique to determine the signal derivative by measuring the derivative current arising from sampling an analog input signal undergoing analog-to-digital conversion, at the sampling instant. The analog derivative sampling technique achieves significant reduction in power consumption with less complexity compared with a digital approach, with strong improvements in HD3, SDFR, and IM3 measures. |
| US09559704B1 |
Fractional-N phase-locked loop with reduced jitter
In an example, operating a PLL circuit includes generating an error signal in response to comparison of a reference clock signal having a reference frequency and a feedback clock signal having a feedback frequency, generating a plurality of clock signals having an output frequency based on the error signal, and generating the feedback clock signal from the plurality of clock signals based on a first divider value and a control value derived from a second divider value. Operating the PLL circuit further includes multiplying each of a first integer value and a first fractional value by a power of two to generate a second integer value and a second fractional value, respectively, generating the second divider value using a sigma-delta modulator (SDM) based on the second integer value and the second fractional value, and dividing the second divider value by the power of two to generate the first divider value. |
| US09559703B2 |
System ready in a clock distribution chip
Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready. |
| US09559701B2 |
Sensor system, power feeding apparatus, and synchronization method
A power feeding apparatus includes a power feeding stop section that stops, all together, the supply of electric power to a plurality of sensors connected to the power feeding apparatus. Each of the sensors outputs a signal including timing information indicating the timing at which the supply of electric power is stopped by the power feeding stop section. A synchronization section synchronizes the output signals of the plurality of sensors based on the timing information. |
| US09559698B2 |
Spintronic logic element
An embodiment includes a C-element logic gate implemented as a spin logic device that provides a compact and low-power implementation of asynchronous logic by implementing a C-element with spintronic technology. An embodiment includes a first nanopillar including a first contact and a first fixed magnetic layer; a second nanopillar including a second contact and a second fixed magnetic layer; and a third nanopillar including a third contact, a tunnel barrier, and a third fixed magnetic layer; wherein (a) the first, second, and third nanopillars are all formed over a free magnetic layer, and (b) the third fixed magnetic layer, the tunnel barrier, and the free magnetic layer form a magnetic tunnel junction (MTJ). Other embodiments are described herein. |
| US09559696B2 |
Gate driver and related circuit buffer
A circuit buffer for outputting a voltage signal having a magnitude greater than a withstand voltage of any circuit element in the circuit buffer includes a first transistor and a second transistor. The first transistor includes a first terminal and a second terminal electrically connected to an input terminal and an output terminal of the circuit buffer respectively, a third terminal electrically connected to a first power supply terminal, and a fourth terminal electrically connected to the third terminal of the first transistor. The second transistor includes a first terminal and a second terminal electrically connected to the input terminal and the output terminal of the circuit buffer respectively, a third terminal electrically connected to a second power supply terminal, and a fourth terminal electrically connected to the third terminal of the second transistor. Voltages of the first and second power supply terminal are switched between two different levels, respectively. |
| US09559691B1 |
Semiconductor device and semiconductor system
A semiconductor system may include a first semiconductor device configured to output a test stop signal and a calibration control signal. The semiconductor system may include a second semiconductor device configured to generate a first state code from an external resistor, a second state code from an internal resistor, and a third state code from a fuse array in response to the calibration control signal, and to select one of the first to third state codes as a selection code in response to the test stop signal and the calibration control signal. |
| US09559689B2 |
Vehicle control switch with capacitive touch redundancy actuation
A vehicle control switch for controlling operation of a device in a motor vehicle is disclosed. The vehicle control switch includes an electromechanical switch switchable between ON and OFF states responsive to physical actuation of the electromechanical switch by an operator, the physical actuation comprising an application of force onto the electromechanical switch by the operator. The vehicle control switch also includes a capacitance sensitive touch sensor positioned adjacent the electromechanical switch and whose capacitance changes when brought into contact with a grounded object, with activation of the electromechanical switch into the ON state being inhibited until a grounded object is brought into contact with the capacitance sensitive touch sensor, such that an activation of the rocker switch to the ON state is enabled only upon contact with the capacitance sensitive touch sensor by the grounded object. |
| US09559687B2 |
Semiconductor device, power control device and electronic system
In order to reduce the cost and the like of a power control device including a semiconductor device such as a driver IC, as well as an electronic system, the driver IC includes a high side driver, a level shift circuit, first and second transistors, and a comparator circuit. The first transistor is formed in a termination area. The second transistor is formed in the termination region and is driven by a first power supply voltage. The comparator circuit is formed in a first region to drive the first transistor to be ON when the voltage of a sense node is lower than the first power supply voltage, while driving the first transistor to be OFF when the voltage of the sense node is higher than the first power supply voltage. The second transistor is a depression type transistor. |
| US09559686B2 |
Input/output circuit
A circuit includes a first power node, a second power node, an output node, a plurality of first transistors and a plurality of second transistors. The plurality of first transistors is serially coupled between the first power node and the output node. The plurality of second transistors is serially coupled between the second power node and the output node. |
| US09559684B1 |
Non linear resonant switch cell
Switch cells consist of an array of power switches and passive components which can replace the main switches in many power topologies, allowing reduced switching loss without altering the power topology directly. The switch cell topology discussed herein utilizes a saturable resonant inductor to reduce the size and power loss of the cell. Additionally, the cell transfers energy stored in the inductor into a capacitor for efficient energy storage during the cell's conduction region. This energy is then transferred back to the system when the cell turns off, thus reducing the total switching energy. |
| US09559683B2 |
System and method for a switch having a normally-on transistor and a normally-off transistor
In accordance with an embodiment, a circuit includes a first driver having a first output configured to be coupled to a control node of a normally-off transistor. The first driver is configured to drive a first switching signal at the first output in a cascode mode and configured to drive a first constant voltage at the first output in a direct drive mode. The circuit further includes a second driver having a second output configured to be coupled to a control node of a normally-on transistor that has a second load path terminal coupled to a first load path terminal of the normally-off transistor. The second driver is configured to drive a second switching signal at the second output in the direct drive mode. |
| US09559682B2 |
Protected switching element
A circuit is suggested comprising an electronic switching element, a logic unit coupled to control the electronic switching element, and a counter unit coupled to the logic unit, wherein the counter unit comprises a counter and an internal power supply. |
| US09559681B2 |
Semiconductor integrated circuit device
A semiconductor integrated circuit device is configured such that if, due to an erroneous connection or the like, an abnormal state is entered in which an output voltage is lower than a ground potential VSS, an N-type DMOS transistor and a first P-type MOS transistor are turned off and a voltage is applied to their parasitic diodes in the opposite direction, preventing a current from flowing. In a normal state in which the output voltage is higher than the ground potential, at least one of the N-type DMOS transistor and first P-type MOS transistor, which are connected in parallel, is turned on, preventing a current from flowing into the parasitic diode of the N-type DMOS transistor. |
| US09559676B1 |
Output buffer apparatus for controlling rate of rising/falling edge of buffered signal
An output buffer apparatus is provided. A clamp circuit outputs a clamp voltage through a transistor pair having a first configuration. A bias circuit outputs a bias voltage through a transistor pair having a second configuration. A rate control circuit for rising/falling edge buffers an input signal according to the clamp voltage and the bias voltage to generate a buffered signal. |
| US09559672B1 |
Ser tolerant flip flop having a redundant latch
In one or more embodiments, an integrated circuit includes a programmable memory, a key generation module and a module. The programmable memory is to maintain a first key portion. The key generation module is to generate a key using the first key portion from the programmable memory and a second key portion received via a memory interface. The module is to encrypt or decrypt data using the key. |
| US09559671B1 |
Devices and methods with capacitive storage for latch redundancy
A master slave storage circuit can include a first master portion coupled to a first master data storage node and a first slave portion coupled to a first slave data storage node. The first master portion can comprise one of a first master latch or a first master capacitive element coupled to the first master data storage node and the first slave portion comprises one of a first slave latch or a first slave capacitive element coupled to the first slave data storage node. If the first master portion comprises the first master latch, the first slave portion comprises the first slave capacitive element, and if the first master portion comprises the first master capacitive element, the first slave portion comprises the first slave latch. |
| US09559669B1 |
Circuits for and methods of generating clock signals enabling the latching of data in an integrated circuit
A circuit for generating clock signals enabling the latching of data is described. The circuit comprises a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a latch circuit coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal; wherein a pulse width of the output clock signal is determined by the feedback signal and the input signal coupled to the pulse generator. A method of generating clock signals enabling the latching of data is also described. |
| US09559665B2 |
Ultra-low voltage temperature threshold detector
An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A threshold detector selectively applies either a first voltage or second voltage to the doped well region based on whether the temperature of the semiconductor substrate is above or below a threshold temperature. |
| US09559662B2 |
Synchronous charge sharing filter
A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate. |
| US09559660B2 |
Micromechanical devices comprising n-type doping agents
The invention concerns a micromechanical device and method of manufacturing thereof. The device comprises an oscillating or deflecting element made of semiconductor material comprising n-type doping agent and excitation or sensing means functionally connected to said oscillating or deflecting element. According to the invention, the oscillating or deflecting element is essentially homogeneously doped with said n-type doping agent. The invention allows for designing a variety of practical resonators having a low temperature drift. |
| US09559658B2 |
Filter coefficient group computation device and filter coefficient group computation method
A filter coefficient group computation device is configured from a means for performing inverse Fourier transform on a frequency characteristic inputted through an input means; a means for performing short-term Fourier transform on a numerical string obtained by the inverse Fourier transform; a means for performing windowing on a frequency domain signal, obtained by the short-term Fourier transform, using a function of which a window length shortens as frequency increases; a means for performing short-term inverse Fourier transform on the frequency domain signal after the windowing; a means for performing overlap addition on a numerical string obtained by the short-term inverse Fourier transform; and a means for determining a numerical string after the overlap addition as a filter coefficient group which forms a filter having the frequency characteristic inputted through the input means. |
| US09559652B1 |
Systems and methods for identifying a mute/sound sample-set attribute
Presently described are systems and methods for identifying a mute/sound attribute of an audio sample set having first-channel samples and second-channel samples. An embodiment takes the form of a method that includes: (i) receiving the audio sample set; (ii) for each first-channel sample, determining a first max amplitude and a first min amplitude; (iii) calculating a first span based on a first function of the first max amplitude and the first min amplitude; (iv) for each second-channel sample, determining a second max amplitude and a second min amplitude; (v) calculating a second span based on a function of the second max amplitude and the second min amplitude; and (vi) identifying the audio sample set as having a sound attribute if both the first span and the second span are greater than a min-volume threshold. |
| US09559651B2 |
Metadata for loudness and dynamic range control
An audio normalization gain value is applied to an audio signal to produce a normalized signal. The normalized signal is processed to compute dynamic range control (DRC) gain values in accordance with a selected one of several pre-defined DRC characteristics. The audio signal is encoded, and the DRC gain values are provided as metadata associated with the encoded audio signal. Several other embodiments are also described and claimed. |
| US09559648B2 |
Amplifier with reduced idle power loss using single-ended loops
A method of audio signal processing includes receiving a first audio input signal (first input signal) at an input of a first integrating amplifier of a first single-ended (SE) closed loop channel, and second input signal with a polarity reversed relative to the first input signal at an input of a second integrating amplifier configured of a second SE closed loop channel. During audio signal processing a common-mode (CM) reference voltage level applied to a current source coupled to an input of the first and second integrating amplifiers is dynamically changed including whenever a level of the input signals is below a predetermined low level, reducing the CM reference voltage level for implementing low duty cycle (LDC) PWM operation, and whenever the level is above a level that corresponds to an onset of clipping, increasing the CM reference voltage level for at least reducing the clipping to lower crossover distortion. |
| US09559646B2 |
Apparatus and method for dynamically biased baseband current amplifier
A dynamically biased baseband current amplifier is provided. The dynamically biased baseband current amplifier includes an input interface; a controller; a variable resistor network; an amplifier stage; a hybrid differential envelope detector and full-wave rectifier; a transconductor; a first variable transistor; a second variable transistor; a third variable transistor; and a fourth variable transistor. |
| US09559642B2 |
Audio delivery system having an improved efficiency and extended operation time between recharges or battery replacements
Embodiments of the disclosure may include a method and apparatus for improving the efficiency and extending the operation time between recharges or replacement batteries of a portable audio delivery system. The audio delivery system may include a processor, an audio processing device, a speaker, and a rechargeable power source. The audio delivery system is generally configured to generate and/or receive an audio input signal and efficiently deliver an amplified, high quality audio output signal to a user. In some embodiments of the disclosure, the audio processing device of the audio delivery system may include a switch mode power supply (SMPS), a signal delay element, an envelope detector, and a switching signal amplifier. |
| US09559640B2 |
Electrostatic discharge protection for CMOS amplifier
A CMOS amplifier including electrostatic discharge (ESD) protection circuits is disclosed. In one embodiment, the CMOS amplifier may include a PMOS transistor, a NMOS transistor, primary protection diodes, and one or more auxiliary protection diodes to limit a voltage difference between terminals of the CMOS amplifier. In some embodiments, the auxiliary protection diodes may limit the voltage difference between an input terminal of the CMOS amplifier and a supply voltage, the input terminal of the CMOS amplifier and ground, and the input terminal and the output terminal of the CMOS amplifier. |
| US09559638B2 |
Distortion compensation apparatus and distortion compensation method
A distortion compensation apparatus includes a calculation unit that acquires, from calculation performed by using a factor and an output signal from the amplifier, a distortion component that is associated with the distortion generated in the amplifier, and a comparing unit that compares a signal that is obtained by giving the distortion component acquired by the calculation unit to an output signal output from the amplifier, with an input signal input to the amplifier, to which a distortion component is previously given. The calculation unit adjusts, on the basis of a comparison result obtained by the comparing unit, the factor that is used for the calculation. |
| US09559636B2 |
Thyristor-based optoelectronic oscillator with tunable frequency and optical phase lock loop employing same
An optoelectronic circuit for producing an optical clock signal that includes an optical thyristor, a waveguide structure and control circuitry. The waveguide structure is configured to split an optical pulse produced by the optical thyristor such that a first portion of such optical pulse is output as part of the optical clock signal and a second portion of such optical pulse is guided back to the optical thyristor to produce another optical pulse that is output as part of the optical clock signal. The control circuitry is operably coupled to terminals of the optical thyristor and receives first and second control signal inputs. The control circuitry is configured to selectively decrease frequency of the optical clock signal based on the first control signal input and to selectively increase frequency of the optical clock signal based on the second control signal input. |
| US09559634B2 |
Cleaning apparatus
The invention relates to a cleaning apparatus, in particular for cleaning solar installation surfaces or photovoltaic installation surfaces, comprising a carrier, at least one cleaning roller rotatably supported at the carrier, and a rotary drive for the cleaning roller, wherein the rotary drive is designed as a fluid drive, wherein the flow of a cleaning fluid supplied to the cleaning roller for cleaning purposes is converted into a drive movement for the cleaning roller. |
| US09559632B2 |
Solar propelled aircraft structure
A solar propelled aircraft which has a wing having solar cell modules mounted therein includes: first solar cell modules which are positioned in a wing or a tail wing of the aircraft and receive solar energy directly from the sun; second solar cell modules which are positioned in a main wing or a tail wing of the aircraft and supplied with directed energy from the earth; and rotating shafts which rotate the first solar cell modules and the second solar cell modules so that the first solar cell modules and the second solar cell modules correspond to each other in both directions. The first solar cell module at the upper surface obtains solar energy from the sun, and the second solar cell module at the lower surface obtains directed energy transferred from the earth. |
| US09559631B2 |
Clamp assembly for solar panels
A clamp assembly for solar panels comprising a base and a clamp. The base has a baseplate and first and second spaced-apart struts connected to the baseplate to form a channel. Surfaces of the struts define slots adjacent to the channel. Beams are connected to the struts. The clamp includes a plate with fingers extending from the plate into the channel. The clamp further includes angled surfaces and cylindrical surfaces defining holes through the clamp plate. The clamp assembly is preferably made from a nonconductive material to inhibit arcing and the risk of electrical fire from incorrect or failed wiring. |
| US09559630B2 |
System and method for controlling modulation of an inverter
A current measurement module is adapted to measure an observed current level for the inverter. A data processor or mode controller accesses a stored representation of first current level versus rotor speed output at which a total harmonic distortion level is less than threshold total harmonic distortion level. The data processor or mode controller enables the inverter to use SVPWM (space vector pulse width modulation) if the observed current level is less than the first current level for the measured or determined rotor speed. Further, the data processor or mode controller enables the inverter to use DPWM (discontinuous pulse width modulation) if the observed current level is greater than or equal to the first current level for the measured or determined rotor speed. |
| US09559628B2 |
Handheld power tool with compact AC switch
A power tool is disclosed having a compact AC switch assembly. An electric motor driving the power tool is contained within a housing that includes a handle. A trigger is slidingly received in the handle and moves in an axis of trigger travel along a trigger travel distance extending between an extended position of the trigger and a depressed position. A trigger switch including a printed circuit board is disposed in mechanical communication with the trigger and controls the electric motor in accordance with trigger position. The printed circuit board has a plurality of conductive traces that are sequentially arranged and linearly aligned adjacent the trigger in a direction that is transverse to the axis of trigger travel to reduce the width of the printed circuit board to a value that is less than or equal to three times the trigger travel distance. |
| US09559619B2 |
Electronically controlled switch for an electric motor
A system in which the operation of an electric motor is controlled by electronically controlled switches. The system includes the motor having a run winding and a start winding, a heating component, and a motor control subsystem. A control unit closes a first switch to energize the run winding, closes a second switch to energize the start winding, determines based on an amplitude and a lag time of a current flowing through the motor whether the motor has started and is running normally, and if so, opens the second switch to de-energize the start winding and closes a third switch to activate the heating component. The control unit determines whether the motor has started and is running normally by comparing the real time amplitude and lag time of the current to a plurality of stored amplitudes and lag times associated with different operating conditions. |
| US09559618B2 |
Controller for a seatbelt positioning device and seatbelt positioning device
A control (18) for a seat belt positioning device (10) includes a motor (12) for positioning a seat belt component (16). A locking tongue sensor (20) generates a locking tongue signal (S) depending on whether a locking tongue is inserted in a belt buckle (16). A trigger circuit (22) connected to the locking tongue sensor (20) generates a trigger signal (TR, TR1, TR2, VT, TM) in response to the locking tongue signal (S) A timer (32) or a motor load circuit (33) connected to the trigger circuit (22) generates a motor signal (M) having a predetermined period or depending on a motor load in response to the trigger signal (TR, TR1, TR2, VT, TM). A motor control circuit (34) connected to the timer (32) and the trigger circuit (22) turns the motor on and off in response to the motor signal (M). The direction of motion of the motor (12) is selected depending on the trigger signal (TR, TR1, TR2, VT, TM). |
| US09559616B2 |
Quasi-static electric field generator
A generator for producing an electric field for with an inspection technology system is provided. The generator provides the required variable magnitude quasi-static electric fields for the “illumination” of objects, areas and volumes to be inspected by the system, and produces human-safe electric fields that are only visible to the system. The generator includes a casing, a driven, non-conducting and triboelectrically neutral rotation shaft mounted therein, an ungrounded electrostatic dipole element which works in the quasi-static range, and a non-conducting support for mounting the dipole element to the shaft. The dipole element has a wireless motor system and a charging system which are wholly contained within the dipole element and the support that uses an electrostatic approach to charge the dipole element. |
| US09559614B2 |
Grid-connected inverter, inverter arrangement and method for operating an inverter arrangement
A grid-connected inverter for feeding current via a transformer into an electric power grid includes an output bridge arrangement that is actuated via a pulse width modulator, wherein a periodic auxiliary signal is used to determine switching times of the output bridge arrangement. The inverter also includes a synchronization unit for phase synchronization of the auxiliary signal with the electric power grid, wherein the synchronization unit is configured to set a predetermined phase offset (ΔΦ0) of the periodic auxiliary signal with respect to a phase of the electric power grid. |
| US09559613B2 |
System and method for a switch driver
In accordance with an embodiment, switch driver includes a first switch driver configured to be coupled to a control node of a first switch, a second driver configured to be coupled to a control node of a second switch, and a first terminal and a second terminal configured to be couple to a boot capacitor. The first terminal is coupled between a boot input of the first switch driver and the second terminal is configured to be coupled to outputs of the first switch and the second switch. The switch driver further includes a voltage measurement circuit coupled to the first terminal and the second terminal, and a control circuit configured to activate the second switch driver when the voltage measurement circuit indicates that a voltage across boot capacitor is below a first threshold. |
| US09559609B2 |
Integrated power-converting module
An integrated power-converting module includes a bobbin, a primary coil, a magnetic core assembly, and a plurality of power-converting units. The bobbin includes a main body, a plurality of winding portions and a plurality of receiving portions, and the winding portions and the and the receiving portion are arranged in a staggered manner. The primary coil is wound on the winding portions and the magnetic core assembly is assembled with the bobbin. Each power-converting unit includes a circuit board, a rectifier, and a filter, the rectifier and the filter are placed on a base portion of the circuit board and electrically connected thereto. An extending portion of the circuit board connect to the base portion is inserted into a slot formed within the receiving portion, and a penetrating hole formed on the extending portion is aligned with and communicated with a first channel formed on the main body. |
| US09559605B2 |
System for ambient energy harvesting
A method and apparatus is disclosed herein for harvesting ambient energy. In one embodiment, an energy harvester comprises: a first RF rectifier to output a first voltage determined by rectified RF energy in response to received RF energy; a first energy reservoir coupled to the first RF rectifier to store energy at the first voltage; a DC/DC converter coupled to the first energy reservoir to convert the first voltage to a second voltage; a second reservoir coupled to the DC/DC converter to store energy at the second voltage, the second voltage being greater than the first voltage; and a third reservoir coupled to the second reservoir to receive energy transferred from the second reservoir periodically. |
| US09559601B2 |
Forward-flyback topology switched mode power supply
A switched mode power supply (400), comprising a transformer (410) having a primary winding (410-1), a transformer core (410-3) configured to store energy transferred thereto from the primary winding (410-1) during operation, and a secondary winding (410-2) having a first terminal (T1) and a second terminal (T2). The switched mode power supply also has a primary side circuit (Q1, Q2, C1) arranged to generate voltage pulses and thereby to drive the primary winding (410-1) of the transformer (410), and a secondary side circuit comprising a rectification circuit connected to the secondary winding (410-2) at the first and second terminals (T1, T2). The rectification circuit is arranged such that during a forward phase of operation of the switched mode power supply, in which the primary winding (410-1) is driven by the primary side circuit to magnetize, and store energy in, the transformer core (410-3), a current induced to flow in the secondary winding (410-2) from the second terminal (T2) to the first terminal (T1) is output by the rectification circuit. The rectification circuit is further arranged such that during a fly-back phase of operation of the switched mode power supply, in which the magnetization of the transformer core (410-3) is reset, a current induced to flow in the secondary winding from the first terminal (T1) to the second terminal (T2) of the secondary winding (410-2) is output by the rectification circuit so that energy stored in the transformer (410) during the forward phase of operation is output by the rectification circuit. |
| US09559596B2 |
Ultra-low power converter
An AC to DC converter system is disclosed in which a conversion circuit for converting an AC input signal to a DC output signal is operably coupled with a communication circuit designed for sensing output indicative of the presence or absence of a load at the DC output. The system is designed so that the conversion circuit operates in an inactive standby state when there is no load, and in an active state for supplying DC power when a load is present. The system is configured to operate using ultra-low power. |
| US09559594B2 |
Dead-time optimization of resonant inverters
The present disclosure is directed to an electrosurgical generator including a resonant inverter having an H-bridge and a tank. A sensor array measures at least one property of the tank. A pulse width modulation (PWM) controller outputs a first PWM timing signal and a second PWM timing signal to the H-bridge. The PWM controller controls a dead-time between the first PWM timing signal and the second PWM timing signal based on the at least one property measured by the sensor array. |
| US09559593B2 |
Synchronous rectification converter and control method of synchronous rectification converter
A synchronous rectification converter includes: a first switching element coupled between a inductor and an input terminal; a second switching element coupled between the inductor and the input terminal; a capacitive element coupled between the other end of the inductor and the other end of the input terminal; a control circuit detects voltages of the inductor and the capacitive element; a current inversion detection circuit detects inversion of a direction in which a current supplied from the second switching element to the inductor flows and outputs an inversion signal; a delay circuit delays the inversion signal and outputs a delay inversion signal; a synchronous rectification reset circuit that changes the control signal; a load detector detects reduction of an output current supplied from a connection node of the inductor and the capacitive element; and a delay control circuit generates a delay control signal. |
| US09559592B2 |
Synchronous rectifier timer for discontinuous mode DC/DC converter
A DC-DC converter (100) includes a switching transistor (M0) connecting an input power terminal (VIN) to an inductor (114) that is also connected to an output power terminal (VOUT), a synchronous rectification transistor (M1) connected to a junction node (113) between the inductor (114) and the switching transistor (M0), and a synchronous rectifier control circuit (200) with an integration capacitor (226) having a voltage that is charged and discharged by first and second current sources (210, 220) to track the charging and discharging of the inductor current, thereby generating a synchronous rectifier control signal (SR) that is applied to the synchronous rectification transistor to discharge the inductor current to zero. |
| US09559590B2 |
Methods and apparatus for a power supply
Methods and apparatus for a power supply according various aspects of the present invention operate in conjunction with a voltage converter for converting an input voltage to an output voltage. For example, the converter may comprise an output controller configured to generate a control signal, a power mode controller, and an integrated power stage. The power stage may include a multiple switch segments coupled in parallel between the input voltage and the output, and a driver circuit responsive to the output controller and the power mode controller and connected to the switch segments. The driver circuit controls the switch segments according to the control signal to activate the switch segments in the switch circuit. The driver circuit also disables one or more of the switch segments according to the power mode signal to permit reduced power delivery and demand states. |
| US09559589B2 |
High efficiency switching boost converter with reduced inductor current ripple
A voltage or current regulated power converter is presented. The power converter is configured to derive electrical power at an output voltage Vout at an output of the power converter from electrical power at an input voltage Vin at an input of the power converter, wherein the output voltage Vout is greater than or equal to the input voltage Vin. The power converter comprises an inductor, a plurality of capacitors and a plurality of switches. The input and output unit are coupled via an intermediate point, wherein the output unit comprises a first output or second output arrangement, and wherein the input unit comprises a first input or a second input arrangement. The power converter comprises a controller configured to control the plurality of switches such that a commutation cycle of the power converter comprises a plurality of different operation phases. |
| US09559587B2 |
High voltage DC/DC converter with master/slave output stage
The present document relates to DC/DC converters with a modular structure for providing different levels of output currents. A power converter configured to convert electrical power at an input voltage into electrical power at an output voltage is described. The power converter comprises inverter stages with half bridges comprising a high side switches and low side switches which are arranged in series between the input voltage and a reference voltage; and with high side drivers for providing drive signals for the high side switches, subject to a high side control signals at a drive voltage level. In addition, the power converter comprises a level shifting unit configured to convert a high side control signal at a logic voltage level into the high side control signal at the drive voltage level for driving the high side switches. |
| US09559584B2 |
Electric circuit of a switchable current source
An electric circuit of a switchable current source (10) comprises an input path (IP) comprising a first resistor (R1) and a controllable current source (CS) to provide a changeable current (Itrim) and an output current path (OP) including a controllable output driver (MN), a second resistor (R2) and an output terminal (LDR_PIN). A sensing voltage (VSENSE) is tapped at the output current path (OP) and is fed back to a regulator circuit (RC) by a feedback path (FP). The regulator circuit (RC) is connectable to the input path (IP) and the output path (OP) and provides an output signal (Vout2) to control the output current driver (MN). The switchable current source (10) enables to provide an output current (ILDR) at the output terminal (LDR_PIN) in dependence on the first and second resistor (R1, R2) and the changeable current (Itrim). |
| US09559582B2 |
Switching power supply circuit
According to an embodiment, a switching power supply circuit includes a comparison circuit and an operation control circuit. The comparison circuit operates intermittently in response to an operation control signal. The comparison circuit compares a feedback voltage based on the output voltage with a reference voltage to generate a comparison result signal representing a result of comparison. The operation control circuit generates the operation control signal based on the clock signal and the comparison result signal. The operation control circuit generates an operation control signal synchronous with the clock signal, if the comparison result signal is at the first level. |
| US09559581B2 |
Single phase bi-directional AC-DC converter with reduced passive components size and common mode electro-magnetic interference
A bidirectional AC-DC converter is presented with reduced passive component size and common mode electro-magnetic interference. The converter includes an improved input stage formed by two coupled differential inductors, two coupled common and differential inductors, one differential capacitor and two common mode capacitors. With this input structure, the volume, weight and cost of the input stage can be reduced greatly. Additionally, the input current ripple and common mode electro-magnetic interference can be greatly attenuated, so lower switching frequency can be adopted to achieve higher efficiency. |
| US09559580B2 |
Electric motor drive apparatus having function for detecting welding of electromagnetic contactor
An electric motor drive apparatus includes: an AC/DC converter converting AC into DC by the switching of multiple power devices; a control circuit performing PWM switching control of the multiple power devices; a current detecting circuit that detects input current from the AC power supply to the AC/DC converter; an electromagnetic contactor connecting or cutting off power from the AC power supply to the AC converter; and a DC link unit including a smoothing capacitor for smoothing DC voltage, and is constructed such that the control circuit determines that the electromagnetic contactor has been welded when input current is detected in a condition where with the DC link unit having been charged, the electromagnetic contactor is turned off to cut off the power from the AC power supply to the AC/DC converter and the multiple power devices are controlled by PWM switching in accordance with the switching commands. |
| US09559577B2 |
Flux focusing magnetic gear assembly using ferrite magnets or the like
The present invention relates generally to a flux focusing magnetic gear assembly using ferrite magnets or the like. The present invention also relates generally to a flux focusing magnetic gear assembly using ferrite magnets or the like that incorporates an outer stator assembly that converts a variable input to a constant output. The present invention further relates generally to an axially aligned flux focusing magnetic gear assembly using ferrite magnets or the like. The improved flux focusing magnetic gear assemblies of the present invention find applicability in traction, wind, and ocean power generation, among other applications. |
| US09559571B2 |
Methods and system for disassembling a machine
A system and methods for disassembling a rotary machine are provided. The rotary machine includes a casing having a plurality of arcuate channels. The system includes a reaction bridge that is configured to couple to the casing of the rotary machine such that the reaction bridge is moveable along a length of the casing. The reaction bridge includes a front support and a rear support that is substantially parallel to the front support. Each of the supports includes a first leg, a second leg, and a support beam extending therebetween. A force device including an actuator and an engaging rod extending therefrom is coupled to the reaction bridge. The force device is configured to apply a force substantially tangentially to a segment positioned in one of the casing arcuate channels. |
| US09559570B2 |
Electrical machine
An integrated starter generator device comprising a housing, a stator and a rotor contained within the housing, the device further comprising control electronics operable to configure the device as either a starter or generator and contained entirely within the housing. The device may include a high current terminal having brass and rubber bonded together. The rubber forms both a sealing and an insulating function. |
| US09559569B2 |
Arrangement for cooling an electric machine with a layer of thermally conducting and electrically insulating material
An assembly for a gas turbine engine includes a S/G having a rotatable shaft, a main machine, a PMG, and an exciter wherein at least one of the main machine, PMG, and exciter includes a rotor mounted to the shaft and having multiple rotor poles, a stator having multiple stator poles and at least one of the rotor poles and stator poles being formed by a core with a post and wire wound about the post to form a winding, with the winding having at least one end turn, and a layer to increase cooling capabilities of a portion of at least one of the stator and the rotor. |
| US09559568B2 |
Apparatus for road vehicles
An apparatus for road vehicles includes a sealed housing (07) which mounts the shafts (11 & 12) in bearings (10). Closed chain or belt loops (13) are driven by sprockets or pulleys (29) which are supported on the shafts (11 & 12) by one direction clutch bearings (09) such that the shafts (11 & 12) can only transmit power in a single direction (15). A multiple array of active elements (14) are activated by the vehicle wheels and have suitable means or geometry such that they transmit force to cause displacement of the chains or belts (13) and drive a generator (06) when activated but slip in the opposite return direction independently and without further effect to the chains or belts (13). A gearbox (28) may be used to change the shafts orientations. A multiple of chain or belt loops (13) are mounted to the shafts (11 & 12) at a suitable spacing in a direction perpendicular to the vehicle travel direction (04). The active elements (14) have means to bias them to return to their non-activated position after activation. The active elements (14) may operate further active elements having a means of one direction transmission of force to cause the chains or belts (13) to displace. |
| US09559561B2 |
Mounting base for motor/generator
A motor or generator assembly including a motor or generator machine and mounting structure supporting the machine on an appliance is provided. The machine presents an axially extending, radially outermost circumferential face and a pair of axially spaced apart, radially projecting axial margins. The mounting structure includes a pair of at least substantially radially extending plates and a base configured for connection to the appliance. The plates extend at least in part adjacent respective ones of the axial margins and at least in part define a machine-receiving space therebetween. The machine is mounted on the brackets so as to be positioned at least in part in the machine-receiving space. The base is positioned at least substantially radially outside the circumferential face of the machine and presents a pair of axially spaced apart side faces, with each of the plates being secured against a respective one of the side faces. |
| US09559560B2 |
Transverse flux electrical machine stator phases assembly
A modular stator adapted to be used in a transverse flux electrical machine (TFEM) includes a plurality of phase modules comprising respective halves sized and designed to receive therein a plurality of cores about a rotational axis. The phase modules are adapted to be assembled together to produce a multi-phase stator and disassembled to replace or maintain a phase module. The phase modules are configured to be angularly shifted from one another to produce a multi-phase TFEM. A TFEM phase assembly and a kit of phases components sized and designed to assemble a multi-phase stator are also encompassed by the present application. |
| US09559559B2 |
Transverse flux electrical machine stator with stator skew and assembly thereof
A stator adapted to be used in a transverse flux electrical machine (TFEM) includes a plurality of phases comprising respective halves sized and designed to receive therein a plurality of cores about a rotational axis. The halves can be separated in angular portions sized and designed to be assembled together and further locate cores therein in respective predetermined positions. A TFEM phase assembly and a kit of phases components sized and designed to assemble a stator are also encompassed by the present application. |
| US09559555B2 |
Rotor and motor
A rotor includes: a circular rotor core; and a plurality of θ magnets. The θ magnets are contained in a magnet holding sections such that the same magnetic pole of one magnet as that of another magnet adjacent to said one magnet faces the same magnet pole of the adjacent magnet in circumferential directions of the rotor core. Given that the number of magnetic poles of the rotor is denoted by P, the maximum outside diameter of the rotor core is denoted by Dr [mm], and the thickness of the plate-like magnet in a circumferential direction of the rotor core is denoted by Lm [mm], the following inequality (2) is satisfied: 0.665×10−4×P2−0.28×10−2×P+0.577×10−1<(Lm/Dr)<3.38×10−4×P2−1.86×10−2×P+3.36×10−1 (2). |
| US09559552B2 |
Coaxial cable and connector with capacitive coupling
A connector for a plurality of coaxial cables includes: a conductive common base with a contact surface; a plurality of conductive contact pads embedded in the common base, each of the plurality of contact pads having a contact surface; and a plurality of dielectric pads embedded in the common base, each of the dielectric pads surrounding a respective contact pad to isolate the respective contact pad from the common base. |
| US09559547B2 |
User indication of compatible wireless charging area
In some example embodiments, there may be provided a method, which may include detecting a presence of an object at least proximate to a first wireless power transmitter; determining whether the object is compatible with a first wireless power protocol of the first wireless power transmitter; and providing an indication representative of a location of a second wireless power transmitter, when the determining indicates the object is incompatible with the first wireless power protocol of the first wireless power transmitter. Related systems, methods, and articles of manufacture are also disclosed. |
| US09559545B2 |
Automated charging
An automated charging device detects a presence of a power-consuming device. The automated charging device may determine whether the power-consuming device is in need of recharging by determining a status of a power level of the power-consuming device. In response to determining that the power-consuming device is due for recharging, the automated charging device may direct a wireless power source to the power-consuming device without user intervention and/or instruction. The automated charging device may detect a location of the power-consuming device and use the detected location to appropriately direct the wireless power source to the power-consuming device. |
| US09559540B2 |
Mobile terminal with a rechargeable battery and method for discharging the rechargeable battery
A method for discharging a rechargeable battery of a mobile terminal is described, wherein the terminal has a processor system. The method comprises the steps of determining a charge status of the rechargeable battery, comparing the charge status with a threshold value and, if the charge status exceeds the threshold value, discharging the rechargeable battery by increasing the energy consumption of the processor system. A computer program product for executing the process, a mobile terminal and a motor vehicle which comprises the described mobile terminal, are moreover described. |
| US09559537B2 |
Guidance light for mobile device
The invention is directed to activating a guidance light for a mobile device. The guidance light is located proximate to connector, such that activation of the guidance light serves to help a user guide a charging wire into the connector, especially during less than ideal lighting conditions. Specific embodiments of the invention provide for determining, at the mobile occurrence of a trigger and, in response to determining the trigger event activating the guidance light. |
| US09559534B2 |
Data cable for fast charging
A data cable for fast charging comprises: a cable for transmitting data and charging; a first connection unit which is disposed on one end of the cable so as to be connected to a power source; a second connection unit which is disposed on the other end of the cable so as to be connected to a mobile terminal; and a mode switching circuit which enables mode switching between a data transmission mode and a fast charging mode, wherein the mode switching circuit comprises: a terminal switching logic which applies an input voltage of the first connection unit; divided resistances; a switch for the mode switching between the data transmission mode and the fast charging mode; and an analog switching logic which responds to the switch for the mode switching. |
| US09559531B2 |
Universal system for charging at least one portable device
A universal system for recharging at least one portable appliance, the dedication of which is being capable from a device (4) of suiting any portable appliance version with at least one adapter (6) which may be specific in all or part of the relevant portable appliance. The system, in its preferred alternative embodiments, allows simultaneous or sequential recharging of a plurality of portable appliances. With the system it is further possible to save electric energy in a stand-by mode and the risks of fire and electrocution in the case of any dysfunction are reduced as compared with the solutions of the state of the art. |
| US09559530B2 |
Fault tolerant wireless battery area network for a smart battery management system
A Wireless battery area network permits the wirelessly monitoring and controlling of individual batteries within large-scale battery applications. The system automatically configures its wireless nodes in the network and provides for the linking of a plurality of batteries (10) to a master battery management unit (M-BMU) (100) by establishing a wireless battery area network within a battery pack that include slave units (S-BMU) (210). The entire system may also be controlled by a top level battery management unit (T-BMU) (510). The system and method allows for the monitoring of voltage, current, temperature, or impedance of individual batteries and for the balancing or bypassing of a battery. A communications controller allows for optimization of wireless communications parameters and beamforming. |
| US09559527B2 |
Discharging circuit, image forming apparatus having the discharging circuit, and power supply unit
A discharge circuit, an image forming apparatus having the discharge circuit, and a power-supply unit are disclosed to minimize a standby power generated in a standby mode and improve a discharging speed of a capacitor charged with electricity by the AC power in a power off mode. The discharge circuit connected between AC power input lines receiving an AC power includes a first resistor and a first switch element connected in series between the AC power lines, and a second resistor and a second switch element which are connected in series between the AC power lines, turn off the first switching element upon receiving an electric current during supply of the AC power, and turn on the first switching element in response to cutoff of the AC power to discharge the first capacitor. |
| US09559525B2 |
Network monitoring device
A network monitoring device for a supply network and a method for actuating a switch unit are disclosed, wherein the switch unit can control the energy supply of a consumer connected to a supply network. In order to prevent an overload of the supply network or of parts thereof, according to an embodiment of the invention, the network monitoring device includes a communication device, wherein the network monitoring device can receive a switch command for a switch unit via the communication device and transmit same to the switch unit, wherein the network monitoring device is designed to determine a network utilization of the supply network by way of a measurement device and, in dependence on the determined network utilization,; to influence a received switch command for the switch unit, which would lead to increased energy consumption on the supply network. |
| US09559524B2 |
Feed system, feed unit, and electronic unit
A feed system has a first electronic unit, a second electronic unit, and a feed unit. The first electronic unit and the feed unit are separated. The feed unit transmits power to a power reception section of the second electronic unit based upon result information of a first authentication between the first electronic unit and the second electronic unit. The feed unit performs a second authentication on the second electronic unit in conjunction with power transmission. |
| US09559523B2 |
Multilevel electronic power converter
The invention is a multilevel electronic DC/AC or AC/DC power converter for n output voltage levels with a positive branch (POS) with a positive DC voltage terminal (2), a negative branch (NEG) with a negative DC voltage terminal (1), and an AC voltage terminal (3) connected to the positive branch (POS) and to the negative branch (NEG), DC bus capacitors (4) interconnected between positive (2) and negative (1) DC voltage terminals and an intermediate DC voltage terminal (5) connected between the two DC bus capacitors (4); a plurality of first external controlled semiconductors (6) and second external controlled semiconductors (7) and, at least, one high-current DC capacitor (11), at least two high-frequency and low-current capacitors (12) and one intermediate controlled semiconductor (8) connected between the intermediate DC voltage terminal (5) and an intermediate terminal (10) of an internal branch (INT) connected in parallel with each high-current DC capacitor (11). |
| US09559518B2 |
System and method of solar module biasing
A system and method for biasing one or more arrays of photovoltaic modules. An array of biasing photovoltaic modules is coupled to an array of photovoltaic modules to be biased. The coupling may be via a current regulating device. The array of biasing photovoltaic modules and current regulating device provide a forward bias current to the array of photovoltaic modules to be biased. The array of biasing photovoltaic modules includes more photovoltaic modules than the array of photovoltaic modules to be biased. |
| US09559517B2 |
Encapsulation of components and a low energy circuit for hazardous locations
Embodiments of the disclosure provide an encapsulated compressor overload, an encapsulated compressor relay start, an encapsulated head pressure control switch and a wiring diagram for a circuit for air conditioning units which prevent gases from being ignited by means of encapsulating sparking components, use of solid-state switching devices, and/or wiring circuits in such a way that open contacts do not contain enough energy to produce a spark capable of igniting the atmosphere. |
| US09559512B1 |
Programmable rise time controlled load switch and integrated temperature sensor system with interface bus
A fully integrated circuit configuration that can be used to control the slew rate of a PMOS load switch is described. The circuit also integrates a multichannel temperature sensing system which can be coupled to an external set of temperature sensors, preferably non-linear PTC (positive temperature coefficient) sensors to provide both current inrush control as well as thermal overload protection. A communications data bus, such as an I2C bus, is employed to provide temperature feedback for the system controller so that the system can better control the temperature of its own environment. |
| US09559510B2 |
Signalling device for a transmission line
The invention relates to a signalling device (1) for an aerial transmission line (2) comprising two signalling elements (3, 4) which are configured to be mounted one against the other around a conductor portion (2) of the transmission line, in which at least one of the two signalling elements (3, 4) comprises at least partially an outer signalling coating in the context of air safety, which device is characterized in that the two signalling elements (3, 4) are at least partially electrically conductive and at least one of the two signalling elements (3, 4) comprises a clamping means (5) which is configured to clamp the conductor portion (2) of the transmission line. The invention also relates to a method for assembling such a device on a high-voltage aerial transmission line. |
| US09559509B2 |
Power supply control device
A power supply control device includes: a control board that is configured to control a voltage of a battery module; and a bus bar module that is configured to electrically connect the control board and the battery module, the control board and the bus bar module are arranged in a stacked manner, and connection terminals of the bus bar module which are connected to the battery module are exposed when viewed from the control board. |
| US09559495B1 |
System and method for optical amplification
An optical amplifier includes a plurality of photon amplifying regions. Each photon amplifying region includes a bottom electrode, an insulating layer formed over the bottom electrode, and having a through hole to the bottom electrode, a semiconductor layer and a top electrode formed over the semiconductor layer, wherein the top and bottom electrodes electrically contact the semiconductor layer. The semiconductor layer is formed over the insulating layer and in the through hole, and has a semiconductor active region in the through hole. The semiconductor active region has a direct electronic band gap with a conduction band edge, and is embedded within a photonic crystal having an electromagnetic band gap having photon energies overlapping the energy of the conduction band edge of the electronic band gap such that spontaneous emission of photons in the semiconductor active region is suppressed. |
| US09559493B2 |
Power monitoring device and transmitter having same
A power monitoring device includes: a silicon support layer being attached to a PCB board; a glass layer disposed above the silicon support layer; at least one sensing element disposed on the glass layer; and at least one metal pad disposed on the glass layer. The sensing element is suspended over a laser element that is attached to the PCB board and configured for sensing light directed thereto that is emitted by the laser element. A cavity is defined in the silicon support layer and configured for accommodating the laser element. A transmitter that includes the power monitoring device is also provided. |
| US09559492B2 |
Laser system with reduced apparent speckle
Laser systems with reduced apparent speckle are provided. The laser systems emit laser light having different mode structures that change within a time period of an integration period of an imaging system used to observe a field of view that is at least in part illuminated by the laser systems. |
| US09559483B2 |
High power parallel fiber arrays
High power parallel fiber arrays for the amplification of high peak power pulses are described. Fiber arrays based on individual fiber amplifiers as well as fiber arrays based on multi-core fibers can be implemented. The optical phase between the individual fiber amplifier elements of the fiber array is measured and controlled using a variety of phase detection and compensation techniques. High power fiber array amplifiers can be used for EUV and X-ray generation as well as pumping of parametric amplifiers. |
| US09559481B2 |
Large aperture uniform-amplification laser module
A large aperture uniform-amplification laser module including a longer, larger diameter crystal bar is disclosed. The laser module includes a ring-shaped pump bar structure, a crystal bar, a glass sleeve, and a structural component. The pump bar structure includes pump blocks composed of a bar, a cooling heat sink, and a cooling pipe. The bar is connected with the heat sink, and a cooling water channel is provided inside of the cooling heat sink. Heat sinks are provided with outlet pipes and an inlet pipes to communicate with water channels, which are connected in series through the cooling pipes to form a ring shape. The bar is close to a center axis of the ring-shaped pump bar structure. The crystal bar is provided in the glass sleeve. A plurality of the ring-shaped pump bar structures are sleeved on the glass sleeve along the length of the glass sleeve. |
| US09559479B2 |
Angled connector for connecting two devices and having a fastening device
Embodiments of the present disclosure include an apparatus and a method for connecting a first device and second device. An apparatus includes an angled connector configured to connect to a first device to a second device, the first device and the second device configured to communicate through signal paths in the connector, the signal paths configured to pass digital data signals, a fastening device configured to secure the angled connector to the first device. |
| US09559475B1 |
Plug assemblies
A plug assembly includes a plug housing, six connector cavities, and a first and a second electrical connector. The plug housing is configured to be positioned in a receptacle assembly. The six connector cavities are defined in the plug housing and radially disposed around a connecting face in compliance with the Society of Automotive Engineers (“SAE”) J2863 standard. The first electrical connector is disposed and positioned with respect to a first connector cavity of the six connector cavities such that a first contact surface of the first electrical connector is contactable within the first connector cavity. The second electrical connector is disposed and positioned with respect to the first connector cavity such that a second contact surface of the second electrical connector is contactable within the first connector cavity and such that the second electrical connector is displaced relative to the first electrical connector and electrically insulated therefrom. |
| US09559472B2 |
Wire arrangement for hand-reachable USB charger related devices
A desktop USB-charger related product has space to receive an AC power-wire, USB-charger wire, or another charging related wire(s). The USB-charger related product is arranged to be installed on a desk top at a hand-reachable distance from a user by attachment means so that there is no need for the user to bend body or knee in order to charge a device using the charger. The USB-charger related product has at least one USB-port that can supply a desired output-current in the range of from 1.0 A to 12 A and 3.5VDC to 8.5VDC by converting input AC power ranging from 110VAC to 250VAC. The USB-charger product may also incorporate at least one additional device such as an AC outlets, sensor, motion sensor, remote control, time display, LEDs, other lights, a power fail device, a smell device, an audio device, a video device, or other electric or electronic devices. |
| US09559471B2 |
Coaxial cable and connector with capacitive coupling
A coaxial cable-connector assembly includes a coaxial cable and a coaxial cable connector. The coaxial cable includes: a central conductor having a connector end; a dielectric layer that overlies the central conductor; and an outer conductor that overlies the dielectric layer having a connector end. The coaxial connector includes: a central conductor extension configured to mate with a mating connector at one end; a first insulative layer interposed between an opposed second end of the central conductor extension and the connector end of the central conductor; an outer conductor extension configured to mate with a mating connector at one end; and a second insulative layer interposed between an opposed second end of the outer conductor extension and the connector end of the outer conductor. This configuration can reduce and/or avoid PIM within the connection of two coaxial connectors. |
| US09559466B2 |
Communications plugs and patch cords with mode conversion control circuitry
Patch cords include a communications cable that has first through eighth conductors that are arranged as four twisted pairs and a plug attached thereto. The plug includes a housing that receives the cable, first through eighth plug contacts, and a printed circuit board that includes first through eighth conductive paths that connect the first through eighth conductors to the respective first through eighth plug contacts. The plug further includes a first crosstalk injection circuit between the second conductive path and the sixth conductive path and a second crosstalk injection circuit between the first conductive path and the sixth conductive path. |
| US09559464B2 |
Positive locking confirmation mechanism for battery contact of electric vehicle
The present invention provides a positive locking confirmation mechanism for a battery contact of an electric vehicle. The positive locking confirmation mechanism uses a terminal bolt with an expansive tail section and judges whether the battery contact is in a positive locking state according to a voltage signal measured by a battery management unit. Before the battery contact is possibly not in the positive locking state, the system notifies the user to check and repair the possibly-loosened contact. Consequently, the problem of losing power or generating electric arc in the battery box will be avoided. |
| US09559463B2 |
Automated tightener for a wet mateable connection assembly
Automated tightener for a wet mateable connection assembly includes a first and a second watertight case, the automated tightener bearing a fixing assembly and including a first and a second sliding portion arranged in a parallel lay, connected together by a push/pull actuator substantially orthogonal thereto, each sliding portion being provided with operable engagers. |
| US09559462B1 |
Port connector securement device
The present invention is a port connector securement device comprising a resting piece, a planar surface, and at least one projection extending from the bottom of the planar surface where the at least one projection rests within at least one slot of an USB port when the port connector securement device is slideably insertable, along with the USB cable into the USB port to ensure that the USB cable cannot be removed upon the port connector securement device insertion into the USB port. |
| US09559460B2 |
Lever-type connector with regulating protrusion on male housing that engages lever on female housing to achieve connection without inclination between male and female housings
A lever-type connector has a female housing (F) with a tubular fitting (13) that includes a lever accommodating portion (15) for accommodating a lever (30) and an inner regulating wall (16) on a side opposite to the lever accommodating portion (15). A male housing (M) has a receptacle (43) with an outer regulating wall (44) facing the inner regulating wall (16), and has a supporting wall (45) facing the lever accommodating portion (15). A cam follower (47) and a regulating protrusion (48) are formed on an outer surface of the supporting wall (45) and can contact the lever (30) by being inserted into an opening (23) of the lever accommodating portion (15). Contact of the regulating protrusion (48) and the lever (30) regulates inclination of the housings (F, M) in the process of rotating the lever (30). |
| US09559459B2 |
Push-lock electrical connector
An inline multi-pin connector includes cylindrical male and female connector members which are electrically connected together by pushing the two members together end-to-end. Either the male or the female connector member has a metal cylinder disposed about its conductive pins or sockets, which are adapted for mutual engagement, while the other connector member is provided with inner threads. The metal cylinder includes plural resilient, spaced arms, or tabs, disposed about its outer periphery and urged radially outward and into engagement with the other member's threads to connect the two connector members. Coaxial seals are disposed between and in contact with the two members as is a compressible O-ring seal. The outer periphery of the inner member's cylindrical insulator is provided with alternating peaks and valleys, while the other member's metal cylinder is provided with inwardly extending resilient arms which are adapted for positioning within a respective facing valley to prevent vibration-induced disconnection. |
| US09559454B2 |
USB memory device
The present invention is a USB memory device comprising a chip-on-board (COB) package having a flash memory and a flash memory controller embedded within, a COB carrier for storing the COB package comprising a tray having a G-shaped block with a pair of side lock bumps, and a metal housing for inserting the COB carrier having a top surface, a bottom surface, a top rectangular cut out, a bottom rectangular cut out, a pair of ends, a pair of side cut outs, a pair of top rectangular openings and a pair of bottom rectangular openings. The COB package, the COB carrier and the metal housing are used to assemble the device by inserting the COB carrier from either of the pair of ends and sliding the COB carrier within the metal housing until the pair of side lock bumps interlocks with the pair of side cut outs. |
| US09559453B1 |
Heavy current mini connector
A heavy current mini connector. The connector has a power terminal assembly and a holder. The power terminal assembly includes a set of resilient contacting tabs. The power terminal assembly and a busbar conductive plate are inserted into each other. The power terminal assembly is conductively connected with a PCB and covered on its outer side with the holder made from steel. The set of resilient contacting tabs is located at the front portion of the power terminal assembly and in contact with the busbar conductive plate. The clamping plates, fastened to the base and provided in the front of the holder, are clamped to the two sides of the power terminal assembly. The base is located on the rear of the holder and is clamped onto the outside of the rear part of the power terminal assembly. The ventilation apertures are situated on the middle of the base. |
| US09559452B1 |
Housing for electrical contact
A housing for an electrical contact that includes a unitary one-piece body that has an internal bore that extends between a front end and an opposite rear end of the unitary one-piece body and is adapted to receive the electrical contact. A front holding member extends into the internal bore from an inner surface of the internal bore, and the front holding member is located at the front end of the one-piece body. A rear holding member extends into the internal bore, and is disposed on the inner surface of the internal bore at the rear end of the one-piece body. A contact retaining member receiving area is defined in the internal bore between the front holding member and the rear holding member for capturing a contact retaining member therebetween. |
| US09559449B2 |
Printed wiring board and connector connecting the wiring board
A printed wiring board (1) includes: a base substrate (3); a plurality of pads (15a, 17a) for electrical connection that are disposed at one surface side of the base substrate (3) and at a connection end portion (13) to be connected with another electronic component (50); wirings (9, 11) that are connected with the pads (15a, 17a); and engageable parts (28, 29) that are formed at side edge parts of the connection end portion (13) and are to be engaged with engagement parts (58) of the other electronic component (50) in the direction of disconnection. The flexible printed wiring board (1) further includes: reinforcement layers (31, 32) that are disposed at the one surface side of the base substrate (3) and at a frontward side with respect to the engageable parts (28, 29) when viewed in the direction of connection with the other electronic component and that are formed integrally with the pads (15a); and insulating layers (34, 35) that cover the reinforcement layers (31, 32). |
| US09559448B2 |
Board edge connector
A board edge connector to which a board is inserted along an oblique direction relative to its fixed posture includes a main body, a plurality of contacts arranged in juxtaposition on the main body along a direction perpendicular to an insertion direction of the board, and a cover member covering the main body. The main body includes a base portion on which the multiple contacts are juxtaposed and a pair of arm portions extending from the base portion along opposed lateral edges of the board which assumes a fixed posture. The cover member includes an attaching portion covering the base portion and a pair of arm members covering lateral faces of the pair of arm portions, the pair of arm members being formed integral with the attaching portion. |
| US09559447B2 |
Mechanical contact retention within an electrical connector
An electrical connector and a method of make the same. The electrical connector includes an insulator housing formed with a plurality of through holes extending from a first surface to a second surface of the insulator housing. A flowable polymeric material is located adjacent at least one retention region in each of the through holes. Contact members are positioned within each of the through holes. Energy and/or pressure is applied to the electrical connector so the flowable polymeric material flows into engagement with retention features on the contact members. The electrical connector is cooled so the flowable polymeric material fuses to the contact members in a retention regions. |
| US09559444B1 |
Quick connection battery terminal
A battery terminal for terminating to a terminal post of a battery. A lever is rotatably mounted to a lever engaging portion and includes an engagement member with a pair of mounting members extending therefrom. The mounting members are spaced apart by a first distance which is greater than a second distance which is the distance that the lever receiving members are spaced from each other. The mounting members are positioned to the outside of the lever receiving members. Camming members extend from the mounting members. The camming members have engaging portions which extend inward from the mounting members. The camming members and the engaging portions have an elastic spring behavior which allows the camming members and the engaging portions to be elastically deformed when the lever is rotated between an open position and a closed position. |
| US09559442B2 |
Sequencer terminal block, sequencer, and sequencer unit
To provide a sequencer terminal block having a terminal connection surface on which a plurality of terminal connection portions, to which terminals can be respectively connected, are arrayed. The sequencer terminal block includes a band attachment portion formed to protrude in a first direction parallel to an array direction of the terminal connection portions. The band attachment portion includes two first legs formed to protrude in the first direction, and a first joining portion that joins ends of the first legs to each other. An area surrounded by an attachment-portion forming surface on which the band attachment portion is formed, the first legs, and the first joining portion becomes an insertion hole into which a banding band can be inserted. |
| US09559435B2 |
Systems, apparatus, and related methods for weather-proofed wire splicings
Disclosed are systems, apparatus and related methods for making weather, fire, or water-proofed wire-to-wire electrical connections. |
| US09559434B2 |
Method for closed-loop tuner in a receiver antenna
Described herein are architectures, platforms and methods for implementing a closed-loop tuner in a receiver circuitry of a portable device. For example, the closed-loop tuner is based upon a configured or an inherent local oscillator (LO) leakage power in the receiver circuitry of the portable device. |
| US09559432B2 |
Antenna control system and multi-frequency shared antenna
A multi-frequency shared antenna comprises a low frequency radiation array and a first high frequency radiation array both of which are disposed on a reflection plate and provided with power by different feeding networks. The first high frequency radiation array comprises a number of high frequency radiation units, at least partial high frequency radiation units are arranged on a same axis which overlaps one of two axes of the low frequency radiation array, in all high frequency radiation units arranged on said axis, at least partial high frequency radiation units are nested with the low frequency radiation units arranged on the same axis, and the orthogonal projection area of these nested high frequency radiation units on the reflection plate falls within the orthogonal projection area of the corresponding low frequency radiation units on the same reflection plate. |
| US09559426B1 |
Frequency selective surfaces
A switchable Frequency Selective Surface (FSS) in which the switchable elements are Plasma-shells. Plasma-shells as described herein allow for control or ‘reconfiguration’ of the FSS electromagnetic (EM) properties. |
| US09559423B2 |
Wideband deformed dipole antenna for LTE and GPS bands
A deformed dipole is suggested with trace elements configured for wideband LTE and GPS operation. The deformed dipole comprises a first dipole conductor disposed on a first surface and first side of the circuit board and a second dipole conductor disposed on an opposite surface and opposite side of the circuit board. |
| US09559419B2 |
Reflector and a multi band antenna
The present invention relates to a reflector for an antenna comprising a first reflector assembly and at least one second reflector assembly, the first reflector assembly having a first reflector structure adapted for a first antenna frequency band f1 and at least one second antenna frequency band f2; the at least one second reflector assembly having a second reflector structure adapted for the first antenna frequency band f1 and at least one third antenna frequency band f3; and wherein the first reflector assembly and the at least one second reflector assembly are electrically coupled so that the first reflector assembly and the at least one second reflector assembly together form a common reflector structure adapted for the first f1, at least one second f2 and at least one third f3 antenna frequency bands. Furthermore, the invention also relates to a multi band antenna comprising at least one such reflector. |
| US09559418B2 |
Phase shifter having dielectric members inserted into a movable support frame
A phase shifter includes dielectric members including facing portions facing a signal line formed on a surface of a substrate and being made of a dielectric material, a supporting member configured to support the dielectric members and receive a moving force for moving the dielectric members in a direction which is parallel to the substrate and crosses the signal line, and a moving mechanism configured to apply the moving force to the supporting member. At least either the dielectric members or the supporting member is provided with a protrusion configured to keep a distance between the facing portions of the dielectric members and the signal line. |
| US09559416B2 |
Accessing LP transponders with CP terminals via wavefront multiplexing techniques
The invention is about a method and apparatus for grouping multiple satellite transponders with both (LP) polarization formats in different frequencies through Wave-Front (WF) Multiplexing (muxing) techniques for ground terminals with incompatible (CP) polarization formats. As a result of this invention, linear polarized (LP) transponders can be accessed and efficiently utilized by circularly polarized (CP) ground terminals and vice versa. This invention consists of conventional ground terminals, a unique organization of space assets, and a unique polarization alignment processor. The applications of wavefront multiplexing techniques to satellite communications offer many potential advantages, including improved flexibility and utility efficiency of existing space assets. Our proposed “Polarization Utility Waveforms” is an entirely new concept in VSAT and Earth Station Antenna diversity. The implementation enables antennas to switch between different polarization formats at the press of a button, and provides teleport operators with greater flexibility in how they manage their assets. |
| US09559412B2 |
Wireless portable electronic device having a conductive body that functions as a radiator
An apparatus, such as a wireless portable electronic device, is provided that includes a body formed of a conductive material. The body defines an internal cavity and an opening. The wireless portable electronic device also includes a ground plane disposed within the internal cavity and electromagnetically coupled to the body. The wireless portable electronic device additionally includes an antenna, such as a loop antenna or a monopole, disposed within the internal cavity and electromagnetically coupled to the body such that the body functions as a radiator. The wireless portable electronic device further includes a three-dimensional ground plane extension disposed within the internal cavity so that at least a part of the three-dimensional ground plane extension overlies the antenna. The three-dimensional ground plane extension is galvanically coupled to the ground plane and electromagnetically coupled to the body. |
| US09559410B2 |
Breakaway mast
A sensor mounting bracket for attachment to a vehicle including a mast configured to support a sensor at a first end, a base pivotably connected to the mast at a second end, a shock absorber attached between the mast and the base, wherein the base is attached to a vehicle and the shock absorber predisposes the mast to either a deployed position or a stowed position. |
| US09559406B2 |
Electronic device with dual clutch barrel cavity antennas
An electronic device has antennas formed from cavity antenna structures. The electronic device may have a metal housing. The metal housing may have an upper housing in which a component such as a display is mounted and a lower housing in which a component such as a keyboard is mounted. Hinges may be used to mount the upper housing to the lower housing for rotation about a rotational axis. Cavity antennas may be formed in a clutch barrel region located between the hinges and running along the rotational axis. A flexible printed circuit may be formed between the cavity antennas. Each cavity antenna may have a first end that is adjacent to one of the hinges and a second end that is adjacent to the flexible printed circuit. Cavity walls for the cavity antennas may be formed from metal housing structures such as metal portions of the lower housing. |
| US09559402B2 |
Combiner including land pattern formed on printed board
The combiner includes a printed board, first and second conductor plates, and first and second conductor parts. The printed board includes a hole passing from a first surface to a second surface opposite to the first surface. The first conductor plate is made of a copper plate and mounted on the first surface of the printed board to close the hole. The second conductor plate is made of a copper plate and mounted on the second surface of the printed board to close the hole. The first conductor part is opposed to the first conductor plate with a predetermined space between the first conductor part and the first conductor plate. The second conductor part is opposed to the second conductor plate with a predetermined space between the second conductor part and the second conductor plate. |
| US09559401B2 |
Printed board and wiring arrangement method
A printed board includes: a transmission line that includes a curved region in which a first signal line and a second signal line are arranged separately from each other and curved, wherein the second signal line is arranged on an inner side of the curved region with respect to the first signal line in the curved region and has a portion extending away from the first signal line on a path arranged to be circuitous and extending partially toward the first signal line in the curved region. |
| US09559399B2 |
Dielectric waveguide input/output structure and dielectric waveguide duplexer using the same
The present invention provides a dielectric waveguide input/output structure for connecting to a coaxial connector a plurality of dielectric waveguide resonators each comprising an approximately parallelepiped-shaped dielectric block, wherein the plurality of dielectric waveguide resonators include a first dielectric waveguide resonator and a second dielectric waveguide resonator each having an exterior coated with an electrically conductive film, except for a coupling window, wherein each of the coupling window is formed with a probe composed of an electrically conductive film, the probe having one end connected to a feeding point, and the other end connected to the electrically conductive film, and wherein the first dielectric waveguide resonator and the second dielectric waveguide resonator are arranged in such a manner that the one side surfaces thereof are located in opposed relation to each other. |
| US09559398B2 |
Multi-mode filter
A multi-mode cavity filter comprises: a dielectric resonator; a coupling structure for at least one of coupling input signals to the dielectric resonator and extracting filtered output signals from the dielectric resonator; a covering of conductive material around the dielectric resonator and comprising an aperture; and a printed circuit board structure having at least one ground plane layer arranged over said aperture and electrically coupled to the covering of conductive material. |
| US09559395B2 |
Lithium/air battery with variable volume insertion material
In accordance with one embodiment, an electrochemical cell includes a negative electrode including a form of lithium, a positive electrode spaced apart from the negative electrode and including an electron conducting matrix and a lithium insertion material which exhibits a volume change when lithium is inserted, a separator positioned between the negative electrode and the positive electrode; and an electrolyte including a salt, wherein Li2O2 or Li2O is formed as a discharge product. |
| US09559390B2 |
Battery degradation accumulation methods
A vehicle includes a traction battery subject to alternating cycling and storage modes and a controller. The controller is programmed to calculate an accumulated degradation for the traction battery based on a degradation profile for the traction battery. The degradation profile defines degradation accumulated over time and may differ based on the mode and temperature. The initial degradation value includes the accumulated degradation for the present mode and at least a portion of the accumulated degradation for the other mode. Degradation is then accumulated according to the degradation profile starting from the initial degradation value. The amount of accumulated degradation from the other mode that is included may vary based on the mode and the accumulated degradation. |
| US09559388B2 |
Electrochemical systems configured to harvest heat energy
Electrochemical systems for harvesting heat energy, and associated electrochemical cells and methods, are generally described. The electrochemical cells can be configured, in certain cases, such that at least a portion of the regeneration of the first electrochemically active material is driven by a change in temperature of the electrochemical cell. The electrochemical cells can be configured to include a first electrochemically active material and a second electrochemically active material, and, in some cases, the absolute value of the difference between the first thermogalvanic coefficient of the first electrochemically active material and the second thermogalvanic coefficient of the second electrochemically active material is at least about 0.5 millivolts/Kelvin. |
| US09559385B2 |
Nickel iron battery employing an untreated polyolefin separator with a surfactant in the electrolyte
Provided is a nickel-iron battery. The battery comprises a positive nickel electrode, an iron negative electrode, an electrolyte comprising a surfactant, and a non-polar separator. In one embodiment, the non-polar separator is comprised of a polyolefin, and the surfactant comprises a zwitterionic surfactant. |
| US09559383B2 |
Sealed lithium secondary battery
The present invention provides a sealed lithium secondary battery in which redox shuttle reactions of an aromatic compound that is an overcharge inhibitor are inhibited, and the aromatic compound decomposes appropriately, and a desired amount of gas can be generated more stably than in conventional instances, even in high-temperature environments. In the sealed lithium secondary battery (100), an electrode assembly (80) and an electrolyte are accommodated in a battery case (50) that is provided with a current interrupt device (30). The electrolyte comprises a compound that is capable of suppressing drops in viscosity of the electrolyte as a result of a rise in temperature in a temperature region up to 100° C., and an aromatic compound capable of generating hydrogen gas when a predetermined battery voltage is exceeded. |
| US09559382B2 |
Nonaqueous electrolyte secondary battery
A nonaqueous electrolyte secondary battery includes a flat winding electrode assembly including a positive electrode substrate exposed portion on one end and a negative electrode substrate exposed portion on the other end. The winding numbers of the positive and the negative electrode substrate exposed portions are each 30 or more. The positive and negative electrode substrate exposed portions each have an outermost surface welded and connected with a positive and a negative electrode collectors, respectively. A nonaqueous electrolyte used to fabricate the battery contains a lithium salt having an oxalate complex as an anion. At the welded connection portions, all of the layers of the positive electrode substrate exposed portion are melted to be welded and connected to the positive electrode collector, and all of the layers of the negative electrode substrate exposed portion are melted to be welded and connected to the negative electrode collector. |
| US09559378B2 |
Fuel cell stack case with pressure plate
A fuel cell that includes a cell stack in which a plurality of unit cells are stacked, a case that houses the cell stack, and a pressure plate that is placed in the case at a position between an end of the cell stack in the stacking direction and the case. The case has a first opening through which a pressing member that presses the pressure plate in the stacking direction from outside the case is brought into contact with the pressure plate, and a fixing portion that fixes the pressure plate in place with the cell stack compressed in the stacking direction. |
| US09559373B2 |
Formation of hydrophilic polymer membranes using a bronsted base
A method of forming a hydrophilic polymer is disclosed. The method can include: reacting a monomer comprising an acid group with a Bronsted base to form an ionic liquid; polymerizing the ionic liquid with at least one other monomer; and converting the ionic liquid back to the acid group after polymerization. Also disclosed are hydrophilic polymers and membrane electrode assemblies formed using the above method. |
| US09559372B2 |
High temperature membrane electrode assembly with high power density and corresponding method of making
A membrane electrode assembly (MEA) with enhanced current density or power density is fabricated using high temperature (HT) proton exchange membrane (PEM). The MEA can be utilized in high temperature PEM fuel cell applications. More specifically, the MEA is modified with the addition of one or more of selected materials to its catalyst layer to enhance the rates of the fuel cell reactions and thus attain dramatic increases of the power output of the MEA in the fuel cell. The MEA has application to other electro-chemical devices, including an electrolyzer, a compressor, or a generator, purifier, and concentrator of hydrogen and oxygen using HT PEM MEAs. |
| US09559371B2 |
Fuel cell system
To provide a fuel cell system that is advantageous for maintaining an S/C value in an appropriate region even when a rotational speed of the water pump is abnormal with respect to a target rotational speed region during a power generation operation of a fuel cell. When the rotational speed of the water pump is abnormal with respect to the target rotational speed region during the power generation operation of the fuel cell, the control unit repeats a short time increase and a short time decrease of the S/C value in a reforming reaction, by alternately repeating an increase in a short time (ΔT increase, within 10 seconds) and a decrease in a short time (ΔT decrease, within 10 seconds) of the rotational speed of the water pump with respect to an abnormal rotational speed, while continuing the power generation operation of the fuel cell, thereby averaging the S/C value. |
| US09559370B2 |
Lithium air battery system
Provided is a lithium air battery system, and more particularly, a lithium air battery system capable of stably and continuously operating a lithium air battery by recovering an electrolytic solution evaporated in the lithium air battery and injecting the recovered electrolytic solution into the lithium air battery. |
| US09559369B2 |
Fuel cell supply system
A supply system of the anode circuit of a fuel cell (1) comprising: a primary fuel tank (2) intended to supply the anode circuit during an operating phase of the fuel cell, a secondary fuel tank (4) intended to supply the anode circuit when the fuel cell is shut down, the primary and secondary tanks are installed so that the secondary tank is recharged with fuel from the primary tank during an operating phase of the fuel cell, and the system further comprises a permeable membrane (6) installed between the secondary fuel tank and the anode circuit of a fuel cell. Also disclosed is a fuel cell system comprising a fuel cell and the described supply system. |
| US09559363B2 |
Method for preparing catalyst layer by in-situ sol-gel reaction of tetraethoxysilane in Nafion ionomer solution
Provided are a method for preparing a catalyst layer by an in-situ sol-gel reaction of tetraethoxysilane, and a fuel cell including the catalyst layer prepared thereby. Addition of silica mitigates specific adsorption of sulfonate groups contained in a Nafion ionomer on a Pt catalyst layer in a high-voltage region where the role of a catalyst predominates, resulting in improvement of ORR performance. |
| US09559361B2 |
Modified guaran binder for lithium ion batteries and methods for producing the same
The presently disclosed and/or claimed inventive concept(s) relates generally to a composition of a slurry for use in preparation of a lithium ion battery. The slurry comprises a binder composition comprising a modified guaran for use in battery electrodes and methods of preparing such. The presently disclosed and/or claimed inventive concept(s) also relates to compositions and methods of making electrodes, either anodes and/or cathodes, with the binder composition comprising the modified guaran. |
| US09559359B2 |
Lithium secondary battery and positive electrode for the battery
The lithium secondary battery positive electrode provided by the present invention has a positive electrode collector and a positive active material layer formed on the collector. The positive active material layer is composed of a matrix phase containing at least one particulate positive active material and at least one binder, and an aggregate phase dispersed in the matrix phase, constituted by aggregation of at least one particulate positive active material and containing substantially no binder. |
| US09559357B2 |
Method for preparing a titanium and niobium mixed oxide by solvothermal treatment; electrode and lithium accumulator comprising said mixed oxide
A method of preparing a titanium and niobium mixed oxide including the steps of: preparing a titanium and niobium mixed oxide in amorphous form by a solvothermal treatment of at least one titanium precursor and of at least one niobium precursor, mechanically crushing the titanium and niobium mixed oxide obtained at the end of the solvothermal treatment and calcinating the mixed oxide obtained after crushing. |
| US09559356B2 |
Li4Ti5O12, Li(4-α)ZαTi5O12 or Li4ZβTi(5-β)O12 particles, processes for obtaining same and use as electrochemical generators
Synthesis process for new particles of Li4Ti5O12, Li(4-α)ZαTi5O12 or Li4ZβTi(5-β)O12, preferably having a spinel structure, wherein β is greater than 0 and less than or equal to 0.5 (preferably having a spinel structure), α representing a number greater than zero and less than or equal to 0.33, Z representing a source of at least one metal, preferably chosen from the group made up of Mg, Nb, Al, Zr, Ni, Co. These particles coated with a layer of carbon notably exhibit electrochemical properties that are particularly interesting as components of anodes and/or cathodes in electrochemical generators. |
| US09559355B2 |
Particulate anode materials and methods for their preparation
Method for preparing a particulate material including particles of an element of group IVa, an oxide thereof or an alloy thereof, the method including: (a) dry grinding particles from an ingot of an element of group IVa, an oxide thereof or an alloy thereof to obtain micrometer size particles; and (b) wet grinding the micrometer particles dispersed in a solvent carrier to obtain nanometer size particles having a size between 10 to 100 nanometers, optionally a stabilizing agent is added during or after the wet grinding. Method can include further steps of (c) drying the nanometer size particles, (d) mixing the nanometer size particles with a carbon precursor; and (e) pyrolyzing the mixture, thereby forming a coat of conductive carbon on at least part of the surface of the particles. The particulate material can be used in fabrication of an anode in an electrochemical cell or electrochemical storage energy apparatus. |
| US09559351B2 |
Nickel composite hydroxide particles and nonaqueous electrolyte secondary battery
A method for producing nickel composite hydroxide particles may include: a first step of producing nuclei including primary particles by controlling the pH of an aqueous solution for nucleation, the aqueous solution for nucleation containing a metal compound having an atomic ratio of metals corresponding to an atomic ratio of metals in the nickel composite hydroxide particles and substantially not containing a metal complex ion-forming agent; and a second step of forming, on an outer surface of each of the nuclei, an outer shell portion including platy primary particles larger than primary particles of the nuclei by controlling the pH of an aqueous solution for particle growth containing the nuclei obtained in the nucleation step. |
| US09559347B2 |
Negative electrode terminal for battery and method for producing negative electrode terminal for battery
A negative electrode terminal for a battery in which a first metal layer and a second metal layer hardly separate from each other is provided by inhibiting an intermetallic compound from being formed between the first metal layer and the second metal layer. This negative electrode terminal (8) for a battery is composed of a clad material formed by bonding a first metal layer (80), made of Al, including a first region connected with a battery terminal connecting plate and an adjacent second region on the same surface side as the first region and a second metal layer (81), made of Ni, connected with battery negative electrodes, while the second metal layer is arranged to be stacked on the first metal layer in the second region of the first metal layer. |
| US09559346B2 |
Traction battery electrical joint
An exemplary assembly includes an array plate of a traction battery and an insert held by the array plate. The insert is in electrical communication with a bus bar of the traction battery. Another exemplary assembly includes an array plate of a traction battery and a fastening insert recessed within the array plate. The fastening insert is more electrically conductive than the array plate. |
| US09559344B2 |
Lithium battery
The present invention relates to a lithium battery and, more particularly, to a lithium battery, in which the structure of a battery module contained in the lithium battery is simplified, thus reducing the size of the entire lithium battery, and which includes a connector by which two or more lithium batteries are mechanically coupled to each other so that in response to a required amount of power, an appropriate number of lithium batteries can be easily connected to each other. |
| US09559342B2 |
Battery terminal cover
A cap configured to cover a terminal of a battery includes a base and a top having a plug and a cavity. The cavity is configured to receive the terminal and the plug is configured to retain the top on the terminal. A tether has a first end fixed to the base and a second end fixed to the top and connects the top to the base. The base is configured to retain the top to the terminal when the top is both connected to the terminal and separate from the terminal. |
| US09559340B2 |
Battery and motor vehicle comprising said battery
A battery includes at least one battery module that has several battery cells arranged next to each other on a support plate. The battery module is arranged with the support plate on a base plate of the battery or on a base plate of a lower unit of the battery. The support plate and the base plate are fixed together by at least one fixing system that includes at least two fixing elements engaging in each other. The first fixing element is arranged on the battery module and the second fixing element is arranged on the base plate. A motor vehicle includes the battery. |
| US09559328B2 |
Organic light-emitting display apparatus and method of manufacturing the same
Provided is an organic light-emitting display apparatus including a substrate; a first electrode formed on the substrate; an emission layer formed on the first electrode; and a second electrode formed on the emission layer, wherein the first electrode includes a first layer including silver (Ag); and a second layer disposed on the first layer and comprising oxide of non-silver metal. |
| US09559326B2 |
Light emitting element
A light emitting element is disclosed, including a substrate layer, a first metal layer and a second metal layer stacked sequentially on the substrate layer, and an organic material layer disposed between the first metal layer and the second metal layer. The first metal layer includes a first metal portion and a second metal portion that cover a surface of the substrate layer, and an opening portion disposed between the first metal portion and the second metal portion and exposes a portion of the surface. The organic material layer emits light having a wavelength within a first range. A first coupling generated between the first metal portion and the second metal layer shifts the light from the first range to a second range. A second coupling generated between the second metal portion and the second metal layer shifts the light from the first range to a third range. |
| US09559325B2 |
Light-emitting device having stacked light-emitting layers
Disclosed is a light-emitting element with a microcavity structure which is capable of amplifying a plurality of wavelengths to give emission of a desired color. The light-emitting element includes a pair of electrodes and an EL layer having a light-emitting substance interposed between the pair of electrodes. One of the pair of electrodes gives a reflective surface and the other electrode gives a semi-reflective surface. The light-emitting element is arranged so that the emission of the light-emitting substance covers at least two wavelengths λ and an optical path length L between the reflective surface and the semi-reflective surface satisfies an equation L=nλ/2 where n is an integer greater than or equal to 2. |
| US09559321B2 |
Metal complexes for use as dopants and other uses
The invention relates to electrochemical devices comprising complexes of cobalt comprising at least one ligand with a 5- or six membered, N-containing heteroring. The complex are useful as p- and n-dopants, as over of electrochemical devices, in particular in organic semiconductors. The complexes are further useful as over-discharge prevention and overvoltage protection agents. |
| US09559310B2 |
Compound with electron injection and/or electron transport capabilities and organic light-emitting device including the same
A compound represented by Formula 1 below and an organic light-emitting device including the compound are provided: Substituents in Formula 1 are the same as defined in the specification. |
| US09559308B1 |
Method for growing carbon nanotubes
A method of forming carbon nanotubes (CNTs) is disclosed. The method includes dispersing a plurality of substantially semiconductor pure carbon nanotube (CNT) seeds on a substrate to provide a seeded substrate, ozonating the seeded substrate to remove defects on end faces of the plurality of substantially semiconductor pure CNT seeds, and growing carbon extensions on the end faces of the plurality of substantially semiconductor pure CNTs seeds to form a plurality of substantially pure CNTs. |
| US09559307B2 |
Polymer and organic electronic device
A composition comprising a polymer and a phosphorescent material wherein the polymer comprises repeat units of formula (I): wherein A is a heteroaryl group containing a nitrogen atom, and A may be unusubstituted or substituted with one or more substituents; R1 in each occurrence is independently a substituent; and n is 0, 1, 2, 3 or 4. |
| US09559304B2 |
Forming of optoelectronic devices, particularly of inverted-type OPV cells
This forming involves a composition including: poly(3,4-ethylenedioxythiophene) or PEDOT; polystyrene sulfonate or PSS; a compound (A) having formula: with 0 |
| US09559303B2 |
Conjugated polymers
The invention relates to novel polymers containing repeating units based on benzo[1,2-d;4,3-d′]bisthiazole, monomers and methods for their preparation, their use as semiconductors in organic electronic (OE) devices, especially in organic photovoltaic (OPV) devices, and to OE and OPV devices comprising these polymers. |
| US09559301B2 |
Methods of forming memory device constructions, methods of forming memory cells, and methods of forming semiconductor constructions
Memory device constructions include a first column line extending parallel to a second column line, the first column line being above the second column line; a row line above the second column line and extending perpendicular to the first column line and the second column line; memory material disposed to be selectively and reversibly configured in one of two or more different resistive states; a first diode configured to conduct a first current between the first column line and the row line via the memory material; and a second diode configured to conduct a second current between the second column line and the row line via the memory material. In some embodiments, the first diode is a Schottky diode having a semiconductor anode and a metal cathode and the second diode is a Schottky diode having a metal anode and a semiconductor cathode. |
| US09559295B2 |
Nano multilayer film, field effect tube, sensor, random accessory memory and preparation method
A nano multilayer film of electrical field modulation type, a field effect transistor of electrical field modulation type, an electrical field sensor of switch type, and a random access memory of electrical field drive type can obtain an electro-resistance effect in an electrical field modulation multilayer film at room temperature. The nano multilayer film includes in succession from bottom to top a bottom layer, a substrate, a bottom layer, a functional layer, a buffer layer, an insulation layer, a conductive layer, and a cap layer. The buffer layer and the insulation layer can be selectively added as required when the conductive layer is made of a magnetic metal. The effect of influencing and changing the conductivity of the metal layer and thus adjusting the change in the resistance of the devices can obtain different resistance states corresponding to different electrical fields and achieving an electro-resistance effect. |
| US09559289B2 |
Polymeric piezoelectric material and process for producing the same
A polymeric piezoelectric material is provided that includes an aliphatic polyester (A) with a weight-average molecular weight of from 50,000 to 1,000,000 and having optical activity, and a stabilizing agent (B) with a weight-average molecular weight of from 200 to 60,000 having at least one kind of functional group selected from the group consisting of a carbodiimide group, an epoxy group and an isocyanate group, wherein the crystallinity of the material obtained by a DSC method is from 20% to 80%, a content of the stabilizing agent (B) is from 0.01 part by mass to 10 parts by mass with respect to 100 parts by mass of the aliphatic polyester (A), and internal haze with respect to visible light is 50% or less, as well as a process for producing the same. |
| US09559286B2 |
Positioning device
A positioning device includes a positioning element that is situated movably in a first direction and a second direction, the first and the second directions being opposed to one another, and a first piezoelectric actuator and a second piezoelectric actuator, the first piezoelectric actuator moving the positioning element in the first direction and the second piezoelectric actuator moving the positioning element in the second direction. |
| US09559284B2 |
Silicided nanowires for nanobridge weak links
Silicided nanowires as nanobridges in Josephson junctions. A superconducting silicided nanowire is used as a weak-link bridge in a Josephson junction, and a fabrication process is employed to produce silicided nanowires that includes patterning two junction banks and a rough nanowire from a silicon substrate, reshaping the nanowire through hydrogen annealing, and siliciding the nanowire by introduction of a metal into the nanowire structure. |
| US09559282B2 |
Thermoelectric generator, thermoelectric generation method, electrical signal detecting device, and electrical signal detecting method
A thermoelectric generation method using a thermoelectric generator includes: placing a thermoelectric generator in a temperature-changing atmosphere; drawing to outside a current that is generated due to a temperature difference between first and second support members when the temperature of the second support member is higher than that of the first support member, and that flows from a second thermoelectric conversion member to a first thermoelectric conversion member, using first and second output sections as a positive terminal and a negative terminal, respectively; and drawing to outside a current that is generated due to a temperature difference between the first and second support members when the temperature of the first support member is higher than that of the second support member, and that flows from a fourth thermoelectric conversion member to a third thermoelectric conversion member, using third and fourth output sections as a positive terminal and a negative terminal, respectively. |
| US09559275B2 |
Light emitting device package and light unit having the same
Disclosed is a light emitting device package. The light emitting device is a package body including a first recess which is provided with a bottom face and a plurality of inner walls surrounding the bottom face the plurality of inner walls including a first inner wall and a second inner wall, which are opposing walls; a lead frame exposed at the bottom face of the package body, the lead frame including a bottom frame and a reflector exposed along one of the first inner wall and the second inner wall; a light emitting element provided on the lead frame; and a transparent material provided in the package body to cover the light emitting element. A material of the reflector is a same as a material of the bottom frame of the lead frame. |
| US09559272B2 |
Efficient lighting system with wide color range
Broadband solid state light sources include remote phosphor LED(s), short-wavelength direct emitting LED(s), and long-wavelength direct emitting LED(s). A diffuse or clear cover member covers these LEDs. Each remote phosphor LED includes an LED, a phosphor layer, and a dichroic reflector. The light sources can provide a broadband output light over a wide color range, and can do so efficiently while energizing a high percentage or proportion of the total number of LEDs in the system. The broadband output may for example exhibit a color difference of at least 0.2 in CIE chromaticity units, and/or a correlated color temperature difference of at least 4000 or 5000 Kelvin, while energizing more than half, or at least 60%, or at least 70%, of the total number of LEDs. Numbers of LEDs can be replaced with effective numbers of LEDs if LEDs of substantially different sizes are included in the light source. |
| US09559269B2 |
Outdoor luminaire
An outdoor luminaire comprising a blue LED chip having a maximum peak at a wavelength of 420-480 nm and a phosphor layer disposed forward of the LED chip in its emission direction is provided. The phosphor layer comprises a phosphor of the formula: Lu3Al5O12:Ce3+ which is activated with up to 1 mol % of Ce relative to Lu, the phosphor being dispersed in a resin. In scotopic and mesopic vision conditions, the luminaire produces illumination affording brighter lighting, higher visual perception and brightness over a broader area. |
| US09559266B2 |
Lighting apparatus including an optoelectronic component
The invention relates to an illumination device (1) specifically a packaged LED (2), which is embedded in a casing body leaving the bottom side of the LED (2) exposed; on the bottom side, a contacting element (7) is vacuum deposited onto the LED (2), which contacting element protrudes laterally above the LED (2) and allows on a macroscopic level for an electric contacting of the LED (2), namely by connection of flat surfaces, such as welding. |
| US09559261B2 |
Nitride underlayer and fabrication method thereof
A nitride layer with embedded hole structure can be used for fabricating GaN-based LED of high external quantum efficiency through epitaxial growth. The approaches can have advantages such as reducing the complexity chip process for forming hole structure, reducing impacts from the chip process on chip reliability, effective reduction of hole structure size and increase of device stability, crush resistance, and reliability. A fabrication method of an underlayer structure with embedded micro-hole structure is also provided. |
| US09559259B2 |
Light-emitting device and manufacturing method thereof
An LED manufacturing method includes steps of: providing a substrate including a first surface; forming a first portion of a first semiconductor layer on the first surface in a first atmosphere including a first carrier gas; and forming a second portion of the first semiconductor layer on the first portion in a second atmosphere including a second carrier gas; wherein a plurality of first cavities is formed on a surface of the first portion during forming the first portion; and wherein the plurality of first cavities is transformed to a plurality of second cavities during forming the second portion, and one of the second cavities includes a first inclined surface and a second inclined surface above the first inclined surface. |
| US09559257B2 |
Light emitting device and lighting system
A light emitting device may include a first conductive type semiconductor layer, an active layer including a quantum well and a quantum wall on the first conductive type semiconductor layer, an undoped last barrier layer on the active layer; an AlxInyGa(1-x-y)N (0≦x≦1, 0≦y≦1)-based layer on the undoped last barrier layer; and a second conductive type semiconductor layer on the AlxInyGa(1-x-y)N-based layer. The undoped last barrier layer may be provided between the AlxInyGa(1-x-y)N (0≦x≦1, 0≦y≦1)-based layer and a last quantum well which is closest to the second conductive type semiconductor layer among the quantum well and may include a first Inp1Ga1-p1N (0 |
| US09559252B2 |
Substrate removal process for high light extraction LEDs
A method for fabricating light emitting diode (LEDs) comprises providing a plurality of LEDs on a substrate wafer, each of which has an n-type and p-type layer of Group-III nitride material formed on a SiC substrate with the n-type layer sandwiched between the substrate and p-type layer. A conductive carrier is provided having a lateral surface to hold the LEDs. The LEDs are flip-chip mounted on the lateral surface of the conductive carrier. The SiC substrate is removed from the LEDs such that the n-type layer is the top-most layer. A respective contact is deposited on the n-type layer of each of the LEDs and the carrier is separated into portions such that each of the LEDs is separated from the others, with each of the LEDs mounted to a respective portion of said carrier. |
| US09559248B2 |
Laser soldering systems and methods for joining crystalline silicon solar batteries
The disclosure includes a laser soldering method of connecting crystalline silicon solar batteries. Methods can include placing conductive soldering strips and crystalline silicon solar batteries on a lower press plate and aligning the conductive soldering strips on metal electrodes of crystalline silicon solar batteries. Methods can also include placing an upper press plate on the conductive soldering strips and the crystalline silicon solar batteries and vacuuming between the upper and lower press plates such that absolute pressure between the upper and lower press plates is less than atmospheric pressure. Methods can also include laser soldering the conductive soldering strips and the crystalline silicon solar batteries. |
| US09559246B2 |
Solar cell emitter region fabrication using silicon nano-particles
Methods of fabricating solar cell emitter regions using silicon nano-particles and the resulting solar cells are described. In an example, a method of fabricating an emitter region of a solar cell includes forming a region of doped silicon nano-particles above a dielectric layer disposed above a surface of a substrate of the solar cell. A layer of silicon is formed on the region of doped silicon nano-particles. At least a portion of the layer of silicon is mixed with at least a portion of the region of doped silicon nano-particles to form a doped polycrystalline silicon layer disposed on the dielectric layer. |
| US09559244B2 |
CMOS image sensors and methods for forming the same
A method includes forming a first implantation mask comprising a first opening, implanting a first portion of a semiconductor substrate through the first opening to form a first doped region, forming a second implantation mask comprising a second opening, and implanting a second portion of the semiconductor substrate to form a second doped region. The first portion of the semiconductor substrate is encircled by the second portion of the semiconductor substrate. A surface layer of the semiconductor substrate is implanted to form a third doped region of an opposite conductivity type than the first and the second doped regions. The third doped region forms a diode with the first and the second doped regions. |
| US09559240B1 |
Nano-pillar-based biosensing device
In one example, a device includes a trench formed in a substrate. The trench includes a first end and a second end that are non-collinear. A first plurality of semiconductor pillars is positioned near the first end of the trench and includes integrated light sources. A second plurality of semiconductor pillars is positioned near the second end of the trench and includes integrated photodetectors. |
| US09559236B2 |
Solar cell fabricated by simplified deposition process
Methods of fabricating solar cells using simplified deposition processes, and the resulting solar cells, are described. In an example, a method of fabricating a solar cell involves loading a template substrate into a deposition chamber and, without removing the template substrate from the deposition chamber, performing a deposition method. The deposition method involves forming a first silicon layer on the template substrate, the first silicon layer of a first conductivity type. The deposition method also involves forming a second silicon layer on the first silicon layer, the second silicon layer of the first conductivity type. The deposition method also involves forming a third silicon layer above the second silicon layer, the third silicon layer of a second conductivity type. The deposition method also involves forming a solid state doping layer on the third silicon layer, the solid state doping layer of the first conductivity type. |
| US09559235B2 |
Photoelectric conversion device
The present invention provides a photoelectric conversion device. Specifically, the photoelectric conversion device has a structure in which a substrate including a photoelectric conversion element provided at the bottom and a substrate including a photoelectric conversion element provided at the side are secured in a brace form by a light-dividing device. This structure divides incident light using the light-dividing device into a plurality of wavelength bands, and causes the divided light to fall onto the photoelectric conversion elements provided at the bottom and side, thereby making it possible to provide a photoelectric conversion device which is capable of generating a lame amount of electric power. In addition, the light-dividing device distributes pressures and impacts applied to the substrates at the bottom and side, thus making it possible to provide a photoelectric conversion device which has resistance to pressures and impacts. |
| US09559227B2 |
Nanostructure and optical device including the nanostructure
Provided are a nanostructure and an optical device including the nanostructure. The nanostructure is formed on a two-dimensional material layer such as graphene and includes nanopatterns having different shapes. The nanopattern may include a first nanopattern and a second nanopattern and may be spherical; cube-shaped; or poly-pyramid-shaped, including a triangular pyramid shape; or polygonal pillar-shaped. |
| US09559226B2 |
Solid-state imaging apparatus and electronic apparatus
A solid-state imaging apparatus includes a phase difference detection pixel including a photoelectric conversion section that is formed on a semiconductor substrate and configured to photoelectrically convert incident light, a waveguide configured to guide the incident light to the photoelectric conversion section, and a light-shielding section that is formed in vicinity of an opening of the waveguide and configured to shield a part of the incident light that enters the waveguide. |
| US09559221B2 |
Solar cell production method, and solar cell produced by same production method
This solar cell production method involves productively forming an antireflection film comprising silicon nitride, said antireflection film having an excellent passivation effect. In an embodiment, a remote plasma CVD is used to form a first silicon nitride film on a semiconductor substrate (102) using the plasma flow from a first plasma chamber (111), then to form a second silicon nitride film, which has a different composition than the first silicon nitride film, using the plasma flow from a second plasma chamber (112), into which ammonia gas and silane gas have been introduced at a different flow ratio than that of the first plasma chamber (111). The plasma chambers (111, 112) have excitation parts (111a, 112a) that excite the ammonia gas, and activation reaction parts (111b, 112b) and a flow controller (113). |
| US09559220B2 |
Solar cell
A solar cell is discussed. The solar cell includes a substrate of a first conductive type, an emitter region which is positioned at a front surface of the substrate and has a second conductive type different from the first conductive type, a front passivation region including a plurality of layers which are sequentially positioned on the emitter region, a back passivation region which is positioned on a back surface opposite the front surface of the substrate and includes three layers, a plurality of front electrodes which pass through the front passivation region and are connected to the emitter region, and at least one back electrode which passes through the back passivation region and is connected to the substrate. |
| US09559218B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device comprises a semiconductor layer including a mesa structure and a peripheral surface extending around the mesa structure, the mesa structure having a plateau shape with an upper surface and a side surface; a Schottky electrode forming a Schottky junction with the upper surface; an insulating film extending from the peripheral surface, across the side surface, and onto the Schottky electrode, the insulating film having an opening formed on the Schottky electrode; and a wiring electrode electrically connected to the Schottky electrode inside the opening, the wiring electrode extending from inside of the opening, across a portion of the insulating film formed on the side surface, and onto another portion of the insulating film formed on the peripheral surface. |
| US09559209B2 |
Field effect transistors and methods of forming same
Semiconductor devices and methods of forming the same are provided. A first source/drain layer is formed over a substrate. A channel layer is formed over the first source/drain layer. A second source/drain layer is formed over the channel layer. The first source/drain layer, the channel layer, and the second source/drain layer are patterned to form a fin-shaped structure. A gate stack is formed on a sidewall of the fin-shaped structure. The fin-shaped structure is patterned to expose a top surface of the first source/drain layer. |
| US09559205B2 |
Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate and a gate stack covering a portion of the fin structure. The gate stack includes a work function layer and a gate dielectric layer. The semiconductor device structure also includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the gate dielectric layer, and a lower width of the isolation element is greater than an upper width of the isolation element. |
| US09559204B2 |
Strained semiconductor device and method of making the same
In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess. |
| US09559201B2 |
Vertical memory devices, memory arrays, and memory devices
Vertical memory devices comprise vertical transistors in an array region and digit lines extending in a first direction and comprising a source region or a drain region of at least some of the vertical transistors. The vertical memory devices further include word lines extending in a second direction along sidewalls of the vertical transistors and along sidewalls of columns of an oxide material in a word line end region. The wordlines extend closer to an upper surface of the vertical memory device on the sidewalls of the oxide material than on the sidewalls of the vertical transistors. Memory arrays comprising vertical transistors in an array region, digit line, and word lines are disclosed, as are memory devices comprising transistors in an array region, digit lines, and word lines. |
| US09559200B2 |
Method and apparatus for power device with multiple doped regions
A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type. |
| US09559191B2 |
Punch through stopper in bulk finFET device
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure. |
| US09559188B2 |
Trench gate type semiconductor device and method of producing the same
A method of producing a trench gate type MOSFET is provided in which each intersection trench is formed as a two-stage trench structure. A gate trench is backfilled with a mask material and the mask material is then patterned to form a mask used for forming each intersection trench. The intersection trench intersecting the gate trench is provided so as to be deeper than the gate trench. A Schottky electrode is provided in the bottom of each intersection trench 10p. In this manner, there is provided a trench gate type semiconductor device and a method of producing the same, in which: the cell pitch can be reduced even when a wide band gap semiconductor is used as a main semiconductor substrate; good ohmic contacts can be obtained; and an excessive electric field is prevented from being applied to an insulating film in the bottom of each trench. |
| US09559186B2 |
Epitaxially grown stacked contact structure of semiconductor device
The embodiments described above provide mechanisms of forming contact structures with low resistance. A strained material stack with multiple sub-layers is used to lower the Schottky barrier height (SBH) of the conductive layers underneath the contact structures. The strained material stack includes a SiGe main layer, a graded SiG layer, a GeB layer, a Ge layer, and a SiGe top layer. The GeB layer moves the Schottky barrier to an interface between GeB and a metal germanide, which greatly reduces the Schottky barrier height (SBH). The lower SBH, the Ge in the SiGe top layer forms metal germanide and high B concentration in the GeB layer help to reduce the resistance of the conductive layers underneath the contact structures. |
| US09559178B2 |
Non-volatile memory (NVM) cell and device structure integration
A dielectric layer is formed over the substrate in the capacitor region and the memory region and a select gate layer is formed over the dielectric layer. A select gate is formed over the memory region and a plurality of lines of electrodes over the capacitor region from the select gate layer. A charge storage layer is formed over the capacitor region and the memory region including over the select gate and the plurality of lines. A control gate layer is formed over the charge storage layer over the capacitor region and over the memory region. The control gate layer is patterned to form a control gate of a memory cell over the memory region and a first electrode of a capacitor over the capacitor region. The plurality of lines are connected to the capacitor region to form a second electrode of the capacitor. |
| US09559177B2 |
Memory devices and method of fabricating same
A device comprises a control gate structure over a substrate, a memory gate structure over the substrate, wherein a charge storage layer formed between the control gate structure and the memory gate structure, a first spacer along a sidewall of the memory gate structure, a second spacer along a sidewall of the control gate structure, an oxide layer over a top surface of the memory gate structure, a top spacer over the oxide layer, a first drain/source region formed in the substrate and adjacent to the memory gate structure and a second drain/source region formed in the substrate and adjacent to the control gate structure. |
| US09559176B2 |
FinFET conformal junction and abrupt junction with reduced damage method and device
A method of forming a source/drain region with abrupt vertical and conformal junction and the resulting device are disclosed. Embodiments include forming a first mask over a fin of a first polarity FET and source/drain regions of the first polarity FET; forming spacers on opposite sides of a fin of a second polarity FET, the second polarity being opposite the first polarity, on each side of a gate electrode; implanting a first dopant into the fin of the second polarity FET; etching a cavity in the fin of the second polarity FET on each side of the gate electrode; removing the first mask; performing rapid thermal anneal (RTA); epitaxially growing a source/drain region of the second polarity FET in each cavity; forming a second mask over the fin of the first polarity FET and source/drain regions of the first polarity FET; and implanting a second dopant in the source/drain regions of the second polarity FET. |
| US09559175B2 |
Semiconductor device
The parasitic capacitance formed by a gate electrode, a contact, and a side wall is reduced.The gate electrode and the side wall are covered by an insulating layer. The contact passes through the insulating layer and is connected to a diffusion layer. Then, an air gap is located between the side wall and the contact. The air gap faces the contact at the side face on the contact side via the insulating layer. |
| US09559174B2 |
Semiconductor film, transistor, semiconductor device, display device, and electronic appliance
Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed. |
| US09559173B2 |
Nitride semiconductor device using insulating films having different bandgaps to enhance performance
The semiconductor device includes: a channel layer, a barrier layer, a first insulating film, and a second insulating film, each of which is formed above a substrate; a trench that penetrates the second insulating film, the first insulating film, and the barrier layer to reach the middle of the channel layer; and a gate electrode arranged in the trench and over the second insulating film via a gate insulating film. The bandgap of the second insulating film is smaller than that of the first insulating film, and the bandgap of the second insulating film is smaller than that of the gate insulating film GI. Accordingly, a charge (electron) can be accumulated in the second (upper) insulating film, thereby allowing the electric field strength at a corner of the trench to be improved. As a result, a channel is fully formed even at a corner of the trench, thereby allowing an ON-resistance to be reduced and an ON-current to be increased. |
| US09559172B2 |
Semiconductor device and method of manufacturing the same
A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm−3 and not higher than 1×1022 cm−3. |
| US09559171B2 |
Semiconductor device
In order to realize an SJ-MOSFET and an IGBT on a single chip and realize a new arrangement configuration for an SJ-MOSFET section and an IGBT section in a single semiconductor chip, provided is a semiconductor device including a semiconductor substrate; two or more super-junction transistor regions provided on the semiconductor substrate; and one or more IGBT regions that are provided in regions sandwiched by the two or more super-junction transistor regions, in a cross section obtained by cleaving along a pane perpendicular to the semiconductor substrate. |
| US09559170B2 |
Electrostatic discharge protection devices
A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion. |
| US09559167B2 |
Semiconductor component with dynamic behavior
One embodiment provides a semiconductor component including a semiconductor body having a first side and a second side and a drift zone; a first semiconductor zone doped complementarily to the drift zone and adjacent to the drift zone in a direction of the first side; a second semiconductor zone of the same conduction type as the drift zone adjacent to the drift zone in a direction of the second side; at least two trenches arranged in the semiconductor body and extending into the semiconductor body and arranged at a distance from one another; and a field electrode arranged in the at least two trenches adjacent to the drift zone. The at least two trenches are arranged at a distance from the second semiconductor zone in the vertical direction, a distance between the trenches and the second semiconductor zone is greater than 1.5 times the mutual distance between the trenches, and a doping concentration of the drift zone in a section between the trenches and the second semiconductor zone differs by at most 35% from a minimum doping concentration in a section between the trenches. |
| US09559164B2 |
Nanowire transistor device and method for manufacturing nanowire transistor device
A nanowire transistor device includes a substrate, a plurality of nanowires formed on the substrate, and a gate surrounding at least a portion of each nanowire. The nanowires respectively include a first semiconductor core and a second semiconductor core surrounding the first semiconductor core. A lattice constant of the second semiconductor core is different from a lattice constant of the first semiconductor core. |
| US09559158B2 |
Method and apparatus for an integrated capacitor
An integrated capacitor can be fabricated with both electrodes formed by trenches for low resistance. According to one embodiment, the capacitor can comprise a first trench electrode, one or more dielectric layers, and a second trench electrode. The first trench electrode and the second trench electrode can be fabricated in different trenches to improve capacitance density and resistance of the integrated capacitor. |
| US09559157B2 |
Display device
A display device includes a display panel and a flexible printed circuit (FPC) connected to the display panel. The FPC includes a first region and a second region, the second region having greater flexibility than the first region. |
| US09559156B2 |
Organic light emitting diode display
An organic light emitting diode display includes a substrate including a display area and a non-display area, a display unit that is formed in the display area and includes a plurality of subpixels arranged in a matrix form, a main ground line that is positioned at a first side of the non-display area and is formed using the same material as source and drain electrodes included in each subpixel, and an auxiliary ground line that is formed to surround the non-display area, overlaps at least a portion of the main ground line at the first side of the non-display area, is electrically connected to the main ground line, and is formed using the same material as a lower electrode included in each subpixel. |
| US09559154B2 |
Display device keeping a distance between a light emitting layer and a counter substrate uniformly
A display device includes a first substrate, pixel electrodes located in correspondence with pixels above the first substrate, a first partition covering ends of a group of the pixel electrodes, a second partition covering ends of another group of the pixel electrodes, the second partition being lower than the first partition, a solid filler located above the first partition and the second partition, and a second substrate facing the first substrate, the second substrate being away from the first substrate by a distance kept by the first partition, the second partition and the filler. |
| US09559153B2 |
Display device
A display device includes: an organic layer arranged in plural pixels which are arranged in a display area in a matrix; a first electrode that is formed on a surface of the organic layer opposite to a substrate, and transmits a visible light; a second electrode that holds the organic layer in cooperation with the first electrode, and is lower in the transmittance of the visible light, and higher in the reflectance than the first electrode; an insulating layer that holds the second electrode in cooperation with the organic layer, and higher in the transmittance of the visible light, and lower in the reflectance than the second electrode; and a third electrode that holds the insulating layer in cooperation with the second electrode, is formed across adjacent pixels of the plural pixels, and lower in the transmittance of the visible light, and higher in the reflectance than the second electrode. |
| US09559150B2 |
High efficiency LEDs and LED lamps
In various embodiments, lighting systems include an electrically insulating carrier having a plurality of conductive elements disposed thereon and a light-emitting array. The light-emitting array is disposed over the carrier and includes a plurality of light-emitting diodes (LEDs) that are interconnected in parallel in a first direction and interconnected in series in a second direction different from the first direction. |
| US09559148B2 |
Solid-state imaging device and imaging apparatus
A solid-state imaging device includes a plurality of pixel electrodes disposed two-dimensionally, an opposite electrode provided opposite to the pixel electrodes, and an organic layer formed of an organic material and provided between the pixel electrodes and the opposite electrode, in which a protrusion and recess section is formed on a surface of the organic layer on the opposite electrode side, and the protrusion and recess section includes a first protrusion and recess section formed at a position opposite to each pixel electrode and a second protrusion and recess section formed at a position opposite to the space between each pixel electrode. |
| US09559145B2 |
Electronic device and method for fabricating the same
Provided is an electronic device including a semiconductor memory which includes a first region in which a first variable resistance element for storing data is disposed; and a second region in which a reference resistance element for sensing data stored in the first variable resistance element is disposed, and wherein the reference resistance element comprising: a plurality of second variable resistance elements formed of the same material at the same level as the first variable resistance element; a plurality of contacts coupled to each of the second variable resistance elements; and a first pad coupled to part of the contacts which are coupled to one of two adjacent second variable resistance elements and part of the contacts which are coupled to the other of the two adjacent second variable resistance elements for coupling the two adjacent second variable resistance elements with each other. |
| US09559143B2 |
Method and system for providing magnetic junctions including free layers that are cobalt-free
A magnetic junction usable in a magnetic device and a method for providing the magnetic junction are described. The magnetic junction includes a free layer, a nonmagnetic spacer layer, and a reference layer. The free layer includes at least one of Fe and at least one Fe alloy. Furthermore, the free layer excludes Co. The nonmagnetic spacer layer adjoins the free layer. The nonmagnetic spacer layer residing between reference layer and the free layer. The magnetic junction is configured such that the free layer is switchable between a plurality of stable magnetic states when a write current is passed through the magnetic junction. |
| US09559142B2 |
Active matrix display panel with ground tie lines
A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. A ground line is located in the non-pixel area and an array of ground tie lines run between the bank openings in the pixel area and are electrically connected to the ground line in the non-pixel area. |
| US09559134B2 |
Deep trench spacing isolation for complementary metal-oxide-semiconductor (CMOS) image sensors
An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided. |
| US09559133B2 |
Photodetector and image sensor including the same
A photodetector may have a structure including conductive patterns and an intermediate layer interposed between the conductive patterns. A length L of at least one side of the second conductive pattern that overlaps the first conductive pattern and the intermediate layer satisfies the equation L=λ/2neff, wherein the neff is an effective refractive index of a surface plasmon waveguide formed of the first conductive pattern, the intermediate layer, and the second conductive pattern during a surface plasmon resonance. Heat generated in the intermediate layer when the electromagnetic wave having the wavelength λ is incident thereon generates a current variation. |
| US09559129B2 |
Semiconductor device having antenna and method for manufacturing thereof
The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device including the antenna. The invention further provides a semiconductor device with high reliability that is formed by attaching an element formation layer and an antenna, wherein the element formation layer is not damaged due to a structure of the antenna. The semiconductor device includes the element formation layer provided over a substrate and the antenna provided over the element formation layer. The element formation layer and the antenna are electrically connected. The antenna has a base film and a conductive body, wherein at least a part of the conductive body is embedded in the base film. As a method for embedding the conductive body in the base film, a depression is formed in the base film and the conductive body is formed therein. |
| US09559124B2 |
Display panel
A display panel includes a first base substrate that includes an upper surface to which an external light is incident and a lower surface facing the upper surface and includes a plurality of pixel areas and a peripheral area adjacent to the pixel areas when viewed in a plan view, a plurality of pixels disposed on the lower surface of the first base substrate to respectively correspond to the pixel areas, and a black matrix layer disposed between the pixels and the lower surface of the first base substrate to overlap the peripheral area. The black matrix layer includes a low reflection layer disposed on the lower surface of the first base substrate and a light blocking layer disposed on the low reflection layer. |
| US09559120B2 |
Porous silicon relaxation medium for dislocation free CMOS devices
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer outside the first portion and growing an undoped silicon layer on the doped portion and the first portion. The undoped silicon layer becomes tensile-strained. Strain in the undoped silicon layer over the doped portion is relaxed by converting the doped portion to a porous silicon to form a relaxed silicon layer. The porous silicon is converted to an oxide. A SiGe layer is grown and oxidized to convert the relaxed silicon layer to a compressed SiGe layer. Fins are etched in the first portion from the tensile-strained silicon layer and the undoped silicon layer and in the second portion from the compressed SiGe layer. |
| US09559116B2 |
Semiconductor device
A semiconductor device may include an insulating layer provided in one body on a substrate, a first gate electrode and a second gate electrode disposed on the insulating layer, the first and second gate electrodes extending in a first direction parallel to a top surface of the substrate, a first channel structure penetrating the first gate electrode and the insulating layer so as to be connected to the substrate, a second channel structure penetrating the second gate electrode and the insulating layer so as to be connected to the substrate, and a contact penetrating the insulating layer between the first gate electrode and the second gate electrode. The contact may be connected to a common source region formed in the substrate, and the common source region may have a first conductivity type. Further, the first gate electrode and the second gate electrode may be spaced apart from each other in a second direction at the same level from the substrate, wherein the second direction intersects the first direction and is parallel to the top surface of the substrate. |
| US09559114B2 |
Manufacturing method of three-dimensional non-volatile memory device including a selection gate having an L shape
A 3-dimensional (3-D) non-volatile memory device includes a first channel protruding from a substrate, a selection gate formed on sidewalls of the first channel and in an L shape, and a gate insulating layer interposed between the first channel and the selection gate and surrounding the first channel. A method of manufacturing a 3-D non-volatile memory device includes forming first channels protruding from a substrate, forming a first gate insulating layer surrounding the first channels, and forming first selection gates having an L shape on sidewalls of the first channels on which the first gate insulating layers are formed. |
| US09559113B2 |
SSL/GSL gate oxide in 3D vertical channel NAND
A memory device includes an array of strings of memory cells. The device includes a plurality of stacks of conductive strips separated by insulating material, including at least a bottom plane of conductive strips, a plurality of intermediate planes of conductive strips, and a top plane of conductive strips. A plurality of vertical active strips is formed between the plurality of stacks. Charge storage structures are formed in interface regions at cross-points between side surfaces of the conductive strips in the plurality of intermediate planes and the vertical active strips in the plurality of vertical active strips. Gate dielectric, having a different composition than the charge storage structures, is formed in interface regions at cross-points between the vertical active strips and side surfaces of the conductive strips in at least one of the top plane of conductive strips and the bottom plane of conductive strips. |
| US09559112B2 |
Semiconductor devices and methods of fabricating the same
A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts. |
| US09559111B2 |
Three-dimensional semiconductor memory device
A three-dimensional (3D) semiconductor memory device and a method for fabricating the same, the device including insulating layers stacked on a substrate; horizontal structures between the insulating layers, the horizontal structures including gate electrodes, respectively; vertical structures penetrating the insulating layers and the horizontal structures, the vertical structures including semiconductor pillars, respectively; and epitaxial patterns, each of the epitaxial patterns being between the substrate and each of the vertical structures, wherein a minimum width of the epitaxial pattern is less than a width of a corresponding one of the vertical structures. |
| US09559110B2 |
Dense arrays and charge storage devices
There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing. |
| US09559108B2 |
Chip and an electronic device
A method for processing a carrier accordance with various embodiments may include: forming a structure over the carrier, the structure including at least two adjacent structure elements arranged at a first distance between the same; depositing a spacer layer over the structure, wherein the spacer layer may be deposited having a thickness greater than half of the first distance, wherein the spacer layer may include electrically conductive spacer material; removing a portion of the spacer layer, wherein spacer material of the spacer layer may remain in a region between the at least two adjacent structure elements; and electrically contacting the remaining spacer material. |
| US09559106B2 |
Memory cell that prevents charge loss
A memory cell including a substrate, a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The substrate includes a channel region situated between a drain region and a source region. The first dielectric layer is situated over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The second dielectric layer is situated over the floating gate and the control gate is capacitively coupled to the floating gate through the second dielectric layer. A dielectric nitride layer is situated between the floating gate and the second dielectric layer to prevent charge loss from the floating gate to the second dielectric layer. |
| US09559092B2 |
Electronic device including a diode
An electronic device can include a substrate, lower and upper semiconductor layers over the substrate, and a doped region at the interface between the lower and upper semiconductor layers. The doped region can have a conductivity type opposite that of a dopant within the lower semiconductor layer. Within the lower semiconductor layer, the dopant can have a dopant concentration profile that has a relatively steeper portion adjacent to the substrate, another relatively steeper portion adjacent to an interface between the first and second semiconductor layers, and a relatively flatter portion between the relative steeper portions. A diode lies at a pn junction where a second dopant concentration profile of the first doped region intersects the relatively flatter portion of the first dopant concentration profile. The electronic device can be formed using different processes described herein. |
| US09559091B2 |
Method of manufacturing fin diode structure
A method of manufacturing a fin diode structure includes providing a substrate, forming a doped well in said substrate, forming at least one doped region of first conductivity type or at least one doped region of second doped type in said doped well, performing an etching process to said doped region of first conductivity type or said doped region of second conductivity type to form a plurality of fins on said doped region of first conductivity type or on said doped region of second conductivity type, forming shallow trench isolations between said fins, and performing a doping process to said fins to form fins of first conductivity type and fins of second conductivity type. |
| US09559090B2 |
Silicon wafer with a plurality of chip patterns
A silicon wafer includes a plurality of chip patterns arranged parallel to a first direction and a second direction intersecting the first direction, wherein the plurality of chip patterns include one or more patterns arranged in the first direction and the second direction in a straight line, the plurality of chip patterns include a first chip pattern and a second chip pattern adjacent to the first chip pattern, and the second chip pattern is arranged by rotating the first chip pattern at 90 degrees, the plurality of chip patterns are arranged so that an axis in which a cleavage plane of the silicon wafer and a surface arranged with the pattern on the silicon wafer intersect, and the first direction are different, and an angle between the axis and the first direction of the second chip pattern is 90 degrees. |
| US09559089B2 |
Semiconductor arrangement with active drift zone
A semiconductor device arrangement includes a semiconductor layer and at least one series circuit with a first semiconductor device and a plurality of n second semiconductor devices, with n>1. The first semiconductor device has a load path and active device regions integrated in the semiconductor layer. Each second semiconductor device has active device regions integrated in the semiconductor layer and a load path between a first and second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each second semiconductor device has its control terminal connected to the load terminal of one of the other second semiconductor devices. One of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. The arrangement further includes an edge termination structure. |
| US09559088B2 |
Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the same
An apparatus includes a substrate having a land side having a plurality of contact pads and a die side opposite the land side. The apparatus includes a first die and a second die wherein the first die and second die are embedded within the substrate such that the second die is located between the first die and the land side of the substrate. |
| US09559087B2 |
Techniques for packaging multiple device components
Techniques for fabricating multiple device components. Specifically, techniques for fabricating a stacked package comprising at least one I/C module and a multi-chip package. The multi-chip package includes a plurality of integrated circuit dice coupled to a carrier. The dice are encapsulated such that conductive elements are exposed through the encapsulant. The conductive elements are electrically coupled to the chips. The I/C module comprises an interposer having a plurality of integrated circuit dice disposed thereon. The dice of the I/C module are electrically coupled to the interposer via bondwires. The interposer is configured such that vias are aligned with the conductive elements on the multi-chip package. The multi-chip package and I/C module may be fabricated separately and subsequently coupled together to form a stacked package. |
| US09559085B2 |
Method for producing an optoelectronic device and optoelectronic device
A method for producing an optoelectronic device is specified. A housing base body is formed with a self-healing polymer material. A recess is found in the housing base body. The recess is confined by a bottom surface and at least one side wall which are formed at least in places by the plastic material of the base body. An optoelectronic semiconductor chip has a first main surface, a second main surface facing away from the first main surface and at least one side surface connecting the first main surface and the second main surface with each other. The optoelectronic semiconductor chip is placed in the recess, so that the first main surface is brought in contact with the bottom surface and the at least one side surface is brought in contact with the at least one side wall. |
| US09559078B2 |
Electronic component
An electronic component includes an electrically conductive carrier. The electrically conductive carrier includes a carrier surface and a semiconductor chip includes a chip surface. One or both of the carrier surface and the chip surface include a non-planar structure. The chip is attached to the carrier with the chip surface facing towards the carrier surface so that a gap is provided between the chip surface and the carrier surface due to the non-planar structure of one or both of the carrier surface and the first chip surface. The electronic component further includes a first galvanically deposited metallic layer situated in the gap. |
| US09559077B2 |
Die attachment for packaged semiconductor device
A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects. |
| US09559070B2 |
Post-passivation interconnect structure and method of forming same
A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure. |
| US09559060B2 |
Method of forming stacked trench contacts and structures formed thereby
Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate. |
| US09559058B2 |
Semiconductor device and method for manufacturing the same
A semiconductor device includes a semiconductor substrate, an oxygen-containing insulating film disposed above the above-described semiconductor substrate, a concave portion disposed in the above-described insulating film, a copper-containing first film disposed on an inner wall of the above-described concave portion, a copper-containing second film disposed above the above-described first film and filled in the above-described concave portion, and a manganese-containing oxide layer disposed between the above-described first film and the above-described second film. Furthermore, a copper interconnection is formed on the above-described structure by an electroplating method and, subsequently, a short-time heat treatment is conducted at a temperature of 80° C. to 120° C. |
| US09559055B2 |
Semiconductor device
A semiconductor device includes a fuse element that can be cut and removed by laser irradiation. The fuse element has a large width portion having a large sectional area to be irradiated with a laser spot, and two small width portions having a small sectional area connected to opposite sides of the large width portion. Penetration of moisture is suppressed even after cutting of the fuse element since the large width portion is removed by the laser irradiation and only the small width portions having the small sectional area remain as exposed cut surfaces. |
| US09559053B2 |
Compact vertical inductors extending in vertical planes
A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor. |
| US09559051B1 |
Method for manufacturing in a semiconductor device a low resistance via without a bottom liner
A method for depositing a conductor in the via opening electronic structure removes the via bottom liner so that the conductor deposited in the via opening directly contacts the underlying conductive layer. The method includes depositing amorphous silicon over the dielectric layer and the liner layer on the via opening sidewalls and bottom. The amorphous silicon extends substantially over the entire via opening while leaving below a void within the via opening. The amorphous silicon over the via opening and on the via opening bottom and the liner layer on the via opening bottom are anisotropically etched to leave a layer of amorphous silicon over the dielectric layer and the via opening side walls. The amorphous silicon is then removed to form a via opening having a substantially open-bottom liner. The conductor is then deposited in the via opening and contacts the underlying conductive layer. |
| US09559050B2 |
Semiconductor device and manufacturing method thereof
A method for manufacturing a semiconductor device includes forming a first conductor pattern and a second conductor pattern running side by side with each other, including forming a first portion of the first conductor pattern and a second portion of the second conductor pattern by patterning using a first mask, and forming a second portion of the first conductor pattern and a first portion of the second conductor pattern by patterning using a second mask. A first inter-conductor capacity is formed by the first portion of the first conductor pattern and the first portion of the second conductor pattern. A second inter-conductor capacity is formed by the second portion of the first conductor pattern and the second portion of the second conductor pattern. |
| US09559042B2 |
Semiconductor device
A semiconductor device includes an insulating substrate having an insulating plate formed of ceramic and a circuit plate fixed on a main face of the insulating plate; a semiconductor element fixed on the circuit plate; a printed circuit board disposed to face the main face of the insulating plate; a ceramic plate disposed to face the main face of the insulating plate, and arranged at a position away from the main face of the insulating plate further than the printed circuit board; a supporting member fixed to the main face of the insulating plate or to the circuit plate, to fix a position of the ceramic plate; and a resin covering the circuit plate, the semiconductor element, the printed circuit board, and the ceramic plate. |
| US09559040B2 |
Double-sided segmented line architecture in 3D integration
Embodiments of the present invention relate generally to electronic components such as semiconductor wafers and more particularly, to a double-sided three-dimensional (3D) hierarchal architecture scheme for multiple semiconductor wafers using an arrangement of through silicon vias (TSVs) and backside wiring. In an embodiment a first word line architecture may be formed on a front side of an IC chip and connected to a second word line architecture formed on a back side of the IC chip through intra-wafer, TSVs, thereby relocating required wiring to the back side of the IC chip. |
| US09559027B2 |
Semiconductor device and semiconductor module
A semiconductor device includes a housing with a fragile portion. The fragile unit or portion has a resistance to a pressure or a melting point temperature that is lower than other portions of the housing. The semiconductor device further includes a plurality of semiconductor elements disposed inside the housing. Each semiconductor element includes a semiconductor element region having a first surface and a second surface opposite to the first surface. A first electrode is provided on the first surface and a second electrode is provided on the second surface. |
| US09559026B2 |
Semiconductor package having a multi-layered base
A semiconductor package for mounting to a printed circuit board (PCB) includes a semiconductor die in a ceramic case, a conductive base coupled to the semiconductor die at a top surface of the conductive base, where the conductive base includes a first layer having a first coefficient of thermal expansion (CTE), and a second layer having at least one mounting tab and a second CTE. The conductive base is configured to reduce thermal stress in the ceramic case, where the first CTE is equal to or slightly different than a CTE of the ceramic case, the second CTE is greater than the first CTE, and a CTE of the PCB is greater than or equal to the second CTE. The conductive base is configured to electrically couple a power electrode of the semiconductor die to the PCB. |
| US09559018B2 |
Dual channel finFET with relaxed pFET region
Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide. |
| US09559017B2 |
Method of forming shallow trench isolations for a semiconductor device
A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench. |
| US09559015B2 |
Method of forming a conductive line pattern in FinFET semiconductor devices
The present invention provides a formation method of forming, on a substrate, a fin pattern in which a plurality of linear fins are arrayed, the method comprising forming a resist pattern having a line-and-space shape on the substrate, wherein the substrate includes a first active region and a second active region adjacent to each other, and in the forming the resist pattern, the resist pattern is formed on the substrate such that an interval between a first fin and a second fin becomes wider than a pitch of the fins, the first fin being closest to a boundary of the first active region and the second active region out of the fins formed in the first active region, and the second fin being closest to the boundary out of the fins formed in the second active region. |
| US09559014B1 |
Self-aligned punch through stopper liner for bulk FinFET
A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect. |
| US09559013B1 |
Stacked nanowire semiconductor device
A semiconductor device a first epitaxially grown source/drain region comprising a first material arranged on a first fin, a second epitaxially grown source/drain region comprising the first material arranged on the second fin, the second epitaxially grown source/drain region arranged above the first epitaxially grown source/drain region, a third epitaxially grown source/drain region comprising the first material arranged on a second fin, a fourth epitaxially grown source/drain region comprising a second material arranged on the second fin, the fourth epitaxially grown source/drain region arranged above the third epitaxially grown source/drain region, and a gate stack arranged over a channel region of the first fin and a channel region of the second fin. |
| US09559012B1 |
Gallium nitride complementary transistors
A semiconductor device includes a substrate, a III-nitride buffer layer on the substrate, an N-channel transistor including a III-nitride N-channel layer on one portion of the buffer layer, and a III-nitride N-barrier layer for providing electrons on top of the N-channel layer, wherein the N-barrier layer has a wider bandgap than the N-channel layer, a P-channel transistor including a III-nitride P-barrier layer on another portion of the buffer layer for assisting accumulation of holes, a III-nitride P-channel layer on top of the P-barrier layer, wherein the P-barrier layer has a wider bandgap than the P-channel layer, and a III-nitride cap layer doped with P-type dopants on top of the P-channel layer. |
| US09559011B2 |
Mechanisms for forming FinFETs with different fin heights
Methods for forming a semiconductor device are provided. The method includes forming a first fin and a second fin over a substrate and forming a first isolation structures and a second isolation structure adjacent to the substrate. The first fin is partially surrounded by the first isolation structure and a second fin is partially surrounded by the second isolation structure, and the first isolation structure has a dopant concentration higher than that of the second isolation structure. |
| US09559008B2 |
FinFET-based ESD devices and methods for forming the same
A device includes a plurality of STI regions, a plurality of semiconductor strips between the STI regions and parallel to each other, and a plurality of semiconductor fins over the semiconductor strips. A gate stack is disposed over and crossing the plurality of semiconductor fins. A drain epitaxy semiconductor region is disposed on a side of the gate stack and connected to the plurality of semiconductor fins. The drain epitaxy semiconductor region includes a first portion adjoining the semiconductor fins, wherein the first portion forms a continuous region over and aligned to the plurality of semiconductor strips. The drain epitaxy semiconductor region further includes second portions farther away from the gate stack than the first portion. Each of the second portions is over and aligned to one of the semiconductor strips. The second portions are parallel to each other, and are separated from each other by a dielectric material. |
| US09559007B1 |
Plasma etch singulated semiconductor packages and related methods
A method of forming a plurality of semiconductor packages includes providing an array of unsingulated semiconductor packages that are at least partially encapsulated in an encapsulant. The array of unsingulated semiconductor packages may be coupled with a lead frame or a substrate. A first plurality of singulation lines are simultaneously etched in the encapsulant through slits in an etch mask using a plasma etching process and a fixture coupled with the array. A second plurality of parallel singulation lines may also be etched. The first and second pluralities of singulation lines may include substantially straight or arcuate lines. The second plurality of parallel singulation lines may be substantially perpendicular to the first plurality of parallel singulation lines and be formed using the plasma etching process, the fixture, and an etch mask. The formation of singulation lines in the array singulates the array into a plurality of singulated semiconductor packages. |
| US09558999B2 |
Ultra-thin metal wires formed through selective deposition
The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process. |
| US09558994B2 |
Semiconductor devices and methods of fabricating the same
A semiconductor device includes a substrate including a first region and a second region, first conductive patterns disposed on the first region and spaced apart from each other by a first distance, second conductive patterns disposed on the second region and spaced apart from each other by a second distance greater than the first distance, and an interlayer insulating layer disposed between the second conductive patterns and including at least one recess region having a width corresponding to the first distance. |
| US09558992B2 |
Metal wiring of semiconductor device and method for manufacturing the same
A metal wiring for applying a voltage to a semiconductor component of a semiconductor device, the semiconductor device comprising a low voltage applying region adjacent to a high voltage applying region, is provide. The metal wiring includes: an isolator region, a first lower metal layer electrically connected to the semiconductor component, a first upper metal layer configured to be electrically connected to an external power supply, and a plurality of inter-metal dielectric layers deposited between the first lower metal layer and the first upper metal layer, each of the plurality of inter-metal dielectric layers comprising at least one contact plug for providing an electrical connection between the first lower metal layer and the first upper metal layer. |
| US09558988B2 |
Method for filling the trenches of shallow trench isolation (STI) regions
A method for manufacturing a shallow trench isolation (STI) region with a high aspect ratio is provided. A semiconductor substrate is provided with a trench. A first dielectric layer is formed lining the trench. A second dielectric layer is formed filling the trench over the first dielectric layer. In some embodiments, before forming the second dielectric layer, ions are implanted into an implant region of the first dielectric layer that extends along and is limited to a lower region of the trench. In alternative embodiments, after forming the second dielectric layer, an ultraviolet curing process is performed to the second dielectric layer. With the second dielectric layer formed and, in some embodiments, the ultraviolet curing process completed, an annealing process is performed to the second dielectric layer. A semiconductor structure for a STI region is also provided. |
| US09558985B2 |
Vacuum chuck
A vacuum chuck is disclosed for holding and positioning wafers more stably and securely. The vacuum chuck includes a supporting assembly having a receiving groove and at least one first vacuum aperture defined in the receiving groove. A seal unit includes a seal ring bulging to form a vacuum trough. The seal ring is fixed in the receiving groove of the supporting assembly and has at least one second vacuum aperture communicating with the first vacuum aperture. A chuck connector fastened with the supporting assembly has at least one vacuum port and at least one vacuum orifice communicating with the vacuum port. At least one vacuum hose connects the first vacuum aperture, the second vacuum aperture with the vacuum orifice and the vacuum port of the chuck connector for evacuating the air of the vacuum trough to hold and position the wafer on the seal ring and the supporting assembly. |
| US09558980B2 |
Vapor compression refrigeration chuck for ion implanters
Aspects of the present invention relate to ion implantation systems that make use of a vapor compression cooling system. In one embodiment, a thermal controller in the vapor compression system sends refrigeration fluid though a compressor and a condenser according to an ideal vapor compression cycle to help limit or prevent undesired heating of a workpiece during implantation, or to actively cool the workpiece. |
| US09558963B2 |
Plasma reactor with conductive member in reaction chamber for shielding substrate from undesirable irradiation
Placing a conductive member between a plasma chamber in a remote plasma reactor and a substrate to shield the substrate from irradiation of undesirable electromagnetic radiation, ions or electrons. The conductive member blocks the electromagnetic radiation, neutralizes ions and absorbs the electrons. Radicals generated in the plasma chambers flows to the substrate despite the placement of the conductive member. In this way, the substrate is exposed to the radicals whereas damages to the substrate due to electromagnetic radiations, ions or electrons are reduced or removed. |
| US09558962B2 |
Substrate processing method
A method for passivating a surface of a semiconductor substrate with fluorine-based layer to protect the surface against oxidation and allow longer queue times. According to one embodiment, the method includes providing a substrate having an oxidized layer formed thereon, replacing the oxidized layer with a fluorine-based layer, exposing the fluorine-based layer to an oxidizing atmosphere, where the fluorine-based layer protects the substrate against oxidation by the oxidizing atmosphere, and removing the fluorine-based layer from the substrate using a plasma process. According to another embodiment, the method includes providing a passivated substrate in a vacuum processing tool, the passivated substrate having a fluorine-based layer thereon that is effective for protecting the passivated substrate against oxidation by an oxidizing atmosphere, removing the fluorine-based layer from the passivated substrate using a microwave plasma process in the vacuum processing tool, thereby forming a clean substrate, and processing the clean substrate under vacuum conditions. |
| US09558961B2 |
Manufacturing method of semiconductor device
In accordance with an embodiment, a manufacturing method of a semiconductor device includes: respectively forming a first layer and a second layer at the top of a protruding portion and at the bottom of a depressed portion of a treatment target having protrusions/depressions in such a manner that sidewalls of the protruding portion is exposed, supplying a treatment liquid to the treatment target having the first layer and the second layer, bringing a catalyst into contact with or closer to the first layer and thereby increasing the dissolution rate of the first layer in dissolving into the treatment liquid and dissolving the first layer into the treatment liquid, and sequentially dissolving the protruding portion and the second layer into the treatment liquid after the dissolution of the first layer. |
| US09558960B2 |
Substrate processing method, non-transitory storage medium and heating apparatus
A substrate processing method includes a coating step that applies a coating liquid to a substrate having a front surface on which a pattern is formed, thereby forming a coating film on the substrate, a film removing step that heats the substrate to gasify components of the coating film thereby to reduce a thickness of the film, and a film curing step that is performed after or simultaneously with the film removing step and that heats the substrate to cure the coating film through crosslinking reaction. The film removing step is performed under conditions ensuring that an average thickness of the cured coating film is not greater than 80% of an average thickness of the coating film before being subjected to the film removing step. |
| US09558958B2 |
Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation
A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. An insulating layer is formed over the semiconductor wafer. A protective layer is formed over the insulating layer including an edge of the semiconductor die along the saw street. The protective layer covers an entire surface of the semiconductor wafer. Alternatively, an opening is formed in the protective layer over the saw street. The insulating layer has a non-planar surface and the protective layer has a planar surface. The semiconductor wafer is singulated through the protective layer and saw street to separate the semiconductor die while protecting the edge of the semiconductor die. Leading with the protective layer, the semiconductor die is mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier and protective layer are removed. A build-up interconnect structure is formed over the semiconductor die and encapsulant. |
| US09558955B2 |
Formation method of semiconductor device that includes performing hydrogen-containing plasma treatment on metal gate stack
A method for forming a semiconductor device structure is provided. The method includes forming a metal gate stack over a semiconductor substrate. The method also includes performing a hydrogen-containing plasma treatment on the metal gate stack to modify a surface of the metal gate stack. The hydrogen-containing plasma treatment includes exciting a gas mixture including a first hydrogen-containing gas and a second hydrogen-containing gas to generate a hydrogen-containing plasma. |
| US09558952B2 |
Alkaline pickling process
A process for edge isolation or texture smoothing of a substrate, in which a process medium which allows control treatment of limited regions of the substrate is used. The process is therefore particularly suitable for one-sided treatment of substrates. The viscosity of the process medium plays a central role here. Furthermore, an apparatus designed for the process is presented. |
| US09558951B2 |
Trap rich layer with through-silicon-vias in semiconductor devices
An integrated circuit chip is formed with a circuit layer, a trap rich layer and through-semiconductor-vias. The trap rich layer is formed above the circuit layer. The through-semiconductor-vias are also formed above the circuit layer. In some embodiments, the circuit layer is included in a wafer, and the trap rich layer and through-semiconductor-vias are included in another wafer. The two wafers are bonded together after formation of the trap rich layer and through-semiconductor-vias. Additionally, in some embodiments, yet another wafer may also be bonded to the wafer that includes the trap rich layer and through-semiconductor-vias. Furthermore, in some embodiments, another circuit layer may be formed in the wafer that includes the trap rich layer and through-semiconductor-vias. |
| US09558949B2 |
Vertical bit line non-volatile memory systems and methods of fabrication
Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and methods of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. The gates overlie the global bit lines with one or more insulating layers therebetween to provide adequate isolation between the gates and the global bit lines. Processes for fabricating the vertical TFT select devices utilize a gate dielectric and optional dielectric bases to provide isolation between the gates and bit lines. |
| US09558948B1 |
Laser thermal annealing of deep doped region using structured antireflective coating
A semiconductor body having a first surface is provided. A deep doped region of the semiconductor body is formed using masked ion implantation to implant dopant atoms into a discrete region within the semiconductor body. A structured anti-reflective coating region is formed on a portion of the first surface that is aligned with the deep doped region in a lateral direction of the semiconductor body, the lateral direction being parallel to the first surface. A laser thermal anneal of the deep doped region of the semiconductor body is performed through the anti-reflective coating region thereby activating the implanted dopant atoms in the deep doped region. |
| US09558945B2 |
Semiconductor memory device with electrode connecting to circuit chip through memory array chip
According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer. |
| US09558941B2 |
Method of forming oxide thin film and method of fabricating oxide thin film transistor using hydrogen peroxide
Provided are a method of forming an oxide thin film using hydrogen peroxide, and a method of fabricating an oxide thin film transistor using hydrogen peroxide. Embodiments of the present disclosure provide methods of forming an oxide film, including: mixing hydrogen peroxide with a precursor solution in which a precursor material is dissolved in a solvent; applying the precursor solution mixed with the hydrogen peroxide to a substrate; heat treating the substrate. |
| US09558940B2 |
Method and apparatus for forming silicon film
A method of forming a silicon film in grooves formed on a surface of an object to be processed, the method including forming a first silicon film containing impurities so as to embed the first silicon film in the grooves of the object to be processed; doping the impurities in the vicinity of the surface of the first silicon film; expanding opening portions of the grooves by etching the first silicon film thereby forming expanded openings having grooves; and forming a second silicon film so as to embed the second silicon film in the grooves of the expanded openings is provided. |
| US09558937B2 |
Method of manufacturing semiconductor device, substrate processing apparatus, and non-transitory computer-readable recording medium
A method of manufacturing a semiconductor device includes: (a) forming a first film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including: (a-1) supplying a first precursor gas being a fluorine-free inorganic gas containing the metal element to the substrate; and (a-2) supplying a first reactant gas having reducibility to the substrate; (b) forming a second film containing the metal element on the first film by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a second precursor gas containing the metal element and fluorine to the substrate; and (b-2) supplying a second reactant gas having reducibility to the substrate; and (c) forming a film containing the metal element and obtained by the first film and the second film being laminated on the substrate by performing the (a) and (b). |
| US09558920B2 |
System and method for direct fiber-end surface structuring
A fiber-end surface structuring chamber or system having a main body with multiple ports including a fiber-holder port, a process port that is either a stamp/shim holder port or a plasma etching enabler port, an evacuation port, a gas delivery port, and one or more observation ports, where the fiber-end surface structuring system forms structures directly into the end of the fiber to enhance transmission of light over a wide range of wavelengths and increase the laser damage threshold. |
| US09558917B2 |
Adjustable non-dissipative voltage boosting snubber network for achieving large boost voltages
This disclosure describes a non-dissipative snubber circuit configured to boost a voltage applied to a load after the load's impedance rises rapidly. The voltage boost can thereby cause more rapid current ramping after a decrease in power delivery to the load which results from the load impedance rise. In particular, the snubber can comprise a combination of a unidirectional switch, a voltage multiplier, and a current limiter. In some cases, these components can be a diode, voltage doubler, and an inductor, respectively. |
| US09558914B2 |
Bipolar wafer charge monitor system and ion implantation system comprising same
A charge monitor having a Langmuir probe is provided, wherein a positive and negative charge rectifier are operably coupled to the probe and configured to pass only a positive and negative charges therethrough, respectively. A positive current integrator is operably coupled to the positive charge rectifier, wherein the positive current integrator is biased via a positive threshold voltage, and wherein the positive current integrator is configured to output a positive dosage based, at least in part, on the positive threshold voltage. A negative current integrator is operably coupled to the negative charge rectifier, wherein the negative current integrator is biased via a negative threshold voltage, and wherein the negative current integrator is configured to output a negative dosage based, at least in part, on the negative threshold voltage. A positive charge counter and a negative charge counter are configured to respectively receive the output from the positive current integrator and negative current integrator in order to provide a respective cumulative positive charge value and cumulative negative charge value associated with the respective positive charge and negative charge. |
| US09558912B2 |
Ion milling device
The present invention aims at providing an ion milling apparatus for emitting an ion beam to a sample to process the sample and capable of controlling the temperature of the sample with high accuracy regardless of deformation or the like of the sample being irradiated with the ion beam, and proposes an ion milling apparatus including at least one of a shield holding member for supporting a shield for shielding the sample from the ion beam while exposing a part of the sample to the ion beam; a shifting mechanism for shifting a surface of the sample stand in contact with the sample following deformation of the sample during irradiation with the ion beam, the shifting mechanism having a temperature control mechanism for controlling temperature of at least one of the shield holding member and the sample stand; and a sample holding member disposed between the shield and the sample, the sample holding member deforming following deformation of the sample during irradiation with the ion beam, for example. |
| US09558906B2 |
Electrical switch
An electrical switch is disclosed, especially an electrical circuit breaker, including an overcurrent tripping device which, in the event of an overcurrent situation, switches off the flow of current through the switch; and a thermal tripping device which, in the event of a thermal overload, switches off the flow of current through the switch. In at least one embodiment, the overcurrent tripping device includes a first shaft which is disposed such that, in the event of an overcurrent situation, it is rotated from a first position into a second position and thereby indicates the overcurrent situation; and the thermal tripping device includes a second shaft which is disposed such that, it is rotated in the event of a thermal overload and is also rotated as well in the event of a rotation of the first shaft and when rotated initiates a switching-off of the switch. |
| US09558904B2 |
Fuse
A fuse comprises two electric contacts with a contact width, a fuse element disposed between two opposed fuse ends and comprising a first fuse having a minimum-section part with a first width and a first section. The fuse element further comprises at least one second fuse disposed between the first fuse and one of said two fuse ends. The second fuse comprises a narrowed part with a second width smaller than the first width and the contact width and with a second section ranging from 20% to 50% of the first section. |
| US09558901B2 |
Method of manufacturing bus bar
A bus bar forming die (1) includes an upstream-side die block (25) configured to shape an upstream-side fuse-element portion (9) of a bus bar (23), a downstream-side die block (27) configured to shape a downstream-side fuse-element portion (15) of the bus bar (23), and a fixation portion die block (29) configured to shape fixation portions (21) of the bus bar (23). The upstream-side die block (25), the downstream-side die block (27), and the fixation portion die block (29) are configured to shape the bus bar (23) while placed in respective predetermined positions. Each of the upstream-side die block (25), the downstream-side die block (27), and the fixation portion die block (29) is replaceable in accordance with an intended shape of the bus bar (23). |
| US09558899B2 |
Direct-current contactor with additional switching capability for AC loads and a polarity against the preferential current direction
Disclosed is a DC contactor comprising a double break with two contact points, each having a fixed and a movable contact, the movable contacts arranged on a contact bridge. The contactor includes an arc extinguishing device and a blowing device configured to blow a switch arc, which forms at the first contact point when the contact points are being opened, into the arc extinguishing device, when switching takes place in the preferential current direction. A commutating plate is arranged adjacent the movable contact of the first contact point, the contact bridge and the commutating plate being electrically insulated from one another and the commutating plate being potentially connected to the fixed contact of the second contact point, so that, when switching takes place in the preferential current direction, the switch arc forming at the first contact point jumps from the contact bridge to the commutating plate by the blowing device. |
| US09558898B2 |
Magnetic control switch
A contactless control switch that is resistant to influence from external magnetic fields is disclosed. The switch includes a switch housing, a button moveably mounted to the housing that has at least one protrusion formed on an underside thereof, a circuit board mounted to the housing and including at least one magnet sensor, and a magnet holder positioned adjacent each respective magnet sensor, the magnet holder housing a positive field magnet and a negative field magnet therein and being rotatably mounted to the housing. A respective protrusion interacts with the magnet holder responsive to an actuation of the button by a user, so as to position one of the positive field magnet and the negative field magnet proximate to its respective sensor and the other of the positive field magnet and the negative field magnet distal to its respective sensor. |
| US09558895B2 |
Method for preparing carbon nanofiber composite and carbon nanofiber composite prepared thereby
The present invention relates to a method for preparing a carbon nanofiber composite, and a carbon nanofiber composite prepared thereby. The method for preparing a carbon nanofiber composite provided by the present invention has reduced costs and is economical and efficient compared with a convention method for preparing a carbon nanofiber composite. In addition, the carbon nanofiber composite of the present invention can provide remarkable decomposition performance of organic pollutants, and a carbon nanofiber composite prepared by the preparation method of the present invention can be used in an electrode for an electric double-layer supercapacitor, a fuel cell electrode, a filter, a hydrogen storage material, and the like. |
| US09558893B2 |
Power storage device
A power storage device that includes an electrolyte retaining layer between a first internal electrode and a second internal electrode. The electrolyte retaining layer retains an electrolyte. The first internal electrode has a first current collector and a first active material layer. The first active material layer is on a surface of the first current collector, which is closer to the second internal electrode. The second internal electrode has a second current collector and a second active material layer. The second active material layer is on a surface of the second current collector, which is closer to the first internal electrode. At least one of the electrolyte retaining layer, first active material layer, and second active material layer is exposed at the first and second end surfaces of the power storage device. |
| US09558892B1 |
Thin-film electro devices based on derivatized poly (benzo-isimidazobenzophenanthroline) ladder polymers
A method for making electronic devices based on derivatized ladder polymer poly(benzo-isimidazobenzophenanthroline) (BBL) including photovoltaic modules and simple thin film transistors in planar and mechanically flexible and stretchable constructs. |
| US09558880B2 |
Microtechnical component for a magnetic sensor device or a magnetic actuator and production method for a microtechnical component for a magnetic sensor device or a magnetic actuator
A microtechnical component for a magnetic sensor device or a magnetic actuator includes: a magnetic core oriented along an axis; a first drive coil having windings arranged in a first direction of rotation about the magnetic core; a contact, via which a first current flow is created in a first current direction through the first drive coil; and a second drive coil having windings arranged in a second direction of rotation about the magnetic core, the first and second directions of rotation differing from one another. Simultaneously with the first current flow, a second current flow is created via the contact in a second current direction opposite the first current direction through the second drive coil. |
| US09558879B2 |
Teardrop-shaped magnetic core and coil device using same
The present invention provides a teardrop-shaped magnetic core having excellent manufacturing efficiency, a large initial inductance, and stable DC superposition characteristics and a coil device using this teardrop-shaped magnetic core. A teardrop-shaped magnetic core according to the present invention is a magnetic core that is made from a magnetic material and is to be used in a coil device 20, the magnetic core including a first rectilinear portion 11 and a second rectilinear portion 15 that have a straight-line shape and are connected to each other at one end via a bent portion 16 that is bent at a right angle, and a circular arc portion 17 that has a circular arc shape and connects the first rectilinear portion and the second rectilinear portion to each other at the other end. A coil device according to the present invention is configured by winding a wire around the teardrop-shaped magnetic core 10. |
| US09558878B1 |
Multi-stage permanent magnet structure and integrated power inductors
Apparatuses and methods directed to multi-stage permanent magnet and implementations of a permanent magnet on-chip power inductor. Various circuit models, design considerations and simulation results are described. The multi-stage permanent magnet includes layers with uniform or non-uniform magnets used to control the flux distribution. The permanent magnet on-chip power converter for DC-DC switching power converters that may include a top ferrite layer, a spiral winding layer, a permanent magnet layer, a bottom ferrite layer, and a substrate layer. The permanent magnet layer may comprise a multi-stage structure wherein each stage has a decreasing area as compared to an immediate lower stage. A method of manufacturing a Permanent On-Chip Power Inductor (PMOI) is also disclosed. |
| US09558877B2 |
Ferrite ceramic composition, ceramic electronic component, and method for producing ceramic electronic component
A coil conductor and a via electrode placed away from the coil conductor are embedded in a magnetic layer. The magnetic layer is sandwiched between a pair of non-magnetic layers. The coil conductor and the via electrode are formed from a conductive material containing Cu as its main constituent, and the magnetic layer is formed from Ni—Mn—Zn ferrite where the CuO molar content is 5 mol % or less, and (x, y) falls within the range of A (25, 1), B (47, 1), C (47, 7.5), D (45, 7.5), E (45, 10), F (35, 10), G (35, 7.5), and H (25, 7.5) when the molar content x of Fe2O3 and the molar content y of Mn2O3 are represented by (x, y). Thus, insulation properties can be ensured, favorable electrical characteristics can be achieved, and a ceramic electronic component is achieved which is able to be reduced in size. |
| US09558876B2 |
Halbach array of electromagnets with substantially contiguous vertical and horizontal cores
Electromagnetic Halbach array device with substantially contiguous vertical and horizontal cores. The device is equipped with horizontal cores having protrusions which establish substantial contiguity between horizontal and vertical cores. |
| US09558868B2 |
Use of hydrophobic epoxide resin system for encapsulation of a instrument transformer
Disclosed is the use of a curable composition for padding-free encapsulation of instrument transformers comprising (a) a cycloaliphatic epoxy resin, (b) a polyoxyalkylene diglycidylether (c) an OH-terminated polysiloxane, (d) a cyclic polysiloxane and (e) a non-ionic, fluoroaliphatic surface-active reagent, (f) a filler, (g) a hardener selected from anhydrides, (h) a curing accelerator selected from accelerators for anhydride curing of epoxy resins. |
| US09558865B2 |
Cable with resin molded body and method of manufacturing the same
A method of manufacturing a cable with resin molded body, wherein the cable with resin molded body includes a cable and a resin molded body formed by resin molding, wherein the resin molded body includes a main body to cover the tip portion of the cable and a flange integrally molded with the main body, and wherein the flange includes a bolt hole through which a bolt is inserted so as to fix the flange to the attachment object. The method includes molding the resin molded body by injecting a resin into a mold, the mold including a main body-molding portion for molding the main body, a flange-molding portion for molding the flange and a first resin inlet formed behind the flange-molding portion in relation to the main body-molding portion, and injecting the resin through the first resin inlet into the mold during the molding of the resin molded body. |
| US09558862B2 |
Conductive polymer composition, coated article having antistatic film formed from the composition, and patterning process using the composition
The present invention is a conductive polymer composition containing a π-conjugated conductive polymer, a polyanion, and a gemini surfactant. There can be provided a conductive polymer composition that has excellent antistatic performance and excellent application properties, does not adversely affect a resist, and can be suitably used in lithography using electron beam or the like. |
| US09558861B2 |
Block copolymers that disperse nanofillers in water
The invention relates to novel block copolymers that enable a good dispersion of nanofillers in water and also to a dispersion of nanofillers obtained owing to these block copolymers. This dispersion may be used as a transparent electrode in organic solar cells or other photoemitter or photoreceptor devices. |
| US09558859B2 |
Multilayer substrate and method for manufacturing the same
The invention provides a slip layer substrate which can reduce the thermal residual stresses between components induced by their mismatch of thermal expansion, thus greatly improve the reliability of electronic packages. The slip layer substrate comprises: a base material; a first metallization layer formed on the base material; a first diffusion barrier layer formed on the first metallization layer; a slip layer formed on the first diffusion barrier layer; a second diffusion barrier layer formed on the slip layer; and a second metallization layer formed on the second diffusion barrier layer. |
| US09558858B2 |
System and method for imaging a sample with a laser sustained plasma illumination output
The inspection of a sample with VUV light from a laser sustained plasma includes generating pumping illumination including a first selected wavelength, or range of wavelength, containing a volume of gas suitable for plasma generation, generating broadband radiation including a second selected wavelength, or range of wavelengths, by forming a plasma within the volume of gas by focusing the pumping illumination into the volume of gas, illuminating a surface of a sample with the broadband radiation emitted from the plasma via an illumination pathway, collecting illumination from a surface of the sample, focusing the collected illumination onto a detector via a collection pathway to form an image of at least a portion of the surface of the sample and purging the illumination pathway and/or the collection pathway with a selected purge gas. |
| US09558851B2 |
Soft post package repair of memory devices
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the detective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus. |
| US09558848B2 |
Testing storage device power circuitry
The present invention extends to methods, systems, and computer program products for testing storage device power circuitry. A storage device controller includes an embedded test program. The storage device controller executes the test program in response to receiving a test command. In one aspect, the test program issues a plurality of different command patterns to test shared power circuitry of storage device components (e.g., shared by an array of NAND flash memory devices). The test program identifies a command pattern that causes a greatest total current draw. In another aspect, the test program issues a specified command pattern (possibly repeatedly) to shared power circuitry to determine if the shared power circuitry fails. |
| US09558844B2 |
Identifying stacked dice
Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described. |
| US09558842B2 |
Discrete three-dimensional one-time-programmable memory
The present invention discloses a discrete three-dimensional one-time-programmable memory (3D-OTP). It comprises at least a 3D-array die and at least a peripheral-circuit die. At least a peripheral-circuit component of the 3D-OTP arrays is located on the peripheral-circuit die instead of the 3D-array die. The 3D-array die and the peripheral-circuit die have substantially different back-end-of-line (BEOL) structures. |
| US09558835B2 |
Semiconductor device and operating method thereof
Disclosed are a semiconductor device and an operating method thereof. The semiconductor device includes a plurality of memory blocks including cell strings coupled between bit lines and a source line, a peripheral circuit configured to perform an erase operation on a selected memory block among the plurality of memory blocks; and a control circuit configured to control the peripheral circuit, so that when an erase command is received, local word lines coupled to a non-selected memory block among the plurality of memory blocks are pulled to ground, the local word lines coupled to the non-selected memory block float after a pre-erase voltage lower than an erase voltage is applied to the source line, and the erase operation of the selected memory block is performed by applying the erase voltage to the source line. |
| US09558834B2 |
Nonvolatile memory device and an erasing method thereof
An erase method of a nonvolatile memory device includes applying an erase voltage to a substrate; sensing a temperature of a memory cell array; setting a delay time based on the temperature of the memory cell array, wherein the delay time starts in response to the erase voltage being applied to the substrate; applying a ground voltage to a ground selection line connected to a ground selection transistor during the delay time; and increasing a voltage of the ground selection line after the delay time. |
| US09558833B2 |
Write controlling method for memory
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block. |
| US09558832B2 |
Semiconductor device including boosted voltage supply circuit for supplying boosted voltage to memory array
To maintain constant an output voltage of a boosted voltage circuit even when a program current of a nonvolatile memory increases; in a boosted voltage circuit provided in a semiconductor device, an output voltage of a charge pump is detected by a voltage dividing circuit, and on-off control is performed on an oscillation circuit for driving the charge pump so that the detected output voltage becomes constant. Further, an output current of the charge pump is detected, and a control current according to a magnitude of the detected output current is generated. The control current is fed into or drawn from a coupling node between a plurality of series-coupled resistance elements configuring the voltage dividing circuit. |
| US09558831B2 |
Non-volatile memory programming
Some embodiments include a memory device and a method of programming memory cells of the memory device. One such method includes applying voltages to data lines associated with different groups of memory cells during a programming operation. Such a method applies the voltages to the data lines associated with a last group of memory cells being programmed in a different fashion from the other groups of memory cells after the other groups of memory cells have been programmed. Other embodiments including additional memory devices and methods are described. |
| US09558827B2 |
Semiconductor memory device having memory strings including drain-side and source-side memory cells connected to pipe transistor and peripheral circuit suitable for applying pipe gate voltage to pipe transistor during read operation
A semiconductor memory device is provided. The semiconductor memory device includes memory strings including drain-side memory cells connected between a bit line and a pipe transistor, and source-side memory cells connected between the pipe transistor and a source line, and a peripheral circuit suitable for applying a pipe gate voltage to a pipe gate of the pipe transistor before applying pass voltages to turn on non-selected memory cells among the drain-side memory cells and the source-side memory cells during a read operation. |
| US09558825B1 |
System and method to discover and encode indirect associations in associative memory
Described is a system for detecting and encoding indirect associations in associative memory. The system receives a data storage input in a content-addressable memory (CAM), the data storage input comprising an association between a first data pattern A and a second data pattern B. At least one indirect association related to the data storage input is identified with an inductive logic unit (ILU) interfaced with the CAM, and the indirect association is stored for later recall. A query is generated from the ILU to the CAM to determine whether either of the first data pattern A or the second data pattern B is stored as part of an existing association in the CAM. If either the first data pattern A or the second data pattern B are known, then a new indirect association for the known data pattern is stored. |
| US09558821B2 |
Resistive memory device and method of operating the same
Provided are a resistive memory device and a method of the resistive memory device. The method of operating the resistive memory device includes performing a pre-read operation on memory cells in response to a write command; performing an erase operation on one or more first memory cells on which a reset write operation is to be performed, determined based on a result of comparing pre-read data from the pre-read operation with write data; and performing set-direction programming on at least some memory cells from among the erased one or more first memory cells and on one or more second memory cells on which a set write operation is to be performed. |
| US09558819B1 |
Method, system and device for non-volatile memory device operation
Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state. |
| US09558818B2 |
Memory and memory managing method
A method for managing memory includes setting a state of a first memory cell to a first state representing a first data and setting a state of a second memory cell to a second state representing the first data. If the state of the second memory cell has changed to a third state representing a second data different from the first data, the method also includes changing the state of the second memory cell back to the second state. |
| US09558815B2 |
Semiconductor storage device
A semiconductor storage device according to an embodiment includes a memory cell array including a plurality of memory cells. A plurality of word lines are connected to the memory cells. A plurality of bit lines are connected to one end of current paths of the memory cells. A sense amplifier part repeats a detection operation plural times when detecting data of memory cells connected to a word line WLn (n is an integer) among the word lines. A controller selects one of a plurality of detection results obtained by the detection operations, based on data of memory cells connected to a word line WLn−1 and data of memory cells connected to a word line WLn+1. |
| US09558810B2 |
Semiconductor device
A semiconductor device capable of reconfiguration, including a plurality of logic units which are connected to each other by an address line or a data line, wherein each of the logic units includes: a plurality of address lines; a plurality of data lines; a clock signal line to receive a system clock signal; a first and a second memory cell units which operate synchronously with the clock signal; a first address decoder which decodes an address signal and outputs a decode signal to the first memory cell unit; a second address decoder which decodes an address signal and outputs a decode signal to the second memory cell unit; and an address transition detection unit which generates an internal clock signal and outputs the internal clock signal to the first memory cell unit, when a transition of the address signal input from the plurality of address lines is detected, wherein the first memory cell unit operates synchronously with the internal clock signal, and the second memory cell unit operates synchronously with the system clock signal. |
| US09558804B2 |
Charge storage ferroelectric memory hybrid and erase scheme
A technique for erasing a ferroelectric field effect transistor (FeFET) memory circuit comprising a plurality memory cells comprising FeFETs is described. Each FeFET comprises a gate stack, a source, a drain, a channel and a bulk substrate region, where the gate stack comprises a gate and a ferroelectric layer disposed between the gate and the channel. A positive or a negative voltage is applied to the source and drain regions of at least one FeFET memory cell depending on the channel type. The gate and bulk substrate regions are held at a ground state during said applying of the positive voltage to the source and drain regions of the FeFET memory cell to cause erasure of the at least one FeFET memory cell. In addition, a FeFET is described with a charge storage layer disposed adjacently to the ferroelectric layer within the gate stack. |
| US09558799B2 |
Timing violation handling in a synchronous interface memory
A memory device includes an operation having a phase to provide an upper row address from a row address buffer, a phase to combine the upper row address with a lower row address to select data for a row data buffer, and a phase to output the data from the row data buffer, wherein an activate command starts and following activate commands are ignored until a preset time has elapsed. |
| US09558796B2 |
Systems and methods for maintaining memory access coherency in embedded memory blocks
Enhanced memory circuits are described that maintain coherency between concurrent memory reads and writes in a pipelined memory architecture. The described memory circuits can maintain data coherency regardless of the amount of pipelining applied to the memory inputs and/or outputs. Moreover, these memory circuits may be implemented as dedicated hard circuits in a field programmable gate array (FPGA) or other programmable logic device (PLD), and can be supplemented with user-configurable logic to achieve coherency in a variety of applications. |
| US09558790B1 |
Hermetic sealing with high-speed transmission for hard disk drive
Embodiments disclosed herein generally relate to hermetic electrical connectors used in hard disk drives. The hermetic electrical connector includes a barrier structure having a first plurality of connecting pads disposed on a first surface of the barrier structure and a second plurality of connecting pads disposed on a second surface of the barrier structure opposite the first surface. A plurality of conductors is disposed within the barrier structure, and each conductor is coupled to a connecting pad of the first plurality of connecting pads and a corresponding connecting pad of the second plurality of connecting pads. The barrier structure further includes a dielectric material between the first and second surfaces, and one or more layers embedded in the dielectric material. The addition of the layers helps choke the helium gas flow, thus improving sealing of the electrical connector while maintaining high-speed electrical transmission. |
| US09558789B1 |
Storage device sled and assembly method thereof
An improved storage device sled is provided. The storage device sled includes first and second portions, each of which includes a threaded fastener, a longitudinal member, and a bezel member. The longitudinal members are configured to couple to mounting holes of a storage device. Each of the bezel members is orthogonal to a longitudinal member. One of the bezel members includes a latching clip and cutouts to receive one or more alignment projections. The other bezel member includes a latching clip receiver, configured to receive and capture the latching clip, and the one or more alignment projections. Each of the longitudinal members includes a hole for the threaded fastener, which retains the longitudinal member to a mounting hole on a side of the storage device. The longitudinal members also include a tapered post, which captures a mounting hole on a side of the storage device. |
| US09558788B2 |
Systems and methods of providing user interface features for a media service
In an exemplary method, a computer-implemented media service system provides a graphical user interface view associated with a first functional area of the media service for display on a display screen, detects a peek request input while the graphical user interface view is displayed, and provides, in response to the peek request input and for display with the graphical user interface view, an activity indicator indicating a tracked activity associated with the second functional area of the media service. Corresponding systems and methods are also described. |
| US09558786B2 |
Systems, methods, and computer program products for multiple aspect ratio automated simulcast production
A system, method, and computer program product for producing a show. In an embodiment, the invention is directed to a production system having a first production path, a second production path, and a control system that causes the first production path to generate a show in a first aspect ratio (4:3), and that causes the second production path to generate the same show in a second aspect ratio (16:9). In another embodiment, the invention is directed to producing a show from live material and from archived material. This aspect of the invention operates by producing a first show comprising a plurality of stories, segmenting the first show, and storing the show segments in an archive. Then, the invention produces a second show using live portions as well as show segments retrieved from the archive. The invention is also directed to a media manager that interacts with a server. In some cases, the server is integrated with the production system. The media manager automatically assigns channels/ports of the server when accessing material stored in the server. |
| US09558782B2 |
Partial reverse concatenation for data storage devices using composite codes
In one embodiment, a data storage system includes a write channel for writing data to a storage medium, the write channel configured to utilize a partial reverse concatenated modulation code. The write channel includes logic adapted for encoding data sets using a C2 encoding scheme, logic adapted for adding a header to each subunit of the data sets, logic adapted for encoding the headers of the data sets with a first modulation encoding scheme, logic adapted for encoding data portions of the data sets with a second modulation encoding scheme, logic adapted for encoding portions of the one or more C2-encoded data sets using a C1 encoding scheme, logic adapted for combining the C1-encoded portions with the modulation-encoded headers of the C2-encoded data sets using a multiplexer, and logic adapted for writing the one or more combined C1 - and C2-encoded data sets to data tracks. |
| US09558780B2 |
Library device and accessor device
A library device includes: a housing having a substantially rectangular parallelepiped shape, the housing having a first surface and a second surface differing from each other; a first track that is provided within the housing, the first track extending along the first surface; a second track that is provided within the housing, the second track extending along the second surface, the second track being parallel with the first track; and an accessor device that includes a first portion engaging with the first track, and a second portion engaging with the second track. |
| US09558776B1 |
Durable coating for magnetic tape recording media
A product such as a magnetic recording tape, according to one embodiment, includes a flexible magnetic media having a substrate, a magnetic recording layer having cobalt therein, and an at least partially polycrystalline coating above the magnetic recording layer. A product according to another embodiment includes a flexible magnetic media having a substrate, a magnetic recording layer having cobalt therein, and coating above the magnetic recording layer. The coating includes a ceramic material. |
| US09558765B2 |
CoFe/Ni multilayer film with perpendicular anisotropy for microwave assisted magnetic recording
A spin transfer oscillator (STO) with a seed/FGL/spacer/SIL/capping configuration is disclosed with a composite seed layer made of Ta and a metal layer having a fcc(111) or hcp(001) texture to enhance perpendicular magnetic anisotropy (PMA) in an overlying (A1/A2)YFeCo laminated field generation layer (FGL). The spin injection layer (SIL) may be laminated with a (A1/A2)XFeCo configuration. The FeCo layer in the SIL is exchanged coupled with the (A1/A2)X laminate (x is 5 to 50) to improve robustness. The (A1/A2)Y laminate (y=5 to 30) in the FGL may be exchange coupled with a high Bs layer to enable easier oscillations. A1 may be one of Co, CoFe, or CoFeR where R is a metal, and A2 is one of Ni, NiCo, or NiFe. The STO is typically formed between a main pole and trailing shield in a write head. |
| US09558763B1 |
Magnetic recording write apparatus having a pole including an assist portion extending in the cross-track direction
A magnetic write apparatus has a media-facing surface (MFS), a pole, side shield(s), a side gap and coil(s) for energizing the pole. The pole includes main and assist portions. The main portion is ferromagnetic, includes a pole tip and includes side surface(s) having a flare angle from the MFS. The pole tip occupies a portion of the MFS. The flare angle is nonzero and acute. The assist portion adjoins the main portion, extends from the main portion in a direction having a component in a cross-track direction, and has a depth of not more than three hundred nanometers. The side shield(s) occupy another portion of the MFS, have a back surface, and are between the assist portion and the MFS. The assist portion is conformal with the back surface of the side shield(s). The side gap is between the main portion of the pole and the side shield(s). |
| US09558760B2 |
Real-time remodeling of user voice in an immersive visualization system
A visualization system with audio capability includes one or more display devices, one or more microphones, one or more speakers, and audio processing circuitry. While a display device displays a holographic image to a user, a microphone inputs an utterance of the user, or a sound from the user's environment, and provides it to the audio processing circuitry. The audio processing circuitry processes the utterance (or other sound) in real-time to add an audio effect associated with the image to increase realism, and outputs the processed utterance (or other sound) to the user via the speaker in real-time, with very low latency. |
| US09558755B1 |
Noise suppression assisted automatic speech recognition
Noise suppression information is used to optimize or improve automatic speech recognition performed for a signal. Noise suppression can be performed on a noisy speech signal using a gain value. The gain to apply to the noisy speech signal is selected to optimize speech recognition analysis of the resulting signal. The gain may be selected based on one or more features for a current sub band and time frame, as well as one or more features for other sub bands and/or time frames. Noise suppression information can be provided to a speech recognition module to improve the robustness of the speech recognition analysis. Noise suppression information can also be used to encode and identify speech. |
| US09558754B2 |
Audio encoder and decoder with pitch prediction
In one embodiment, an audio decoder for decoding an encoded audio bitstream is disclosed. The audio decoder is capable of being operated in at least three different decoding modes. The audio decoder includes a demultiplexer for obtaining audio data and control information from the encoded audio bitstream. The audio decoder also includes a first audio decoder configured to operate in a first decoding mode using a first decoding technique and a second audio decoder configured to operate in a second decoding mode using a second decoding technique. The audio decoder also includes a pitch predictor integrated into the second audio decoder. The pitch predictor includes a long-term prediction filter and a short-term prediction filter. The audio decoder further includes a selector for selecting one of the at least three different decoding modes based on at least some of the control information. |
| US09558753B2 |
Pitch filter for audio signals
In some embodiments, a pitch filter for filtering a preliminary audio signal generated from an audio bitstream is disclosed. The pitch filter has an operating mode selected from one of either: (i) an active mode where the preliminary audio signal is filtered using filtering information to obtain a filtered audio signal, and (ii) an inactive mode where the pitch filter is disabled. The preliminary audio signal is generated in an audio encoder or audio decoder having a coding mode selected from at least two distinct coding modes, and the pitch filter is capable of being selectively operated in either the active mode or the inactive mode while operating in the coding mode based on control information. |
| US09558752B2 |
Encoding device and encoding method
This encoding device (100) is provided with: a CELP encoding unit (102) that decodes CELP encoded data resulting from CELP encoding an input signal, generating a CELP decoded signal; a transform encoding unit (106) that generates a decoded signal spectrum by decoding transform encoded data resulting from using the spectrum of the input signal and the suppression spectrum of suppressing using a first suppression factor to transform encode the amplitude of the spectrum of the CELP decoded signal, and that outputs an index of the transform encoded frequency component; a pulse index recording unit (107) that forms and records an array using the index; and a CELP component suppression unit (109) that uses a second suppression factor and the array to suppress the amplitude of the spectrum resulting from adding the decoded signal spectrum and the suppression spectrum. |
| US09558749B1 |
Automatic speaker identification using speech recognition features
Features are disclosed for automatically identifying a speaker. Artifacts of automatic speech recognition (“ASR”) and/or other automatically determined information may be processed against individual user profiles or models. Scores may be determined reflecting the likelihood that individual users made an utterance. The scores can be based on, e.g., individual components of Gaussian mixture models (“GMMs”) that score best for frames of audio data of an utterance. A user associated with the highest likelihood score for a particular utterance can be identified as the speaker of the utterance. Information regarding the identified user can be provided to components of a spoken language processing system, separate applications, etc. |
| US09558748B2 |
Methods for hybrid GPU/CPU data processing
The present invention describes methods for performing large-scale graph traversal calculations on parallel processor platforms. The invention describes methods for on-the-fly hypothesis rescoring that utilizes graphic processing units (GPUs) in combination with utilizing central processing units (CPUs) of computing devices. The invention is described in one embodiment as applied to the task of large vocabulary continuous speech recognition. |
| US09558745B2 |
Service oriented speech recognition for in-vehicle automated interaction and in-vehicle user interfaces requiring minimal cognitive driver processing for same
A system and method for implementing a server-based speech recognition system for multimodal automated interaction in a vehicle includes receiving, by a vehicle driver, audio prompts by an on-board human-to-machine interface and a response with speech to complete tasks such as creating and sending text messages, web browsing, navigation, etc. This service-oriented architecture is utilized to call upon specialized speech recognizers in an adaptive fashion. The human-to-machine interface enables completion of a text input task while driving a vehicle in a way that minimizes the frequency of the driver's visual and mechanical interactions with the interface, thereby eliminating unsafe distractions during driving conditions. After the initial prompting, the typing task is followed by a computerized verbalization of the text. Subsequent interface steps can be visual in nature, or involve only sound. |
| US09558741B2 |
Systems and methods for speech recognition
Systems and methods are provided for speech recognition. For example, audio characteristics are extracted from acquired voice signals; a syllable confusion network is identified based on at least information associated with the audio characteristics; a word lattice is generated based on at least information associated with the syllable confusion network and a predetermined phonetic dictionary; and an optimal character sequence is calculated in the word lattice as a speech recognition result. |
| US09558740B1 |
Disambiguation in speech recognition
Automatic speech recognition (ASR) processing including a feedback configuration to allow for improved disambiguation between ASR hypotheses. After ASR processing of an incoming utterance where the ASR outputs an N-best list including multiple hypotheses, the multiple hypotheses are passed downstream for further processing. The downstream further processing may include natural language understanding (NLU) or other processing to determine a command result for each hypothesis. The command results are compared to determine if any hypotheses of the N-best list would yield similar command results. If so, the hypothesis(es) with similar results are removed from the N-best list so that only one hypothesis of the similar results remains in the N-best list. The remaining non-similar hypotheses are sent for disambiguation, or, if only one hypothesis remains, it is sent for execution. |
| US09558739B2 |
Methods and systems for adapting a speech system based on user competance
Methods and systems are provided for adapting a speech system. In one example a method includes: logging speech data from the speech system; processing the speech data for a pattern of a user competence associated with at least one of task requests and interaction behavior; and selectively updating at least one of a system prompt and an interaction sequence based on the user competence. |
| US09558732B2 |
Active noise control system
An active noise control system includes a first microphone, a controller operably coupled to the first microphone, and a speaker operably coupled to the controller. The first microphone senses a sound input in an audible spectrum, wherein the sound input includes a disturbance noise portion. The controller includes a selection unit and an output unit. The selection unit determines the disturbance noise portion of the sound input based on a highest frequency level of the sound input. The output unit removes the disturbance noise portion from the sound input to generate a filtered sound input. The speaker generates a speaker output based on the filtered sound input. |
| US09558729B2 |
Digital circuit arrangements for ambient noise-reduction
A digital circuit arrangement for an ambient noise-reduction system affording a higher degree of noise reduction than has hitherto been possible. The arrangement converts the analog signals into N-bit digital signals at sample rate f0, and then subjects the converted signals to digital filtering. The value of N in some embodiments is 1 but, in any event, is no greater than 8, and f0 may be 64 times the Nyquist sampling rate but, in any event, is substantially greater than the Nyquist sampling rate. This permits digital processing to be used without incurring group delay problems that rule out the use of conventional digital processing in this context. Furthermore, adjustment of the group delay can readily be achieved, in units of a fraction of a micro-second, providing the ability to fine tune the group delay for feed forward applications. |
| US09558725B2 |
Disk, wind instrument, counter piece, and method of producing the disk
A disk for stabilizing a pad assembly in a key cup for closure of a wind instrument tone hole includes an integral body made of a material which is in a solid state at a room temperature and in a malleable state at a predetermined temperature higher than the room temperature. |
| US09558721B2 |
Content-based adaptive refresh schemes for low-power displays
A content-based adaptive refresh technique is implemented in an active matrix display system for reducing power consumption. The active matrix display system includes a display panel having multiple rows of display elements arranged as a display matrix. The display panel is coupled to a scan driver and a data driver. The scan driver selects one row at a time to receive data signals, and the data driver provides the data signals. The active matrix display system also includes a timing controller operable to signal the scan driver to cause a first row of the display panel to be not refreshed in a current data frame and a second row of the display panel to be refreshed in the current data frame. |
| US09558720B2 |
Variable resolution seamless tileable display
A tileable display panel includes an illumination layer, a display layer, and a screen layer. The display layer is disposed between the screen layer and the lamp layer and includes pixelets. Each of the pixelets is positioned to be illuminated by lamp light from the illumination layer and to project a magnified image sub-portion onto the screen layer such that the magnified image sub-portions collectively blend together to form a unified image on the screen layer. Each of the pixelets includes core pixels and peripheral pixels surrounding the core pixels on one or more sides which provide a higher image resolution in overlap regions on the screen layer when the magnified image sub-portions overlap on the screen layer. |
| US09558719B2 |
Information processing apparatus
An information processing apparatus comprising first and second display units for respectively displaying first and a second composite images for the two eyes of a user, comprising: a moving unit configured to move positions of the first and second display units; a detecting unit configured to detect moving amounts of the first and second display units; first and second image capturing units configured to respectively obtain first and second captured images; an extracting unit configured to generate first and second extracted images by respectively extracting portions of the first and second captured images in extraction ranges associated with the moving amounts; and a composite image generating unit configured to generate the first and second composite images by respectively compositing first and second CG images with the first and second extracted images. |
| US09558713B2 |
Dynamic transparency adjustment of user interface element
A user device dynamically adjusts one or more portions of a user interface (UI) element. The user device detects content color data describing the color of content that is overlaid by a UI element on a display of a user device, the UI element including one or more components and a UI element background. The user device determines component color data describing the color of the one or more components of the UI element, and dynamically determines transparency data for the UI element background using the content color data and the component color data. The user device displays the UI element in accordance with the transparency data and the component color data. |
| US09558710B2 |
Transitioning operation between device display screens and interface therefor
A method and system for transitioning operation between display screens of a computing device, with a user interface. The device further includes primary and secondary touch screen displays, an ambient lighting brightness sensor, a memory storing instructions and an e-book having content displayable according to a series of digitally constructed pages. The method comprises receiving, at a screen transition interface presented on one of the primary display screen and the secondary display screen, selections of an upper and a lower brightness threshold limits of ambient lighting, sensing a brightness level of ambient lighting, activating the secondary display screen for operation only if one of: (i) the ambient lighting brightness level exceeds the upper threshold limit and (ii) the ambient lighting brightness level is less than the lower threshold limit, and transitioning operation of the computing device to the secondary display screen by rendering the pages of e-book content thereon. |
| US09558705B2 |
Flat panel display device controlling initialization of data lines supplied to a pixel unit
A flat panel display device includes a pixel unit having scan-lines, data-lines, and first through third pixels that are coupled to the scan-lines and the data-lines, a scan driver that applies a scan signal to the pixel unit, a data driver that selectively applies a first data signal, a second data signal, a third data signal, and an initialization signal to the pixel unit, a demultiplexing unit having at least one demultiplexer that applies the first data signal, the second data signal, and the third data signal to the first pixels, the second pixels, and the third pixels, respectively, and that simultaneously applies the initialization signal to the first through third pixels, and a timing control unit that controls the scan driver, the data driver, and the demultiplexing unit. |
| US09558703B2 |
Liquid crystal display and driving method thereof
Among data voltages applied to a plurality of pixels on a display panel, a first data voltage is shifted from a first original data voltage by a first value, a second data voltage is shifted from a second original data voltage by a second value, and a third data voltage is shifted from a third original data voltage by a third value to compensate for AC and DC afterimages. A common voltage generator provides an optimal common voltage for the third data voltage when the temperature of the liquid crystal panel assembly is lower than a reference temperature and provides an optimal common voltage for the first data voltage or the second data voltage when the temperature of the liquid crystal panel assembly is higher than or equal to the reference temperature. The first, second, and third values correspond to respective kickback voltages of the respective gray level data voltages. |
| US09558701B2 |
Shift register, integrated gate line driving circuit, array substrate and display
A shift register an integrated gate line driving circuit, an array substrate and a display are disclosed. Two electronic switching modules are added to the existing shift register, wherein one of the two electronic switching modules is arranged among a puling-down node, a low level signal terminal and a pulling-up node, and the other is arranged among the pulling-down node, the low level signal terminal and a signal output terminal; during the non-operating time of the shift register and when the pulling-down node is at a low level, the two electronic switching modules are turned on, and discharge the pulling-up node and the signal output terminal respectively to pull down the noise voltage, thereby effectively reducing the noise interference of the shift register during the non-operating time. |
| US09558698B2 |
Data driver and display device driving method
A driving method for driving a display apparatus including a plurality of pixels, a plurality of data lines and a data driver. The data driver includes a first latch outputting a first sample data signal to a second latch, the second latch, a first charge sharing line and a second charge sharing line. The method includes performing a first charge sharing when a polarity of one of the pixels changes so as to output a first calibrated data signal to the data line electrically coupled to the pixel, and executing a second charge sharing when the most significant bit of the first sample data signal is different from the most significant bit of the second sample data signal so as to output a second adjusted data signal to the data line. |
| US09558697B2 |
Display device driving sub-pixels of a plurality of colors
According to one embodiment, a display element includes a plurality of scanning lines and a plurality of signal lines. Into the plurality of signal lines, signals of different polarities are alternately input, respectively. In the respective regions surrounded by the scanning lines and the signal lines, a first pixel and a second pixel are arrayed. Along the scanning line, two each of the first pixels and the second pixels are provided, and the two first pixels or the two second pixels are arrayed so as to be juxtaposed to each other. Along the signal line, the first pixel and the second pixel are arrayed alternately. |
| US09558696B2 |
Electrophoretic display device
This specification relates to an electrophoretic display device, and particularly, to an electrophoretic display device capable of reducing power consumption by blocking a leakage current generated from a Power On Reset (POR) circuit which resets each driver Integrated Circuit (IC) at an initial period, whereby a transistor as an active element connected to a POR circuit may be turned on by applying a positive voltage, other than a power supply voltage, to a gate thereof at an image update period to drive a bias block, and thereafter turned off at an image static period, thereby blocking a leakage current and accordingly reducing power consumption. |
| US09558694B2 |
Organic light emitting display device
An organic light emitting display device, including pixels positioned at crossing regions of scan lines and data lines and a bias voltage supply configured to supply bias voltages to the pixels. Each of the pixels includes an organic light emitting diode (OLED), a first transistor coupled between a first power supply and the OLED and driven in a saturation region by a corresponding one of the bias voltages to supply a set current to the OLED, a second transistor coupled between the first power supply and the OLED and driven in a linear region by a data signal supplied from a corresponding one of the data lines to turn on or off, and a second capacitor coupled between a gate electrode of the first transistor and the first power supply. |
| US09558693B2 |
Display devices and electronic devices having the same
A display device includes a display panel driver and a DC-DC converter. The display panel driver divides one frame into a plurality of periods and outputs a control signal to generate an analog supply voltage, a first power voltage, and a second power voltage for driving pixels. The DC-DC converter receives the control signal from the display panel driver through a single wire. The DC-DC converter includes an analog supply voltage generator, a first power voltage generator, and a second power voltage generator. The analog supply voltage generator generates the analog supply voltage during a first pulse period. The first power voltage generator generates the first power voltage during a second pulse period. The second power voltage generator generates the second power voltage during the third pulse period. |
| US09558689B2 |
Pixel structure and display panel
A pixel structure includes a plurality of red sub-pixels, white sub-pixels, blue sub-pixels and green sub-pixels, which are arranged to form a plurality of first sub-pixel cells and second sub-pixel cells. The first and second sub-pixel cells may be arranged to form a plurality of pixel cells. The pixel cells may be arranged in the vertical direction repeatedly to form a plurality of pixel array cells. The pixel array cells may be arranged in the horizontal direction repeatedly to form a plurality of pixel arrays. The pixel structure further includes a supplement pixel array disposed in the pixel arrays according to a preset mode and configured to supplement polarity inversion in the pixel structure. The sub-pixels with a same color in a same row in a same signal frame may not have a same polarity, thereby reducing flicker and horizontal crosstalk of images and improving the image display quality. |
| US09558687B2 |
Display device and method for driving the same
In order to display 3D images by a parallax barrier method, a display screen and the eyes of a viewer need to have a specific positional relation. An object is to provide a display device with an extended area where the viewer can perceive 3D images with the naked eye. Attention is focused on the position of the viewer with respect to pixels provided in a display device and a mode of a parallax barrier provided between the viewer and the pixels. This leads to a structure in which the position of the viewer with respect to pixels is specified by using an ultrasonic wave to change a mode of a parallax barrier in accordance with the position of the viewer, thereby achieving the above object. |
| US09558686B2 |
Combination mounting and storing device for a vehicle safety flag
Disclosed is a combination mounting and storing device for a vehicle safety flag that is used to mark an oversized load. The device includes a hollow cylindrical housing having an interior volume and a bobbin disposed therein. The bobbin includes a reel that is adapted to retract and extend an elongated cord that is attached to the vehicle safety flag. The device further includes a magnet that allows a user to removably mount the device onto the inside of a truck bed or trunk. When the device is in use, the cord is extended outward so as to allow a user to secure the safety flag onto the extreme rear of the projecting load. The device can be mounted to the rear of the vehicle when transporting an oversized load and can be easily stored in a glove compartment when it is not in use. |
| US09558684B2 |
Cable marker
A cable marker includes a housing which has an accommodating opening to accommodate a label to mark a cable, a cover to close the accommodating opening in a closed position of the cable marker, and a film hinge integrally connecting the housing to the cover such that in an open position, in which the cover does not close the accommodating opening, the cover can be pivoted in relation to the housing along a pivoting plane. The film hinge has a first base portion connecting the film hinge to the housing, a second base portion connecting the film hinge to the cover, and a connecting portion arranged between the first base portion and the second base portion. The connecting portion has a width that is reduced in comparison with at least one of the base portions as viewed in a direction perpendicular to the pivoting plane. |
| US09558683B2 |
Identification tag adapted to be clipped to a shaft
The identification tag is provided in a general horseshoe shape with resilient prongs engageable to a shaft such as a shaft of a pulley-mounted hook at a beginning of a processing line. The identification tag can be used to track a product throughout the processing line. |
| US09558677B2 |
Mock attack cybersecurity training system and methods
A training system senses a user action that may expose the user to a threat, such as a cybersecurity threat. The user action may be in response to a mock attack delivered via a messaging service, a wireless communication service, a fake malware application or another device, service, system or mechanism. The system selects a training action from a collection of available training actions and causes the training action to be delivered to the user. |
| US09558670B1 |
Method and system for air traffic rerouting for airspace constraint resolution
A dynamic constraint avoidance route system automatically analyzes routes of aircraft flying, or to be flown, in or near constraint regions and attempts to find more time and fuel efficient reroutes around current and predicted constraints. The dynamic constraint avoidance route system continuously analyzes all flight routes and provides reroute advisories that are dynamically updated in real time. The dynamic constraint avoidance route system includes a graphical user interface that allows users to visualize, evaluate, modify if necessary, and implement proposed reroutes. |
| US09558668B2 |
Systems and methods for improving an in-trail procedures request
Systems and methods for improving the reception and delivery of an In-Trail Procedures (ITP) altitude change request. An example system located on board a host aircraft includes a communication component, a display device and a processor unit that is in signal communication with the communication component and the display device. The processor unit presents a user interface on the display device. The user interface includes a plurality of fields for receiving In-Trail Procedures (ITP) altitude change request information. The processor sends the ITP altitude change request information received within the plurality of fields to an Air Traffic Control (ATC) facility via the communication component. An ITP unit having a display receives an altitude selection and presents ITP altitude change request information if the received altitude selection is determined to be valid. |
| US09558667B2 |
Systems and methods for cooperative collision detection
A vehicle collision detection system may be configured to coordinate with collision detection systems of other vehicles. The coordination may comprise sharing sensor data with other vehicles, receiving sensor information from other vehicles, using sensor information to generate a collision detection model, sharing the collision detection model with other vehicles, receiving a collision detection model from other vehicles, and the like. In some embodiments, vehicles may coordinate sensor operation to form a bistatic and/or multistatic sensor configuration, in which a detection signal generated at a first land vehicle is detected at a sensing system at a second land vehicle. |
| US09558664B1 |
Method and apparatus for providing parking availability detection based on vehicle trajectory information
An approach is provided for parking availability detection based on vehicle trajectory information. A trajectory processing platform processes and/or facilitates a processing of trajectory data associated with at least one journey of at least one vehicle to determine at least one portion of the at least one journey that is associated at least one parking search by the at least one vehicle. The trajectory processing platform also determines one or more street segments associated with the at least one portion of the at least one journey. The trajectory processing platform further causes, at least in part, a classification of the one or more street segments as associated with the at least one parking search. The trajectory processing platform further determines parking availability information for the one or more street segments based, at least in part, on the trajectory data. |
| US09558663B2 |
Animal detecting and notification method and system
Driving condition monitoring system and method includes animal detecting components that detect presence of an animal, each located in a stationary mounting structure in a vicinity of the travel surface and apart from the travel surface, and a vehicle detecting sensor coupled to each animal detecting component and that is activated to detect the presence of a vehicle within a set distance therefrom only when the animal detecting component coupled to the vehicle detecting sensor detects the presence of an animal in the vicinity of the animal detecting component. A communication system is coupled to each animal detecting component and communicates directly to the vehicle or occupant thereof, the detected presence of an animal in the vicinity of the animal detecting component when the vehicle detecting sensor coupled to the animal detecting component detects the presence of a vehicle within the set distance from the vehicle detecting sensor. |
| US09558660B1 |
Method and apparatus for providing state classification for a travel segment with multi-modal speed profiles
An approach is provided for state classification for a travel segment with multi-modal speed profiles. A traffic processing platform processes and/or facilitates a processing of probe data associated with at least one travel segment to determine that probe data indicates a plurality of speed profiles. The plurality of speed profiles represent one or more observed clusters of speed states. The traffic processing platform also determine that the at least one travel segment exhibits a multi-modality with respect to travel speed based, at least in part, on the plurality of speed profiles. The traffic processing platform then determines at least one likely sequence of speed states for traversing the at least one travel segment based, at least in part, on the one or more observed clusters of speed states and state transition probability information, wherein the state transition probability information represents one or more probabilities for transitioning among the plurality of speed states and causes, at least in part, a classification of at least one hidden state of the at least one travel segment based, at least in part, on the at least one likely sequence of speed states. |
| US09558659B1 |
Determining the stationary state of detected vehicles
Aspects of the disclosure relate to an autonomous vehicle that may detect other nearby vehicles and designate stationary vehicles as being in one of a short-term stationary state or a long-term stationary state. This determination may be made based on various indicia, including visible indicia displayed by the detected vehicle and traffic control factors relating to the detected vehicle. For example, the autonomous vehicle may identify a detected vehicle as being in a long-term stationary state based on detection of hazard lights being displayed by the detected vehicle, as well as the absence of brake lights being displayed by the detected vehicle. The autonomous vehicle may then base its control strategy on the stationary state of the detected vehicle. |
| US09558655B2 |
Utility monitoring device, system and method
A monitoring device, system and method are provided for in-home/on-premises monitoring of usage of utilities, such as electricity and other services. The monitoring device receives information from a smart meter, and displays usage through a display, illuminating an area using a colour indicative of the current cost of consumption, and varying the illuminated area at a rate indicative of a rate of consumption or other metric, the varying of the illuminated area simulating movement in the display. The display provides a consumer with “at a glance” visual information on current usage. Optionally a digital display screen provides detailed alphanumeric and graphical information, through a number of selectable display modes. One or more devices may be networked, and interface directly or indirectly with a transceiver of a smart metering system, or a retrofit transceiver for a conventional meter. Monitoring of other utilities and services may alternatively or additionally be provided. |
| US09558652B2 |
Motion based service provision
In one example embodiment, an apparatus includes a reader configured to read motion information, received from an end device, regarding a motion that was enacted by a user relative to the end device; a request generator configured to generate a service request that includes an identifier of the apparatus and the read motion information; a transmitter configured to transmit, to a service provider, the service request; and a receiver configured to receive, from the service provider, an expression of a service that is associated with the identifier of the apparatus and the read motion information. |
| US09558651B2 |
Convertible wireless remote controls
Convertible wireless remote controls for controlling a variety of media devices are described. The convertible wireless remote controls function in a non-PC mode and a PC mode. The convertible wireless remote controls transition between modes offering control of a variety of devices in the different modes and are shaped with usability and power consumption in mind. |
| US09558645B2 |
Released offender geospatial location information trend analysis
Methods of trend analysis for information related to released criminal offenders, the methods include accessing geospatial location information including date and time information for released criminal offenders and identifying repeated visits by one of the released criminal offenders within a defined proximity of a particular geospatial location, identifying a movement pattern of one of the released criminal offenders, correlating the movements of one the released criminal offenders to the movements of a subscriber, correlating the proximity of one of the released criminal offenders to a location where criminal activity has occurred, or comparing the geospatial location with previous activity of the released offender to predict potential future criminal activity. |
| US09558640B2 |
Camera hidden in ID card holder
A surveillance system comprising an electronic identity card holder 100 and corresponding identity card 170. The card holder 100 comprises a slot 150 for receiving an identity card 170. The slot 150 has a first side 150a and an opposing second side 150b. The first side 150a of the slot 150b comprising a viewing window 140 positioned to allow viewing of the second side 150b of slot 150. The card holder 100 also has a camera housed within the holder 100, and the camera has a camera aperture 196 provided on the second side 150b of the slot 150. The corresponding identity card 170 comprises an optically transparent region 175 that is configured to overlie the camera aperture 196 when the identity card 170 is received in the slot 150 of the holder 100. |
| US09558636B1 |
Automatic teller machine inventory and distribution system
A bank server allows a user of one ATM to reserve cash at another, nearby ATM when the first ATM has an inadequate cash inventory to serve the user's requested transaction. The user attempts to withdraw cash from the first ATM, but the first ATM has insufficient cash to perform the withdrawal transaction. Through the first ATM, the bank server offers the user a cash reservation at the other ATM. The bank server causes the other ATM to reserve a requested amount of cash for the user, possibly refusing to dispense cash to other users if doing so would leave the other ATM with insufficient cash to dispense the reserved cash. The user travels a short distance to the other ATM and withdraws the reserved cash. In effect, the other ATM can now perform the withdrawal transaction requested of the first ATM when the first ATM couldn't. |
| US09558635B2 |
Gaming machine having hybrid art glass
A gaming terminal for conducting a wagering game includes a gaming cabinet, a video display, and an art panel. The video display is positioned within the gaming cabinet and is configured to display content associated with the wagering game. The art panel is positioned within the gaming cabinet and overlays the video display such that a first region of the art panel is illuminated by the video display. |
| US09558632B2 |
Electronic gaming device with card tournament functionality
Examples disclosed herein relate to systems and methods, which may receive wagers on one or more paylines. The systems and methods may utilize one or more tournament game structures. The systems and methods may utilize one or more power-up cards in the one or more tournament game structures. |
| US09558628B2 |
Method and apparatus for providing a bonus to a player based on a credit balance
An apparatus and method allow a value of a credit balance on a gaming device to be determined. If the value is not less than a predetermined threshold, a benefit is provided to the player of the gaming device. In various embodiments, the benefit may be, e.g., an increase in the player's credit balance. |
| US09558626B2 |
Gaming system and method providing a group game having multiple stages
Various embodiments of the present disclosure provide a gaming system and method providing a group game having a same average expected total payback percentage regardless of the number of players participating in the group game. In various embodiments, the gaming system determines or sets one or more characteristics, features, or parameters of the group game based on the number of players participating in the group game such that the average expected total payback percentage of the group game is the same or substantially the same for each play of the group game regardless of the number of players participating in that play of the group game. |
| US09558624B2 |
Multi-mode multi-jurisdiction skill wagering interleaved system
Systems are provided including: a player's device constructed to: communicate device information; receive an authorization message; communicate an authorization to commence a SWig session; communicate updated device information; and receive an authorization revocation; a geographical location server constructed to: receive the device information; determine a geographical location of the player's device; and communicate the geographical location; and the SWig server connected to the player's device and the geographical location server by a network, and constructed to: receive the device information; receive the geographical location of the player's device; when the geographical location of the player's device is within a real credit wagering jurisdiction, communicate the authorization message; receive the authorization to commence the SWig session; initiate the SWig session; receive the updated device information; determine if the player's device has changed location; and when the player's device has changed location, revoke authorization of real credit wagering. |
| US09558622B2 |
Logistics methods for processing lottery and contest tickets with generic hardware
A lottery data transfer method for processing lottery ticket data piggybacks on a merchant's existing debit or credit card interchange system. A BIN is assigned to lottery tickets that is unique in the merchant's credit or debit card interchange, the BIN associated with a lottery data blob also provided on the lottery ticket. The lottery BIN and data blob are into the merchant's existing credit or debit card activation barcode protocol to initiate transfer of the lottery data to a central lottery site via the interchange. At a processor within the interchange, the unique lottery BIN is flagged to initiate special routing to and further processing of the lottery data blob at the lottery central site, wherein the lottery data blob is processed outside of the interchange's debit or credit card data transfer and processing procedures. |
| US09558621B2 |
Gaming system
A method of operating a gaming system including a plurality of gaming machines and at least one server system. The method includes providing at least a first gaming service to each gaming machine by way of one or more first software processes and providing at least one second service common to a subset of the plurality of gaming machines, the second service implemented by one or more second software processes. The method also includes enabling inter-process interaction between at least one software process of the first service and at least one software process of the second service to enable interaction between the services. A server system, gaming machine and gaming system is also disclosed. |
| US09558617B2 |
Electronic poker system
An electronic poker system is a system for reducing slowdowns and errors during play while delivering an authentic poker experience for players. The system includes a table where players are able to sit at a plurality of player stations while a live dealer sits at a dealer station. Each player's cards are shown on at least one flexible display while community cards and other game information is shown on at least one game display that is visible to all players. Each of the at least one flexible display is secured to a playing surface of the table through a tether device. A gameplay control unit automates many functions such as dealing player cards, dealing community cards, fixing dealer mistakes, and folding player hands. The live dealer is able to initiate these functions through at least one dealer input device. |
| US09558613B2 |
Social network interaction via games
Techniques for enabling members to learn about and interact with their social network via games are described. According to various embodiments, it is determined that a content item or entity associated with an online social network service is relevant to a member of the online social network service. An online game including a game question and a correct game answer is generated based on the content item or entity. The game question is then displayed to the member, and a member response to the displayed game question is received. Thereafter, a game result is displayed, and the member is enabled to interact with the content item or entity. |
| US09558608B2 |
Electronic locker right acquisition via an external system
A locker rental system includes electronic lockers centrally managed by a locker manager. The locker manager is in communication with a separate external system, which handles admissions and sales for a venue. Users are provided with a unique external identification (ID) code for purposes such as admission to the venue. Determinative sequences of the external ID codes are provided to the locker manager as validation codes. When the external ID code is scanned, the locker manager validates the external ID code using the validation codes. A valid external ID code may be used to rent and access lockers in the locker system. In some implementations, locker rights may be sold through the external system and details of the transaction provided to the locker manager. If the external ID code is valid, the locker manager generates a rental plan. |
| US09558606B2 |
System and method for integrating and adapting security control systems
A system for controlling access to one or more enclosed areas comprises at least one access card reader and controller powered via a Power-over-Ethernet (PoE) interface, each access card reader and controller being capable of controlling access through a particular entrance to a particular enclosed area and an access control server in communication with the at least one access card reader and controller, the access control server being capable of controlling the operation of the at least one access card reader and controller, and a signal converter disposed between the access card reader and the access control server. In a network mode of operation, the access control server is configured to perform authentication of a card identifier (ID) received from the at least one access card reader and controller and to signal the at least one access card reader and controller to unlock a door at the particular entrance to the particular enclosed area when the access control server has successfully authenticated the received card ID. In a standalone mode of operation, the at least one access card reader and controller is configured to perform local authentication of a received card ID independently of the access control server and to unlock a door at the particular entrance to the particular enclosed area when the at least one access card reader and controller has successfully authenticated the received card ID. |
| US09558603B2 |
Smartcard receiving device for providing a remote communication with switching means
The invention relates to a smartcard receiving device, comprising a contact interface (11) for communicating with the received smartcard (2); a remote communication interface (13) for communicating with a first remote device (3); a protocol bridge (12) designed to establish a transaction with the received smartcard (2) through the contact interface (11). The smartcard receiving device further comprises a communicating device detector (14, 15) adapted to detect a second remote device (5) communicating according to a remote communication protocol different from the communication protocol used by said remote communication interface (13). The protocol bridge (12) interrupts the transaction with the received smartcard (2) when the second remote device (5) communicating according to said different remote communication protocol is detected. |
| US09558600B2 |
Duty cycle recording system and method for estimation of damage and remaining life of drivetrain components
A duty cycle recording system and method is disclosed for a vehicle with a drivetrain having a plurality of components and sensors. The duty cycle recording system may include a control unit and communication link. The control unit may receive sensor readings, compute damage estimates for drivetrain components based on the readings, and compute estimated remaining life (ERL) estimates based on the damage estimates. The communication link may transmit the computed damage and ERL estimates. The control unit may sample transmission torque and speed sensor readings, and for each sample may populate a three-dimensional histogram of transmission torque and speed the vehicle has experienced. |
| US09558598B2 |
Providing communications between a vehicle control device and a user device via a head unit
A vehicle head unit may receive a request, from a user device and by the head unit, to establish communication with a control device of a vehicle. The control device may be in communication with the head unit via a vehicle communication network associated with the vehicle. The head unit may establish communication between the user device and the control device based on the received request. The head unit may forward a message between the user device and the control device based on the established communication. The message may be forwarded between the user device and the control device via the head unit. |
| US09558586B2 |
Method for estimating the opacity level in a scene and corresponding device
A method and device for estimating the opacity at a point of a scene lit by an area light source and comprising an object defined by a mesh and occluding some of the emitted light. In order to optimize the calculations for live estimation of the opacity, the method comprises sampling said area light source in a plurality of samples, for at least one sample of the plurality of samples and for at least one first mesh element of the occluding object visible from the at least one sample, generating one shadow plane per edge of the at least one first mesh element, estimating a opacity level depending on coefficients of projection in a function base from values representative of the opacity for a set of intersection points between at least one ray having for origin a viewpoint of the scene and shadow planes crossed by said at least one ray, depending on an angle formed by the normal associated with each shadow plane crossed and by said at least one ray. |
| US09558585B2 |
Hidden surface removal in graphics processing systems
A graphics processing pipeline 1 includes a rasteriser 3 that tests patches representing respective different regions of a render output against the edges of primitives 2 to determine if the primitive at least partially covers the patch and an early depth test stage 4 that performs early depth tests for primitives in respect of patches of the render output that the primitive has been found by the rasteriser at least partially to cover, by using depth test information 5 associated with a patch indicating the number and distribution of different depth value regions associated with the patch to determine the depth value region or regions associated with the patch that the primitive should be depth tested against, and then performing a depth test or tests for the primitive in respect of the respective determined depth value region or regions associated with the patch. |
| US09558582B2 |
Image processing method and image processing apparatus
An image processing method and an image processing apparatus which remove the effects of cosmic rays, noise and defective pixels without losing data in a specified time and which can correct image data efficiently and with high accuracy are provided. An image processing method of performing correction processing on an abnormal value of X-ray image data is provided which includes the steps of: (S3) determining whether or not there exists a target element with intensity significantly different from intensity of peripheral elements, in a three dimensional space formed with a space axis and a time axis defined by a series of captured image frames; and (S9) replacing the intensity of the target element with a replacement value calculated from the intensity of peripheral elements. |
| US09558581B2 |
Method for representing virtual information in a real environment
A method for representing virtual information in a view of a real environment is provided that includes the following steps: providing a system setup comprising at least one display device, determining a position of a viewing point relative to at least one component of the real environment, providing a geometry model of the real environment, providing at least one item of virtual information and its position, determining a visualization mode of blending in the at least one item of virtual information on the display device according to the position of the viewing point and the geometry model, calculating a ray between the viewing point and the item of virtual information, and determining a number of boundary intersections by the ray, wherein if the number of boundary intersections is less than 2, the item of virtual information is blended in a non-occlusion mode, otherwise in an occlusion mode. |
| US09558580B2 |
Image processing apparatus and method therefor
A first surface, a second surface, and a third surface are set in order in a direction of a scene, and the first surface has a plurality of cells and a plurality of sub-cells divided from each of the plurality of cells, the second surface has a plurality of segments, and the plurality of cells and the plurality of segments are associated respectively. A trace direction of a ray passing through each sub-cell is determined based on a segment associated with a cell including the sub-cell. Ray tracing on the determined trace direction is performed for each sub-cell so as to generate light-field data of the scene between the second and third surfaces. |
| US09558577B2 |
Rhythmic mosaic generation methods, apparatuses and media
A request to generate templates for a template set may be received. A template set member from the template set may be selected and the template set member's dimensions may be determined based on an initial cut. A desired number of image tiles for the template set member may be identified, and templates having the desired number of image tiles may be generated for the template set member based on logical rules. |
| US09558572B2 |
Visualization of data clusters
The disclosure generally describes computer-implemented methods, software, and systems, including a method for presenting information. A first graph is presented that represents plural groups, each representing an aggregated set of data points grouped based on a first set of common attributes. User input selecting a particular group is received. The aggregated set of data points is analyzed to determine whether the number of aggregated set of data points exceeds a threshold. In response to determining that the number exceeds the threshold, the aggregated set of data points is re-grouped. A second set of common attributes associated with the re-grouped set of data points is identified. The data points are aggregated based on the second set of common attributes. A second graph is provided for presentation, the updated graph representing plural groups, each group representing an aggregated subset of data points from the aggregated set of data points. |
| US09558571B2 |
Contour gradients using three-dimensional models
A method and systems of applying a contour gradient to a two-dimensional path are provided. A three-dimensional polygonal shell may be constructed from the two-dimensional path. Then the three-dimensional polygonal shell may be projected into two dimensions, resulting in a two-dimensional projected model, while saving values for a third dimension for each point in the two-dimensional projected model. Then a range of all values for the third dimension in the two-dimensional projected model is determined from the saved values. The range can then be mapped to a visual attribute. The two-dimensional projected model may be displayed using the mapped visual attribute. |
| US09558567B2 |
Palette prediction in palette-based video coding
In palette-based coding, a video coder may form a so-called “palette” as a table of colors representing the video data of a given block. The video coder may code index values for one or more pixels values of a current block of video data, where the index values indicate entries in the palette that represent the pixel values of the current block. According to the techniques, a video coder determines one or more palette entries in a predictive palette that are copied to the current palette, and a number of new palette entries not in the predictive palette that are included in the current palette. The video coder calculates a size of the current palette equal to the sum of the number of the copied palette entries and the number of the new palette entries, and generates the current palette including the copied palette entries and the new palette entries. |
| US09558563B1 |
Determining time-of-fight measurement parameters
In a system that monitors the positions and movements of objects within an environment, a depth camera may be configured to produce depth images based on configurable measurement parameters such as illumination intensity and sensing duration. A supervisory component may be configured to roughly identify objects within an environment and to specify observation goals with respect to the objects. The measurement parameters of the depth camera may then be configured in accordance with the goals, and subsequent analyses of the environment may be based on depth images obtained using the measurement parameters. |
| US09558556B2 |
Three-dimensional object detection device
A three-dimensional object detection device includes an image capturing unit, a detection area setting unit, an image conversion unit, a three-dimensional object detection unit, and a relative movement speed calculation unit. The detection area setting unit sets a detection area in a lateral direction rearward of the host vehicle. The image conversion unit converts a viewpoint of the images obtained by the image capturing unit to create bird's-eye view images. The three-dimensional object detection unit detects a presence of a three-dimensional object within the detection area by vehicle width direction detection processing. The detection area setting unit widens the detection area rearward with respect to a direction of vehicle progress when the three-dimensional object is detected in the detection area and the relative movement speed of the three-dimensional object, as calculated by relative movement speed calculation unit, is at a predetermined value or greater. |
| US09558554B1 |
Defining basis function requirements for image reconstruction
A system, method and computer program product for determining an accuracy of a reconstructed image relative to a reference image. The method includes decomposing a reference image into a plurality of basis functions; reconstructing the image using the plurality of basis functions; determining differences between the reference image and reconstructed image; using statistical parametric mapping (SPM) to quantify existence of statistically significant regions of excursion in the determined differences; determining, based on the quantified regions of excursion, a minimum number of basis functions to reconstruct the image; and storing the determined number. The difference image is used as input to a univariate statistical test at every pixel to calculate an image of the test statistic which is then modeled as a multiGaussian random field. Quantities are calculated from the test statistic image for comparison to expected values to determine if the reconstructed image is an accurate representation of the reference image, or whether the number of basis functions used in the reconstruction is to be increased. |
| US09558550B2 |
Method and system for the automatic analysis of an image of a biological sample
Method for the automatic analysis of an image of a biological sample with respect to a pathological relevance, wherein a)local features of the image are aggregated to a global feature of the image using a bag of visual word approach, b) step a) is repeated at least two times using different methods resulting in at least two bag of word feature datasets, c) computation of at least two similarity measures using the bag of word features obtained from a training image dataset and bag of word features from the image, d) the image training dataset comprising a set of visual words, classifier parameters, including kernel weights and bag of word features from the training images, e) the computation of the at least two similarity measures is subject to an adaptive computation of kernel normalization parameters and/or kernel width parameters, f) for each image one score is computed depending on the classifier parameters and kernel weights and the at least two similarity measures, the at least one score being a measure of the certainty of one pathological category compared to the image training dataset, g) for each pixel of the image a pixel-wise score is computed using the classifier parameters, the kernel weights, the at least two similarity measures, the bag of word features of the image, all the local features used in the computation of the bag of word features of the image and the pixels used in the computations of the local features, h) the pixel-wise score is stored as a heatmap dataset linking the pixels of the image to the pixel-wise scores. |
| US09558548B2 |
Method, system, and computer program product for detection of defects based on multiple references
A system includes a memory and a processor device operatively coupled to the memory to obtain an inspected noise-indicative value representative of an analyzed pixel of an inspected image of an inspected object, and a reference noise-indicative value representative for each of multiple reference pixels of the inspected image. The processor device computes a representative noise-indicative value based on the inspected noise-indicative value and multiple reference noise-indicative values, calculates a defect-indicative value based on an inspected value representative of the analyzed pixel and determines a presence of a defect in the analyzed pixel based on the representative noise-indicative value and the defect-indicative value. |
| US09558546B2 |
Three-dimensional object detection device, and three-dimensional object detection method
A three-dimensional object detection device has an image capturing unit, an object detection unit, a nighttime assessment unit, a luminance detection unit, a luminance peak detection unit and a controller. The image capturing unit captures images rearward of a vehicle. The object detection unit detects a presence of an object from the captured images. The nighttime assessment unit assesses if nighttime has fallen. The luminance detection unit detects a luminance of image areas from the captured image. The luminance peak detection unit detects a peak in the luminance having a luminance gradient that is greater than or equal to a predetermined reference value from among the detected peaks in the luminance as a target luminance peak. The controller controls detection of the object in an image area in which the target luminance peak is detected when an assessment has been made that nighttime has fallen by the nighttime assessment unit. |
| US09558540B2 |
Display instrument and image display method
A head-mounted display device including an image display apparatus configured to display a captured image of a portion of an environment viewable through the head-mounted display device; and a dimmer configured to, while the captured image is displayed, allow a portion of ambient light from the environment to pass through the dimmer. Also, a method of displaying information on a head-mounted display device. The method may include displaying a captured image of a portion of an environment viewable through the display device; and dimming ambient light received through the head-mounted display device from the environment while displaying the captured image. |
| US09558538B2 |
Dynamic range converter with frame by frame adaptation and methods for use therewith
In various embodiments, a dynamic range converter includes a first color space converter to convert a source color space of a source video having a source dynamic range to nonlinear color space signals. A linearizer configured converts the nonlinear color space signals to linearized color space signals having a mastering dynamic range via a piecewise linear interpolation of a transfer function. A color volume transformer applies dynamic color transform metadata associated with the source video on a frame by frame basis to generate master adjusted color space signals from the linearized color space signals. A delinearizer converts the master adjusted color space signals to nonlinearized color space signals via a piecewise linear interpolation of an inverse transfer function in accordance with a display dynamic range. A second color space converter converts the nonlinearized color space signals to display domain signals. Other embodiments are disclosed. |
| US09558531B2 |
Graphics processing method for three-dimensional images applied to first buffer for storing right-view contents and second buffer for storing left-view contents and related graphics processing apparatus thereof
A graphics processing method for three-dimensional images, applied to a first buffer for storing right-view contents and a second buffer for storing left-view contents, includes the following steps: when a current Vsync status indicates that a display engine is not operating within a right Vsync period of a right-view frame, the drawing engine drawing the right-view contents stored in first buffer; when current Vsync status indicates that the display engine is not operating within a left Vsync period of a left-view frame, the drawing engine drawing the left-view contents stored in second buffer; during the right Vsync period of the right-view frame, the display engine displaying right-view contents stored in first buffer; and during the left Vsync period of the left-view frame, the display engine displaying left-view contents stored in second buffer. |
| US09558527B2 |
Systems and methods for orchestrating external graphics
Systems and methods that may be implemented to orchestrate external graphics, for example to support and extend switchable graphics capability beyond internal system components of a host information handling system so as to include an external discrete graphics processing unit (xGPU) that is not integrated or embedded within the chassis enclosure of the host information handling system, and that is coupled to the host information handling system from outside the host system chassis enclosure. |
| US09558526B2 |
Signal continuity assessment using embedded watermarks
Methods, apparatus, and systems for signal continuity assessment using embedded watermarks are provided. The embedded watermarks are recovered from the content and one or more attributes associated with the recovered watermarks are identified. A continuity of the content can then be assessed in accordance with the one or more attributes. The continuity assessment may be based on a variety of factors, including but not limited to a determined heartbeat of the recovered watermarks, a density, separation, location, or extent, of the recovered watermarks, as well as information associated with the watermarks, such as a stego key, channel bits, packet numbers, a fingerprint, or the like. |
| US09558524B2 |
Risk assessment using social networking data
Tools, strategies, and techniques are provided for evaluating the identities of different entities to protect individual consumers, business enterprises, and other organizations from identity theft and fraud. Risks associated with various entities can be analyzed and assessed based on analysis of social network data, professional network data, or other networking connections, among other data sources. In various embodiments, the risk assessment may include calculating an authenticity score based on the collected network data. |
| US09558523B1 |
Secure nonscheduled video visitation system
Described are methods and systems in which the censorship and supervision tasks normally performed by secured facility personnel are augmented or automated entirely by a Secure Nonscheduled Video Visitation System. In embodiments, the Secure Nonscheduled Video Visitation System performs voice biometrics, speech recognition, non-verbal audio classification, fingerprint and other biometric authentication, image object classification, facial recognition, body joint location determination analysis, and/or optical character recognition on the video visitation data. The Secure Nonscheduled Video Visitation utilizes these various analysis techniques in concert to determine if all rules and regulations enforced by the jurisdiction operation the secured facility are being followed by the parties to the video visitation session. |
| US09558522B2 |
Centralized licensing system
A request to activate a license file is received by a licensing system. The license file comprises a number of licenses. A license may be any type of license. The license file is assigned a license file identifier. A license extension is assigned to the license file identifier. A request to acquire a portion (or all) of the number of licenses of the license file is received from an entity. The portion (or all) of the number of licenses of the license file is assigned to the entity based on the license extension. The entity can then use the licenses as necessary. |
| US09558519B1 |
Exposing reporting cycle information
A computing device is configured to acquire or access credit or reporting data associated with a consumer. The computing device then is configured to analyze the credit or reporting data to determine reporting cycles for accounts associated with the consumer. For example, the computing device may determine that credit information for a particular account may be updated at a regular interval (e.g., once a month on the 3rd) or some other more complex cycle. The computing device can subsequently used the determined reporting cycles to predict the next reporting dates for respective accounts and provide the information, for instance, to the consumer. |
| US09558516B2 |
Social mobile shopping system
Methods and system are provided for enhancing consumer shopping. The methods and systems allow consumers to more readily purchase products of interest to them. The consumers' ability to shop effectively and efficiently is enhanced while a payment provider, such as PayPal, Inc., and/or an online seller, such as eBay, is given a mechanism for recruiting new users. For example, a user's online searches and/or stored shopping list can be used to determine which products the user is interested in purchasing and the availability of at least some of these products can be provided to the user, along with directions to the nearest POS brick-and-mortar stores where the products can be purchased. |
| US09558509B2 |
Social networking system data exchange
An online publisher provides content items such as advertisements to users. To enable publishers to provide content items to users who meet targeting criteria of the content items, an exchange server aggregates data about the users. The exchange server receives user data from two or more sources, including a social networking system and one or more other service providers. To protect the user's privacy, the social networking system and the service providers may provide the user data to the exchange server without identifying the user. The exchange server tracks each unique user of the social networking system and the service providers using a common identifier, enabling the exchange server to aggregate the users' data. The exchange server then applies the aggregated user data to select content items for the users, either directly or via a publisher. |
| US09558507B2 |
Reminding users of offers
Provided is a computer implemented process for reminding users of offers that were discovered by the user at one location when, at a later time, the user is at another location, the process including: displaying, with a mobile device, an offer and a reminder interface to indicate that the user requests themselves or another reminder recipient to be reminded of the offer when near another computing device of the reminder recipient; receiving an interaction with the reminder interface by the user and, in response, storing a reminder request in memory, the reminder request identifying the offer; obtaining data identifying the other computing device, a geographic area of the other computing device, or a wireless environment of the other computing device; detecting, with a processor of the mobile device, that the reminder recipient has interacted with the other computing device, entered the geographic area, or entered the wireless environment; and in response to the detection, presenting a notification reminding the reminder recipient of the offer. |
| US09558506B2 |
System and method for exploring new sponsored search listings of uncertain quality
According to some example embodiments, a method includes calculating learning values associated with a plurality of listings, at least one of said learning values associated with one of said listings representing a value based, at least in part, on a probability distribution of selections of said listing. The method further includes applying said learning values to ranking scores associated with said listings to provide an updated ranking, and electronically auctioning advertising inventory to purchasers associated with said listings based, at least in part, on said updated ranking. |
| US09558505B2 |
System and method for prepaid rewards
A system and method provide rewards or loyalty incentives to card member customers. The system includes an enrolled card member customer database, an enrolled merchant database, a participating merchant offer database and a registered card processor. The enrolled card member customer database includes transaction accounts of card member customers enrolled in a loyalty incentive program. The enrolled merchant database includes a list of merchants participating in the loyalty incentive program. The participating merchant offer database includes loyalty incentive offers from participating merchants. The registered card processor receives a record for charge for a purchase made with an enrolled merchant by an enrolled card member customer and uses the record of charge to determine whether the purchase qualifies for a rebate credit in accordance with a discount offer from the enrolled merchant. If the purchase qualifies for a rebate credit, the registered card processor provides the rebate credit to an account of the enrolled card member customer. The registered card processor also provides for electronic notification of rewards offers or credit to prepaid cards, in response to purchases conforming to a specific set of merchant criteria. The system provides a coupon-less way for merchants to provide incentive discounts and/or credits to enrolled customers, along with notifying customers of other available incentive offers. |
| US09558501B2 |
Content recommendation system, content recommendation method, content recommendation apparatus, program, and information storage medium
A content recommendation system including a step which selects some from a plenty of music compositions in accordance with attribute conditions successively generated, a step which further selects a part or all of the selected music compositions in accordance with the similarity degree between the feature vector of each of the selected music compositions and the user preference vector, and a step which presents the selected music composition to the user. |
| US09558500B2 |
Method and apparatus for providing internet advertising service
A method and apparatus for providing advertising service in a computer network is provided. This method and apparatus further comprises receiving a request from a user via this computer network to view a Web page, providing conditions to the user for viewing this Web page, delivering this Web page to the user, determining if the user has met the conditions required for viewing this Web page, and terminating access of the user to this Web page if these conditions are not met. |
| US09558498B2 |
System and method for advertisement management
The present invention relates to systems and methods for optimizing and managing advertising campaigns. The method of the present invention comprises storing one or more advertisement data structures associated with an ad group data structure in the ad group data structure. One or more ad group data structures associated with a campaign data structure are stored in an ad campaign data structure. Additionally, one or more ad campaign data structures associated with an advertised property are stored in an account data structure. |
| US09558497B2 |
System and method for internet domain name fraud risk assessment
Internet Domain Name Fraud Risk Assessment using a system of data element collection and computation. Data elements associated with the Internet Domain Name are acquired from internal and external data sources, captured, evaluated, and then assigned a value. Data acquisition may include use of domain information, databases, corporate and social media services, and search engine services. Using the assigned values, an Internet Domain Name category type and a Fraud Risk Score are computed and then displayed to a user along with additional information, explanations and recommendations. |
| US09558493B2 |
Secure authorizations using independent communications and different one-time-use encryption keys for each party to a transaction
A registered provider device encrypts provider input related to a transaction between the provider device and one of many registered user devices to create an encrypted one-time-use provider code (the encryption is performed using an encryption key produced, in part, using a uniquely sequenced number generated by a sequencer maintained by the provider device). Similarly, a provider institution app encrypts user input to create an encrypted one-time-use user code using an encryption key produced, in part, using a uniquely sequenced number generated by a user sequencer maintained by the user device. The provider and provider institution app independently transmit their different encrypted one-time-use codes to an intermediate entity, which decrypts the encrypted codes using one-time-use encryption keys produced using sequencers maintained by the intermediate entity. This decryption generates an authorization request. The intermediate entity obtains an authorization decision regarding the authorization request from the authorization entity. |
| US09558492B2 |
Secure authorizations using independent communications and different one-time-use encryption keys for each party to a transaction
A registered provider device encrypts provider input related to a transaction between the provider device and one of many registered user devices to create an encrypted one-time-use provider code (the encryption is performed using an encryption key produced, in part, using a uniquely sequenced number generated by a sequencer maintained by the provider device). Similarly, the user device encrypts user input to create an encrypted one-time-use user code using an encryption key produced, in part, using a uniquely sequenced number generated by a user sequencer maintained by the user device. The provider and user devices independently transmit their different encrypted one-time-use codes to an intermediate entity, which decrypts the encrypted codes. This decryption is performed using one-time-use encryption keys produced using sequencers maintained by the intermediate entity, and this decryption generates an authorization request. The intermediate entity obtains an authorization decision regarding the authorization request from the authorization entity. |
| US09558487B2 |
Public transit system fare processor for multi-balance funding
An implementation of a system and method for processing transfer rides associated with at least one public transit network is provided. The system and method preprocess transactions to consolidate or eliminate unnecessary transactions with a financial institution clearing and settlement network. |
| US09558485B2 |
Two step near field communication transactions
A two step method for transferring money from a sender to a recipient includes entering information relating to the transfer into a near field communication (NFC) enabled device of the sender. The device is then placed in contact with or close proximity to a recipient's device a first time, causing the sender's device to establish an NFC link between the two devices and to gather information relating to the recipient via the NFC link. The sender's device is then placed in contact with or close proximity to the recipient's device a second time, causing it to transmit the information relating to the transfer and the recipient to a third party service provider via another network, e.g., the Internet, thereby causing the service provider to transfer the money from an account of the sender to an account of the recipient. |
| US09558483B2 |
Systems and methods for transferring value to payment accounts
Systems and methods are provided for transferring value from to a payment account associated with a virtual wallet of a consumer. The value can be transferred using voucher-based transactions or cash-based transactions. One exemplary method includes receiving, at a computing device, a load request to transfer value to a payment account associated with a consumer. The load request includes the value to be transferred and a directory number for a mobile device associated with the consumer. The method also includes determining an account number for the consumer's payment account, at the computing device, based on the directory number for the consumer's mobile device and generating, by the computing device, a request indicating the value to transfer to the payment account and the account number for the consumer's payment account. |
| US09558478B2 |
Multi-platform in-application payment system
Systems and methods for providing multi-platform, in-application payments include transferring funds, by a payment service provider device, from a funding source to a payment account in response to receiving a first fund transfer instruction from one of a first user device and a second user device over a network. The payment service provider device then associates the payment account with a first platform application in response to receiving a first association instruction from the first user device over the network, and associates the payment account with a second platform application in response to receiving a second association instruction along with the user account information from a second user device over the network. The payment service provider device will pay for each of a first in-application purchase associated with the first platform application and a second in-application purchase associated with the second platform application using the payment account. |
| US09558476B2 |
Method and device for editing workspace data objects
Disclosed herein are methods and devices for associating a first workspace data object with a first workspace service and for determining characteristics of the association of the first workspace data object with the first workspace service. The methods and devices described herein relate to receiving touch-screen based input in a plurality of display areas of a display to make the associations. |
| US09558470B2 |
System and method for managing inventory of consumable articles
Restocking cards with machine readable tags are placed on article packaging in a supply room. When an employee wishes to order an article, the employee removes the restocking card from the article packaging and presents the restocking card to a container equipped with a machine readable tag reader. The machine readable tag of the restocking card enables the container to generate an order for a predefined quantity of the identified article. The order is sent to a central stock server which processes the order and sends it to the appropriate fulfillment server. |
| US09558464B2 |
System and method to determine defect risks in software solutions
A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive one or more risk factors, receive one or more contexts, identify one or more context relationships and associate the one or more contexts with the one or more risk factors. Additionally, the programming instructions are operable to map the one or more risk factors for an associated context to a software defect related risk consequence to determine a risk model and execute a risk-based testing based on the risk model to determine a defect related risk evaluation for a software development project. |
| US09558456B2 |
Entity analysis system
A method for building a factual database of concepts and entities that are related to the concepts through a learning process. Training content (e.g., news articles, books) and a set of entities (e.g., Bill Clinton and Barack Obama) that are related to a concept (e.g., Presidents) is received. Groups of words that co-occur frequently in the textual content in conjunction with the entities are identified as templates. Templates may also be identified by analyzing parts-of-speech patterns of the templates. Entities that co-occur frequently in the textual content in conjunction with the templates are identified as additional related entities (e.g., Ronald Reagan and Richard Nixon). To eliminate erroneous results, the identified entities may be presented to a user who removes any false positives. The entities are then stored in association with the concept. |
| US09558455B2 |
Touch classification
A method for touch classification includes obtaining frame data representative of a plurality of frames captured by a touch-sensitive device, analyzing the frame data to define a respective blob in each frame of the plurality of frames, the blobs being indicative of a touch event, computing a plurality of feature sets for the touch event, each feature set specifying properties of the respective blob in each frame of the plurality of frames, and determining a type of the touch event via machine learning classification configured to provide multiple non-bimodal classification scores based on the plurality of feature sets for the plurality of frames, each non-bimodal classification score being indicative of an ambiguity level in the machine learning classification. |
| US09558453B1 |
Forecasting leaks in pipeline network
Technical solutions are described for forecasting leaks in a pipeline network. An example method includes identifying a subsystem in the pipeline network that includes a first station. The method also includes accessing historical temporal sensor measurements of the stations. The method also includes generating a prediction model for the first station that predicts a pressure measurement at the first station based on the historical temporal sensor measurements at each station in the subsystem. The method also includes predicting a series of pressure measurements at the first station based on the historical temporal sensor measurements. The method also includes determining a series of deviations between the series of pressure measurements and historical pressure measurements of the first station and identifying a threshold value from the series of deviations, where a pressure measurement at the first station above or below the threshold value is indicative of a leak in the subsystem. |
| US09558443B2 |
Dual deterministic and stochastic neurosynaptic core circuit
One embodiment provides a system comprising a memory device for maintaining deterministic neural data relating to a digital neuron and a logic circuit for deterministic neural computation and stochastic neural computation. Deterministic neural computation comprises processing a neuronal state of the neuron based on the deterministic neural data maintained. Stochastic neural computation comprises generating stochastic neural data relating to the neuron and processing the neuronal state of the neuron based on the stochastic neural data generated. |
| US09558441B2 |
Legacy application migration to real time, parallel performance cloud
A system and method 10 that provides legacy software applications 12 to be incorporated into a massively parallel and distribution processing model in the Cloud, with a high performance parallel and distributed computing (cloud) “wrapper” 14 around legacy and current systems to enable, without legacy product code change or invasive addition/editing, the legacy product to access and fully utilize the power and ability of distributed computing within the cloud through a Pneuron “cortex” platform virtual server 10. The system and method also provides the ability to distribute multiple, concurrent instances of the legacy applications, dynamically manage the load volumes, and automatically create and remove new virtual machines based upon demand requirements. |
| US09558437B2 |
Systems for and methods of communicating barcode information to point-of-sale terminal
A method of communicating barcode information using audio signaling is disclosed. A mobile device being brought into physical proximity to a communication bridge device is detected. Two-way audio communication is commenced between the mobile device and the bridge device upon detection of the mobile device by the bridge device. Barcode information is communicated from the mobile device to the bridge device. The barcode information is converted into a pulsed signal to simulate scanning of a static image of a barcode. A human perceptible signal is provided that indicates the barcode information has been received into the bridge device. The barcode information is transmitted as light pulses emitted from the bridge device for reception by a barcode scanner. |
| US09558436B2 |
Coded light pattern having hermitian symmetry
A method includes identifying one or more codewords of a bit sequence that fail to satisfy at least one codeword constraint. The method also includes removing the one or more codewords from the bit sequence to generate a punctured bit sequence. The method further includes determining whether the punctured bit sequence is symmetric. The method includes, in response to determining that the punctured bit sequence is symmetric, generating a hermitian symmetric codebook primitive based at least in part on the punctured bit sequence, where the hermitian symmetric codebook primitive is useable to form a diffractive optical element (DOE) of a structured light depth sensing system. |
| US09558433B2 |
Image processing apparatus generating partially erased image data and supplementary data supplementing partially erased image data
An image processing apparatus acquires target image data generated by optically reading a sheet. The sheet includes an original image and an added image. The added image is added on the sheet. The apparatus specifies, from the target image, an added region surrounded by a surrounding line. The apparatus specifies a written target in the added region. The apparatus generates partially-erased image data and supplementary data by using the target image data and a result of the specifying of the written target. The partially-erased image data represents a partially-erased image that is based on the target image with an image inside the added region being erased. The supplementary data concerns the added image. The apparatus generates an image file including the partially-erased image data and the supplementary data so that the partially-erased image and supplementary information can be reproduced in selective one of a simultaneous manner and an independent manner. |
| US09558430B2 |
Image forming apparatus using filters to correct potential distribution on photoreceptor due to spot shape of emitted light
The image forming apparatus includes an exposure head. The exposure head includes an organic EL element array and a rod lens array, and forms an image on a photosensitive drum by irradiating light emitted from each organic EL element on the photoreceptor via each rod lens. In the exposure head, light emitting from the organic EL element is controlled by a controller. The controller generates a filter coefficient for correcting a spot shape based on the difference between the spot shape of the light spot on the photosensitive drum and the target spot shape on the photosensitive drum. It is noted that the difference is generated by the deviation between the distance from the organic EL element to the photosensitive drum, and the correct focus position. |
| US09558427B2 |
Shape similarity measure for body tissue
A shape similarity metric can be provided that indicates how similar two or more shapes are. A difference between a union of the shapes and an intersection of the shapes can be used to determine the similarity metric. The shape similarity metric can provide an average distance between the shapes. Different processes for determining shapes can be evaluated for accuracy based on the shape similarity metric. New or alternative shape-determining processes can be compared for accuracy against other shape-determining processes including reference shape-determining processes. Shape similarity metrics can be determined for two-dimensional shapes and three-dimensional shapes. |
| US09558422B2 |
Methods and systems for differentiating synthetic and non-synthetic images
The techniques introduced here include a system and method for transcoding multimedia content based on the results of content analysis. The determination of specific transcoding parameters, used for transcoding multimedia content, can be performed by utilizing the results of content analysis of the multimedia content. One of the results of the content analysis is the determination of image type of any images included in the multimedia content. The content analysis uses one or more of several techniques, including analyzing content metadata, examining colors of contiguous pixels in the content, using histogram analysis, using compression distortion analysis, analyzing image edges, or examining user provided inputs. Transcoding the multimedia content can include adapting the content to the constraints in delivery and display, processing and storage of user computing devices. |
| US09558416B2 |
Method and system for replaying a voice message and displaying a signed digital photograph contemporaneously
Disclosed are methods and systems for generating digital fantasy sports memorabilia including: providing a digital fantasy sports memorabilia signor with a digital fantasy sports photograph, a digital fantasy sports jersey, or a combination thereof; receiving at least one of an electronic signature or an electronic written message from the fantasy sports digital memorabilia signor to be embedded in the digital fantasy sports photograph, the digital fantasy sports jersey, or the combination thereof; embedding the at least one of an electronic signature or an electronic written message from the digital fantasy sports memorabilia signor into the digital fantasy sports photograph, the digital fantasy sports jersey, or a combination thereof to form the generated digital fantasy sports memorabilia; sending the generated digital fantasy sports memorabilia including the electronic signature and the electronic written message to a verification service to verify authenticity of the electronic signature and electronic written message in the generated digital fantasy sports memorabilia; and delivering the generated fantasy sports memorabilia to a digital fantasy sports receiver. |
| US09558415B2 |
Biometric authentication technology
Biometric authentication technology, in which biometric data is maintained for a group of people. The biometric data includes sorted similarity scores, where each of the sorted similarity scores is computed to represent similarity between a corresponding biometric image and a reference image. A biometric verification system accesses a biometric image of at least a portion of a person, accesses the reference image, and computes a similarity score that represents similarity between the accessed biometric image and the reference image. The biometric verification system searches the sorted similarity scores included in the biometric data using the computed similarity score and outputs a result based on the searching. |
| US09558410B2 |
Road environment recognizing apparatus
A road environment recognizing apparatus includes an edge image generator, a first area extractor, and an object recognizer. The edge image generating unit generates an edge image by extracting edge points from an image of a road captured by a camera. The edge points have amounts of change in luminance from surroundings, which are higher than or equal to a predetermined value. The first area extractor extracts a first area from the edge image. The first area is partitioned by the edge points and has a luminance higher than the luminances of the surroundings. If a second area having a luminance lower than the luminances of the surroundings exists around the first area in the edge image, the object recognizer recognizes a projection on the road on the basis of a third area resulting from joining of the first area and the second area. |
| US09558409B2 |
Vehicle vision system with trailer angle detection
A vehicular vision system includes at least one camera and an image processor. The camera is disposed at a vehicle and has an exterior field of view rearward of the vehicle. The camera is operable to capture image data. The image processor is operable to process captured image data. The vision system, responsive at least in part to image processing of captured image data, is operable to determine a trailer angle of a trailer that is towed by the vehicle. The vision system is operable to determine a path of the trailer responsive to a steering angle of the vehicle and the vision system is operable to display information for viewing by the driver to assist the driver in driving the vehicle with the trailer. |
| US09558406B2 |
Image processing apparatus including an object setting section, image processing method, and program using the same
An image processing apparatus includes: an object setting section that sets an object image indicating an object which is placed in an image generated by an image capturing section; a detection section that detects the object included in a synthetic image in which the object image and the image generated by the image capturing section are synthesized; and an output section that outputs output information for setting a detection parameter used in a detection process performed by the detection section, that is, output information in which the synthetic image and a detection result of the detection process are associated. |
| US09558404B2 |
Method and device for filtering electrical consumption curves and allocating consumption to classes of appliances
The invention relates to a method for analyzing the electrical consumption of a plurality of electrical appliances operating on a consumption site, by filtering a demand curve representing the electrical consumption of said appliances according to time. Said method is characterized in that it comprises the following steps: before the filtering per se of the demand curve, the demand curve is recorded and digitalized in such a way as to obtain a demand curve digitalized by periods of time; a set of categories of appliances is defined, each category being defined by similar cycles of power variation according to the time; an algorithm is defined for each category of appliances, for filtering the demand curve for said category of appliances, said algorithm being able to extract the power variation cycles from the digitalized demand curve and to allocate the electrical consumption to said category of appliances; then during the filtering per se of the digitalized demand curve, the filtering algorithms for each category of appliance are used successively to identify and regroup the power variation cycles consumed by said electrical appliances, from the digitalized demand curve. |
| US09558403B2 |
Chemical structure recognition tool
A method of extracting and then reusing/remodeling chemical data from a hand written or digital input image without manual inputs using Chemical Structure Recognition Tool (CSRT) is disclosed herein. It comprises loading said input image, converting said input image into a grayscale image i.e. stretching of loaded input image, converting said grayscale image into a binary image i.e. binarization, smoothing to reduce noise within said binary image, recognizing circle bond to identify presence of a circle inside a ring, predicting OCR region to find zones containing text, image thinning to identify specific shapes within said binary image, edge detection to detect image contrast, detecting double and triple bond, and obtaining output files. |
| US09558401B2 |
Scanbox
Embodiments are provided for content item classification. In some embodiments, an image for classification is received, a compact representation for the image having values indicative of pixel values within the received image is generated, a plurality of angle measurements for possible edges of at least one potential document within the received image are determined, and the image is classified using said compact representation and said plurality of angle measurements. |