最新美国发明专利第2017-01-10期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US09543565B2	Actinic and electron beam radiation curable electrode binders and electrodes incorporating same A process for manufacturing an electrode utilizing electron beam (EB) or actinic radiation to cure electrode binding polymers is provided. A process is also disclosed for mixing specific actinic or EB radiation curable chemical precursors with electrode solid particles, application of the mixture to an electrode current collector, followed by the application of actinic or EB radiation to the current collector for curing the polymer, thereby binding the electrode material to the current collector. Lithium ion batteries, electric double layer capacitors, and components produced therefrom are also provided.
US09543564B2	Protective coatings for conversion material cathodes Battery systems using coated conversion materials as the active material in battery cathodes are provided herein. Protective coatings may be an oxide, phosphate, or fluoride, and may be lithiated. The coating may selectively isolate the conversion material from the electrolyte. Methods for fabricating batteries and battery systems with coated conversion material are also provided herein.
US09543555B2	Battery module A battery module including a plurality of unit cells, a plurality of bus bars electrically connecting the plurality of unit cells, a positive electrode terminal and a negative electrode terminal that are electrically connected and in contact with two ends of the plurality of unit cells, a battery housing accommodating the plurality of unit cells and the bus bars, and detection terminals that are respectively electrically connected to the plurality of bus bars, wherein the detection terminals are exposed outside the battery housing. Accordingly, voltage balancing between the unit cells may be controlled without disassembling the battery module.
US09543554B2	Battery device that holds batteries A battery holder includes restriction members protruded from a holding base plate in an axial direction of batteries to be located in spaces between the batteries. Each of the restriction members has: a tapered surface which is inclined to the axial direction and is in line contact with an outer periphery of the end face of the battery when the restriction member is inserted into the space, so as to apply a force to move the battery in a radial direction of the battery; and a support surface which supports a side face of the battery that is not in contact with the tapered surface, by surface contact. The support surface receives a moving force in the radial direction from the tapered surface and supports the side face of the battery by a reactive force.
US09543553B2	Sealing member and battery comprising the same A sealing member and a battery comprising the sealing member are provided. The sealing member comprises a sealing part, an operation part having a supporting portion, an operation protrusion disposed on an upper surface of the supporting portion, and a deformable leg depending from a bottom surface of the supporting portion. The sealing member also comprises a connecting part connecting the sealing part and operation part. The sealing part has a maximum diameter greater than that of the connecting part.
US09543549B2	Adhesive tape for encapsulating an organic electronic arrangement The invention relates to a method for protecting an electronic arrangement which is disposed on a substrate and comprises organic constituents, where a cover is applied to the electronic arrangement in such a way that the electronic arrangement is at least partly covered by the cover, the cover being bonded at least over a partial area to the substrate and/or to the electronic arrangement, the adhesive bond being produced by means of at least one layer of an adhesive in an adhesive tape, characterized in that the adhesive comprises a getter material which is capable of at least one permeable substance, the getter material being present in the adhesive in a proportion of not more than 2 wt %, based on the adhesive with the getter material.
US09543545B2	Display substrate with bragg reflection unit for each of the display units of at least three primary colors The present invention relates to the technical field of display, and provides a display substrate and a preparing method thereof which can solve the problem of lower light-emitting efficiency of the display substrate in the prior art. The display substrate of the present invention comprises a plurality of display units of at least two different colors. The display substrate further comprises a plurality of bragg reflection units in different regions corresponding to respective display units, each bragg reflection unit comprises first structural layer and second structural layer which are alternately stacked with each other and have different refractive indexes; thickness of each of the first and second structural layers is ¼n wavelength of incident light from corresponding display unit, wherein n is refractive index of the first or the second structural layer. The display substrate of the present invention has higher light-emitting efficiency and is applicable to full-color display.
US09543541B1	Optoelectronic component and method for the production thereof A method for producing an optoelectronic component includes forming an optoelectronic layer structure including a functional layer structure above a carrier, forming a frame structure including a first metallic material on the optoelectronic layer structure such that a region above the functional layer structure is free of the frame structure and that the frame structure surrounds the region, forming an adhesion layer including a second metallic material above a covering body, applying a liquid first alloy to the optoelectronic layer structure and/or to the adhesion layer of the covering body in the region, coupling the covering body to the optoelectronic layer structure such that the adhesion layer is coupled to the frame structure and the liquid first alloy is in direct contact with the adhesion layer and the frame structure, and reacting part of the first alloy chemically with the metallic materials of the frame structure and the adhesion layer.
US09543537B2	Solution processed metal oxide thin film hole transport layers for high performance organic solar cells A method for the application of solution processed metal oxide hole transport layers in organic photovoltaic devices and related organic electronics devices is disclosed. The metal oxide may be derived from a metal-organic precursor enabling solution processing of an amorphous, p-type metal oxide. An organic photovoltaic device having solution processed, metal oxide, thin-film hole transport layer.
US09543536B2	Organic molecular memory An organic molecular memory in an embodiment includes a first conducive layer, a second conductive layer, and an organic molecular layer provided between the first conductive layer and the second conductive layer, the organic molecular layer having an organic molecule, the organic molecule having a linker group bonded to the first conductive layer, a π conjugated chain bonded to the linker group, and a phenyl group bonded to the π conjugated chain opposite to the linker group and facing the second conductive layer, the π conjugated chain including electron-accepting groups or electron-donating groups arranged in line asymmetry with respect to a bonding direction of the π conjugate chain, the phenyl group having substituents R0, R1, R2, R3, and R4 as shown in the following formula, the substituent R0 being an electron-accepting group or an electron-donating group.
US09543535B1	Self-aligned carbon nanotube transistor including source/drain extensions and top gate A carbon nanotube semiconductor device includes at least one carbon nanotube disposed on an insulator portion of a substrate. The at least one carbon nanotube includes a non-doped channel portion interposed between a first doped source/drain portion and a second doped source/drain portion. A first source/drain contact stack is disposed on the first doped source/drain portion and an opposing second source/drain contact stack is disposed on the second doped source/drain portion. A replacement metal gate stack is interposed between the first and second source/drain contact stacks, and on the at least one carbon nanotube. The first and second doped source/drain portions are each vertically aligned with an inner edge of the first and second contact stacks, respectively.
US09543533B2	Display device One embodiment of the present invention provides a highly reliable display device. In particular, a display device to which a signal or a power supply potential can be supplied stably is provided. Further, a bendable display device to which a signal or a power supply potential can be supplied stably is provided. The display device includes, over a flexible substrate, a display portion, a plurality of connection terminals to which a signal from an outside can be input, and a plurality of wirings. One of the plurality of wirings electrically connects one of the plurality of connection terminals to the display portion. The one of the plurality of wirings includes a first portion including a plurality of separate lines and a second portion in which the plurality of lines converge.
US09543532B2	Organic electroluminescent materials and devices Novel organic compounds comprising a substituted anthracene or acridine ligand are provided. In particular, the compound includes an anthracene ligand substituted at the 9 and 10 positions. The compound may be used in organic light emitting devices to provide devices having improved efficiency and lifetime. In particular, these compounds may be especially beneficial for use in blue-emitting OLEDs.
US09543530B2	Compound for organic optoelectronic device, organic light emitting diode including the same and display including the organic light emitting diode A compound for an organic optoelectronic device and an organic photoelectric device including the same are provided. A compound for an organic optoelectronic device represented by Chemical Formula 1 is provided to fabricate an organic photoelectric device having excellent electrochemical and thermal stability and life-span characteristics, and high luminous efficiency at a low driving voltage.
US09543529B2	Compounds containing electron rich and electron deficient regions and their use in organic electronic applications Disclosed are semiconducting or conducting organic small molecules, oligomers, and polymers that are based on a donor-acceptor strategy featuring heavy group 16 elements (Se and Te) at the core of acceptor unit(s). The small molecules, oligomers, and polymers can have the following generic structure and can be used in areas such as organic electronic materials and devices:
US09543524B2	Compounds and organic electronic device using same The present invention provides a new compound and an organic electronic device using the same. The compound according to the present invention may serve as hole injection, hole transporting, electron injection and transporting, and light emitting materials and the like in an organic electronic device comprising an organic light emitting device, and the organic electronic device according to the present invention shows excellent properties in terms of efficiency, driving voltage and service life.
US09543519B2	Deposition apparatus and method of manufacturing organic light-emitting display apparatus Provided are a deposition apparatus and a method of manufacturing an organic light-emitting display (OLED) apparatus, which are capable of reducing manufacturing time and manufacturing costs of the OLED apparatus. The method includes: turning a substrate such that a deposition surface of the substrate faces upward; depositing a first deposition layer on a deposition surface of a first donor mask while the deposition surface of the first donor mask faces downward; arranging the first donor mask and the substrate such that the first donor mask is above the substrate while the first deposition layer faces downward and the deposition surface of the substrate faces upward; depositing, on the deposition surface of the substrate, a part of the first deposition layer of the deposition surface of the first donor mask; and turning the substrate such that the deposition surface of the substrate faces downward.
US09543514B2	Memory component, memory device, and method of operating memory device A memory component including first and second electrodes with a memory layer therebetween, the memory layer having first and second memory layers, the first memory layer containing aluminum and a chalcogen element of tellurium, the second memory layer between the first memory layer and the first electrode and containing an aluminum oxide and at least one of a transition metal oxide and a transition metal oxynitride having a lower resistance than the aluminum oxide.
US09543511B2	RRAM device The present disclosure relates to an integrated circuits device having a RRAM cell, and an associated method of formation. In some embodiments, the integrated circuit device has a lower metal interconnect layer surrounded by a lower ILD layer and a bottom electrode disposed over the lower metal interconnect layer. The bottom electrode has a lower portion surrounded by a bottom dielectric layer and an upper portion wider than the lower portion. The bottom dielectric layer is disposed over the lower metal interconnect layer and the lower ILD layer. The integrated circuit device also has a RRAM dielectric with a variable resistance located on the bottom electrode, and a top electrode located over the RRAM dielectric. The integrated circuit device also has a top dielectric layer located over the bottom dielectric layer abutting sidewalls of the upper portion of the bottom electrode, the RRAM dielectric, and the top electrode.
US09543506B2	Magnetic random access memory with tri-layer reference layer The present invention is directed to an MTJ memory element including a magnetic free layer structure which comprises one or more magnetic free layers that have a same variable magnetization direction substantially perpendicular to layer planes thereof; an insulating tunnel junction layer formed adjacent to the magnetic free layer structure; a magnetic reference layer structure comprising a first magnetic reference layer formed adjacent to the insulating tunnel junction layer and a second magnetic reference layer separated therefrom by a perpendicular enhancement layer with the first and second magnetic reference layers having a first fixed magnetization direction substantially perpendicular to layer planes thereof; an anti-ferromagnetic coupling layer formed adjacent to the second magnetic reference layer opposite the perpendicular enhancement layer; and a magnetic fixed layer comprising first and second magnetic fixed sublayers with the second magnetic fixed sublayer formed adjacent to the anti-ferromagnetic coupling layer opposite the second magnetic reference layer.
US09543504B2	Vertical hall sensors with reduced offset error A semiconductor chip for measuring a magnetic field based on the Hall effect. The semiconductor chip comprises an electrically conductive well having a first conductivity type, in a substrate having a second conductivity type. The semiconductor chip comprises at least four well contacts arranged at the surface of the well, and having the first conductivity type. The semiconductor chip comprises a plurality of buffer regions interleaved with the well contacts and having the first conductivity type. The buffer regions are highly conductive and the buffer region dimensions are such that at least part of the current from a well contact transits through one of its neighboring buffer regions.
US09543503B2	Magnetic memory cells and methods of fabrication A magnetic cell includes a magnetic tunnel junction that comprises magnetic and nonmagnetic materials exhibiting hexagonal crystal structures. The hexagonal crystal structure is enabled by a seed material, proximate to the magnetic tunnel junction, that exhibits a hexagonal crystal structure matching the hexagonal crystal structure of the adjoining magnetic material of the magnetic tunnel junction. In some embodiments, the seed material is formed adjacent to an amorphous foundation material that enables the seed material to be formed at the hexagonal crystal structure. In some embodiments, the magnetic cell includes hexagonal cobalt (h-Co) free and fixed regions and a hexagonal boron nitride (h-BN) tunnel barrier region with a hexagonal zinc (h-Zn) seed region adjacent the h-Co. The structure of the magnetic cell enables high tunnel magnetoresistance, high magnetic anisotropy strength, and low damping. Methods of fabrication and semiconductor devices are also disclosed.
US09543502B2	Small pitch and high density contact array A method of forming high density contact array is disclosed. The method includes providing a first dielectric layer and forming a hard mask stack over the first dielectric layer. The hard mask stack includes first, second and third hard mask layers. The first and second hard mask layers are processed to form high density array of hard mask stack structures using a double patterning process. The hard mask stack structures include patterned first and second hard mask layers having a first width F1. The width of the patterned second hard mask layers is reduced to a second width F2 to form high density array of hard mask posts. A fourth hard mask layer is formed over the third hard mask layer and surrounding the hard mask posts. The hard mask posts and portions of the third hard mask layer and first dielectric layer underlying the hard mask posts are removed to form high density contact hole array.
US09543499B2	Power generation device A power generation device includes: first and second beams which are arranged to face each other and are bent by vibration; and a coil wound around the first and second beams. Each of the first and second beams includes: a beam body; and a stress relaxation layer made of a material different from a material of the beam body and partially covering the surface of the beam body.
US09543492B2	Thermoelectric elements A thermoelectric element includes a body formed of a single thermoelectric material and extending in a first direction along which a thermal gradient is established in thermoelectric operation, wherein the body has at least first and second adjacent sections in the first direction; at least one of the sections is subject to stress which is applied to that section substantially all around a central axis of the body in the first direction; and the arrangement is such that the stress results in different strain in the first and second sections producing an energy barrier in the body to enhance thermoelectric operation.
US09543491B2	Thermal power generation portable device and power generation control method for thermal power generation portable device A portable thermal power generation device generates power using heat produced by a living body. A thermal power generation member generates power on the basis of a temperature difference between a temperature at a heat source-side position and a temperature at a heat release destination-side position between the living body that is a heat source and a heat release destination of heat released from the portable thermal power generation device. A movable member is configured to change a thermal resistance of at least part of a heat transfer path between the living body and the heat release destination.
US09543486B1	LED package with reflecting cup The present disclosure provides a light emitting diode package which includes a plurality of electrodes, an LED die, a reflecting cup, a reflecting layer, and a phosphor layer. The LED die are electrically connected with the electrodes. The reflecting cup is formed on the electrodes and surrounds the LED die. The reflecting cup includes an inner surface. The reflecting layer is formed between the inner surface and LED die, and the reflecting layer has a higher pyrogenation temperature than the reflecting cup. The phosphor layer covers the LED die.
US09543485B2	Light emitting device A light emitting device includes a semiconductor structure layer including a first conductive semiconductor layer, an active layer on the first conductive semiconductor layer, and a second conductive semiconductor layer on the active layer. A plurality of lower refractive layers is provided on an outer surface of the semiconductor structure layer. The lower refractive layers includes a first lower refractive layer having a first refractive index lower than a refractive index of the semiconductor structure layer on a surface of the semiconductor structure layer, and a second lower refractive layer having a second refractive index lower than the first refractive index on an outer surface of the first lower refractive layer. The second refractive index of the second lower refractive layer is 1.5 or less, and the second lower refractive layer is provided on an outer surface thereof with a plurality of protrusions. The second lower refractive layer includes a plurality of metallic oxide powders.
US09543479B2	Method for producing an optoelectronic component and optoelectronic component produced in such a way A semiconductor chip without a substrate is provided on an electrically insulating carrier. The carrier has electrically conductive contact metallizations. Furthermore, an electrically conductive carrier substrate and a covering substrate are provided. The covering substrate has electrically conductive contact structures. The carrier is attached to the carrier substrate. Subsequently, the covering substrate is attached to the semiconductor chip and/or to the carrier. The electrically conductive contact structures are connected in an electrically conductive manner to the electrically conductive contact metallizations and the electrically conductive carrier substrate.
US09543473B2	Polycrystalline gallium-nitride self-supporting substrate and light-emitting element using same Provided is a self-supporting polycrystalline GaN substrate composed of GaN-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate. The crystal orientations of individual GaN-based single crystal grains as determined from inverse pole figure mapping by EBSD analysis on the substrate surface are distributed with tilt angles from the specific crystal orientation, the average tilt angle being 1 to 10°. There is also provided a light emitting device including the self-supporting substrate and a light emitting functional layer, which has at least one layer composed of semiconductor single crystal grains, the at least one layer having a single crystal structure in the direction approximately normal to the substrate. The present invention makes it possible to provide a self-supporting polycrystalline GaN substrate having a reduced defect density at the substrate surface, and to provide a light emitting device having a high luminous efficiency.
US09543471B2	Optoelectronic component and method for the production thereof An optoelectronic device (10, 1010) having a semiconductor layer structure (100, 1100) comprising a first light-active layer (140) and a second light-active layer (240). A first tunnel junction (200) is formed between the first light-active layer (140) and the second light-active layer (240). A first Bragg reflector (160) is formed between the first light-active layer (140) and the first tunnel junction (200). A second Bragg reflector (260) is formed between the second light-active layer (240) and the first tunnel junction (200).
US09543469B2	III nitride semiconductor epitaxial substrate and III nitride semiconductor light emitting device, and methods of producing the same A III nitride semiconductor epitaxial substrate having more excellent surface flatness is provided, in which the problems of crack formation and the double peaks in the shape of the EL spectrum are mitigated by employing appropriate conditions for Si doping on an AlN layer on a substrate; a III nitride semiconductor light emitting device; and methods of producing the same. A III nitride semiconductor epitaxial substrate has a substrate of which at least a surface portion is made of AlN, an undoped AlN layer formed on the substrate, an Si-doped AlN buffer layer formed on the undoped AlN layer, and a superlattice laminate formed on the Si-doped AlN buffer layer. The Si-doped AlN buffer layer has an Si concentration of 2.0×1019/cm3 or more and a thickness of 4 nm to 10 nm.
US09543468B2	High bandgap III-V alloys for high efficiency optoelectronics High bandgap alloys for high efficiency optoelectronics are disclosed. An exemplary optoelectronic device may include a substrate, at least one Al1-xInxP layer, and a step-grade buffer between the substrate and at least one Al1-xInxP layer. The buffer may begin with a layer that is substantially lattice matched to GaAs, and may then incrementally increase the lattice constant in each sequential layer until a predetermined lattice constant of Al1-xInxP is reached.
US09543462B2	Insulated-gate photoconductive semiconductor switch This present invention provides a novel photoconductive semiconductor switch (PCSS) comprising: a semi-insulating substrate, an anode formed on the upper surface of said semi-insulating substrate, a first n-type doped layer formed on the lower surface of said semi-insulating substrate, a p-type doped layer formed on said first n-type doped layer, a second n-type doped layer formed on said p-type doped layer, a cathode formed on said second n-type doped layer, several recesses facing towards said first n-type doped layer and vertically extending into a part of said first n-type doped layer, an insulating layer formed on said second n-type doped layer and on the walls and the bottoms of said recesses, a gate electrode consisting of two parts, one part of the which formed on said insulating layer on the walls and the bottoms of recesses, and the other part of the which formed on a part of the insulating layer on the second n-type doped layer for electrically connecting the part of the gate electrode on the recesses, wherein the cathode and the gate electrode are electrically isolated.
US09543453B2	Semiconductor device including junction field effect transistor and method of manufacturing the same An on-resistance of a junction FET is reduced. In a semiconductor device in an embodiment, a gate region of the junction field effect transistor includes a low concentration gate region and a high concentration gate region whose impurity concentration is higher than an impurity concentration of the low concentration gate region, and the high concentration gate region is included in the low concentration gate region.
US09543452B1	High voltage junction field effect transistor Provided is a semiconductor device, including: a substrate, a well region of a first conductivity type, a field region of a second conductivity type, a first doped region of the first conductivity type, and a second doped region of the second conductivity type. The well region is located in the substrate. The field region is located in the well region. The first doped region is located in the well region of a first side of the field region. The second doped region is located in the field region, wherein the first doped region is at least partially surrounded by the second doped region.
US09543448B1	Semiconductor structure and method of forming the same The present invention provides a semiconductor structure, including a base, a patterned oxide semiconductor (OS) layer, two source/drain regions, a protective layer, a gate layer and a gate dielectric layer. The patterned OS layer is disposed on the base. Two source/drain regions are disposed on the patterned OS layer and are separated by a recess. Each source/drain region includes an inner sidewall facing the recess and an outer sidewall opposite to the inner sidewall. The protective layer is disposed on a sidewall of the patterned OS layer but is not on the inner sidewall of the source/drain region. The gate layer is disposed on the patterned OS layer, and the gate dielectric layer is disposed between the gate layer and the patterned OS layer. The present invention further provides a method of forming the same.
US09543447B2	Oxynitride semiconductor thin film The purpose of the present invention is to provide an oxide semiconductor thin film, which has relatively high carrier mobility and is suitable as a channel layer material for a TFT, from an oxynitride crystalline thin film. According to the present invention, a crystalline oxynitride semiconductor thin film is obtained by annealing an amorphous oxynitride semiconductor thin film containing In, O, and N or an amorphous oxynitride semiconductor thin film containing In, O, N, and an additional element M, where M is one or more elements selected from among Zn, Ga, Ti, Si, Ge, Sn, W, Mg, Al, Y and rare earth elements, at a heating temperature of 200° C. or more for a heating time of 1 minute to 120 minutes.
US09543445B2	Semiconductor device with oxide semiconductor layer A semiconductor device which includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer is provided. The thickness of the oxide semiconductor layer is greater than or equal to 1 nm and less than or equal to 10 nm. The gate insulating layer satisfies a relation where ∈r/d is greater than or equal to 0.08 (nm−1) and less than or equal to 7.9 (nm−1) when the relative permittivity of a material used for the gate insulating layer is ∈r and the thickness of the gate insulating layer is d. The distance between the source electrode and the drain electrode is greater than or equal to 10 nm and less than or equal to 1 μm.
US09543444B2	Oxide sputtering target, and thin film transistor using the same An oxide sputtering target includes at least one of indium (In), zinc (Zn), tin (Sn), and gallium (Ga), and tungsten (W) in an amount from 0.005 mol % to 1 mol %.
US09543443B2	Thin film transistor assembly, array substrate method of manufacturing the same, and display device The present disclosure discloses a thin film transistor assembly, an array substrate and a method of manufacturing the same, and a display device including the array substrate. The array substrate includes a substrate; a plurality of thin film transistors formed on the substrate; and a plurality of light shielding layers, each of the light shielding layers being arranged between a source electrode and a drain electrode of the thin film transistor and configured to block light from the exterior from illuminating an active layer of the thin film transistor. The light shielding layer and the source electrode and the drain electrode of the thin film transistor are formed in the same layer on the substrate. As the light shielding layer, the source electrode and the drain electrode of the thin film transistor and a data line may be formed on the substrate by using the same material layer through a single patterning process, times of performing patterning processes and the number of masks used may be reduced and thus manufacturing process and cost of the array substrate may be decreased.
US09543440B2	High density vertical nanowire stack for field effect transistor An alternating stack of layers of a first epitaxial semiconductor material and a second epitaxial semiconductor material is formed on a substrate. A fin stack is formed by patterning the alternating stack into a shape of a fin having a parallel pair of vertical sidewalls. After formation of a disposable gate structure and an optional gate spacer, raised active regions can be formed on end portions of the fin stack. A planarization dielectric layer is formed, and the disposable gate structure is subsequently removed to form a gate cavity. A crystallographic etch is performed on the first epitaxial semiconductor material to form vertically separated pairs of an upright triangular semiconductor nanowire and an inverted triangular semiconductor nanowire. Portions of the epitaxial disposable material are subsequently removed. After an optional anneal, the gate cavity is filled with a gate dielectric and a gate electrode to form a field effect transistor.
US09543438B2	Contact resistance reduction technique An embodiment is a method of manufacturing a semiconductor device, the method including forming a first gate over a substrate, forming a recess in the substrate adjacent the first gate, epitaxially forming a strained material stack in the recess, the strained material stack comprising at least three layers, each of the at least three layers comprising a dopant. The method further includes co-implanting the strained material stack with dopants comprising boron, germanium, indium, tin, or a combination thereof, forming a metal layer on the strained material stack, and annealing the metal layer and the strained material stack forming a metal-silicide layer.
US09543434B2	Device active channel length/width greater than channel length/width A device including a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is situated over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.
US09543433B2	Dual work function recessed access device and methods of forming A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.
US09543432B2	High voltage LDMOS device with an increased voltage at source (high side) and a fabricating method thereof A high voltage LDMOS device having high side source voltage, an n type buried layer and a p type buried layer situated on the interface between a p type substrate and an n type epitaxial layer; a lateral surface of the n type buried layer and a lateral surface of the p type buried layer not in contact, and are distant from one another with a distance, thereby increasing the withstand voltage between the n type buried layer and the p type buried layer; the p type buried layer and the drain overlap at least partially in a vertical direction, enabling the p type buried layer to exert a reduced surface field action on the drain, to increase the withstand voltage of the drain against the source; the source and the body terminal centrally on top of the n type buried layer.
US09543428B2	Silicon carbide semiconductor device and method for producing the same An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.
US09543427B2	Semiconductor device and method for fabricating the same A semiconductor device includes: semiconductor layer having an impurity region of a first conductivity type; a gate insulating layer, at least a part of the gate insulating layer positioned on the semiconductor layer; a gate electrode positioned on the gate insulating layer and having a first surface in contact with the part of the gate insulating film and a second surface opposite to the first surface; an interlayer insulating layer covering the gate electrode; and an electrode in contact with the impurity region. The gate electrode has a recess at a corner in contact with the second surface, in a cross section of the gate electrode perpendicular to a surface of the semiconductor layer. A cavity surrounded by the gate electrode and the interlayer insulating layer is positioned in a region including at least a part of the recess.
US09543421B2	Trench-type insulated gate semiconductor device including an emitter trench and an overlapped floating region A semiconductor device includes a semiconductor layer, a plurality of gate trenches, a gate electrode in the plurality of gate trenches, an n+-type emitter region, a p-type base region, and an n−-type drift region disposed, lateral to each gate trench, a p+-type collector region, a plurality of emitter trenches formed between the plurality of gate trenches, a buried electrode in the plurality of emitter trenches, and electrically connected with the n+-type emitter region, and a p-type floating region formed between the plurality of emitter trenches.
US09543417B2	High mobility devices and methods of forming same An embodiment method includes forming a first fin and a second fin over a semiconductor substrate. The first fin includes a first semiconductor strip of a first type, and the second fin includes a second semiconductor strip of the first type. The method further includes replacing the second semiconductor strip with a third semiconductor strip of a second type different than the first type. Replacing the second semiconductor strip includes masking the first fin using a barrier layer while replacing the second semiconductor strip and performing a chemical mechanical polish (CMP) on the third semiconductor strip using a slurry that planarizes the third semiconductor strip at a faster rate than the barrier layer. In some embodiments, the method may further include depositing a sacrificial layer over a wafer containing the first and second fins and performing a non-selective CMP to substantially level a top surface of the wafer.
US09543416B2	Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the product One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.
US09543413B2	Corner layout for high voltage semiconductor devices A corner layout for a semiconductor device that maximizes the breakdown voltage is disclosed. The device includes first and second subsets of the striped cell arrays. The ends of each striped cell in the first array is spaced a uniform distance from the nearest termination device structure. In the second subset, the ends of striped cells proximate a corner of the active cell region are configured to maximize breakdown voltage by spacing the ends of each striped cell a non-uniform distance from the nearest termination device structure. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
US09543406B2	Structure and method for overlay marks The overlay mark and method for making the same are described. In one embodiment, a semiconductor overlay structure includes gate stack structures formed on the semiconductor substrate and configured as an overlay mark, and a doped semiconductor substrate disposed on both sides of the gate stack structure that includes at least as much dopant as the semiconductor substrate adjacent to the gate stack structure in a device region. The doped semiconductor substrate is formed by at least three ion implantation steps.
US09543404B2	Vertical BJT for high density memory Some aspects of this disclosure relate to a memory device. The memory device includes a collector region having a first conductivity type and which is coupled to a source line of the memory device. A base region is formed over the collector region and has a second conductivity type. A gate structure is coupled to the base region and acts as a shared word line for first and second neighboring memory cells of the memory device. First and second emitter regions are formed over the base region and have the first conductivity type. The first and second emitter regions are arranged on opposite sides of the gate structure. First and second contacts extend upwardly from the first and second emitter regions, respectively, and couple the first and second emitter regions to first and second data storage elements, respectively, of the first and second neighboring memory cells, respectively.
US09543399B2	Device having sloped gate profile and method of manufacture A semiconductor device having an open profile gate electrode, and a method of manufacture, are provided. A funnel-shaped opening is formed in a dielectric layer and a gate electrode is formed in the funnel-shaped opening, thereby providing a gate electrode having an open profile. In some embodiments, first and second gate spacers are formed alongside a dummy gate electrode. The dummy gate electrode is removed and upper portions of the first and second gate spacers are removed. The first and second gate spacers may be formed of different materials having different etch rates.
US09543396B2	Vertical transistor device structure with cylindrically-shaped regions A vertical power transistor device includes a semiconductor layer of a first conductivity type, with a plurality of cylindrically-shaped dielectric regions disposed in the semiconductor layer. The cylindrically-shaped dielectric regions extend in a vertical direction from a top surface of the semiconductor layer downward. Adjacent ones of the cylindrically-shaped dielectric regions being laterally separated along a common diametrical axis by a narrow region of the semiconductor layer having a first width. Each dielectric region has a cylindrically-shaped, conductive field plate member centrally disposed therein. The cylindrically-shaped, conductive field plate member extends in the vertical direction from the top surface downward to near a bottom of the dielectric region. The dielectric region laterally separates the cylindrically-shaped, conductive field plate member from the narrow region. A source region is disposed at the top surface, and a drain region is disposed at the bottom, of the semiconductor layer.
US09543391B2	High electron mobility transistor having reduced threshold voltage variation and method of manufacturing the same According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second channel supply layer, source and drain electrodes on the first channel supply layer, and a gate electrode on the depletion layer. The channel includes a 2DEG channel configured to generate a two-dimensional electron gas and a depletion area. The first channel supply layer corresponds to the 2DEG channel and defines an opening that exposes the depletion area. The depletion layer is on the depletion area of the channel layer. The second channel supply layer is between the depletion layer and the depletion area.
US09543389B2	Semiconductor device with recombination region A semiconductor device includes a drift zone in a semiconductor body. A charge-carrier transfer region forms a pn junction with the drift zone in the semiconductor body. A control structure electrically connects a recombination region to the drift zone during a desaturation cycle and disconnects the recombination region from the drift zone outside the desaturation cycle. During the desaturation cycle the recombination region reduces a charge carrier plasma in the drift zone and reduces reverse recovery losses without adversely affecting blocking characteristics.
US09543385B2	Heavily doped semiconductor nanoparticles Herein, provided are heavily doped colloidal semiconductor nanocrystals and a process for introducing an impurity to semiconductor nanoparticles, providing control of band gap, Fermi energy and presence of charge carriers. The method is demonstrated using InAs colloidal nanocrystals, which are initially undoped, and are metal-doped (Cu, Ag, Au) by adding a metal salt solution.
US09543379B2	Semiconductor device with peripheral breakdown protection A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.
US09543376B2	Semiconductor device and method for manufacturing the same According to one embodiment, a semiconductor device includes a semiconductor layer including Ge; and a metal Ge compound region provided in a surface portion of the semiconductor layer. Sn is included in an interface portion between the semiconductor layer and the metal Ge compound region. A lattice plane of the semiconductor layer matches with a lattice plane of the metal Ge compound region.
US09543373B2	Semiconductor structure and manufacturing method thereof A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.
US09543371B2	Transparent display device having a minimized bezel A transparent organic light-emitting display device is described herein. The transparent substrate includes a display area and non-display area adjacent to the display area. An organic light-emitting element is disposed on the display area of the transparent substrate. A first power line is disposed on the display area of the transparent substrate. The first power line supplies power to the organic light-emitting element. A first circuit board comprises a first power supply provided on a first side of the transparent substrate and a second circuit board comprises a second power supply provided on a second side of the transparent substrate. The first power supply is configured to receive power from the second power supply via the first power line. An additional interconnection film to supply power to the first power supply is not required, and thus the width of the bezel can be reduced.
US09543369B2	Display device A display device includes a plurality of pixels each including a light emitting region; and a light blocking layer provided on a side of the plurality of pixels on which light is output. In each of the plurality pixels, the light blocking layer has a plurality of openings allowing light from the light emitting region to be output. In one embodiment, in the light blocking layer, the openings adjacent to each other may be located line-symmetrically. In one embodiment, in the light blocking layer, the openings adjacent to each other may be located point-symmetrically.
US09543367B2	Organic light emitting display devices An organic light emitting display device may have a pixel region and a transparent region, and may include a substrate, at least one semiconductor device disposed on the substrate in the pixel region, an organic light emitting structure disposed on the at least one semiconductor device, and a capacitor disposed on the substrate in the transparent region. The capacitor may have a sufficient capacitance without substantially reducing a transmittance of the organic light emitting display device. Additionally, the transparent region of the organic light emitting display device may serve as a mirror in accordance with the material included in a lower electrode of the capacitor and/or an upper electrode of the capacitor.
US09543365B2	Touch panel The present invention provides a touch panel, including a lower substrate, an organic light-emitting component, disposed on the lower substrate, a nano silver sensing layer, disposed on the organic light emitting component, and an upper substrate, disposed on the nano silver sensing layer.
US09543363B2	Organic light emitting diode display device A display device includes a first pixel and a second pixel. The second pixel is controlled to emit light in a predetermined range in a first time period and to not emit light in the predetermined range in a second time period during which the first pixel emits light. The first pixel includes a first organic emission layer having a first thickness and the second pixel includes a second organic emission layer having a second thickness different from the first thickness. A resonance pattern is formed in the second pixel to emit light in a melatonin production inhibition wavelength range that corresponds to the predetermined range. The first pixel may emit blue light, green light, red light, or another color of light including white light.
US09543362B2	Protective layer(s) in organic image sensors The present disclosure relates to an organic image sensor and an associated method. By inserting an inorganic protective layer between an electrode and an organic photo active region of the image sensor, the organic photo active region is protected from moisture, oxygen or following process damage. The inorganic protective layers also help to suppress the leakage in the dark. In some embodiments, the organic image sensor comprises a first electrode, an organic photoelectrical conversion structure disposed over the first electrode and a second electrode disposed over the organic photoelectrical conversion structure. The organic image sensor further comprises a first protective structure covering a top surface and a sidewall of the organic photoelectrical conversion structure.
US09543359B2	Switching device having a non-linear element A switching device includes a substrate; a first electrode formed over the substrate; a second electrode formed over the first electrode; a switching medium disposed between the first and second electrode; and a nonlinear element disposed between the first and second electrodes and electrically coupled in series to the first electrode and the switching medium. The nonlinear element is configured to change from a first resistance state to a second resistance state on application of a voltage greater than a threshold.
US09543356B2	Pixel sensor cell including light shield CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.
US09543345B2	Method for manufacturing solid-state imaging element, solid-state imaging element, method for manufacturing electronic apparatus, and electronic apparatus Disclosed herein is a method for manufacturing a solid-state imaging element, the method including forming lenses that are each provided corresponding to a light receiving part of a respective one of a plurality of pixels arranged in an imaging area over a semiconductor substrate and collect light onto the light receiving parts; forming a light blocking layer by performing film deposition on the lenses by using a material having light blocking capability; and forming a light blocker composed of the material having light blocking capability at a boundary part between the lenses adjacent to each other by etching the light blocking layer in such a manner that the material having light blocking capability is left at the boundary part between the lenses.
US09543342B2	Solid-state imaging device A plurality of first pixels P1 corresponding to color filters of two or more colors constitute a pixel group. A plurality of the pixel groups are arranged so that each of the pixel groups corresponds to one of second pixels P2. The light which is transmitted through the color filters enters first photoelectric conversion units of the first pixels P1 corresponding to the color filters. The light which is transmitted through the pixel group enters a second photoelectric conversion unit of the second pixel P2 corresponding to the pixel group. The number of colors of the color filters corresponding to the plurality of first pixels P1 that constitute the pixel group, and the number of the first pixels P1 corresponding to each color are equal to each other among the plurality of pixel groups.
US09543340B2	Photoelectric conversion device and method of manufacturing photoelectric conversion device A photoelectric conversion device includes a pixel including a transfer transistor transferring signal charges generated in a photoelectric conversion portion from a charge accumulation region to a floating diffusion region, and a peripheral transistor forming a peripheral circuit for controlling a read-out operation of a pixel signal based on the signal charges from the pixel. A gate electrode of the transfer transistor and the floating diffusion region are separated from each other by a first distance in a plan view. A gate electrode and a drain region of the peripheral transistor are separated from each other by a second distance smaller than the first distance in a plan view.
US09543337B2	Semiconductor device and manufacturing method thereof, delamination method, and transferring method A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed.
US09543335B2	Liquid-crystal display and element substrate thereof An element substrate is provided, including a substrate, a metal layer and a planarization layer. The metal layer is located on the substrate. The metal layer has a first edge in a first direction. The planarization layer is located on the metal layer. The planarization layer includes a contact hole. The contact hole has a contiguous wall and a bottom side. The metal layer is exposed in the bottom side. A contour line of the contiguous wall on a vertical plane is a curved line. The first edge corresponds vertically with a critical point on the contour line. The slope of a tangent line on the critical point of the contour line is between 0.087 to 0.364.
US09543332B2	Array substrate, display panel and display device An array substrate comprises: a plurality of flexible cushions; and a plurality of signal lines, wherein the signal lines have ends respectively located on the flexible cushions.
US09543330B1	Method of manufacturing a thin film transistor and a pixel structure A method manufacturing a thin film transistor is provided. A gate, a first insulation layer covering the gate, a semiconductor layer over the gate, and a first photoresist pattern are sequentially formed on a substrate. The semiconductor layer is patterned into a channel layer by using the first photoresist pattern as a mask and the first photoresist pattern is subsequently shrunken to remain a portion of the first photoresist pattern on the channel layer. A conductive material layer covering the remained portion of the first photoresist pattern, the channel layer and the first insulation layer is patterned by using a second photoresist pattern as a mask to form a source and a drain separated by a gap region exposing the remained portion. The second photoresist pattern and the remained portion are removed by performing a stripping process to expose the channel layer between the source and the drain.
US09543324B2	Array substrate, display device and manufacturing method of the array substrate An array substrate, a display device and a manufacturing method of the array substrate. The array substrate includes: a base substrate (1) and a plurality of pixel units located on the base substrate (1), each of the pixel units including a thin film transistor unit. The thin film transistor unit includes: a gate electrode located on the base substrate (1), a gate insulating layer (3) located on the gate electrode, an active layer (4) located on the gate insulating layer (3) and opposed to the gate electrode in position, an ohmic layer (5) located on the active layer (4), a source electrode (6a) and a drain electrode (6b) that are located on the ohmic layer (5) and a resin passivation layer (8) that are located on the source electrode (6a) and the drain electrode (6b) and covers the substrate.
US09543322B2	Methods for producing a thin film ferroelectric device using a two-step temperature process on an organic polymeric ferroelectric precursor material stacked between two conductive materials Methods for producing ferroelectric device are described. A method includes positioning an organic polymeric ferroelectric layer between two conductive materials to form a stack. The stack can be subjected to a 2-step heat treating process. The first heat treating step transforms the organic polymeric ferroelectric precursor to a ferroelectric material having ferroelectric hysteresis properties, and the second heat treating step densities the ferroelectric material to obtain the ferroelectric device. The thin film ferroelectric device can include a thin film ferroelectric capacitor, a thin film ferroelectric transistor, or a thin film ferroelectric diode.
US09543314B2	Manufacturing method of semiconductor device and semiconductor device A semiconductor device including a memory cell having a control gate electrode and a memory gate electrode formed via a charge accumulation layer with respect to the control gate electrode is provided which improves its performance. A control gate electrode which configures a memory cell, and a metallic film which configures part of the memory gate electrode are formed by a so-called gate last process. Thus, the memory gate electrode is configured by a silicon film corresponding to a p-type semiconductor film being in contact with an ONO film, and the metallic film. Further, a contact plug is coupled to both of the silicon film and the metallic film which configure the memory gate electrode.
US09543313B2	Nonvolatile memory device and method for fabricating the same A nonvolatile memory device includes: a channel layer protruding perpendicular to a surface of a substrate; a tunnel insulation layer formed on a surface of the channel layer; a stack structure, in which a plurality of floating gate electrodes and a plurality of control gate electrodes are alternately formed along the channel layer; and a charge blocking layer interposed between each floating gate electrode, of the plurality of floating gate electrodes, and each control gate electrode of the plurality of control gate electrodes, wherein the floating gate electrode includes a first floating gate electrode between two control gate electrodes and a second floating gate electrode positioned in the lowermost and uppermost parts of the stack structure and having a smaller width in a direction parallel to the substrate than the first floating gate electrode.
US09543311B2	Vertical memory cell with non-self-aligned floating drain-source implant Various embodiments provide a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
US09543305B2	Reverse conducting power semiconductor device A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w′), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w′) of each one of the two outer cathode layer regions next to a diode cell neighboring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.
US09543304B2	Vertical junction FinFET device and method for manufacture A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.
US09543301B2	Fin-last FinFET and methods of forming same Embodiments of the present disclosure are a FinFET device, and methods of forming a FinFET device. An embodiment is a method for forming a FinFET device, the method comprising forming a semiconductor strip over a semiconductor substrate, wherein the semiconductor strip is disposed in a dielectric layer, forming a gate over the semiconductor strip and the dielectric layer, and forming a first recess and a second recess in the semiconductor strip, wherein the first recess is on an opposite side of the gate from the second recess. The method further comprises forming a source region in the first recess and a drain region in the second recess, and recessing the dielectric layer, wherein a first portion of the semiconductor strip extends above a top surface of the dielectric layer forming a semiconductor fin.
US09543300B2	CMOS transistor, semiconductor device including the transistor, and semiconductor module including the device Provided are a CMOS transistor, a semiconductor device having the transistor, and a semiconductor module having the device. The CMOS transistor may include first and second interconnection structures respectively disposed in first and second regions of a semiconductor substrate. The first and second regions of the semiconductor substrate may have different conductivity types. The first and second interconnection structures may be disposed on the semiconductor substrate. The first interconnection structure may have a different stacked structure from the second interconnection structure. The CMOS transistor may be disposed in the semiconductor device. The semiconductor device may be disposed in the semiconductor module.
US09543297B1	Fin-FET replacement metal gate structure and method of manufacturing the same A method of forming fins and the resulting fin-shaped field effect transistors (finFET) are provided. Embodiments include forming silicon (Si) fins over a substrate; forming a first metal over each of the Si fins; forming an isolation material over the first metal; removing an upper portion of the isolation material to expose and upper portion of the first metal; removing the upper portion of the first metal to expose an upper portion of each Si fin; removing the isolation material after removing the upper portion of the first metal; and forming a second metal over the first metal and the upper portion of the Si fins.
US09543291B2	Method of forming a high electron mobility semiconductor device and structure therefor In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device.
US09543283B2	Light emitting diode package and method for manufacturing same An LED packaging includes a substrate having a top surface and a bottom surface opposite to the top surface, a recess defined in the top surface, an LED mounted on the top surface of the substrate, a zener diode received in the recess, and a reflecting layer formed in the recess and enclosing the zener diode therein.
US09543280B2	Light emitting module and lighting device Disclosed herein are a light emitting module and a lighting device that may be used for a display application or a lighting application. The light emitting module includes an electrode layer including a plurality of blocks that are insulated from each other by an electrode separating line; and one or more light emitting elements mounted on the electrode layer so as to be electrically connected to any one block of the blocks of the electrode layer and a neighboring block, respectively, wherein the blocks have another neighboring block disposed in a first direction and still another neighboring block disposed in a second direction, based on any one block of the blocks while having the electrode separating line formed to be bent more than once at a predetermined interval therebetween so that heat generated from the light emitting elements is emitted through the blocks.
US09543272B2	Method for interconnecting stacked semiconductor devices A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.
US09543271B2	Semiconductor device having a sealing layer covering a semiconductor memory unit and a memory controller A semiconductor device includes a substrate, a semiconductor memory unit mounted on a surface of the substrate, a memory controller configured to control the semiconductor memory unit and mounted on the surface of the substrate adjacent to the semiconductor memory unit, and a sealing layer disposed on the surface of the substrate and covering the semiconductor memory unit and the memory controller.
US09543270B1	Multi-device package and manufacturing method thereof A multi-device package includes a substrate, at least two device regions, a first redistribution layer, an external chip, a plurality of first connectors and a conductive contact. The two device regions are formed from the substrate, and the substrate has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface and electrically connected to the two device regions, and the external chip is disposed on the first redistribution layer. The first connectors are interposed between the first redistribution layer and the external chip to interconnect the first redistribution layer and the external chip, and the conductive contact is extended from the second surface to the first surface of the substrate to electrically connect the device region.
US09543265B2	Joint material, and jointed body Disclosed is a jointed body wherein multiple base members are jointed to each other through a jointing layer, and at least one of the base members is a base member of a ceramic material, semiconductor or glass. The joint material layer contains a metal and an oxide. The oxide contains V and Te, and is present between the metal and the base members. Disclosed is also a joint material in the form of a paste containing an oxide glass containing V and Te, metal particles, and a solvent; in the form of a foil piece or plate in which particles of an oxide glass containing V and Te are embedded; or in the form of a foil piece or plate containing a layer of an oxide glass containing V and Te, and a layer of a metal.
US09543263B2	Semiconductor packaging and manufacturing method thereof The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top surface; and a conductive structure. The top surface of the PPI includes a first region receiving the conductive structure, and a second region surrounding the first region. The second region includes metal derivative transformed from materials made of the first region. The present disclosure provide a method of manufacturing a semiconductor package, including forming a first flux layer covering a portion of a top surface of a PPI; transforming a portion of the top surface of the PPI uncovered by the first flux layer into a metal derivative layer; removing the first flux layer; forming a second flux layer on the first region of the PPI; dropping a solder ball on the flux layer; and forming electrical connection between the solder ball and the PPI.
US09543262B1	Self aligned bump passivation A method of fabricating multiple conductor layers utilizing the same seed layer is described. In an embodiment a stud bump structure is described in which the seed layer is encapsulated by the passivation layer. By forming the stud bump prior to the passivation layer, the height of the stud bump extending from the top surface of the passivation layer can be controlled.
US09543251B2	Semiconductor chip and semiconductor package having the same A semiconductor chip includes a semiconductor substrate having a front surface, a circuit unit formed within the semiconductor substrate and extending from the front surface into the semiconductor substrate, and a rear surface opposite the front surface, and a girder beam disposed outside of the circuit unit and within the semiconductor substrate.
US09543250B2	Semiconductor devices including through-silicon via Semiconductor devices, and methods of fabricating a semiconductor device, include forming a via hole through a first surface of a substrate, the via hole being spaced apart from a second surface facing the first surface, forming a first conductive pattern in the via hole, forming an insulating pad layer on the first surface of the substrate, the insulating pad having an opening exposing the first conductive pattern, performing a thermal treatment on the first conductive pattern to form a protrusion protruding from a top surface of the first conductive pattern toward the opening, and then, forming a second conductive pattern in the opening.
US09543247B1	Surface-mount electronic component A surface-mount chip is formed by a silicon substrate having a front surface and a side. The chip includes a metallization intended to be soldered to an external device. The metallization has a first portion covering at least a portion of the front surface of the substrate and a second portion covering at least a portion of the side of the substrate. A porous silicon region is included in the substrate to separating the second portion of the metallization from the rest of the substrate.
US09543242B1	Semiconductor package and fabricating method thereof A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
US09543239B2	Semiconductor device and production method therefor A semiconductor device includes a semiconductor chip, a lead arranged on a side portion of the semiconductor chip, and a wire, whose one end and another end are bonded to the semiconductor chip and the lead respectively, having a ball portion and a stitch portion wedged in side elevational view on the semiconductor chip and the lead respectively. An angle of approach of the wire to the lead is not less than 50°, and the length of the stitch portion is not less than 33 μm.
US09543233B2	Chip package having a dual through hole redistribution layer structure A chip package includes a chip, a laser stopper, an isolation layer, a redistribution layer, an insulating layer, and a conductive structure. The chip has a conductive pad, a first surface, and a second surface opposite to the first surface. The conductive pad is located on the first surface. The second surface has a first though hole to expose the conductive pad. The laser stopper is located on the conductive pad. The isolation layer is located on the second surface and in the first though hole. The isolation layer has a third surface opposite to the second surface. The isolation layer and the conductive pad have a second though hole together, such that the laser stopper is exposed through the second though hole. The redistribution layer is located on the third surface, the sidewall of the second though hole, and the laser stopper.
US09543232B2	Semiconductor package structure and method for forming the same A semiconductor package structure and method for forming the same are provided. The semiconductor package structure includes a substrate and the substrate has a front side and a back side. The semiconductor package structure includes a through silicon via (TSV) interconnect structure formed in the substrate; and a first guard ring doped region and a second guard ring doped region formed in the substrate, and the first guard ring doped region and the second guard ring doped region are adjacent to the TSV interconnect structure.
US09543230B2	Semiconductor device and method of manufacturing the same The semiconductor device includes first interlayer insulating layers and first conductive patterns which are alternately stacked; a second interlayer insulating layer formed on the first interlayer insulating layers and the first conductive patterns; and a slit passing through the second interlayer insulating layer, the first interlayer insulating layers and the first conductive patterns to divide the first interlayer insulating layers and the first conductive patterns into stack structures.
US09543225B2	Systems and methods for detecting endpoint for through-silicon via reveal applications Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior region with a wafer receiving mechanism and a viewport disposed on a sidewall of the plasma processing chamber providing visual access from the exterior to the wafer received on the wafer receiving mechanism. A camera is mounted to the viewport of the plasma processing chamber on the exterior and coupled to an image processor. The image processor includes pattern recognition logic to match images of emerging pattern captured and transmitted by the camera, to a reference pattern and to generate signal defining an endpoint when a match is detected. A system process controller coupled to the image processor and the plasma processing chamber receives the signal from the image processor and adjusts controls of one or more resources to stop the etching operation.
US09543224B1	Hybrid exposure for semiconductor devices Semiconductor packages and methods, systems, and apparatuses of forming such packages are described. A method of forming a semiconductor package may include encapsulating a semiconductor die with a molding compound, applying a seed layer on the die and the molding compound, applying a resist layer on the seed layer, exposing a first portion of the resist layer, and exposing a second portion of the resist layer. The first portion can include a first area of the resist layer to be used for forming a redistribution layer (RDL) without including a second area of the resist layer to be used for forming an electrical communications pathway between at least one of the contact pads and the RDL. The second portion can include the second area of the resist layer that includes the electrical communications pathway.
US09543220B2	Substrate processing apparatus, semiconductor device manufacturing method, substrate processing method, and recording medium According to the present disclosure, it is possible to prevent particles from being generated and to improve substrate processing quality. A substrate processing apparatus includes cassette mounting unit on which process substrate cassette and dummy substrate cassette are mounted, the process substrate cassette being configured to accommodate a plurality of process substrates, and the dummy substrate cassette being configured to accommodate a plurality of dummy substrates, process chamber configured to process the process substrates and the dummy substrates, substrate support unit installed within the process chamber and provided with a plurality of substrate mounting portions where the process substrates and the dummy substrates are mounted, transfer unit configured to transfer the process substrates and the dummy substrates between the cassette mounting unit and the process chamber, and control unit configured to control substrate processing and to transfer processing of the process substrates and the dummy substrates.
US09543218B2	Semiconductor component and method for producing a semiconductor component A method can be used to produce a semiconductor component. A semiconductor layer sequence has an active region that is provided for generating radiation and also has an indicator layer. Material of the semiconductor layer sequence that is arranged on that side of the indicator layer that is remote from the active region is removed in regions. The material is removed using a dry-chemical removal of the semiconductor layer sequence. A property of a process gas is monitored during the removal to determine that the indicator layer has been reached based on a change in the property of the process gas.
US09543214B2	Method of forming stressed semiconductor layer The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.
US09543211B1	Semiconductor structure and manufacturing method thereof A manufacturing method of a semiconductor structure includes the following steps. Gate structures are formed on a semiconductor substrate. A source/drain contact is formed between two adjacent gate structures. The source/drain contact is recessed by a recessing process. A top surface of the source/drain contact is lower than a top surface of the gate structure after the recessing process. A stop layer is formed on the gate structures and the source/drain contact after the recessing process. A top surface of the stop layer on the source/drain contact is lower than the top surface of the gate structure. A semiconductor structure includes the semiconductor substrate, the gate structures, a gate contact structure, and the source/drain contact. The source/drain contact is disposed between two adjacent gate structures, and the top surface of the source/drain contact is lower than the top surface of the gate structure.
US09543209B2	Non-planar transistors with replacement fins and methods of forming the same A method includes forming a first semiconductor fin, and oxidizing surface portions of the first semiconductor fin to form a first oxide layer. The first oxide layer includes a top portion overlapping the first semiconductor fin and sidewall portions on sidewalls of the first semiconductor fin. The top portion of the first oxide layer is then removed, wherein the sidewall portions of the first oxide layer remains after the removing. The top portion of the first semiconductor fin is removed to form a recess between the sidewall portions of the first oxide layer. An epitaxy is performed to grow a semiconductor region in the recess.
US09543204B2	Method for manufacturing semiconductor device In order to provide a semiconductor device that includes a conductive layer on one surface of a semiconductor substrate with an insulating layer therebetween, a bump on the other surface of the semiconductor substrate, and a through-electrode through the semiconductor substrate connecting the conductive layer with the bump, a through-hole is formed from the other surface of the semiconductor substrate to be connected to the conductive layer, a seed metal film is formed on the through-hole and the other surface, a photoresist is formed thereon, a mask layer is formed by processing the photoresist with a pattern larger than the through-hole, a plated film is grown by electrolytic plating so as to integrally form the through-electrode and a part of the bump.
US09543200B2	Methods for fabricating semiconductor devices having through electrodes Methods for fabricating semiconductor devices having through electrodes are provided. The method may comprise forming a via hole which opens towards an upper surface of a substrate and disconnects with a lower surface of the substrate; forming a via isolation layer which extends along an inner surface of the via hole and covers the upper surface of the substrate; forming a seed layer on the via isolation layer which extends along the via isolation layer; annealing the seed layer in-situ after forming the seed layer; forming a conductive layer, filling the via hole, by an electroplating using the seed layer; and planarizing the upper surface of the substrate to form a through electrode surrounded by the via isolation layer in the via hole.
US09543197B2	Package with dielectric or anisotropic conductive (ACF) buildup layer Embodiments of the present disclosure are directed to techniques and configurations for an integrated circuit (IC) package having one or more dies connected to an integrated circuit substrate by an interface layer. In one embodiment, the interface layer may include an anisotropic portion configured to conduct electrical signals in the out-of-plane direction between one or more components, such as a die and an integrated circuit substrate. In another embodiment, the interface layer may be a dielectric or electrically insulating layer. In yet another embodiment, the interface layer may include an anisotropic portion that serves as an interconnect between two components, a dielectric or insulating portion, and one or more interconnect structures that are surrounded by the dielectric or insulating portion and serve as interconnects between the same or other components. Other embodiments may be described and/or claimed.
US09543192B2	Stitched devices A stitched device is disclosed. The stitched device includes first and second base devices having first and second stitched interconnects electrically coupled in a stitching level. This enables a single substrate of the stitched device to have electrically coupled first and second base devices.
US09543190B2	Method of fabricating semiconductor device having a trench structure penetrating a buried layer A method of fabricating a semiconductor device is disclosed. The method includes the steps of: providing a semiconductor substrate; forming a buried layer in the semiconductor substrate; forming a deep well having a first conductivity type in the semiconductor substrate, wherein the deep well is disposed on the buried layer; forming a first trench structure in the deep well, wherein the first trench structure extends into the buried layer; and forming a second trench structure in the semiconductor substrate, wherein a depth of the second trench structure is larger than a depth of the buried layer.
US09543184B2	Electrostatic chuck The present invention is an electrostatic chuck including a ceramic base body and an adsorption electrode provided inside of or on the lower surface of the ceramic base body and having a portion where a Mn content is 1×10−4% by mass or less in a region from the upper surface of the ceramic base body to the adsorption electrode.
US09543179B2	Load port module A load port module includes a plate to support at least one substrate, a sensor to detect foreign matter at a predetermined location, and a cleaner to remove the foreign matter at the predetermined location when the foreign matter is detected by the sensor. The cleaner removes the foreign matter at the predetermined location in synchronism with movement of the plate. A mover to move the plate continues to operate after detection of the foreign matter by the sensor and removal of the foreign matter by the cleaner.
US09543177B2	Pod and purge system using the same An object is to prevent the partial pressure of oxidative gas over time in an FOUP mounted on an FIMS system and left open. A surface purge unit is provided on a side opposite to the opening of the FOUP in such a way that wafers supported in the FOUP is located between the opening and the surface purge unit. The surface purge unit ejects inert gas from a plurality of vent holes provided in its surface toward the opening. Uniform purging or replacement of the interior of the FOUP with inert gas can be achieved by creating inert gas flow from an inert gas supply part extending over a surface in the direction from the interior of the FOUP toward the opening along the wafer surface.
US09543176B2	Operating methods of purge devices for containers Operating methods of purge devices for containers are provided. The operating methods comprise a step of aligning an opening of a container to a first purging unit and placing the container in the purge device. After the container is purged, the container will be heated and filled with extreme clean dry air (XCDA) or nitrogen to finalize the purging process.
US09543173B2	Decapsulator with applied voltage and etchant cooling system for etching plastic-encapsulated devices An apparatus and a method for selectively etching an encapsulant forming a package of resinous material around an electronic device includes an electronic device package mountable on the etch head; a conductive electrode in electrical contact with package leads of the electronic device package to apply a first voltage to the package leads of the electronic device; a first pump configured to pump a first quantity of the etchant solution from the source into the etch head where the etchant solution is electrically biased to a second voltage different from the first voltage and is cooled to a temperature below the ambient temperature. An etch cavity is formed on an exterior surface of the electronic device package. When the etchant solution has etched through an exterior surface of the electronic device package, the conductive bond wires of the electronic device is prevented from being etched by the applied first voltage.
US09543158B2	Technique to deposit sidewall passivation for high aspect ratio cylinder etch Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in dielectric material on a substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in substantial preservation of a mask layer on the substrate. The protective coating may be deposited using particular reactants and/or reaction conditions that are unlikely to damage the mask layer. The protective coating may also be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. In some cases the protective coating is deposited using plasma assisted atomic layer deposition, a modified plasma assisted atomic layer deposition, or plasma assisted chemical vapor deposition.
US09543157B2	Method for processing a carrier, a method for operating a plasma processing chamber, and a method for processing a semiconductor wafer According to various embodiments, a method for processing a carrier may include: performing a dry etch process in a processing chamber to remove a first material from the carrier by an etchant, the processing chamber including an exposed inner surface including aluminum and the etchant including a halogen; and, subsequently, performing a hydrogen plasma process in the processing chamber to remove a second material from at least one of the carrier or the inner surface of the processing chamber.
US09543156B1	Method for growing graphene on surface of gate electrode and method for growing graphene on surface of source/drain surface The present invention provides a method for growing graphene on a surface of a gate electrode and a method for growing graphene on a surface of a source/drain electrode, in which a low-temperature plasma enhanced vapor deposition process is adopted to grow a graphene film, of which a film thickness is controllable, on a gate electrode or a source/drain electrode that contains copper, and completely coincides with a pattern of the gate electrode or the source/drain electrode. The manufacturing temperature of graphene is relatively low so that it is possible not to damage the structure of a thin-film transistor to the greatest extents and the supply of carbon sources that is used wide, having low cost and a simple manufacturing process, where existing PECVD facility of a thin-film transistor manufacturing line can be used without additional expense. The gate electrode or the source/drain electrode is covered with graphene and is prevented from contact with moisture and oxygen thereby overcoming the problem of a conventional TFT manufacturing process that a gate electrode or a source/drain electrode that contains copper is readily susceptible to oxidization. Further, the high electrical conductivity of graphene makes it possible not to affect the electrical performance of the entire device.
US09543155B2	Method of forming minute patterns and method of manufacturing a semiconductor device using the same A method includes forming a first etch target layer and a first mask layer on a substrate. Sacrificial patterns extending in a first direction are formed on the first mask layer in a second direction. Spacers are formed on sidewalls of the sacrificial patterns. After removing the sacrificial patterns, the first mask layer is etched using the spacers as an etching mask to form first masks. Second masks are formed on sidewalls of each first mask to define a third masks including each first mask and the second masks on sidewalls of each first mask. The first etch target layer is etched using the first and third masks as an etching mask to form first and second patterns in the first and second regions, respectively. Each first pattern has a first width, and each second pattern has a second width greater than the first width.
US09543153B2	Recess technique to embed flash memory in SOI technology An integrated circuit arranged on a silicon-on-insulator (SOI) substrate region is provided. The SOI substrate region is made up of a handle wafer region, an oxide layer arranged over the handle wafer region, and a silicon layer arranged over the oxide layer. A recess extends downward from an upper surface of the silicon layer and terminates in the handle wafer region, thereby defining a recessed handle wafer surface and sidewalls extending upwardly from the recessed handle wafer surface to meet the upper surface of the silicon layer. A first semiconductor device is disposed on the recessed handle wafer surface. A second semiconductor device is disposed on the upper surface of the silicon layer.
US09543151B2	Ionizer and substrate transfer system having the same, and method of manufacturing a semiconductor device using the same An ionizer includes a body extending in a first direction, a sheath gas nozzle installed in a lower portion of the body and having a spray hole and an electrode needle disposed within the spray hole to generate a corona discharge, a gas supply provided in the body and configured to be in fluid communication with the spray hole to supply a gas to the spray hole such that ions generated by the electrode needle are spayed out to the outside of the ionizer from the spray hole, and a pair of first and second guiding plates disposed at opposite sides of the sheath gas nozzle and extending downward from first and second sides of the body opposite to each other to guide the ions sprayed from the spray hole to be directed to a target. A semiconductor device may be manufactured using the ionizer.
US09543147B2	Photoresist and method of manufacture A system and method for anti-reflective layers is provided. In an embodiment the anti-reflective layer comprises a floating additive in order to form a floating additive region along a top surface of the anti-reflective layer after the anti-reflective layer has dispersed. The floating additive may comprise an additive group which will decompose along with a fluorine unit bonded to the additive group which will decompose. Additionally, adhesion between the middle layer and the photoresist may be increased by applying an adhesion promotion layer using either a deposition process or phase separation, or a cross-linking may be performed between the middle layer and the photoresist.
US09543139B2	In-situ support structure for line collapse robustness in memory arrays Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.
US09543138B2	Ion optical system for MALDI-TOF mass spectrometer An ion accelerator for a time-of-flight mass spectrometer includes a pulsed ion accelerator positioned proximate to a sample plate and having an electrode that is electrically connected to the sample plate. An accelerator power supply generates an accelerating potential on the ion accelerator electrode that accelerates a pulse of ions generated from the sample positioned on the sample plate. An ion focusing electrode is positioned after the pulsed ion accelerator. A potential applied to the ion focusing electrode focuses the pulse of ions into a substantially parallel beam propagating in an ion flight path. A static ion accelerator is positioned proximate to the ion focusing electrode with an input that receives the pulse of ions focused by the ion focusing electrode. The static ion accelerator accelerating the focused pulse of ions.
US09543136B2	Ion optics components and method of making the same A method of making an ion optics component includes providing an electrically isolating substrate and machining away material of the substrate from at least one major surface thereof to form features of a first electrode sub-assembly. The formed features include a first surface for supporting integration of a first electrode body and a second surface for supporting integration of a second electrode body. Subsequent plating and masking steps result in the formation of a first electrode body on the first surface and a second electrode body on the second surface. A bridge is integrally formed in the electrically isolating material, so as to electrically isolate the first electrode body from the second electrode body.
US09543135B2	Mass spectrometer and mass analyzing method for efficiently ionizing a sample with less carry-over A mass spectrometer for efficiently ionizing a sample with less carry-over. The ratio of the amount of sample gas to that of a whole headspace gas is increased by decreasing the pressure inside of a sample vessel in which the sample is sealed thereby efficiently ionizing the sample.
US09543133B2	Processing of ion current measurements in time-of-flight mass spectrometers Aspects relate to methods for processing individual spectra acquired with a time-of-flight mass spectrometer to form a sum spectrum. The peak position of a peak and its total intensity are determined in an individual spectrum, and entries in an addition raster of the sum spectrum adjacent to the peak position are selected; then the total intensity is divided up into portions, wherein more of the total intensity is added to entries which are closer to the peak position than is added to entries which are further away from the peak position.
US09543132B2	Multi-dimensional survey scans for improved data dependent acquisitions A method of analyzing ions is disclosed comprising performing an initial multi-dimensional survey scan comprising separating parent ions according to a first physico-chemical property (e.g. ion mobility) and then separating the parent ions according to a second physico-chemical property (e.g. mass to charge ratio). A plurality of parent ions of interest are then determined from the initial multi-dimensional survey scan. Once parent ions of interest have been determined, the plurality of parent ions of interest are sequentially selected based upon the first and second physico-chemical properties during a single cycle of separation. The parent ions of interest may then be fragmented and corresponding fragment ions may then be mass analyzed.
US09543128B2	Sputtering target for forming protective film and laminated wiring film A sputtering target for forming protective film according to the invention is used to form protective film on one surface or both surfaces of a Cu wiring film, and includes 8.0 to 11.0% by mass of Al, 3.0 to 5.0% by mass of Fe, 0.5 to 2.0% by mass of Ni and 0.5 to 2.0% by mass of Mn with a remainder of Cu and inevitable impurities. In addition, a laminated wiring film includes a Cu wiring film and protective film formed on one surface or both surfaces of the Cu wiring film, and the protective film is formed by using the above sputtering target.
US09543127B2	Method and table assembly for applying coatings to spherical components A method of coating spherical components with a coating process in which the spherical components have a surface area includes positioning the spherical components within a containment boundary on a moving member and positioning the moving member within a chamber. The method includes reducing the pressure within the chamber to less than one atmosphere. The method also includes revolving the moving member about a longitudinal axis. The method further includes oscillating the moving member in a direction of the longitudinal axis and commencing the coating process. The oscillating and revolving produce motion of the spherical components within the containment boundary such that an entirety of the surface area of each component is exposed to the coating process.
US09543125B2	Directing plasma distribution in plasma-enhanced chemical vapor deposition Plasma-enhanced chemical vapor deposition (PECVD) devices enable the generation of a plasma in a plasma zone of a deposition chamber, which reacts with a surface of a substrate to form a deposited film in the fabrication of a semiconductor component. The plasma generator is often positioned over the center of the substrate, and the generated plasma often remains in the vicinity of the plasma generator, resulting in a thicker deposition near the center than at the edges of the substrate. Tighter process control is achievable by positioning one or more electromagnets in a periphery of the plasma zone and supplying power to generate a magnetic field, thereby inducing the charged plasma to achieve a more consistent distribution within the plasma zone and more uniform deposition on the substrate. Variations in the number, configuration, and powering of the electromagnets enable various redistributive effects on the plasma within the plasma zone.
US09543123B2	Plasma processing apparatus and plasma generation antenna A plasma generation antenna and a plasma processing apparatus can supply a gas and an electromagnetic wave effectively. A plasma processing apparatus 10 includes a processing chamber 100 in which a plasma process is performed; a wavelength shortening plate 480 configured to transmit an electromagnetic wave; and a plasma generation antenna 200 having a shower head 210 provided adjacent to the wavelength shortening plate 480. The shower head 210 is made of a conductor, and has a multiple number of gas holes 215 and a multiple number of slots 220 through which the electromagnetic wave passes. The slots 220 are provided at positions isolated from the gas holes 215.
US09543122B2	Method for controlling an RF generator In one embodiment, an RF generator includes an RF amplifier that includes an RF input, a DC input, and an RF output, the RF amplifier configured to receive at the RF input an RF signal from an RF source; receive at the DC input a DC voltage from a DC source; and provide an output power at the RF output; and a control unit operably coupled to the DC source and the RF source, the control unit configured to receive a power setpoint for the RF output; determine a power dissipation at the RF generator; and alter the DC voltage to a final DC voltage that decreases the power dissipation at the RF generator while enabling the output power at the RF output to be substantially equal to the power setpoint.
US09543121B2	Inductively coupled plasma processing apparatus An inductively coupled plasma processing apparatus performs plasma processing on a substrate by generating an inductively coupled plasma in a plasma generation region in a processing chamber. The apparatus includes a high frequency antenna for generating the inductively coupled plasma in the plasma generation region and a metal window provided between the plasma generation region and the high frequency antenna. The metal window is firstly divided into two or more sections electrically insulated from each other by a line along a peripheral direction of the metal window and then secondly divided into sections electrically insulated from each other by lines along directions crossing with the peripheral direction.
US09543119B2	Multi charged particle beam writing apparatus and method for correcting a current distribution of groups of charged particle beams A multi charged particle beam writing apparatus of the present invention includes an aperture member to form multiple beams, a plurality of first deflectors to respectively perform blanking deflection of a corresponding beam, a second deflector to collectively deflect the multiple beams having passed through the plurality of openings of the aperture member so that the multiple beams do not reach the target object, a blanking aperture member to block each beam that has been deflected to be in the off state by the plurality of first deflectors, and a current detector, arranged at the blanking aperture member, to detect a current value of all beams in the on state in the multiple beams that have been deflected by the second deflector.
US09543118B2	Gold ion beam drilled nanopores modified with thiolated DNA origamis A nanopore structure includes an aperture extending from a first surface to a second surface of a substrate, the aperture having a wall comprising gold ions embedded in the substrate, the wall defining a first diameter; a first deoxyribonucleic acid (DNA) layer including a thiolated DNA strand covalently bonded to the embedded gold ions within the wall of the aperture; and a second DNA layer hydrogen bonded to the first DNA layer, the second DNA layer defines a substantially cylindrical nanopore that defines a second diameter within the wall of the aperture, the second DNA layer including a single-stranded DNA strand; wherein the second diameter is less than the first diameter.
US09543105B2	Component having a multipactor-inhibiting carbon nanofilm thereon, apparatus including the component, and methods of manufacturing and using the component A high power RF energy device component is disclosed that is exposed to high power RF energy in a vacuum environment, and includes a multipactor-inhibiting carbon nanofilm covering at least one surface of the component. A secondary electron efficiency emission (SEE) coefficient of the multipactor inhibiting carbon nanofilm is desirably less than a SEE coefficient of the underlying surface of the component.
US09543093B2	Universal box system A switch actuator device is disclosed. The switch actuator device includes a switch housing, a body having a first and second arm, and a resilient member having a first and second end. The first and second ends of the resilient member are configured to be coupled to the body and switch housing, respectively. The resilient member exerts a first force on the body when the body is at a first position, a second force when the body is at a second position, and a third force when the body is at a threshold position. When the body is rotated about a pivot point from the first to second position, or vice versa, the respective first or second force increases in magnitude and acts on the body to first resist the rotation until the body is in the threshold position, and then assists the rotation.
US09543091B2	Switch unit and game machine A switch unit has a display part that displays an image in at least one input area, a substrate provided above the display part, the substrate having a contact, and at least one substrate opening configured to allow the image in the at least one input area to be viewed from above, an operating button case that covers the substrate, having at least one button case opening, at least one operating button that has translucency, and that is freely pressed down through the at least one button case opening of the operating button case and causes conduction of the contact by being pressed down, light sources mounted on the substrate, that illuminate an area surrounding the at least one operating button, and a light transmissive water-proof sheet made of an elastic member.
US09543088B2	Circuit arrangement for suppressing an arc occurring over a contact gap of a switching member The disclosure relates to a circuit arrangement for suppressing an arc occurring during a switching process, wherein a current bypass path comprises a PTC resistor connected in series with a fuse. The current bypass path is provided in parallel with a switch. The disclosure also relates to a photovoltaic power plant with a photovoltaic generator which is connected to an inverter via DC lines. In this arrangement, such a circuit arrangement is arranged in at least one of the DC lines.
US09543084B2	Switch state detection circuit and switch system A switch state detection circuit according to the present invention comprises: a plurality of switch connection portions to each of which a switch is connected, a connection line to which any one of the switch connection portions is connected in a switchable manner, a detection portion that detects a state of the switch connected to the connection line based on a state of the connection line, and a connection control portion that switches successively each of the switch connection portions and connects it to the connection line, wherein the state of each switch is detected.
US09543081B2	Electrical apparatus with dual movement of contacts comprising a return device with two levers The invention provides electric power line switchgear (10) comprising a main movable contact (14) and a secondary movable contact (16), capable of moving along a main axis A of the switchgear (10), in which the main movable contact (14) is connected to the secondary movable contact (16) by means of a crank mechanism (20) that transforms the movement of the main movable contact (14) in one direction into a movement of the secondary movable contact (16) in an opposite direction; the switchgear being characterized in that the crank mechanism (20) comprises two levers (22, 24) mounted to pivot relative to the stationary housing (12) about respective parallel pivot axes (B, C), each lever (22, 24) being connected firstly to a respective one of the main movable contact (14) and the secondary movable contact (16), and secondly to the other lever (24, 22).
US09543080B1	Hydrogen hydrothermal reaction tube for use in nanoparticle production and nanoparticle applications A hydrogen based mixing system for the fabrication of nanoparticles allowing for selection of specified particle size, narrow particle size distribution and core shell nanoparticle encapsulation. A further description of a Dense Energy UltraCapacitor that utilizes the core shell nanoparticles to create an energy storage device.
US09543079B2	Production process for electrode material, electrode and electric storage device The present invention relates to a production process for an electrode material, an electrode and an electric storage device, and the production process for an electrode material comprises a step of heating a polymer having a silicon-containing unit and a silicon-non-containing unit.
US09543077B2	Separator with heat resistant insulation layer A separator with a heat resistant insulation layer includes a porous substrate, and a heat resistant insulation layer formed on one surface or both surfaces of the porous substrate and containing at least one kind of inorganic particles and at least one kind of a binder, wherein a content mass ratio of the inorganic particles to the binder in the heat resistant insulation layer is in a range from 99:1 to 85:15, a BET specific surface area of the inorganic particles is in a range from 3 m2/g to 50 m2/g, and a ratio of the moisture content per mass of the binder to the BET specific surface area of the inorganic particles is greater than 0.0001 and smaller than 2.
US09543075B2	Niobium powders having a particle shape A valve metal powder having a particle shape factor mean value f, as determined by SEM image analysis, of 0.65≦f≦1, said powder has an average agglomerate particle size D50 value, as determined with a MasterSizer in accordance with ASTM B 822, of 40 to 200 μm and wherein the valve metal powder is niobium.
US09543072B2	Inductive power harvester with power limiting capability A power harvester having a current transformer configured to be inductively coupled to a current conductor and a circuit for delivering power to a load. The transformer core has two sections joined together and separable from one another at interleaved portions, allowing the transformer to be installed around the current conductor. The circuit includes a rectifier coupled to the transformer and a transistor coupled in series between the rectifier and a load. The transistor receives an output current from the rectifier and provides power to the load. A resistor is coupled to the transistor and the load, and the transistor and resistor provide for limiting of the power to the load over a wide range of the conductor line currents.
US09543070B2	Chip coil component A chip coil component may include: a ceramic body including a plurality of first to fourth insulating layers, and an internal coil including a first internal pattern part having the plurality of first insulating layers on which first pattern portions are disposed and a second internal pattern part having the plurality of second insulating layers on which second pattern portions are disposed. The first pattern portions disposed on the plurality of first insulating layers are disposed to correspond to each other and are connected to each other by two first connection terminals each having one via electrode, and the second pattern portions disposed on the plurality of second insulating layers are disposed to correspond to each other and are connected to each other by two second connection terminals each having one via electrode.
US09543067B2	Magnetic pre-conditioning of magnetic sensors Methods, systems and apparatus are provided to apply a magnetic pre-conditioning to magnetic tunneling junction (MTJ) sensors and other micro-magnetic devices after fabrication but before testing, trimming or other subsequent processing. The fabricated sensor device is passed through a magnetic field that has a known direction and orientation relative to the device so that the device is placed into a known state prior to final testing and trimming. Various embodiments allow the field to be applied in situ by a permanent magnet or electromagnet as the devices are being processed by a conventional device handler or similar processing system.
US09543066B2	Superconducting magnets with thermal radiation shields A cylindrical superconducting magnet has a number of axially-aligned annular coils of superconducting wire, arranged for cooling by thermal conduction through a cooled surface in mechanical contact with the coils. The coils are provided with a cryogenic radiation shield located between respective radially inner surfaces of the coils and respective axes of the coils. The cryogenic radiation shield is formed of a metal layer in thermal contact with the cooled surface.
US09543062B2	Positioning device for cable accessories and methods and assemblies including same A pre-expanded cover unit for an electrical cable includes a cold-shrinkable, tubular, elastomeric cover sleeve, a removable holdout, and a positioning device. The cover sleeve defines a cover sleeve through passage configured to receive the electrical cable. The holdout is mounted within the cover sleeve through passage and configured to be withdrawn therefrom. The holdout maintains the cover sleeve in an expanded state in which the cover sleeve is elastically expanded and, when withdrawn from the cover sleeve through passage, permits the cover sleeve to radially contract to a contracted state about the electrical cable. The positioning device is secured to the cover sleeve and includes a cable clamp. The cable clamp is configured to secure the positioning device to the electrical cable such that, when the holdout is withdrawn from the cover sleeve, the positioning device axially constrains the cover sleeve relative to the cable to axially align the contracted cover sleeve with the electrical cable.
US09543053B2	Electron beam equipment To improve the efficiency of generation of chromatic aberrations of an energy filter for reducing energy distribution. Mounted are an energy filter for primary electrons, the energy filter having a beam slit and a pair of a magnetic deflector and an electrostatic deflector that are superimposed with each other. An electron lens is arranged between the beam slit and the pair of the magnetic deflector and the electrostatic deflector.
US09543049B2	Apparatus for holding radioactive objects An apparatus for holding radioactive objects includes a base and a central pillar extending upwardly between a bottom end coupled to the base and a top end above the base. A plurality of inner segments are spaced around the central pillar, and a plurality of outer segments are spaced around the inner segments to form pairs. The inner segments, the outer segments and the central pillar may be coupled together to permit limited radial movement of at least one of the segments of each pair. Each pair may define a generally vertical, object-receiving channel arranged between the inner and outer segment of the pair. The segments of each pair may be adapted to bear against an object in the channel of the pair to laterally restrain the object and facilitate heat transfer from the object.
US09543043B2	Method for testing array fuse of semiconductor apparatus A method for testing an array fuse block of a semiconductor apparatus may include a series of operations for testing an array fuse block of the semiconductor apparatus as a test program is executed. The series operations may include the following steps: generating a test source file containing information for accessing the array fuse block; generating a test vector using the test source file; extracting repair confirmation information by performing a simulation using the test vector; extracting a repair confirmation information expected value from the test source file; and determining a pass or fail by comparing the repair confirmation information to the repair confirmation information expected value.
US09543042B2	Semiconductor memory apparatus A semiconductor memory apparatus includes a first comparison block configured to compare a plurality of channel data with one another and generate a first comparison signal, or output one of the plurality of channel data as the first comparison signal, in response to a plurality of channel select signals; a second comparison block configured to compare the plurality of channel data and generate a second comparison signal when the plurality of channel select signals have a predetermined combination and a channel detection signal has a predetermined logic level; a channel selection detection block configured to enable the channel detection signal when only one channel select signal among the plurality of channel select signals is enabled; and a combined output block configured to enable a test result signal when at least one comparison signal of the first and second comparison signals is enabled.
US09543040B2	Shift register unit and driving method thereof, gate driver and display device Provided are a shift register unit and driving method thereof, a gate driver and a display device, the circuit configuration of the shift register unit can be simplified by disposing, in the shift register unit, the signal input unit for outputting the first level signal or the second level signal to the first terminal of the latch unit under the control of the input signal and the reset signal, the latch unit for latching the signal input from the signal input unit and outputting the latched processed signal to the pull-down unit, the pull-down unit for outputting the first level signal or the second level signal to the signal output unit under the control of the latched processed signal, and the signal output unit for receiving and inverting the signal output from the pull-down signal to generate an output signal and outputting a signal being opposite to the output signal, which is helpful for achieving the narrow bezel of the display panel.
US09543038B2	Shift register and control method thereof A shift register has a first switch, a pull-up circuit, and a pull-down circuit. The first switch receives a first clock signal. The pull-up circuit is configured to turn on the first switch to pull up a voltage level of an output terminal of the shift register. The pull-up circuit has a second switch and a first control circuit. The first control circuit is coupled to a first system power terminal to avoid an excessive voltage difference between two nodes of the first control circuit. The pull-down circuit is configured to pull down the voltage level of the output terminal of the shift register when the first switch is turned off, and further configured to keep a voltage level of a control node of a switch coupled between the output terminal and a second system power terminal at a low voltage.
US09543031B2	Semiconductor device to improve reliability of read operation for memory cells A semiconductor device includes memory cells; an operation circuit suitable for performing a read operation on the memory cells; and a check circuit suitable for comparing the number of memory cells of which threshold voltages are divided by the read operation, wherein the operation circuit changes a read voltage to be applied to the memory cells in the read operation, based on a result of the comparison.
US09543030B1	Sense amplifier design for ramp sensing Methods and systems for sensing memory cells using a sense amplifier that can support both ramp sensing and conventional sensing are described. With ramp sensing, a word line of a memory array may be ramped up linearly and a sensing operation may be performed by the sense amplifier while the word line is continuously being ramped up. In this case, during the sensing operation, the sense amplifier may sense a bit line of the memory array connected to a memory cell while the word line is ramping up and then transfer the result into a data latch. In contrast, with conventional sensing, a bit line of the memory array may be first precharged to a particular voltage level (e.g., a read voltage level) and then sensed while the word line is held at the particular voltage level.
US09543029B2	Non-volatile semiconductor memory device and reading method for non-volatile semiconductor memory device that includes charging of data latch input node prior to latching of sensed data A non-volatile semiconductor memory device includes a memory cell, and a sense amplifier that includes a latch unit, a first transistor having a first end electrically connected to the latch unit and a second end electrically connected to a first node, a second transistor having a first end electrically connected to the first node and a second end electrically connected to the memory cell, and a third transistor having a first end electrically connected to a second node between the first end of the first transistor and the latch unit. A control unit of the device controls the sense amplifier during a read operation, to charge the second node to a first voltage, and then charge the first node to a second voltage, turn on the second transistor after charging the first node to the second voltage, and turn on the third transistor after turning on the second transistor.
US09543028B2	Word line dependent temperature compensation scheme during sensing to counteract cross-temperature effect Methods for reducing cross-temperature dependent word line failures using a temperature dependent sensing scheme during a sensing operation are described. In some embodiments, during a read operation, the sensing conditions applied to memory cells within a memory array (e.g., the sensing time, source line voltage, or bit line voltage) may be set based on a temperature of the memory cells during sensing and a word line location of the memory cells to be sensed. In one example, the memory array may comprise a NAND memory array that includes a NAND string and the sensing time for sensing a memory cell of the NAND string and the source line voltage applied to a source line connected to a source end of the NAND string may be set based on the temperature of the memory cells during sensing and the word line location of the memory cells to be sensed.
US09543026B2	Nonvolatile memory device and operating method thereof An operating method of a nonvolatile memory device is provided. The nonvolatile memory device includes first and second page buffers, and first and second bit lines connected thereto, respectively. First and second latch nodes of the first page buffer are charged to have a voltage having a first level according to data stored in a first latch of the first page buffer. After the charging of the first latch node is started, a sensing node of the second page buffer is pre-charged. The sensing node is connected to the second bit line. Data stored in the first latch is dumped into a second latch of the first page buffer during the pre-charging of the sensing node of the second page buffer.
US09543025B2	Storage control system with power-off time estimation mechanism and method of operation thereof A storage control system, and a method of operation thereof, including: a power-down module for powering off a memory sub-system; a decay estimation module, coupled to the power-down module, for estimating a power-off decay rate upon the memory sub-system powered up, the power-off decay rate is for indicating how much data in the memory sub-system has decayed while the memory sub-system has been powered down; and a recycle module, coupled to the decay estimation module, for recycling an erase block for data retention based on the power-off decay rate.
US09543021B2	Semiconductor device and programming method thereof A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular direction from a semiconductor substrate, a peripheral circuit configured to program the memory cells, and a control circuit configured to program a memory cell selected from the plurality of memory cells to trap charge in the selected memory cell, and to issue at least one command to the peripheral circuit to manage a dispersion of at least a portion of the trapped charge between memory cells adjacent to the selected memory cell.
US09543020B2	Nonvolatile semiconductor memory device A nonvolatile semiconductor memory device includes an array of memory cells arranged at the position intersecting positions of the word line and the bit line, a control signal generating circuit for carrying out a writing operation including a program for carrying out writing in the memory cell and a verification for verifying whether the data has been correctly written in the memory cell by the program, and a cell source monitoring circuit for detecting a voltage of the source line connected to the memory cell during the writing operation. The control signal generating circuit directly shifts the source line voltage at the time of program to a lower voltage necessary at the time of verification after the end of the program, based on the voltage the source line detected by the cell source monitoring circuit.
US09543019B2	Error corrected pre-read for upper page write in a multi-level cell memory Methods, apparatuses and articles of manufacture may receive a first page of data and correct one or more errors in the first page of data to generate a page of corrected data. A program command may then be sent with a second page of data and the page of corrected data, to program a page of memory to store the second page of data.
US09543018B2	Non-volatile memory with a variable polarity line decoder The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the first row of memory cells, and a second driver coupled to a control line of the second row of memory cells. The first driver is made in a first well, the second driver is made in a second well electrically insulated from the first well, and the two rows of memory cells are produced in a memory array well electrically insulated from the first and second wells.
US09543013B1	Magnetic tunnel junction ternary content addressable memory A Magnetic Tunnel Junction (MJT) Ternary Content Addressable Memory (TCAM) employing six transistors and exhibiting reduced standby leakage and improved area-efficiency. In the proposed TCAM, data can be written to the MJT devices by conventional current induced magnetization techniques and by controlling the source line, thereby eliminating the need for external writing circuitry.
US09543012B2	System for writing data in a memory A system including: a first memory including several portions of one or more pages each, said memory including first and second ports that can simultaneously access, for reading and writing respectively, two distinct pages of portions of the memory; and a control circuit capable of performing write operations to the pages of the memory, each write operation to a page of the memory requiring a reading step of a former datum on said page via the first port, and including a writing step of a new datum to the page via the second port, taking account of the former datum.
US09543007B2	Semiconductor device including memory cell and sense amplifer, and IC card including semiconductor device A semiconductor device includes a memory cell; circuitry that generates a reference voltage; and a sense amplifier including a first input terminal electrically connected to the memory cell, and a second input terminal electrically connected to the circuitry. The sense amplifier obtains a value in correlation with a resistance value of the memory cell based on a comparison between a sense voltage applied to the first input terminal and the reference voltage applied to the second input terminal. The sense voltage changes at a speed in correlation with the resistance value of the memory cell. In at least part of a period during which the sense voltage changes, the circuitry causes the reference voltage to change in a direction opposite to a direction in which the sense voltage changes.
US09543003B2	Memory array plane select Memory arrays and methods of forming the same are provided. An example memory array can include at least one plane having a plurality of memory cells arranged in a matrix and a plurality of plane selection devices. Groups of the plurality of memory cells are communicatively coupled to a respective one of a plurality of plane selection devices. A decode logic having elements is formed in a substrate material and communicatively coupled to the plurality of plane selection devices. The plurality of memory cells and the plurality of plane selection devices are not formed in the substrate material.
US09542998B1	Write assist circuit integrated with leakage reduction circuit of a static random access memory for increasing the low voltage supply during write operations A transient voltage collapse circuit provides a reference voltage for an SRAM (static random access memory). The SRAM receives a first reference voltage and a second reference voltage higher than the first reference voltage. The transient voltage collapse circuit provides the first reference voltage to the SRAM via a voltage supply line. The transient voltage collapse circuit maintains the voltage supply line at a first voltage level during a power save mode of the SRAM. The transient voltage collapse circuit increases the voltage of the voltage supply line during a write operation of the SRAM. The increase in the voltage of the supply line reduces the gap between first reference voltage and the second reference voltage, thereby assisting with the write operation of the SRAM.
US09542993B2	Leakage-current abatement circuitry for memory arrays In one memory array embodiment, in order to compensate for bit-line leakage currents by OFF-state bit-cell access devices, a leakage-current reference circuit tracks access-device leakage current over different process, voltage, and temperature (PVT) conditions to generate a leakage-current reference voltage that drives a different leakage-current abatement device connected to each different bit-line to inject currents into the bit-lines to compensate for the corresponding leakage currents. In one implementation, the leakage-current reference circuit has a device that mimics the leakage of each access device configured in a current mirror that drives the resulting leakage-current reference voltage to the different leakage-current abatement devices.
US09542987B2	Magnetic memory cells with low switching current density Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a substrate defined with a memory cell region. A cell selector unit is defined on the substrate. The cell selector unit includes at least one select transistor. A storage element which includes a magnetic tunnel junction (MTJ) element is coupled to the selector unit. The MTJ element includes a free layer, a fixed layer and a tunnel barrier sandwiched between the fixed and free layers. A spin-orbit-torque (SOT) layer is coupled to the selector unit and is in direct contact with the free layer. A strain induced layer is coupled to a digital line (DL) and is in direct contact with the SOT layer. When the DL is activated, an electric field applied to the strain induced layer induces a strain on the SOT layer.
US09542986B2	Low power input gating Various implementations described herein are directed to an integrated circuit for implementing low power input gating. In one implementation, the integrated circuit may include a chip enable device configured to receive and use a clock input signal to toggle a control input of memory based on a chip enable signal. The integrated circuit may include a latch device configured to latch the control input of the memory. The integrated circuit may include a latch enable device coupled between the chip enable device and the latch device. The latch enable device may be configured to receive the clock input signal from the chip enable device and use the clock input signal to gate the latch device based on a latch enable signal so as to selectively cutoff toggling of the clock input signal to the control input of the memory.
US09542985B2	Channel skewing The present disclosure includes methods and systems for channel skewing. One or more methods for channel skewing includes providing a number of groups of data signals to a memory component, each of the number of groups corresponding to a respective channel, and adjusting a phase of a group of data signals corresponding to at least one of the number of channels such that the group of data signals are skewed with respect to a group of data signals corresponding to at least one of the other respective channels.
US09542983B1	Semiconductor devices and semiconductor systems including the same A semiconductor device may include a buffer control signal generation circuit, an input control signal generation circuit and an internal data generation circuit. The buffer control signal generation circuit may be configured to generate a buffer control signal. The buffer control signal may be enabled in synchronization with a point of time that a predetermined section elapses from a point of time that a write command signal is generated. The input control signal generation circuit may be configured to receive a data strobe signal to generate an input control signal, in response to the buffer control signal. The internal data generation circuit may be configured to receive a data signal to generate internal data.
US09542979B1	Memory structure A memory structure includes N array regions and N page buffers coupled to the N array regions, respectively. N is an integer ≧2. Each of the N array regions includes a 3D array of a plurality of memory cells. The memory cells have a lateral distance d between two adjacent memory cells on a horizontal cell plane of the 3D array. Each of the N array regions further includes a plurality of conductive lines. The conductive lines are disposed over and coupled to the 3D array. The conductive lines have a pitch p, and p/d=⅕ to ½. The N array regions and the N page buffers are arranged on one line along an extension direction of the conductive lines.
US09542978B2	Semiconductor package with terminals adjacent sides and corners A semiconductor package includes: a plurality of memory packages which are arranged on a substrate; and a logic chip, which has a rhombus shape including first through fourth corners and first through fourth sides connecting the first through fourth corners, is arranged adjacent to the plurality of memory packages, and includes a plurality of terminals that are electrically connected to the plurality of memory packages, as seen on a plan view of the semiconductor package, wherein the plurality of terminals include system address terminals which are adjacent to the first corner of the logic chip and first and second system data terminals which are respectively arranged on the first and second sides contacting the first corner. Another semiconductor package and a method of fabrication are disclosed.
US09542977B2	Semiconductor device and electronic device Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.
US09542975B2	Centralized database for 3-D and other information in videos Methods and systems for a centralized database for 3-D and other information in videos are presented. A centralized database contains video metadata such as camera, lighting, sound, object, depth, and annotation data that may be queried for and used in the editing of videos, including the addition and removal of objects and sounds. The metadata stored in the centralized database may be open to the public and admit contributor metadata.
US09542973B1	Adaptive data-dependent noise-predictive maximum likelihood detection for channels with non-linear transition shifts In one embodiment, a data storage system includes a head configured to produce a signal representing data stored on a storage medium, a bank of noise whitening filters configured to apply one or more noise whitening filters to the signal to produce a filtered signal, and a data-dependent noise mean calculator configured to estimate a data-dependent noise mean from the filtered signal. The system also includes a branch metric calculator configured to perform one or more branch metric calculations on the filtered signal to produce one or more branch metrics, the one or more branch metric calculations accounting for the data-dependent noise mean. Moreover, the system includes an adaptive data-dependent noise-predictive maximum likelihood (D3-NPML) detector configured to generate an output stream from the one or more branch metric calculations.
US09542967B2	Magnetic recording medium There is provided a magnetic recording medium including a surface having a longitudinal direction and a lateral direction. An arithmetic average roughness Ra, a ratio PSDMD,short/PSDTD,short, and a ratio PSDMD,long/PSDTD,long on the surface satisfy Ra≦3.0 nm, PSDMD,short/PSDTD,short≦0.65, and 1.3≦PSDMD,long/PSDTD,long≦2.3, in which PSDMD,short is an average value of PSD values in a range from 0.15 μm to 0.4 μm in the longitudinal direction of the surface, PSDTD,short is an average value of PSD values in a range from 0.15 μm to 0.4 μm in the lateral direction of the surface, PSDMD,long is an average value of PSD values in a range from 0.4 μm to 5.0 μm in the longitudinal direction of the surface, and PSDTD,long is an average value of PSD values in a range from 0.4 μm to 5.0 μm in the lateral direction of the surface.
US09542965B2	Skewed shingled magnetic recording data reader A data storage device may be configured with at least a transducing head separated from a data storage medium. The transducing head can have a data reader and data writer. A plurality of data bits may be arranged in first and second shingled data tracks on the data storage medium. The data writer can be configured with a writer centerline aligned with a track centerline of the first shingled data track and a data reader having a reader centerline skewed with respect to the track and writer centerlines.
US09542963B2	Method and apparatus to detect and mitigate contamination between a read/write head and a recording medium A first adaptive fly height measurement is performed between a read/write head and a recording medium during a stage of qualification testing of a magnetic disk drive. A second adaptive fly height measurement of the read/write head is performed during a subsequent stage of the qualification testing. In response to determining that a fly height decrease between the first and second adaptive fly height measurements is above a threshold value, a mitigation operation is performed to remove a contaminant from a media-facing surface of the read/write head.
US09542961B2	Magnetoresistive sensor with stop-layers Tolerances for manufacturing reader structures for transducer heads continue to grow smaller and storage density in corresponding storage media increases. Reader stop layers may be utilized during manufacturing of reader structures to protect various layers of the reader structure from recession and/or scratches while processing other non-protected layers of the reader structure. For example, the stop layer may have a very low polish rate during mechanical or chemical-mechanical polishing. Surrounding areas may be significantly polished while a structure protected by a stop layer with a very low polish rate is substantially unaffected. The stop layer may then be removed via etching, for example, after the mechanical or chemical-mechanical polishing is completed.
US09542959B2	Protecting information written to recording medium A data storage device can include a recording medium; a controller unit to generate control signals in response to write information and write commands; and a transducer section coupled to receive the controls signals, and in response, write the write information into the recording medium and form a data protection pattern in the recording medium adjacent to the write information.
US09542950B2	Method for reduction of aliasing introduced by spectral envelope adjustment in real-valued filterbanks The present invention proposes a new method for improving the performance of a real-valued filterbank based spectral envelope adjuster. By adaptively locking the gain values for adjacent channels dependent on the sign of the channels, as defined in the application, reduced aliasing is achieved. Furthermore, the grouping of the channels during gain-calculation, gives an improved energy estimate of the real valued subband signals in the filterbank.
US09542948B2	Text-dependent speaker identification Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for speaker verification. The methods, systems, and apparatus include actions of inputting speech data that corresponds to a particular utterance to a first neural network and determining an evaluation vector based on output at a hidden layer of the first neural network. Additional actions include obtaining a reference vector that corresponds to a past utterance of a particular speaker. Further actions include inputting the evaluation vector and the reference vector to a second neural network that is trained on a set of labeled pairs of feature vectors to identify whether speakers associated with the labeled pairs of feature vectors are the same speaker. More actions include determining, based on an output of the second neural network, whether the particular utterance was likely spoken by the particular speaker.
US09542942B2	Promoting voice actions to hotwords Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for designating certain voice commands as hotwords. The methods, systems, and apparatus include actions of receiving a hotword followed by a voice command. Additional actions include determining that the voice command satisfies one or more predetermined criteria associated with designating the voice command as a hotword, where a voice command that is designated as a hotword is treated as a voice input regardless of whether the voice command is preceded by another hotword. Further actions include, in response to determining that the voice command satisfies one or more predetermined criteria associated with designating the voice command as a hotword, designating the voice command as a hotword.
US09542936B2	Fast out-of-vocabulary search in automatic speech recognition systems A method including: receiving, on a computer system, a text search query, the query including one or more query words; generating, on the computer system, for each query word in the query, one or more anchor segments within a plurality of speech recognition processed audio files, the one or more anchor segments identifying possible locations containing the query word; post-processing, on the computer system, the one or more anchor segments, the post-processing including: expanding the one or more anchor segments; sorting the one or more anchor segments; and merging overlapping ones of the one or more anchor segments; and searching, on the computer system, the post-processed one or more anchor segments for instances of at least one of the one or more query words using a constrained grammar.
US09542931B2	Leveraging interaction context to improve recognition confidence scores On a computing device a speech utterance is received from a user. The speech utterance is a section of a speech dialog that includes a plurality of speech utterances. One or more features from the speech utterance are identified. Each identified feature from the speech utterance is a specific characteristic of the speech utterance. One or more features from the speech dialog are identified. Each identified feature from the speech dialog is associated with one or more events in the speech dialog. The one or more events occur prior to the speech utterance. One or more identified features from the speech utterance and one or more identified features from the speech dialog are used to calculate a confidence score for the speech utterance.
US09542930B2	System and method for enhancing locative response abilities of autonomous and semi-autonomous agents A computer system and method according to the present invention can receive multi-modal inputs such as natural language, gesture, text, sketch and other inputs in order to simplify and improve locative question answering in virtual worlds, among other tasks. The components of an agent as provided in accordance with one embodiment of the present invention can include one or more sensors, actuators, and cognition elements, such as interpreters, executive function elements, working memory, long term memory and reasoners for responses to locative queries, for example. Further, the present invention provides, in part, a locative question answering algorithm, along with the command structure, vocabulary, and the dialog that an agent is designed to support in accordance with various embodiments of the present invention.
US09542929B2	Systems and methods for providing non-lexical cues in synthesized speech Systems and methods for providing non-lexical cues in synthesized speech are described herein. Original text is analyzed to determine characteristics of the text and/or to derive or augment an intent (e.g., an intent code). Non-lexical cue insertion points are determined based on the characteristics of the text and/or the intent. One or more nonlexical cues are inserted at insertion points to generate augmented text. The augmented text is synthesized into speech, including converting the non-lexical cues to speech output.
US09542925B2	Generating sound for a rotating machine of a device The invention relates to a method for generating sound for a rotating machine, including a step (E1) of determining the frequencies and amplitudes of n partials and/or harmonics (i) pertaining to the sound of a rotating machine, characterized in that the method includes a step (E2) of determining values (a1) and a step (E7-E8) of calculating a synthetic sound for the rotating machine, said synthetic sound being composed from the n partials and/or harmonics (i), while the frequency thereof is entirely or partially shifted by the values (ai).
US09542923B1	Music synthesizer A music synthesizer is provided. The synthesizer divides an input sound into a plurality of musical bands, and, for each divided band, generates a waveform having a predetermined shape with a period corresponding to a detected pitch and with a level corresponding to a detected level. The synthesizer then adds up the waveforms generated for each band and outputs a result thereof.
US09542921B2	Manually advanced sequencer An improved method of manually advancing through Steps in a Sequence using an electromechanical momentary switch, an electronic device capable of detecting changes in the state of said electromechanical momentary switch, and a Sequencer, whereby said electronic device will, upon detecting each change of state in said electromechanical momentary switch, trigger said Sequencer to advance to a next Step in a Sequence and recall a Data Set associated with said Step.
US09542919B1	Cyber reality musical instrument and device Systems and methods for creating and presenting sensory stimulating content in a cyber reality environment. One aspect of the disclosure allows a composer to associate audio content with one or more virtual triggers, and to define behavior characteristics which control the functioning of each virtual trigger. Another aspect of the disclosure provides a variety of user interfaces through which a performer can cause content to be presented to an audience.
US09542914B2	Display system with improved graphics abilities while switching graphics processing units Methods and apparatuses are disclosed for improving graphics abilities while switching between graphics processing units (GPUs). Some embodiments may include a display system, including a plurality of graphics processing units (GPUs) and a memory buffer coupled to the GPUs via a timing controller, where the memory buffer stores data associated with a first video frame from a first GPU within the plurality of GPUs and where the timing controller is switching between the first GPU and a second GPU within the plurality.
US09542913B2	Common voltage driving compensation unit, method and display panel using the same A common voltage driving compensation unit is disclosed, comprising: an operational amplifier and a controller, wherein an in-phase input terminal and a reverse-phase input terminal of the operational amplifier are inputted a common voltage and a feedback voltage respectively. Multiple paths are provided in parallel between the reverse-phase input terminal and a first output terminal, and each path including an analog switch and a resistor. The controller is configured to control a combination of on and off of the analog switches based on a range to which the count value of the CPV signal belongs. The common voltage driving compensation unit is configured to produce corresponding amplification ratios based on the combination, so as to provide common voltages with corresponding amplification ratios for the compensation of the common electrodes in different display areas. For a display panel with a heavy-load, the fluctuation coupling of the common electrodes may be compensated.
US09542912B2	Information processing device and program An information processing device includes: execution means for executing an application program; determination means for determining a size of a window to be displayed depending on the application program; receiving means for receiving at least one data set from among a plurality of data sets; data selection means for selecting one data set from among the plurality of data sets, depending on the window size determined by the determination unit; execution control means for controlling the execution means to process the one data set selected by the data selection means from among the received at least one data set, in accordance with the application program; and display control means for controlling the display means to show a screen based on the one data set to be processed by the execution means.
US09542907B2	Content adjustment in graphical user interface based on background content Adjustments to content to be rendered on top of background content, such as wallpaper, in a graphical user interface are disclosed. One example method can include adjusting a color characteristic of new content to be rendered on top of the background content, based on at least one color characteristic of the background content, so as to preserve the new content's color. Another example method can include adjusting a color characteristic of text to be rendered on top of the background content, based on at least one color characteristic of the background content, so that the text is legible.
US09542905B2	Display device and control method for display device A display device that can be used with another display device, includes: a display unit; a command receiving unit which receives a control command or ID information from an external remote controller; and a command processing unit. The display unit displays the display device's own ID in response to reception of the control command by the command receiving unit. If the command receiving unit receives the ID information indicating the display device's own ID after the display unit starts displaying the display device's own ID, the command processing unit performs processing corresponding to the control command.
US09542898B2	Driving method of a liquid crystal display panel, a liquid crystal display panel and a display device This invention provides a liquid crystal display panel, a source driver in the liquid crystal display panel comprises an amplifier whose amplification coefficient is adjustable, the amplifier can adjust a received data signal based on a currently selected amplification coefficient, and output the adjusted data signal to a data line that is currently signally-connected with the amplifier, moreover, the currently selected amplification coefficient is inversely proportional to a rate at which the data line charges a current signally-connected sub-pixel unit. For the case that the rate at which the data line charges the sub-pixel unit is relatively low, a relative large amplification coefficient can be selected, thereby nonuniform brightness of the display image caused by a low charging rate of the sub-pixel unit can be avoided; for the case that the rate at which the data line charges the sub-pixel unit is relatively high, a relatively small amplification coefficient is selected, thereby unnecessary power consumption can be saved. This invention further provides a display device comprising such a liquid crystal display panel and a driving method for use in such a liquid crystal display panel.
US09542897B2	Gate signal line drive circuit and display device A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
US09542892B2	Organic light-emitting diode display with reduced lateral leakage A display may have an array of pixels. Each pixel may have a light-emitting diode that emits light under control of a drive transistor. The organic light-emitting diodes may have a common cathode layer, a common electron layer, individual red, green, and blue emissive layers, a common hole layer, and individual anodes. The hole layer may have a hole injection layer stacked with a hole transport layer. Pixel circuits for controlling the diodes may be formed from a layer of thin-film transistor circuitry on a substrate. A planarization layer may cover the thin-film transistor layer. Lateral leakage current between adjacent diodes can be blocked by shorting the common hole layer to a metal line such as a bias electrode that is separate from the anodes. The metal line may be laterally interposed between adjacent pixels and may be formed on the planarization layer or embedded within the planarization layer.
US09542891B2	Organic electroluminescence display and driving method thereof An organic electroluminescence display that drives a display panel by a digital driving scheme. The organic electroluminescence display includes: a data driver that supplies a data signal in units of subframes to the display panel; and a power supply that supplies a high-potential voltage to the display panel, wherein the power supply that varies the high-potential voltage supplied to subpixels of the display panel for each subframe.
US09542890B2	Display device including function of reducing luminance gradient According to one embodiment, a display device includes a plurality of pixel units which each includes a light-emitting element and a pixel circuit, a plurality of first scan lines and second scan lines, a plurality of video signal lines, a controller which controls a scan line drive circuit and a signal line drive circuit, wherein the pixel circuit comprises an output switch, a drive transistor, a capacitance, and a pixel switch, wherein the controller controls a reset operation, a cancellation operation, a correction operation, and a light-emitting operation, and the controller deforms a waveform of a control signal which is supplied from the second scan line in a manner that a time of transitioning the pixel switch from an on-state to an off-state is longer than the time of transitioning by a non-deformed control signal, when writing the video voltage signal in the correction operation.
US09542889B2	Display device configured to be driven in one of a plurality of modes A display device is disclosed. In one aspect, the display device includes a timing controller configured to receive an image signal and a control signal and output a mode signal and a gate pulse signal based on the image signal and the control signal, wherein the mode signal has a voltage level and wherein the gate pulse signal has a frequency. The display device further includes a clock generator configured to generate a gate clock signal based on the mode signal and the gate pulse signal, wherein the gate clock signal has a voltage level and wherein the clock generator is further configured to set the voltage level of the gate clock signal based at least in part on the mode signal. The display device includes gate lines and a gate driver configured to drive gate lines based at least in part on the gate clock signal.
US09542888B2	Display apparatus According to one embodiment, a display apparatus includes a plurality of semiconductor layers, a first insulation film, a first conductive layer, a second insulation film and a display element includes a second conductive layer. The first conductive layer and the second conductive layer are opposed to each other to form a capacitance unit.
US09542886B2	Organic light emitting display device and method for driving the same A pixel includes a driving transistor, an organic light emitting diode, a first transistor, and the second transistor. The driving transistor includes a gate electrode coupled to a first node, a first electrode coupled to a second node, and a drain electrode coupled to a third node. The driving transistor controls an amount of drain-source current based on a level of a voltage applied to the first node. The first transistor is coupled between the second node and a data line, and turns on by a scan signal of a scan line. The second transistor is coupled between the first node and an initialization voltage line, and turns on by an initialization signal of an initialization line. The first and second transistors are turned on during a first period.
US09542882B2	Organic light emitting diode display An organic light emitting diode display includes: a panel; a data driver connected to a data line formed on the panel; a gate driver crossing the data line in an insulated manner and connected to gate lines formed on the panel; an input line for receiving clock signals from the outside; a first connecting line electrically connected to the input line to supply the clock signal to the gate driver; a second connecting line electrically connected to the input line; and a third connecting line extended from the second connecting line to electrically connect the second connecting line and the first connecting line.
US09542880B2	Eliminating flicker in LED-based display systems A system includes a driver circuit, a modulator circuit, and a reset circuit. The driver circuit drives a plurality of light emitting diodes via a switch. The switch is controlled by a first signal having a first frequency. The driver circuit controls brightness of the light emitting diodes based on a second signal including a plurality of pulses. The modulator circuit modulates the first signal using a direct sequence spread spectrum modulation. The direct sequence spread spectrum modulation uses a sequence generated based on the first signal. The reset circuit resets the modulator circuit at each of the plurality of pulses of the second signal. The modulator circuit repeats the sequence at each of the plurality of pulses of the second signal.
US09542878B2	Shift register unit, display panel and display apparatus A shift register unit includes a latch circuit and a transmission circuit. The latch circuit is configured to process a clock signal received by its first clock signal end and a low level signal by a NOR operation to obtain a signal and output the obtained signal when a selection signal is of a high level; during a first time period where the selection signal is of a low level, process a signal outputted by the latch circuit when the selection signal is of a high level by a NOT operation, then process the resultant signal with a feedback signal by a NOR operation to obtain a signal and output the obtained signal; output a low level signal during a time period where the selection signal is of a low level other than the first time period. The transmission circuit is configured to output a signal related to the clock signal received by its first clock signal end when the signal outputted by the latch circuit is of a high level; and output a corresponding signal when the signal outputted by the latch circuit is of a low level.
US09542876B2	Method of obtaining luminance and chromaticity of white in RGBW display device using RGB display device A method of obtaining luminance and chromaticity of white in the RGBW display using RGB display, including; obtaining spectral values of a q grayscale of red sub-pixels, green sub-pixels and blue sub-pixels of the RGB display; obtaining spectral values of red, green and blue sub-pixels of a color filter in the RGB display; calculating a spectral value of the q greyscale of white in the RGB display as a spectral value of the q grayscale of the white sub-pixels of the RGBW display; calculating tristimulus values WXq, WYq and WZq of the q greyscale of the white sub-pixels of the RGBW display; using the stimulus value WYq as a luminance of the q greyscale of the white sub-pixels of the RGBW display, and using the formulae x = WX q WX q + WY q + WZ q ⁢ ⁢ and y = WY q WX q + WY q + WZ q to calculate a chromaticity (x, y) of the white sub-pixel of the RGBW display.
US09542874B2	Display apparatus A display apparatus includes: a plurality of pixels coupled to gate lines and to data lines configured to cross the gate lines, a gate driver configured to apply gate signals to the gate lines, a first data driver configured to apply first data voltages to first signal lines, a first DEMUX part configured to selectively couple the first signal lines to the data lines, a second data driver configured to apply second data voltages to second signal lines positioned to correspond to the first signal lines, and a second DEMUX part positioned to face the first DEMUX part such that the pixels are positioned between the first and second DEMUX parts, the second DEMUX part configured to couple the second signal lines to the data lines, which are not coupled to the first signal lines. Each of the first data voltages has a polarity opposite to a polarity of a corresponding second data voltage of the second data voltages.
US09542872B2	Data driver for electrophoretic display A data driver for an electrophoretic display (EPD) includes multiple driver sub-circuits. Each of the driver sub-circuits includes first and second latches, first and second capacitors, a multiplexer and a comparator. The first and second latches respectively provide updated latch image data and current latch image data in response to original image data. When the updated and current latch image data correspond to different levels, the comparator controls the multiplexer in a first period to selectively couple one of the first and second capacitors to a driver end, so as to recycle charges at pixels, and controls the multiplexer in a second period to selectively couple the other of the first and second capacitors to the driver end to pre-charge the pixels with the charges.
US09542870B2	Billboard and lighting assembly with heat sink and three-part lens A lighting assembly includes a substantially planar substrate and a number of light emitting diodes (LEDs) arranged in rows on a first surface of the substrate. The rows extend along a longitudinal axis of the substrate. The lighting assembly also includes a number of optical elements, each including a three-part lens. Each optical element is proximate an associated LED such that each optical element overlies a single LED and each LED underlies a single optical element. A heat sink is thermally coupled to a second surface of the substrate that is opposite the first surface. The heat sink has a first section substantially parallel to the substrate and a number of fins extending away from the first section and substantially perpendicular thereto. A longitudinal axis of each fin is substantially perpendicular to the longitudinal axis of the substrate.
US09542868B2	Light emitting device, surface mounted device-type light emitting device, and display device Embodiments of a light emitting device, a surface mounted device-type light emitting device and a display device are provided. In one aspect, a light emitting device may include a main body and a light source. The main body may include a base and a number of terminals. The base may have a support surface. Each of the terminals may respectively have a welding portion such that the welding portions of the terminals form a connection surface with a first angle between the support surface and the connection surface. The first angle may be between 0 degree and 90 degrees. The light source may be disposed on the support surface and electrically connected to one or more of the terminals.
US09542867B2	Vehicle parking space sign system A parking space sign system that is mountable to existing parking bumpers or includes a flexible support structure for placement in parking spaces with parking bumpers, a frame mount having at least one transparent frame sleeve formed by sleeve flanges, at least one panel with indicia on its face and at least one mounting aperture for mounting the frame to a parking bumper with hardware or slotted end caps instead of mounting apertures in the frame mount for sealing the ends of the frame mount and securing it to a parking bumper.
US09542866B1	Device screen protector article An article for protecting a display screen of an electronic device with a display surface. The article may comprise a substrate configured to cover the screen of the device during us of the device, at least a portion of the substrate being substantially transparent to permit viewing of the display surface through the substrate. The substrate may have a perimeter, an outer surface for facing outwardly from the display surface when the substrate is applied to the display surface, and an inner surface for facing toward the display surface when the substrate is applied to the display surface. The article may comprise at least one marking on the substrate.
US09542865B2	Three-dimensional stand alone pop up assembly and method A three dimensional stand alone pop up assembly and method for making the same, the assembly comprising outer structural wall panels connected with an internal support structure having a spreader, center support element and base components. The assembly moves between a first position, whereby the support structure is folded within the wall panels of the outer structure, and a second position whereby outer structural panels are unfolded into a three-dimensional stand-alone pop-up structure supported in the open position by the internal support structure. The assembly utilizes an internal support structure which folds internally and alleviates the need for an extended base or protruding member. The assembly accommodates a variety of lighting and sound features and can be configured in a variety of three dimensional stand alone pop up designs.
US09542863B2	Methods and apparatus for generating output data streams relating to underground utility marking operations Methods and apparatus for generating electronic records of marking operations for underground facilities/utilities. Electronic records of marking information may be logged/stored in local memory of a marking device, formatted in various manners, processed and/or analyzed at the marking device itself, and/or transmitted in whole or in part to another device (e.g., a remote computer/server) for storage, processing and/or analysis. In one example, an output stream of data packets is provided, wherein each data packet includes one or more flag fields that is/are set or reset upon at least one actuation of the marking device.
US09542860B2	Spinal injection trainer and methods therefor For use in training needle techniques such as spinal anesthesia and or lumbar epidural steroid injections, a spinal model includes a complete natural bone vertebral column that is embedded in a matrix of crystal clear ballistic gel. The synthetic gel does not harbor bacteria, can be reused and does not require refrigeration. Natural bone offers significantly better image contrast over radiopaque replicas. A transparent synthetic gel matrix permits observation of needle progression by both the trainee and the trainer and provides unique opportunities for coaching and intercession to prevent poor needle placement prior to its occurrence.
US09542855B2	Method of driving a main rotor of a rotorcraft in the context of simulating a failure of one of the engines of the rotorcraft A method of driving a main rotor of a rotorcraft in rotation while implementing an in-flight simulation mode that simulates failure of one of the engines of the rotorcraft. In simulation mode, and when a current speed of rotation (NR) of the main rotor is detected as being lower than a predetermined threshold speed of rotation (S), the simulation mode is kept active and a regulation command is generated in order to perform a controlled operation (A) of gradually increasing the power delivered by the engines by authorizing the limit imposed by a setpoint (OEI/2) for regulating operation of the engine in simulation mode to be exceeded. Said gradually increasing power is interrupted by the pilot staying under training and operating a collective pitch maneuver of the blade of the main rotor providing a rotation of main rotor at the predetermined threshold speed in rotation.
US09542853B1	Instruction based on competency assessment and prediction An intelligent tutoring system can be implemented using filters, predictive modeling, and a knowledge warehouse, which allows content to be dynamically selected for individualized presentation to a learner. Such an intelligent tutoring system can be implemented using a variety of techniques, including polynomial vector equations in modeling, extensible markup language storage formats for presentation data, and a knowledge warehouse with information stored in data cubes.
US09542851B1	Avionics flight management recommender system A flight management system is modified so that it can deal with an unpredicted current event happening to an airplane based on non-standard maneuvers that have been carried out previously by other airplanes in similar circumstances. This allows the flight management system to adaptively or dynamically respond to a variety of flight path changes rather than rely solely on a set of fixed responses to predictable events during a flight. Specifically, the flight management system is configured to provide procedural recommendations to a flight crew in real time based on collaboratively filtered historical data such that the flight crew can make smarter choices while operating airplanes.
US09542850B2	Secure communications with unmanned aerial vehicles A device receives a request for a flight path for a UAV to travel from a first location to a second location, and determines, based on credentials of the UAV, whether the UAV is authenticated for utilizing the device. The device determines, when the UAV is authenticated, capability information for the UAV based on component information of the UAV, and calculates the flight path. The device determines whether the UAV is capable of traversing the flight path based on the capability information, and generates, when the UAV is capable of traversing the flight path, flight path instructions for the flight path. The device provides the flight path instructions and credentials of the device to the UAV to permit the UAV to travel from the first location to the second location when the UAV authenticates the device based on the credentials of the device.
US09542846B2	Redundant lane sensing systems for fault-tolerant vehicular lateral controller A vehicle lateral control system includes a lane marker module configured to determine a heading and displacement of a vehicle in response to images received from a secondary sensing device, a lane information fusion module configured to generate vehicle and lane information in response to data received from heterogeneous vehicle sensors and a lane controller configured to generate a collision free vehicle path in response to the vehicle and lane information from the lane information fusion module and an object map.
US09542842B2	Device and method for detecting wetness on a roadway A detection device is provided for a motor vehicle (10) for detecting wetness (18) on a roadway (20). The detection device has a moisture-detection unit (12) and an evaluation unit (40) designed to determine wetness (18) on the roadway (20) on the basis of a moisture value (42) detected by the moisture-detection unit (12). The moisture-detection unit (12) is embodied as a sensor unit and is arranged at a rear region of the motor vehicle (10).
US09542841B2	Apparatus and method employing sensor-based luminaires to detect areas of reduced visibility and their direction of movement A method and system that relies on visibility detectors deployed on luminaires in outdoor lighting networks (OLNs) to independently treat and consolidate the sensed data in a fault-tolerant manner. By communicating with neighboring luminaires and/or with a centralized server, the invention is able to identify the position and direction of movement of areas of reduced visibility (e.g. fog). This information can then be used to alert drivers who are approaching the identified area.
US09542838B2	Electronic apparatus, control method thereof, remote control apparatus, and control method thereof An electronic apparatus, control method thereof, remote control apparatus that controls the electronic apparatus, and control method thereof. The remote control apparatus includes a communication unit which communicates with the electronic apparatus; a user input unit which receives a user button selection indicating an input button; a sensing unit which senses movement of the remote control apparatus; and a control unit which controls the communication unit to transmit information about the user button selection to perform a function corresponding to the input button if the remote control apparatus is in a button input mode, and to transmit information about the movement of the remote control apparatus to the electronic apparatus to control the electronic apparatus by the movement if the remote control apparatus is in a motion recognition mode. Accordingly, controlling a game or a multimedia content is easier, and the user is provided with a new and interesting experience.
US09542837B2	Ulifecare management service method and device using adaptive control protocol for USN interface A control method of a gateway communicating with at least one sensor and a service server is provided. The control method may include receiving, from the at least one sensor, first information comprising at least one of bioinformation, disaster prevention information, and public information, transmitting the first information to the service server when the first information meets a first standard, or processing the first information in a data format of the first standard and transmitting the processed first information to the service server when the first information does not meet the first standard, receiving, from the service server, a control command to control the at least one sensor, and transmitting the control command to a sensor corresponding to the control command.
US09542826B2	Devices, systems and methods for locating and interacting with medicament delivery systems In some embodiments, a method includes establishing a communications link between a computing device and an adapter. The adapter is configured to receive at least a portion of a medicament delivery device. A wireless signal is received to maintain the communications link. A relative position between the computing device and the adapter is determined. An alarm is produced when the wireless signal is not received within a time period. The alarm is based on the relative position between the computing device and the adapter.
US09542825B2	Detection system for cold chain transportation device A cold chain transportation device includes a body, a cover, and a detection system. The cover is coupled to the body. The detection system includes a control unit, a temperature sensor, and a detection unit. The temperature sensor senses a temperature of the cold chain transportation device. The detection unit detects opened/closed states of cover. The control unit determines motion states and working states of the cold chain transportation device and transmits the temperature, the opened/closed states, the motion states, and the working states of the cold chain transportation device to an electronic terminal.
US09542824B2	Methods and apparatus to detect and warn proximate entities of interest Systems and methods to detect and warn proximate entities of interest are described herein. An example detection system includes a light source attachable to a forktruck, where the light source projects an illuminated warning field on a floor on which the forktruck is to traverse. The light source projects the illuminated warning field at a distance from a front end of the forktruck. The light source is separate from a headlight of the forktruck.
US09542823B1	Tag-based product monitoring and evaluation Aspects of tag-based product monitoring and evaluation are described. In one embodiment, an arrangement includes a product package and one or more tags with the product package. At least one of the tags may include a memory that stores a unique identifier, product detail data, and product usage data for the product, a continuity trace that extends across an access covering of the product package, a radio frequency front end configured to be excited by an electromagnetic field, and a tag processor configured to detect a continuity of the continuity trace and identify whether the product package has been opened based on the continuity. When excited in the presence of the electromagnetic field, the tag is configured to transmit a continuity status indicator regarding whether the product package has been opened. In this case, a purchaser may be alerted as to whether the product package has been opened before purchasing.
US09542819B2	Home appliance and controlling method thereof A home appliance includes a tactile signal generator and a controller. The tactile signal generator has a first function which allows the home appliance to perform a predetermined function and a second function to generate a tactile signal. The controller determines whether an event is generated and controls the generation of the tactile signal generated by the tactile signal generator upon determination that the event is generated.
US09542817B2	Personal safety and security light A personal safety and security light used to deter aggressors, visually and audibly alert people within proximity, and illuminate surrounding areas. The personal safety and security light includes a casing, a plurality of lights, a microcontroller, a sound emitting device, a power supply and a trigger. The plurality of lights is externally mounted on the casing to illuminate the surround area from the casing. The sound emitting device audibly alerts nearby people for help or intervention. The microcontroller conducts power from the power supply to the plurality of lights and the sound emitting device when the trigger completes the circuit. The microcontroller controls the duration, intensity and sequence pattern for the plurality of lights and the sound emitting device. The trigger toggles the circuit open or closed to actuate the microcontroller that begins the sequence for the plurality of lights and the sound emitting device.
US09542812B2	Wagering game leaderboards Leaderboards that aggregate data from across different wagering games (e.g., online wagering games and casino based wagering games) can create a game independent spirit of competition and recognition. Wagering game data of a plurality of players across different wagering games can be aggregated together. The plurality of players are ranked based, at least in part, on the wagering game data aggregated across the different wagering games. A leaderboard is updated based, at least in part, on the ranking of the plurality of players.
US09542808B2	Electronic game and method for playing a game based upon removal and replacing symbols in the game matrix Payout methods in a mechanical, an electromechanical and/or computer-based slot machine-like games-of-chance enable a series of awards based upon: appearance of predetermined symbol combinations in the symbol matrix; issuance of awards for the predetermined combination of symbols; removal of the winning symbol combinations from the symbol matrix; replacement of removed symbols with other symbols; issuance of awards for predetermined combination of symbols in the symbol matrix; and recurring cycles of award, removal and replacement until no winning symbol combinations appear in the symbol matrix.
US09542806B2	Methods and systems for electronic gaming An electronic gaming machine and a computer implemented method of administering game play, include displaying an electronic reel simulation including a multiple reel array for a wagering game on a display. A user input is accepted indicating a selected play option from a plurality of play options, wherein all play options of the plurality of play options enable all displayed positions of the multiple reel array to be considered in winning outcomes. A game outcome is determined and presented on the game display, the game outcome including game symbols for the displayed positions of the multiple reel array. Winning combinations of the game symbols are determined, where each winning combination includes three or more matching game symbols appearing in the displayed positions on each of three or more adjacent reels and at least one of the three or more matching game symbols is not used in another winning combination.
US09542803B2	Products and processes for gaming with points Methods of tracking points among participants in various wagers. An indication of a wager may be received, including point distributions, participants, an event, etc. An indication of an outcome of the wager may be received. Points may be allocated among participants in accordance with a desired point distribution based on the outcome of the wager. An indication of a point adjustment may be received, and points may be adjusted accordingly. The point adjustment may be associated with an external exchange between participants in a wager. Other embodiments are disclosed.
US09542800B2	Wagering game with concealed elements continuously revealed A method, apparatus, and computer readable storage medium for implementing a bonus round of a slot machine game. A plurality of concealed elements are displayed, and a player can reveal each element one by one, until a terminating symbol is revealed. Combinations are formed and a player is awarded a highest combination upon revealing a terminating symbol.
US09542799B2	Hybrid arcade-type, wager-based gaming techniques and predetermined RNG outcome batch retrieval techniques Various aspects described for implementing hybrid arcade/wager-based gaming techniques via computer networks, including one or more casino gaming networks. The hybrid arcade/wager-based game may include a non-wager based gaming portion and a wager-based gaming portion. One or more players are able to concurrently engage in continuous game play of the non-wager based gaming portion during execution of wager-based gaming events which are automatically triggered based on events which occur during play of the non-wager based gaming portion. Other aspects are directed to wager-based gaming techniques for remotely retrieving, before the occurrence of wager-based triggering events, one or more batches of predetermined RNG outcomes from an RNG engine, and for using at least one of the retrieved, predetermined RNG outcomes to determine future wager-based game event outcomes.
US09542798B2	Personal electronic device for gaming and bonus system Embodiments of the present invention are directed to communication methods in gaming networks using portable devices. In some networks portable devices communicate information about the status of particular gaming machines on the gaming network. In other networks portable devices are used as a secondary display for the gaming device. In yet other networks bonus games may be played on the portable devices. Further embodiments include a portable device that operates to match a current state of a game to a pre-defined state or states.
US09542794B2	Wagering game with multiple reels forming multiple symbol arrays A gaming system for playing a wagering game comprises at least one display adapted to display a plurality of reels having symbols. The symbols indicate a randomly selected outcome of the wagering game. The plurality of reels includes at least one single-symbol reel and at least one multi-symbol reel. The at least one display is adapted to display at least one payline overlapping at least one symbol from the at least one single-symbol reel and at least one symbol from the at least one multi-symbol reel.
US09542791B2	Self-checking cash box The invention relates to a cash box (10) having a receiving area (12) for receiving notes of value, an invalidating unit (14), a sensor unit (18) for detecting manipulation attempts and a control unit (16). In an activated operating state, the control unit (16) triggers the invalidating unit (14) when the sensor unit (18) detects a manipulation attempt. In a deactivated operating state, the control unit (16) does not trigger the invalidating unit (14) even in the presence of a manipulation attempt. Prior to the activation of the cash box (10), the control unit (16) checks the proper functioning of at least one sensor (20) of the sensor unit (18). In addition, the invention relates to a method for activating a cash box (10).
US09542788B2	Value document and method for checking the presence of the same The invention concerns a value document comprising particulate agglomerates respectively containing at least two different homogeneous phases, wherein the first homogeneous phase is based on a first non-luminescent substance detectable by a spectroscopic method and the second homogeneous phase is based on a second non-luminescent substance detectable by a spectroscopic method, and wherein upon an evaluation of measurement values that are obtainable by a location-specific measurement, carried out at different locations of the value document, of the first measurement-signal intensity caused by the first substance and underlying the spectroscopic method and the second measurement-signal intensity caused by the second substance and underlying the spectroscopic method, there is a statistical correlation between the first measurement-signal intensities and the second measurement-signal intensities.
US09542785B2	Mobile key devices systems and methods for programming and communicating with an electronic programmable key Systems, methods, and apparatuses for communicating information, altering access rights, and transferring power to and from an electronic programmable key are disclosed. A mobile key interface device is configured to couple to a contact pin of the electronic programmable key to establish a channel of communication. Using the channel of communication, the mobile key interface device may communicate information, alter access rights, and transfer power to and from the electronic programmable key. The mobile key interface device may also communicate with a mobile communication device. Using the mobile communication device's network connection, the mobile key interface device may further establish a channel of communication from a control center to the electronic programmable key.
US09542784B2	Pairable secure-access facilities Systems and methods are provided for providing access to secure-access facilities based on pairing of the secure-access facilities with a user device such as a wearable device. A pairable secure-access facility may be a public storage facility or device such as a locker that includes communications circuitry for pairing with the user device. Once paired with the user device, the locker may operate a locking mechanism to lock the locker when the user device is away from the locker and to unlock the locker when the user device is in the vicinity of the locker. The locker may include a beacon for detecting and pairing with the user devices. Pairing the user device and the locker may include entering a locker identifier into the user device to ensure that the intended user device is paired with the intended locker.
US09542783B2	Method and apparatus for authenticating access to a multi-level secure environment of an electronic device An electronic system utilizes a method (500) for authenticating access to a multi-level secure environment. According embodiments, the system stores (501) fingerprint data for at least one authorized human user of the system. The fingerprint data for each authorized user includes copies of fingerprints for two or more fingers of the user. Some time after storing the fingerprint data, the system senses (503) one or more fingers of an individual who is attempting to use the system and compares (505) the sensed finger data to the stored fingerprint data. When at least some of the sensed finger data matches copies of fingerprints in the stored fingerprint data, the system determines (509) a quantity of matching fingerprints. The system then determines (525) a security level for the individual based on the quantity of matching fingerprints and provides access (527) to particular functionality of the system based on the determined security level.
US09542781B2	Vehicle system communicating with a wearable device to provide haptic feedback for driver notifications A system includes a user interface and a controller in communication with a transceiver and the user interface. The controller is configured to receive a predefined threshold and alert for a vehicle indication at the user interface. The controller is further configured to generate a notification based on the preconfigured alert in response to the vehicle indication exceeding the predefined threshold. The controller is further configured to transmit, via the transceiver, the notification for the vehicle indication to a wearable device configured to output the predefined alert.
US09542780B1	Lottery ticket dispenser with side-by-side engaging members Disclosed is a display and dispensing lottery ticket dispenser designed to be attached in a side-by-side relationship with a similar type dispenser. More particularly, this invention relates to a lottery ticket dispenser that has side engagement members for attaching two dispensers together.
US09542778B1	Systems and methods related to an interactive representative reality Disclosed herein are methods and apparatus related to the creation and maintenance of an interactive and explorable representative reality. The interactive representative reality may be compiled from a plurality of geotagged media from a plurality of individual sources. Similarly geotagged images of the geotagged media may be stitched together to form portions of the representative reality. Portions of the representative reality may be layerable spatially and/or temporally. The apparatus and methods disclosed herein provide for recognition of objects within the geotagged images and link the images to one or more related items.
US09542776B2	Generating random sampling distributions using stochastic rasterization Stochastic rasterization may be used as a flexible volumetric sampling mechanism. By bounding and tessellating the sampling domain, uniform sampling distributions over an arbitrary domain can be efficiently generated in up to five dimensions. Sample placement allows pseudo-random, stratified random, or blue noise sampling. Random sampling with an adaptive density function may be achieved by adding one dimension.
US09542770B1	Automatic method for photo texturing geolocated 3D models from geolocated imagery A method and system for applying photo texture to geolocated 3D models operates within a 3D modeling system. The modeling system includes a modeling application operating on a workstation and a database of geotagged imagery. A 3D model created or edited within the 3D modeling system is geolocated such that every point in the 3D modeling space corresponds to a real world location. For a selected surface, the method and system search the database of imagery to identify in the database one or more images depicting the selected surface of the 3D model. The method and system identify the boundaries of the selected surface within the image by transforming two or more sets of coordinates from the 3D modeling space to a coordinate space corresponding to the image. The portion of the image corresponding to the selected surface is copied and mapped to the selected surface of the 3D model.
US09542768B2	Apparatus, method, and program for processing 3D microparticle data An information processing apparatus for 3D microparticle data analysis is provided. The information processing apparatus includes a data storage unit configured to store measurement data of microparticles; a data processing unit configured to create a 3D image in a coordinate space with three types of variables from the measurement data, the 3D image represents a characteristic distribution of the microparticles; and a display unit configured to display the 3D image, wherein in a case that a gating region is set in the 3D image, the 3D image is rotated or scaled up or down along with the gating region on the display unit. An information processing method and program for 3D microparticle data analysis are also provided.
US09542762B2	X-ray CT apparatus and image reconstruction method To provide an X-ray CT apparatus and an image reconstruction method that can generate an image in which motion influence of a site to be scanned is reduced, the image processing device 403 of the X-ray CT apparatus 1 calculates a reconstruction data range which is a range of projection data to be used for reconstruction based on a motion direction of the site to be scanned. An image is reconstructed using the projection data in the calculated reconstruction data range. The reconstruction data range is set as the projection data in a projection range of at least 180 degrees or more including a projection direction that approximately corresponding to the motion direction of the site to be scanned.
US09542761B2	Generalized approximate message passing algorithms for sparse magnetic resonance imaging reconstruction A method for reconstructing magnetic resonance imaging data includes acquiring a measurement dataset using a magnetic resonance imaging device and determining an estimated image dataset based on the measurement dataset. An iterative reconstruction process is performed to refine the estimated image dataset. Each iteration of the iterative reconstruction process comprises: updating the measurement dataset and a sparse coefficient dataset based on the estimated image dataset and a plurality of belief propagation terms, incorporating a noise prior dataset into the measurement dataset, incorporating a sparsity prior dataset into the sparse coefficient dataset, updating the plurality of belief propagation terms based on the measurement dataset and the sparsity prior dataset, and updating the estimated image dataset based on the plurality of belief propagation terms. A reconstructed image and confidence map are generated using the estimated image dataset.
US09542758B2	Image processing apparatus and light source identification method An image processing apparatus is provided including a storage unit for storing relationships of color coordinates between a plurality of reference colors under each of a plurality of different light sources for each light source, with respect to the plurality of reference colors set in a color space and being different from one another; and a calculation unit for detecting color coordinates of the plurality of reference colors from an object image to be processed, and identifying a light source used in capturing of the object image according to a similarity between relationships of the detected color coordinates and the relationships of color coordinates stored in the storage unit for each light source.
US09542755B2	Image processor and image processing method An image acquisition section of an information processor acquires stereo images from an imaging device. An input information acquisition section acquires an instruction input from a user. A depth image acquisition portion of a position information generation section generates a depth image representing a position distribution of subjects existing in the field of view of the imaging device in the depth direction using stereo images. A matching portion adjusts the size of a reference template image in accordance with the position of each of the subjects in the depth direction represented by the depth image first, then performs template matching on the depth image, thus identifying the position of a target having a given shape and size in the three-dimensional space. An output information generation section generates output information by performing necessary processes based on the target position.
US09542752B2	Document image compression method and its application in document authentication A method for compressing a bi-level document image containing text is disclosed. The document image is segmented into symbol images each representing a letter, numeral, etc. in the document. The symbol images are classified into a plurality of classes, each class being associated with a template image and a class index. Classification is done by comparing each symbol to be classified with template of existing classes, using a number of image features including zoning profiles, side profiles, topology statistics, and low-order image moments. These image features are compared using a tolerance based method to determine whether the symbol matches the template. After classification, certain classes that have few symbols classified into them may be merged with other classes. In addition, the template images of the classes are down-sampled, where the final sizes of the template images are dependent on the likelihood of confusion of the template with other templates.
US09542749B2	Fast general multipath correction in time-of-flight imaging Fast general multipath correction in time of flight imaging is described, for example, to obtain accurate depth maps at frame rate from a time of flight camera. In various embodiments accurate depth maps are calculated by looking up corrected depth values stored in a look up table. In various embodiments the corrected depth values are highly accurate as they take into account three or more possible light ray paths between the camera and a surface in a scene being imaged. In an example accurate depth maps are computed at a frame rate of a time of flight camera. In an example accurate depth maps are computed in less than 30 milliseconds for an image having over 200,000 pixels using a standard CPU.
US09542748B2	Front-end architecture for image processing Systems and methods for image processing may perform one or more operations including, but not limited to: receiving raw image data from at least one imaging device; computing at least one image depth distance from the raw image data; computing one or more image validity flags from the raw image data; generating at least one data validity mask from the one or more image validity flags; determining a background imagery estimation from at least one image depth distance; generating at least one foreground mask from the background imagery estimation and the at least one image depth distance; generating at least one region-of-interest mask from the data validity mask and the foreground mask; and generating filtered raw image data from the raw image data and at least one region of interest mask.
US09542745B2	Apparatus and method for estimating orientation of camera An orientation estimation apparatus estimates a position and an orientation of an image capturing unit based on positions of a marker on the image and in the real space when the maker is detected; and based on positions of feature points on the captured image and in the real space, and initial values of the position and the orientation of the unit when the maker is not detected. Further, the apparatus calculates a failure index from a first image acquired while the position and the orientation are estimated by the position of marker, where the failure index indicates a possibility that the detection of the marker is failed. When the failure index satisfies a shift-preparation-start reference, the initial values are set from the position and the orientation estimated by the position of the marker on the image having been acquired in a predetermined period before the first image.
US09542744B2	Medical image display apparatus and medical image display method To retrieve a desired image from plural types of successive images arranged based on various physical quantities, a cuboid object that is an assembly of multiple unit cells is displayed on a display device, a successive image group is arranged according to the physical quantities of the three axes of the cuboid object that are respectively the body-axis direction position, the first time phase intervals, and the second time phase intervals narrower than the first time phase intervals, and the respective images included in the successive image group and the respective unit cells are associated on one-to-one basis and stored in a main memory. When a three-dimensional position in the cuboid object is input by a mouse operation etc., the CPU retrieves one or multiple images associated with one or multiple unit cells determined according to the input three-dimensional position from the main memory and displays the images in an image display region.
US09542741B2	Method and system for automatic pelvis unfolding from 3D computed tomography images A method and system for automatic pelvis unfolding from 3D computed tomography (CT) images is disclosed. A 3D medical image, such as a 3D CT image, is received. Pelvis anatomy is segmented in the 3D medical image. The 3D medical image is reformatted to visualize an unfolded pelvis based on the segmented pelvis anatomy.
US09542739B1	Virtual turbomachine blade contact gap inspection A system and method for virtually inspecting contact gaps of a blade stage of a turbomachine is disclosed. The system may include a digitizing device for obtaining a three-dimensional model of a shroud of each blade of the blade stage. A computer system may include at least one module configured to perform the following steps: extracting a geometric location data of a hard place plane of each shroud from the three-dimensional model; generating a three-dimensional virtual rendering of the shrouds of the blade stage based on the geometric location data and the known dimensions of the blade stage, the three-dimensional virtual rendering including a rendering of contact gaps between adjacent shrouds; and inspecting the blade stage using the three-dimensional virtual rendering.
US09542737B2	Image inspecting apparatus and image inspecting program Image inspecting apparatus compares first image data created as data representing a reference-image acting as an inspecting reference with second image data created as data representing an inspection-image acting as a target to automatically extract a difference point between first and second image data, and includes a storage means for the reference- and inspection-image, an image processing means for establishing correspondences between part of stored reference-image as first image data with part of stored target image as second image data at a pixel level to perform an image matching processing of them, a difference detecting means for comparing image-matched first and second image data to detect a difference between first and second image data, image producing means for comparing difference with a plurality of threshold values to produce error representing image data at each threshold value, and inspecting process using produced error representing image data at each threshold value.
US09542736B2	Evaluating image sharpness A system may be configured to calculate and use image sharpness results. In some example embodiments, a content-aware image sharpness evaluation scheme is implemented by the system to calculate the degree of sharpness or blur of photographs taken of objects of interest. In certain example embodiments, a calculated sharpness score from the image sharpness evaluation scheme is converted into a score that is meaningful relative to other photographs of the same category as the object depicted in the photograph. In various example embodiments, a mobile-based assistant is configured to provide instant (or near instant) feedback to users uploading photographs using a mobile device. In alternative example embodiments, a web-based assistant is configured to provide instant (or near instant) feedback to users uploading one or more photographs simultaneously to an electronic commerce or marketplace website.
US09542732B2	Efficient image transformation The present disclosure provides a multi-stage image mapping mechanism for mapping a distorted image to a rectified image. For example, the multi-stage image mapping mechanism can remove homography from a distorted image to reconstruct a rectified image in two-stages: (1) a first stage in which distortion is partially removed from a distorted image to generate an intermediate image, and (2) a second stage in which residual distortion is removed from the intermediate image to recover the rectified image.
US09542730B2	Image processing device, image processing method, and image processing program Image processing is performed in view of the difference between the chroma component and the brightness component in an image, with a relatively smaller amount of data processed during the image processing. A frequency decomposing unit 110 performs frequency decomposition directly on Bayer image signals from an imaging element 3. With this, a high frequency component representing color information and a low frequency component representing brightness information are obtained. A filter coefficient obtaining unit 131 of a correction processing unit 130 obtains filter coefficients and the filter coefficients for the high frequency component are different from those for the low frequency component. A filtering processing unit performs a filtering process on subimages based on the filter coefficients obtained by the filter coefficient obtaining unit 131 in such a manner that processing details of the filtering process for the high frequency component are different from those for the low frequency component.
US09542727B2	Reproducing device, setting changing method, and setting changing device A method, an apparatus, and a non-transitory computer-readable medium for display control. The display control apparatus comprises a circuitry configured to determine whether a hold condition is satisfied, determine an attitude of the display control apparatus, change a display state from a first state displaying a first screen to a second state in response to the display control apparatus not being operated in a predetermined period, and responsive to an operation, return the display state to the first state-displaying the first screen in an orientation based on the attitude of the display control apparatus in response to the hold condition not being satisfied. The non-transitory computer-readable medium comprises instructions to configure the apparatus to perform the display control method.
US09542726B2	Mobile terminal, display device and controlling method thereof A display device, a mobile terminal, and a method for displaying a second screen image are discussed. The display device according to one embodiment includes an interface unit configured to be connected to a mobile terminal having a first display unit displaying a first screen image in a first display direction; a second display unit; and a controller configured to receive information related to the first screen image, and display a monitor window for displaying a second screen image corresponding to the first screen image on the second display unit. The second screen image is displayed in the first display direction. The controller is further configured to receive a user command to intend the monitor window to be oriented in a second display direction and control the monitor window to be oriented in the second display direction according to the user command, and transmit a control signal.
US09542725B2	Image processing device, image processing method and medium An image processing device according to the present invention includes: a weight calculation unit that determines an area where a feature value of an input image is saved, based on a gradient of a feature value of a pixel of the input image and a direction of the gradient, and calculates a weight for reducing a regularization constraint that is a constraint based on regularization of image processing in the area where the feature value is saved; a regularization term calculation unit that calculates a regularization constraint of a high resolution image restored based on the input image by using the weight; a reconstruction constraint calculation unit that calculates a reconstruction constraint that is a constraint based on reconstruction of the high resolution image; and an image restoring unit that restores the high resolution image from the input image based on the regularization constraint and the reconstruction constraint.
US09542720B2	Terminal device, image display method, and storage medium Captured or input image data is converted into an image of a size of a specific number of pixels. Then, predetermined plural types of different effects are applied to image data obtained through the conversion. Several types of image data items with the applied effects are arranged and simultaneously displayed.
US09542717B2	Display device and information collecting method using the same A display device is provided. The device includes memories, a display unit, and a data collecting memory. The memories store a plurality of kinds of image data generated based on information acquired from different kinds of sensors, respectively. The display unit displays the image data that is selected by a user among the plurality of kinds of image data. The data collecting memory stores, in response to a predetermined report instruction, at least data of an image displayed on the display unit at the timing of the report instruction and, among the image data stored in the memories at the timing of the report instruction, the image data that is not displayed on the display unit.
US09542715B2	Memory space mapping techniques for server based graphics processing The server based graphics processing techniques, describer herein, include loading a given instance of a guest shim layer and loading a given instance of a guest display device interface that calls back into the given instance of the guest shim layer, in response to loading the given instance of the guest shim layer, wherein the guest shim layer and the guest display device interface are executing under control of a virtual machine guest operating system. The given instance of the shim layer requests a communication channel between the given instance of the guest shim layer and a host-guest communication manager (D3D HGCM) service module from a host-guest communication manager (HGCM). In response to the request for the communication channel loading, the D3D HGCM service module is loaded and a communication channel between the given instance of the shim layer and the D3D HGCM service module is created by the HGCM. The given instance of the shim layer maps the graphics buffer memory space of a host D3D DDI binary executing under control of a host operating system. Thereafter, function calls are sent from the given instance of the guest shim layer through the communication channel to the D3D HGCM service module utilizing the graphics buffer memory space mapping.
US09542714B2	Concealing data within images A method and apparatus for concealing data. Frequency information is identified for a number of data object types of a set of data objects in the data using a frequency map. A set of pixel values is assigned to the set of data objects based on the frequency information for use in encrypting the set of data objects to form encrypted data. An image is generated that includes a set of pixels that represents the encrypted data. Each pixel in the set of pixels has a pixel value from the set of pixel values that is assigned to a corresponding data object of the set of data objects.
US09542713B2	Systems and methods for securing the manufacturing supply chain Securing the manufacturing supply chain with digital certificates. A token is coupled to a manufacturing station and enabled via a personal identification number. The token includes a counter limiting the maximum number of certificates to be signed, and compares a serial number of a digital certificate to a tracked serial number. In some embodiments, the token is linked to a particular manufacturing station once the token is enabled.
US09542711B2	Computer implemented methods and apparatus for providing selective notifications in an online social network Disclosed are various implementations of different methods, apparatus, systems, and computer-readable storage media for providing selective notifications in an online social network. In some implementations, an information update is capable of being stored in a database and capable of being included in an information feed displayed on a display device. One or more notification options is provided in association with the information update. A selection of the one or more notification options can be received. The selected one or more notification options can define one or more conditions for sending a network communication indicating data received in association with the information update. The one or more notification options is stored on a storage medium.
US09542706B2	Footwear products including data transmission capabilities Footwear systems include an article of footwear and a data transmission system engaged with the article of footwear. The transmission system transmits data to a remote system, such as a display system, another data transmission system, a processing system, etc. Such footwear systems further may include activation systems for activating the transmission and/or display systems. The transmitted data may be used for various purposes, such as: (a) identifying a user of the article of footwear; (b) activating targeted advertising or product information; (c) confirming the user's presence at a specific location and/or at a specific time; (d) determining start, finish, and/or intermediate split times for specific user; (e) confirming athletic equipment usage; (f) providing data for a game or reward program; (g) registering the user for an event or competition; or the like.
US09542701B2	Providing commercial enterprise data with map data Disclosed are methods and systems for downloading map data. A database of layers of map data is maintained. The map data may be representative of at least one map image of a geographic area. Each layer may provide progressively more detailed display information. Map data is downloaded to a client computer, and the may data may be sufficient to allow a user to navigate within a geographic area without requiring new map data to be downloaded.
US09542699B2	Order management system with technical decoupling An order management system is provided. The order management system receives a provisioning order, where the provisioning order includes at least one order line, and where the at least one order line of the provisioning order references a product specification. The order management system transforms the provisioning order into a service order, where the service order includes at least one order line, and where at least one order line of the service order references a customer-facing service specification. The order management system transforms the service order into a technical order, where the technical order includes at least one order line, and where at least one order line of the service order references one of: a resource-facing service specification; or a resource. Thus, the order management system can define a customer-facing service that is not coupled to a technical implementation, nor coupled to a product offering.
US09542694B2	Determining influence in a social networking system An influence metric describing the influence of a social networking system object on social networking system users is determined based on affinities between the users and the object. For example, affinities between the associated users and the object are combined to determine the influence metric. Content may be selected for presentation to users based in part on influence metrics of the content. Additionally, influence metrics of objects associated with a user may be combined to determine the relevance of objects associated with the user, which may also be used to select content for presentation to the user.
US09542691B1	System and method for securely managing delivery and redemption of location-based incentives and customer loyalty rewards to mobile devices A plurality of credentials is retrieved for a user by a computing device, wherein each of the plurality of credentials is associated with a loyalty program. For each loyalty program, itinerary data is retrieved from a server associated with the loyalty program using the credentials associated with the loyalty program from the plurality of credentials. The retrieved itinerary data retrieved for each of the loyalty programs is aggregated into an itinerary. The itinerary is presented to the user at the computing device. Loyalty points may be awarded to a user based on interaction with an application running on the computing device where the loyalty points may be redeemed for goods and services. Advertisers may be provided compensated based on the redemption of the loyalty point by users at their physical or virtual stores.
US09542688B2	Method and system for targeting small businesses A method for identifying business service recommendations includes: storing merchant profiles, each profile including data related to a merchant including a merchant identifier and transaction for a plurality of payment transactions; receiving, a data file including a plurality of merchant entries, each entry including data related to a merchant including a merchant identifier and firmographics; identifying a specific merchant entry where the merchant identifier corresponds to a merchant identifier in a specific merchant profile; calculating transaction scores for the specific merchant entry based on the transaction data in the specific merchant profile; identifying a related merchant entry where the firmographics correspond to the firmographics in the specific merchant entry and where the merchant identifier is not included in a merchant profile; and identifying one or more business service recommendations for the merchant related to the related merchant entry based on transaction scores and firmographics in the related merchant entry.
US09542685B2	Wearable device made with silicone rubber and electronic components A wearable device includes a wearable device structure at least partially made of a silicone rubber. A support member is at least partially positioned in the wearable device structure. ID circuitry is at least partially positioned and coupled to the support. One or more batteries coupled to the ID circuitry.
US09542677B1	Receipt generation service A method includes receiving, by a server via a network, transaction information descriptive of a money transfer transaction initiated at a point of entry device. The transaction information includes information that identifies a location of the point of entry device. The method includes determining, by the server, receipt information to be included in a receipt for the money transfer transaction. The receipt information may be determined based, at least in part, on the transaction information, and at least a portion of the receipt information included in the receipt satisfies regulatory requirements associated with the location of the point of entry device. The method includes generating, by the server, the receipt that includes the receipt information, and transmitting the receipt from the server to the point of entry device via the network.
US09542676B2	Host device, printing system, and data processing method Text data is acquired from print request data, print content is expressed as raster data and print data is generated using a printer command based on the print request data, the acquired text data is added to the print data using the command, and the print data is sent with the text data to the printer.
US09542674B2	System for an automated dispensing and retrieval kiosk for recorded media A system for an automated dispensing and retrieval kiosk for recorded media includes a kiosk having a plurality of vertical racks arranged in a circular formation, each vertical rack configured for storing a plurality of recorded media. A customer interface allows a customer to select or return a recorded media. A robotic element delivers the selected recorded media from the vertical racks to a media output, at the customer interface. The element also delivers a returned recorded media from a media input at the customer interface to the vertical racks. A computer controls operation of the kiosk, and an internet interface connects the kiosk to the Internet. The kiosk may communicate with a central server and/or other kiosks of a group, to locate a requested recorded media within a kiosk of the group. Once located within the group, the requested media may be reserved for customer pick-up.
US09542673B2	Methods and systems for prepaid mobile payment staging accounts Prepaid staging account systems and methods are described that allow issuer financial institutions to quickly and efficiently launch NFC device payment programs. In an embodiment, a staging account provider computer receives a request to provision a mobile account. The staging account provider computer generates a mobile account PAN and associates it with a funding account PAN, and transmits a personalization request to personalize a payment application for the cardholder's mobile device to a trusted service manager (TSM) computer. The staging account provider computer receives a status confirmation message from the TSM computer indicating that the payment application has been personalized and loaded onto the cardholder's mobile device, and then transmits a mobile account initialization message that includes the mobile account PAN to the primary issuer.
US09542672B2	Systems and methods for providing manufacturer-based financial service accounts The disclosed embodiments include a mobile client device for providing real-time manufacturer-based financing. In one embodiment, the mobile device is configured to receive a product code associated with a manufacturer product offered for sale at a merchant location. The mobile device may further provide the product code to a financial service provider system configured to create a manufacturer-based financial service account associated with the product manufacturer. Further, the mobile device may provide, to the financial service provider system, information associated with a received account application, where the financial service provider system may create the manufacturer-based financial service account based on the received information and the product code. The mobile device may also receive a purchase code for purchasing the product using the manufacturer-based financial service account, provide it at the merchant POS location, and receive a confirmation of product purchase.
US09542671B2	Method and system to facilitate securely processing a payment for an online transaction A computer-implemented method, to facilitate processing a payment for an online transaction, includes, responsive to receiving secure transaction data from a merchant server, using a payment processor to generate a transaction data identifier to identify the transaction data. The payment processor communicates the transaction data identifier to the merchant server. In response to receiving a request to process a payment, including the transaction data identifier, the payment processor requests user credentials from a user. Upon receiving user credentials from the user, the payment processor verifies the user credentials. The payment processor processes the payment and generates a payment identifier to identify payment data associated with the payment. The payment processor communicates the payment identifier to the merchant server. Upon receiving a request for payment data, including the payment identifier, over a secure communication channel from the merchant server, the payment processor communicates the payment data to the merchant server.
US09542667B2	Navigating messages within a thread A user may easily read, browse, and jump through the messages contained within a thread. Different portions of the message may be highlighted such that they are easily identifiable. The user may easily navigate through the thread by selecting a user interface element, such as an arrow button, to move to the next or previous message within the thread. The order of the thread may also be reversed such that the user may view the thread from the first message to the last message, or view the thread from the last message to the first message. The messages within the thread may be marked, such as by using XML tags, in order to facilitate the identification of the sections of the messages within the thread.
US09542665B2	Methods for creating, arranging, and leveraging an ad-hoc collection of heterogeneous organization components Methods for creating, arranging, and leveraging an ad-hoc collection of heterogeneous organization components are provided. In one example, a method includes the steps of displaying a scratchpad affordance associated with a scratchpad, and detecting an update to the scratchpad based on an input associated with a first organization component of the one or more organization components and the scratchpad affordance. The method includes the additional step of updating the scratchpad based at least in part on the input.
US09542662B2	Lineage information for streaming event data and event lineage graph structures for visualization Implementations of the present disclosure include methods for providing transparency in streaming event data. In some implementations, methods include receiving a plurality of events, each event comprising event data and being generated by an event source in response to a real-world activity, processing the plurality of events using one or more complex event processing (CEP) rules to generate a complex event, in response to generating the complex event, generating at least one lineage event that comprises lineage information, the lineage information comprising information corresponding to one or more source events, each of the one or more source events contributing to the complex event, and storing the lineage event and the one or more source events in an event archive provided as a computer-readable storage medium.
US09542656B2	Supporting ETL processing in BPEL-based processes Methods and apparatus, including computer program products, implementing and using techniques for integrating and data activities in a process flow. A data transformation activity is invoked through local or remote invocation. The data transformation activity is part of a process flow defined in a standard business process execution language format and is invoked from within the process flow. A system for executing a process flow including one or more control activities and one or more data transformation activities is also described. The system includes a process control engine for executing activities included in the process flow, a data transformation subsystem for storing domain specific definitions of data transformation processes of data in one or more databases, and a control data repository for storing domain specific activity information related to the process flow.
US09542655B1	Generating streaming analytics applications using a glossary Examples of techniques for generating streaming analytics applications are described herein. An example computer-implemented method includes receiving, via a processor, subject matter requirements in a semi-structured format. The method includes classifying, via the processor, the subject matter requirements based on a predefined taxonomy. The method includes extracting, via the processor, a list of entities from the subject matter requirements based on grammar. The method includes generating a solution based on a glossary and the list of extracted entities. The method includes generating, via the processor, a streaming analytics application based on the solution.
US09542654B2	Overlapping trace norms for multi-view learning In multi-view learning, optimized prediction matrices are determined for V≧2 views of n objects, and a prediction of a view of an object is generated based on the optimized prediction matrix for that view. An objective is optimized, wherein is a set of parameters including at least the V prediction matrices and a concatenated matrix comprising a concatenation of the prediction matrices, and comprises a sum including at least a loss function for each view, a trace norm of the prediction matrix for each view, and a trace norm of the concatenated matrix. may further include a sparse matrix for each view, with further including an element-wise norm of the sparse matrix for each view. may further include regularization parameters scaling the trace norms of the prediction matrices and the trace norm of the concatenated matrix.
US09542649B2	Content based recommendation system A media control system enables a device-agnostic and source-agnostic entertainment experience through use of an internet-enabled user device. The user device includes a client application for navigating through media or entertainment content, controlling media devices according to a type of media content selected by the user, and sharing media experiences via social networks. The user device includes smartphones, tablet computers, and other internet-enabled processor-based devices. The media control system leverages the internet access of the user device to enable search and discovery of all available media content. A recommendation engine coupled to the client application learns media preferences from user behavior, generates from numerous disparate media sources recommended media choices corresponding to the media preferences, and presents the recommended media choices on the user device.
US09542638B2	RFID tag and micro chip integration design An integrated micro chip, method of integrating a micro chip, and micro chip integration system are described. In an embodiment, a micro chip such as a micro RFID chip or integrated passive device (IPD) is electrostatically transferred and bonded to a conductive pattern including a line break. In an embodiment, the line break is formed by a suitable cutting technique such as laser laser ablation, ion beam etching, or photolithography with chemical etching to accommodate the micro chip.
US09542636B2	RFID chip module A chip module comprises a carrier, having a first main surface and a second main surface opposite to the first main surface. A first recess structure is arranged in the carrier in the first main surface, and a chip is arranged in the first recess structure of the carrier. A patterned metallization layer is deposited on the second main surface of the carrier, the metallization layer having a first metallization structure and a second metallization structure, the first metallization structure being electrically isolated from the second metallization structure. The chip is electrically connected to the first metallization structure and the second metallization structure. The chip module comprises in particular an RFID chip and is suited to be connected to a textile substrate by way of laser reflow soldering.
US09542635B2	Foil composite card Composite cards formed in accordance with the invention include a security layer comprising a hologram or diffraction grating formed at, or in, the center, or core layer, of the card. The hologram may be formed by embossing a designated area of the core layer with a diffraction pattern and depositing a thin layer of metal on the embossed layer. Additional layers may be selectively and symmetrically attached to the top and bottom surfaces of the core layer. A laser may be used to remove selected portions of the metal formed on the embossed layer, at selected stages of forming the card, to impart a selected pattern or information to the holographic region. The cards may be “lasered” when the cards being processed are attached to, and part of, a large sheet of material, whereby the “lasering” of all the cards on the sheet can be done at the same time and relatively inexpensively. Alternatively, each card may be individually “lasered” to produce desired alpha numeric information, bar codes information or a graphic image, after the sheets are die-cut into cards.
US09542627B2	System and methods for generating quality, verified, and synthesized information An improved system and methods for identifying, assessing, obtaining, evaluating, processing and displaying information about specific topics of interest. In certain embodiments, information is processed with advanced computation and analytical techniques in which detailed statistical data is generated and refined to produce meaningful quantitative and qualitative information that may be useful in analyzing the economic performance of specific businesses or geographical regions of interest.
US09542626B2	Augmenting layer-based object detection with deep convolutional neural networks By way of example, the technology disclosed by this document receives image data; extracts a depth image and a color image from the image data; creates a mask image by segmenting the depth image; determines a first likelihood score from the depth image and the mask image using a layered classifier; determines a second likelihood score from the color image and the mask image using a deep convolutional neural network; and determines a class of at least a portion of the image data based on the first likelihood score and the second likelihood score. Further, the technology can pre-filter the mask image using the layered classifier and then use the pre-filtered mask image and the color image to calculate a second likelihood score using the deep convolutional neural network to speed up processing.
US09542625B2	Multi range object detection device and method The present disclosure discloses device and method for detecting objects placed at multiple ranges from vehicle. Images of the objects may be captured by an image capturing unit housed in the vehicle. The image may be splitted into plurality of sub-images. Further, one or more features may be extracted from the plurality of sub-images. Further, each of the plurality of sub-images may be simultaneously processed for computing gradients associated with the plurality of sub-images. Further, a cell histogram may be created by casting weighted vote for an orientation based histogram channel based on values associated with the gradient. The gradients computed may be normalized by grouping the cells in spatial blocks. Further, a Support vector Machine (SVM) linear classifier may be applied on the plurality of sub-images in order to classify the near object and the far object in a category of a pedestrian or a vehicle.
US09542620B1	Locating persons of interest based on license plate recognition information Possible locations of a person of interest are ranked based on LPR instances captured around physical locations and license plate numbers associated with the person of interest. An LPR instance includes an indication of a vehicle license plate number, a physical location, and a time when the LPR instance was captured by a LPR system. A possible location of the person of interest may be a location of an LPR instance that matches the license plate number or an address location associated with the person of interest. The ranking may be based on the number of LPR visits to each location, the number of license plate number matches at each location, or an attribute of a cluster of LPR instances. In some examples, an electronic message is rapidly communicated to an entity if a target license plate number is found at a highly ranked location.
US09542617B2	Image processing device and image processing method for correcting a pixel using a corrected pixel statistical value The present invention is directed to an image processing method, comprising: deriving a pixel statistical value of pixels and edge information for each of regions in a plurality of layers, the regions including attention pixels and having ranges that are successively narrower; correcting differential information between a pixel statistical value for a region in an attention layer and a pixel statistical value for a region in a layer wider than the region in the attention layer by using the edge information; correcting the pixel statistical value for the region in the attention layer by using the corrected differential information and the pixel statistical value for the region wider than the region in the attention layer; re-correcting the corrected pixel statistical value for the region in the attention layer by using a pixel statistical value for a region equal to or wider than a region in each of the layers and differential information between the uncorrected pixel statistical value for the region in the attention layer and the corrected pixel statistical value for the region in the attention layer; and correcting the attention pixel by repeating the correcting and the re-correcting the pixel statistical value for the region in the attention layer sequentially in the respective layers until the region is reduced from a maximum range to a minimum range.
US09542616B1	Determining user preferences for data visualizations A method for determining user preferences for data visualizations is provided. The method may include receiving data visualizations. The method may also include collecting the shapes, the line segments, and the colors associated with the data visualizations. The method may further include converting the shapes and the line segments to polygonal outlines. Additionally, the method may include categorizing and measuring the line segments. The method may further include identifying and categorizing the angles formed by the line segments and determining weighted values for the angles. The method may further include calculating the total length for the line segments, and the total weighted value for the angles. The method may also include characterizing the line segments based on the categorization of the line segments and the angles based on the categorization of the angles. The method may further include scoring the at least one data visualization based on the characterizations.
US09542615B2	Image processing apparatus and image processing method This invention provides an image processing apparatus including a unit which generates index image data, a unit which obtains a position of thumbnail image data in the index image data, a unit which divides the index image data so as to prevent overlap of the thumbnail image data, a unit which calculates a histogram of a luminance value of image data corresponding to each partial area including the thumbnail image data, a unit which determines image correction characteristics of each piece of image data based on the histogram and performing image correction, and a unit which reconfiguring the index image data using the corrected image data to output the reconfigured index image data.
US09542611B1	Logo detection for macroblock-based video processing The subject matter of this specification can be embodied in, among other things, a method that includes receiving a current frame, the current frame including one or more macroblocks, analyzing the current frame using a first set of image characteristics to determine if logo detection can be performed on the current frame, and performing the logo detection on the current frame if the current frame satisfies the first set of image characteristics to determine presence of a logo macroblock among the one or more macroblocks.
US09542610B1	Optical polling platform methods, apparatuses and media An image associated with a poll may be acquired via a camera. One or more symbols indicating responses may be found by analyzing the image. The responses specified by the symbols may be determined and saved. The responses may also be displayed to the operator and/or to the respondents.
US09542609B2	Automatic training of a parked vehicle detector for large deployment Methods and systems for training a parked vehicle detector. Video data regarding one or more parking sites can be captured. Positive training samples can then be collected from the video data based on a combination of one or more automated computing methods and human-input auxiliary information. Additionally, negative training samples can be collected from the video data based on automated image analyses with respect to the captured video data. The positive training samples and the negative training samples can then be used to train, re-train or update one or more parked vehicle detectors with respect to the parking site(s) for use in managing parking at the parking site(s).
US09542606B2	Lane line recognition apparatus In a lane line recognition apparatus, an abnormality determiner is configured to determine whether or not a width of a travel lane defined by left-side and right-side lane lines is abnormal, and a lane-line recognizer is configured to, when the width of the travel lane is not abnormal, recognize both of the left-side and right-side lane lines in a both-side line recognition mode, and when the width of the travel lane is abnormal, recognize one of the lane lines in a one-side line recognition mode. In the one-side line recognition mode, the lane-line recognizer is configured to, for each of the left-side and right-side lane lines, calculate two or more parameters of the lane line, and then integrate recognition results for the respective two or more parameters, and based on the integrated recognition results of the left-side and right-side lane lines, select one of the lane lines to be recognized.
US09542602B2	Display control device and method A display control device includes circuitry configured to detect a specific object that is supported by an authentication target in an image, obtain content data associated with the specific object, the content data including a registered image of a registered user and positional information between the specific object and the registered image, and control a display to superimpose the registered image on the image at a position based on the positional information in order to provide a comparison between the authentication target and the registered user.
US09542598B2	Package structure and fabrication method thereof A method for fabricating a package structure is provided, including the steps of: disposing and electrically connecting a sensing chip to a substrate; forming an encapsulant on the substrate to encapsulate the sensing chip; and forming a bright layer on the encapsulant to increase the gloss of the package structure. The encapsulant includes an additive to increase the Mohs hardness of the encapsulant. Further, the encapsulant with different additives presents different colors. Therefore, the invention obtains a high-gloss, high-hardness and colorful sensor package structure.
US09542597B2	Event registration and management system and method for a mass gathering event A system and method employing geo-tagging and/or biometric identification is employed for registration and management of a mass gathering event. Electronic devices are configured for capturing data and geo-tagging the captured data using the geographic position of the electronic device. Data relating thereto and related data concerning persons and/or locations and/or other things are associated with a unique identifier and are stored in a relational database from when they may be retrieved and processed for generating a response or other follow up which can be communicated to an electronic device. Responses are communicated to the electronic device that captured the data relating to the particular group of registrants or to an electronic device using its geographic location.
US09542596B2	Systems and apparatus for facilitating the production and presentation of strokes gained golf statistics Systems, methods, and apparatus to facilitate the production and presentation of strokes gained golf statistics. Some systems include mobile devices for the collection of essential shot data necessary for producing strokes gained statistics during play. The device travels with a golfer, measures and records distance-to-hole automatically using GPS and/or laser and/or radio technology, in combination with one of various lie-type classifications (tee, fairway, rough, sand, green, recovery, penalty, hazards, etc.) before and after a golf shot as selected by the golfer using human judgement. The device transfers essential shot data to a remote database and receives and displays calculated strokes gained results.
US09542595B2	Systems and methods for recommending cosmetic products for users with mobile devices An electronic device for analyzing a skin of a subject and identifying a cosmetic product for the subject includes one or more processors and memory storing one or more programs for execution by the one or more processors. The device transfers a digital image of at least a portion of a face of the subject. The digital image includes a plurality of pixels. Skin pixels in the plurality of pixels are identified. Color space values are identified from the skin pixels. A cosmetic product is identified at least based on the color space values. The device transfers information of the cosmetic product.
US09542589B2	Signal strength enhancement in a biometric sensor array A biometric imager may comprise a plurality of sensor element traces formed in or on a sensor substrate which may comprise at least a portion of a display screen defining a biometric sensing area and forming in-active pixel locations; an auxiliary active circuit formed in or on the sensor substrate on the periphery of the biometric sensing area and in direct or indirect electrical contact with the sensor element traces; and providing a signal processing interface to a remotely located controller integrated circuit. The sensor element traces may form a portion of one dimensional linear sensor array or pixel locations in a two dimensional grid array capacitive gap biometric imaging sensor. The auxiliary circuit may provide pixel location selection or pixel signal amplification. The auxiliary circuit may be mounted on a surface of the display screen. The auxiliary circuit further comprising a separate pixel location selection controller circuit.
US09542588B2	Capacitive fingerprint sensor with quadrature demodulator and multiphase scanning A fingerprint sensing circuit, system, and method is disclosed. The fingerprint sensor maybe include a plurality of inputs coupled to a plurality of fingerprint sensing electrodes and to an analog front end. The analog front end may be configured to generate at least one digital value in response to a capacitance of at least one of the plurality of fingerprint sensing electrodes. Additionally, the analog front end may include a quadrature demodulation circuit to generate at least one demodulated value for processing by a channel engine. The channel engine may generate a capacitance result value that is based, in part, on the demodulated value and is stored in a memory.
US09542587B2	Fingerprint information detection circuit The present invention relates to a chip design and discloses a fingerprint information detection circuit. The invention includes a reset unit, a feedback unit, an amplification unit and a source follower unit; the reset unit is connected to the feedback unit and amplification unit, while the feedback unit is connected to the amplification unit, and the amplification unit is connected to the source follower unit; when the reset transistor built-into the reset unit is on, it stores an electric charge, and resets the feedback unit; when the reset transistor is off, the stored electric charge is injected into the feedback unit and amplification unit; the feedback unit receives the electric charge, and outputs the second voltage signal generated when it detects fingerprints to the source follower unit; the amplification unit amplifies the received signal and outputs it to the source follower unit; the source follower unit receives the signal, performs voltage level shifting before outputting the first voltage signal that carries the detected fingerprint information. The present invention enables the circuit to use a reduced chip area, hence, saving the cost of the chip.
US09542586B2	Pattern inspection apparatus and pattern inspection method A pattern inspection method according to one aspect of the present invention includes generating a first positional deviation amount map by using data acquired by a pre-scan, generating a second positional deviation amount map by using data acquired by a full scan, generating a first positional deviation difference map by calculating a difference between the first positional deviation amount map and the second positional deviation amount map, generating a third positional deviation amount map from the first positional deviation difference map and the second positional deviation amount map, and judging existence of a value exceeding an allowable value, in values defined by the third positional deviation amount map.
US09542580B2	RFID communication system and method for controlling same Described herein is a system and method for the continuous operation of an RFID communication system in a user-friendly manner and to ensure the reliability thereof in a cost-effective manner by uploading and storing configuration data from each active reader into a memory of the management system. A control unit polls an activity status for each active reader at regular time intervals. In the event of an active reader failing, the control unit identifies the failed reader, loads the configuration data for the failed reader from a memory into a specified inactive reader, and activates the specified inactive reader in place of the failed reader to identify the at least one RFID transponder.
US09542575B2	Transaction terminal device In a transaction terminal device, a magnetic head module that supports a magnetic head which reads a magnetic card, and a plurality of communication antennas used for communications according to different standards are arranged at the same end within a housing. The magnetic head module includes a line-shaped metal urging member that exerts urging force to a magnetic head in a passing path direction of the magnetic card. Even though a communication antenna is arranged close to the magnetic head, a reradiated radio wave generated from the metal urging member of the magnetic head receiving a radio wave radiated from an adjacent communication antenna is reduced, and communication quality is secured. Accordingly, even though the communication antenna is arranged close to the magnetic head that reads the magnetic card, the transaction terminal device can normally complete the transaction using the read magnetic card.
US09542572B2	Method of managing map information, navigation system, information terminal, and navigation device A method of managing map information including: attaching a retrieval identifier, according to input information, to map information which is obtained by retrieval based on the input information, the retrieval identifier indicating whether the map information is personal data or public data; storing the map information as the personal data into a storage device, the map information being indicated to be the personal data by the retrieval identifier attached in the attaching, and storing the map information as the public data into the storage device, the map information being indicated to be the public data by the retrieval identifier; and executing a navigation process using at least one of the personal data and the public data which are stored in the storage device.
US09542571B2	System and method of owner application control of electronic devices Systems and methods of owner application control of an electronic device are provided. Owner application control information is stored on the electronic device and/or one or more remote servers. Owner application control information is consulted to determine if one or more required applications are available for execution on the electronic device. If not, one or more required applications not available are downloaded and installed. This could be in a manner transparent to the user of the electronic device. If one or more required applications are not available on the electronic device, the device can be functionally disabled in whole, or in part, until one or more required applications are available.
US09542564B2	Personal site privacy policy A request, from a requester, is received to view user information on a user's personal site associated with a user. A relationship is determined between the requester and the user. User information is provided to the requester based on the requester's relationship to the user.
US09542562B2	Display system, display method, display terminal and non-transitory computer-readable recording medium stored with display program A display system for displaying a document includes a tablet terminal and a head mounted display device (HMD). The tablet terminal includes a display device which does not display confidential information that a third party is not allowed to browse, but displays non-confidential information that the third party is allowed to browse with regard to the document. The HMD includes a glasses-type display unit which does not allow the third party to browse, but allows a HMD user to browse, a communication unit which receives the confidential information, and a video camera for capturing the non-confidential information displayed on the display device. The glasses-type display unit, based on the captured non-confidential information, displays the received confidential information so that the received confidential information is visually recognized by the HMD user in a state of being aligned with the non-confidential information displayed on the display device.
US09542559B2	Detecting exploitable bugs in binary code Systems and methods for performing hybrid symbolic execution to detect exploitable bugs in binary code are described. In some example embodiments, the systems and methods determine that resources associated with an execution client performing symbolic execution of a target program are below, at, or above a threshold performance level, generate checkpoints for active executing paths of the online symbolic execution, and cause the execution client to perform symbolic execution in response to the determination that the resources are at or above the threshold performance level.
US09542556B2	Malware family identification using profile signatures A potential malware sample is received from a security device at a server associated with a security cloud service. The sample is executed in a sandbox environment on the server, including by monitoring interaction of the sample with an application program interface (API), provided by the sandbox environment, in order to obtain an API log. It is determined whether the sample is associated with a known malware family including by determining, based at least in part on the API log, if the sample created an executable file and if the sample registered the executable file in a run key. If it is determined that the sample is associated with a known malware family, then an alert is generated.
US09542555B2	Malware detection system and method for compressed data on mobile platforms A system and method for detecting malware in compressed data. The system and method identifies a set of search strings extracted from compressed executables, each of which is infected with malware from a family of malware. The search strings detect the presence of the family of malware in other compressed executables, fragments of compressed executables, or data streams.
US09542552B2	Extensible platform for securing apps on a mobile device using policies and customizable action points An extensible platform gives app developers more control and granularity when developing apps and making them secure. App developers are able to use an app wrapping process to have more control over including non-security related features, such as managerial and administrative features, and more granularity with respect to security features included in the apps they develop. The app wrapping software is extended to be viewed more as a platform for the app developer to customize app security and administrative features without losing the efficiency and simplicity of the original app wrapping process of the present invention.
US09542551B2	Information processing apparatus, information processing method, and non-transitory computer-readable medium An information processing apparatus comprises: a manual login unit configured to display a login screen, and to perform user authentication using user information input through the login screen; an auto login unit configured to perform user authentication using user information held beforehand, without displaying the login screen; a determination unit configured to determine whether or not a password included in user information of a user who is to log in is required to be changed; and a control unit configured to cause not the auto login unit but the manual login unit to perform the user authentication, in the case where the determination unit determines that the password is required to be changed.
US09542547B2	Identification to access portable computing device A portable computing device receives an identity card and restricts access to the portable computing device if the identity card is unassociated with the portable computing device. If access to the portable computing device is restricted, the portable computing device receives identification from a second portable computing device and grants access to the portable computing device if the identification is successfully authenticated.
US09542540B2	System and method for managing application program access to a protected resource residing on a mobile device A computer-implemented method for managing application program access to a protected resource residing on a mobile device is provided. The method includes receiving from an application program a request for a permission to access the protected resource, and receiving from a source external to the mobile device an authentication of the application program. An authorization to provide the permission to access the protected resource is received and permission to access the protected resource is provided to the application program in response to receiving the authorization. Data produced by the protected resource is cryptographically signed, and a notification is generated in response to at least one of the application program requesting the permission to access the protected resource and the application program accessing the protected resource. A system for managing application program access to a protected resource residing on a mobile device is further provided.
US09542538B2	Electronic content management and delivery platform An education digital reading platform provides aggregation, management, and distribution of digital education content and services. The platform ingests content from a variety of content sources, transforms the content for web-based publication, and distributes the content to connected end-user devices via a network. The transformed content preserves the original page structure of the content document regardless of the original format of the content file. As the user experiences the content, the user's web browser regularly communicates with the platform for updating reading content and connected services. User-generated content such as notes are uploaded to the platform so that the user's user-generated content can be accessed from any of the user's registered devices. Moreover, the platform enables the user-generated content and other user activities to be optionally shared among friends, classmates, campus, or other groups, as part of an education social platform.
US09542537B2	Method and system for confidentially providing software components A method and system for confidentially providing a software component which is encrypted using a secret cryptographic key of a software component manufacturer, and the key is then encrypted using a first cryptographic system key, wherein the encrypted software component and the encrypted key are transported by the software component manufacturer to a destination system device. After decrypting the transported encrypted key using a second cryptographic system key, the transported encrypted software component is decrypted using the decrypted key, wherein the decrypted software component is provided for execution on the destination system device. The method can be used to protect source codes or object codes of a developed software component from access by a third party and still allows for processing using standard tools.
US09542528B2	Automated extraction of bio-entity relationships from literature Automated, standardized and accurate extraction of relationships within text. Automatic extraction of such relationships/information allows the information to be stored in structured form so that it can be easily and accurately retrieved when needed. Such information can be used to build online search engines for highly specific and accurate information retrieval. Generally, according to the current invention, extracting such information (i.e., relationships within text) from raw text can be accomplished using natural language processing (NLP) and graph theoretic algorithm. Examples of such textual relationships include, but are not limited to, biological relationships between biological terms such as proteins, genes, pathways, diseases and drugs. The current methodology is also able to recognize negative dependences in context, match patterns, and provide a shortest path between related words.
US09542527B2	Compositions and methods for nucleic acid sequencing Compositions and methods for nucleic acid sequencing include template constructs that comprise double stranded portions in a partially or completely contiguous constructs, to provide for redundant sequence determination through one or both of sequencing sense and antisense strands, and iteratively sequencing the entire construct multiple times. Additional sequence components are also optionally included within such template constructs. Methods are also provided for the use and preparation of these constructs as well as sequencing compositions for their application.
US09542526B2	Method and system for temperature correction in thermal melt analysis The present invention relates to methods and systems for temperature correction in thermal melt analysis. More specifically, embodiments of the invention relate to the correction of the melting temperature (Tm) observed for a sample nucleic acid due to the effect of the nucleic acid concentration.
US09542523B2	Method and apparatus for selecting data path elements for cloning A method and apparatus for selecting data path elements for cloning within an integrated circuit (IC) design is described. The method comprises performing timing analysis of at least one data path within the IC design to determine at least one timing slack value for the at least one data path, calculating at least one annotated delay value for cloning a candidate element within the at least one data path, calculating at least one modified slack value for the at least one data path in accordance with the at least one calculated annotated delay value, and validating the cloning of the candidate element based at least partly on the at least one modified slack value.
US09542522B2	Interconnect routing configurations and associated techniques Embodiments of the present disclosure are directed toward interconnect routing configurations and associated techniques. In one embodiment, an apparatus includes a substrate, a first routing layer disposed on the substrate and having a first plurality of traces, and a second routing layer disposed directly adjacent to the first routing layer and having a second plurality of traces, wherein a first trace of the first plurality of traces has a width that is greater than a width of a second trace of the second plurality of traces. Other embodiments may be described and/or claimed.
US09542518B2	User experience based management technique for mobile system-on-chips A method for designing a system-on-chip (SOC) for a wireless device includes receiving, at a design processor, first usage conditions for a first module of the SOC and second usage conditions for a second module of the SOC. The method further includes determining design parameters for the SOC. The design parameters are determined based on the first usage conditions and the second usage conditions.
US09542517B2	Techniques for fast resonance convergence Some methods provide an electronic design file, which includes an integrated circuit (IC) component that is operably coupled to a package component. The IC component and package component collectively form a resistor inductor capacitor (RLC) resonant circuit. The method also provides a damping component in the electronic design file. This damping component is configured to reduce a pre-resonant time during which energy exchanged in the RLC resonant circuit approaches a steady-state, and thereby speeds simulation time.
US09542516B1	Spice circuit model for twinaxial cable A method to generate a reduced delay twinaxial SPICE model is provided. The method may include measuring near-end S-parameter components and far-end S-parameter components of a twinaxial cable, reducing an original time delay of the far-end S-parameter components by multiplying each of the far-end S-parameter components by a complex exponential based on an equivalent delay length, a signal frequency, and an effective dielectric constant, simulating a signal transmitted across a twinaxial cable by running a 4-port SPICE model using the near-end S-parameter components and the multiplied far-end S-parameter components, and recording a magnitude and a phase of the transmitted signal with respect to frequency as outputs of the reduced delay twinaxial SPICE model.
US09542507B2	Feature detection in seismic volumes Methods, systems, and computer-readable media for analyzing a domain are provided. The method includes defining a mask plane that includes a first dimension of a first number of voxels and a second dimension of a second number of voxels, and selecting a plurality of first angles for orientating the mask plane in the domain with respect to a first axis. The method also includes for each one of the plurality of first angles selected populating, using one or more processors, sum cubes associated with each one of a first plurality of subject voxels. The method also includes selecting a plurality of second angles, and for each one of the plurality of second angles selected, calculating a planar sum for each one of a second plurality of subject voxels selected.
US09542503B2	Estimation of closeness of topics based on graph analytics Embodiments relate to estimating closeness of topics based on graph analytics. A graph that includes a plurality of nodes and edges is accessed. Each node in the graph represents a topic and each edge represents a known association between two topics. A statistical traversal experiment is performed on the graph. A strength of relations between any two topics represented by nodes in the graph is inferred based on statistics extracted from the statistical traversal experiment.
US09542502B2	System and method for XML subdocument selection Methods for XML subdocument selection and corresponding systems and computer-readable mediums. A method includes receiving a document having fragments with attribute/value pairs and receiving logical expressions that define relationships between fragments of the document. The method includes analyzing the logical expressions according to the document and creating an index based on the analysis that includes names of the fragments to be candidates for selection into subdocuments. The method includes extracting, from the document, all fragments named in the index and creating, in the index, an entry for each attribute/value pair. The method includes creating a plurality of subdocuments corresponding to the document and storing the subdocuments, including the respective related fragments.
US09542500B1	Generating network pages using customer-generated network page portions Disclosed are various embodiments for generating network pages for customers that include customer-generated page portions. A request for a network page is obtained from a client. The network page is associated with a network site hosted by a hosting provider on behalf of a customer. A portion of the network page is obtained from a service operated by the customer in response to the request. The network page, which includes the portion, is generated in response to the request. The generated network page is sent to the client in response to the request.
US09542494B2	Proactive delivery of related tasks for identified entities A search engine database is utilized to identify “entities”, or things for which there exists associated discrete, objective information. For hosted information that is independently available, the entity detector independently accesses such information and identifies entities. For information that has defined potential entities, such as entertainment or lifestyle information such defined potential entities are provided to the entity detector to verify, with reference to the search engine database, whether they are entities. Once entities have been identified, a related task generator, with reference to the search engine database, identifies tasks that are related to the identified entities. Such tasks include informational tasks, economic tasks, time-sensitive and location-sensitive tasks. The identified entities and related tasks are provided to applications, with metadata quantifying confidence, relationship, importance, location and time sensitivity, and the like, thereby enabling those applications to proactively provide selects ones of that information to users.
US09542493B1	Data system with temporal user interface Disclosed is an electronic device and system in mobile or stationary environments with an intelligent user interface enabling temporal, categorical or multi-user display capabilities for the user of the system.
US09542488B2	Associating audio tracks with video content In one example, a system comprises at least one processor configured to determine an indication of an audio portion of video content, determine, based at least in part on the indication, one or more candidate audio tracks, determine, based at least in part on the one or more candidate audio tracks, one or more search terms, and provide a search query that includes the search terms. The at least one processor may be further configured to, in response to the search query, receive a response that indicates a number of search results, wherein each one of the search results is associated with content that includes the one or more search terms, select, based at least in part on the response, a particular audio track of the one or more candidate audio tracks, and send a message that associates the video content with at least the particular audio track.
US09542486B2	Techniques for real-time translation of a media feed from a speaker computing device and distribution to multiple listener computing devices in multiple different languages A computer-implemented technique can include receiving a media feed from a speaker computing device representing speech of a speaker user captured by the speaker computing device. The technique can include receiving a plurality of translation requests, each translation request being received from a listener computing device associated with a listener user and corresponding to a request to obtain a translated version of the media feed into a preferred language of the listener user. The technique can include determining the preferred language for each listener user. The technique can include obtaining a machine translated media feed for each of the translation requests, the machine translated media feed corresponding to a translation of the media feed from the source language to the preferred language of the listener user associated with the translation request. The technique can also include outputting the machine translated media feeds to the listener computing devices.
US09542485B1	Method and system for music program selection In providing a music program, a personal music player displays personal activity choices. A user selects a personal activity and provides a time duration for the activity. The player sends a request to a music program server for a music program. The request includes the personal activity and the time duration. The music program server selects a music program record from a plurality of music program records that has an activity attribute which matches the personal activity and a program duration which matches or is less than the time duration. The server extracts location information for the music program from the program entry in the music program record, and sends this to the player. The player uses the location information to obtain the music program. In this manner, a music program is provided to a user based on the personal activity of the user.
US09542481B2	Radiology data processing and standardization techniques Systems and methods for establishing standardization of radiology imaging procedure types and data related to such radiology imaging procedure types are disclosed herein. Radiology imaging data produced from radiology procedures at plurality of different systems and locations may produce different data formats and data values, even for the same radiology procedure. In one example, a radiology imaging order system is configured to standardize these different data formats and data values to a standardized format and identification that can be used for radiology study assignment, categorization, analytics, and related data federation activities. In further examples, multiple radiology procedures from respective facilities are normalized to a radiology procedure type schema, with each normalized radiology procedure type identifiable with a human-readable procedure identifier. Other examples of processing activities and use of the procedure identifier and standardized data are also disclosed herein.
US09542480B2	Systems and methods for programatically classifying text using category filtration Systems and methods for programmatically causing a machine to classify and extract the meaning of text are discussed herein. Some embodiments may provide for a system including circuitry configured to identify topics associated with a block of text and one or more categories for each of the topics. Each unique category across the one or more categories may be further associated with one or more levels of parent and/or child categories to form an expanded category set of category nodes having parent-child relationships. Based on a number of category nodes connected to each unique category, the circuitry may be configured to determine one or more filtered categories from the unique categories and one or more filtered topics. Filtered topics or categories may be used to programmatically classify text with a more relevant data set than may be possible without the filtering.
US09542477B2	Method of automated discovery of topics relatedness A computer system and method for automated discovery of topic relatedness are disclosed. According to an embodiment, topics within documents from a corpus may be discovered by applying multiple topic identification (ID) models, such as multi-component latent Dirichlet allocation (MC-LDA) or similar methods. Each topic model may differ in a number of topics. Discovered topics may be linked to the associated document. Relatedness between discovered topics may be determined by analyzing co-occurring topic IDs from the different models, assigning topic relatedness scores, where related topics may be used for matching/linking a feature of interest. The disclosed method may have an increased disambiguation precision, and may allow the matching and linking of documents using the discovered relationships.
US09542476B1	Refining search queries Methods, systems, and apparatus, including computer program products, for refining search queries. In one implementation, a method includes obtaining a submitted search query, and in response to obtaining the search query: obtaining search results responsive to the search query; selecting a document from a group of documents identified by the search results; generating from a subset of one or more entities associated with the document one or more candidates for refined search queries, including: identifying one or more terms in the search query, where the one or more terms occur in the search query in a particular order relative to each other, and combining the one or more terms with the entity to generate a candidate, where the one or more terms occur in the particular order relative to each other; and identifying one or more of the candidates as being refined search queries for providing with the search results.
US09542473B2	Tagged search result maintainance One or more techniques and/or systems are provided for tagging search results, organizing tagged search results for later access from various devices, public sharing of tagged search results, and/or providing targeted content based upon search results tagged by a user. That is, a user may tag a search result (e.g., a website, an image, a social network profile, etc.), such as through a one-click user input, with a tag to create a tagged search result. The tagged search result may be organized into a public tag collection for sharing and/or exploration of tagged search results by other users. The tagged search result may be organized into a personal tag collection for later access by the user from any device. Because the tagged search result may be indicative of an interest of the user, targeted content associated with the tagged search result may be provided to the user.
US09542470B2	Method and apparatus for obtaining content in screenshot Embodiments of the present disclosure may include a method and apparatus for obtaining the content in a screenshot. In the embodiments of the present disclosure, content organization information associated with the screenshot may be obtained, wherein the content organization information may include the structure and data of one or more data objects associated with the content in the screenshot. The content in the screenshot may be determined based on the content organization information.
US09542467B2	Efficiently firing mapping and transform rules during bidirectional synchronization A method and associated system for efficiently firing mapping and transform rules during a bidirectional synchronization of two or more systems. A processor loads a set of mapping and transform synchronization rules and a set of cross-reference tables. When an event message received from a source system identifies a revision to an element of the source system's data, the processor parses the message to identify the revised source-system data. The processor uses the cross-references to identify synchronization rules that are associated with the revised data element. If any of the identified rules requires an additional source-system data element or an extrinsic data element located at an external source, the processor retrieves those further identified data elements. The processor then looks up the synchronization procedure of the identified rules, packages it into a synchronization message, and sends the message to the target system.
US09542463B2	Method and system for optimizing XA open and XA close operations in a distributed database system A system and method in accordance with the present invention provides for delaying an xa_close call on a connection and reducing the number of xa_open/xa_close calls. This process improves upon the original method of carrying out the xa_close call. The connection is always in an xa_open stage and will avoid a subsequent costly xa_open/xa_close. The only event which triggers the xa_close is the time out on the connection.
US09542462B1	Scaling high-level statistical languages to large, distributed datasets A system and method for performing large-scale data processing using a statistical programming language are disclosed. One or more high-level statistical operations may be received. The received high-level statistical operations may be dynamically translated into a graph of low-level data operations. The unnecessary operations may be removed and operations may be fused or chained together. Operations may then be grouped into distributed data processing operation. The low-level operations may then be run.
US09542460B1	Optimized autocompletion of search field A computer receives event information associated with a user. The computer determines one or more social media contacts associated with the event, wherein the social media contacts are further associated with the user. The computer determines one or more terms utilized by the determined one or more social media contacts. The computer detects an input by the user, wherein the input includes one or more characters. The computer determines one or more autocomplete suggestions based on the one or more terms utilized by the determined one or more social media contacts.
US09542455B2	Anti-trending An automated system for message analysis whereby messages within a given category may be identified and processed as a category connote. While a domain of messages may be monitored and processed in the due course of business, connote message are different. For example, a number of messages may fall into a domain of “poor airline food.” Such messages may be processed in the due course of business. However, a message with a different aspect, such as, “I found glass in my food,” may be initially identified as begin within the domain of “poor airline food,” and processed further to distinguish the message as being a connote with regard to the “poor airline food” category and warranting special handling.
US09542454B2	Object-based information storage, search and mining system The patent application taught an object based information storage, search and mining system and method, which can store, retrieve, and mine massively amount of object data efficiently. A first embodiment includes an object based search engine which can organize and identify the objects efficiently from the search space based on certain operational measure quantifying the search objectives. A second embodiment includes an operational measure estimator which can adaptively adjust or reconfigure itself to improve the accuracy of the estimation. A third embodiment includes a method for mapping objects onto a topological maps to enable identifying objects rapidly from the search space according to certain measures for search objectives. A forth embodiment includes a method for conducting object based search through mapping query objects and search objects onto topological maps and searching effectively through the maps based on certain operational measures.
US09542452B1	Systems and methods for identifying and ranking successful agents based on data analytics A system and a method for identifying and ranking agents are disclosed herein. The system includes an analytics engine which retrieves information from external and internal databases. The analytics engine uses the information retrieved from these databases, in addition to one or more success factors or key attributes, to identify and rank prospective agents. The analytics engine can also match one or more prospective agents with a general agent and provide ranking and performance assessment reports for evaluating and following up on the agent's career development.
US09542450B1	Selecting content using entity properties Systems and methods of the disclosure relate to selecting content via a computer network. A search query provided by a user device can be received. An entity of a search query, a corresponding confidence score, and a property can be identified via a data structure having information about entities. A match between a property of an entity of content selection criteria and the property of the entity of the search query can be determined. The content item can be selected as a candidate for display on the user device based on the match and the confidence score.
US09542447B1	Supplementing candidate answers Candidate answers are generated by a question-answering system in response to a question from a user. One or more generated candidate answers are compared to previous question-answer sets. The previous question-answer sets are indexed and stored in a database which includes a knowledge graph on the previous questions-answer sets. A previous question-answer set is identified as correlating with a first generated candidate answers. The previous question-answer set is identified using relationships of the database. The first generated candidate answer is restructured using the question as a statement which is embedded with the first generated candidate answer. The restructured generated candidate answer which correlates with the previous question-answer set is supplemented with content from the previous question-answer set.
US09542446B1	Automatic generation of composite datasets based on hierarchical fields Datasets are annotated with metadata including categories. Each category corresponds to one or more fields. A hierarchy mapping is generated to indicate a hierarchical relationship between different categories. A natural language query specifies a first granularity level indicating a particular category and one or more field values corresponding to the particular category. Based on the hierarchy mapping, one or more categories that are hierarchically related to the particular category are identified. Based on the metadata, two or more datasets that include at least one hierarchically related category is selected. Based on the first granularity level, one or more dataset filters are generated. The one or more dataset filters are translated to a second granularity level corresponding to the at least one hierarchically related category. The translated filters are applied to at least one of the selected datasets. The two or more datasets are joined to generate a composite dataset.
US09542440B2	Enterprise graph search based on object and actor relationships Systems, methods, and software are disclosed herein for implementing enterprise graph search. In at least one implementation, an enterprise search service receives a search request that includes a graph query directed to an enterprise graph. The graph is representative of various objects and actors associated with an enterprise, as well as which of the actors performed which of various actions with respect to each of the various objects. The service searches at least a portion of the enterprise graph to identify a subset of the objects that relate to the actors as defined by the graph query in terms of at least the actors and actions. A reply to the search request may include graph results indicative of the subset of the objects.
US09542439B1	Simplified query language for accessing metadata A CaQL API is provided by receiving a query directed to a catalog that includes metadata. A catalog access target is determined based at least in part on one or more of the following: a CaQL keyword which is included in the query, a name of a table in the catalog which is included in the query, or a predicate which is included in the query. A catalog function is generated based at least in part on the CaQL keyword and the catalog function is performed on the catalog access target.
US09542437B2	Layout-driven data selection and reporting A system includes a database with a plurality of records, each record including a plurality of data fields. The system receives input from an end user. The end user input is received via an end user interface, and the end user input includes a subset of the plurality of data fields. The system queries the database using the subset of data fields, and data is retrieved from the database using the subset of data fields. The data retrieved from the database substantially include only data fields that are the data fields supplied by the end user. In an embodiment, the retrieved data do not include data fields that are not part of the data fields supplied by the end user.
US09542433B2	Quality assurance checks of access rights in a computing system Systems and methods for ensuring the quality of identity and access management information at a computing system are described. Access right information that respectively corresponds to one or more access rights may be stored at a data store. The access right information may be stored in accordance with a data model that defines respective relationships between the access rights and both the users having access to the computing system and the computing resources of the computing system. At least a portion of the access right information may be retrieved, and quality assurance tasks may be performed using the portion of the access right information retrieved.
US09542431B2	Cyclic commit transaction protocol A cyclic commit protocol is used to store relationships between transactions and is used by the technology to determine whether a transaction is committed or not. The protocol allows creation of a cycle of transactions which can be used to recover the state of a storage device after a host failure by identifying the last committed version of intention records as committed or uncommitted based on the data stored in the physical pages.
US09542428B2	Systems and methods for real-time de-duplication Disclosed are systems, apparatus, and methods for identifying and processing duplicative records in one or more database systems. In various implementations, a first data object may be created and stored in a first database system, where the first data object includes a plurality of data fields capable of storing a plurality of data values. A trigger function may be executed in response to creating the first data object, where the trigger function causes one or more servers to determine if one or more existing data objects stored in the second database system match the first data object, and where the trigger function further causes one or more servers in the first database system to retrieve one or more data values from the one or more existing data objects. The retrieved one or more data values may be stored in one or more data fields of the first data object.
US09542426B2	Memory management for in-memory processing computing environments and systems Data can be stored in a memory for an in-memory processing system such the data is available for processing as soon as it is needed to be processed. A first portion and a second portion of the data can be stored in the memory of the in-memory processing system for processing by the in-memory processing system, such that the second portion of the data is stored in the memory before the in-memory processing system completes the processing of the first portion of the data, thereby allowing the in-memory processing system to process the second portion of the data when the processing system is able to process the second portion of the data.
US09542423B2	Backup user interface Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for storing data are disclosed. In some implementations, visual representations of files are generated for presentation in a backup user interface. The visual representations are generated from sparse file system metadata stored on the computing device, thus allowing faster navigating of the backup user interface. During a restore operation, the metadata can be used to retrieve the items from their physical storage locations. In some implementations, when the storage capacity of a backup storage device exceeds a threshold, the data for the N oldest backups are replaced with sparse file system metadata, which can be used to generate visual representations for presentation in the backup user interface.
US09542413B2	Stored data deduplication method, stored data deduplication apparatus, and deduplication program Method of dividing data to be stored in storage device into data fragments; recording the data by using configurations of divided data fragments; judging whether identical data fragments exist in data fragments; when it is judged that identical data fragments exist, storing one of the identical data fragments in storage area of the storage device, and generating and recording data-fragment attribute information indicating an attribute unique to the data fragment stored; upon receipt of request to read data stored in the storage area of the storage device, acquiring the configurations of the data fragments forming the read-target data, reading the corresponding data fragments from the storage area of the storage device, and restoring the data; acquiring and coupling the recorded data fragments to generate concatenation target data targeted for judgment on whether chunk concatenation is possible or not, and detecting whether the concatenation target data has a repeated data pattern.
US09542411B2	Adding cooperative file coloring in a similarity based deduplication system For adding cooperative file coloring in a similarity based deduplication system using a processor device in a computing environment. Input streams of backup application are parsed and the data segments are marked with file coloring that represents a source file of the backup application for comparing the data segments to determine if the data segments are identical during a similarity check operation.
US09542409B2	Deduplicated file system An apparatus and a method for maintaining a file system is described. An allocation module receives a request from a kernel module to allocate a block of the file system to a file. The allocation module examines an other block of the file system to determine whether the other block contain a same data as the block. The allocation module also determines an external reference count of the other block containing the same data. The other block is then allocated to the file and the external reference count is updated accordingly.
US09542403B2	Symbolic-link identifying Identifying symbolic links in network file systems is provided. An absolute path may be determined at a network file server. This may include determining a complete client path from an initial client path and combining the complete client path with a server export path. Once the absolute path is determined, it may be traversed using a file descriptor of each file in the absolute path to identify a symbolic link.
US09542402B2	Computing devices with multi-layer file systems Technologies are generally described for a multi-layer file system. In the multi-layer file system, a file is arranged into two or more data blocks respectively associated with corresponding multi-entry file indices. Each multi-entry file index can point to a location index at the beginning of a linked list (an initial entry in the linked list). The linked list may have at least one location index as an entry to identify a location in the storage device where the associated data block is stored.
US09542401B1	Using extents of indirect blocks for file mapping of large files Large files in a file system are mapped by extents of contiguous indirect blocks in order to reduce the time for read or write access to the large files while allowing allocation of data blocks one at a time. The inode of a file includes an indication of whether file mapping metadata of the file includes either an extent of contiguous indirect blocks or a tree of blocks. In a preferred mapping scheme, an inode contains an array of block pointer entries, and each entry includes a flag indicating whether the block pointer is pointing to either an extent of indirect blocks or a tree of blocks. For sharing of data blocks between files, the block pointer fields of the indirect blocks each contain an ownership flag indicating whether the pointed-to block is shared or not.
US09542399B2	System and method for removable data storage elements provided as cloud based storage system Provided is a system and method for providing removable data storage elements as a cloud based storage system. More specifically, the method achieves this for at least one embodiment by receiving at least one generally random stream of data objects, each data object having at least one identifiable element. The method directs the selection of at least a first identifiable element. The method then orders the stream of data objects against the first identifiable element and disposes the data objects upon at least one of the removable data storage elements in accordance with the ordered stream of data objects. A system for performing the method is also disclosed.
US09542390B2	Method and apparatus for mitigating face aging errors when performing facial recognition A computer implemented method and apparatus for mitigating face aging errors when performing facial recognition. The method comprises receiving an indication of a face that needs to be searched in an image set, where each image in the image set comprises a timestamp that identifies a creation date of the image, the creation date being in a continuum of successive time intervals; and identifying the indicated face in images taken in each time interval of a plurality of successive time intervals for the indicated face, wherein each face found in images taken in a previous successive time interval is used as a reference set for identifying the face in images taken in a next successive time interval.
US09542388B2	Identifying unchecked criteria in unstructured and semi-structured data A method, system and computer-usable medium are disclosed for identifying unchecked criteria in unstructured and semi-structured data within a form. Text spans representing unchecked criteria within unstructured text in a form are detected and classified to facilitate accurate interpretation of the text. Section identification and annotation operations are then performed to identify and categorize sections within the form. Checklist sections within the form, along with associated checkmarks and boxes, are then identified, followed by the identification of checked item, criteria scope, and previously undetected checklist sections. Once all checklist sections and checked criteria have been identified, remaining text spans within a checklist section are annotated as unchecked criteria.
US09542386B2	Entailment evaluation device, entailment evaluation method, and recording medium An entailment evaluation device includes: a generation unit which generates first information indicating at least the order of occurrence of events of first and second simple sentences included in the hypothesis text and generates second information indicating at least the order of occurrence of events of third and fourth simple sentences included in a target text, the third simple sentence being related to the first simple sentence, the fourth simple sentence being related to the second simple sentence; a calculation unit which obtains a calculation result by comparing, based on the first and second information, the order of occurrence of events of first and second simple sentences and order of occurrence of events of third and fourth simple sentences; and a determination unit which determines, based on at least the calculation result, whether or not the target text entails the hypothesis text.
US09542385B2	Incremental multi-word recognition In one example, a computing device includes at least one processor that is operatively coupled to a presence-sensitive display and a gesture module operable by the at least one processor. The gesture module may be operable by the at least one processor to output, for display at the presence-sensitive display, a graphical keyboard comprising a plurality of keys and receive an indication of a continuous gesture detected at the presence-sensitive display, the continuous gesture to select a group of keys of the plurality of keys. The gesture module may be further operable to determine, in response to receiving the indication of the continuous gesture and based at least in part on the group of keys of the plurality of keys, a candidate phrase comprising a group of candidate words.
US09542381B2	Automatic training of a syntactic and semantic parser using a genetic algorithm Disclosed are methods, systems, and computer-readable mediums for automatic training of a syntactic and semantic parser using a genetic algorithm. An initial population is created, where the initial population comprises a vector of parameters for elements of syntactic and semantic descriptions of a source sentence. A natural language compiler (NLC) system is used to translate the sentence from the source language into a target language based on the syntactic and semantic descriptions of the source sentence. A vector of quality ratings is generated where each quality rating in the vector of quality ratings is of a corresponding parameter in the vector of parameters. Quality ratings are evaluated according to specific criterion, which comprise parameters such as a BLEU score and a number of emergency sentences. A number of parameters in the vector of parameters are replaced with adjusted parameters.
US09542375B2	Structured document bounding language Using a bounding language to control or restrict the changes that can be made to contents of a structured document (e.g., a document encoded in the Extensible Markup Language, or “XML”), and also the bounding language and documents encoded according to the bounding language. A Document Type Definition (“DTD”) is defined as a “bounding DTD”, and one or more structured documents containing editing restrictions are defined according to this DTD. A processing component uses a structured document containing editing restrictions as input, and programmatically determines which fields of another structured document can be edited, which fields should be hidden, and so forth. By restricting the parts of the file that can be edited, users who need to do the editing are shielded from irrelevant details, and can carry out their task with less risk of making errors (and without needing to understand the details of the structured document markup language).
US09542370B2	Method and apparatus for sharing JavaScript object in webpages A method and apparatus for sharing webpage JavaScript objects are disclosed. An embodiment of the invention provides a method for sharing JavaScript objects of webpages that are provided by a server by way of a browser executed at a user client. The method includes: (a) storing a shared JavaScript object from among one or more JavaScript objects of a first webpage in a predefined object storage area; (b) checking for a shared JavaScript object in a second webpage; and (c) forming the second webpage with the shared JavaScript object extracted, where the object storage area is positioned in a JavaScript context.
US09542367B2	Programmatic self-learning of inter-system document processing configurations In response to reception of an electronic data interchange (EDI) instance document, a determination is made that a hierarchical EDI reception processing rule sequence, useable to partition encoded hierarchical envelopes of the EDI instance document and to invoke processing of payload data packaged within the encoded hierarchical envelopes, has not been configured. Through analysis of content of the EDI instance document, an EDI standard and syntax formatting of the encoded hierarchical envelopes that package the payload data within the EDI instance document are determined. An EDI reception processing sequence definition that encodes the hierarchical EDI reception processing rule sequence is configured that is usable to partition the encoded hierarchical envelopes of the EDI instance document and to invoke the processing of the payload data packaged within the encoded hierarchical envelopes.
US09542355B2	Method for recalibrating coordinate positioning apparatus A method and corresponding apparatus are described for recalibrating coordinate positioning apparatus after a disturbance, such as a stylus replacement. The coordinate positioning apparatus includes a platform, a measurement probe and a probe head for reorienting the measurement probe relative to the platform. A calibration data set is taken for the coordinate positioning apparatus that includes datum data for a plurality of orientations of the measurement probe. The datum data includes at least first datum data for a first nominal orientation of the measurement probe. After a disturbance to the coordinate positioning apparatus, the calibration data set is updated by acquiring one or more position measurements and calculating a first correction from the one or more position measurements. The first correction describes any change in the first datum data following the disturbance and is used to update the datum data for plurality of different orientations of the measurement probe. Corresponding apparatus is also described.
US09542352B2	System and method for reducing command scheduling constraints of memory circuits A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
US09542348B2	Arbitration monitoring for serial attached small computer system interface systems during discovery Methods and structure for detecting that arbitration is delaying discovery. One embodiment is a Serial Attached Small Computer System Interface (SAS) expander. The SAS expander includes multiple SAS ports, a port monitor, and a controller. The port monitor is able to track physical link events during arbitration for at least one of the ports while discovery is in progress at the expander, and to detect based on the physical link events that arbitration is delaying discovery. The controller is able to prioritize discovery requests at the expander responsive to detecting that arbitration is delaying discovery.
US09542345B2	Interrupt suppression strategy The disclosed embodiments provide a system that suppresses interrupts to facilitate efficient use of a processor in a computer system. The system includes a node that transmits a first interrupt to the processor upon receiving a first packet for processing at the processor and disables subsequent interrupts to the processor during an interrupt-suppression state in the processor. The system also includes the processor, which processes the first packet upon receiving the first interrupt and transmits a first acknowledgment of the first packet to the node to enable the interrupt-suppression state.
US09542343B2	Memory modules with reduced rank loading and memory systems including same A memory module includes memory devices arranged in ranks and columns and designated in first and second groupings, the first grouping includes memory devices arranged in only a first rank nearest a memory controller and directly connected to the memory controller, the memory devices in the second grouping are indirectly connected to the memory controller via a corresponding memory device in the first grouping arranged in a same column, and each memory device selectively provides either self-data retrieved from a constituent memory core or other-data retrieved from a memory core of another memory device during the read operation.
US09542332B2	System and method for performing hardware prefetch tablewalks having lowest tablewalk priority A hardware prefetch tablewalk system for a microprocessor including a tablewalk engine that is configured to perform hardware prefetch tablewalk operations without blocking software-based tablewalk operations. Tablewalk requests include a priority value, in which the tablewalk engine is configured to compare priorities of requests in which a higher priority request may terminate a current tablewalk operation. Hardware prefetch tablewalk requests having the lowest possible priority so that they do not bump higher priority tablewalk operations and are bumped by higher priority tablewalk requests. The priority values may be in the form of age values indicative of relative ages of operations being performed. The microprocessor may include a hardware prefetch engine that performs boundless hardware prefetch pattern detection that is not limited by page boundaries to provide the hardware prefetch tablewalk requests.
US09542329B1	System and method for managing an object cache In order to optimize efficiency of deserialization, a serialization cache is maintained at an object server. The serialization cache is maintained in conjunction with an object cache and stores serialized forms of objects cached within the object cache. When an inbound request is received, a serialized object received in the request is compared to the serialization cache. If the serialized byte stream is present in the serialization cache, then the equivalent object is retrieved from the object cache, thereby avoiding deserialization of the received serialized object. If the serialized byte stream is not present in the serialization cache, then the serialized byte stream is deserialized, the deserialized object is cached in the object cache, and the serialized object is cached in the serialization cache.
US09542328B2	Dynamically controlling a file system write cache Methods, computing systems and computer program products implement embodiments of the present invention that include initializing, by a processor executing a file system in communication with a block manager managing multiple storage regions on a storage device, a file system write cache to have a default cache size, the default cache size corresponding to a first storage capacity of a default number of the storage regions. Upon detecting that a current number of the storage regions that are not in use by the block manager is less than the default number, the file system write cache is resized to a reduced cache size that corresponds to a second storage capacity of the current number of the storage regions. While the file system write cache has the reduced cache size, the file system write cache can be resized back to the default cache size as unused storage regions become available.
US09542327B2	Selective mirroring in caches for logical volumes Methods and structure for selective cache mirroring. One embodiment includes a control unit and a memory. The memory is able to store indexing information for a multi-device cache for a logical volume. The control unit is able to receive an Input/Output (I/O) request from a host directed to a Logical Block Address (LBA) of the logical volume, to consult the indexing information to identify a cache line for storing the I/O request, and to store the I/O request at the cache line on a first device of the cache. The control unit is further able to mirror the I/O request to another device of the cache if the I/O request is a write request, and to complete the I/O request without mirroring the I/O request to another device of the cache if the I/O request is a read request.
US09542326B1	Managing tiering in cache-based systems A method and a system for use in managing tiering in a cache-based system is disclosed wherein the cache-based system comprises a first data storage tier and a second data storage tier configured such that the performance characteristics associated with one of the tiers is superior to the performance characteristics associated with the other tier. In at least one embodiment the method and system comprises collecting a first set of I/O activity data for at least one data unit located in a cache, wherein the at least one data unit is associated with a data group located on the first data storage tier; collecting a second set of I/O activity data for the data group located on the first data storage tier; analyzing the first and second set of I/O activity data; and based on the analysis and the performance characteristics associated with the second data storage tier, determining whether the data group should be migrated to the second data storage tier.
US09542322B2	Data access management in a hybrid memory server Once or more embodiments manage access to data by accelerator systems in an out-of-core processing environment. In one embodiment, a request from an accelerator system is received for access to a given data set. An access context associated with the given data set is determined. The accelerator system is dynamically configured, based on the access context that has been determined, based on the access context that has been determined, to one of access the given data set directly from the server system; locally store a portion of the given data set in a memory; and locally store all of the given data set in the memory.
US09542316B1	System and method for adaptation of coherence models between agents A system and method are disclosed for multiple coherent caches supporting agents that use different, incompatible coherence models. Compatibility is implemented by translators that accept coherency requests and snoop responses from an agent and accept snoop requests and coherency responses from a coherence controller. The translators issue corresponding coherency requests and snoop responses to the coherence controller and issue corresponding coherency responses and snoop requests to the agent. Interaction between translators and the coherence controller accord with a generic coherence model, which may be a subset, superset, or partially inclusive of features of any native coherence model. A generic coherence protocol may include binary values for each of characteristics: valid or invalid, owned or non-owned, unique or shared, and clean or dirty.
US09542315B2	Tiled storage array with systolic move-to-front organization A tiled storage array provides reduction in access latency for frequently-accessed values by re-organizing to always move a requested value to a front-most storage element of array. The previous occupant of the front-most location is moved backward according to a systolic pulse, and the new occupant is moved forward according to the systolic pulse, preserving the uniqueness of the stored values within the array, and providing for multiple in-flight access requests within the array. The placement heuristic that moves the values according to the systolic pulse can be implemented by control logic within identical tiles, so that the placement heuristic moves the values according to the position of the tiles within the array. The movement of the values can be performed via only next-neighbor connections of adjacent tiles within the array.
US09542313B2	Parallel computer system, control method of parallel computer system, information processing device, arithmetic processing device, and communication control device A parallel computer system includes information processing devices, each of the information processing devices including a communication control device that performs communication, a main memory that stores data, and an arithmetic processing device that is coupled to the communication control device and the main memory, the information processing devices being coupled to each other through a network by the respective communication control device, wherein the arithmetic processing device includes a cache memory and a cache controller, the cache controller that executes an atomic operation for target data on the cache memory that stores the target data when the communication control device outputs an atomic operation request that is used to request the atomic operation, the atomic operation being not divided into a smaller operation, and notifies the communication control device of a result that is obtained by executing the atomic operation on the cache memory.
US09542312B2	Selectively programming data in multi-level cell memory Devices, systems, methods, and other embodiments associated with accessing memory are described. In one embodiment, a method detects that a power quality associated with a volatile memory in a computing device meets a threshold value and in response thereto, reprogramming data from the volatile memory to a flash memory comprising multi-level cells. The reprogramming comprises: copying the data from the volatile memory, and writing the copied data: (1) to the most significant bits of the multi-level cells in the flash memory while skipping the least significant bits of the multi-level cells, or (2) to the least significant bits of the multi-level cells while skipping the most significant bits.
US09542307B2	Shiftable memory defragmentation Shiftable memory that supports defragmentation includes a memory having built-in shifting capability, and a memory defragmenter to shift a page of data representing a contiguous subset of data stored in the memory from a first location to a second location within the memory to be adjacent to another page of stored data. A method of memory defragmentation includes defining an array in memory cells of the shiftable memory and performing a memory defragmentation using the built-in shifting capability of the shiftable memory to shift a data page stored in the array.
US09542299B2	Processing core data produced by a computer process A method, apparatus, computer program and computer program product for processing core data produced by a computer process to identify data relevant to the computer process, the method comprising the steps of: identifying core data for a computer process; identifying trace data comprising sequential trace entries for the computer process; selecting a predetermined number of most recent entries in the trace data; identifying any references to a memory address in each selected trace data entry; dereferencing each identified memory address in the core data; and extracting the data from the dereferenced memory location in the core data.
US09542296B1	Disk replacement using a predictive statistical model In a provider network, attributes of one of a plurality of storage devices of the provider network are identified for failure monitoring. Based on a failure prediction model, a predicted probability of failure of the selected storage device is determined. The failure prediction model is based on historical and current data associated with failures of the storage devices of the provider network that have common attributes. The selected storage device is deactivated in response to determining that the predicted probability of failure of the selected storage device meets a criterion.
US09542291B2	Self-monitoring event-based system and method Certain example embodiments relate to an event-based system configured for self-monitoring. The event-based system includes a complex event processing (CEP) engine for consuming and producing events in accordance with at least one continuous query. The CEP engine in turn includes a first continuous query for producing events of a first event type and for consuming the events of the first event type. The CEP engine also is configured to detect performance issues based on the first continuous query.
US09542290B1	Replicating test case data into a cache with non-naturally aligned data boundaries Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.
US09542284B2	Buffered automated flash controller connected directly to processor memory bus A mechanism is provided for direct memory access in a storage device. Responsive to the buffered flash memory module receiving from a memory bus of a processor a memory command specifying a write operation, the mechanism initializes a first memory buffer in the buffered flash memory module. The mechanism writes to the first memory buffer based on the memory command. Responsive to the buffer being full, the mechanism deterministically maps addresses from the first memory buffer to a plurality of solid state drives in the buffered flash memory module using a modular mask based on a stripe size. The mechanism builds a plurality of input/output commands to persist contents of the first memory buffer to the plurality of solid state drives according to the deterministic mapping and writes the contents of the first memory buffer to the plurality of solid state drives in the buffered flash memory module according to the plurality of input/output commands.
US09542276B2	Multi stream deduplicated backup of collaboration server data Techniques to backup collaboration server data are disclosed. An indication to begin backup of a collaboration server dataset is received. An associated directory is walked in a prescribed order to divide the dataset into a prescribe number of approximately equal-sized subsets. A separate subset-specific thread is used to back up the subsets in parallel. In some embodiments in which the collaboration data is stored in multiple volumes, a volume-based approach is used to back up the volumes in parallel, e.g., one volume per thread. In some embodiments, transaction logs are backed up in parallel with volumes of collaboration data.
US09542274B2	System and methods of managing content in one or more networked repositories during a network downtime condition A method of managing content in a network by a cache repository that includes receiving content from a content source; storing the content in the cache repository; sending the content to a remote repository for storage; and determining if a connection to the remote repository can be established in the network. If the connection to the remote repository can be established, the method includes retrieving the content from the remote repository; and if the connection to the remote repository cannot be established, the method retrieves the content from a backup repository.
US09542273B2	Storage control apparatus, storage control system, and storage control method for failure detection and configuration of cascaded storage cabinets A storage control apparatus includes: a detector configured to detect a failure in one of a plurality of storages, each of a plurality of cabinets coupled in a cascade and having the plurality of storage units; a mover configured to move data in one or a plurality of first storages accommodated in a first cabinet including a failed storage having the failure detected by detector to one or a plurality of second storages accommodated in a second cabinet included in the plurality of cabinets; and a connection controller configured to control a first connection between the first cabinet and the plurality of cabinets other than the first cabinet and a second connection between the plurality of first storages in the first cabinet and the plurality of cabinets other than the first cabinet.
US09542271B2	Method and apparatus for reducing read latency A method and an apparatus for reducing a read latency are provided. The method includes: when one or more flash chips corresponding to a read command are in a busy state, setting data read from the one or more flash chips in a busy state to wrong data; obtaining, according to the wrong data and data read from other flash chips, reconstructed correct data, and reporting the correct data. By using the present invention, data read from a flash chip is set to wrong data, and reconstructed correct data is obtained according to the wrong data and data read from other flash chips. In this way, when the flash chip is in a busy state, it can be avoided that a read operation is blocked by an erase operation or a write operation, thereby effectively reducing latency and improving a performance of a storage system.
US09542269B1	Controller controlling semiconductor memory device and operating method thereof An operating method for controlling a semiconductor memory device according to an embodiment may include storing read commands in a command queue managed on first-in first-out basis; providing one of the read commands to the semiconductor memory device; determining whether the provided read command passes or fails based on read data, which is provided from the semiconductor memory device in response to the provided read command; and aborting remaining read commands in the command queue when the provided read command passes.
US09542262B1	Error correction A method for error correction, the method comprises receiving a codeword that comprises a payload and a redundancy section; error-correction decoding the codeword by applying a syndrome-based error correction process to provide an amended payload and an error-correction decoding success indicator; wherein the amended payload comprises an amended CRC signature and an amended payload data; calculating, using the amended payload CRC signature, a validity of the amended payload to provide a CRC validity result; estimating a number of errors in the redundancy section; and determining that the error-correction succeeded when the number of errors in the redundancy section did not exceed a threshold, the error correction success indicator indicates that the error-correction decoding failed, and the CRC validity result indicates that the amended payload is valid.
US09542255B2	Troubleshooting based on log similarity The present disclosure relates to a method and apparatus for troubleshooting based on log similarity. In one embodiment, there is provided a method for troubleshooting based on log similarity, comprising: extracting log patterns from multiple log files in response to having collected the multiple log files from at least one system with troubles, the log pattern describing a regular expression to which a log message in a log file among the multiple log files conforms; building a pattern repository using the log patterns; mapping each of the multiple log files to an n-dimensional vector based on the pattern repository; and clustering multiple n-dimensional vectors to which each of the multiple log files is mapped into at least one group, wherein each of the at least one group indicates one trouble type of the at least one system. In another embodiment, there is provided a corresponding apparatus.
US09542248B2	Dispatching function calls across accelerator devices In one embodiment, a computer-implemented method for dispatching a function call includes receiving, at a supervisor processing element (PE) and from an origin PE, an identifier of a target device, a stack frame of the origin PE, and an address of a function called from the origin PE. The supervisor PE allocates a target PE of the target device. The supervisor PE copies the stack frame of the origin PE to a new stack frame on a call stack of the target PE. The supervisor PE instructs the target PE to execute the function. The supervisor PE receives a notification that execution of the function is complete. The supervisor PE copies the stack frame of the target PE to the stack frame of the origin PE. The supervisor PE releases the target PE of the target device. The supervisor PE instructs the origin PE to resume execution of the program.
US09542247B2	Content sharing between sandboxed apps Embodiments may include sharing application management data between sandboxed applications on a device. A method includes sending application management data from a first sandboxed application in a first sandbox on the device to a sharing service external to the first sandbox. The method further includes receiving at a second sandboxed application in a second sandbox on the device, a representation of the application management data. Based on the representation of the application management data, the method includes performing an application management function.
US09542246B2	Sharing a partitioned data set across parallel applications Provided are techniques for sharing a partitioned data set across parallel applications. Under control of a producing application, a partitioned data set is generated; a descriptor that describes the partitioned data set is generated; and the descriptor is registered in a registry. Under control of a consuming application, the registry is accessed to obtain the descriptor of the partitioned data set; and the descriptor is uses to determine how to process the partitioned data set.
US09542244B2	Systems and methods for performing primitive tasks using specialized processors A primitives library facilitates compiling, linking, and execution of programs that use specialized processors to perform primitive tasks. Data associated with a primitive may be accessed by a specialized-processor-based storage node manager independently of any other processing device.
US09542242B2	Efficient operations of components in a wireless communications device Various embodiments comprise apparatuses and methods including a communications subsystem having an interface module and a protocol module with the communications subsystem being configured to be coupled to an antenna. An applications subsystem includes a software applications module and an abstraction module. The software applications module is to execute an operating system and user applications; the abstraction module is to provide an interface with the software applications module. A controller interface module is coupled to the abstraction module and the interface module and is to convert signals from the applications subsystem into signals that are executable by the communications subsystem. Additional apparatuses and methods are described.
US09542240B2	Information processing apparatus, computer-readable storage medium having information processing program stored therein, information processing method, and information processing system An application process unit executes a predetermined application program and a communication process unit performs a predetermined data communication process with another communication target. A communication stop determination unit determines whether or not to stop the data communication process performed by the communication process unit, on the basis of an instruction from the application process unit. When it is determined by the communication stop determination unit to stop the data communication process, the data communication process is stopped.
US09542238B2	Systems and methods for direct memory access coherency among multiple processing cores A multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access (DMA) engine capable of selecting, by a task scheduler of a first core, a first task for execution by the first core. In response to a semaphore lock request, the task scheduler of the first core switches the first task to an inactive state and selects a next task for execution by the first core. After the semaphore engine acquires the semaphore lock of the first semaphore, a data transfer request is provided to the DMA engine. In response to the data transfer request, the DMA engine transfers data associated with the locked first semaphore to the entry of the workspace of the first core.
US09542233B1	Managing a free list of resources to decrease control complexity and reduce power consumption Embodiments include method, systems and computer program products for searching a social network for media content. Aspects include identifying one or more available resources for execution by the processor, determining a maximum number of resources the processor can utilize in executing an instruction group, and grouping the one or more available resources into one or more resource groups, wherein each of the one or more resource groups has a size equal to the maximum number. Aspects also include receiving a request from a decode logic for a number of resources for execution and dispatching one of the one or more resource groups in response to the request by providing the number of resources for execution to the processor and sending remaining resources in the one of the one or more resource groups to a recycle queue.
US09542232B2	System and method for transforming legacy desktop environments to a virtualized desktop model A system and method for transforming a legacy device into a virtualized environment, comprising includes analyzing the profiling data for at least one application to determine usage frequency and resource requirements of the at least one application. Captured user events are benchmarked to simulate a user workload for the at least one application to determine how resource utilization and execution times scale from a legacy environment to a virtualized environment. The legacy device is transformed into the virtualized environment in accordance with a provisioning plan.
US09542230B2	System and method for selective timer coalescing A method and apparatus of a device that coalesces the execution of several timers by scheduling the timers using a scheduling window is described. The device determines a scheduling window for each of several timers. The device selects a coalesced execution time that is within the scheduling window of the timers. The device coalesces the execution of the timers by scheduling the timers to execute at the coalesced execution time. The device can further coalesce multiple timers by opportunistic execution of the timers. In response to a detection of an opportunistic execution trigger event, the device receives multiple timers. The device selects a subset of the timers to execute based on an initial execution time and a latency time for each of the timers. The device schedules each of the subset of timers to execute during or before the opportunistic execution trigger event.
US09542225B2	Method and apparatus for determining allocation design of virtual machines A disclosed method includes: receiving a request to allocate one or plural virtual machines for a system that includes the one or plural virtual machines to one or plural physical machine; reading out first data concerning an evaluation indicator for virtual machine allocation, wherein the first data is registered in association with the system or a requesting source of the request; first calculating, for each virtual machine of the one or plural virtual machines, a first cost in case where the virtual machine is allocated to any one of usable physical machines, based on the read first data to identify, for each virtual machine of the one or plural virtual machines, a physical machine for which the calculated first cost is the least; and generating allocation design data including second data concerning the physical machine identified for each virtual machine of the one or plural virtual machines.
US09542220B2	System and method for supporting resource manager (RM) instance awareness in a transactional environment A system and method can support transaction processing in a transactional environment. A transactional server operates to receive resource manager (RM) instance information from a data source that is associated with one or more RM instances, wherein the received instance information allows the transactional server to be aware of which RM instance that the transactional server is currently connected to. Furthermore, the transactional server operates to save the received instance information into one or more tables that are associated with the transactional server. Then, the transactional server can process a global transaction based on the instance information saved in the one or more tables.
US09542214B2	Operating system virtualization for host channel adapters A host information handling system (IHS) provides virtualization of host channel adapters (HCAs). A hypervisor partitions a system memory of the host IHS into multiple logical partitions (LPARs). A particular LPAR includes a single instance of an operating system. The single instance of the operating system includes a common layer that provides virtualization of physical HCAs and sharing of the physical HCAs by multiple virtual HCAs.
US09542213B2	Method and system for identifying virtualized operating system threats in a cloud computing environment Systems for monitoring a virtual machine in a cloud computing environment are disclosed. The systems include a baseline module residing on the virtual machine configured to retrieve baseline information from the virtual machine and create a plurality of baseline files and a trends module configured to retrieve a number of baseline files, comparatively analyze the number of baseline files and generate at least one trends report based on the comparative analysis of baseline files.
US09542207B2	Plurality of interface files usable for access to BIOS A computer may comprise a processor and first storage device coupled to the processor. The first storage device contains a basic input/output system (BIOS) executable by the processor. The system may also comprise a second storage device coupled to the processor. The second storage device may contain a management interface usable by an operating system to access the BIOS. A plurality of interface files may also be provided, each interface file being usable by the management interface to access the BIOS and each interface file defining one or methods for use by the interface or BIOS. Upon execution of the BIOS, the processor is to determine a configuration of the system and, based on the determined configuration, to select a particular interface file for use during run-time.
US09542205B2	Configuring a data center Embodiments of the present disclosure disclose a method and an apparatus for configuring a data center. The method comprises obtaining a function call corresponding to data to be configured based on a template for configuring the data center; obtaining a vendor driver corresponding to the data based on the template for configuring the data center. The method further comprises configuring the data by the vendor driver executing the function call. Based on the embodiments of the present disclosure, the way of automatically configuring the data center based on the template may improve the efficiency and security for configuration of the data center.
US09542202B2	Displaying and updating workspaces in a user interface Providing a bridge interface for managing virtual workspaces is disclosed. A plurality of workspace images is presented in a user interface, each workspace image corresponding to a different virtual workspace available to a user of a computer system. A user input indicating a selection of a presented workspace image is received. The user interface is updated to display a plurality of application windows associated with the selected virtual workspace in addition to displaying the plurality of workspace images.
US09542199B2	Method of managing a solid state drive, associated systems and implementations One embodiment of a method includes loading, by a memory controller, a boot image from a solid state drive to an operating memory of a computing system during an initialization operation of the computing system. The initialization operation initializes components of the computing system.
US09542197B2	Router and a virtual trusted runtime BIOS An implementation may include a virtual trusted runtime BIOS managed by the virtual machine monitor. A replacement portion of the virtual trusted runtime BIOS may be included. A router can replace an address to a resource of the virtual trusted runtime BIOS with the address to the resource of the replacement portion of the virtual trusted runtime BIOS.
US09542196B2	Communication terminal and method for providing configuration data for a modem with system boot firmware A communication terminal is described comprising a modem; a first memory configured to store configuration data for the modem; a second memory configured to store a system boot firmware; and a processor configured to execute the system boot firmware and to read the configuration data from the memory and provide it for the modem under the control of the system boot firmware.
US09542195B1	Motherboards and methods for BIOS failover using a first BIOS chip and a second BIOS chip Systems and methods for BIOS failover. A processor reset is detected and a timer is set to expire after a predetermined time corresponding to a time to complete loading a first BIOS image from a first BIOS chip. Loading of the first BIOS image is initiated and it is determined whether the first BIOS image loaded successfully before the timer expired. If the timer expires before the first BIOS image is loaded successfully, loading is switched to a second BIOS image from a second BIOS chip. According to another aspect, loading of a first BIOS image from a first BIOS chip is initiated and a reset of a processor is detected. A reset counter is incremented in response to detecting a reset of the processor and loading is switched to a second BIOS image from a second BIOS chip when the reset counter reaches a reset threshold.
US09542193B2	Memory address collision detection of ordered parallel threads with bloom filters A semiconductor chip is described having a load collision detection circuit comprising a first bloom filter circuit. The semiconductor chip has a store collision detection circuit comprising a second bloom filter circuit. The semiconductor chip has one or more processing units capable of executing ordered parallel threads coupled to the load collision detection circuit and the store collision detection circuit. The load collision detection circuit and the store collision detection circuit is to detect younger stores for load operations of said threads and younger loads for store operations of said threads.
US09542190B2	Processor with fetch control for stoppage A data processor of an embodiment includes a memory, an instruction cache, a processing unit (CPU), and a fetch process control unit. The memory stores a program in which a plurality of instructions are written. The instruction cache operates only when a branch instruction included in the program is executed, and data of a greater capacity than a width of a bus of the memory is read from the memory and stored in the instruction cache in advance. The processing unit accesses both the memory and the instruction cache and executes, in a pipelined manner, instructions read from the memory or the instruction cache. The fetch process control unit generates, in response to a branch instruction executed by the processing unit, a stop signal for stopping a fetch process of reading an instruction from the memory, and outputs the stop signal to the memory.
US09542189B2	Heuristics for improving performance in a tile-based architecture One embodiment of the present invention includes a technique for processing graphics primitives in a tile-based architecture. The technique includes storing, in a buffer, a first plurality of graphics primitives and a first plurality of state bundles received from a world-space pipeline, and transmitting the first plurality of graphics primitives to a screen-space pipeline for processing while a tiling function is enabled. The technique further includes storing, in the buffer, a second plurality of graphics primitives and a second plurality of state bundles received from the world-space pipeline. The technique further includes determining, based on a first condition, that the tiling function should be disabled and that the second plurality of graphics primitives should be flushed from the buffer, and transmitting the second plurality of graphics primitives to the screen-space pipeline for processing while the tiling function is disabled.
US09542178B2	In-place definition of software extensions Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for providing in-place extensions to an application, including receiving one or more artifacts associated with the application; graphically depicting a representation of at least one artifact of the one or more artifacts on a display, the at least one artifact comprising extension points defined by a developer of the application; receiving first user input indicating a first extension to the at least one artifact, the first extension being associated with an extension point of the one or more extension points and being applied to the representation, the at least one artifact remaining unchanged in view of the first extension being applied to the representation; determining a delta based on the first extension and the at least one artifact; and storing the delta in an extension repository, the delta being usable to extend one or more other artifacts.
US09542177B1	Peer configuration analysis and enforcement The states or configurations of peer hosts within a host class may be analyzed and enforced by comparing records of the respective systems' states or configurations to one another and taking steps to address any inconsistencies between the records. In such a manner, the respective systems within the host class may identify, analyze and/or correct any changes in states or configurations of any of the systems, which may have been caused by a malfunction or security breach. The configurations may include one or more of a set of data, a version of a software application, a level of permission, a particular operational setting or any other element of operation. The hosts may be defined as peers based on a common location or a common function of each of the systems, or on any other basis, and the records may include any relevant data relating to the states or configurations of each of the systems.
US09542172B2	Automatic updating of applications In some implementations, a mobile device can be configured to automatically download and install updates to applications installed on the mobile device. In some implementations, the automatic updates can be performed based on how the mobile device is connected to a network that provides access to the application updates. In some implementations, the automatic updates can be performed based on whether the mobile device has previously downloaded applications or application updates from a caching server. In some implementations, indicia can be presented on a graphical user interface of the mobile device to indicate which applications have been updated. In some implementations, an application update can be downloaded while the corresponding application is in use by the user. The application can be installed when the application is no longer being used by the user.
US09542168B2	Hostable compiler utilizing type information from a host application A hostable compiler interacts with a host application to enable the host application to execute program code supported by the hostable compiler. The host application and the hostable compiler exchange data through an interface that allows the hostable compiler to receive type information pertaining to data elements used in applications executing within the host application process. This type information may then be used by the hostable compiler in the compilation of source code to infer a type for data elements used in the source code that are not declared yet associated with a value of an expression used in an application executed within the host application process.
US09542167B2	Performance monitoring of virtualized instructions Systems and methods for monitoring performance of virtualized instructions are provided. One method includes, during emulated execution of non-native program code including non-native instructions, maintaining a program flow history in a computing system representing a flow of program execution of the non-native program code. The program flow history includes a listing of non-native jump instructions for which execution is emulated in the computing system. The method also includes capturing one or more statistics regarding performance in native execution of the non-native program code on the computing system. The method further includes correlating the one or more statistics to the program flow history to determine performance of the computing system in executing one or more non-native instructions between each of the non-native jump instructions.
US09542165B2	Model to Petri-Net transformation Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for model-to-model transformation including actions of providing a source meta-model, the source meta-model having a plurality of classes and one or more references, receiving first user input to a graphical editor, processing the first user input to provide a plurality of class modules and one or more reference modules, each class module corresponding to a class of the plurality of classes and each reference module corresponding to a reference of the one or more references, automatically generating transformation code based on the plurality of class modules and the one or more reference modules, receiving a source model, the source model being provided based on the source meta-model and being provided in a computer-readable file that is stored in memory, and generating a simulation model based on the source model and the transformation code.
US09542163B2	Systems and methods for processing analytics on mobile devices Embodiments of a system and method are described for generating and distributing programming to mobile devices over a network. Devices are provided with Players specific to each device and Applications that are device independent. Embodiments include a full-featured WYSIWYG authoring environment, including the ability to bind web components to objects.
US09542157B2	Random number generator and method for generating random numbers A random number generator for generating random numbers using a solid-state memory is proposed. The random number generator includes a determination unit for determining management data stored in the solid-state memory and for managing the solid-state memory during operation. The random number generator also includes a computing unit for calculating a starting value on the basis of the determined management data. The random number generator also includes a generation unit for generating a random number on the basis of the calculated starting value.
US09542155B2	Proxy calculation system, method, request device and program thereof Where G and H are cyclic groups, M is an integer of two or more, i=1, . . . , M, f is a homomorphic function of mapping a member xi of group H to group G, Ri and R0 are random variables with a value in group G, ri is a realized value of the random variable Ri,, r0 is a realized value of the random variable R0, and ai is a random number of an integer of 0 or more, a random number generation unit 11 generates random numbers a1, a2, . . . , aM. A sampler 21 is capable of calculating f(x1)r1, f(x2)r2, . . . , f(xM)rM to obtain a calculation result thereof as z1, z2, . . . , zM, respectively. A power calculation unit 12 calculates (z1)a1, (z2)a2, . . . , (zM)aM. An extended randomizable sampler 22 is capable of calculating f(x1a1×x2a2× . . . ×xMaM)r0 to obtain a calculation result z0 thereof. A determination unit 16 determines whether or not (z1)a1×(z2)a2× . . . ×(zM)aM=z0.
US09542154B2	Fused multiply add operations using bit masks Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.
US09542150B2	Controlling audio players using environmental audio analysis A method, system, and computer program product containing instructions for analyzing audio input to a receiver coupled to an audio player to identify an audio event as one of a plurality of pre-determined audio event types. In response to identifying the audio event, the audio player is caused to adjust an audio output. Adjusting the audio output may include causing the audio player to pause playing audio output or to lower the volume of the audio output. The audio input to the receiver may be recorded. In response to identifying the audio event, the audio player may be caused to replay a recorded portion of the audio input. The recorded portion of the audio input may include a portion recorded prior to identifying the audio event.
US09542149B2	Method and apparatus for detecting audio sampling rate It is inter alia disclosed to receive a set of encoded audio parameters for an audio frame, wherein the set comprises indices representing at least two quantized line spectral frequency coefficients, wherein the audio frame when decoded comprises audio samples digitally sampled at a sampling frequency, wherein the sampling frequency is one of a plurality of sampling frequencies for an audio decoder; to convert the indices to the at least two quantized line spectral frequency coefficients; and to determine the sampling frequency for the audio frame by checking the value of a highest order quantized line spectral frequency coefficient of the at least two quantized line spectral frequency coefficients.
US09542148B2	Adapting a user interface of a remote desktop host An apparatus and method are presented for adapting a user interface of a remote desktop host. The apparatus includes a processor, a memory, a detection module and an adaptation module. The detection module detects a remote desktop connection between a remote client and a host. The remote client and the host may have different user interface characteristics. The adaptation module adapts a user interface of the host to accommodate user interface characteristics of the remote client.
US09542145B2	Dynamic user interface for device management system Tools are provided for managing information technology (IT) devices in an IT environment in which at least some of the devices are connected to a network, and device information is presented to a user in a dynamic, manageable and informative manner. The device information presented may be on a global or enterprise-wide scale, or drilled down to a more specific level, geographically or otherwise.
US09542134B2	Terminal device and printer A terminal device may send a registration request to a print intermediation server. The registration request may cause the print intermediation server to register virtual printer related information. The terminal device may receive authentication information from the print intermediation server. The terminal device may send image data related information to the print intermediation server. The image data related information may be related to target image data representing a target image of a print target. The image data related information may be associated with the virtual printer related information and the authentication information in the print intermediation server. The terminal device may send the authentication information to an actual printer. The authentication information may be used by the actual printer to obtain target print data. The target print data may be data which is created from the target image data by the print intermediation server.
US09542131B2	Image forming apparatus for retrieving print data using an address of the stored print data A printing apparatus which communicates with a data providing apparatus includes a printing mechanism which executes a printing operation. The printing apparatus receives a number of print copies, and acquires print data from the data providing apparatus by executing a request processing of transmitting to the data providing apparatus a data request of the print data, and a reception processing of receiving the print data from the data providing apparatus. When executing a printing operation of N copies (N is an integer of 2 or larger), the acquiring executes, for each copy, the request processing and the reception processing to acquire the print data from the data providing apparatus while executing the request processing of the print data of M-th copy (M is an integer of 2 or larger and N or smaller) after the reception processing of the print data of (M−1)-th copy is completed.
US09542130B2	Mask based toner reduction Systems and methods for reducing toner usage. A print job is received into a print engine. The print engine comprises a processor, and the print job comprises an image. A halftone screen is applied to the pixels of continuous image data for the image. The processor produces a threshold array of pixel values based on the halftone screen. The processor generates a mask based on the halftone screen for each color plane of the image. The processor applies the mask to the threshold array, creating a modified threshold array. The modified threshold array corresponds to relatively reduced toner usage for rendering the image.
US09542129B2	Printing apparatus and method of controlling the same, and storage medium There are provided a printing apparatus which holds a job, determines whether attribution information of a sheet to be used by the stored job is registered for a sheet storage unit, judges whether a sheet exists in a sheet storage unit to be used by the job, and notifies a result of the determination and a result of the judgment.
US09542127B2	Image processing method and image processing apparatus A page containing a large number of graphics and therefore having a high process load can be processed in parallel and quickly by dividing an edge extraction process into a plurality of threads. In this case, if the number of cores is eight, the edge extraction process is performed by allocating four cores to one of regions obtained by dividing a page and the remaining four cores to the other region.
US09542126B2	Redundant array of independent disks systems that utilize spans with different storage device counts for a logical volume Methods and structure are provided for defining span sizes for Redundant Array of Independent Disks (RAID) systems. One embodiment is a RAID controller that includes a control system and a span manager. The control system is able to identify storage devices coupled with the controller and is able to receive input requesting the creation of a RAID logical volume. The span manager is able to define multiple RAID spans to implement the volume, each span comprising one or more of the coupled storage devices, at least one of the spans including a different number of drives than at least one other span.
US09542125B1	Managing data relocation in storage systems A method is used in managing data relocation in storage systems. Data relocation elapsed time is determined in a storage system. The data relocation elapsed time indicates time taken to relocate data of storage objects in the storage system. Based on the determination, relocation of data is effected in the storage system. Effecting relocation of the data includes adjusting relocation of the data of a set of storage objects. The number of storage objects in the set of storage objects is changed based on the data relocation elapsed time.
US09542122B2	Logical block addresses used for executing host commands A logical block address space of a storage compute device is reserved for use in executing commands from a host. The logical block address space is not mapped to a physical address space. First data is received at a first portion of the logical block address space, the first data causing a computation to be performed by the storage compute device. Second data is sent to the host via a second portion of the logical block address space, the second data describing a result of the computation.
US09542120B2	Systems and methods for processing instructions while repairing and providing access to a copied volume of data A volume of data is copied from a first location to a second location. A procedure to repair a volume of data is initiated. A first instruction associated with the repair procedure is selectively redirected to a staging storage, based on a determination that the first instruction relates to an action that makes a change to the volume. A second instruction is selectively redirected to one of the staging storage and the volume, based on data stored in the staging storage.
US09542119B2	Solid-state mass storage media having data volumes with different service levels for different data types Methods for providing non-volatile solid-state mass storage media with different service levels for different types of data associated with different applications. The method includes partitioning the non-volatile solid-state mass storage media into at least first and second volumes, individually assigning different service levels to the first and second volumes based on a type of data to be stored in the first and second volumes and based on the first and second volumes having different data retention requirements and/or data reliability requirements, and then performing service maintenance on data stored within at least the first volume according to the service level of the first volume.
US09542116B2	Direct attached storage system and method for implementing multiple simultaneous storage schemes A direct attached storage (DAS) system configurable to simultaneously implement a plurality of data storage schemes, comprising one or more storage devices, a controller coupled to the storage devices for implementing and managing a plurality of data storage schemes on the storage devices, an I/O port for inputting data to and outputting data from the storage devices, and an apportionment selector coupled to the controller for selecting a portion of the storage devices to be allocated to a determined data storage scheme.
US09542113B2	Apparatuses for securing program code stored in a non-volatile memory An embodiment of an apparatus for securing program code stored in a non-volatile memory is introduced. A non-volatile memory contains a first region and a second region. Two NVMMCS (non-volatile memory management controllers) are respectively coupled to the two regions. A programming command-and-address decoder is coupled to the NVMMCS. The programming command-and-address decoder instructs the first NVMMC to erase data from the first region when receiving a command to erase the first region via a programming interface, and instructs the second NVMMC to erase data from the second region when receiving a command to erase the second region via the programming interface.
US09542112B2	Secure cross-process memory sharing Techniques for enabling secure cross-process memory sharing are provided. In one set of embodiments, a first user process executing on a computer system can create a memory handle representing a memory space of the first user process. The first user process can further define one or more access restrictions with respect to the memory handle. The first user process can then transmit the memory handle to a second user process executing on the computer system, the memory handle enabling the second user process to access at least a portion of the first process' memory space, subject to the one or more access restrictions.
US09542102B2	Stacked memory devices, systems, and methods Memory requests for information from a processor are received in an interface device, and the interface device is coupled to a stack including two or more memory devices. The interface device is operated to select a memory device from a number of memory devices including the stack, and to retrieve some or all of the information from the selected memory device for the processor. Additional apparatus, systems and methods are disclosed.
US09542101B2	System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules A data storage system and methods for managing data to be transferred between a host and a data volume distributed across solid state storage modules are disclosed. A storage controller couples the host to the data volume and manages data transfers to and from the logical volume. The storage controller receives a set of parameters that define how an array of blocks and chunks of buffered data will be distributed across solid state storage modules. The storage controller receives and buffers data to be stored and transfers the same when the capacity of the buffered data will fill a set of arranged stripes in the defined array in a single write operation.
US09542100B2	Management of memory pages In a method for managing memory pages, responsive to determining that a server is experiencing memory pressure, one or more processors identifying a first memory page in a listing of memory pages in the server. The method further includes determining whether the first memory page corresponds to a logical partition (LPAR) of the server that is scheduled to undergo an operation to migrate data stored on memory pages of the LPAR to another server. The method further includes, responsive to determining that the first memory page does correspond to a LPAR of the server that is scheduled to undergo an operation to migrate data, determining whether to evict the first memory page based on a memory page state associated with the first memory page. The method further includes, responsive to determining to evict the first memory page, evicting data stored in the first memory page to a paging space.
US09542095B2	Display control device, display control method, and recording medium Provided is a display control device including a display controller which generates a control signal for controlling a display part in such a manner that a boundary line between a content display region and a region adjacent to the content display region has a wave-like shape and the boundary line is displayed while being fluctuated with progress of time, and an output part which outputs the control signal to the display part.
US09542094B2	Method and apparatus for providing layout based on handwriting input A method and an apparatus are provided for providing a layout based on a handwriting input. A first input is received from a user. The first input includes handwriting data. A layout is created based on the handwriting data. A second input is received from the user. Content of the second input is arranged in the created layout.
US09542093B2	Methods and apparatus for providing partial modification of a digital illustration A graphical user interface (GUI) including an illustration can be rendered. In response to receiving a signal from an input device indicating a location within the illustration, a layer can be defined. When the layer is applied to the illustration, the GUI can be updated such that a portion of the illustration under a filter is displayed as an altered feature. The filter can overlay the indicated location. In some embodiments, another portion of the illustration different from indicated location may not be filtered. Similarly stated, only a portion of the layer can include the filter and/or the layer may not overlay the entire illustration. A signal can be received from the input device indicating a use of the tool on the layer and, in response, the altered feature can be modified.
US09542092B2	Prediction-based touch contact tracking In embodiments of prediction-based touch contact tracking, touch input sensor data is recognized as a series of components of a contact on a touch-screen display. A first component of the contact can be identified, and a second component can be determined to correlate to the contact. The first component and the second component can then be associated to represent a tracking of the contact. Subsequent components of the contact can be determined and associated with the previous components of the contact to further represent the tracking of the contact.
US09542085B2	Universal console chassis for the car Methods and systems for a complete vehicle ecosystem are provided. Specifically, systems that when taken alone, or together, provide an individual or group of individuals with an intuitive and comfortable vehicular environment. The present disclosure includes a universal chassis that may be mounted in the head unit of a vehicle. The chassis may accept one or more modules that each have common dimensions. With a common form factor, the universal chassis is configurable as different modules with different functionality may be inserted into the chassis with ease.
US09542083B2	Configuration responsive to a device Various features described herein may include updating settings on a device in response to a themed cover being placed on a device (e.g., a remote control) associated with the device. The settings may be updated to correspond to a theme of the themed cover. Alternatively or additionally, the device may receive access to different content based on the theme. For example, a device may receive filtered content in response to a child-themed cover. In another example, the device may receive additional football-related content in response to a football-themed cover. The device may revert to its original settings and content access in response to the remote control being removed from the themed cover. In some embodiments, a device may update settings or content access in response to other themed devices (e.g., wearable devices) being within a threshold distance of the device.
US09542082B1	Systems and methods for matching, naming, and displaying medical images A method of matching medical images according to user-defined matches rules. In one embodiment, the matched medical images are displayed according user-defined display rules such that the matched medical images may be visually compared in manner that is suitable to the viewer's viewing preferences.
US09542081B2	Methods and apparatuses for operating a data processing system Methods and apparatuses for operating data processing systems. One exemplary method of operating a data processing system which includes a display device includes receiving an input from a user, the input specifying an object to be represented in a user configurable portion of a window which is displayable on a display device, and displaying the window with the user configurable portion wherein the user configurable portion is present in an open interface window or a save interface window. Other methods are also described, and data processing systems are also described.
US09542071B2	System for inline expansion of social network content and method therefor A device, system, and method may variously include a network interface device communicatively coupled to a user interface and a processor, coupled to the network interface device, configured to cause the user interface to display a newsfeed including social network content items, the newsfeed being configured to scroll to display ones of the social network content items on the user interface. At least one of the content items includes a title and content. The content item is configurable in an expanded state corresponding to displaying all of the content of the content item upon a user selection and a contracted state corresponding to displaying a sub-portion of the content. The newsfeed is configured to display the content items in the contracted state upon the social network content item scrolling onto the user interface without respect to the content item being in an expanded state when previously displayed.
US09542067B2	Panel system for use as digital showroom displaying life-size 3D digital objects representing real products Electronic panel system, an arrangement and methods for providing enriched visualization possibilities and user-controlled interaction experience with life-size and real-looking 3D models of real objects are provided. The arrangement comprising a virtual product assistant sub-system and the electronic panel system facilitates receiving real-time product information related to current state of 3D model representing real object displayed on the electronic panel system. Advanced user-controlled interactions with the displayed 3D model is made possible to perform deletion interaction, addition interaction, immersive interactions, linked movement interactions, interaction for getting un-interrupted view of internal parts using transparency-opacity effect, inter-interactions, liquid and fumes flow interactions, extrusive and intrusive interactions, time bound changes based interactions, environment mapping based interactions and engineering disintegration interactions with the displayed 3D model. The 3D model displayed is preferably a life-size 3D model, which can be further zoomed to view detailing without any blurring.
US09542066B2	Window grouping A framework is provided for obtaining window information. The window information can be applied to different assignment models to assign windows to different groups. A group may correspond to a task being performed by a user. The window information can be semantic or temporal information captured as window events and properties of windows whose events are captured. Temporal information can be information about switches between windows. Semantic information can be window titles. Temporal information, semantic information, or both, can be used to assign windows to groups.
US09542065B2	System and method of skinning themes A mobile communication device and non-transitory computer readable memory is provided. A processor executes instructions to provide a parser for parsing at least one skinning theme document into a template describing rendering characteristics of a graphical interface, the skinning theme document identifying at least one data element. The instructions also provide an interaction interface for receiving from data from at least one application associated with one or more of the at least one data element. A renderer is provided for rendering the received data on a display in accordance with the template as the graphical interface wherein the graphical interface presents one or more data elements of the at least one application that is rendered.
US09542063B1	Managing alert thresholds A method is used in managing alert thresholds. An integrated slider settings dialog is provided. An existing setting for the severity of an alert threshold is displayed by the dialog. A user is allowed to view and change the setting for the severity of the alert threshold by hovering over a slider thumb.
US09542060B1	User interface for access of content User interfaces for selecting content for presentation or other actions is described in this disclosure. Using a small number of input controls a user may quickly and easily navigate content available for presentation from one or more content providers. Additional information may be presented to the user to facilitate selection of the content. Users may select content using one or more of a graphical user interface, or voice input.
US09542059B2	Graphical symbol animation with evaluations for building automation graphics Automation systems, methods, and mediums. A method includes identifying a value for a data point associated with a device in a building. The value is received from a management system operably connected to the device. The method includes mapping the value for the data point to a graphical representation of the value for the data point. The method includes generating a display comprising a graphic for the building and a symbol representing the device. The method includes displaying the graphical representation of the value for the data point in association with the symbol representing the device. Additionally, the method includes modifying the graphical representation of the value based on a change in the value in response to identifying the change in the value from the management system.
US09542058B2	System and method for interactive competitive release board A method and system for manipulating data that includes accessing content data related to an upcoming event that is scheduled for release. A data record for the event is generated from information about the event such as day and month of release. A first representation of the event release information is displayed on a display module such as a monitor so that position of the release information relates to the date of release. The first representation may then be accessed to display additional data and the position of the event release may change based on changes to the event.

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