| Document | Document Title |
|---|---|
| US09544057B2 |
Interconnect structure for E/O engines having impedance compensation at the integrated circuits' front end
The present invention relates to an interconnect structure for coupling at least one electronic unit for outputting and/or receiving electric signals, and at least one optical unit for converting said electric signals into optical signals and/or vice versa, to a further electronic component. The interconnect structure comprises an electrically insulating substrate (102) and a plurality of signal lead pairs (104, 120) to be coupled between said electronic unit (108, 116) and a front end contact region (106) for electrically contacting said interconnect structure by said further electronic component. A ground plane layer (118) is electrically insulated from said pairs of signal leads (104, 120), wherein each pair of signal leads (104, 120) has a circuit connecting region (122) for electrically contacting respective terminals of said at least one electronic unit (108, 116), and wherein in a region adjacent to said terminals of said at least one electronic unit (108, 116) said ground plane layer (118) has a plurality of clearances (126) that are each allocated to one pair of signal leads (104, 120) and separated from a respective neighboring clearance. |
| US09544055B2 |
Optical network element
A method for operating an optical network element is provided, wherein based on a quality parameter a subsequent set of parameters is selected to operate the optical network element. Also, an according optical network element and a communication system comprising at least one such optical network element are suggested. |
| US09544050B2 |
Optical supervisory channel
A supervisory channel is provided on an optical path (31) between nodes of an optical communication network. The nodes are arranged to use a set of wavelengths allocated for carrying traffic channels. An optical signal (16) which carries a supervisory channel is generated at a supervisory channel transmitter (15) and added (12) to the optical path (31) downstream of an optical amplifier (11). The optical signal (16) has a wavelength which is one of the set of wavelengths allocated for carrying traffic. The method is performed at a time when the wavelength is not being used to carry traffic. An impairment parameter of the received optical signal is measured at a supervisory channel receiver (15). The receiver is a coherent receiver and the impairment parameter is chromatic dispersion or polarization mode dispersion. |
| US09544049B2 |
Fibre network comprising sensors
Fiber network for interrogating fiber-optic sensors in a first Passive Optical Network (PON) and in a second PON, the fiber network comprising a test signal transceiver for emitting query signals and for receiving response signals, a first PON and a second PON. Each PON comprises a light source for generating telecommunication signals and a fiber-optic sensor. Each PON can transmit the telecommunication signals to a plurality of subscribers, and is optically connected to the test signal transceiver such that the query signals can be fed into the respective PON and propagate in the PON to the fiber-optic sensor, and such that the test signal transceiver can receive response signals from the fiber-optic sensor through the PON. The fiber network further comprises a query signal splitter, optically connected to the test signal transceiver and to the PONs such that it can feed a query signal into the PONs simultaneously, and such that it can feed response signals from the PONs into the test signal transceiver. |
| US09544048B2 |
System and method for persistent wireless docking
Various aspects of the present disclosure enable a persistent docking procedure that, once a persistent docking environment has been established, can simplify the future establishment of a docking environment between the dockee and docking host. Other aspects, embodiments, and features are also claimed and described. |
| US09544047B2 |
System and method to prevent misuse of aircraft messages
An avionics system allows aircraft to introduce bogus “ADS-B Out” messages that are recognized as false only by authorized users. The system enables aircrafts flying at low altitudes to prevent misuse of their ADS-B Out information by maliciously operated cyber and physical attack tools. Aspects of the illustrative embodiment include the system architecture, including an Airborne ATC Processor and Ground ATM System Processor; a process employed by aircraft for generating authorized bogus ADS-B Out messages; a process employed by aircraft for transmitting authorized bogus ADS-B Out messages; and a process employed by air traffic control and other aircraft for decoding the authorized bogus ADS-B Out messages. |
| US09544046B2 |
Systems and methods for adaptive repeaters
In some embodiments, a first RF signal is received at a wireless repeater, a signal quality is determined based on the first RF signal, the signal quality is analyzed based on a parameter, an operation mode is auto selected based on analysis of the signal quality, and a second RF signal based on the first RF signal is generated for transmission according to the selected operation mode. Under one mode, a first RAC of the wireless may generate data based on a first IF signal downconverted from a first RF signal. Based on the data, a second RAC of the wireless repeater may generate a second IF signal, which can be used to generate a second RF signal for transmission. Under another mode, the first RAC may provide the IF signal to the second RAC, which provides the IF signal for generation of the second RF signal. |
| US09544041B2 |
Independent and concurrent automatic gain control for wireless communication and spectral intelligence
A set of receiver path circuits is allocated for processing a radio-frequency (RF) signal provided by receive antennas coupled to the receiver path circuits. The RF signal may belong to a first signal class, such as Wi-Fi. A first gain control signal is applied to each of the allocated receiver path circuits to condition a signal level of the RF signal for the first signal class. A second gain control signal is applied to another set of receiver path circuits coupled to the receive antennas to condition the RF signal of a second signal class. First receive gain control signals are generated from the RF signals of the first signal class by the allocated set of the receiver path circuits. The first receive gain control signals are configured to optimize the signal level for processing the first signal class. A second receive gain control signal is generated to optimize the signal level of the RF signal for the second signal class. |
| US09544040B2 |
Single antenna sharing for multiple wireless connections
A wireless device includes: a first radio and first transceiver configured to transmit and receive according to a first radio access technology; a second radio and second transceiver configured to transmit and receive according to a second radio access technology; a first antenna and a second antenna connected to the first radio and the second radio; a switch; and a control unit configured to control the switch to configure connections of the first and second antennas to the first and second radios. The control unit is configured to control the switch to disconnect the second radio from the second antenna in response to a receiving, by the second radio through the second antenna, a signal that is below a predetermined threshold, and to connect the second radio to the first antenna during a wakeup period of the second radio. |
| US09544039B2 |
Method and apparatus for implementing signal quality metrics and antenna diversity switching control
A method for detecting the digital quality of a radio signal includes: receiving a radio signal including an analog modulated portion; digitally sampling an analog modulated portion of the radio signal to produce a plurality of samples; using a ratio between an average magnitude and an RMS magnitude of a block of the samples to compute an analog signal quality metric. Receivers that implement the method are also provided. |
| US09544037B2 |
Method and apparatus for interference cancellation
A method and apparatus for performing interference cancellation is disclosed. The method includes receiving information about an interference configuration set related to characteristic of an interference signal, receiving an interference sequence signal indicating one interference configuration of the interference configuration set, and performing cancellation of the interference signal using the indicated interference configuration, wherein the interference sequence signal is received in at least a portion of a channel state information-interference measurement (CSI-IM) resource, and the interference sequence signal is received from an interference base station (BS) when the interference signal is scheduled to transmit and corresponds to the interference sequence signal. |
| US09544034B2 |
System and method for multiplexing control and data channels in a multiple input, multiple output communications system
A system and method for system and method for multiplexing control and data channels in a multiple input, multiple output (MIMO) communications system are provided. A method for transmitting control symbols and data symbols on multiple MIMO layers includes selecting a first set of codewords from Ncw codewords, distributing control symbols onto the first set of layers, placing data symbols of the first set of codewords onto the first set of layers, placing data symbols of the (Ncw−Ncw1) remaining codewords to remaining layers if Ncw>Ncw1, and transmitting the multiple MIMO layers. The first set of codewords is associated with a first set of layers from the multiple MIMO layers, and the Ncw codewords are to be transmitted simultaneously and the first set of codewords comprises Ncw1 MIMO codewords, where Ncw and Ncw1 are integers greater than or equal to 1. The remaining layers are MIMO layers from the multiple MIMO layers not in the first set of layers. |
| US09544029B2 |
Method for antenna array with steerable spotlight beams
Cellular array implementations with multiple steerable spotlight beams irradiated from a common aperture are disclosed herein. Such an approach can easily be adapted to suit various geographical population densities and distributions. The array is capable of producing multiple 65-degree cellular coverage beams, which may be used for regular coverage or in MIMO (Multiple Input Multiple Output) mode. The array may also produce multiple steerable beams, or “spotlight” beams. These beams may be relatively narrow and may be steered electronically both in azimuth and elevation directions. By steering the beams in this way, the beams are able to provide cellular services at high-demand “hotspot” regions where high capacity service is required. The spotlight beams may also be used to fill voids or deficiencies caused by regular coverage beams. |
| US09544028B2 |
Doppler frequency shift compensation for wireless communication
Technologies and implementations for Doppler frequency shift compensation are generally disclosed. |
| US09544024B2 |
Wireless power receiving device and wireless power transmission device
A wireless power receiving device includes a voltage detection unit that detects an output voltage value of a rectifying unit, a power reduction unit that includes a switching element connected to a charging unit in parallel, and a control unit that controls operations of the switching element. In a case where the output voltage value detected by the voltage detection unit exceeds a first reference voltage value set in advance, the control unit controls and turns the switching element on by applying a voltage to the switching element, and controls the value of the voltage to be applied to the switching element so that the difference between the voltage value calculated on the basis of a current flowing in the switching element and a second reference voltage value set in advance decreases. |
| US09544020B2 |
NFC negotiated pairing
A mobile device includes a transceiver for performing wireless communication, a microprocessor for operating said mobile device, a near field communications (NFC) system for performing wireless communication independent of the transceiver and at a lower amount of power than said transceiver, a contactless front end included in the NFC system for receiving or transmitting signals with an NFC capable device, and a pairing system implemented in the microprocessor for pairing one NFC capable device with another NFC capable device. The pairing system configures the mobile device to receive a tag or a device driver from one of the NFC capable devices that are to be paired with each other; and transfers the tag or a device driver obtained from the tag to the other of the NFC capable devices in order to enable interoperation between the two NFC capable devices. |
| US09544019B1 |
Systems and methods for ripple communication decoding
The embodiments described herein provide devices and methods to facilitate ripple control communication. Specifically, the embodiments provide devices and methods for decoding ripple control data from ripple signals, such as ripple signals that have been superimposed over power signals used to transmit power. These embodiments provide devices and methods that use band-pass filter, signal multiplier, fast and slow low-pass filters, and accumulate a difference between outputs of these slow and fast low-pass filters. This accumulated difference is then used to decode the ripple control data. |
| US09544017B2 |
Powerline communicated load control
A system for transmitting communication signals, the system comprising an injector circuit connected to a powered circuit conductor and configured to modulate a power signal with a direct current voltage offset, the direct current voltage offset being within a range that causes approximately 1 percent or less total harmonic distortion of the power signal; and a decoder connected to the powered circuit conductor and a load, the decoder configured to demodulate the direct current voltage offset to control the load. A method for transmitting communication signals, the method comprising modulating a power signal on a powered circuit conductor with a direct current voltage offset, the direct current voltage offset being within a range that causes approximately 1 percent or less total harmonic distortion of the power signal; and demodulating the direct current voltage offset to control a load. |
| US09544016B2 |
Power line communications using frame control data blocks for data transport
Method, systems, and apparatus include a communication device configured to receive a data unit in accordance with a power line communications protocol, to extract data within the data unit to provide extracted data, and to process the extracted data in accordance with a non-power line communication protocol. Embodiments also describe a communication device configured to format data according to a non-power line communication protocol as part of a data unit conforming to a power line communication protocol, to redundantly encode the data unit across a plurality of subcarriers in accordance with the second communication protocol, and to transmit the data unit in accordance with the second communication protocol to another communications device. |
| US09544013B2 |
Channel encoding based on temporal spreading of input block
Aspects of the present disclosure aim at providing a channel encoder configured to implement a temporally spreading coding scheme, wherein each bit of duration ‘T’ from a block of k bits is spread in time domain to ‘k times T’ i.e., k*T duration by means of one or more orthogonal codes. In an aspect, orthogonal codes of the present disclosure can be constituted from a sequence of discrete or digital values such that spreading (using convolution operation) and dispreading or concentrating or reconstruction (using de-convolution operation) of transmitted bit is unique and deterministic. Discrete values could be from Gaussian waveform or truncated Gaussian waveform. Digital values could be 1 (one) and 0 (zero). |
| US09544008B2 |
Integrated circuit
Wireless communication wherein channel estimation accuracy is improved while keeping the position of each bit in a frame, even when a modulation system having a large modulation multiple value is used for a data symbol. An encoding operation encodes and outputs transmitting data (bit string) and a bit converting operation converts at least one bit of a plurality of bits constituting a data symbol to be used for channel estimation, among the encoded bit strings, into ‘1’ or ‘0’. A modulating operation modulates the bit string inputted from the bit converting operation by using a single modulation mapper and a plurality of data symbols are generated. |
| US09544006B2 |
Transmission device with mode division multiplexing and methods for use therewith
Aspects of the subject disclosure may include, for example, a transmission device that includes at least one transceiver configured to modulate data to generate a plurality of first electromagnetic waves. A plurality of couplers are configured to couple at least a portion of the plurality of first electromagnetic waves to a transmission medium, wherein the plurality of couplers generate a plurality of mode division multiplexed second electromagnetic waves that propagate along the outer surface of the transmission medium. Other embodiments are disclosed. |
| US09544001B1 |
Sending and receiving messages using target criteria other than a network identifier
A system, method and a computer program product for performing the method are provided. The system includes a communication device installed in a vehicle, wherein the communication device is configured to receive a wireless network broadcast message including target criteria other than a network identifier, and output the broadcast message to a user if the communication device satisfies the target criteria. The method includes determining a current location of a first mobile communication device, and the first device sending a message containing target criteria associated with a target vehicle over a wireless data network, wherein the target criteria does not include a network identifier. The method further includes broadcasting the message containing the target criteria over a geographically-specific area including the current location of the first mobile communication device, wherein only a second mobile communication device satisfying the target criteria will receive and display the message. |
| US09543998B2 |
Systems, methods, and devices for managing coexistence of multiple transceiver devices using bypass circuitry
A communications apparatus includes a first and second transceiver, and a first and second antenna. The communications apparatus further includes a front end module (FEM) coupled between the first transceiver and the first antenna, and includes an amplifier for amplifying signals received by the first antenna, and a bypass line. The FEM is configured to couple the first antenna to the first transceiver via the bypass line when the second transceiver is active and transmitting signals using the second antenna such that a signal received via the first antenna is not amplified by the amplifier prior to being passed to the first transceiver. Furthermore, the FEM is configured to couple the first antenna to the first transceiver via the amplifier when the second transceiver is not transmitting signals using the second antenna such that a signal received via the first antenna is amplified. |
| US09543997B2 |
System and method for a mixer
In accordance with an embodiment, a circuit includes a mixer having a signal input port, a local oscillator input port and an output port, a lowpass filter circuit having an input coupled to the output port of the mixer and a terminal configured to be connected to a shunt capacitor, and a difference circuit having a first input coupled to the output port of the mixer, and a second input coupled to an output of the lowpass filter. The output of the difference circuit substantially rejects a DC signal component at the output port of the mixer. |
| US09543995B1 |
Analog front end receivers with resonant mixer configured to reject local oscillator harmonics
Some of the embodiments of the present disclosure provide a receiver comprising a class AB common-gate transformer-based low noise transconductance amplifier (LNT) configured to receive an electromagnetic signal, a passive resonant mixer electrically connected to (i) an output port of the class AB common-gate transformer-based LNT and (ii) a local oscillator. The passive resonant mixer can be configured to reject at least one harmonic of the local oscillator. The receiver also comprises a base-band module electrically connected to an output port of the passive resonant mixer. |
| US09543993B1 |
Radio frequency interconnect
A radio frequency interconnect includes a plurality of transmitters. Each transmitter is associated with an individual carrier of a plurality of carriers. The radio frequency interconnect also includes a transmission channel communicatively coupled with the transmitters and a plurality of receivers communicatively coupled with the transmission channel. Each receiver is associated with a respective carrier. A combiner on a transmitter-side of the transmission channel is coupled with the transmitters between the transmitters and the transmission channel. A decoupler on a receiver-side of the transmission channel is coupled with the receivers between the receivers and the transmission channel. The radio frequency interconnect also includes at least one channel loss compensation circuit communicatively coupled between the plurality of transmitters and the plurality of receivers. |
| US09543992B2 |
Simulcasting MIMO communication system
A wireless multiple-input multiple output (MIMO) communication system includes signaling simulcasting. Base stations include a plurality of transmit antennas and terminals include a plurality of receive antennas to form MIMO channels. In one embodiment, a simulcasting MIMO wireless communication system includes orthogonal frequency division multiplexing (OFDM). This arrangement achieves the spectral efficiency advantages of OFDM and simulcasting. |
| US09543991B2 |
Compressed amplitude wireless signal and compression function
Compression of an input signal prior to high power radio frequency (RF) amplification and transmission is disclosed. A compression device can receive an input signal and generate a compressed signal that can be passed to an amplification stage to reduce intermodulation effects. The compression device can further generate compression information that can be transmitted to enable a mobile device receiving an amplified version of the compressed signal and the compression information to decompress the amplified version of the compressed signal. Further, a mobile device that can receive an amplified compressed signal and compression information, such that the mobile device can decompress the amplified compressed signal, is also disclosed. The disclosed subject matter can enable use of lower cost, smaller, and less complex RF amplifiers within a wireless network environment. |
| US09543986B2 |
Communication device for uplink transmission with encoded information bits and method thereof
A communication device for uplink transmission with a first type of information and a second type of information includes a demultiplexing circuit, a vector selection circuit, a permutation circuit and a Reed-Muller encoding circuit. The demultiplexing circuit generates a first group of information bits and a second group of information bits according to the first type of information and the second type of information. The vector selection circuit selects code vectors from a predetermined vector set for the first group of information bits and the second group of information bits. The permutation circuit permutes the code vectors according to the first group of information bits and according to the second group of information bits. The Reed-Muller encoding circuit encodes the first group of information bits and the second group of information bits with the permuted code vectors for providing different levels of protection. |
| US09543972B2 |
Stability controlled high frequency chopper-based oscillator
Circuitry for providing an oscillating output signal. This circuitry includes a transconductance circuit having a first input, a second input, an output. The transconductance also includes a first transistor, a second transistor, and chopping circuitry. The chopping circuitry is for alternatively connecting, in a first clock cycle phase, a first node to a first terminal of the first transistor and a second node to a first terminal of the second transistor and, in a second clock cycle phase, following the first clock cycle phase, the first node to the first terminal of the second transistor and the second node to a first terminal of the first transistor. An oscillator circuit is also included and coupled to receive voltage from the output of the transconductance circuit, wherein the oscillating output signal is responsive to an output of the oscillator circuit. Further connected to the transconductance circuit are circuitry for providing a first voltage to its first input and a frequency controlled circuit for providing a second voltage to its second input. |
| US09543965B1 |
Interposer with embedded clock network circuitry
An integrated circuit package includes an interposer with an embedded clock network formed by multiple clock trees. A die with first and second clock circuits is disposed over the interposer. At least one of the first and second clock trees is a resonant clock tree and both the first and second clock circuits may provide clock signals at different frequencies. The first clock circuit may provide clock signals at one frequency to a clock tree in the embedded clock network while the second clock circuit may provide clock signals at another frequency to another clock tree in the embedded clock tree network. |
| US09543954B2 |
Driver circuit with device variation compensation and operation method thereof
A driver circuit with device variation compensation function and an operation method thereof are provided. The driver circuit includes a pull-up switch unit, an isolating switch and a pull-down switch unit. A first terminal of the pull-up switch unit is coupled to a first voltage. A second terminal of the pull-up switch unit is coupled to an output terminal of the driver circuit. A first terminal of the isolating switch is coupled to the second terminal of the pull-up switch unit. A first terminal of the pull-down switch unit is coupled to a second terminal of the isolating switch. A second terminal of the pull-down switch unit is coupled to a second voltage. The pull-down switch unit has a device variation compensation function. |
| US09543950B2 |
High speed complementary NMOS LUT logic
A programmable logic is provided that uses only NMOS pass transistors to pass a true output signal to an internal true node and to pass a complement output signal to an internal complement node. The internal true and complement nodes are cross-coupled through PMOS transistors so that the discharge of one of the internal true and complement nodes switches on a corresponding one of the cross-coupled PMOS transistors to charge a remaining one of the internal true and complement nodes. |
| US09543946B2 |
Signal processing device without mechanical switch for on/off operation
A signal processing device includes a detection unit configured to detect an intent to use the signal processing device based on whether the signal processing device is in contact with a subject; and a power supply unit configured to supply power to operate the signal processing device based on the detected intent to use the signal processing device without using a separate ON/OFF switch to supply the power to operate the signal processing device. |
| US09543942B2 |
Method and apparatus for controlling an IGBT device
The present invention comprises a method and apparatus for controlling an IGBT device. The method comprises, upon receipt of a first and at least one further IGBT control signals, the first IGBT control signal indicating a required change in operating state of the IGBT device, controlling an IGBT driver module for the IGBT device to change an operating state of the IGBT device by applying a first logical state modulation at an input of an IGBT coupling channel, and applying at least one further modulation to the logical state at the input of the IGBT coupling channel in accordance with the at least one further IGBT control signal within a time period from the first logical state modulation, the time period being less than a state change reaction period Δt for the at least one IGBT device. |
| US09543941B2 |
Radio-frequency switches having frequency-tuned body bias
Radio-frequency (RF) switch circuits are disclosed providing improved switching performance. An RF switch system includes at least one field-effect transistor (FET) disposed between a first node and a second node, each FET having a respective gate and body. A resonance circuit connects the body of each of the at least one FET to a reference node. The resonance circuit may be configured to behave as an approximately closed circuit at low frequencies below a selected value and an approximately open circuit at an operating frequency, wherein the approximately closed circuit allows removal of surface charge from the body to the reference node. |
| US09543929B2 |
Apparatus and method for obtaining power voltage from control signals
An power voltage generating unit for a radio frequency switch includes a first input and a second input respectively configured to receive a first control signal and a second control signal, wherein the first control signal and the second control signal are configured to control which one of a plurality of paths in the radio frequency switch is enabled, and at least one output, configured to output an auxiliary voltage, derived from at least one of the first control signal or the second control signal, that is used to operate the radio frequency switch. The power voltage may be a voltage used to power an inverting circuit used to enable a selected branch as an isolation branch or shunt branch. |
| US09543927B2 |
Electronic device with switched-capacitor tuning and related method
A device comprises a first capacitor block comprising a plurality of first capacitors connected in a first configuration, a second capacitor block comprising a plurality of second capacitors connected in the first configuration, a third capacitor block comprising a plurality of third capacitors connected in a second configuration, a fourth capacitor block comprising a plurality of fourth capacitors connected in the second configuration, a first switch connected between the first capacitor block and the second capacitor block, a second switch connected between the third capacitor block and the fourth capacitor block, a third switch connected between the first capacitor block and the fourth capacitor block and a fourth switch connected between the third capacitor block and the second capacitor block. |
| US09543925B2 |
Voltage controlled impedance synthesizer
A voltage controlled impedance synthesizer providing stepwise variable impedance values according to a prescribed function of the control voltage, said synthesizer comprises of one or more two-terminal impedance modules connected in series, in each impedance module one or more essentially identical two-terminal impedance elements connected in series, a corresponding number of switches to short out by selection none to all of the impedance elements in the impedance module, and said switches being controlled by the control voltage through analog-to-digital conversion and digital processing means. The values of the impedance elements between the impedance modules in ratios being uniquely defined according to the numbers of impedance elements in the impedance modules, the voltage controlled impedance synthesizer is controlled to provide monotonic and stepwise variable impedance values. Further, through the use of the voltage controlled impedance synthesizer, other electrical parameters such as current and power can be controlled according to any prescribed functions. |
| US09543923B2 |
Crystal resonator including blank and supporting portion
A crystal resonator includes a blank and a supporting portion. The blank is cut out from a crystal parallel to a surface that includes a X″-axis and a Z″-axis respectively obtained by rotating an X′-axis and a Z′-axis by 45° around a Y′-axis in a direction from the Z′-axis toward the X′-axis. The X′-axis, the Y′-axis, and the Z′-axis are respectively obtained by rotating a crystallographic X-axis, Y-axis, and Z-axis of the crystal by equal to or more than +37° and equal to or less than 51.5° around the X-axis. The supporting portion is connected to an outer periphery of the blank at a position near an apex of the reference rectangle and where a displacement of vibration in the X″-axial direction or the Z″-axial direction becomes a local minimum when two longitudinal modes of vibration are coupled. |
| US09543919B2 |
Dual mode power amplifier control interface with a multi-mode general purpose input/output interface
In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier. |
| US09543917B2 |
Software for manipulating equalization curves
The disclosed embodiment may be a parametric equalization hardware that is coupled to computer readable memory software configured to present a command interface to a user and control the equalization hardware to manipulate the frequency, Q, and gain. Additionally, software is configured to simultaneously vary the Q and gain of an equalization curve between two preset values defined by: (1) a high gain and narrow Q (“Fire”); and (2) low gain and wide Q (“Water”). |
| US09543916B2 |
Active device which has a high breakdown voltage, is memory-less, traps even harmonic signals and circuits used therewith
An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals. |
| US09543915B1 |
Stacked active RF circuits including in-situ bias monitoring systems and methods
Systems and methods according to one or more embodiments are provided for stacked active RF circuits implemented as amplification stages in high gain phased array antenna systems. Stacked active RF circuits may be implemented, for example, as an amplification stage of an element electronic circuit. Stacked active RF circuits may be implemented, for example, as a second amplification stage to maintain amplification in a high gain phased array antenna system. In one example, a system comprises a substrate comprising a plurality of substrate layers and one or more input ports and output ports. A plurality of amplification stages comprising a plurality of amplifiers, attenuators, and phase shifters are integrated within the plurality of substrate layers, the amplification stage coupled between the input and output ports. One or more monitor circuits are coupled to the plurality of amplification stages. Additional systems and methods are also provided. |
| US09543914B2 |
Doherty amplifier structure
An integrated Doherty amplifier structure comprising; a main amplifier stage; at least one peak amplifier stage; an output combination bar configured to receive and combine an output from both the main amplifier stage and the or each peak amplifier stage; a main connection configured to connect an output of the main amplifier stage to the combination bar, the main connection comprising, at least in part, a bond wire forming a first inductance; a peak connection configured to connect an output of the peak amplifier stage to the combination bar; wherein the main connection connects to the combination bar at a first point along the bar and the peak connection connects to the combination bar at a second point along the bar spaced from the first point and the main amplifier stage is located further from the output combination bar than the at least one peak amplifier stage. |
| US09543911B2 |
Phase-modulated load apparatus and method
Methods and apparatus are provided to improve the efficiency of an outphasing amplifier through modulating the phase angle of a reflected signal in the outphasing amplifier. An outphasing amplifier includes a first amplifier and a second amplifier. A circulator is provided having a first port coupled to an output of the outphasing amplifier, a second port coupled to a load and a third port coupled to a phase shifter. The phase shifter is configured to provide a different phase angle of a reflected signal from the phase shifter to the outphasing amplifier through the circulator. |
| US09543908B2 |
Adaptive rail voltage regulation on power supplies
The system comprises a Digital Signal Processing module, a Power Supply Unit and an audio amplifier. In the Digital Signal Processing module, the level of the digital audio signal is detected for adjusting the rail voltage in the amplifier. The digital audio signal is delayed by the Digital Signal Processing module prior to transforming and feeding it into the audio amplifier for amplification in order to stabilize the rail voltage after adjustment of the rail voltage to an increased level. Further in order to decrease the power consumption, especially in battery driven amplifiers, an adjustment of the rail voltage to a reduced level is delayed by a second predetermined time length (S_Hold) of 1 to 5 seconds as this reduces the number of adjustments of the rail voltage. |
| US09543907B2 |
Current-voltage conversion amplifier circuit including multiplier with a current offset removal unit and multi input amplifier
Provided is a current-voltage conversion amplifier circuit including: a plurality of light receiving devices generating a current signal proportional to an amount of light by receiving the light; multipliers amplifying the current signal, converting the amplified current signal into a first voltage signal, outputting the amplified current signal, or outputting the converted first voltage signal; multi input amplifiers outputting first and second output voltage pairs through a process for receiving output values of multipliers and an offset voltage and amplifying the received output values and offset voltage; a multiplexing unit selecting and outputting one first and second output voltage pair among the first and second output voltage pairs outputted from multi input amplifiers; and a signal conversion unit converting a difference value between first and second output voltages outputted from the multiplexing unit and outputting the converted digital signal. |
| US09543904B1 |
Differential amplifier circuit and semiconductor memory device including same
Disclosed are a differential amplifier circuit and a semiconductor memory device including the same, wherein the differential amplification circuit includes: a differential amplifier activated in response to an enable signal, capable of differentially amplifying input signals inputted through input terminals and outputting output signals; and an operation control section capable of sequentially applying signals having a voltage difference increasing in stepped fashion to the input terminals of the differential amplifier, measuring voltages of the output signals of the differential amplifier to detect an input offset, and adjusting an activation timing of the enable signal depending on a detected offset. |
| US09543901B2 |
Optimization methods for amplifier with variable supply power
Optimization methods via various circuital arrangements for amplifier with variable supply power are presented. In one embodiment, a switch can be controlled to include or exclude a feedback network in a feedback path to the amplifier to adjust a response of the amplifier dependent on a region of operation of the amplifier arrangement (e.g. linear region or compression region). |
| US09543896B2 |
Multiple-input multiple-output low-noise block downconverter and low-noise module
A low-noise block downconverter (LNB) is disclosed. The low-noise block downconverter comprises a first input module, for outputting a first intermediate frequency (IF) signal after receiving a first polarization signal via a first input end; a second input module, for outputting a second IF signal after receiving a second polarization signal via a second input end; a first output module, coupled to the first input module, for amplifying the first IF signal; and a second output module, coupled to the second input module, for amplifying the second IF signal, such that the LNB selectively outputs a first user signal or a second user signal. |
| US09543895B2 |
Circuit configuration using a frequency converter to achieve tunable circuit components such as filters and amplifiers
A frequency converting circuit including: an impedance network having a first pair of terminals and operable to provide a first signal in a frequency band centered at a first frequency f1; an output network having second and third pairs of terminals and configured to pass, between the second and third pairs of terminals, a second signal in a frequency band centered at a second frequency f2 different from f1; a pump circuit having a fourth pair of terminals and operative to provide, at the fourth pair of terminals, a third signal at a pump frequency fp, where fp?f1 and f2; and a frequency converter having a first port connected to the first terminals, a second port connected to the second terminals and a third port connected to the fourth terminals, the frequency converter being operative to cause the difference between f1 and f2 to be equal to fp. |
| US09543893B2 |
Method and system for frequency generation
Methods and systems for frequency generation may comprise a circuit with a first input coupled to receive a first satellite signal at a first satellite downlink frequency, a second input coupled to receive a second satellite signal at a second satellite downlink frequency, and a first analog-to-digital converter (ADC) having an input coupled to receive the first satellite signal and an output. The first ADC may be configured to create a first digital output signal representing the first satellite signal. A second ADC having an input coupled to receive the second satellite signal and an output may be configured to create a second digital output representing the second satellite signal. The circuit may comprise a dielectric resonator oscillator having an output and a clock generator circuit having an input coupled to the oscillator output and configured to output one or more clocks used by the first and second ADCs. |
| US09543888B2 |
Frameless solar module mounting
In an example, a clamp assembly for a glass on glass solar module for a tracker is included. The assembly has a lower clamp structure characterized by a top-hat shaped rail structure having a length extending from a first end to a second end. In an example, the assembly has an upper clamp structure configured to sandwich a pair of edges of a pair of solar modules with a portion of the lower clamp structure. In an example, the assembly has a locking spacer configured to the pair of edges of the pair of solar modules. In an example, the pair of edges comprises substantially glass material. In an example, the assembly has a pair of key structures configured with the locking spacer. Each of the key structures is affixed to each of the solar modules to physically lock each of the solar modules to the upper clamp structure. |
| US09543887B2 |
Heat pump device, heat pump system, and method for controlling three-phase inverter
A selection unit switches between a phase θp and a phase θn different from the phase θp substantially by 180 degrees, and outputs one of them in synchronization with a carrier signal. A voltage-command generation unit generates and outputs three-phase voltage command values Vu*, Vv* and Vw* based on the phase outputted by the selection unit. A PWM-signal generation unit generates three-phase voltage command values Vu*′, Vv*′ and Vw*′ by correcting the three-phase voltage command values Vu*, Vv* and Vw* outputted by the voltage-command generation unit according to a predetermined method, and generates six drive signals corresponding to switching elements of the inverter based on the three-phase voltage command values Vu*′, Vv*′ and Vw*′ and the carrier signal. The PWM-signal generation unit outputs the generated drive signals to the corresponding switching elements of the three-phase inverter, to cause the inverter to generate a high-frequency AC voltage. |
| US09543886B2 |
Short circuit detection circuit and short circuit detection method for multi-phase rectifier at frequency domain
A short circuit detection circuit and a short circuit detection method for a multi-phase rectifier are provided, which are used for detecting conditions of a spectrum of a FWR signal outputted from the multi-phase rectifier in the frequency domain. Next, determining whether the detected signal indicating the amplitude of the frequency of the AC signal is greater than or equal to the reference signal, so as to determine whether the multi-phase rectifier has a short circuit condition. Therefore, the short circuit detection circuit and the short circuit detection method do not have any requirements for configuring a short circuit detection element on each current path of the multi-phase rectifier, so that the power loss and the cost can be reduced effectively. |
| US09543879B2 |
System and method for controlling muliphase electric motors
Controlling a multiphase electric motor by controlling the transmission of power to a first set of phases of a multiphase electric motor in accordance with a first operating configuration; detecting the presence of a shorted phase in the first set of phases while the first set of phases are being operated in accordance with the first operating configuration; and, responsive to detection of the shorted phase, adjusting control of the transmission of power to the multiphase electric motor such that power is transmitted to a second set of phases in accordance with a second operating configuration. |
| US09543877B2 |
Control apparatus for a switched reluctance motor
An apparatus for controlling a switched reluctance motor with use of a power conversion circuit. In the apparatus, a command voltage setter sets a command voltage for a coil of the motor, where the command voltage is set to change gradually during either or both of a ramp-up period and a ramp-down period of the command voltage. A voltage controller controls an applied voltage to the coil to the command voltage set by the command voltage setter by operating the power conversion circuit. |
| US09543875B2 |
Motor control device, and method and device for estimating magnetic flux of electric motor
A motor control device is provided, which includes a power converter for applying output voltage according to a voltage command to an electric motor, a magnetic flux estimator for estimating a vector of stator magnetic flux of the electric motor based on a difference between the output voltage and a voltage drop caused by a coil resistance of the electric motor, and a phase estimator for estimating a phase of the stator magnetic flux based on the vector of the stator magnetic flux estimated by the magnetic flux estimator. The magnetic flux estimator includes a variable low-pass filter for applying a low-pass filter to the difference at a cut-off frequency according to a frequency of the output voltage, and a phase adjuster for retarding at least one of an output phase of the variable low-pass filter and a phase of the difference before inputted into the variable low-pass filter. |
| US09543874B2 |
Dual alternator system
A dual alternator system includes a main alternator controlled by an electronic voltage regulator, a secondary alternator system having a secondary alternator controlled by a LIN controlled alternator voltage regulator and an electronic control unit (“ECU”) coupled to the LIN controller alternator voltage regulator by a LIN bus that that determines whether the secondary alternator should be off or operated to generate current. The ECU when it determines that the secondary alternator should be off sends a voltage setpoint signal to the LIN controlled alternator voltage regulator having a low value that is well below nominal system voltage. The ECU when it determines that the secondary alternator should be operated to provide current sends a voltage setpoint to the LIN controlled alternator voltage regulator having a high value that is well above a nominal system voltage and a MECL setpoint value. |
| US09543867B2 |
Brushless direct current motor and driving apparatus thereof
The present invention relates to driving apparatus for a brushless direct current motor, comprising: at least three half-bridge circuits, each having two switches connected in series and being configured to supply a voltage to a terminal of a rotor coil; a zero crossing detection module configured to detect whether the rotor coils experience BEMF zero crossing and provide a control module with an indication signal that indicates whether the rotor coils experience BEMF zero crossing, based on a type of the brushless direct current motor; and a control module configured to transmit to the zero crossing detection module information regarding the type of the brushless direct current motor, and generate and output, based on the indication signal, pulse width modulation signals to control the switches of the half-bridge circuits. The driving apparatus may drive a plurality of types of brushless direct current motors. |
| US09543864B1 |
Motor driving circuit with power reversal protection and fan device
A motor driving circuit with power reversal protection and a fan device are disclosed. The motor driving circuit has a supply end and a ground end. A reversal protection circuit is configured in the motor driving circuit and is electrically connected to the supply end. When a power line and a ground line of a power supply electrically and respectively connect to the supply end and the ground end (indicating a correct connection condition), the reversal protection circuit is turned on, so that the motor driving circuit receives the power transmitted from the power supply to operate. When the power line and the ground line of the power supply electrically and respectively connect to the ground end and the supply end (indicating an incorrect connection condition), the reversal protection circuit is turned off, so that the motor driving circuit does not receive the power transmitted from the power supply. |
| US09543862B2 |
Electric motor control device and electric motor control method
A current command generator 117 generates a current command that indicates a value of current supplied from an inverter circuit to electric motors connected in parallel with the inverter circuit. A voltage command calculator 120 generates a voltage compensation signal for compensating a difference between a value of actual current supplied to each of the electric motors and a value of current indicated by the current command. A determiner 135 determines, based on a value obtained from the voltage compensation signal, whether or not an abnormality is occurring in at least one of the electric motors. A shutdown controller 136 shuts down, upon the determiner 135 determining that an abnormality is occurring, the power supply from the inverter circuit to the each of the electric motors. |
| US09543858B2 |
Semiconductor device and inverter using same
A semiconductor device includes a gate pad, a first source pad and a second source pad insulated from each other, a drain pad, a main region, and a sense region for detecting a forward current and a reverse current. The main region and the sense region each include a plurality of unit cells which are in parallel connection, the number of unit cells in the sense region being smaller than the number of unit cells in the main region. A source electrode of any unit cell in the main region is connected to the first source pad, and a source electrode of any unit cell in the sense region is connected to the second source pad. |
| US09543856B2 |
Power conversion apparatus having a negative terminal of a power supply connected to one of connection nodes of a negative side bus with U-phase, V-phase and W-phase lower-arm switching elements except the end-side ones
A power conversion apparatus has a structure in which the negative terminal of an insulated power supply is connected to one of connection nodes of a negative side bus with U-phase, V-phase and W-phase lower-arm switching elements except the end-side ones. That is the negative terminal of the insulated power supply is connected to the connection node between the negative side bus and the V-phase lower arm switching element to enable suppressing variations of input voltages supplied from the insulated power supply to respective drive circuits for driving the lower-arm switching elements by using low pass filters having smaller filtering capacity and smaller size. |
| US09543851B2 |
Matrix converter
A matrix converter includes: a power converter configured to couple an AC power supply and a load together; and a controller configured to selectively execute: a first control mode in which the controller is configured to perform power conversion between the AC power supply and the load; and a second control mode in which the controller is configured to directly combine the AC power supply with the load. The controller is configured to: increase the output voltage and cause a phase of the output voltage follow up a voltage phase of the AC power supply in a case where a difference between a frequency of an output voltage from the power converter to the load and a frequency of the AC power supply becomes within a predetermined range. |
| US09543849B2 |
Power conversion apparatus, power conversion method, motor system, and three-phase motor
A power conversion method including: receiving, by a pair of input terminals, an input voltage in which is a single-phase AC voltage; designating a first target voltage ref1, a second target voltage ref2, and a third target voltage ref3 respectively representing consecutive target values of first-phase, second-phase, and third-phase output voltages forming a three-phase AC voltage; and cyclically connecting and disconnecting (i) the input terminals and first output terminals at a duty cycle corresponding to |ref1/in| when an instantaneous value of |in| is greater than an instantaneous value of |ref1|, (ii) the input terminals and second output terminals at a duty cycle corresponding to |ref2/in| when the instantaneous value of |in| is greater than an instantaneous value of |ref2|, and (iii) the input terminals and third output terminals at a duty cycle corresponding to |ref3/in| when the instantaneous value of |in| is greater than an instantaneous value of |ref3|. |
| US09543848B2 |
Activation circuit of a resonance converter
An activation circuit for activating a power bridge circuit of a resonance converter, including an inductive activation transformer that transfers a pulsed control signal generated via a CMOS driver to the power bridge circuit, wherein a clamping circuit is arranged at the output of each CMOS driver, where the clamping circuit clamps a primary winding of the activation transformer to a ground potential during the dead time between two pulses of the pulsed control signal such that overvoltages, which otherwise arise when switching the activation transformer inductance, are thus clamped during a dead time and a circuit breaker switches off securely. |
| US09543845B2 |
Generating a control signal based on leading edge dimming detection for maintaining input current of a power converter
A power converter includes an energy transfer element, a power switch, a controller and a leading edge dimming detection circuit. The controller is coupled to control switching of the power switch to regulate the output of the power converter by controlling a transfer of energy through the energy transfer element. The leading edge dimming detection circuit is coupled to generate a control signal in response to detecting leading edge dimming at the input of the power converter. In one aspect, the leading edge dimming detection circuit detects the leading edge dimming and then generates a control signal to engage a compensator which maintains the input current of the power converter to be equal to or greater than a minimum current. In another aspect, the leading edge dimming detection circuit detects and reutilizes the turn-on current spike energy of a leading edge dimmer. |
| US09543843B2 |
Power supply device
There is provided a power supply device having a primary side and a secondary side isolated from each other. The power supply device includes: a power supply unit converting power from the primary side to output the converted power to the secondary side; a control unit located on the secondary side and acquiring control information on the power supply unit based on a voltage output from the power supply unit; and a delivery unit delivering the control information to the primary side, the delivery unit including a Y-capacitor that provides an EMI noise path between the primary side and the secondary side. |
| US09543840B2 |
Method and apparatus for sensing multiple voltage values from a single terminal of a power converter controller
A controller includes a switching control coupled to switch a power switch of a power converter to regulate an output of the power converter. A sensor is coupled to receive a signal from a single terminal of the controller. The signal from the single terminal is representative of a line input voltage of the power converter during at least a portion of an on time of the power switch, and an output voltage of the power converter during at least a portion of an off time of the power switch. The switching control is responsive to an output of the sensor, and includes a first current source, an internal voltage supply coupled to the first current source, and a buffer circuit coupled to receive the signal from the single terminal. The first current source is coupled to supply a first current to the buffer circuit. |
| US09543834B2 |
Switching regulator, electronic device, and electronic circuit
There is provided a switching regulator configured to convert an input voltage into an output voltage. A control unit is configured to perform switching control in response to a result of comparison between a reference voltage and a complex voltage which includes a feedback voltage acquired by feeding back the output voltage, and a derived voltage derived on the basis of an input current. |
| US09543833B2 |
Constant on time controller
The present invention provides a constant on time controller packaged in one single package for controlling a buck converting circuit to convert an input voltage into an output voltage. The constant on time controller includes an input voltage detecting circuit, an on-time determining circuit and a driving circuit. The input voltage detecting circuit receives a bootstrap voltage to generate an input voltage detecting signal indicative of the input voltage. The on-time determining circuit receives the input voltage detecting signal and generates an on-time signal in response to the input voltage detecting signal and the output voltage. The driving circuit controls the buck converting circuit according to the n-time signal. |
| US09543832B2 |
Current detection circuit and switching regulator thereof
In one embodiment, a current detection circuit configured for a switching regulator can include: (i) a feedback controlling circuit configured to control a feedback signal to be consistent with a reference signal, and to generate a feedback control signal; and (ii) a feedback signal generator configured to receive a rise time and a fall time of inductor current of the switching regulator, and to generate the feedback signal in direct proportion with the feedback control signal. |
| US09543830B2 |
Sense current measurement in switch mode power converters
A switch mode power converter configured for operation with a plurality of outputs is disclosed. The switch mode power converter includes an inductive element and a resistance in series with the inductive element. The resistance is series with the inductive element is used for determining a current through the inductive element. The resistance is a resistance between the main terminals of a switch in an on-state. The switch have two main terminals and a control terminal and being arranged for directing current through the inductive element to a one of the plurality of outputs. |
| US09543827B2 |
Internal voltage generation circuits
An internal voltage generation circuit may include a pump controller and an internal voltage generator. The pump controller suitable for generating a first control signal enabled if a level of an internal voltage signal is lower than a target voltage level and a second control signal enabled if a level of the internal voltage signal is lower than the target voltage level after a predetermined period elapses from a point of time that the internal voltage signal is pumped. The internal voltage generator suitable for pumping the internal voltage signal with a first drivability in response to the first control signal and suitable for pumping the internal voltage signal with a second drivability in response to the second control signal. |
| US09543825B2 |
Power conversion apparatus and control method thereof
A power conversion apparatus and control method thereof are provided. The power conversion apparatus includes an output capacitor, an AC-to-DC conversion circuit, a transformer-based auxiliary circuit, an inrush suppression component and a switching circuit. The AC-to-DC conversion circuit is configured to convert an AC power into a DC power. The auxiliary circuit provides a leakage inductance energy. The inrush suppression component provides a first conduction path, and the switching circuit provides a second conduction path. When the switching circuit cuts off the second conduction path in response to the leakage inductance energy, the AC-to-DC conversion circuit conducts the DC power to the output capacitor via the first conduction path. When the switching circuit turns on the second conduction path in response to the leakage inductance energy, the AC-to-DC conversion circuit conducts the DC power to the output capacitor via the second conduction path. |
| US09543824B2 |
Active power factor correction control circuit, chip and LED driving circuit thereof
In one embodiment, an active power factor correction (APFC) control circuit, configured to generate a pulse-width modulation (PWM) control signal to control the operation of a power converter, includes: (i) an inductor current zero crossing detection circuit coupled to a common node between a power switch of the power converter and a first switch that are coupled in series, where the inductor current zero crossing detection circuit is configured to generate a comparison signal based on a voltage signal at the common node; (ii) the comparison signal being activated when an inductor current of the power converter decreases to zero; and (iii) the APFC control circuit being configured as a source driver, wherein a control terminal of the power switch is coupled to a constant voltage supply. |
| US09543821B2 |
MOSFET driver with pulse timing pattern fault detection and adaptive safe operating area mode of operation
A Safe Operating Area (SOA) adaptive gate driver for a switch mode power converter is disclosed. In response to a detection of a fault condition, the SOA adaptive gate driver may limit the peak current in a power transistor (e.g., power MOSFET) of the power converter by limiting the voltage applied to the gate of the power MOSFET or by limiting the current injected into the gate of the power MOSFET. The limited gate voltage or current may increase the margin between an SOA border and the turn-off locus of the drain voltage and current (VD and ID) to ensure safe operation of the switch mode power converter during the fault condition. |
| US09543819B2 |
Adaptive BJT driver for switching power converter
A flyback converter is provided that includes a base driver for driving a base current into a base of a BJT power switch. The base driver is controlled so as to adaptively vary the base current across at least some of the pulses. |
| US09543816B2 |
Vibration generator having swing unit, frame and elastic member
A vibrator includes a frame, a swing unit, and an elastic member. The swing unit is disposed within the frame and holds a magnet. The elastic member connects the swing unit and the frame. The swing unit is movable with respect to the frame while deforming the elastic member. The frame, the swing unit, and the elastic member are integrally molded with each other. |
| US09543813B2 |
Apparatus and methods for winding supports for coils and single poles of cores of dynamo electric machines
Apparatus and method for winding at least one electric wire W on a coil support (10) of a core of a dynamo electric by using a wire dispensing member (19) means (21, 25) for rotating the coil support with respect to the dispensing member (19). It is foreseen to provide a relative movement of the dispensing member (19) with respect to the coil support (10) to maintain the angular orientation constant during winding. Furthermore it is foreseen to press on a portion (WP) of wire wound on the coil support (10) where the portion of wire (WP) is located immediately adjacent to a portion of wire that still has to be wound on the coil support (10). Engaging occurs also of the wire portion (WP) wound on the coils support and that extends to the dispensing member (19) when passage from one turn to another occurs for the stratification; the engagement occurring in opposition to the direction (Z′) of stratification of the wire. Pressing on the wire (W) can be accomplished in a direction (K) having an angle (E) that is more than zero and not perpendicular to an axis of the coil support. |
| US09543810B2 |
Semiconductor module and driver device
A semiconductor module includes a switching element, a molded body, and a motor terminal. The molded body having the switching element disposed therein. The motor terminal has a base portion and a connection portion having an insertion hole into which a motor wire is inserted and connected with the winding wire. The connection portion has a cutaway region that defines a slot. The winding wire of the motor and the semiconductor module are connected via the motor wire and the motor terminal, thereby reducing the number of components used for such connection compared with a connection that uses a connector, and achieving a volume reduction of the semiconductor module and a driver device using the same. |
| US09543804B2 |
Electric linear drive, in particular for adjusting furniture used for sitting or lying down
An electric linear drive, in particular for adjusting moveably mounted parts of furniture used for sitting or lying down, includes a drive motor, a threaded spindle, a speed reduction gear arranged between the drive motor and the threaded spindle, a spindle nut placed on the threaded spindle, which can be selectively locked in the direction of rotation and, depending on the direction of rotation of the threaded spindle, moved in the axial direction of the threaded spindle. The linear drive has a lifting element for adjusting the moveable furniture parts, the lifting element being driven by axial movement of the spindle nut. Simple design, easy assembly and operation, and robust mounting of the driving parts are achieved. |
| US09543802B2 |
Motor drive apparatus
A motor drive control apparatus 30, on which a switching element 73 for performing drive control of the motor 10 is mounted, includes: a heat sink 50 placed on the front side or rear side of the motor; and a housing 40 that is coupled to the heat sink and couples the heat sink to the frame or that covers the switching element mounted on the heat sink, and wherein an abutment surface 110 between the housing and the heat sink is located on a single plane intersecting with the direction of the rotation axis of the motor, and screw holes 42 and 52 for coupling the frame, the heat sink and the housing to each other are provided such that the positions in the circumferential direction of the screw holes 42 and 52 correspond to each other. |
| US09543797B2 |
Cross-interlocked switch type DC electric machine having auxiliary excitation winding and conduction ring and brush
The present invention relates to a multi-set switched DC electric machine having conduction ring and brush and having its rotary part of electric machine being installed with an auxiliary excitation winding set, which is served to be driven by the DC power source or by the DC power source rectified from the AC power source, for being connected in series with a magnetic field winding set of electric machine of another electric machine through the auxiliary excitation winding set installed on the rotary part of electric machine, such that the excitation can be variable through altering the current of the magnetic field winding set of electric machine of the another electric machine thereby changing the operational characteristic of the electric machine. |
| US09543796B2 |
Motor with stepped rotor tube coupled to the inner race of a multiple-row bearing
A motor includes a stator, a rotor tube which is disposed inside the stator, a rotor core assembly which is coupled to an outer circumferential surface of the rotor tube, and a shaft which is coupled in the rotor tube. The rotor tube is divided into at least two stepped regions having different diameters. A multiple-row bearing has an inner wheel coupled to an outer circumferential surface of any one of the at least two stepped regions, and rotatably supports the rotor tube. Such a configuration ensures structural stability of the motor and minimizes a space occupied by a bearing. |
| US09543794B2 |
Motor and washing machine having the same
A motor includes an enhanced strength of a stator, the stator being formed with a plurality of core plates stacked one on top of another, and a rotor rotatably disposed at an inner side or at an outer side of the stator. Each core plate includes a body provided in a shape of an arc, a plurality of teeth radially extended from the body, and having a coil wound thereto, at least one first slit part formed on the body by being slit in a radial direction of the body, and at least one second slit part formed on the body by being slit in a circumferential direction of the body. |
| US09543793B2 |
Radial-winding stator of a motor
A radial-winding stator of a motor including a core and eight poles is disclosed. Each pole has a magnetic pole and a pole piece. The magnetic pole is connected to the core and extends outwards from the core in a radial direction. The pole piece is formed at one end of the magnetic pole distant to the core. The pole piece includes a magnetic end face having an arc length along a circumferential direction of the core, as well as an axial height along an axial direction perpendicular to the radial direction. A ratio of the arc length to the axial height is between 2.05 and 10. In another embodiment, the radial-winding stator includes ten or twelve poles. |
| US09543792B2 |
Rotary electric machine, electric motor, machine, electric generator, and electric generating machine
According to one embodiment, a rotary electric machine includes a rotor that is rotatable at a predetermined position and includes a plurality of first magnetic members arranged along an outer circumferential surface, the first magnetic members each including a first magnetic pole and a second magnetic pole. The rotary electric machine includes a first supporting member that surrounds a periphery of the rotor. The rotary electric machine includes a plurality of second supporting members that are fixed to an inner circumferential surface of the first supporting member. The rotary electric machine includes a plurality of second magnetic members that are fixed on side surfaces of the second supporting members and that have a third magnetic pole facing the first magnetic pole with an air gap and a fourth magnetic pole facing the second magnetic pole with an air gap. |
| US09543786B2 |
Portable power system
A power management system and method are disclosed. The system can be a high availability power delivery system. The system can be GPS tracked. The system can have multiple batteries, multiple input power sources, and multiple loads. The system can switch between the multiple batteries and the power source to deliver power to the load. The system can ensure there will always be an input power source to power the load. |
| US09543785B2 |
Electrical charging/discharging control apparatus, electric-power management apparatus, electric-power management method and electric-power management system
Disclosed herein is an electrical-charging/discharging control apparatus composing an electric-power accumulation facility in conjunction with an electric-power accumulation battery and including: a communication section configured to receive a command to carry out either of electrical charging and discharging operations on the electric-power accumulation battery from an electric-power management apparatus for managing the electrical charging and discharging operations carried out on the electric-power accumulation battery; a control section configured to control the electrical charging and discharging operations carried out on the electric-power accumulation battery on the basis of the command; and a power conditioner for supplying electric power from an electric-power network to the electric-power accumulation battery and transferring electric power accumulated in the electric-power accumulation battery to the electric-power network in accordance with control carried out by the control section. |
| US09543781B2 |
Apparatus for inductively transmitting electrical energy
An apparatus for inductively transmitting electrical energy from a stationary unit to a mobile unit which is located adjacent to the stationary unit. The apparatus has a coil and a flux guide unit for guiding a magnetic flux occurring during operation of the apparatus with at least one ferromagnetic body, which consists of a multiplicity of individual elements. The flux guide unit has the basic shape of a plate and is arranged on one side of the coil perpendicular to the winding axis thereof in such a way that it covers the cross-sectional area of the coil at least partially. The ferromagnetic body includes individual elements with anisotropic magnetic permeability and has, overall, anisotropic magnetic permeability. In a viewing plane perpendicular to the winding axis of the coil, the individual elements of the ferromagnetic body are aligned with respect to the coil in those regions in which a ferromagnetic body with anisotropic permeability covers winding sections of the coil, in such a way that the preferred direction of magnetic permeability, in which the magnetic permeability has its greatest magnitude in the viewing plane, is at least approximately perpendicular to the winding sections of the coil. |
| US09543777B2 |
Power supplying device and power transmission device
A power-supplying device supplies the power to a power-supplied device in a non-contact manner, without interfering with communication between the power-supplying device and power-supplied device. More specifically, the power-supplying device supplies the power to the power-supplied device in a non-contact manner, such that the error rate of wireless communication does not increase. |
| US09543776B2 |
Charging/discharging circuit for electro active polymer based variable capacitor
Electronic device (1) for charging and discharging a capacitor (10) from and to a power source (30). The electronic device is connectable to the capacitor and to the power source, and includes a first circuit (SI, D, R1, LI) for charging the capacitor and at least one second circuit (S2, D, R2, L2) for discharging the capacitor. The capacitor is connected to the first circuit in a charge line (31) and is connected to the second circuit in a discharge line (32). Both the charge line and discharge line are connectable to the power source. The first circuit is arranged as a first buck converter circuit and the at least one second circuit is arranged as a second buck converter circuit. |
| US09543769B2 |
Pop up electrical apparatus
An electric supply pop up apparatus for use in a generally horizontal surface that has three main sections, first, a permanently installed, weatherproof containment unit where the unit has a bottom, at least one side wall and an open top; second, a moveable tower that has at least one side wall and a cover; and at least one electrical receptacle module installed in said tower; the tower is slideably moveable within the containment unit so that the tower can be raised or lowered within the containment unit such that when the tower is lowered and in a down position the tower is fully secured and enclosed within the containment unit or the tower can be raised to an up position so that the electrical receptacle module is accessible to a user; and where power is available at the electrical receptacle module when the tower is in the up position. |
| US09543768B2 |
Safety device
A safety device includes a discharge device for discharging an electric energy store in response to a deformation of the energy store, that is impending or has occurred. |
| US09543766B2 |
Wireless power transmission system, and method of controlling transmission and reception of resonance power
A resonance power transmission system, and a method of controlling transmission and reception of a resonance power are provided. According to one embodiment, a method of controlling resonance power transmission in a resonance power transmitter may include: transmitting resonance power to a resonance power receiver, the resonance power having resonance frequencies which vary with respect to a plurality of time intervals; and receiving, from the resonance power receiver, information regarding the resonance frequency having the highest power transmission efficiency among the resonance frequencies used in the time intervals. |
| US09543761B2 |
Home energy control system and controlling method thereof
A method of controlling a home energy control system includes controlling the system to run in at least one of a new energy generating mode, a grid-connected inverter mode and an off-grid inverter mode after mode conflict check. In the new energy generating mode, a new energy generating unit is controlled to generate power to charge an energy storage unit. In the grid-connected inverter mode, the energy storage unit supplies power to a power grid or is charged by the power grid according to the status of the energy storage unit and power consumption of the power grid. In the off-grid inverter mode, household devices are supplied with power from the energy storage unit according to the status of the energy storage unit under the control of an off-grid inverter. A home energy control system is also provided. |
| US09543760B2 |
Power distribution circuit
A transformer (2A) outputs differential signals of a positive phase signal (Vout2Ap) having phase θ1+90° and a negative phase signal (Vout2An) having phase θ1−90°. A transformer (2B) outputs differential signals of a positive phase signal (Vout2Bp) having phase θ2+90° and a negative phase signal (Vout2Bn) having phase θ2−90°. An adding circuit (3) composes a pair of differential output signals, as signals corrected in phase error (θ1−θ2) generated in the transformers (2A, 2B), in a manner of summing up vectors of two pairs of the differential signals outputted from the transformers (2A, 2B) for the positive phase signal and the negative phase signal, respectively. |
| US09543758B1 |
Adaptive battery power distribution to remote radio heads in long term evolution (LTE) networks
A method and system are provided for adjusting power distribution to remote radio heads in a telecommunication network. Multiple buses are implemented in a configuration to individually distribute power to remote radio heads. Each bus is connected to a remote radio heads allowing the remote radio head to receive power on an individual basis and different from other remote radio heads. An eNodeB collects operational measurements from a cell site which are used to provide instructions to adjust the power to each bus and corresponding remote radio head. |
| US09543757B2 |
ESD protection circuits and methods
An electrostatic discharge (ESD) protection circuit includes a first inductor coupled to an input node configured to receive an input signal and to an output node. A second inductor is coupled to the input node and to a first ESD protection device, and a third inductor is coupled to the output node and to a second ESD protection device. |
| US09543746B2 |
Enclosure for a cable connection
The present invention is directed to an enclosure for protecting a cable connection. The enclosure includes a sealing member contained within an inner shell. The sealing member is secured around the cable connection by slideably engaging a rigid outer shell over the inner shell. The inner shell has an external topography defining an inner shell profile and wherein the outer shell has an internal topography defining an outer shell profile such that the outer shell profile is similar to the inner shell profile. |
| US09543745B2 |
Arrester bypass devices
An arrester bypass device can include a switch having an normal state and an operated state. The arrester bypass device can also include a first electrode mechanically coupled to the switch, where the first electrode is held when the switch is in the normal state and released when the switch is in the operated state. The arrester bypass device can also include a second electrode positioned in line with the first electrode, wherein the first electrode contacts the second electrode when the switch is in the operated state. The arrester bypass device can further include a ground strap having a first end and a second end, where the first end is mechanically coupled to the plunger, and where the second end is mechanically coupled to an electrical ground. |
| US09543744B1 |
Sealed cable conduit electrical box
A cable conduit electrical box including a base having at least one opening for receiving a cable conduit, a cover removably attachable to the base, and an adapter removably positioned on the base or the cover for sealing the at least one opening around the cable conduit. A gasket may be positioned between the base and the cover and a gasket may surround the cable conduit. |
| US09543742B2 |
Protective electrical device
The present invention is directed to a protective device including a fault protection circuit configured to provide a fault detection stimulus in response to detecting at least one type of predetermined fault condition. A circuit interrupter is disposed on a first side of a PCB and an auxiliary switch is at least partially disposed on a second side of the at least one PCB. The auxiliary switch includes a switch throw element movably extending through an opening in the PCB between the first state and the second state, the auxiliary switch being configured to decouple at least a portion of the fault protection circuit assembly from the plurality of line terminals in the second state. |
| US09543739B2 |
Spark plug, and method for manufacturing spark plug
A spark plug comprises an insulator having a axial hole penetrating in a direction of an axis, a central electrode provided on the front end side of the axial hole, a tubular metal shell that holds the insulator, and a ground electrode including a surface layer and a core material that is surrounded by the surface layer and has a larger thermal conductivity than that of the surface layer. The metal shell of the spark plug has a protruding portion in which at least a part of the metal shell protrudes toward the front end side in the direction of the axis. The ground electrode has an end surface at one end portion thereof joined to the inside of the protruding portion and the other end portion thereof facing the central electrode. |
| US09543738B2 |
Low voltage laser diodes on {20-21} gallium and nitrogen containing substrates
A low voltage laser device having an active region configured for one or more selected wavelengths of light emissions. |
| US09543730B2 |
Wire transfer system having wire singulating device
A wire singulating device includes a carrier member and a retention feature. The carrier member has a front edge and an opposite rear edge. The front edge defines an opening to a slot that extends at least partially towards the rear edge. The carrier member is configured to move relative to a wire bundle that includes plural wires such that the front edge engages the wire bundle. The slot is configured to receive one wire of the wire bundle therein. The retention feature is coupled to the carrier member and juxtaposed relative to the slot to retain the wire within the slot as the carrier member moves away from the wire bundle to separate the wire from the wire bundle. |
| US09543727B2 |
Nest dies, indent crimp die sets, and crimp tools having such die sets
A nest die for mechanically securing an electrical connector to a conductor wire is provided. The nest die includes a conductor receipt area and a lip. The receipt area has an outer periphery and a bottom surface. The lip is at the outer periphery of the receipt area. The outer periphery is sufficient to receive a free end of the conductor wire abutting the bottom surface and a lower face of the electrical connector on the lip. In this manner, the nest die can be used to easily and reproducibly seat the electrical connector in the die at a predetermined position on the conductor wire. |
| US09543726B2 |
Crimping die for terminal fitted wire
A crimping die includes a first die for constraining the wire crimping portion by a concave die surface shaped in conformity with the wire crimping portion, and a second die including a convex die surface paired with the concave die surface. A width of a recess on the concave die surface and that of a projection on the convex die surface are equal to an outer diameter of the wire crimping portion. The wire crimping portion is pressed by the concave die surface of the first die and the convex die surface of the second die, whereby the wire crimping portion and the wire inserted into the cylindrical interior of the wire crimping portion are crimped and fixed. |
| US09543722B2 |
Connector for supporting electronic device
Provided is a connector including a case having an opposing surface facing external device and a flat plate-shaped contact built in the case. The case includes a first opening which is formed at the opposing surface and through which a contact point of the contact to be connected to a connection terminal of the external device protrudes from the opposing surface, a receiver configured to receive a connector for external connection, and a holder configured to hold the contact. The contact includes the contact point which is disposed in the first opening and which is to contact with the connection terminal of the external device, an elastic portion which is disposed in the case and which moves the contact point in a substantially perpendicular direction relative to the opposing surface, a contact portion which is disposed in the receiver and which is to contact with a connection terminal of the connector for external connection, a held portion which is formed between the elastic portion and the contact portion and which is held by the holder in the case, and a connection portion which is formed between the elastic portion and the contact portion and which connects between the contact point and the contact portion in the case. |
| US09543721B2 |
Connectors for electrically active grid
A connector for electrical connection to an electrified grid element having first and second conductors disposed on a top portion of the grid element. In one embodiment, the connector comprises a single-piece insulator housing; a fastening means on the insulator housing for attaching the connector to a device; and first and second contacts within the insulator housing, the insulator housing configured to align the first and second contacts with the first and second conductors of the electrified grid element; wherein a base of the insulator housing comprises a recess that corresponds to the shape of the top portion of the grid element such that the housing can be mounted over the top portion of the grid member. |
| US09543716B2 |
Electrically compensated SMA shell connector with cable dielectric captivation
The present invention relates to a microwave cable and connector. The microwave cable includes a cable center conductor, a cable dielectric surrounding the cable center conductor and a cable outer conductor surrounding the cable dielectric. A connector body is provided that surrounds the cable outer connector. The connector body has a reduced diameter portion extending beyond the edges of the cable dielectric and the cable outer conductor, and the reduced diameter portion further extends radially inwardly to create a step. The diameter across the step is less than the diameter of the cable dielectric, and the step at the end of the connector body is able to block movement of the cable dielectric. The connector body includes at least one soldering hole that extends through the connector body in a circular recess formed in the connector body dimensioned for receipt of a snap ring. |
| US09543710B2 |
Connector module with cable exit region gasket
A connector module includes a housing and a gasket. The housing is defined by a first shell and a second shell that mate at a seam. The housing includes a cable exit region extending along a cable axis. A passage through the cable exit region has an elliptical cross-section along a plane perpendicular to the cable axis. The gasket is within the passage of the cable exit region. An outer perimeter of the gasket in an uncompressed state has a non-elliptical cross section along a plane perpendicular to the cable axis. The gasket has an outer side engaging the inner surface of the cable exit region and an inner side configured to engage at least one cable received within the cable exit region. As the shells are mated, the gasket is sandwiched in a compressed state between the at least one cable and the cable exit region. |
| US09543708B2 |
Pluggable connector and communication system configured to reduce electromagnetic interference leakage
Pluggable connector including a connector housing having a leading end. The connector housing includes interior sidewalls that define a receiving space and an opening to the receiving space at the leading end. The pluggable connector also includes a contact array of electrical contacts disposed in the receiving space. The contact array is configured to engage corresponding electrical contacts of a mating connector. The pluggable connector also includes an inner electromagnetic interference (EMI) gasket that is coupled to the interior sidewalls and surrounds a portion of the interior space about the central axis. The connector housing is configured to receive the mating connector through the opening and into the receiving space when the connector housing is moved in a mating direction along the central axis. The inner EMI gasket engages the mating connector in the receiving space to electrically couple the mating connector to the connector housing. |
| US09543706B2 |
Electrical connector with power terminals
An electrical connector assembly comprises a receptacle electrical connector and a plug electrical connector. The receptacle electrical connector includes a first body having a first and a second tongues and a plurality of first terminals, the first terminals located on opposite surfaces of the first tongue and offset relative to each other. The plug electrical connector includes a second body and a third and fourth mating chambers located in the second body; a plurality of third terminals, wherein the third terminals located on upper and lower sides of the third mating chamber are offset relative to each other. The receptacle electrical connector and the plug electrical connector can mate with each other so the first terminals and the third terminals are mated with each other to transmit signals and the second tongue and the fourth mating chamber are connected to transmit power. |
| US09543704B1 |
Power adapter
A power adapter includes a body, a plug, and an operation board. The plug is detachably received in and electrically connected to the body. The plug has an engagement slot. The operation board is rotatably received in the body and includes a hook, a pressing portion and a pop portion. The hook latches to the engagement slot to secure the plug to the body. The pressing portion is pressed by external forces. The pop portion is positioned below the plug. When the pressing portion receives an external force, the pressing portion rotates towards the body and drives the pop portion to rotate away from the body, whereby the pop portion pops up the plug from the body. |
| US09543700B2 |
Conductor terminal
A conductor terminal (1) having an insulating material housing (2) and having at least one spring-loaded clamping connection (11) in the insulating material housing (2) and also having at least one actuation element (4), which is pivotably accommodated in the insulating material housing (2) and is designed to open in each case at least one associated spring-loaded clamping connection (11), is described. The actuation element (4) has two side wall portions (8a, 8b) which are spaced from one another and at least partially enter the insulating material housing (2) with a pivot bearing region (14) and, opposite said pivot bearing region (14), are connected to each other by a transverse web (5) to form a lever arm. The pivot bearing regions (14) of the mutually distanced side wall portions (8a, 8b) of an actuation element (4) form an axis of rotation (D), about which the actuation element (4) is pivotably mounted in the insulating material housing (2). An associated spring-loaded clamping connection (11) is at least partially accommodated in the space between the pivot bearing regions (14) of an actuation element (4). The pivot bearing regions (14) have actuation portions (16), which in each case are designed in order to act on an associated clamping spring (17) of a spring-loaded clamping connection (11) as the actuation element (16) is pivoted from a closed position into an open position, and in that the actuation portions (4) are arranged on the pivot bearing regions (14) of the side wall portions (8a, 8b) at a distance from one another that is shorter than the distance between the side wall portions (8a, 8b). The actuation portions (16) extend parallel to the side wall portions (8a, 8b) and are formed integrally with the side wall portions (8a, 8b), such that in each case a guide slot (30) is provided between an actuation portion (16) and the associated, directly adjacent side wall portion (8a, 8b), and in that a guide web (27) of the insulating material housing (2) in each case enters an associated guide slot (30) for guiding the actuation element (4) in the event of a pivot motion about an axis of rotation (D) in the pivot bearing region (14). |
| US09543698B2 |
Connector
A connector has a first housing (21) provided movably in a holder (10) and movements thereof are regulated by locking between resilient locking pieces (15) formed on the holder (10) and locks (23) formed on the first housing (21). In the process of assembling a first device (60) and a second device (70), the first housing (21) and a second housing (40) are connected properly and lock releasing portions (47) resiliently deflect the resilient locking pieces (15) to separate the resilient locking pieces (15) from the locks (23). When locking between the resilient locking pieces (15) and the locks (23) is released, the first housing (21) moves with respect to the holder (10) while being kept properly connected to the second housing (40) as assembly of the first and second devices (60, 70) proceeds. |
| US09543695B2 |
Pre-tensioned connector
Connector (100) with locking components (107) about a peripheral section of the connector. The locking components extend in an axial direction engage with the connector (100) at a first end and engage with a connecting part (201) at an opposite locking end with a locking profile (109). A radial locking movement of the locking end is provided by an axial movement of an actuation sleeve (113). The locking components (107) are arranged to pivot in a substantially radial direction, about their section of engagement with the connector (100), into and out of a locking position. The connector (100) comprises guiding plates (111) between the locking components (107) in the area of their locking ends. The guiding plates exhibit protective faces (111a) that extend further radially inwards than the locking profile (109) of the locking components (107) when the latter are in the outwardly pivoted position. |
| US09543694B2 |
Radiation imaging system, radiation imaging apparatus, and apparatus
An X-ray imaging system includes an X-ray imaging apparatus for converting an X-ray into an image signal, a cable for transmitting signals to the X-ray imaging apparatus, a connector, disposed at an end of the cable, for connecting the cable and the X-ray imaging apparatus, and fixing portions for fixing the connector and the X-ray imaging apparatus and allowing the connector to be detached from the X-ray imaging apparatus by a detachment load. A cable outlet of the connector is separated from an outline center axis of the connector. The fixing portions include a first fixing portion disposed on the cable outlet side with respect to the connector outline center axis, and a second fixing portion disposed on the opposite side of the cable outlet. The moment of force required to detach the first fixing portion is larger than that required to detach the second fixing portion. |
| US09543688B2 |
Electrical connector having terminals embedded in a packaging body
An electrical connector includes a housing and a plurality of terminal wafers. The housing is formed with a plurality of terminal slots along a traverse direction. The terminal wafers are contiguous to each other and retained in the housing. Each terminal wafer has a first terminal, a second terminal and a packaging body. The first terminal has a first contacting section, a first soldering portion and a first embedded section. The second terminal has a second contacting section, a second soldering portion and a second embedded section. The first and second contacting sections are extended along a plugging direction into one corresponding terminal slot. The packaging body wraps the first and second embedded sections. A curve contour of the first embedded section is corresponded to a curve contour of the second embedded section, so that an attachment relationship is configured with substantial identical distance therebetween. |
| US09543685B2 |
Tamper resistant receptacle with cam feature
A tamper resistant electrical receptacle for use with 20 A receptacles. A pair of pivoting shutter and trap doors biased in the same direction use a cam and cam follower that moves laterally a distance sufficient to allow passage of the perpendicular portion of a neutral blade of a 20 A electrical plug when simultaneous insertion of electrical plug tines overcome the spring bias of the springs to allow the tines to access the devices hot and neutral electrical contacts. Absent simultaneous insertion, the shutter and trap doors cannot operate in tandem to provide the tines passage to the electrical contacts. |
| US09543684B1 |
Trim panel
A trim panel having a main body, a plurality of attachment structures and a dummy electric connector. The main body has a trim surface and an attachment surface opposite the trim surface. The plurality of attachment structures are formed on the attachment surface and are configured to contact and engage a separate panel securing the main body to the separate panel and covering an aperture formed in the separate panel. The dummy electric connector is formed on the attachment surface. The dummy electric connector is configured to receive and retain an electric connector in the absence of any electrical contacts within or on the dummy electric connector. The dummy electrical connector enables retention of a wiring harness having a connector that is not currently used, the unused connector to be connected to and retained by the dummy connector. |
| US09543681B2 |
Terminal for an antenna connector
A terminal for an antenna connector has a soldering base, two wings, a resilient electric contacting arm, and two pre-pressing elements. The wings are formed on the soldering base, and each wing has an opening. The resilient electric contacting arm is formed on and protrudes from a rear end of the soldering base and has an extension section, a resilient section, and an electronic contacting section. The pre-pressing elements are located respectively in the openings of the wings, pre-press the resilient section of the resilient electric contacting arm toward the soldering base, and limit the resilient section to sway in an extent from an inner upper edge of each opening to the soldering base. The terminal with the pre-pressing elements performs an excellent electrical contacting effect to improve signal transmission of the antenna connector and a corresponding antenna module. |
| US09543680B2 |
Contact assembly of a robotic garden tool charging device
A contact assembly of a robotic garden tool charging device 10 . The contact assembly 100 is arranged to engage a contact element 200 of a robotic garden tool 20 for a charging operation. The contact assembly 100 comprises a contact member 110 having a plurality of connection points 121 , arranged to provide a plurality of points of contact 30 between the contact member 110 and the contact element 200 . The contact member is configured to be pivotably and translatably connected to a body portion 11 of the charging device 10 . The contact assembly 100 comprises a biasing member 140 arranged to interconnect the contact member 110 and the body portion 11, so as to bias the contact member 110 towards the contact element 200 during the charging operation. |
| US09543679B2 |
Electrical contact assembly
An electrical contact assembly includes a first electrical contact having a first mating element, and a second electrical contact having a second mating element. The first and second electrical contacts being configured to mate together at the first and second mating elements such that the first and second mating elements engage each other at a contact interface. A distribution of contact pressure across the contact interface at least partially coincides with a distribution of electrical current flow across the contact interface. |
| US09543676B2 |
Connector adapter and circuit board assembly including the same
Connector adapter includes an adapter body having a mating side and a mounting side. The mating side includes signal cavities that open to the mating side. The connector adapter also includes signal conductors extending through the adapter body. Each of the signal conductors has and extends between a pin socket positioned at the mating side and a signal tail positioned at the mounting side. The pin sockets are positioned within corresponding signal cavities. Each of the pin sockets includes first and second arms that oppose each other and define a thru-hole therebetween. The first and second arms engage a signal tail of an electrical connector when the signal tail of the electrical connector is inserted into the thru-hole. |
| US09543668B2 |
Electrical terminal and method
A connection terminal for connecting, in an electrically contacting manner, to at least one conductor includes a current bar held on a mount. The current bar connects to the at least one conductor. The connection terminal also includes an actuation lever, a clamping spring, and a slotted guide. The slotted guide has at least one closure slot and a clamping slot that branches off transversely therefrom. The actuation lever is movably guided in the slotted guide by a first pin and a second pin. |
| US09543664B2 |
Insulation displacement connector
An insulation displacement contact includes a monolithic electrically conductive contact body that includes mating portion and a mounting portion. The mating portion defines a pair of insulation displacement slots configured to receive an electrical cable delivered by a connector housing. The insulation displacement contact includes a retention wall that is received by the connector housing in order to insert the electrical cable into the insulation displacement slots. The connector housing can further receive the insulation displacement contact so as to deliver the mounting portion to a complementary electrical component to which the insulation displacement contact is mounted. |
| US09543658B2 |
Satellite antenna
A satellite antenna is provided, including a dish, a bracket, an extension rod and a receiver. The dish includes a reflective surface and a back surface. The bracket is connected to the back surface, wherein the bracket includes a pivot portion. The extension rod includes a first end and a second end, wherein the first end pivots on the pivot portion of the bracket, the extension rod is adapted to be rotated between a first orientation and a second orientation around a pivoting axis. The receiver is disposed on the second end of the extension rod and corresponds to the reflective surface, wherein the pivoting axis is located between the reflective surface and the receiver. |
| US09543652B2 |
Loop antenna
A loop antenna is provided, which includes a first loop section, a second loop section and a third loop section. The first loop section surrounds and defines an empty area. The second loop section surrounds and connects the first loop section, and an annular groove is formed between the first loop section and the second loop section. The third loop section surrounds and connects the second loop section. The width of a gap between the third loop section and the second loop section is smaller than the width of the annular groove. |
| US09543648B2 |
Switchable antennas for wireless applications
Techniques of designing an antenna array with antenna units controlled electronically are described. Through controlling the combination of the reflectors in each of the antenna units, a desired antenna pattern is formed, adapting to the environment, and providing reliable and efficient links between two transceivers. According to one aspect of the present invention, a switch (e.g., a diode) is used to couple two reflectors. The diode is controlled to be on or off so that the reflectors are conductively integrated or separated. |
| US09543642B2 |
Antenna device and wireless device
An RFID tag includes an antenna element and a feed device. The antenna element includes a base sheet and a coil conductor on the upper surface thereof. The feed device includes a feed element and an RFIC. The feed element includes a base sheet and a first coil conductor and a second coil conductor on the upper surface of the base sheet. The first coil conductor and the second coil conductor are arranged on the base sheet such that magnetic flux generated in the first coil conductor and the second coil conductor constitutes a closed magnetic circuit. The feed device is adhered to a coupling portion of the antenna element. As a result, the RFIC is strongly coupled to the antenna element. |
| US09543639B2 |
Back face antenna in a computing device case
An antenna assembly includes a portion of the metal computing device case as a primary radiating structure. The metal computing device case includes a back face and one or more side faces bounding the back face. The metal computing device case further includes a radiating structure having an aperture formed in the back face from which a notch extends from the aperture cutting through the back face and through at least one side face of the metal computing device case. A conductive feed structure is connected to a radio. The conductive feed structure is positioned proximal to the radiating structure of the metal computing device case and is configured to excite the radiating structure at one or more resonance frequencies. |
| US09543638B2 |
Fixing bracket for antenna cable and portable terminal having the same
Provided is a portable terminal. The portable terminal includes a metal frame including a cable accommodation part; an antenna cable accommodated into the cable accommodation part, the antenna cable including a conductive part; and a bracket clamping the antenna cable, the bracket being inserted into and coupled to the cable accommodation part. The bracket is formed of a conductive material and in contact with the conductive part. |
| US09543637B2 |
Thin-film transistor display device having integrated NFC antenna
A thin-film transistor display device having integrated an NFC antenna (3). The NFC antenna (3) is arranged on a display screen (S) of the thin-film transistor display device, where the NFC interface is equipped with an output circuit of the display screen (S) and is connected to a control mainboard of the display screen (S). The thin-film transistor display device combines the display screen (S) and NFC antenna (3) features, and has the NFC antenna (3) provided directly on the thin-film transistor display device, thus preventing the problem of signal quality deterioration and reception failure due to wearing of the NFC antenna interface and inaccurate alignment, while facilitating reception and transmission of signals by the antenna, thus ensuring the smoothness of communication. |
| US09543636B2 |
Hybrid radio frequency/inductive loop charger
Biometric monitoring devices, including various technologies that may be implemented in such devices, are discussed herein. Additionally, techniques, systems, and apparatuses are discussed herein for providing a hybrid antenna including an RF radiator and an electrically coupled inductive loop. The hybrid antenna is capable of providing both RF and induction functionality, e.g., radio frequency transmission/reception capabilities for Bluetooth as well as near-field-communications (NFC) functionality via the inductive loop. The inductive loop may be in conductive contact with the RF radiator or may be inductively coupled with the RF radiator and not in conductive contact with the RF radiator. The inductive loop may act as a planar element of a planar inverted-F antenna (PIFA). |
| US09543635B2 |
Operation of radio devices for long-range high-speed wireless communication
Methods and apparatuses for point-to-point or point-to-multipoint transmission/communication of high bandwidth signals. High bandwidth signals may be efficiently transmitted by a radio device having a pair of reflectors separated by an isolation choke boundary. The two reflectors may be connected or formed of a single housing, and may be mounted to a wall, pole, etc. using a quick-connect. The devices may be configured to operate in any appropriate band (e.g., a 5GHz band, a 24 GHz band, etc.) and may be configured for accurate and easy alignment with one or more remote radio devices. Alignment may be assisted by displaying both local and remote transmission information during alignment. |
| US09543634B1 |
Telescoping strut with fixed rail feature
Various embodiments provide a telescoping strut with a fixed rail feature. The telescoping strut includes an outer tube having slits and holes, an inner tube having rail slots and an insert guide, a threaded insert, and bolts. The threaded insert is positioned in the insert guide of the inner tube, which is inserted in the outer tube. The threaded insert, positioned in the insert guide, is aligned with the holes of the outer tube and the rail slots of the inner tube. The bolts are inserted in to the holes and the rail slots, and are threadably attached to the threaded insert. The insert guide and the rail slots allow the threaded insert and the bolts to slide freely with respect to the inner tube. As a result, the inner tube slides freely within the outer tube until the threaded insert and the bolts are tightened. When a desired length of the telescoping strut is obtained, the bolts and the threaded insert are tightened causing the slits of the outer tube to deform around the inner tube. |
| US09543632B2 |
Directional coupler
A directional coupler includes a multilayer body including a plurality of stacked dielectric layers, a main line including a first main line portion and a second main line portion which are connected in series to each other in this order and that is provided in the multilayer body, and a sub-line including a first sub-line portion and a second sub-line portion which are connected in series to each other in this order, the first sub-line portion being electromagnetically coupled to the first main line portion, the second sub-line portion being electromagnetically coupled to the second main line portion, and the sub-line being provided on one side in a stacking direction with respect to the main line in the multilayer body. The second main line portion is provided on a dielectric layer that is different from a dielectric layer on which the first main line portion is provided and/or the second sub-line portion is provided on a dielectric layer that is different from a dielectric layer on which the first sub-line portion is provided. |
| US09543625B2 |
Metal/oxygen battery with multistage oxygen compression
A vehicular battery system includes an oxygen reservoir having a first outlet and a first inlet, a multistage compressor supported by the vehicle and having a second inlet and a second outlet, the second outlet operably connected to the first inlet, a cooling system operably connected to the multistage compressor and configured to provide a coolant to the multistage compressor to cool a compressed fluid within the multistage compressor, and a vehicular battery system stack including at least one negative electrode including a form of lithium, the vehicular battery system stack having a third inlet removably operably connected to the first outlet, and a third outlet operably connected to the second inlet. |
| US09543621B2 |
Electrode assembly and battery pack including the same
An electrode assembly includes a structure including a first electrode plate and a second electrode plate that are wound together, and a separator between the first electrode plate and the second electrode plate, a first electrode tab that is electrically connected to the first electrode plate, and a second electrode tab that is electrically connected to the second electrode plate. The structure includes a pair of grooves at opposite sides of the structure, the grooves being formed by compression of the structure at the opposite sides in a direction perpendicular to a winding surface. The structure including a first part and a second part that are oppositely located with respect to a reference line connecting the pair of grooves, and the second part is shifted in a first direction such that the second part is partially misaligned with the first part. |
| US09543617B2 |
Lithium-ion battery containing an electrolyte comprising an ionic liquid
A lithium-ion battery containing: a positive electrode, a negative electrode, an electrolyte comprising: an organic solvent chosen from the group comprising carbonates, linear esters of a saturated acid, or a mixture thereof, an additive capable of forming a passivation film on the surface of the negative electrode, at least one lithium salt, at least one ionic liquid for which the percentage by weight in the electrolyte is greater than or equal to 20% and less than 50%; a separator for which the apparent contact angle between the surface thereof and the electrolyte is less than 20°. |
| US09543616B2 |
Electrolyte for magnesium rechargeable battery and preparation method thereof
Disclosed is an electrolyte solution for a magnesium rechargeable battery with a high ionic conductivity and a wide electrochemical window compared to the conventional electrolyte solution. The electrolyte solution is prepared by dissolving magnesium metal into the ethereal solution using combinations of metal chloride catalysts. The electrolyte solution can be applied to fabricate magnesium rechargeable batteries and magnesium hybrid batteries with a markedly increased reversible capacity, rate capability, and cycle life compared to those batteries employing the conventional electrolyte solution. Also disclosed is a method for preparing the electrolyte. |
| US09543613B2 |
Secondary battery with electrolytic solution including a methylene cyclic carbonate, battery pack, electric vehicle, energy storage system, electric power tool, and electronic unit including the same
A secondary battery includes: a cathode, an anode, and a nonaqueous electrolytic solution in a package member having a flat surface, in which the nonaqueous electrolytic solution includes a methylene cyclic carbonate represented by an expression (1): where R1 and R2 each are a hydrogen group, a halogen group, a monovalent hydrocarbon group, a monovalent halogenated hydrocarbon group, an oxygen-containing monovalent hydrocarbon group, or an oxygen-containing monovalent halogenated hydrocarbon group, and R1 and R2 may be bonded to each other. |
| US09543612B2 |
Rechargeable battery
A rechargeable battery includes an electrode assembly, a first current collecting plate and a second current collecting plate spaced apart from each other and electrically connected to first and second electrode uncoated regions n the electrode assembly, a case receiving the electrode assembly, a cap plate sealing the case, a first electrode terminal and a second electrode terminal extending through the cap plate and electrically connected to the first and second current collecting plates, a first retainer adjacent to the cap plate and coupled to firsts regions of the first and second current collecting plates, and a second retainer coupled to second regions of the first and second current collecting plates or to the first and second electrode uncoated regions, the first and second regions of the first and second current collecting plates being different from each other. |
| US09543610B2 |
Fuel cell vehicle
A fuel cell vehicle includes a fuel cell stack, a front side panel, and a fuel gas device. The fuel cell stack includes a plurality of fuel cells, one end and another end, a first end plate, and a second end plate. The first end plate is disposed at the one end. The second end plate is disposed at the another end. The front side panel is connected to side surfaces of the first and second end plates. The side surfaces face forward in a vehicle driving direction. The front side panel includes a first protruding end portion that protrudes from the first end plate outward in a vehicle width direction. The fuel gas device is disposed on the first end plate so as to be covered by the first protruding end portion when seen from a front side in the vehicle driving direction. |
| US09543608B2 |
Solid oxide fuel cell and manufacturing method and manufacturing apparatus for same
The present invention provides a novel manufacturing method for a solid oxide fuel cell apparatus in which members of the apparatus are joined together with an adhesive, such as a ceramic adhesive. The method implements first and second types of drying and hardening steps. The first type of step may be called a workable hardening step and gives an assembly of members in the solid oxide fuel cell apparatus structural rigidity to go through assembling of the solid oxide fuel cell apparatus. The second type of step may be called a solvent elimination and hardening step and gives the assembled members property to withstand the operation temperature of the solid fuel oxide cell apparatus. The first type of step is performed at a first temperature lower than a second temperature at which the second type of step is performed. The second type of step is performed only after the first type of step is performed at multiple times. |
| US09543597B2 |
Fuel-cell power generation system and method of manufacturing the same
According to one embodiment, a fuel-cell power generation system includes a fuel cell that generates electricity by electrochemical reaction using fuel and an oxidizer and a resin module that includes a flow path through which fuel, air, or water flows, inner walls defining the flow path being made of resin. |
| US09543595B2 |
Separator plate with intermediate injection of gas, fuel cell, method of feeding a fuel cell
A fuel cell separator plate is provided. The fuel cell separator plate includes at least one groove formed in a face of the separator plate so as to feed reactant gas to a membrane electrode assembly applied against the face of the separator plate, the groove comprising an inlet section and an outlet section. The fuel cell separator plate also includes injection means configured so as to inject gas into at least one intermediate section of the groove, situated between the inlet section and the outlet section. |
| US09543593B2 |
Electrode compartment for an electrochemical cell, a refreshing system for it and an emulsion to be used therefore
The invention relates to an electrode compartment for an electrochemical cell, including a bicontinuous micro-eπulsion, wherein catalytic parts are generated in-situ in a fluid, which can act as a cathode as well as an anode. The electrode compartment comprises a connection to supply fuel or an oxidator, for example oxygen, to the compartment. The electrode compartment is part of a refreshing system with a reserve container for an emulsion and a storage container for used emulsion, conduits to connect each of the containers with the electrode compartment and a transport unit, for example a pump, to move the emulsion. |
| US09543591B2 |
Non-carbon mixed-metal oxide electrocatalysts
Electrocatalysts having non-corrosive, non-carbon support particles are provided as well as the method of making the electrocatalysts and the non-corrosive, non-carbon support particles. Embodiments of the non-corrosive, non-carbon support particle consists essentially of titanium dioxide and ruthenium dioxide. The electrocatalyst can be used in fuel cells, for example. |
| US09543589B2 |
Lead-acid battery construction
Batteries comprise a carbon fiber electrode construction of the invention and have improved DCA and/or CCA, and/or may maintain DCA with an increasing number of charge-discharge cycles, and thus may be particularly suitable for use in hybrid vehicles. |
| US09543588B2 |
Aluminum alloy foil for electrode collectors and production method therefor
An object of the present invention is to provide an aluminum alloy foil for an electrode current collector, the foil having a high strength after the drying step while keeping a high electrical conductivity. Disclosed is a method for manufacturing an aluminum alloy foil for electrode current collector, including: maintaining an aluminum alloy ingot comprising 0.1 to 0.5% of Fe, 0.01 to 0.3% of Si, 0.01 to 0.2% of Cu, 0.01% or less of Mn, with the rest being Al and unavoidable impurities, at 550 to 620° C. for 1 to 20 hours, and subjecting the resulting ingot under a hot rolling with a starting temperature of 500° C. or higher and an end-point temperature of 255 to 300° C. |
| US09543581B2 |
Alumina dry-coated cathode material precursors
A particulate precursor compound for manufacturing an aluminum doped lithium transition metal (M)-oxide powder usable as an active positive electrode material in lithium-ion batteries includes a transition metal (M)-hydroxide or (M)-oxyhydroxide core and a non-amorphous aluminum oxide coating layer covering the core. By providing an aluminum dry-coating process where the particulate precursor core compound is mixed with alumina powder in one or more procedures, higher doping levels of aluminum compared to the known prior art may be achieved. The crystal structure of the alumina is maintained during the coating procedures and the core of each mixed transition metal precursor particle is surrounded by a coating layer containing crystalline alumina nano particles. The aluminum concentration in the particulate precursor decreases as the size of the core increases. |
| US09543575B2 |
Silicon-based anode and method for manufacturing the same
A silicon-based anode comprising silicon, a carbon coating that coats the surface of the silicon, a polyvinyl acid that binds to at least a portion of the silicon, and vinylene carbonate that seals the interface between the silicon and the polyvinyl acid. Because of its properties, polyvinyl acid binders offer improved anode stability, tunable properties, and many other attractive attributes for silicon-based anodes, which enable the anode to withstand silicon cycles of expansion and contraction during charging and discharging. |
| US09543570B2 |
Nonaqueous electrolyte secondary battery
According to one embodiment, there is provided a nonaqueous electrolyte secondary battery. A negative electrode current collector comprises a coated portion on which the negative electrode active material layer is provided and a noncoated portion which is adjacent to the coated portion, in which the negative electrode active material layer is not present. A density of the negative electrode active material layer is within a range of 2.1 g/cc to 2.4 g/cc. A ratio W1/W2 of a mass of the coated portion per unit area (W1) to a mass of the noncoated portion per unit area (W2) is from 0.997 to 1. |
| US09543567B2 |
Method for manufacturing cathode active material for lithium secondary battery
The present invention relates to a method for manufacturing cathode active material for a lithium secondary battery. The manufacturing method according to the present invention is characterized by including: (1) an intermediate generation process, wherein an intermediate which is powder or a shaped object containing the first material compound which is a compound of the transition metal other than lithium, which constitutes said lithium composite oxide, is generated, (2) a lithium source compound addition process, wherein the second material compound which is a lithium compound is added so that the second material compound in the shape of film may adhere to the surface of said intermediate, and (3) a sintering process, wherein lithium composite oxide is generated by sintering said intermediate in the state where said second material compound has adhered to its surface. |
| US09543566B2 |
Electrode with feedthrough pin for miniature electrochemical cells and methods of making
Miniature electrodes and electrochemical cells are disclosed. Such electrodes are made from forming an electrode mixture onto a current collector and distal end of a feedthrough pin such that the current collector and distal end of the feedthrough pin is encapsulated. The methods and electrode assemblies disclosed herein allow such electrode assemblies to be made free from the step of directly attaching a formed electrode to a feedthrough pin and thus simplifying assembly and decreasing size. |
| US09543563B2 |
Electric storage device including current interruption device
An electric storage device comprises the current interruption device which includes a deformable plate electrically connected to a first conductive member and a second conductive member to constitute part of a conductive path. The deformable plate deforms to interrupt the conductive path, when a pressure inside the casing rises. The first conductive member, the second conductive member, and the current interruption device are disposed between the terminal attachment wall and the electrode assembly. The first conductive member extends along the terminal attachment wall to connect the tab and the current interruption device. The second conductive member is connected to the current interruption device at a location that is farther from the terminal attachment wall than a connection between the first conductive member and the current interruption device, and extends along the terminal attachment wall to connect the current interruption device and the electrode terminal. |
| US09543561B2 |
Battery
A battery comprises: a battery cell; and tabs configured as one pair of an anode tab and a cathode tab and included in the battery cell. At least one of the anode tab and the cathode tab is configured in such a way that a welding region exposed outside the battery cell and a reaction region positioned in the battery cell are formed of different metals and are joined to each other. |
| US09543556B2 |
Battery assembly
A battery stack is provided having lower and upper battery tiers each formed of at least two battery cell arrays. A pair of brackets are provided for connecting the lower arrays along a top surface of the lower tier and connecting the upper arrays to a bottom surface of the upper tier. The lower and upper battery tiers are secured together by the brackets without hardware mounted to an exterior surface of the stack. |
| US09543552B2 |
EMF-shielded plastic prepreg hybrid structural component
The present invention relates to an EMF-screened plastic-organic sheet hybrid structural component, preferably a battery housing, and to its use in motor vehicles, preferably in electrically powered motor vehicles or hybrid motor vehicles, the abbreviation EMF meaning electromagnetic field(s). |
| US09543548B2 |
Deposition donor substrate and method for manufacturing light-emitting device
One surface of a first substrate provided with at least light-absorbing layers separately formed, partition layers each formed between the light-absorbing layers and having an inverse taper shape, and material layers formed on the light-absorbing layers and on the partition layers so that the material layers are separated from each other is disposed to face a deposition target surface of a second substrate; light irradiation is performed from the other surface of the first substrate, only the material layers in regions overlapped with the light-absorbing layers are heated and evaporated to the deposition target surface of the second substrate. |
| US09543547B2 |
OLED display apparatus and the production method thereof
This disclosure provides an OLED display apparatus and the production method thereof, for decreasing the microcavity effect and improving the intensity of the light emitted by the OLED display apparatus. The OLED display apparatus comprises: an array substrate and an OLED device which is provided on the array substrate and comprises an anode, an organic light-emitting layer and a cathode in this order along the direction away from the array substrate, and further comprises: a refractive layer positioned between the array substrate and the anode, wherein the refractive index of the refractive layer is greater than that of the anode. In the above-mentioned OLED display apparatus, by providing a refractive layer, the refractive index of which is greater than that of an anode in an OLED device, the occurrence of total reflection phenomenon when light is irradiated onto an array substrate is reduced and thereby the microcavity effect is reduced, and it is allowed that the light is refracted from the surface of the array substrate as much as possible and the light-emitting intensity of the OLED display apparatus is improved. |
| US09543539B2 |
OLED device and manufacturing method thereof and display apparatus
An OLED device and a manufacturing method thereof and a display apparatus are provided. The OLED device comprises: a substrate, and a first electrode, an organic material function layer and a second electrode which are sequentially provided on the substrate. The OLED device further comprises an uneven layer provided between the first electrode and the substrate, and a surface of the uneven layer corresponding to the first electrode and away from the substrate is not even. The first electrode and/or the second electrode provided on a light output side of the OLED device comprise(s) a metal layer. |
| US09543538B2 |
Organic light-emitting device
An organic light-emitting device includes a positive electrode, a negative electrode and at least one organic material layer between the positive electrode and the negative electrode. The at least one organic material layer includes a hole-injecting layer, a hole-transporting layer, an emission layer, an electron-transporting layer, and an electron-injecting layer, and the emission layer includes a host material and a dopant material. In addition, a lifetime enhancement layer including a bipolar compound is positioned between the emission layer and the electron-transporting layer. |
| US09543528B2 |
Compound for an organic optoelectric device, organic optoelectric device including the same, and display device including the optoelectric device
A compound for an organic optoelectric device, an organic optoelectric device including the same, and a display device including the organic optoelectric device, the compound including a combination of a moiety represented by the following Chemical Formula I and a moiety represented by the following Chemical Formula II: |
| US09543523B2 |
Cyclohexadiene fullerene derivatives
The invention relates to novel fullerene derivatives, to methods for their preparation and educts or intermediates used therein, to mixtures and formulations containing them, to the use of the fullerene derivatives, mixtures and formulations as organic semiconductors in, or for the preparation of, organic electronic (OE) devices, especially organic photovoltaic (OPV) devices and organic photodetectors (OPD), and to OE, OPV and OPD devices comprising, or being prepared from, these fullerene derivatives, mixtures or formulations. |
| US09543520B1 |
Method of manufacturing mask for deposition
A manufacturing method of a mask for deposition including forming a second layer on a side of a first layer, coating a photoresist layer on a side of the second layer, forming a plurality of photoresist patterns which penetrate the photoresist layer according to an exposing and developing process, forming a plurality of pattern grooves in the second layer by etching portions of the second layer, which are exposed through the plurality of photoresist patterns, forming an electro-forming mold by removing the photoresist layer from the second layer, disposing an electrode plate to contact the second layer of the electro-forming mold, performing an electro-forming process of growing a metal layer from the electrode plate in spaces in the corresponding pattern grooves of the second layer of the electro-forming mold, to form a deposition mask, and separating the deposition mask from the electrode plate. |
| US09543517B2 |
Method of making a multicomponent film
Described herein is a method and precursor composition for depositing a multicomponent film. In one embodiment, the method and composition described herein is used to deposit a germanium-containing film such as Germanium Tellurium, Antimony Germanium, and Germanium Antimony Tellurium (GST) films via an atomic layer deposition (ALD) and/or other germanium, tellurium and selenium based metal compounds for phase change memory and photovoltaic devices. In this or other embodiments, the Ge precursor used trichlorogermane. |
| US09543516B2 |
Method for forming a doped metal oxide for use in resistive switching memory elements
Methods for producing RRAM resistive switching elements having reduced forming voltage include doping to create oxygen deficiencies in the dielectric film. Oxygen deficiencies in a dielectric film promote formation of conductive pathways. |
| US09543515B2 |
Electrode materials and interface layers to minimize chalcogenide interface resistance
A phase-change memory cell having a reduced electrode-chalcogenide interface resistance and a method for making the phase-change memory cell are disclosed: An interface layer is formed between an electrode layer and a chalcogenide layer that and provides a reduced resistance between the chalcogenide-based phase-change memory layer and the electrode layer. Exemplary embodiments provide that the interface layer comprises a tungsten carbide, a molybdenum carbide, a tungsten boride, or a molybdenum boride, or a combination thereof. In one exemplary embodiment, the interface layer comprises a thickness of between about 1 nm and about 10 nm. |
| US09543510B2 |
Multi-layer phase change material
A multi-layer phase change material, including: a multi-layer film structure. The multi-layer film structure includes a plurality of periodic units. The periodic units each includes a first single-layer film phase change material and a second single-layer film phase change material. The first single-layer film phase change material and the second single-layer film phase change material are alternately stacked. The first single-layer film phase change material includes chemical components that are different from chemical components included in the second single-layer film phase change material, or the first single-layer film phase change material includes chemical components that are the same as chemical components included in the second single-layer film phase change material and a percent composition of the chemical components included in the first single-layer film phase change material is different from a percent composition of the chemical components included in the second single-layer film phase change material. |
| US09543507B2 |
Selector for low voltage embedded memory
Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less). |
| US09543505B2 |
Magnetic memory device and method for manufacturing the same
A memory device includes a magnetic tunnel junction comprising a first free layer, a pinned layer, and a tunnel barrier layer disposed between the first free layer and the pinned layer, wherein the first free layer comprises a first free magnetic pattern adjacent to the tunnel barrier layer, and a second free magnetic pattern spaced apart from the tunnel barrier layer with the first free magnetic pattern interposed therebetween, wherein the second free magnetic pattern contacts the first free magnetic pattern, wherein the first and second free magnetic patterns include boron (B), wherein a boron content of the first free magnetic pattern is higher than a boron content of the second free magnetic pattern, and wherein the boron content of the first free magnetic pattern is in a range of about 25 at % to about 50 at %. |
| US09543501B2 |
Metal oxide
Provided is a piezoelectric material excellent in piezoelectricity. The piezoelectric material includes a perovskite-type complex oxide represented by the following General Formula (1). A(ZnxTi(1-x))yM(1-y)O3 (1) wherein A represents at least one kind of element containing at least a Bi element and selected from a trivalent metal element; M represents at least one kind of element of Fe, Al, Sc, Mn, Y, Ga, and Yb; x represents a numerical value satisfying 0.4≦x≦0.6; and y represents a numerical value satisfying 0.1≦y≦0.9. |
| US09543495B2 |
Method for roll-to-roll production of flexible, stretchy objects with integrated thermoelectric modules, electronics and heat dissipation
A method of forming a flexible thermal regulation device having multiple functional layers. The layers of the device are formed using various manufacturing techniques and are then integrated to form a sheet having multiple devices disposed thereon. The individual devices are then formed from the sheet. |
| US09543494B2 |
Thermoelectric conversion module and method of manufacturing the same
A p-type semiconductor block is made of a p-type thermoelectric conversion material, and has a pillar portion and a connection portion laterally protruding from the pillar portion. In addition, an n-type semiconductor block is made of an n-type thermoelectric conversion material, and has a pillar portion and a connection portion laterally protruding from the pillar portion. The p-type semiconductor block and the n-type semiconductor block are alternately arranged in such a way that the connection portion of the p-type semiconductor block is connected with the pillar portion of the n-type semiconductor block and the connection portion of the n-type semiconductor block is connected with the pillar portion of the p-type semiconductor block. The connection portions and tip-end portions of the pillar portions are made of a thermoelectric conversion material containing metal powder. |
| US09543489B2 |
Light emitting device
Disclosed is a light emitting device. The light emitting device includes a body, first and second metal layers on a top surface of the body, a heat radiation plate disposed between the first and second metal layers and having a circular outline, a plurality of light emitting parts on the heat radiation plate, first and second bonding regions disposed on the first and second metal layers and electrically connected with the light emitting parts, and a molding member disposed on the heat radiation plate to cover the light emitting parts. Each of the light emitting parts includes a plurality of light emitting chips connected with each other, and a plurality of wires to electrically connect the light emitting chips with the first and second bonding regions, and the wires of each light emitting part are arranged a radial direction about a central of the heat radiation plate. |
| US09543488B2 |
Light emitting device
Disclosed herein is a light emitting device manufactured by separating a growth substrate in a wafer level. The light emitting device includes: a base; a light emitting structure disposed on the base; and a plurality of second contact electrodes disposed between the base and the light emitting structure, wherein the base includes at least two bulk electrodes electrically connected to the light emitting structure and an insulation support disposed between the bulk electrodes and enclosing the bulk electrodes, the insulation support and the bulk electrodes each including concave parts and convex parts engaged with each other on surfaces facing each other, and the convex parts including a section in which a width thereof is changed in a protrusion direction. |
| US09543487B2 |
Light-emitting device and method of manufacturing the same
A light-emitting device includes a first light-emitting element, a second light-emitting element, a third light-emitting element placed between the first and second light-emitting elements, and a bonding wire passing directly over the third light-emitting element and connecting the first light-emitting element with the second light-emitting element. |
| US09543482B2 |
LED package
The present invention is related to a light emitting diode (LED) package. The LED package includes a blue LED chip, a first electrode, a second electrode and a phosphor layer. The phosphor layer covers an outer periphery of the blue LED chip, except a bottom surface of the blue LED chip. The phosphor layer is mixed by yellow fluorescent powder and glue. The phosphor layer includes a main portion corresponding to a central portion of an emitting angle of the blue LED chip and an extending portion corresponding to a periphery of the emitting angle. An average thickness of the main portion is larger than the thickness of the extending portion. |
| US09543480B2 |
Ceramic composite for light conversion and method for manufacture thereof
A ceramic composite for light conversion comprising a solidified body in which crystalline phases of oxides are three-dimensionally entangled and a method for manufacture thereof. A manufacture method of a ceramic composite for light conversion is characterized in that a polishing step is provided in a chemical mechanical polishing (CMP) process applied to the surface of a solidified body with a structure in which an Al2O3 phase and other phases are three-dimensionally entangled. |
| US09543477B2 |
Semiconductor light-emitting device
A semiconductor light emitting device (A) includes an elongated substrate (1) formed with a through-hole (11), a first, a second and a third semiconductor light emitting elements (3R, 3G, 3B) mounted on the main surface of the substrate (1), and an electrode (2R) electrically connected to the first semiconductor light emitting element (3R) and extending to the reverse surface of the substrate (1) via the through-hole (11). The first semiconductor light emitting element (3R) and the through-hole (11) are positioned between the second semiconductor light emitting element (3G) and the third semiconductor light emitting element (3B) in the longitudinal direction of the substrate (1). The second semiconductor light emitting element (3G) is arranged closer to one end of the substrate (1), whereas the third semiconductor light emitting element (3B) is arranged closer to the other end of the substrate (1). |
| US09543470B2 |
Semiconductor light emitting device
A semiconductor light emitting device includes a substrate, a reflective layer and a light emitting structure. The reflective layer includes at least two porous layers alternately disposed on the substrate and having different porosities. The light emitting structure is disposed on the reflective layer and includes a first conductivity-type semiconductor layer, an active layer and a second conductivity-type semiconductor layer. |
| US09543467B2 |
Light emitting device
Disclosed is a light emitting device. The light emitting device includes a first conductive semiconductor layer, an active layer over the first conductive semiconductor layer, a second conductive semiconductor layer over the active layer, a superlattice structure layer over the second conductive semiconductor layer, and a first current spreading layer including a transmissive conductive thin film over the superlattice structure layer. |
| US09543464B2 |
Method of making a light emitting device and a light emitting device made thereof
The method includes preparing a plurality of light-emitting units, one of the plurality of light-emitting units comprising an electrode, a light-emitting stack, and a protection layer with a first part covering the electrode and a second part which comprises a portion surrounding the electrode and covers the light-emitting stack; removing the portion without removing the first part; forming a wavelength conversion layer on the first part and the light-emitting stack not covered by the second part; and removing the first part to substantially expose the electrode. |
| US09543463B2 |
Signal distribution in integrated circuit using optical through silicon via
An optical through silicon via is formed in a silicon substrate of an integrated circuit. A photo detector is formed within the integrated circuit and is optically coupled to a first side of the optical through silicon via. A light generating source optically coupled to a second side of the optical through silicon via is provided. The photo detector is configured to receive a light, generated by the light generating source, propagating through the optical through silicon via. The light, generated by the light generating source, is controlled by a signal generated by a signal generating source. |
| US09543459B2 |
Flexible solar cell apparatus and method of fabricating the same
Disclosed are a flexible solar cell apparatus and a method of fabricating the same. The flexible solar cell apparatus includes a support substrate including an internal region and an outer region surrounding the internal region, a plurality of solar cells on the internal region, and a protective layer on the outer region and the solar cells. A top surface of each solar cell is lower than a top surface of the outer region of the support substrate. |
| US09543458B2 |
Full color single pixel including doublet or quadruplet Si nanowires for image sensors
An image sensor comprising a substrate and one or more of pixels thereon. The pixels have subpixels therein comprising nanowires sensitive to light of different color. The nanowires are functional to covert light of the colors they are sensitive to into electrical signals. |
| US09543457B2 |
Method and system for manufacturing back contacts of photovoltaic devices
A method for manufacturing a photovoltaic device includes a step of depositing one of an amorphous layer of ZnTe and a multilayer stack of Zn and Te adjacent a semiconductor layer. The one of the amorphous layer and the multilayer stack is then subjected to an energy impulse at a temperature equal to or greater than its critical temperature. The energy impulse results in an explosive crystallization to form a polycrystalline layer of ZnTe from the one of the amorphous layer and the multilayer stack. |
| US09543456B1 |
Multijunction solar cell employing extended heterojunction and step graded antireflection structures and methods for constructing the same
Material and antireflection structure designs and methods of manufacturing are provided that produce efficient photovoltaic power conversion from single- and multi-junction devices. Materials of different energy gap are combined in the depletion region of at least one of the semiconductor junctions. Higher energy gap layers are positioned to reduce the diode dark current and enhance the operating voltage by suppressing both carrier injections across the junction and recombination rates within the junction. Step-graded antireflection structures are placed above the active region of the device in order to increase the photocurrent. |
| US09543455B2 |
System and method for low-cost, high-efficiency solar panel power feed
A cascading regulation system connected to a number of serially connected power sources and uses multiple regulators having different cutoff voltages to provide an output for the local power consumption unit. Each of the regulators is connected to a subset of serially connected power sources and so configured that if the voltage generated at the lowest tap is no longer sufficient for a stable supply to the local power consumption unit, the next higher regulator takes over, and the output voltage drops in small steps reflective of that takeover of the next higher tap. When the voltage generated across a subsection grows, a lower connected tap may take over again, producing a slightly higher output voltage for the local power consumption unit. The cutover steps are chosen such that the output voltage range matches the range given as the acceptable input range for the local power consumption unit. |
| US09543454B1 |
Diodes with multiple junctions
A diode includes a semiconductor substrate having a surface; a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type; and a second contact region disposed at the surface, laterally spaced from the first contact region, and having a second conductivity type. The diode also includes a buried region disposed in the semiconductor substrate vertically adjacent to the first contact region, having the second conductivity type, and electrically connected with the second contact region; and an isolation region disposed at the surface between the first and second contact regions. The diode also includes a separation region disposed at the surface between the first contact region and the isolation region, the separation region formed from a portion of a first well region disposed in the semiconductor substrate that extends to the surface. |
| US09543451B2 |
High voltage junction field effect transistor
The present invention discloses a high voltage JFET. The high voltage JFET includes a second conductivity type drift region located on the first conductivity type epitaxial layer; a second conductivity type drain heavily doped region located in the second conductivity type drift region; a drain terminal oxygen region located on the second conductivity type drift region and at a side of the second conductivity type drain heavily doped region; a first conductivity type well region located at a side of the second conductivity type drift region; a second conductivity type source heavily doped region and a first conductivity type gate heavily doped region located on the first conductivity type well region, and a gate source terminal oxygen region; a second conductivity type channel layer located between the second conductivity type source heavily doped region and the second conductivity type drift region; a dielectric layer and a field electrode plate located on the second conductivity type channel layer. Wherein a drain electrode electrically is led out from the second conductivity type drain heavily doped region; a source electrode electrically is led out from a connection of the field electrode plate and the second conductivity type source heavily doped region; and a gate electrode electrically is led out from the first conductivity type gate heavily doped region. The transistor has a high breakdown voltage and easy to be integrated. |
| US09543441B2 |
Methods, apparatus and system for fabricating high performance finFET device
At least one method, apparatus and system disclosed herein fin field effect transistor (finFET) comprising a bulbous fin head. A fin of a gate of a transistor is formed. A first recess step is performed for striping a hard mask material by a first dimension to expose a first portion of the fin. An epitaxy layer is formed upon the first portion. An oxidation process is performed upon the fin. An oxide removal process is performed upon the fin to provide a bulbous shape upon the first portion. |
| US09543431B2 |
Radio frequency LDMOS device and a fabrication method therefor
A radio frequency LDMOS device, wherein the drift region includes a first injection region and a second injection region; the first injection region situated between a second lateral surface of a polysilicon gate and a second lateral surface of a first Faraday shielding layer; the second injection region situated between the second lateral surface of the first Faraday shielding layer and the drain region and encloses the drain region; the second lateral surface of the second Faraday shielding layer is a surface of a side near the drain region, the maximum electric field strength of the drift region on the bottom of the second lateral surface of the second Faraday shielding layer is regulated via regulation of the doping concentration of the second injection region; the doping concentration of the first injection region is higher than the second injection region. |
| US09543430B2 |
Segmented power transistor
A power transistor includes multiple substantially parallel transistor fingers, where each finger includes a conductive source stripe and a conductive drain stripe. The power transistor also includes multiple substantially parallel conductive connection lines, where each conductive connection line connects at least one source stripe to a common source connection or at least one drain stripe to a common drain connection. The conductive connection lines are disposed substantially perpendicular to the transistor fingers. At least one of the source or drain stripes is segmented into multiple portions, where adjacent portions are separated by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain stripe. |
| US09543429B2 |
Silicon carbide semiconductor device
There is provided a silicon carbide semiconductor device allowing for increased switching speed with a simpler configuration. A silicon carbide semiconductor device includes: a gate electrode provided on a gate insulating film; and a gate pad. The gate electrode includes a first comb-tooth shaped electrode portion extending from outside of the gate pad toward a circumferential edge portion of the gate pad and overlapping with the gate pad at the circumferential edge portion of the gate pad when viewed in a plan view. A p+ region includes: a central portion overlapping with the gate pad when viewed in the plan view; and a peripheral portion extending from the central portion toward the outside of the gate pad, the peripheral portion being provided to face the first comb-tooth shaped electrode portion of the gate electrode with a space interposed therebetween. |
| US09543425B2 |
Multi-finger large periphery AlInN/AlN/GaN metal-oxide-semiconductor heterostructure field effect transistors on sapphire substrate
MOSHFET devices are provided, along with their methods of fabrication. The MOSHFET device can include a substrate; a multilayer stack on the substrate; a ultra-thin barrier layer on the multilayer stack, wherein the ultra-thin barrier layer has a thickness of about 0.5 nm to about 10 nm; a dielectric, discontinuous thin film layer on portions of the ultra-thin barrier layer, wherein the dielectric, discontinuous thin film layer comprises SiO2; a plurality of source electrodes and drain electrodes formed directly on the ultra-thin barrier layer in an alternating pattern such that the dielectric, discontinuous thin film layer is positioned between adjacent source electrodes and drain electrodes; a plurality of gate electrodes on the dielectric, discontinuous thin film layer; and a gate interconnect electrically connecting the plurality of gate electrodes. |
| US09543423B2 |
Hot-electron transistor having multiple MSM sequences
In one aspect, a transistor comprises a metal emitter, a first semiconductor barrier, a metal base, a second semiconductor barrier, and a metal collector. The first semiconductor barrier separates the metal emitter and the metal base and has an average thickness based on a first mean free path of a charge carrier in the first semiconductor barrier emitted from the metal emitter. The second semiconductor barrier separates the metal base from the metal collector and has an average thickness based on a second mean free path of the charge carrier in the second semiconductor barrier injected from the metal base. The metal base comprises two or more metal layers and has an average thickness based on a multi-layer mean free path of the charge carrier. |
| US09543420B2 |
Protection device and related fabrication methods
Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region. |
| US09543418B2 |
Semiconductor liner of semiconductor device
The disclosure relates to a fin field effect transistor (FinFET) formed in and on a substrate having a major surface. The FinFET includes a fin structure protruding from the major surface, which fin includes a lower portion, an upper portion, and a middle portion between the lower portion and upper portion, wherein the fin structure includes a first semiconductor material having a first lattice constant; a pair of notches extending into opposite sides of the middle portion; and a semiconductor liner adjoining the lower portion. The semiconductor liner is a second semiconductor material having a second lattice constant greater than the first lattice constant. |
| US09543414B2 |
Method of forming a silicon-carbide device with a shielded gate
A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed. |
| US09543412B2 |
Method for manufacturing silicon carbide semiconductor device
A silicon carbide substrate including a first layer having first conductivity type, a second layer having second conductivity type, and a third layer having the first conductivity type is formed. A trench provided with an inner surface having a side wall surface and a bottom surface is formed, the side wall surface extending through the third layer and the second layer and reaching the first layer, the bottom surface being formed of the first layer. A silicon film is formed to cover the bottom surface. A gate oxide film is formed on the inner surface by oxidation in the trench. The gate oxide film includes a first portion formed by oxidation of the silicon carbide substrate, and a second portion formed by oxidation of the silicon film on the bottom surface. Accordingly, a method for manufacturing a silicon carbide semiconductor device having a high breakdown voltage is provided. |
| US09543407B2 |
Low-K spacer for RMG finFET formation
A method for semiconductor fabrication includes providing mask layers on opposite sides of a substrate, the substrate having one or more mandrels. Dummy spacers are formed along a periphery of the mask layers. A dummy gate structure is formed between the dummy spacers. The dummy spacers are removed to provide a recess. Low-k spacers are formed in the recess. |
| US09543402B1 |
Integrated high performance lateral schottky diode
A diode includes a two-dimensional electron gas formed in a heterojunction defined between first and second semiconductor material layers. First and second layers of insulating material are disposed on the second semiconductor layer. First and second electrodes are disposed in the second layer of insulating material. The first electrode is coupled to the second semiconductor material layer. The second electrode is coupled to the heterojunction. Third and fourth layers of insulating material are disposed on the second insulating layer. A first via is disposed in the fourth layer of insulating material and coupled to the second electrode. A first field plate is disposed in the fourth layer of insulating material. An edge of the first field plate laterally extends towards first via. The first via is separated from an edge of the first via. The first field plate is coupled to the first electrode. |
| US09543400B2 |
Ohmic contact to semiconductor
A solution for forming an ohmic contact to a semiconductor layer is provided. A masking material is applied to a set of contact regions on the surface of the semiconductor layer. Subsequently, one or more layers of a device heterostructure are formed on the non-masked region(s) of the semiconductor layer. The ohmic contact can be formed after the one or more layers of the device heterostructure are formed. The ohmic contact formation can be performed at a processing temperature lower than a temperature range within which a quality of a material forming any semiconductor layer in the device heterostructure is damaged. |
| US09543397B2 |
Backside source-drain contact for integrated circuit transistor devices and method of making same
An integrated circuit transistor is formed on and in a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region epitaxially grown above the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate is preferably of the silicon on insulator (SOI) type. |
| US09543395B2 |
Normally-off power JFET and manufacturing method thereof
In general, in a semiconductor active element such as a normally-off JFET based on SiC in which an impurity diffusion speed is significantly lower than in silicon, gate regions are formed through ion implantation into the side walls of trenches formed in source regions. However, to ensure the performance of the JFET, it is necessary to control the area between the gate regions thereof with high precision. Besides, there is such a problem that, since a heavily doped PN junction is formed by forming the gate regions in the source regions, an increase in junction current cannot be avoided. The present invention provides a normally-off power JFET and a manufacturing method thereof and forms the gate regions according to a multi-epitaxial method which repeats a process including epitaxial growth, ion implantation, and activation annealing a plurality of times. |
| US09543394B2 |
Quantum rod and method of fabricating the same
A quantum rod includes a core of ZnS semiconductor particle having a rod shape; and a transition metal with which the core is doped and which is biased at one side of a length direction of the core. |
| US09543393B2 |
Group III nitride wafer and its production method
The present invention discloses a group III nitride wafer such as GaN, AlN, InN and their alloys having one surface visually distinguishable from the other surface. After slicing of the wafer from a bulk crystal of group III nitride with a mechanical method such as multiple wire saw, the wafer is chemically etched so that one surface of the wafer is visually distinguishable from the other surface. The present invention also discloses a method of producing such wafers. |
| US09543386B2 |
Semiconductor device with field electrode structures, gate structures and auxiliary diode structures
A semiconductor device includes field electrode structures extending in a direction vertical to a first surface in a semiconductor body. Cell mesas are formed from portions of the semiconductor body between the field electrode structures and include body zones that form first pn junctions with a drift zone. Gate structures between the field electrode structures control a current flow through the body zones. Auxiliary diode structures with a forward voltage lower than the first pn junctions are electrically connected in parallel with the first pn junctions, wherein semiconducting portions of the auxiliary diode structures are formed in the cell mesas. |
| US09543380B2 |
Multi-directional trenching of a die in manufacturing superjunction devices
A method of manufacturing a superjunction device includes providing a semiconductor wafer having at least one die. At least one first trench having a first orientation is formed in the at least one die. At least one second trench having a second orientation that is different from the first orientation is formed in the at least one die. |
| US09543375B2 |
MIM/RRAM structure with improved capacitance and reduced leakage current
Some embodiments of the present disclosure provide an integrated circuit (IC) device including a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes a lower metal capacitor electrode, an upper metal capacitor electrode, and a capacitor dielectric separating the lower metal capacitor electrode from the upper metal capacitor electrode. The capacitor dielectric is made up of an amorphous oxide/nitride matrix and a plurality of metal or metal oxide/nitride nano-particles that are randomly distributed over the volume of amorphous oxide/nitride matrix. |
| US09543372B2 |
Organic light emitting diode display
An organic light emitting diode (OLED) display including a substrate main body; a driving circuit on the substrate main body; an organic light emitting element on the driving circuit; and a front substrate covering the organic light emitting element and coupled to the substrate main body, wherein the driving circuit includes a wire, the wire including a planar portion parallel to a surface of the substrate main body, and a connection portion connected to the planar portion and extending in a direction orthogonal to the substrate main body. |
| US09543370B2 |
Silicon and semiconducting oxide thin-film transistor displays
An electronic device display may have an array of pixel circuits. Each pixel circuit may include an organic light-emitting diode and a drive transistor. Each drive transistor may be adjusted to control how much current flows through the organic light-emitting diode. Each pixel circuit may include one or more additional transistors such as switching transistors and a storage capacitor. Semiconducting oxide transistors and silicon transistors may be used in forming the transistors of the pixel circuits. The storage capacitors and the transistors may be formed using metal layers, semiconductor structures, and dielectric layers. Some of the layers may be removed along the edge of the display to facilitate bending. The dielectric layers may have a stepped profile that allows data lines in the array to be stepped down towards the surface of the substrate as the data lines extend into an inactive edge region. |
| US09543368B2 |
OLED array substrate having black matrix, manufacturing method and display device thereof
An OLED array substrate and a manufacturing method thereof, and a display device provided with the OLED array substrate are disclosed. The OLED array substrate includes a plurality of thin film transistors (2) disposed on a base substrate (1), each thin film transistor (2) being provided with a black matrix (6) thereon, and the black matrix (6) being provided with a via (60); over the black matrix (6) being disposed from bottom to top a first electrode (41), a luminescent layer (43) and a second electrode (42). The first electrode (41) is connected with the thin film transistor (2) through the via (60), and the first electrode (41) disposed over adjacent thin film transistors (2) are separated from each other by a barrier (44). The black matrix can block light emitted by the OLED to prevent TFTs from being illuminated, thereby ensuring the display effect of an active matrix type OLED display device. |
| US09543364B2 |
Electronic devices having displays with openings
An electronic device may have a display. The display may have an active region in which display pixels are used to display images. The display may have one or more openings and may be mounted in a housing associated with the electronic device. An electronic component may be mounted in alignment with the openings in the display. The electronic component may include a camera, a light sensor, a light-based proximity sensor, status indicator lights, a light-based touch sensor array, a secondary display that has display pixels that may be viewed through the openings, antenna structures, a speaker, a microphone, or other acoustic, electromagnetic, or light-based component. One or more openings in the display may form a window through which a user of the device may view an external object. Display pixels in the window region may be used in forming a heads-up display. |
| US09543361B2 |
Organic photoelectronic device including a PN junction and image sensor
An organic photoelectronic device includes a first electrode and a second electrode facing each other, and an active layer between the first electrode and the second electrode, the active layer including a heterojunction of a p-type semiconductor and an n-type semiconductor, the p-type semiconductor including a compound represented by Chemical Formula 1. |
| US09543360B2 |
Tailorable flexible sheet of monolithically fabricated array of separable cells each comprising a wholly organic, integrated circuit adapted to perform a specific function
A flexible sheet of organic polymer material, may include a monolithically fabricated array of one or more types of cells juxtaposed among them to form a multi-cell sheet. Each cell may include a self consistent, organic base integrated circuit, replicated in each cell of same type of the array, and shares, in common with other cells of same type, at least a conductor layer of either an electrical supply rail of the integrated circuit or of an input/output of the integrated circuit. A piece of the multi-cell, sheet including any number of self consistent integrated circuit cells, may be severed from the multi-cell sheet by cutting the sheet along intercell boundaries or straight lines, with a reduced affect on the operability of any cell spared by the cutting. |
| US09543358B2 |
Electronic device and method for fabricating the same
This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a gate where at least a portion of the gate is filled in a semiconductor substrate including an active region defined by an isolation layer; a junction which is disposed over the active region at both side of the gate and includes a metal-containing layer and a first semiconductor layer doped with an impurity and interposed between the active region and the metal-containing layer; and a material layer which is interposed between the junction and the active region to prevent diffusion of the impurity from the first semiconductor layer and defines an opening for coupling the junction to the active region. |
| US09543355B2 |
Dark current reduction for back side illuminated image sensor
A method of fabricating a semiconductor image sensor device is disclosed. A plurality of radiation-sensing regions is formed in a substrate. The radiation-sensing regions are formed in a non-scribe-line region of the image sensor device. An opening is formed in a scribe-line region of the image sensor device by etching the substrate in the scribe-line region. A portion of the substrate remains in the scribe-line region after the etching. The opening is then filled with an organic material. |
| US09543354B2 |
Optoelectronic modules that have shielding to reduce light leakage or stray light, and fabrication methods for such modules
Various optoelectronic modules are described that include an optoelectronic device (e.g., a light emitting or light detecting element) and a transparent cover. Non-transparent material is provided on the sidewalls of the transparent cover, which, in some implementations, can help reduce light leakage from the sides of the transparent cover or can help prevent stray light from entering the module. Fabrication techniques for making the modules also are described. |
| US09543353B2 |
Formation of buried color filters in a back side illuminated image sensor with an ONO-like structure
A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of light-blocking structures is disposed over the second side of the substrate. A passivation layer is coated on top surfaces and sidewalls of each of the light-blocking structures. A plurality of spacers is disposed on portions of the passivation layer coated on the sidewalls of the light-blocking structures. |
| US09543351B2 |
Image sensor, imaging apparatus, and imaging method
There is provided an image sensor including a normal pixel group composed of a plurality of normal pixels, each of the normal pixels having a photoelectric conversion device for photoelectrically converting an incident light, and a detection pixel configured to detect a light incident from a neighboring pixel by the photoelectric conversion device within an effective pixel area of the normal pixel group. |
| US09543350B2 |
Solid-state imaging device and camera including discrete trench isolation structure
A solid-state imaging device including is provided. The solid-state imaging device includes: pixels arrayed; a photoelectric conversion element in each of the pixels; a read transistor for reading electric charges photoelectrically-converted in the photoelectric conversion elements to a floating diffusion portion; a shallow trench element isolation region bordering the floating diffusion portion; and an impurity diffusion isolation region for other element isolation regions than the shallow trench element isolation region. |
| US09543348B2 |
Backlight image sensor chip having improved chip driving performance
The present invention relates to a backlight image sensor chip having improved chip driving performance, in which a region other than a pad region, on which a conductive pad is formed, and a sensing region, on which an optical filter is formed, is used as a region for auxiliary driving so that additional functions such as auxiliary power supply, auxiliary signal transmission and auxiliary operation control can be performed, without additional process, in the backlight image sensor chip having a restricted area, thereby improving the chip driving performance. |
| US09543347B2 |
Stress released image sensor package structure and method
A sensor package that includes a substrate with opposing first and second surfaces. A plurality of photo detectors are formed on or under the first surface and configured to generate one or more signals in response to light incident on the first surface. A plurality of contact pads are formed at the first surface and are electrically coupled to the plurality of photo detectors. A plurality of holes are each formed into the second surface and extending through the substrate to one of the contact pads. Conductive leads each extend from one of the contact pads, through one of the plurality of holes, and along the second surface. The conductive leads are insulated from the substrate. One or more trenches are formed into a periphery portion of the substrate each extending from the second surface to the first surface. Insulation material covers sidewalls of the one or more trenches. |
| US09543346B2 |
Imaging element and imaging device
An imaging element according to the present disclosure includes: a first pixel and a second pixel each including a light receiving section and a light condensing section, in which the light receiving section includes a photoelectric conversion element, and the light condensing section is configured to allow entering light to be condensed toward the light receiving section; a trench provided between the first pixel and the second pixel; a first light shielding film embedded in the trench; and a second light shielding film provided on part of a light receiving surface of the light receiving section of the second pixel, in which the second light shielding film is continuous with the first light shielding film. |
| US09543343B2 |
Mechanisms for forming image sensor device
Embodiments of mechanisms for forming an image sensor device are provided. The image sensor device includes a semiconductor substrate and a photodetector in the semiconductor substrate. The image sensor device also includes a dielectric layer over the semiconductor substrate, and the dielectric layer has a recess aligned with the photodetector. The image sensor device further includes a filter in the recess of the dielectric layer. In addition, the image sensor device includes a shielding layer between the dielectric layer and the semiconductor substrate and surrounding the filter. |
| US09543341B2 |
Solid-state imaging device and electronic apparatus
A solid-state imaging device includes a layout in which one sharing unit includes an array of photodiodes of 2 pixels by 4×n pixels (where, n is a positive integer), respectively, in horizontal and vertical directions. |
| US09543339B2 |
Array substrate and method of fabricating the same
An array substrate includes an oxide semiconductor layer; an etch stopper including a first contact hole exposing each of both sides of the oxide semiconductor layer; source and drain electrodes spaced apart from each other with the oxide semiconductor layer therebetween; a first passivation layer including a contact hole exposing each of both ends of the oxide semiconductor layer and each of ends of the source and drain electrode that oppose the both ends of the oxide semiconductor layer, respectively; and a connection pattern at the second contact hole contacting both the oxide semiconductor layer and each of the source and drain electrodes. |
| US09543338B2 |
Array substrate, method for manufacturing the same, and display device
The present invention provides a method for manufacturing an array substrate comprising: sequentially forming an adhesion enhancement layer, a copper-bearing metal layer and a photoresist layer on a substrate, and respectively forming a reserved region and a removal region by performing exposure and development on the photoresist layer using a mask plate, simultaneously processing the adhesion enhancement layer, the copper-bearing metal layer and the photoresist layer in the removal region by a single wet etching process, to form an adhesion enhancement intermediate layer corresponding to the adhesion enhancement layer, a copper-bearing metal intermediate layer corresponding to the copper-bearing metal layer and the photoresist layer thereon in the reserved region; simultaneously processing the adhesion enhancement intermediate layer, the copper-bearing metal intermediate layer and the photoresist layer by a dry etching process, then stripping off the photoresist layer, to form a patterned adhesion enhancement layer and a patterned copper-bearing metal layer respectively. |
| US09543336B2 |
Thin film transistor array panel
A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode. |
| US09543334B2 |
Display panel
A display panel is provided. The display panel includes a substrate including a non-display region containing a thin film transistor, which includes a semiconductor layer; a first insulating layer; a first metal layer; a second insulating layer; a first and second via hole series disposed adjacent to the respective opposite sides of the first metal layer. The first via hole series includes a plurality of first via holes, and the second via hole series includes a plurality of second via holes. A second metal layer includes a first portion and a second portion. The minimum distance between an edge of the first portion and an edge of the first metal layer is a first distance, and the minimum distance between an edge of the second portion and another edge of the first metal layer is a second distance, and the second distance is greater than the first distance. |
| US09543333B2 |
Display apparatus
A display apparatus including a display area on a substrate, the display area including at least a display device; and a non-display area adjacent to the display area, wherein the non-display area includes a pull-in area, the pull-in area includes a wiring unit that includes a plurality of wires electrically connected to the display device of the display area, and a conductive pattern unit that is electrically connected to the display device and that includes at least one area separated from and overlapping the wiring unit, and the plurality of wires of the wiring unit are not arranged in parallel such that respective angles between an edge of the display area and at least two of the plurality of wires are different. |
| US09543329B2 |
Thin film transistor substrate and method for manufacturing the same
A thin film transistor substrate includes: a gate insulating film that covers a gate electrode and a common electrode; a transparent oxide film selectively disposed on the gate insulating film; a source electrode and a drain electrode that are spaced from each other on the transparent oxide film; and a light transmissive pixel electrode electrically connected to the drain electrode. The transparent oxide film includes a conductive region and a semiconductor region. The conductive region is disposed in a lower portion of the source electrode and the drain electrode and disposed in a portion that continues from the lower portion of the drain electrode, extends to part of an upper portion of the common electrode, and forms the pixel electrode. The semiconductor region is disposed in a portion corresponding to a lower layer in a region between the source electrode and the drain electrode. |
| US09543328B2 |
Metal oxide TFT device and method for manufacturing the same
A method for manufacturing a metal oxide TFT device is provided. The method includes: selecting a substrate and forming a gate electrode on a first side of the substrate; sequentially depositing an insulating layer, a semiconductor layer, and a photoresist layer on the gate electrode; using the gate electrode as a photomask, exposing from a second side of the substrate and reserving the photoresist layer aligning to the gate electrode; depositing an electrode layer on the semiconductor layer and the reserved photoresist layer; stripping the reserved photoresist layer and lifting off the electrode layer stacked on the reserved photoresist layer; etching a part of the reserved electrode layer and the semiconductor layer, and forming a source electrode, a drain electrode, and a semiconductor island. The method realizes a self-alignment using the gate electrode as the photomask when forming the source, drain electrodes and the channel. Therefore, the manufacturing processes become simple and more accurate. |
| US09543327B2 |
Semiconductor device having insulation layer with concave portion and semiconductor layer that includes channel area disposed at concave portion, electro-optical device, method of manufacturing semiconductor device, method of manufacturing electro-optical device, and electronic apparatus
A first insulation layer includes a concave portion. A semiconductor layer includes a source area and a drain area, and a channel area disposed at the concave portion of the first insulation layer. A gate insulation layer covers the channel area. A gate electrode is disposed to be opposed to the channel area via the gate insulation layer. A first electrode is one of a source electrode and a drain electrode. A second electrode is the other of the source electrode and the drain electrode. |
| US09543323B2 |
Strain release in PFET regions
A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides. |
| US09543320B2 |
Three-dimensional memory structure having self-aligned drain regions and methods of making thereof
A memory stack structure can be formed through a stack of an alternating plurality of first material layers and second material layers and through an overlying temporary material layer having a different composition than the first and second material layers. The memory stack structure can include a memory film and a semiconductor channel layer. The overlying temporary material layer is removed selective to the stack to form a lateral recess. Portions of the memory film are removed around the lateral recess, and dopants are laterally introduced into an upper portion of the semiconductor channel to form a self-aligned drain region. |
| US09543319B1 |
Vertical channel structure
A vertical channel structure including a substrate, a plurality of stacked structures, a charge storage structure, a channel structure and a dielectric structure is provided. The stacked structures are disposed on the substrate. An opening is located between the stacked structures. The charge storage structure is disposed on a sidewall of the opening. The channel structure is disposed on the charge storage structure and on the substrate at a bottom portion of the opening. The dielectric structure includes first and second dielectric layers. The first dielectric layer is disposed on the channel structure. The second dielectric layer is disposed on the first dielectric layer and seals the opening to form a void in the dielectric structure. A top portion of the second dielectric layer is higher than a top portion of the first dielectric layer. The dielectric structure exposes an upper portion of the channel structure. |
| US09543316B2 |
Semiconductor memory device and method of fabricating the same
Inventive concepts provide semiconductor memory devices and methods of fabricating the same. A stack structure and vertical channel structures are provided on a substrate. The stack structure includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. The vertical channel structures penetrate the stack structure. Conductive pads are disposed on the vertical channel structures. An etch stopper covers sidewalls of the conductive pads. Pad contacts are disposed on the conductive pads to be in contact with the conductive pads. The pad contacts are further in contact with the etch stopper. |
| US09543312B1 |
Method for manufacturing a nonvolatile memory device
A method for manufacturing a nonvolatile memory device in accordance with an embodiment of the present invention may include providing a substrate comprising a cell region and a peripheral region, wherein the peripheral region comprises an NMOS region and a PMOS region; performing a well forming ion implantation over the substrate in the cell region and the NMOS region; performing a threshold voltage adjusting ion implantation over a surface of the substrate in the cell region and the NMOS region; forming a gate pattern comprising a floating gate electrode in the cell region and the peripheral region; and performing a junction ion implantation over a surface of the cell region, wherein the floating gate electrode may have P-type conductivity. |
| US09543310B2 |
Semiconductor storage device having communicated air gaps between adjacent memory cells
A semiconductor storage device according to an embodiment of the invention includes a semiconductor substrate and a plurality of memory cells on the semiconductor substrate. A first film is provided above the memory cells to form air gaps above a memory string in which the memory cells are connected in series. |
| US09543309B2 |
Antifuse memory cells and arrays thereof
An antifuse memory cell includes an antifuse element and a gate PN diode. The antifuse element includes a gate terminal coupled to a word line, a drain terminal coupled to a bit line, and a body terminal. The gate PN diode is coupled between the word line and the gate terminal. |
| US09543308B2 |
Semiconductor device
A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer. |
| US09543307B2 |
Vertical memory devices and methods of manufacturing the same
A method of manufacturing a vertical memory device includes: providing a substrate including a cell array region and a peripheral circuit region; forming a mold structure in the cell array region; forming a mold protection film in a portion of the cell array region and the peripheral circuit region, the mold protection film contacting the mold structure; forming an opening for a common source line that passes through the mold structure and extends in a first direction perpendicular to a top surface of the substrate; forming a peripheral circuit contact hole that passes through the mold protection film and extends in the first direction in the peripheral circuit region; and simultaneously forming a first contact plug and a second contact plug, respectively, in the opening for the common source line and in the peripheral circuit contact hole. |
| US09543303B1 |
Complementary metal oxide semiconductor device with dual-well and manufacturing method thereof
The present invention discloses a dual-well complementary metal oxide semiconductor (CMOS) device and a manufacturing method thereof. The dual-well CMOS device includes a PMOS device region and an NMOS device region. Each of the PMOS and NMOS device regions includes a dual-well (which includes a P-well and an N-well), and each of the PMOS and NMOS device regions includes P-type and N-type lightly doped diffusions (PLDD and NLDD) regions respectively in different wells in the dual well. A separation region is located between the PMOS device region and the NMOS device region, for separating the PMOS device region and the NMOS device region. The depth of the separation region is not less than the depth of any of the P-wells and the N-wells in the PMOS device region and the NMOS device region. |
| US09543302B2 |
Forming IV fins and III-V fins on insulator
A semiconductor structure including: a set of first fins in a pFET region and a set of second fins in an nFET region, the first fins and the second fins are on a buried insulator layer, the first fins have a bottom surface coplanar with a bottom surface of the second fins, the first fins have a first pitch between adjacent first fins that is equal to a second pitch between adjacent second fins, the first fins include a group IV semiconductor material, the second fins include a group III-V semiconductor material. |
| US09543299B1 |
P-N bimodal conduction resurf LDMOS
RESURF-based dual-gate p-n bimodal conduction laterally diffused metal oxide semiconductors (LDMOS). In an illustrative embodiment, a p-type source is electrically coupled to an n-type drain. A p-type drain is electrically coupled to an n-type source. An n-type layer serves as an n-type conduction channel between the n-type drain and the n-type source. A p-type top layer is disposed at the surface of the substrate of said semiconductor device and is disposed above and adjacent to the n-type layer. The p-type top layer serves as a p-type conduction channel between the p-type source and the p-type drain. An n-gate controls current flow in the n-type conduction channel, and a p-gate controls current flow in the p-type conduction channel. |
| US09543296B2 |
ESD clamp with auto biasing under high injection conditions
In a dual direction ESD protection circuit formed from multiple base-emitter fingers that include a SiGe base region, and a common sub-collector region, the I-V characteristics are adjusted by including P+ regions to define SCR structures that are operable to sink positive and negative ESD pulses, and adjusting the layout and distances between regions and the number of regions. |
| US09543295B2 |
Semiconductor device
A semiconductor device that includes transistors with different threshold voltages is provided. Alternatively, a semiconductor device including a plurality of kinds of circuits and transistors whose electrical characteristics are different between the circuits is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor includes an oxide semiconductor, a conductor, a first insulator, a second insulator, and a third insulator. The conductor has a region where the conductor and the oxide semiconductor overlap with each other. The first insulator is positioned between the conductor and the oxide semiconductor. The second insulator is positioned between the conductor and the first insulator. The third insulator is positioned between the conductor and the second insulator. The second insulator has a negatively charged region. |
| US09543292B2 |
Field effect transistor with integrated Zener diode
One or more Zener diodes and a field effect transistor having a drain connected in series with the one or more Zener diodes are integrally formed by a plurality of doped regions in the same P-type semiconductor substrate and separated by a punch through stop region. An N-type region is formed under the one or more Zener diodes. |
| US09543290B2 |
Normally-off junction field-effect transistors and application to complementary circuits
A junction field-effect transistor (JFET) with a gate region that includes two separate sub-regions having material of different conductivity types and/or a Schottky junction that substantially suppresses gate current when the gate junction is forward-biased, as well as complementary circuits that incorporate such JFET devices. |
| US09543287B2 |
Integrated circuit and method for fabricating an integrated circuit equipped with a temperature probe
This integrated circuit comprises: a substrate, a first electrical conductor comprising a first end, the first electrical conductor being electrically insulated from the substrate, a second electrical conductor comprising a second end, the second electrical conductor being electrically insulated from the substrate and electrically insulated from the first electrical conductor except at the second end which is mechanically and electrically directly in contact with the first end to form an electrical junction. The first and second ends are entirely buried to at least 5 μm depth inside the substrate and produced, respectively, in different first and second materials chosen for the absolute value of the Seebeck coefficient of the junction to be greater than 1 μV/K at 20° C. such that the combination of these first and second conductors forms a temperature probe. |
| US09543286B2 |
Semiconductor device
A semiconductor device which is capable of operating at an operation frequency “f”, includes a substrate, a first element unit and a second element unit. The substrate has a thermal diffusion coefficient “D”. The first element unit is formed on the substrate. The first element includes a first active element. The second element unit is adjacent to the first element unit on the substrate. The second element includes a second active element. The second active element acts on a different timing from the first active element. Moreover, a distance of between a first gravity center of the first element unit and a second gravity center of the second element unit is equal to or less than twice of a thermal diffusion length (D/πf)1/2. |
| US09543285B2 |
Display panel
A display panel including a plurality of sub-pixel groups arranged repeatedly to form a pixel array. Each of the sub-pixel groups includes a plurality of first pixel units, a plurality of second pixel units and a plurality of third pixel units. Each of the first pixel units includes a first color sub-pixel and a second color sub-pixel, each of the second pixel units includes the second color sub-pixel and a third color sub-pixel, and each of the third pixel units includes the first color sub-pixel and the third color sub-pixel. The first color sub-pixel, the second color sub-pixel and the third color sub-pixel are sub-pixels having three different colors. At least a part of the first pixel units and at least a part of the second pixel units are arranged along a first direction, and the first direction is tilted relative to a column direction of the pixel array. |
| US09543284B2 |
3D packages and methods for forming the same
Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening. |
| US09543282B2 |
Optical sensor package
One or more embodiments are directed to system in package (SiP) for optical devices, including proximity sensor packaging. One embodiment is directed to an optical package that includes a stacked arrangement with a plurality of optical devices arranged over an image sensor processor die that is coupled to a first substrate. Between the two optical devices and the image sensor processor die there is provided at least a second substrate. In one embodiment, the optical package is a proximity sensor package and the optical devices include a light-emitting diode die and a light-receiving diode die. In one embodiment, the light-emitting diode die is secured to a surface of the second substrate and the light-receiving diode die is secured to a surface of a third substrate. The second and the third substrate may be secured to a surface of the image sensor processor die or to a surface of encapsulation material. |
| US09543281B2 |
Semiconductor device having a substrate and input and output electrode units
A plurality of arm elements is arrayed along a first direction of a substrate. Each arm element includes a plurality of semiconductor elements connected in parallel. Each arm element is configured such that a plurality of semiconductor elements is arrayed along a second direction of the substrate which is perpendicular to the first direction and separated into a first element group and a second element group. The substrate includes a first region where the semiconductor element included in the first element group is arranged and a second region where the semiconductor element included in the second element group is arranged, and the first region and the second region are separated along the second direction. An input electrode unit and an output electrode unit are arranged along the first direction in a region provided between the first region and the second region on the substrate. |
| US09543279B2 |
Method of manufacturing a single light-emitting structure
The instant disclosure provides a light-emitting module and a method of manufacturing a single light-emitting structure. The light-emitting module includes two identical light-emitting structures disposed on the same plane. One of the two light-emitting structures disposed on the plane is rotated by 180 degrees relative to the other light-emitting structure, and the two light-emitting structures are connected to each other. Each light-emitting structure includes a base, a conducting element, a light-emitting element and an encapsulation element. The conducting element includes a plurality of conductors separated from each other and passing through the base body, where the number of the conductors is N and N>1. The light-emitting element includes at least one light-emitting chip electrically connected between at least two of the conductors. The encapsulation element includes a transparent encapsulation body disposed on the base to cover the conducting element and the light-emitting element. |
| US09543278B2 |
Semiconductor device with discrete blocks
A semiconductor device and a method of manufacture are provided. In particular, a semiconductor device using blocks, e.g., discrete connection blocks, having through vias and/or integrated passive devices formed therein are provided. Embodiments such as those disclosed herein may be utilized in PoP applications. In an embodiment, the semiconductor device includes a die and a connection block encased in a molding compound. Interconnection layers may be formed on surfaces of the die, the connection block and the molding compound. One or more dies and/or packages may be attached to the interconnection layers. |
| US09543274B2 |
Semiconductor device packages with improved thermal management and related methods
Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack of semiconductor dice may include vias extending through each semiconductor die of the stack for electrically interconnecting the semiconductor dice in the stack to one another and to the substrate. Another semiconductor die may be electrically connected to the stack of semiconductor dice and may be located on a side of the stack of semiconductor dice opposing the substrate. The other semiconductor die may be a heat-generating component configured to generate more heat than each semiconductor die of the stack of semiconductor dice. Electrical connectors may be located laterally adjacent to the vias and may form electrical connections between the substrate and the other semiconductor die in isolation from integrated circuitry of the semiconductor dice in the stack. |
| US09543269B2 |
System-level packaging methods and structures
A system-level packaging method includes providing a packaging substrate having a first functional surface and a second surface with wiring arrangement within the packaging substrate and between the first functional surface and the second surface. The method also includes forming at least two package layers on the first functional surface of the packaging substrate, wherein each package layer is formed by subsequently forming a mounting layer, a sealant layer, and a wiring layer. Further, the method includes forming a top sealant layer and planting connection balls on the second functional surface of the packaging substrate. |
| US09543268B2 |
Electronic component, method of manufacturing same, composite module including electronic component, and method of manufacturing same
A method of manufacturing a composite module prevents a connection electrode electrically coupled to a functional element from separating from a first principal surface of an element substrate. A transmission filter element, a reception filter element, connection electrodes electrically coupled to the transmission filter element and the reception filter element, and an insulating layer surrounding the transmission filter element, the reception filter element, and the connection electrodes are disposed on a first principal surface of an element substrate. The insulating layer covers at least a portion of the surface of each of the connection electrodes. Because the portion of the surface of each of the connection electrodes in an exposed state is covered with the insulating layer, the connection electrodes electrically coupled to the transmission filter element and the reception filter element are prevented from separating from the first principal surface of the element substrate. |
| US09543267B2 |
Ultra fine pitch wedge for thicker wire
An ultra-fine pitch wedge bonding tool and method for its manufacture are disclosed. The wedge tool is formed with a foot width calculated to enable accurate bonding of wires separated at an ultra-fine pitch. The wedge tool is made out of a tungsten carbide alloy having characteristics conforming to specified constraints that lead to improved performance and enable the use of thicker wire. A pocket is formed at the tip of the wedge tool and a wire feeding hole is formed from the rear side of the tool and exiting inside the pocket, at an elevation above the bonding foot. Side walls are provided on both sides of the pocket to guide the wire exiting the feed hole inside the pocket towards the bonding foot. |
| US09543261B2 |
Designs and methods for conductive bumps
Methods, techniques, and structures relating to die packaging. In one exemplary implementation, a die package interconnect structure includes a semiconductor substrate and a first conducting layer in contact with the semiconductor substrate. The first conducting layer may include a base layer metal. The base layer metal may include Cu. The exemplary implementation may also include a diffusion barrier in contact with the first conducting layer and a wetting layer on top of the diffusion barrier. A bump layer may reside on top of the wetting layer, in which the bump layer may include Sn, and Sn may be electroplated. The diffusion barrier may be electroless and may be adapted to prevent Cu and Sn from diffusing through the diffusion barrier. Furthermore, the diffusion barrier may be further adapted to suppress a whisker-type formation in the bump layer. |
| US09543260B2 |
Segmented bond pads and methods of fabrication thereof
In accordance with an embodiment of the present invention, a semiconductor device includes a first bond pad disposed at a first side of a substrate. The first bond pad includes a first plurality of pad segments. At least one pad segment of the first plurality of pad segments is electrically isolated from the remaining pad segments of the first plurality of pad segments. |
| US09543258B2 |
Semiconductor device and method of forming holes in substrate to interconnect top shield and ground shield
A semiconductor device includes a multi-layer substrate. A ground shield is disposed between layers of the substrate and electrically connected to a ground point. A plurality of semiconductor die is mounted to the substrate over the ground shield. The ground shield extends beyond a footprint of the plurality of semiconductor die. An encapsulant is formed over the plurality of semiconductor die and substrate. Dicing channels are formed in the encapsulant, between the plurality of semiconductor die, and over the ground shield. A plurality of metal-filled holes is formed along the dicing channels, and extends into the substrate and through the ground shield. A top shield is formed over the plurality of semiconductor die and electrically and mechanically connects to the ground shield through the metal-filled holes. The top and ground shields are configured to block electromagnetic interference generated with respect to an integrated passive device disposed in the semiconductor die. |
| US09543256B2 |
Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping, and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness. |
| US09543255B2 |
Reduced-warpage laminate structure
A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively patterned high-modulus dielectric material that balances a differential stress between the conductive layer and the dielectric layer to mechanically stiffen the laminate structure and reduce warpage. |
| US09543253B2 |
Method for shaping a laminate substrate
A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate. |
| US09543246B2 |
Semiconductor device
One semiconductor device includes one parallel transistor for connecting in parallel multiple vertical transistors disposed in an active region on a semiconductor substrate. The parallel transistor includes semiconductor pillars that project out in a direction perpendicular to a main surface of the semiconductor substrate; a lower diffusion layer that is disposed below the semiconductor pillars; upper diffusion layers that are each disposed on an upper section of the semiconductor pillars; and gate electrodes disposed, with a gate insulator film therebetween, on the entire side surfaces of the semiconductor pillars. The upper diffusion layers are connected to one upper contact plug that is disposed over the upper diffusion layers. |
| US09543245B2 |
Semiconductor sensor device and method of producing a semiconductor sensor device
The semiconductor device comprises a substrate (1) of semiconductor material with a front side (4) and an opposite rear side (7), a wiring layer (5) at the front side (4), a further wiring layer (8) at the rear side (7), and a through-substrate via (3) connecting the wiring layer (5) and the further wiring layer (8). A hot plate (24) is arranged on or in the substrate, and a sensor layer (21) is arranged in the vicinity of the hot plate. A mold compound (14) is arranged on the rear side (7) above the substrate (1), a cavity (17) is formed in the mold compound (14) to accommodate the sensor layer (21), and the cavity (17) is covered with a membrane (15). |
| US09543244B2 |
Hybrid package transmission line circuits
“Hybrid” transmission line circuits employing multiple interconnect levels for the propagation, or return, of a single signal line across a package length are described. In package transmission line circuit embodiments, a signal line employs co-located traces in two different interconnect levels that are electrically coupled together. In further embodiments, a reference plane is provided above, below or co-planar with at least one of the co-locate traces. In embodiments, a balanced signal line pair includes first and second co-located traces in two adjacent interconnect levels as a propagation signal line and third and fourth co-located traces in the two adjacent interconnect levels as a return signal line with a ground plane co-planar with, and/or above and/or below the two adjacent interconnect levels. |
| US09543243B2 |
Low-noise arrangement for very-large-scale integration differential input/output structures
Embodiments of the invention provide low-noise arrangements for very-large-scale integration (VLSI) differential input/output (I/O) structures (I/O pins, solder bumps, vias, etc.). Novel geometries are described for arranging differential pairs of I/O structures in perpendicular or near-perpendicular “quads.” The geometries effectively place one differential pair on or near the perpendicular bisector of its adjacent differential pair, such that field cancellation and differential reception can substantially eliminate noise without the need for added spacing or shields. By exploiting these effects, embodiments can suppress noise, independent of I/O structure spacing, and arbitrarily small spacings are permitted. Such arrangements can be extended into running chains, and even further into arrays of parallel chains. The parallel chains can be separated by supply structures (e.g., power supply bumps, or the like), and such supply structures can supply power to the I/O circuits of the IC, while also shielding adjacent chains from each other. |
| US09543241B2 |
Interconnect array pattern with a 3:1 signal-to-ground ratio
An electronic device including a plurality of interconnects are orthogonally arranged in a grid pattern and evenly spaced by a first distance, the plurality of interconnects include: a first conductor pair with conductors arranged next to each other in a first direction, the first direction is oriented diagonally relative to the orthogonal grid pattern, a second conductor pair with conductors arranged next to each other in a second direction substantially perpendicular to the first direction, each conductor of the second conductor pair is spaced by the first distance from each signal conductor of the first conductor pair, and a third conductor pair with conductors arranged next to each other in a third direction substantially parallel to the first direction, each conductors of the third conductor pair is spaced by the first distance from one of the signal elements of the second conductor pair. |
| US09543237B2 |
Semiconductor package structure
A semiconductor package structure includes a lead frame, a chip and a molding compound. The lead frame includes a tray pad and a plurality of leads. Two of the leads are different in height positions. The chip is disposed on the tray. The molding compound encapsulates the chip and a portion of each lead. |
| US09543236B2 |
Pad configurations for an electronic package assembly
Embodiments of the present disclosure provide an electronic package assembly comprising a solder mask layer, the solder mask layer having at least one opening, and a plurality of pads coupled to the solder mask layer, wherein at least one pad of the plurality of pads includes (i) a first side, (ii) a second side, the first side being disposed opposite to the second side, (iii) a terminal portion and (iv) an extended portion, wherein the first side at the terminal portion is configured to receive a package interconnect structure through the at least one opening in the solder mask layer, the package interconnect structure to route electrical signals between a die and another electronic device that is external to the electronic package assembly, and wherein the second side at the extended portion is configured to receive one or more electrical connections from the die. |
| US09543231B2 |
Stacked semiconductor package
Provided is a stacked semiconductor package which minimizes a limitation on a design of a lower semiconductor chip due to a characteristic of an upper semiconductor chip stacked on the lower chip. The stacked semiconductor package includes a lower chip having a through electrode area in which a plurality of through electrodes are disposed; and at least one upper chip stacked on the lower chip and having a pad area in which a plurality of pads corresponding to the plurality of through electrodes are disposed. The pad area is disposed along a central axis bisecting an active surface of the upper chip. The central axis where the pad area of the upper chip is disposed is placed at a position which is shifted from a central axis in a longitudinal direction of an active surface of the lower chip. |
| US09543227B2 |
Semiconductor device
A semiconductor device (10) includes a metallic base plate (22) provided with an upper surface (22a) and a lower surface (22b), a plurality of insulating substrates (24) provided on the upper surface (22a), and a plurality of semiconductor elements (26) and (28) mounted side by side on the respective insulating substrates (24). Annular grooves (50) and (52) for storing insulating grease are provided on the lower surface (22b) of the base plate (22). A surface (40a) of a cooling fin (40) is superimposed on the lower surface (22b) with insulating grease (42) interposed therebetween and insides of the annular grooves (50) and (52) are filled with the insulating grease (42). |
| US09543226B1 |
Heat sink for a semiconductor chip device
A heat sink for a semiconductor chip device includes cavities in a lower surface thereof for receiving electrical components on a top surface of the semiconductor chip, and a pedestal extending through an opening in the semiconductor chip for contacting electrical components on a bottom surface of the semiconductor chip. A lid may also be provided on the bottom surface of the semiconductor chip for protecting the electrical components and for heat sinking the electrical components to an adjacent device or printed circuit board. |
| US09543212B2 |
Preventing over-polishing of poly gate in metal-gate CMP
A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device that includes a first gate in a first-type transistor region and a second gate in a second-type transistor region, forming an interlayer dielectric layer on the semiconductor substrate, and planarizing the interlayer dielectric layer to expose the surface of the first and second gates. The method also includes forming a hard mask layer on the second gate, removing the first gate using the hard mask layer as a mask to form a trench, forming sequentially a work function metal layer and a metal gate layer in the trench, and removing a portion of the first work function metal layer and a portion of the metal gate layer that are higher than the interlayer dielectric layer to form a metal gate. |
| US09543207B2 |
Substrate dividing method
A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method comprises the steps of irradiating a semiconductor substrate 1 having a front face 3 formed with functional devices 19 with laser light while positioning a light-converging point within the substrate, so as to form a modified region including a molten processed region due to multiphoton absorption within the semiconductor substrate 1, and causing the modified region including the molten processed region to form a starting point region for cutting; and grinding a rear face 21 of the semiconductor substrate 1 after the step of forming the starting point region for cutting such that the semiconductor substrate 1 attains a predetermined thickness. |
| US09543206B2 |
Wafer die separation
A method of singulating a wafer starts with fracturing the wafer. The method may also include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet. |
| US09543203B1 |
Method of fabricating a semiconductor structure with a self-aligned contact
A method of fabricating a semiconductor structure includes the following steps: forming a first interlayer dielectric on a substrate; forming a gate electrode on the substrate so that the periphery of the gate electrode is surrounded by the first interlayer dielectric; forming a patterned mask layer comprising at least a layer of organic material on the gate electrode; forming a conformal dielectric layer to conformally cover the layer of organic material; and forming a second interlayer dielectric to cover the conformal dielectric layer. |
| US09543201B2 |
Method for forming three-dimensional interconnection, circuit arrangement comprising three-dimensional interconnection, and metal film-forming composition for three-dimensional interconnection
In a method for forming a three-dimensional interconnection, a contact plug is formed within a through hole provided in a substrate and an upper wire formed on an upper side of the substrate and a lower wire formed on a lower side are electrically connected to one another by the contact plug. A coating film is formed on an upper surface of the substrate and inner surface of the through hole by applying a metal film-forming composition containing at least one salt of and a particle of a metal to the substrate provided with the through hole. A metal film is formed by heating the coating film, and plated by filling up the through hole by depositing a conductor on the metal film by a plating process using the metal film as a seed layer. An excess conductor deposited in the plating is removed by a chemical mechanical polishing process. |
| US09543198B2 |
Structure and method for forming interconnect structure
A method for forming a semiconductor structure includes providing a semiconductor substrate and forming a dielectric layer over the semiconductor substrate. An opening is formed in the dielectric layer. A conductive line is formed in the opening, wherein the conductive line has an open void formed therein. A sealing metal layer is formed overlying the conductive line, the dielectric layer, and the open void, wherein the sealing metal layer substantially fills the open void. The sealing metal layer is planarized so that a top surface thereof is substantially level with a top surface of the conductive line. An interconnect feature is formed above the semiconductor substrate, wherein the interconnect feature is electrically coupled with the conductive line and the sealing metal layer-filled open void. |
| US09543196B2 |
Methods of fabricating semiconductor devices using nanowires
Methods of fabricating a semiconductor device may include forming guide patterns exposing base patterns, forming first nanowires on the base patterns by performing a first nanowire growth process, forming a first molding insulating layer between the first nanowires, forming holes exposing surfaces of the base patterns by removing the nanowires, and forming first electrodes including a conductive material in the holes. |
| US09543194B2 |
Semiconductor device and method of manufacturing the same
In one embodiment, a semiconductor device includes a first insulator, and conductors and second insulators alternately provided on the first insulator. Each second insulator of the second insulators has a first side face adjacent to one of the conductors via a first air gap, a second side face adjacent to one of the conductors via a second air gap, first lower faces in contact with the first insulator, and second lower faces provided above the first insulator via third air gaps. |
| US09543193B2 |
Non-hierarchical metal layers for integrated circuits
An integrated circuit structure includes a semiconductor substrate, and a first metal layer over the semiconductor substrate. The first metal layer has a first minimum pitch. A second metal layer is over the first metal layer. The second metal layer has a second minimum pitch smaller than the first minimum pitch. |
| US09543186B2 |
Substrate support with controlled sealing gap
Embodiments of substrate supports are provided herein. In some embodiments, a substrate support may include a support plate having a support surface to support a substrate, a support ring to support a substrate at a perimeter of the support surface; and a plurality of first support elements disposed in the support ring, wherein an end portion of each of the first support elements is raised above an upper surface of the support ring to define a gap between the upper surface of the support ring and an imaginary plane disposed on the end portions of the plurality of first support elements. |
| US09543185B2 |
Packaging process tools and systems, and packaging methods for semiconductor devices
Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon. |
| US09543181B2 |
Replaceable electrostatic chuck sidewall shield
A replaceable electrostatic chuck sidewall shield is provided. The replaceable electrostatic chuck sidewall shield fills or partially fills an indentation located between a base member and a top member of an electrostatic chuck, such that the replaceable electrostatic chuck sidewall shield may protect an epoxy in the indentation or may replace the epoxy within the indentation. The replaceable electrostatic chuck sidewall shield may be fully contained with the indentation. The replaceable electrostatic chuck sidewall shield may also cover an epoxy in the indentation such that the replaceable electrostatic chuck sidewall shield protrudes beyond the indentation. In an alternate embodiment, the replaceable electrostatic chuck sidewall shield substantially covers the area in which a conductive pole is embedded in a bipolar electrostatic chuck. |
| US09543180B2 |
Apparatus and method for transporting wafers between wafer carrier and process tool under vacuum
An integrated transport device for a wafer carrier includes: an evacuatable chamber for accommodating therein a wafer carrier having a front opening with a cover; a rotatable platform for placing the wafer carrier thereon in the chamber; and an opening/closing device for opening and closing the cover of the wafer carrier placed on the platform at a first position, wherein the platform rotates to set the wafer carrier at the first position and a second position for transporting a wafer to a wafer-handling chamber. |
| US09543178B2 |
Semiconductor wafer stocker apparatus and wafer transferring methods using the same
A semiconductor wafer stocker apparatus includes a body frame, an inlet port to load a wafer shipping box into the body frame, an outlet port to unload the wafer shipping box from the body frame, an automated transfer robot operable to convey the wafer shipping box between the inlet port and the outlet port, and a shelf module within the body frame. The shelf module includes a shelf plate configured to support the wafer shipping box. The shelf plate includes first, second, and third protruding support pins arranged to align with respective grooves in an underside of the wafer shipping box and orient the wafer shipping box with a door thereof facing away from the body frame. The first and second support pins may be closer to the body frame than the third support pin. Related apparatus and methods of operation are also discussed. |
| US09543175B2 |
Package assembly for thin wafer shipping and method of use
A package assembly for thin wafer shipping using a wafer container and a method of use are disclosed. The package assembly includes a shipping container and a wafer container having a bottom surface and a plurality of straps attached thereto placed within the shipping container. The package assembly further includes upper and lower force distribution plates provided within the shipping container positioned respectively on a top side and bottom side thereof. |
| US09543174B1 |
Cassette configurations to support platters having different diameters
A material handling apparatus adapted to support a plurality of disc-shaped platters, such as but not limited to a cassette assembly adapted to support data recording media or substrates during manufacturing. In some embodiments, a cassette assembly includes a base cassette with a base and opposing sidewalls configured to support an outermost perimeter of each of a first plurality of disc-shaped platters having a first diameter. An insert contactingly engages the base cassette. The insert has a plurality of spaced apart grooves to contactingly support an outermost perimeter of each of a second plurality of disc-shaped platters having a different, second diameter. |
| US09543170B2 |
Semiconductor packages and methods of forming the same
Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including forming a first die package, the first die package including a first die, a first electrical connector, and a first redistribution layer, the first redistribution layer being coupled to the first die and the first electrical connector, forming an underfill over the first die package, patterning the underfill to have an opening to expose a portion of the first electrical connector, and bonding a second die package to the first die package with a bonding structure, the bonding structure being coupled to the first electrical connector in the opening of the underfill. |
| US09543169B2 |
Lead frame, method for manufacturing lead frame, semiconductor device, and method for manufacturing semiconductor device
A lead frame includes a die pad and a plurality of lead portions each including an internal terminal and an external terminal. The external terminals of the plurality of lead portions are arranged in an alternately staggered form such that the respective external terminals of a pair of lead portions adjacent to each other are alternatively located on an inside or an outside. A lead portion has an inside region located on the inside of a first external terminal, an outside region located on the outside of the first external terminal, and an external terminal region having the first external terminal. The inside region and the outside region are each formed thin by means of half etching. A maximum thickness of the outside region is larger than a maximum thickness of the inside region. |
| US09543168B2 |
Defects annealing and impurities activation in semiconductors at thermodynamically non-stable conditions
A symmetric multicycle rapid thermal annealing (SMRTA) method for annealing a semiconductor material without the material decomposing. The SMRTA method includes a first long-time annealing at a first temperature at which the material is thermodynamically stable, followed by multicycle rapid thermal annealing (MRTA) at temperatures at which the material is not thermodynamically stable, followed in turn by a second long-time annealing at a second temperature at which the material is thermodynamically stable. The SMRTA method can be used to form p-type and n-type semiconductor regions in doped III-nitride semiconductors, SiC, and diamond. |
| US09543166B2 |
External gettering method and device
Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed. |
| US09543165B2 |
Method of fabricating semiconductor device
A method for fabricating a semiconductor device includes forming a first hard mask (HM) layer over a material layer, forming a patterned second HM layer over the first HM layer. The patterned second HM layer has first trench extending along a first direction. The method also includes forming a patterned resist layer over the second HM layer. The patterned resist layer has a first line opening extending along a second direction, which is perpendicular to the first direction. The first line opening overlaps the first trench and exposes a portion of the second HM layer. The method also includes etching the first HM layer by using the patterned resist layer and the exposed portion of the second HM layer as an etch mask together to form a first hole feature in the first HM layer. |
| US09543163B2 |
Methods for forming features in a material layer utilizing a combination of a main etching and a cyclical etching process
Methods for etching a material layer disposed on the substrate using a combination of a main etching step and a cyclical etching process are provided. The method includes performing a main etching process in a processing chamber to an oxide layer, forming a feature with a first predetermined depth in the oxide layer, performing a treatment process on the substrate by supplying a treatment gas mixture into the processing chamber to treat the etched feature in the oxide layer, performing a chemical etching process on the substrate by supplying a chemical etching gas mixture into the processing chamber, wherein the chemical etching gas includes at least an ammonium gas and a nitrogen trifluoride, wherein the chemical etching process further etches the feature to a second predetermined depth, and performing a transition process on the etched substrate by supplying a transition gas mixture into the processing chamber. |
| US09543152B2 |
MIM capacitors for leakage current improvement
The semiconductor device includes a substrate, a bottom electrode, a capacitor dielectric layer, a top electrode, an etching stop layer, a first anti-reflective coating layer and a capping layer. The bottom electrode is on the substrate. The capacitor dielectric layer is on the bottom electrode. The capacitor dielectric layer has a first region and a second region adjacent to the first region. The top electrode is on the first region of the capacitor dielectric layer. The etching stop layer is on the top electrode. The first anti-reflective coating layer is on the etching stop layer, in which the first anti-reflective coating layer, the etching stop layer and the top electrode together have a sidewall. The capping layer overlies the sidewall, the etching stop layer, the second region of the capacitor dielectric layer, in which the capping layer is formed from oxide or nitride. |
| US09543148B1 |
Mask shrink layer for high aspect ratio dielectric etch
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings. |
| US09543146B2 |
Manufacturing method of semiconductor device that includes forming plural nitride semiconductor layers of identical material
According to one embodiment, a manufacturing method of a semiconductor device, comprising: forming a first nitride semiconductor layer on a substrate using a first temperature; decreasing a substrate temperature to a second temperature lower than the first temperature, after the forming the first nitride semiconductor layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer using the second temperature; increasing the substrate temperature to a third temperature higher than the first temperature, after the forming the second nitride semiconductor layer; and forming a third nitride semiconductor layer on the second nitride semiconductor layer using the third temperature. |
| US09543144B2 |
Vapor deposition of chalcogenide-containing films
Chalcogenide-containing film forming compositions, methods of synthesizing the same, and methods of forming Chalcogenide-containing films on one or more substrates via vapor deposition processes using the Chalcogenide-containing film forming compositions are disclosed. |
| US09543143B2 |
Method for producing amorphous oxide thin film and thin film transistor
A method for producing an amorphous oxide thin film includes: a pre-treatment process of selectively changing a binding state of an organic component, at a temperature lower than a pyrolysis temperature of the organic component, in a first oxide precursor film containing the organic component and In, to obtain a second oxide precursor film in which, when an infrared wave number range of from 1380 cm−1 to 1520 cm−1 in an infrared absorption spectrum obtained by performing a measurement by Fourier transform infrared spectroscopy is divided into an infrared wave number range of from 1380 cm−1 to 1450 cm−1 and an infrared wave number range of from more than 1450 cm−1 to 1520 cm−1, a peak positioned within the infrared wave number range of from 1380 cm−1 to 1450 cm−1 exhibits the maximum value in the infrared absorption spectrum within an infrared wave number range of from 1350 cm−1 to 1750 cm−1; and a post-treatment process of removing the organic component remaining in the second oxide precursor film, to transform the second oxide precursor film into an amorphous oxide thin film containing In. |
| US09543142B2 |
Semiconductor nanocrystals and methods
In one embodiment, a method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and an aromatic solvent, introducing one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, reacting the precursors in the reaction mixture, without the addition of an acid compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals, and wherein an amide compound is formed in situ in the reaction mixture prior to isolating the coated semiconductor nanocrystals. In another embodiment, method for forming a coating comprising a semiconductor material on at least a portion of a population of semiconductor nanocrystals comprises providing a first mixture including semiconductor nanocrystals and a solvent, introducing an amide compound, one or more cation precursors and one or more anion precursors into the first mixture to form a reaction mixture for forming the semiconductor material, and reacting the precursors in the reaction mixture in the presence of the amide compound, under conditions sufficient to grow a coating comprising the semiconductor material on at least a portion of an outer surface of at least a portion of the semiconductor nanocrystals. Semiconductor nanocrystals including coatings grown in accordance with the above methods are also disclosed. |
| US09543141B2 |
Method for curing flowable layer
Methods for forming a semiconductor structure are provided. The method for forming a semiconductor structure includes forming a flowable layer over a substrate and heating the flowable layer to form a cured layer in a curing process. In addition, the curing process is performed under a pressure of over 2 atmospheres, and the flowable layer reacts with precursors in the flowable layer during the curing process. |
| US09543140B2 |
Deposition of boron and carbon containing materials
Methods of depositing boron and carbon containing films are provided. In some embodiments, methods of depositing B,C films with desirable properties, such as conformality and etch rate, are provided. One or more boron and/or carbon containing precursors can be decomposed on a substrate at a temperature of less than about 400° C. In some embodiments methods of depositing silicon nitride films comprising B and C are provided. A silicon nitride film can be deposited by a deposition process including an ALD cycle that forms SiN and a CVD cycle that contributes B and C to the growing film. |
| US09543120B2 |
Blanking device for multi charged particle beams, and multi charged particle beam writing apparatus
A blanking device for multi charged particle beams includes a plurality of individual blanking mechanisms configured to individually deflect a corresponding beam of multi charged particle beams so as to control ON/OFF of the corresponding beam, and a common blanking mechanism configured to include a plurality of electrode groups, each composed of facing electrodes, where an array pitch of a plurality of electrode groups is smaller than or equal to a pitch of the multi charged particle beams, and to collectively deflect the multi charged particle beams in order to control an exposure time. |
| US09543117B2 |
Method of processing a material-specimen
A method for generating a smooth surface in a material-specimen includes generating a substantially smooth, first surface region by removing a first material-volume by particle beam etching. The first material-volume is partially defined by the first surface region. An angle between a beam direction and a surface normal of the first surface region is greater than 80° and less than 90°. The method also includes generating a substantially smooth, second surface region by removing a second material-volume. The second material-volume is partially defined by the first surface region and is partially defined by the second surface region. An angle between the beam direction and a surface normal of the second surface region is less than 60°. |
| US09543116B2 |
Method for verifying characteristics of an electron beam
A method is provided for forming a three-dimensional article through successive fusion of parts of a powder bed. The method includes the steps of: applying a first powder layer on a work table; directing an electron beam from an electron beam source over the work table, the directing of the electron beam causing the first powder layer to fuse in first selected locations according to a pre-determined model, so as to form a first part of a cross section of the three dimensional article, and intensity modulating X-rays from the powder layer or from a clean work table with a patterned aperture modulator and a patterned aperture resolver, wherein a verification of at least one of a size, position, scan speed, or shape of the electron beam is achieved by comparing detected intensity modulated X-ray signals with saved reference values. |
| US09543113B2 |
Charged-particle beam device for irradiating a charged particle beam on a sample
The present invention explains a charged-particle beam device for the purpose of highly accurately measuring electrostatic charge of a sample in a held state by an electrostatic chuck (105). In order to attain the object, according to the present invention, there is proposed a charged-particle beam device including an electrostatic chuck (105) for holding a sample on which a charged particle beam is irradiated and a sample chamber (102) in which the electrostatic chuck (105) is set. The charged-particle beam device includes a potential measuring device that measures potential on a side of an attraction surface for the sample of the electrostatic chuck (105) and a control device that performs potential measurement by the potential measuring device in a state in which the sample is attracted by the electrostatic chuck (105). |
| US09543110B2 |
Reduced trace metals contamination ion source for an ion implantation system
An ion source chamber for ion implantation system includes a housing that at least partially bounds an ionization region through which high energy electrons move from a cathode to ionize gas molecules injected into an interior of the housing; a liner section defining one or more interior walls of the housing interior, wherein each liner section includes a interiorly facing surface exposed to the ionization region during operation the ion implantation system; a cathode shield disposed about the cathode; a repeller spaced apart from the cathode; a plate including a source aperture for discharging ions from the ion source chamber; wherein at least one of the repeller, the liner section, the cathode shield; the plate, or an insert in the plate defining the source aperture comprise silicon carbide, wherein the silicon carbide is a non-stoichiometric sintered material having excess carbon. |
| US09543108B2 |
Rotating X-ray anode with an at least partly radially aligned ground structure
A rotating x-ray anode has an annular focal track. The surface of the focal track has a directed ground structure. Over the circumference of the annular focal track and over the radial extent of the focal track, the alignment of the ground structure is inclined relative to a tangential reference direction in the respective surface portion in each case by an angle that lies in the range from 15°, including, up to and including 90°. A corresponding method for producing a rotating x-ray anode is described. |
| US09543107B2 |
Method and apparatus for generating X-ray radiation
The present invention relates in particular to methods and apparatuses for generating and/or providing X-ray radiation with specific radiation characteristics, in particular with a specific radiation dose rate curve (10). In order to provide simple and cost efficient solution, it is provided according to the invention, that the X-ray radiation is generated and/or provided, by composing and/or adapting the X-ray radiation with the specific radiation characteristics, in particular with the specific radiation dose rate curve (10), proportionally from a first specification X-ray radiation with a defined first radiation characteristics, in particular with a predetermined first radiation dose rate curve (11) and a second specification X-ray radiation, which is different from the first specification X-ray radiation, with defined second radiation characteristics, in particular with a predetermined second radiation dose rate curve (12). |
| US09543104B2 |
Fuse assemblies
A fuse assembly includes a bus bar fuse and a clip. The bus bar fuse has a leg with a slotted opening. The clip surrounds a portion of the leg. The clip includes a first side having a threaded through-hole and a second side extending from the first side at an angle with respect to the first side. A third side extends from the second side at an angle with respect to the second side. The third side includes a through-hole. The threaded through-hole of the clip provides for captivation of the fastener within the clip when mounting the fuse assembly to the fuse mounting block assembly. |
| US09543103B2 |
Activation of human-protecting safety mechanisms using smart materials
The present disclosure relates to a system, for selectively actuating a safety mechanism, to protect against electrical shock, using a transformable material. The system includes the transformable material, being: (1) connectable electrically to an electrical component having an unwanted electrical charge and (2) changeable between a deformed shape and an undeformed shape based on electrical input resulting from the electrical charge at the electrical component. The transformable material is also (3) connected mechanically to the safety mechanism so that change in the transformable material causes movement of the safety mechanism. The transformable material is further (4) configured and arranged in the system to, in response to being exposed to the electrical input, change to its undeformed shape and thereby actuate the safety mechanism. |
| US09543100B2 |
Relay having rows of contacts that are separated by an isolation configuration
A relay is provided having a contact set that is disposed in a cover and in a spring bracket, wherein the rows of contacts are isolated by an isolation configuration comprising at least one fixed partition provided on the cover and at least one oppositely oriented fixed partition provided on the spring bracket, and additionally at least one movable actuator is disposed in the space between the cover and the spring bracket, wherein the isolation configuration comprises two mutually parallel and mutually spaced-apart partitions provided on the cover and one partition provided on the spring bracket engaging between the partitions provided on the cover. |
| US09543099B2 |
Direct current relay
The present invention relates to a direct current relay, and more particularly, to a direct current relay capable of reducing an electronic repulsive force generated between a fixed contact and a movable contact by a permanent magnet installed to extinguish an arc. The direct current relay includes: a frame; first and second fixed contacts spaced from each other with a predetermined distance there between; first and second magnetic substances formed to enclose a lower part of the first and second fixed contacts; a movable contact movable to contact or to be separated from the first and second fixed contacts, having a first movable contact contactable to the first fixed contact, and having a second movable contact contactable to the second fixed contact; and a pair of permanent magnets installed on long sides of the frame. |
| US09543098B2 |
Relay and a method for indicating a relay failure
A relay and a method for indicating a relay failure may be provided, whereby the relay comprises a switch assembly capable of providing a trigger signal based on a switching status; an energisation element capable of energisation to affect the switch assembly; and a light indication for indicating a switching status of the switch assembly. |
| US09543097B2 |
Current control device for solenoid, storage medium storing program for controlling current of solenoid, and method for controlling current of solenoid
A current control device sets a target current value of a solenoid, and sets a duty ratio of a PWM signal outputted to a drive circuit of a solenoid based on the target current value. The target current value is a value that periodically varies in a dither period longer than a PWM period of the PWM signal. A setting period of the target current value and a setting period of the duty ratio are shorter than the dither period. As compared with a configuration where the duty ratio is set in the dither period, a time period from a time a basic current value is changed to a time the duty ratio is renewed is shortened. A operation responsiveness of a movable core of the solenoid improves. |
| US09543095B2 |
Gas circuit breaker
A gas circuit breaker is configured by comprising a tank filled with arc extinguishing gas, a pair of fixed side arc contact and moving side arc contact in the tank, a puffer chamber formed with a puffer cylinder including the moving side arc contact at its end and a fixed piston, and an insulating nozzle, attached to the end of the puffer cylinder, surrounding the moving side arc contact, that forms a flow channel to guide arc extinguishing gas from the puffer chamber to the contacts. A puffer cylinder 104 has a cylindrical member 104a at a breaker side end, an end of the insulating nozzle 101 is provided in the cylindrical member 104a. And the gas circuit breaker is configured by further comprising a hollow moving side main contact 102 at a breaker side end of the cylindrical member 104a, a pressing metal fitting 103 to engage an insulating nozzle 101 in the hollow part of the moving side main contact 102. |
| US09543092B2 |
Control device with optimized coaxiality
A control device, includes a switch (2) with a rotary control rod (20) having a diametrical slot (21) which extends in a plane of reference (P), a molded plastic knob (3) which includes a housing receiving the control rod, the housing including two flexible fingers (31, 32) which are diametrically opposed and provided so as to be resilient radially inward, and two fixed fingers (33, 34) which are diametrically opposed and are connected together via a connecting wall (35) which extends along the plane (P), the connecting wall (35) being received in the diametric slot without any play in order to immobilize the knob in relation to the control rod in a direction (Y) perpendicular to the plane (P), the two flexible fingers holding the knob along the axis (A) by friction or by mechanical or spring-assisted blocking. |
| US09543090B2 |
Keyboards with planar translation mechanism formed from laminated substrates
Keyboards with planar translation effecting mechanisms formed by laminated key guides are disclosed. A key assembly for a keyboard includes a keycap having a touch surface for receiving a press force that moves the keycap from an unpressed position toward a pressed position, the unpressed position and pressed position separated in a press direction and a second direction orthogonal to the press direction. A base is included having a laminated key guide contacting a portion of the keycap to provide a planar translation effecting mechanism to guide the keycap in the press direction and the second direction as the keycap moves from the unpressed position toward the pressed position. |
| US09543089B2 |
Switch device
A switching device includes a holder, an operation knob, a ring-like antenna, and a circuit board on which wire connecting the antenna to an external circuit and a detection means (switching portion) for detecting an operation of the knob are disposed. A light source for illuminating a display on the knob is disposed on the circuit board. A transparent lens member disposed on an outer periphery of the knob transmits a light from the light source so as to illuminate the outer periphery of the knob. A slider with a light guide path for a LED is accommodated in the holder so as to be movable forward and rearward integrally with the operation. The antenna is integral with the lens member. The knob and the slider are disposed in a center hole of the lens member. |
| US09543087B2 |
Contact system
An electrical switching device including at least a nominal contact arrangement, the nominal contact arrangement at least a first nominal contact with a plurality of nominal contact fingers forming a finger cage concentric with respect to a longitudinal axis (z), and at least a mating second nominal contact. An arcing contact arrangement including a first arcing contact and a mating second arcing contact. An arcing contact finger including at its free end a first impact area in which a first contacting to the second arcing contact occurs when closing, the electrical switching device. The first impact area is formed by a first planar surface arranged at an inclination angle (α) larger than zero degrees with respect to the longitudinal axis (z). |
| US09543085B2 |
Non-fusible switch assemblies, line base assemblies, load bus connector assemblies, and operational methods
A non-fusible switch assembly including a line base assembly is disclosed. Line base assembly includes a load bus connector assembly with single-piece lug body, first and second load lugs formed in the lug body, and load-side sliding nuts slidably received in first and second load-side slide features, and load-side stationary contacts positioned directly underneath of the first and second load lugs within a projected footprint of the lug body. Line base assemblies, load lug connector assemblies and methods of operating a line base assembly are provided, as are other aspects. |
| US09543082B1 |
Mounting systems for remote controls
Mounting systems can couple a remote control to a wall, such as a wall of a television. In some embodiments, an adhesive couples the mounting system to the wall. The mounting system can include a clamp configured to secure a cable that charges the remote control. Sliding the remote control into the mounting system can couple the remote control to the cable. |
| US09543078B2 |
Structural composite battery with fluidic port for electrolyte
According to the invention there is provided a fluidic port (8-9) for a refillable structural composite electrical energy storage device (1), and a method of producing same. The device may be a battery or supercapacitor with first and second electrodes (2,3) which are separated by a separator structure (6), wherein the device contains an electrolyte (4) which may further contain active electrochemical reagents. The fluidic port allows the addition, removal of electrolyte fluids, and venting of any outgassing by products. |
| US09543074B2 |
Apparatus and method for wireless power reception, apparatus and method for wireless power transmission, and wireless power transmission system
An apparatus and a method for receiving power wirelessly, and an apparatus and a method for transmitting power wirelessly are provided. The apparatus for transmitting power wirelessly includes: a source resonator configured to transmit power wirelessly to a target resonator through a mutual resonance with the target resonator; a power supply unit configured to supply power to the source resonator; and a matching unit configured to connect a passive device to the power supply unit in series or in parallel to match an output impedance of the power supply unit and an input impedance of the source resonator. |
| US09543068B2 |
Inductor structure and application thereof
The present disclosure relates to composite inductor structures for use in integrated circuits. There is provided a composite inductor structure comprising a first inductor coil and a second inductor coil. The second inductor coil comprises a multi-turn loop that surrounds the first inductor coil. The first inductor coil comprises two multi-turn loops which are connected in a figure-of-eight configuration about a central terminal so as to cause a current flowing in a first loop of the multi-turn loops to circulate around the first loop in a first rotational direction, and a current flowing in a second loop of the multi-turn loops to circulate around the second loop in a second rotational direction opposite the rotational direction of current flow in the first loop, said direction of current flow in the first and second loops being mirror images of each other. |
| US09543064B2 |
Electric machine having a low-mass design in magnetically active parts
An electric machine includes a first magnetic pole with an arrangement of interposed magnetically active layers and magnetically inactive layers, and a second magnetic pole movable relative to the first magnetic pole and spaced from the first magnetic pole by a gap. An electrical conductor operates as a coupling element between an electrical circuit and a magnetic circuit. At an operating time, a common useful magnetic flux for electromechanical energy conversion flows through the magnetic circuit composed of the first magnetic pole, the gap and the second magnetic pole. The magnetically inactive layers have a lower average density than the magnetically active layers. A ratio (k) of the total volume of the magnetically active layers to the combined total volume of the magnetically active and inactive layers fulfills the condition 0.5≦k≦0.8 A method for producing an electric machine are also disclosed. |
| US09543063B2 |
Continuous hydrogen pulverization method and production device of rare earth permanent magnetic alloy
A continuous hydrogen pulverization method of a rare earth permanent magnetic alloy includes: providing a hydrogen adsorption room, a heating dehydrogenation room and a cooling room in series, applying hydrogen adsorption, heating dehydrogenation and cooling on a rare earth permanent magnetic alloy in the production device at the same time, wherein collecting and storing under an inert protection atmosphere can also be provided. Continuous production is provided under vacuum and the inert protection atmosphere in such a manner that an oxygen content of the pulverized powder is low and a proportion of single crystal in the powder is high. |
| US09543060B2 |
High-temperature cable having inorganic material
A high-temperature cable and a method of making the same is provided. The high-temperature cable includes at least one conductor. An inorganic tape is wrapped around the at least one conductor. An armor shell is applied exterior of the inorganic tape. |
| US09543058B2 |
Insulated winding wire
An insulated winding wire may include a conductor and insulation formed around the conductor. The insulation may include a base insulation layer formed around the conductor and having a first dielectric constant (ε1). The insulation may further include an extruded thermoplastic layer formed around the base insulation layer and having a second dielectric constant (ε2). The extruded thermoplastic layer may include (i) at least one polymer comprising a ketone group and (ii) at least one fluoropolymer. A ratio of the dielectric constant (ε2) of the extruded thermoplastic layer to the dielectric constant (ε1) of the base layer at 250° C. may be less than or equal to approximately 1.0. |
| US09543057B2 |
Conductive cellulose-based resin composition
The conductive cellulose-based resin composition of the present invention comprises (A) a cellulose acetate ester having a total degree of acetyl substitution of 0.5 to 1.1 and (B) at least one carbon material selected from the group consisting of single-walled carbon nanotube, multi-walled carbon nanotube, single-layer graphene, multi-layer graphene, fullerene, and carbon black. This conductive cellulose resin composition exhibits high conductivity even without being supplemented with a special resin or a third component. Also, the conductive cellulose-based resin composition can be easily molded in an aqueous system. |
| US09543055B2 |
Positive active material for nonaqueous electrolyte secondary battery, method of manufacturing the positive active material, electrode for nonaqueous electrolyte secondary battery, nonaqueous electrolyte secondary battery and method of manufacturing the secondary battery
An object of the present invention is to provide a positive active material for a nonaqueous electrolyte secondary battery which has a large discharge capacity and is superior in charge-discharge cycle performance, initial efficiency and high rate discharge performance, and a nonaqueous electrolyte secondary battery using the positive active material. The present invention pertains to a positive active material for a nonaqueous electrolyte secondary battery containing a lithium transition metal composite oxide which has a crystal structure of an α-NaFeO2 type, is represented by a compositional formula Li1+αMe1−αO2 (Me is a transition metal element including Co, Ni and Mn, α>0), and has a molar ratio Li/Me of Li to the transition metal element Me of 1.2 to 1.6, wherein a molar ratio Co/Me of Co in the transition metal element Me is 0.02 to 0.23, a molar ratio Mn/Me of Mn in the transition metal element Me is 0.62 to 0.72, and the lithium transition metal composite oxide is observed as a single phase attributed to a space group R3-m on an X-ray diffraction chart when it is electrochemically oxidized up to a potential of 5.0 V (vs. Li/Li+). |
| US09543052B2 |
Containing/transporting charged particles
Particle storing apparatus including only one electric field restraining charged particles, such as antiprotons, in an ultrahigh vacuum from striking a container surface for a half-life of at least 1 hour. Depending on implementation, restraining can be devoid of a magnetic field, and the container can be devoid of cryogenic cooling or need not include a dewar. |
| US09543048B2 |
Storage, transportation and disposal system for used nuclear fuel assemblies
An integrated storage, transportation and disposal system for used fuel assemblies is provided. The system includes a plurality of sealed canisters and a cask sized to receive the sealed canisters in side by side relationship. The plurality of sealed canisters include an internal basket structure to receive a plurality of used fuel assemblies. The internal basket structure includes a plurality of radiation-absorbing panels and a plurality of hemispherical ribs generally perpendicular to the canister sidewall. The sealed canisters are received within the cask for storage and transportation and are removed from the cask for disposal at a designated repository. The system of the present invention allows the handling of sealed canisters separately or collectively, while allowing storage and transportation of high burnup fuel and damaged fuel to the designated repository. |
| US09543047B2 |
System and method for storing fresh and irradiated nuclear fuel
A method for storing nuclear fuel includes transferring a fuel assembly from a long term storage vault to a nuclear reactor core, removing the fuel assembly from the nuclear reactor core, determining a heat generation rate of the irradiated fuel assembly, and transferring the irradiated fuel assembly to one of an interim storage vault and a long term storage vault based on the determined heat generation rate. |
| US09543045B2 |
Nuclear reactor and power generation facility
A nuclear reactor provided with a core including a new fuel part which contains uranium and a burning part in which fuel burns, wherein the burning part moves in a direction toward the new fuel part from the beginning to end of the operation cycle. The nuclear reactor is provided with a reactivity applying mechanism to apply the reactivity which can change the power of the core when the temperature of the coolant which flows through the inside of the core changes and performs control to change the temperature of the coolant which flows through the inside of the core in accordance with the change of power which is demanded for the core. The reactivity applying mechanism includes a gap adjusting plate which supports fuel members. This plate is configured to expand when the core coolant temperature rises. The expansion increases distance between the fuel members. |
| US09543044B2 |
System and method for improving memory performance and identifying weak bits
According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge. |
| US09543039B2 |
Pulse output circuit, shift register, and display device
In a pulse output circuit in a shift register, a power source line which is connected to a transistor in an output portion connected to a pulse output circuit at the next stage is set to a low-potential drive voltage, and a power source line which is connected to a transistor in an output portion connected to a scan signal line is set to a variable potential drive voltage. The variable potential drive voltage is the low-potential drive voltage in a normal mode, and can be either a high-potential drive voltage or the low-potential drive voltage in a batch mode. In the batch mode, display scan signals can be output to a plurality of scan signal lines at the same timing in a batch. |
| US09543035B2 |
Transmission error detector for flash memory controller
In one aspect, the present disclosure provides a storage device for accounting for transmission errors to improve a usable life span of memory blocks. In some embodiments, the storage device includes: a memory array including a plurality of memory blocks; and a memory controller in communication with the memory array via an interface, wherein the memory controller is configured to detect an error event associated with data from one of the plurality of memory blocks; determine an origin of the error event; increment an error count if the origin of the error event indicates a data error in the one of the plurality of memory blocks and not if the origin of the error event indicates a transmission error; compare the error count to a threshold value; and mark the one of the plurality of memory blocks as bad when the error count exceeds the threshold value. |
| US09543034B2 |
Non-volatile memory and a method of operating the same
A non-volatile memory includes a current sensing checking block including a programming status input block comprising a plurality of sub-blocks connected with each other in parallel with respect to a first node; a reference block comprising a plurality of sub-blocks connected with each other in parallel with respect to a second node; an operational amplifier operable to compare voltage levels of the first node and the second node to determine whether a actual number of programming failures for a desired group of cells exceeds a reference number of allowable programming failures of the reference block. |
| US09543033B1 |
Semiconductor memory device, control method, and memory system
According to one embodiment, a semiconductor memory device includes a memory cell array, a first circuit, and a second circuit. The first circuit executes program and read. The program is processing for changing a threshold voltage of a memory cell to a voltage according to data. The data includes first data of a bit and second data of a bit. The program of the second data is executed after the program of the first data. The read includes measuring the threshold voltage. The second circuit manipulates a flag in accordance with execution of the program of the second data. In a case where the second data is a target of the read, the second circuit refers to the flag. In a case where the flag indicates non-execution of the program of the second data, the second circuit aborts the measuring before the measuring of the threshold voltage is completed. |
| US09543027B2 |
Memory chip, memory device, and reading method
A memory chip includes a memory cell array having a plurality of memory cells connected to word lines and bit lines, and a sense amplifier configured to detect data stored in a memory cell that is connected to a selected one of the word lines and a selected one of the bit lines, and a control circuit configured to read data from the memory cell in a first read mode when a first command is received and in a second read mode when a second command is received. A peak or an average value of an operation current that is flowing between power supply and ground terminals of the memory chip during a read operation in the first read mode is less than a peak or an average value of the operation current during a read operation in the second read mode. |
| US09543022B2 |
Semiconductor memory device
A semiconductor memory device includes first and second plugs formed on a semiconductor substrate, a word line between the first and second plugs and above the semiconductor substrate, a first semiconductor pillar extending above the semiconductor substrate through the word line, a second semiconductor pillar extending above the semiconductor substrate through the word line, a first bit line electrically connected to the first semiconductor pillar, and a second bit line electrically connected to the second semiconductor pillar. When writing same data in a first memory cell, which is electrically connected to the first bit line, and a second memory cell, which is electrically connected to the second bit line, a first voltage is applied to the first bit line and a second voltage that is different from the first voltage is applied to the second bit line. |
| US09543015B1 |
Memory array and coupled TCAM architecture for improved access time during search operation
A memory device includes a first ternary content addressable memory (TCAM), a second TCAM, a memory array coupled to the first and second TCAMs, a first priority logic coupled between the first TCAM and the memory array, a second priority logic coupled between the second TCAM and the memory array, and a look-ahead signal generated by the first priority logic and provided to the second priority logic. Match lines from the first and second TCAMs are coupled to respective word lines in the memory array. |
| US09543014B2 |
Memory circuits using a blocking state
A memory circuit with blocking states. In one embodiment, the memory circuit includes a two non-volatile transistors connected in series. The input state of the memory cell and the stored state of the memory cell are configured to be a plurality of states including a zero state, a one state, a no care state, and an input blocking state. When the input state of the memory cell is the blocking state, the memory cell is configured to be in a blocking mode unless the stored state of the memory cell is the no care state. When the stored state of the memory cell is the blocking state, the memory cell is configured to be in the blocking mode unless the input state of the memory cell is the no care state. |
| US09543011B2 |
Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device comprises a cell array including a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells arranged in matrix and connected at intersections of the first and second lines between both lines, each memory cell containing a serial circuit of an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data and a non-ohmic element; and a plurality of access circuits operative to simultaneously access the memory cells physically separated from each other in the cell array. |
| US09543009B2 |
Multiple layer forming scheme for vertical cross point reram
Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, during a forming operation, a cross-point memory array may be biased such that waste currents are minimized or eliminated. In one example, the memory array may be biased such that a first word line comb is set to a first voltage, a second word line comb interdigitated with the first word line comb is set to the first voltage, and selected vertical bit lines are set to a second voltage such that a forming voltage is applied across non-volatile storage elements to be formed. In some embodiments, a memory array may include a plurality of word line comb layers and a forming operation may be concurrently performed on non-volatile storage elements on all of the plurality of word line comb layers or a subset of the plurality of word line comb layers. |
| US09543008B2 |
Electronic device having semiconductor storage cells
Provided are, among others, memory circuits or devices and their applications in electronic devices or systems and various implementations of an electronic device which includes a semiconductor memory unit comprising one or more columns and a date line and a data line bar connected with a column selected among the one or more columns. Each of the one or more columns includes a plurality of storage cells each configured to store 1-bit data, each storage cell including a first and second variable resistance elements; a bit line and a source line connected to the first variable resistance element; connected to the other end of the first variable resistance element; a bit line bar and a source line bar connected to the second variable resistance element; and a driving block configured to latch data of the data line and the data line bar. |
| US09543006B2 |
Non-volatile memory cell and non-volatile memory device
A non-volatile memory cell and a non-volatile memory device are provided. The non-volatile memory cell includes a latch structure, a first read/write circuit, a first memristor, a second read/write circuit and a second memristor. The first read/write circuit controls a writing operation of the first memristor. The second read/write circuit controls a writing operation of the second memristor. When a restore operation is performed, the data in the latch structure is restored by using the resistance difference between the first memristor and the second memristor. The non-volatile device of the invention combines the advantages of fast memory unit and non-volatile memory, and it may work at a high speed and retain data when powered off. |
| US09543005B2 |
Multistage memory cell read
A multistage read can dynamically change wordline capacitance as a function of threshold voltage of a memory cell being read. The multistage read can reduce current spikes and reduce the heating up of a memory cell during a read. A memory device includes a global wordline driver to connect a wordline of a selected memory cell to the sensing circuit, and a local wordline driver local to the memory cell. After the wordline is charged to a read voltage, control logic can selectively enable and disable a portion or all of the global wordline driver and the local wordline driver in conjunction with applying different discrete voltage levels to the bitline to perform a multistage read. |
| US09543004B1 |
Provision of holding current in non-volatile random access memory
Embodiments of the present disclosure describe techniques and configurations for controlling current in a non-volatile random access memory (NVRAM) device. In an embodiment, the NVRAM device may include a plurality of memory cells coupled to a plurality of bit lines forming a bit line node with parasitic capacitance. Each memory cell may comprise a switch device with a required level of a holding current to maintain an on-state of the cell. A voltage supply circuitry and a controller may be coupled with the NVRAM device. The controller may control the circuitry to provide a current pulse that keeps a memory cell in on-state. The pulse may comprise a profile that changes over time from a set point to the holding current level, in response to a discharge of the bit line node capacitance through the memory cell after the set point is achieved. Other embodiments may be described and/or claimed. |
| US09543001B1 |
Programming memory cells
First threshold voltages of one or more memory cells in a memory array are obtained. For each memory cell in the one or more memory cells, a target threshold voltage for the memory cell is identified. A number of programming shots to reach the target threshold voltage of the memory cell is determined based on the first threshold voltage of the memory cell. Respective number of programming shots, which are determined for the one or more memory cells, are applied to the one or more memory cells. Whether respective target threshold voltages for the one or more memory cells are reached is verified upon applying the respective number of programming shots to the one or more memory cells. |
| US09542999B2 |
Semiconductor device
A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier. |
| US09542997B2 |
Memory architecture with local and global control circuitry
A system includes a memory block. The memory block includes a local control circuit that is operable to control a memory operation of the memory block. The local control circuit includes a local sense amplifier. The system also includes a global memory control circuit separate from the memory block, and the global memory control circuit is operable to communicate with the local control circuit. The global memory control circuit includes a global data latch operable to receive a sensed data state from the local sense amplifier. |
| US09542995B2 |
Threshold voltage mismatch compensation sense-amplifiers for static random access memories with multiple differential inputs
Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors. |
| US09542992B2 |
SRAM core cell design with write assist
A static random access memory (SRAM) cell includes a storage unit configured to store a data bit in a storage node. The SRAM cell further includes an access unit coupled to the storage unit. The access unit is configured to transfer current to the storage node when a word line is asserted. The SRAM cell further includes a row header configured to provide current from a power supply when the word line is not asserted, and to not provide current from the power supply when the word line is asserted. The SRAM cell further includes a column header configured to provide current from a power supply when a write column line is not asserted, and to not provide current from the power supply when the write column line is asserted. |
| US09542981B2 |
Self-timed, single-ended sense amplifier
An integrated circuit including a sense amplifier connected to a sense line is provided. The sense amplifier is configured to end a precharge phase of the sense line based on a state of the sense amplifier. A single-ended sense amplifier determines its own precharge level, ends the precharge phase, and starts evaluation as soon as precharge is ended, without waiting for a globally timed signal to end the precharge phase. |
| US09542980B1 |
Sense amplifier with mini-gap architecture and parallel interconnect
A memory array structure includes: a plurality of array sections and a plurality of mini-gaps, wherein each mini-gap is disposed between two array sections of the plurality of array sections. Each mini-gap includes: a local write device, for providing a data signal in response to a write enable signal and a write data signal, the data signal for performing a write operation on a memory cell of an array section; and a local sensor, for outputting a data signal in response to an activation command and a read enable signal. The memory array further includes a control logic for providing the write enable and read enable signals, and at least one main sense amplifier, for providing the write data signal to the local write device, receiving the data signal from the local sensor, and amplifying the received data signal for providing a read data signal to output data lines. |
| US09542974B2 |
Video management system and method for event recording using the same
Provided is a video management apparatus and a method for event recording using the same, which are capable of reducing loss of video data in an event recording. The video management apparatus performs an event recording in cooperation with a network camera to transmit a first frame with basic information of video data and a plurality of second frames with changed information of the video data. The video management apparatus includes a buffer unit to store the first and the plurality of second frames, and eliminate the stored frames according to an external control signal. The video management apparatus further includes an event recording unit to save the first frame and at least one of the second frames stored in the buffer unit, and when detecting an occurrence of events, and frames transmitted from the network camera after the detection of the occurrence of events on a storage medium. |
| US09542972B1 |
Systems and methods for multi-head coefficient based scaling
Systems and method are disclosed relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. One example of the system includes a first equalizer circuit, a second equalizer circuit, a summation circuit, a first multiplication circuit, a second multiplication circuit, and a scalar calculation circuit that is capable of calculating a scalar based upon coefficients that are also provided as inputs to the first equalizer and second equalizer. |
| US09542970B2 |
Light interference module and holographic storage apparatus
A light interference module includes an object lens, a first light-guiding element, and a second light-guiding element. The object lens is configured to project a signal light beam to an optical storage media. The first light-guiding element is configured to project a first reference light beam to the optical storage media, in which the first reference light beam and the signal light beam produce a first interference pattern on the optical storage media. The second light-guiding element is configured to project a second reference light beam to the optical storage media, in which the second reference light beam and the signal light beam produce a second interference pattern on the optical storage media, and the first interference pattern is different from the second interference pattern. |
| US09542969B2 |
Optical recording medium and optical information playback method
When a simple magnification optical system is used in reproduction of a recording medium in which a large number of minute modified regions are three-dimensionally formed inside solid matter, contrast is insufficient and interlayer crosstalk is increased, and therefore, it is impossible to take a sufficient S/N ratio. Provided is a recording medium in which at least one layer is configured by a set of two adjacent sub-layers, and dots on a sub-layer correspond to a recording data ‘1’ and dots on the other sub-layer correspond to ‘0’. These data are played back. |
| US09542968B1 |
Single layer small grain size FePT:C film for heat assisted magnetic recording media
FePt-based heat assisted magnetic recording (HAMR) media comprising a thick granular FePt:C magnetic recording layer capable of maintaining a single layer film having desirable magnetic properties. According to one embodiment, the thick granular FePt:C magnetic recording layer comprises a plurality of carbon doped FePt alloy columnar grains, where the plurality of carbon doped FePt alloy columnar grains comprise a carbon gradient along the thickness of the hard magnetic recording layer. |
| US09542964B2 |
Pivot assembly bearing and hard disk drive device
A pivot assembly bearing includes a shaft, a sleeve provided coaxially with the shaft, and a pair of rolling bearings arranged to be separated from each other in an axial direction between the shaft and the sleeve. The sleeve includes a ventilation path configured to communicate a region surrounded by the shaft, the pair of rolling bearings, and the sleeve with the outside of the sleeve. |
| US09542962B2 |
Multi-sensor reader structure having a current path with increased size to reduce noise
In one embodiment, a magnetic head includes a lower magnetic shield layer positioned at a media-facing surface, a pinned layer positioned above the lower magnetic shield layer at the media-facing surface, at least two MR elements extending in an element height direction by a first length positioned above the pinned layer and separated in a cross-track direction by an inner layer, bias layers extending in the element height direction by a second length positioned on outside edges of the MR elements and the pinned layer, and current paths positioned above and in electrical communication with the bias layers on either side of the inner layer, each current path extending in the element height direction away from the media-facing surface by a third length. |
| US09542957B2 |
Procedure and mechanism for controlling and using voice communication
In a method and system for controlling voice communication of a first person with at least a second person via a communication network a first microphone receives and converts vocal utterances from the first person to a voice signal. A first processor generates a transmission signal by processing the voice signal. A transmitter sends the transmission signal to a receiver. The receiver generates a listening signal by processing the received signal and transmits the listening signal to a speaker. The speaker converts the listening signal to an acoustic signal to be perceived by the first person. In this method a second processor generates the listening signal from the received signal by branching the voice signal and adding the branched voice signal to the received signal. The branched voice signal may be subjected to variable attenuation and/or amplification before being added to the branched voice signal to the received signal. |
| US09542956B1 |
Systems and methods for responding to human spoken audio
Systems and methods for responding to human spoken are provided herein. Exemplary methods may include continuously listening, via an intelligent assistant device, for an initiating command. Additionally, the method may include upon receiving the initiating command, continuously listening, via the intelligent assistant device, for an audio command and transmitting the audio command from the intelligent assistant device to a command processing server. The method may also include transmitting the audio command to at least one information source, the audio command having been converted from speech-to-text, receiving at the command processing server, a response from the at least one information source, and transmitting the response from the command processing server to the intelligent assistant device. |
| US09542953B2 |
Intelligent data delivery
Methods and systems for managing and transmitting content are disclosed. A sample method can comprise determining signal-to-noise ratio information relating to one or more data blocks and determining a threshold signal-to-noise ratio. At least one of the one or more data blocks can be requested based upon respective signal-to-noise ratio information and the threshold signal-to-noise ratio. |
| US09542952B2 |
Decoding device, decoding method, encoding device, encoding method, and program
The present technique relates to a decoding device, a decoding method, an encoding device, an encoding method, and a program which can obtain a high-quality realistic sound.The encoding device stores speaker arrangement information in a comment region in a PCE of an encoded bit stream and stores a synchronous word and identification information in the comment region such that other public comments and the speaker arrangement information stored in the comment region can be distinguished from each other. When an encoded bit stream is decoded, it is determined whether the speaker arrangement information is stored on the basis of the synchronous word and the identification information stored in the comment region. Audio data included in the encoded bit stream is output according to the arrangement of the speakers corresponding to the determination result. The present technique can be applied to an encoding device. |
| US09542951B2 |
Method and an apparatus for processing an audio signal
An apparatus for processing an audio signal and method thereof, the method including receiving a downmix signal including at least one normal object signal, and a bitstream including object information determined when the downmix signal is generated; extracting, from an extension part of the bitstream, an extension type identifier indicating whether the downmix signal further includes a multi-channel object signal; generating spatial information using the object information and mix information when mode information indicates that the multi-channel object signal is to be suppressed and the extension type identifier indicates that the downmix signal further includes the multi-channel object signal; and transmitting spatial information. The mix information is to control an object position or an object level of the at least one normal object signal. |
| US09542947B2 |
Method and apparatus including parallell processes for voice recognition
A method and apparatus for voice recognition performed in a voice recognition block comprising a plurality of voice recognition stages. The method includes receiving a first plurality of voice inputs, corresponding to a first phrase, into a first voice recognition stage of the plurality of voice recognition stages, wherein multiple ones of the voice recognition stages includes a plurality of voice recognition modules and multiples ones of the voice recognition stages perform a different type of voice recognition processing, wherein the first voice recognition stage processes the first plurality of voice inputs to generate a first plurality of outputs for receipt by a subsequent voice recognition stage. The method further includes, receiving by each subsequent voice recognition stage a plurality of outputs from a preceding voice recognition stage, wherein a plurality of final outputs is generated by a final voice recognition stage from which to approximate the first phrase. |
| US09542946B2 |
Converting data between users during a data exchange session
A method and system for converting voice data to text data between users is provided. The method includes receiving voice data from at least one user and determining phoneme data items corresponding to the voice data. Conversion candidate string representations of the phoneme data items are identified by referencing a conversion dictionary defining the conversion candidate string representations for each phoneme data item. The plurality of conversion candidate string representations are scored and a specified conversion candidate string representation is selected as text data based on the scores. The text data is transmitted to a terminal device accessed by the at least one user. |
| US09542944B2 |
Hosted voice recognition system for wireless devices
Methods, systems, and software for converting the audio input of a user of a handheld client device or mobile phone into a textual representation by means of a backend server accessed by the device through a communications network. The text is then inserted into or used by an application of the client device to send a text message, instant message, email, or to insert a request into a web-based application or service. In one embodiment, the method includes the steps of initializing or launching the application on the device; recording and transmitting the recorded audio message from the client device to the backend server through a client-server communication protocol; converting the transmitted audio message into the textual representation in the backend server; and sending the converted text message back to the client device or forwarding it on to an alternate destination directly from the server. |
| US09542941B1 |
Situationally suspending wakeup word to enable voice command input
In one aspect, devices and methods are disclosed for receiving at least one signal from at least one sensor and, based on analyzing the at least one signal, situationally suspending a necessity of receiving a wakeup word to enable voice command input to a computer. |
| US09542940B2 |
Method and system for extending dialog systems to process complex activities for applications
A dialog system that includes a dialog manager to manage a conversation between the dialog system and a user, and to associate the conversation with a complex activity, and a plan engine to execute a plan script in connection with the complex activity, the plan script including a set of atomic dialog activities and logic to control a data and sequence flow of the atomic dialog activities, the set of atomic dialog activities being sub-activities of the complex activity, the complex activity being specified via a declarative activity specification language that connects the atomic dialog activities with a process. |
| US09542939B1 |
Duration ratio modeling for improved speech recognition
In speech recognition, the duration of a phoneme is taken into account when determining recognition scores. Specifically, the duration of a phoneme may be evaluated relative to the duration of neighboring phonemes. A phoneme that is interpreted to be significantly longer or shorter than its neighbors may be given a lower duration score. A duration score for a phoneme may be calculated and used to adjust a recognition score. In this manner a duration model may supplement an acoustic model and language model to improve speech recognition results. |
| US09542937B2 |
Sound processing device and sound processing method
A sound processing device includes a noise suppression unit configured to suppress a noise component included in an input sound signal, an auxiliary noise addition unit configured to add auxiliary noise to the input sound signal, whose noise component has been suppressed by the noise suppression unit, to generate an auxiliary noise-added signal, a distortion calculation unit configured to calculate a degree of distortion of the auxiliary noise-added signal, and a control unit configured to control an addition amount by which the auxiliary noise addition unit adds the auxiliary noise based on the degree of distortion calculated by the distortion calculation unit. |
| US09542935B2 |
Voice recognition function realizing method and device
The embodiment of the present invention provides a method for realizing a voice recognition function, including: setting a corresponding relationship between the attitude parameter of a mobile terminal body and a voice recognition mode (S10); if a gravity sensor in the mobile terminal detects that a change of the attitude parameter of the mobile terminal body satisfies a condition of switching the voice recognition mode, then switching the voice recognition mode, and performing voice recognition under the switched voice recognition mode (S20). Through self-adaptively switching the voice recognition mode of the mobile terminal, the voice recognition function of the mobile terminal can be made to free the hands of a user to the greatest extent and save power consumption. An apparatus for realizing the voice recognition function corresponding to the method is also disclosed. |
| US09542934B2 |
Systems and methods for using latent variable modeling for multi-modal video indexing
A computer-implemented method performed in connection with a computerized system incorporating a processing unit and a memory, the computer-implemented method involving: using the processing unit to generate a multi-modal language model for co-occurrence of spoken words and displayed text in the plurality of videos; selecting at least a portion of a first video; extracting a plurality of spoken words from the selected portion of the first video; extracting a first displayed text from the selected portion of the first video; and using the processing unit and the generated multi-modal language model to rank the extracted plurality of spoken words based on probability of occurrence conditioned on the extracted first displayed text. |
| US09542932B2 |
Word-level correction of speech input
The subject matter of this specification can be implemented in, among other things, a computer-implemented method for correcting words in transcribed text including receiving speech audio data from a microphone. The method further includes sending the speech audio data to a transcription system. The method further includes receiving a word lattice transcribed from the speech audio data by the transcription system. The method further includes presenting one or more transcribed words from the word lattice. The method further includes receiving a user selection of at least one of the presented transcribed words. The method further includes presenting one or more alternate words from the word lattice for the selected transcribed word. The method further includes receiving a user selection of at least one of the alternate words. The method further includes replacing the selected transcribed word in the presented transcribed words with the selected alternate word. |
| US09542926B2 |
Synchronizing the playing and displaying of digital content
The techniques disclosed herein allow a user to synchronize the playing and displaying of digital content on an electronic device. The device may render a first portion of digital content so it may be displayed. The device may also play a segment of the digital content as audio using text to speech software. The device may also render a second portion of digital content for display depending on whether the position of the last word read is greater than the last position in the first portion of digital content. |
| US09542922B2 |
Method for inserting watermark to image and electronic device thereof
A method for operating an electronic device is provided. The method includes determining one or more images; determining at least one first sound sources; dividing the first sound source into a plurality of second sound sources; and inserting at least one of the plurality of the second sound sources into the one or more images. |
| US09542920B2 |
Modular wireless sensor network for musical instruments and user interfaces for use therewith
A wireless sensor network for musical instruments is provided that will allow a musician to communicate natural performance gestures (orientation, pressure, tilt, etc) to a computer. User interfaces and computing modules are also provided that enable a user to utilize the data communicated by the wireless sensor network to supplement and/or augment the artistic expression. |
| US09542917B2 |
Method for extracting representative segments from music
A method for extracting the most representative segments of a musical composition, represented by an audio signal, according to which the audio signal is preprocessed by a set of preprocessors, each if which is adapted to identify a rhythmic pattern. The output of the preprocessors that provided the most periodic or rhythmical patterns in the musical composition selected and the musical composition is divided into bars with rhythmic patterns, while iteratively checking and scoring their quality and detecting a section that is a sequence of bars with score above a predetermined threshold. Checking and scoring is iteratively repeated until all sections are detected. Then similarity matrices between all bars that belong to the musical composition are constructed, based on MFCCs of the processed sound, chromograms and the rhythmic patterns. Then equivalent classes of similar sections are extracted along the musical composition. Substantial transitions between sections represented as blocks in the similarity matrices are collected and a representative segment is selected from each class with the highest number of sections. |
| US09542915B2 |
Keyless locking tremolo systems and methods
Embodiments disclosed herein describe keyless locking tremolo systems and methods for musical instruments that are configured to tune and restrain strings for a musical instrument without an external tool. Embodiments are configured to adjust the vertical positioning of a tightening post and string clamp without an external tool. |
| US09542909B2 |
Image processing apparatus and image processing method
An image processing apparatus including: an acquisition unit that acquires a first image, a second image, and an identifier indicating whether or not a portion corresponding to the first image and included in a third image is to be subjected to a second process; a first processing unit that (i) performs a first process on the first and second images acquired by the acquisition unit to generate the third image and (ii) performs conversion on a α blend value of each pixel forming the generated third image for allocating the identifier to a portion of a possible range of the α blend value; and a second processing unit that controls whether to perform the second process on each pixel forming the third image generated by the first processing unit, on the basis of the converted α blend value. |
| US09542904B2 |
Electronic apparatus
A strain quantity threshold value is set in accordance with a distance from a pressure detection unit for each divided predetermined subdivision which is obtained by dividing an operation surface of a touch panel unit into a plurality of subdivisions. The minimum value of the strain quantity threshold value is set to be a value larger than a strain quantity when water or the like is attached to the operation surface of the touch panel unit. |
| US09542899B2 |
Method of driving display panel, display panel driving apparatus for performing the method and display apparatus having the display panel driving apparatus
A method of driving a display panel includes applying gate signals to gate lines of the display panel that extend in a first direction. A plurality of data lines extends in a second direction perpendicular to the first direction. Pixels are defined by an intersection of the gate lines and the data lines. Common electrode contact pixels are provided, in which a common electrode is contacted with a gate electrode extruded from the gate line. A data signal having a first polarity and a data signal having a second polarity, inverse to the first polarity, are applied to an equal number of the common electrode contact pixels. |
| US09542896B2 |
Display apparatus and control method thereof
A control method of a display apparatus including a panel configured to include red (R), green (G), and white (W) subpixels, and a backlight configured to provide the panel with backlight using at least one of a white light source and a blue light source, including: converting image data into R, G, and blue (B) subframe data; turning on the R, G, and W subpixels according to the R, G, and B subframe data; and turning on the W subpixel, setting a brightness of the white light source to a brightness value of the R, G, and B subframe data, providing the panel with white light at the set brightness, turning on subpixels corresponding to remaining subframe data, setting at least one of the brightness of the white light source and a brightness of the blue light source, and providing the panel with light at the set brightnesses, is provided. |
| US09542893B2 |
Image display device, recording medium, and method to control light sources based upon generated approximate curves
A local failure of display video is suppressed. An LED data calculating portion that generates an approximate curve obtained by approximating the distribution of values of an input image, the approximate curve whose amount of change is less than or equal to a predetermined value, and calculates LED data based on the generated approximate curve and a liquid crystal transmittance calculating portion that calculates the liquid crystal transmittance based on the input image and the approximate curve generated by the LED data calculating portion are provided. |
| US09542887B2 |
Organic light emitting display device and method of driving an organic light emitting display device
An organic light emitting diode display device including: a display panel including a plurality of pixels, a scan driving unit configured to supply a scan signal to the pixels via a plurality of scan lines, a data driving unit configured to supply a data signal to the pixels via a plurality of data lines, an emission driving unit configured to supply an emission control signal to the pixels via a plurality of emission control lines, and a timing control unit configured to control the scan driving unit, the data driving unit, and the emission driving unit, and to control the emission driving unit to gradually change an off-period of the emission control signal each time a number of image frames are displayed. |
| US09542883B2 |
Device and method for controlling brightness of organic light emitting diode display
A device and a method for controlling brightness of an OLED display device are disclosed.The method for controlling brightness of an OLED display device includes the steps of forwarding external brightness control information in a PWM signal or a brightness control data, selecting and normalizing either the PWM signal or the brightness control data into an external brightness adjusting gain, analyzing a received video data to detect a peak brightness value, multiplying the peak brightness value by the external brightness adjusting gain to produce a final peak brightness value, adjusting the R/G/B maximum gamma voltage values according to the final peak brightness value, and generating R/G/B reference gamma voltage sets by using the R/G/B maximum gamma voltage values adjusted thus. |
| US09542881B2 |
Display device
A display device includes: a display panel including: a display portion for displaying an image; and a first pad coupled with the display portion and for receiving an out signal from the display portion; a driver coupled with the display portion for supplying a driving signal to the display portion; a cover covering the display panel; and a connection unit coupling the first pad and the driver to each other to transmit the out signal to the driver, wherein at least a portion of the connection unit is in the cover. |
| US09542875B2 |
Signal processing method, signal processor, and display device including signal processor
A method of signal-processing input image data of a display device including a plurality of pixels, each pixel including a green subpixel and one of a red subpixel and a blue subpixel, the method includes: performing a gamma-conversion on input image data corresponding to the one of the red subpixel and the blue subpixel in each pixel; distributing the gamma-converted input image data corresponding to a center pixel to image data of a pixel in a vertical direction based on the center pixel by a first ratio; and distributing the gamma-converted input image data corresponding to the center pixel to image data of a pixel in a horizontal direction based on the center pixel by a second ratio, where the green subpixel and the one of the red subpixel and the blue subpixel are diagonally disposed in each pixel. |
| US09542873B2 |
Organic light emitting display for sensing electrical characteristics of driving element
An organic light emitting display comprises: a display panel with a plurality of pixels connected to data lines and sensing lines, each pixel comprising an OLED and a driving TFT for controlling the amount of light emission of the OLED; and a data driver IC comprising a plurality of sensing units for sensing current data of the pixels through a plurality of sensing channels connected to the sensing lines, each sensing unit comprising: a first current integrator connected to an odd sensing channel; a second current integrator connected to an even sensing channel neighboring the odd sensing channel; and a sample & hold unit that removes common noise components from a first sampled value input from the first current integrator and a second sampled value input from the second current integrator while storing and holding the first and second sampled values. |
| US09542871B1 |
Collapsible sign post apparatus
A sign post assembly including a ground stake, vertical post, a horizontal arm, and a cap, wherein the vertical post is pin join connected with the horizontal arm by means of a fastener allowing the horizontal arm and the vertical post to be arranged in parallel arrangement during disassembly and storage, or in perpendicular arrangement during assembly and fully extended status. The vertical post having a cut-out along its top portion to allow the arrangement of the horizontal arm within the vertical post's inner cavity and the vertical post having a cut-out along at least one of its vertical sides to allow alignment of the horizontal arm within its internal cavity wherein the horizontal arm collapses downward into the vertical post. Disassembly includes inserting the stake (along with other assembly components (i.e. sign clips, removable fasteners, etc.) within the inner cavity of the lower portion of the vertical post. |
| US09542869B2 |
Electronic device with reflection member
An electronic device includes a housing, a reflection member, a glass base board, a decoration pattern, a reflection membrane, a print circuit board, and a light emitting assembly. The reflection member is fixed with the housing and defines a through hole. The glass base board is positioned on the reflection member away from the housing. The decoration pattern is positioned on the glass base board. The reflection membrane is positioned on the glass base board around edges of the decoration pattern for shielding the glass base board and reflecting light. The print circuit board is received in the housing under the glass base board. The light emitting assembly includes a base board and a light source positioned on the base board. A first light emitting portion of the glass base board is positioned between the reflection membrane and the decoration pattern. |
| US09542864B2 |
Methods and apparatus for digital steganography
A computer-implemented digital steganography method includes providing a plurality of target data elements each comprising a sequence of digital bits, providing a plurality of source data elements each comprising a sequence of digital bits and has a specific start bit, and generating, according to a predefined extraction method, a mapping of each of the target data elements with a corresponding source data element. The mapping includes, for each target data element, a corresponding indice indicating the position of the specific start bit within a bitwise representation of the source data elements irrespective of the bitwise position of each of the source data elements. |
| US09542862B2 |
Pressure feedback network for abdominal simulator system
A dynamically-changeable abdominal simulator system comprises a patient manikin having an abdominal cavity covered by a sheet of synthetic skin, an array of inflatable elements emplaced within the abdominal cavity covering respectively distinct areas of pressurization of the abdominal cavity and supplied with pressurized medium under separate and independent inflation control for each of the inflatable elements in order to simulate a wide range of abdominal ailments and/or conditional expressions thereof. An inflation manifold and an electronic control module operable therewith control the supply of pressurized medium to the inflatable elements. The electronic control module can communicate with an external computer that provides a graphical user interface (GUI) for the user to control the training simulation routines to be performed on the manikin. |
| US09542859B2 |
Spinal injection trainer and methods therefore
For use in training needle techniques such as spinal anesthesia and or lumbar epidural steroid injections, a spinal model includes a complete natural bone vertebral column that is embedded in a matrix of crystal clear ballistic gel. The synthetic gel does not harbor bacteria, can be reused and does not require refrigeration. Natural bone offers significantly better image contrast over radiopaque replicas. A transparent synthetic gel matrix permits observation of needle progression by both the trainee and the trainer and provides unique opportunities for coaching and intercession to prevent poor needle placement prior to its occurrence. |
| US09542858B2 |
System for characterizing manual welding operations
A system for characterizing manual welding exercises and providing valuable training to welders that includes components for generating, capturing, and processing data. The data generating component further includes a fixture, workpiece, at least one calibration devices each having at least two point markers integral therewith, and a welding tool. The data capturing component further includes an imaging system for capturing images of the point markers and the data processing component is operative to receive information from the data capturing component and perform various position and orientation calculations. |
| US09542857B2 |
Math teaching tool
A math teaching tool is provided which can perform teaching more efficiently. The math teaching tool is characterized in the followings. It includes a vessel and a plurality of marbles disposed inside the vessel; the vessel includes a partition defining a boundary of a plurality of regions and a communication part allowing the plurality of regions defined by the partition to communicate with each other; at least one region of the plurality of regions of the vessel is configured so that the plurality of marbles are arrayed into a plurality of lines per unit of five marbles along a first direction of the vessel; and the plurality of marbles include five marbles connected together. |
| US09542856B2 |
Method and system for learning call analysis
A system and method are presented for learning call analysis. Audio fingerprinting may be employed to identify audio recordings that answer communications. In one embodiment, the system may generate a fingerprint of a candidate audio stream and compare it against known fingerprints within a database. The system may also search for a speech-like signal to determine if the end point contains a known audio recording. If a known audio recording is not encountered, a fingerprint may be computed for the contact and the communication routed to a human for handling. An indication may be made as to if the call is indeed an audio recording. The associated information may be saved and used for future identification purposes. |
| US09542854B2 |
Reverse-multiple choice method for knowledge engineering and expert system implementation
A system and method of communication based on the Reverse Multiple-Choice Method of teaching and testing is disclosed where at least one communicant is a machine. The method is applicable for training a machine for knowledge engineering and artificial intelligence oriented applications, as well as for a trained machine to assist a human being engaged in the activity of teaching or testing. |
| US09542849B1 |
Risk-based flight path data generating system, device, and method
A system, device, and method for generating and employing risk-based flight path data are disclosed. The system for employing risk-based flight path data may include one or more one avionics systems and/or remote aircraft operator systems configured to receive risk-based flight path data from a route generator (RG). The RG may acquire navigation data representative of one or more waypoints, acquire risk object data based upon the navigation data, determine the risk-based flight path data representative of a risk-based flight path as a function of the acquired navigation data, the acquired risk data, and a route generating algorithm, and provide the flight path data to the one or more avionics systems and/or remote aircraft operator systems. In some embodiments, the risk object data may include a plurality of risk clearance altitudes. In other embodiments, the risk object data may include a plurality of risk clearance elevations. |
| US09542847B2 |
Lane departure warning/assistance method and system having a threshold adjusted based on driver impairment determination using pupil size and driving patterns
A method/system for lane departure warning/assistance that warns the driver that the vehicle is about to leave a current lane and enter an adjacent lane. The driver is identified, and a corresponding profile is accessed. The driver's pupils may be measured and compared to pupil size baseline data stored in the accessed profile. If the difference in pupil size exceeds a pupil size baseline by more than a deviation level, the method/system may adjust a lane departure warning/assistance threshold of a lane departure detector that warns the driver each time the vehicle is getting too close to an adjacent lane, thus alerting the driver that the vehicle may drift into the next lane. Driving patterns, such as steering angles and braking force, may also be used to adjust the lane departure warning/assistance threshold and determine whether the driver may benefit from lane departure warning/assistance. |
| US09542844B2 |
Providing navigation directions in view of device orientation relative to user
To provide effective navigation directions to a user in an automotive environment, a system determines information related to navigating the user to a destination, determines whether a screen of the portable device currently is in a line-of-sight with the user and generates a navigation instruction based on the determined information. Generating the navigation instruction includes selecting a level of detail of visual information for the navigation instruction in view of whether the screen is in the line-of-sight with the user. |
| US09542843B2 |
Personalized updating of digital navigation maps
A digital navigation map is updated by floating car data, wherein vehicles transmit their own position to a traffic control center, the traffic control center and/or at least one vehicle identifies a hazard situation, and an update for the digital navigation maps of the vehicles in the surroundings is initiated and performed. |
| US09542840B2 |
Remote control system and method having reduced vulnerability to noise
A remote control system and method having reduced vulnerability to noise. In an environment having noise at a frequency of infrared signals transmitted by a remote controller, errors and malfunctions in a remote control receiving device such as a set top box are controlled by selectively transmitting an entire code including header pulses and data pulses, or a repeat code including header pulses, data pulses and repeater pulses from the remote controller, and receiving and using the entire code or repeat code at the remote receiving device. |
| US09542836B2 |
Household electric appliance, household electric system, and server apparatus
Provide are a household electric appliance, household electric system and server apparatus that perform operation start or stop at reserved set times and that are convenient with regard to reserving operation. A household electric appliance capable of a reserved operation of performing an operation start or stop at a set time comprises: a receiving unit that receives a setting signal indicative of an operation start time in the reserved operation of the household electric appliance from each of a remote controller and a mobile terminal; a storage unit that stores the setting signal; and a control unit that controls operation of the household electric appliance. The control unit, in the case of overlapping of an operation time zone defined by the setting signal from the remote controller and the operation time zone defined by the setting signal from the mobile terminal, selects the earlier time and performs the operation start. |
| US09542835B2 |
Networked pest control system
A pest control device system includes a plurality of pest control devices and a data collector. The system may further include the data collector in the form of a gateway that is connected to a data management server via a computer network along with other gateways in corresponding pest control device groups. Each pest control device includes a pest sensor and a wireless communication circuit to transmit information from the corresponding sensor. The devices also configure to define a local wireless communication network that can relay the information from one to the next and ultimately to the data collector. |
| US09542833B2 |
Automatic determination of radio control unit configuration parameter settings
A method for determining an output signal is provided. A radio device identifier associated with a second radio device is stored in a first radio device. One or more configuration parameter settings associated with the second radio device are stored in the first radio device. The first radio device identifies the second radio device based on the radio device identifier. In response to identifying the second radio device, the first radio device automatically determines the configuration parameter settings should be used to determine an output signal based on a user input. The first radio device establishes a radio communications link with the second radio device. The first radio device receives the user input. Based on the configuration parameter settings and the user input, the first radio device determines the output signal. The first radio device transmits the output signal to the second radio device through the radio communications link. |
| US09542829B2 |
Alarm system with two-way voice
Techniques are described for establishing a two-way voice communication session with an alarm system. The alarm system may establish a two-way voice communication session with an operator associated with a monitoring service that provides monitoring services for alarm events detected by the alarm system. The alarm system also may establish a two-way voice communication session with a notification recipient that is interested in receiving notifications associated with events detected by the alarm system. |
| US09542818B2 |
Electronic deterrence devices
An example electronic deterrence device includes a housing, and one or more first and second indicator lights. The one or more second indicator lights, when illuminated, illuminate a textual message visible from a front of the housing. The electronic deterrence device also includes a power supply, a switch, and a microcontroller. The microcontroller is configured to determine a position of the switch; responsive to determining that the switch is in a first position, disable the one or more first and second indicator lights; responsive to determining that the switch is in a second position, illuminate the one or more first and second indicator lights using electrical power delivered from the power supply; and responsive to determining that the switch is in a third position, illuminate the one or more first and second indicator lights using electrical power delivered from the power supply based on an ambient condition. |
| US09542814B2 |
Gaming system and method for providing a nudge poker game
A gaming system for providing a poker game with a playing card nudge feature. |
| US09542811B2 |
Gaming device having a selectively accessible bonus scheme
A gaming device having a bonus scheme, wherein the player may choose when to play a bonus scheme, so long as the player is qualified to do so. The method of qualifying the player to enter the bonus round connects or links the base game operation of the gaming device with the bonus scheme. The reels of the base game contain symbols which alone or in combination with other symbols yield one or more bonus awards to a player. The bonus awards are escrowed and displayed a bonus award escrow display. Once the player obtains a single bonus award, the player becomes eligible or qualified to play the bonus round and the player may choose to do so at any time. The player can accumulate bonus awards and use multiple bonus awards at one time. |
| US09542807B2 |
Controlling event-driven behavior of wagering game objects
A behavior controller system and its operations are described herein. In embodiments, the operations can include determining an outcome to present for a wagering game. The wagering game includes a wagering game object configured to present the outcome using a set of possible behavioral responses. The operations can further include, based on the outcome, determining priorities for the set of possible behavioral responses and performing at least a portion of the set of possible behavioral responses according to the priorities. The operations can further include; and causing the wagering game object to present the outcome for the wagering game based on the performing the at least the portion of the set of possible behavioral responses. |
| US09542805B2 |
Wagering game with images having dynamically changing shapes
A gaming system for conducting a wagering game displays images having dynamically changing shapes. In one embodiment, a display device displays a screen for a wagering game. The screen presents a first image that follows a first spline. The first spline is defined by one or more curves passing through a first set of control points. A processor determines a second set of control points to define a second spline for the first image. The screen displays the first image transitioning from following the first spline to following the second spline. The screen may present a graphical interaction involving the first image, and the processor is configured to determine the second set of control points in response to the graphical interaction. The graphical interaction may occur between the first image and a second image. Alternatively, an input from a player causes the graphical interaction with the first image. |
| US09542801B1 |
Wearable wagering game system and methods
In at least some aspects, the present concepts include a wearable haptic device including one or more input devices, one or more haptic output devices, one or more processors, and a communication device, wherein the one or more processors are configured to cause the one or more haptic output devices to output a haptic output, of a plurality of haptic outputs, responsive to an event in a game, of a plurality of possible game events, in accord with a mapping of haptic outputs to game events. |
| US09542796B2 |
System and method of allowing a player to play gaming machines having expanding symbol and column replication
The invention is directed to a gaming machine and method of providing a game. The game machine comprises a display and a controller. The display is configured to display a plurality of symbol positions displayed in a grid, the grid defining a plurality of columns. The controller is configured to: initiate a game; determine at least one symbol associated with each of the plurality of symbol positions along at least one of the columns and display the symbols in the at least one column; evaluate the symbols displayed within the at least one column to determine a highest ranked symbol; replace all remaining symbols displayed within the at least one column with the highest ranked symbol; and insert the highest ranked symbol into the symbol positions of at least one other column within the grid. |
| US09542787B2 |
Systems and methods for detecting a document attribute using acoustics
Systems and methods for detecting a document attribute using acoustics are provided. In one embodiment, a method for detecting a feature of a document using acoustics includes emitting a first acoustic signal from a first acoustic transmitter to a first acoustic receiver while a document is between the first acoustic transmitter and the first acoustic receiver, and emitting a second acoustic signal from a second acoustic transmitter to a second acoustic receiver while the document is between the second acoustic transmitter and the second acoustic receiver. The second acoustic signal differs from the first acoustic signal. The method also includes determining the presence of a feature of the document using at least one of the first acoustic signal or the second acoustic signal. |
| US09542779B2 |
Object modeling in multi-dimensional space
Embodiments of the invention include a method inserting a new face in a polygonal mesh comprising receiving an input corresponding to: a polygonal mesh having a plurality of faces, a selection of a face (fm) of the plurality of faces, a direction vector (d), a modified target plane (pm), and a threshold angle θ. For each edge (e) of the selected face fm, the method further includes determining each adjacent face (fadj) to selected face fm, and inserting a new face at edge e if no adjacent face exists or if fadj is substantially parallel to pm and within threshold θ. In some embodiments, the new face has a normal orthogonal to e and d. |
| US09542777B2 |
Image processing apparatus, image processing method, and storage medium
An image processing apparatus, which determines, for a combined image obtained by combining pixels of a given first image and pixels of an unknown second image either translucently or non-translucently using an unknown coefficient indicating a transparency, whether each of pixels included in the combined image is a translucently combined pixel, is provided. The image processing apparatus calculates, from pixel values of the combined image and the first image of respective pixels in a predetermined area including one pixel, pixel values of an image corresponding to the second image, calculates a total of differences between the calculated pixel values, identifies a coefficient used to obtain the combined image from the total of the difference, and determines that the one pixel is a translucently combined pixel when a value of the identified coefficient is larger than a predetermined value. |
| US09542774B2 |
Determining a node paththrough a node graph
Determining a node path through a node graph includes modifying the node graph in accordance with a predetermined platform performance, performing a path finding process through the node graph to obtain the node path, determining if the platform performance has changed, adjusting the node graph to compensate for a change in the platform performance, and re-performing the path finding process through the adjusted node graph to obtain the node path. |
| US09542773B2 |
Systems and methods for generating three-dimensional models using sensed position data
Embodiments include a computer-implemented method for generating a three-dimensional (3D) model. The method includes receiving a first and second sets of sensed position data indicative of a position of a camera device(s) at or near a time when it is used to acquire first and second images of an image pair, respectively, determining a sensed rotation matrix and/or a sensed translation vector for the image pair using the first and second sets of sensed position data, identifying a calculated transformation including a calculated translation vector and rotation matrix, generating a sensed camera transformation including the sensed rotation matrix and/or the sensed translation vector, and, if the sensed camera transformation is associated with a lower error than the calculated camera transformation, using it to generate a 3D model. |
| US09542772B2 |
Virtual endoscope image-generating device, method, and program
A virtual endoscope image is generated based on an opacity template in which a pixel value of a three-dimensional image is associated with an opacity, the opacity template being capable of showing both of an inner wall of a large intestine region and an inner wall of a residue region present in the large intestine region on the virtual endoscope image, a viewpoint set in the vicinity of a boundary between a space region and the residue region in the large intestine region, a set surface set at a position separated by a previously set distance in a previously set line-of-sight direction from the viewpoint, and a pixel value on a light beam vector beyond the set surface among pixel values of the three-dimensional image on the light beam vector extending from the viewpoint. |
| US09542769B2 |
Apparatus and method of reconstructing 3D clothing model
Disclosed are a method and an apparatus for reconstructing three-dimensional (3D) clothing using captured image information on clothing, which capture image information on clothing put on a mannequin, generate a temporary model using the captured image information, and generate a final clothing model using the temporary model. |
| US09542767B2 |
Animation engine for blending computer animation data
Computer-generated images are generated by evaluating point positions of points on animated objects in animation data. The point positions of the points are used by an animation system to determine how to blend animated sequences or frames of animated sequences in order to create realistic moving animated characters and animated objects. The methods of blending are based on determining distances or deviations between corresponding points and using blending functions with varying blending windows and blending functions that can vary from point to point on the animated objects. |
| US09542765B2 |
Method and system for placing an object on a user
A method, system and computer program product for virtually placing an object on an image of a human appendage is provided. First, image boundaries are detected in the image of the appendage and converted into a set of line segments. A pair of line segments is evaluated according to a function that combines subscores of the pair of line segments to produce a score. The subscores of the line segments are computed based on various properties such as orientation difference, extent, proximity to the center of the image, bilateral symmetry, and the number of skin-colored pixels. A pair of line segments with the highest score is chosen as the appendage boundaries and is used to determine the position, orientation, and extent of the object. The image of the object is then transformed according to the determined parameters and combined with the image of the appendage to produce the desired result. |
| US09542764B2 |
Displaying contents of a file in different regions
The disclosure provides an information processing method and an electronic device. The information processing method includes: acquiring a first file; displaying a first content in a first region in a first display mode, the first content characterizes a first part of a display content of the first file and the first region is a region capable of triggering the display content of the first file to be displayed upon a triggering operation is detected; and displaying a second content in a second region in a second display mode if a first preset condition is satisfied, the second content characterizes a second part of the display content of the first file and the second region is a region capable of triggering the display content of the first file to be displayed upon a triggering operation is detected, the first region is different from the second region. |
| US09542760B1 |
Parallel decoding JPEG images
Devices, systems and methods are disclosed for preprocessing JPEG images to enable parallel decoding and for parallel decoding of JPEG images. A JPEG image may be preprocessed to enable parallel decoding by embedding restart (RST) markers within the JPEG data and embedding information in an application (APPn) marker, which may be included in a header associated with the JPEG data. Using the RST markers and information included in the APPn marker, a device may separate the JPEG data into sections and decode the sections in parallel using multiple cores to reduce a time between acquiring and rendering the JPEG image. The parallel outputs may be stored to identified locations in a buffer so that the finished outputs are sequentially stored as a complete decoded JPEG image. |
| US09542756B2 |
Note recognition and management using multi-color channel non-marker detection
Techniques are described for creating and manipulating software notes representative of physical notes. A computing device comprises a processor and a note identification module executable on the processor and configured to separate an input image into a plurality of channelized input images. Each of the channelized input images are associated with a different color. The note identification module is configured to apply edge detection and feature extraction to identify polygons within each of the channelized input images and select, from the polygons from the channelized input images, a representative polygon for each of the physical notes in the input image. |
| US09542754B2 |
Device and method for detecting moving objects
A moving object detection apparatus comprising: an image acquisition device; a first moving object detection device; a difference image generation device; a second moving object detection device for detecting existence/nonexistence of the moving object based on the difference image generated by the difference image generation device; and an integration device for integrating a detection result by the first moving object detection device and a detection result by the second moving object detection device and determining that the moving object is detected in a case where the moving object is not detected by at least the first moving object detection device and the moving object is detected by the second moving object detection device. |
| US09542753B2 |
3D reconstruction of trajectory
Disclosed is a method of determining a 3D trajectory of an object from at least two observed trajectories of the object in a scene. The observed trajectories are captured in a series of images by at least one camera, each of the images in the series being associated with a pose of the camera. First and second points of the object from separate parallel planes of the scene are selected. A first set of 2D capture locations corresponding to the first point and a second set of 2D capture locations corresponding to the second point are reconstructed to determine an approximated 3D trajectory of the object. |
| US09542751B2 |
Systems and methods for reducing a plurality of bounding regions
A method performed by an electronic device is described. The method includes generating a plurality of bounding regions based on an image. The method also includes determining a subset of the plurality of bounding regions based on at least one criterion and a selected area in the image. The method further includes processing the image based on the subset of the plurality of bounding regions. |
| US09542743B2 |
Calibration and transformation of a camera system's coordinate system
Systems and methods are disclosed that determine a mapping between a first camera system's coordinate system and a second camera system's coordinate system; or determine a transformation between a robot's coordinate system and a camera system's coordinate system, and/or locate, in a robot's coordinate system, a tool extending from an arm of the robot based on the tool location in the camera's coordinate system. The disclosed systems and methods may use transformations derived from coordinates of features found in one or more images. The transformations may be used to interrelate various coordinate systems, facilitating calibration of camera systems, including in robotic systems, such as an image-guided robotic systems for hair harvesting and/or implantation. |
| US09542742B2 |
Estimation of the system transfer function for certain linear systems
The pupil image function (PIF) matrix of a plenoptic imaging system is calibrated, taking advantage of the low rank of the PIF matrix. In one approach, the low rank is utilized by identifying a subspace for the PIF matrix and then estimating the PIF matrix within that subspace. This can lead to a significant reduction in the number of calibration patterns used to estimate the PIF matrix. |
| US09542740B2 |
Method for detecting defect in pattern
Provided is a method of detecting a defect of a pattern using vectorization to increase accuracy and efficiency in OPC modeling and OPC verification. The method includes acquiring a target layout image associated with a target pattern, acquiring a pattern image associated with a pattern formed on a substrate, extracting an edge image from the pattern image, producing a first vector form based on the target layout image, producing a second vector form based on the edge image, and comparing the first vector form with the second vector form. |
| US09542735B2 |
Method and device to compose an image by eliminating one or more moving objects
A method and a device to compose an image by eliminating one or more moving objects in a scene being captured are provided. The method includes capturing plurality of images, generating a background image with a plurality of stationary objects after aligning the plurality of captured images, selecting a base image from a plurality of the aligned images, wherein the base image is selected based on a highest similarity measure with the background image, identifying the at least one moving object in the base image, and eliminating said identified at least one moving object in the base image to compose said image. |
| US09542733B2 |
Image processing method, imaging processing apparatus and image processing program for correcting density values between at least two images
An image processing method includes: a generating step of generating a cumulative histogram of density values of pixels included in at least each of a first image and a second image; a calculating step of calculating a distance between a density value on a first histogram generated from the first image and a density value on a second histogram generated from the second image, in a space defined to include histogram frequencies of the cumulative histograms and the density values; and a determining step of determining a correspondence relation between the density values included in the first image and the density values included in the second image based on the calculated distances between the density values, and determining a conversion function for correcting a density value between the first image and the second image based on the determined correspondence relation. |
| US09542728B2 |
Apparatus and method for processing color image using depth image
An image processing apparatus and method using a depth image are provided. The image processing apparatus may include a region determination unit to determine a foreground region and a background region in a color image using a depth image, and a color compensation unit to compensate a color with respect to the foreground region and the background region. |
| US09542723B2 |
Architectures and methods for creating and representing time-dependent imagery
Aspects of the technology pertain to geographical image processing of time-dependent imagery. Various assets acquired at different times are stored and processing according to acquisition date in order to generate one or more image tiles for a geographical region of interest. The different image tiles are sorted based on asset acquisition date. Multiple image tiles for the same region of interest may be available. In response to a user request for imagery as of a certain date, one or more image tiles associated with assets from prior to that date are used to generate a time-based geographical image for the user. |
| US09542722B2 |
Automatic scaling of objects based on depth map for image editing
Automatic scaling of image objects being moved or copied to a target object location is presented. An original image and its depth map are received within which the user selects an original object and a target location for the object to be moved or copied. A center of scaling is found and a base location selected at which depth value is to be obtained at the target location for use in scaling. Target object is then scaled in response to a ratio between original object depth and target object depth. An occlusion check is made, after which non-occluded pixels are pasted to the target location to complete the move/copy which is in proper proportion and accounts for surrounding structures. |
| US09542721B2 |
Display control device and data processing system
The display control device has a register for holding mode data for giving: a direction about which of a first display mode for performing display control of display data supplied together with a display timing signal from outside, and a second display mode for performing display control of display data written in RAM without accepting supply of a display timing signal from outside to select; and a direction about whether or not to select a scale-up mode for scaling up the display data, so that the mode data can be rewritten from the outside. The display mode is controlled based on the setting values on the register. The control register can be rewritten according to the type of data to be displayed, the system working situation, user settings, etc. Therefore, the low power consumption allowable in terms of system, and a required display performance can be obtained timely and readily. |
| US09542719B2 |
Device for image decomposition using a wavelet transform
A device for decomposing images into at least three levels by wavelet transform comprises a first unit executing a first level of decomposition and a second unit executing the higher levels of decomposition by performing a sequence of processing tasks. The tasks are ordered in time by using a sequence of rows, a routing unit serving to configure the second unit when the level of decomposition associated with the processing task currently being executed changes relative to the level of decomposition associated with the processing task executed previously. The processing tasks are ordered so that any given row is associated with only one level of decomposition. |
| US09542718B2 |
Head mounted display update buffer
Techniques related to providing updates in a head mounted display (HMD) device are described herein. A HMD may be configured to display a view of an environment. An update buffer of the HMD device may be included to store image data. The image data may include image data for a current view of the environment and image data of the environment that is outside of the current view. |
| US09542709B2 |
Graphical display with integrated recent period zoom and historical period context data
A system and method are provided for displaying a data series. In one embodiment, a graphical interface is provided including at least one axis that is divided into a plurality of axis regions. Preferably, each axis region uses a different linear scale, and the plurality of axis regions forms a continuous non-linear scale. The graphical interface also displays the data series in relation to the plurality of axis regions, and the data series is plotted in relation to each axis region based on a scale resolution corresponding to each respective axis region. |
| US09542708B2 |
Event server using caching
An event server adapted to receive events from an input stream and produce an output event stream. The event server uses a processor using code in an event processing language to process the events. The event server obtaining input events from and/or producing output events to a cache. |
| US09542707B2 |
Method, medium, and system for keyword bidding in a market cooperative
A computer-implemented method and system for keyword bidding in a market cooperative are disclosed. A particular embodiment includes receiving a keyword bid from a first party; determining a value to a host associated with the keyword bid; augmenting the keyword bid by an amount corresponding to the value to the host; and sending the augmented keyword bid to a second party. |
| US09542704B2 |
Automatic image-based recommendations using a color palette
Systems and methods are described that recommend images, items, and/or metadata based at least in part on a reference color palette or reference color name. A color name can be converted into a representation of the color name in a color space. The reference color can be used to identify images that contain the reference color. The identified images and associated metadata can be analyzed, sorted and provided as an ordered list of items. Systems and methods are also described that identify items that contain colors affiliated with the reference color. Systems and methods are also described that validate color identifier information in metadata associated with an image. Systems and methods are also described that identify non-color specific keywords associated with the reference color. |
| US09542703B2 |
Virtual custom framing expert system
Disclosed are various embodiments for facilitating an electronic framing process. A virtual framing system may access a digital image provided by or otherwise selected by a user of the virtual framing system to be examined on a pixel-by-pixel basis to identify relevant and/or dominant colors located within the digital image. By utilizing the most relevant and/or the most dominant colors of the digital image, the virtual framing system may subsequently generate recommendations to be presented to the user by comparing the most relevant and/or most dominant colors to one or more predefined design templates, such as those created by an expert designer, that are stored in a data store. |
| US09542700B2 |
Business model based on multi-level application widgets and system thereof
Provided is a business model based on multi-level application widgets and a system thereof, including: embedding, by a server, intended application widgets in an Internet platform equipped with a software application programming interface; providing a business protocol between an end user and the server, thus giving the end user authority to embed data sets in the application widgets and to conduct display, operation, sales, and real-time interaction within the same window; determining, by the end users, whether at least an application widget or a data set is to be embedded in each of the data sets again, so as to finalize the multi-level application widgets. Accordingly, the end user enhances promotion and thereby expands business on the Internet platform at the server. |
| US09542697B1 |
Customized landing pages
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for personalizing landing pages. In one aspect, a method includes generating, by one or more servers belonging to a first domain and for a request, a personalized landing page that includes the personalized landing page data, wherein the landing page belongs to the first domain, and the landing page includes at least one link to a resource of the first party that belongs to the second domain; and providing, by the one or more servers, the personalized landing page to the user device, wherein the personalized landing page, when processed by the user device, generates a personalized landing page environment that belongs to the first domain. |
| US09542696B2 |
Systems and methods for online direct marketing and advertising on registration based websites and web-based email systems
An online direct marketing and advertising system is presented in which advertisers have an opportunity to send targeted promotions, coupons and offers that are placed in a user's web-based email account without the drawbacks of sending conventional email. The promotions do not take up disk quota space and, at the same time, the system does not need to divulge private user information to the advertiser. This system provides a means to free web-based email providers from the need to obtain opt-in permission to send offers to their users as providers are frequently prohibited from sharing the user's email address and personal information with merchants. |
| US09542693B2 |
System and method for assigning pieces of content to time-slots samples for measuring effects of the assigned content
Systems and methods provide for assigning pieces of content to time-slots samples for measuring effects of the assigned content. Systems and methods provide for receiving pair-wise content relatedness data that identifies each piece of content as experimental content or control content relative to other pieces of content, and algorithmically assigning experimental or control content pieces to time-slot samples using the content relatedness data, wherein additional content pieces assigned to a particular time-slot sample exclude non-identical related experimental content pieces defined relative to an experimental content piece previously assigned to the particular time-slot sample. |
| US09542692B2 |
Systems and methods for matching a user to social data
A system comprising a computer-readable storage medium storing at least one program and a computer-implemented method for matching social data to a user of a networked-based content publisher are provided. Consistent with some embodiments, the method may access social network entries published on one or more social networks. Social network entries that include a reference to content published by a particular content publisher may be identified. A social network profile corresponding to a first social network entry of the identified social network entries may be identified. The method may further include determining that the social network profile corresponds to a particular user of the content publisher based on information embedded in the reference to the content. |
| US09542687B2 |
Systems and methods for visual representation of offers
A method and system for providing geographic location notifications for targeted offers is disclosed. One embodiment of the invention is directed to a method including monitoring for an event to trigger a targeted offer. Upon detection of the event, the offer is generated. The offer is targeted to a consumer and is generated using payment data generated in response to transactions conducted by the consumer with a plurality of different merchants. A geographic location for redeeming the offer is determined. A notification message is generated about the offer. The notification message includes the offer and the geographic location for redeeming the offer. The notification message is sent to a notification device which is operated by the consumer. A graphical depiction of the offer is displayed on a map on the notification device. |
| US09542683B2 |
System and method for protecting electronic money transactions
Disclosed are systems and methods for protecting electronic money transactions from fraud and malware. An exemplary method include scanning a computer to detect software objects associated with electronic money that includes at least one of a wallet configured to store electronic money, an electronic money generating application, and data including an interaction history with an electronic exchange for electronic money; identifying and adjusting electronic money security modules configured to provide data security to the detected software objects associated with the electronic money; and executing, by the adjusted electronic money security modules, at least one electronic money transaction involving the electronic money. In one aspect, the electronic money security modules include a wallet protection module, a malware detection module, and a traffic control module. |
| US09542682B1 |
Card registry systems and methods
A card registry system is configured to automatically identify financial card information in one or more credit files associated with a consumer and populate a card registry account of the consumer with the identified financial card information. Once the financial card information has been obtained from the credit file(s), the card registry system may transmit cancellation and/or reissuance requests to the respective card issuers in the instance that one or more cards are compromised, so that the financial cards may be easily and efficiently cancelled and/or reissued at the request of the consumer. |
| US09542681B1 |
Proxy card payment with digital receipt delivery
Disclosed herein are techniques for providing a digital receipt to a consumer upon tender of payment to a merchant through the use of a proxy payment card in a financial transaction. The proxy payment card can be associated with multiple financial accounts (e.g., accounts associated with credit cards, debit cards, or gift cards). The digital receipt is automatically received at a personal computing device of the consumer in response to the financial transaction being charged to a financial account associated with the proxy payment card. The digital receipt includes information indicative of the financial transaction. The digital receipt can also include one or more interactive components that allow the consumer to interact with the transaction (and/or merchant) subsequent to transmission of the receipt, such as adding a tip, providing feedback, redeeming a promotion reward, tracking loyalty reward points, or reviewing transaction records of past and present transactions. |
| US09542680B2 |
Information processing apparatus, information processing method, program, and information processing system
An information processing apparatus includes: processing sections that have respective identification information and that perform processing corresponding to a request from another information processing apparatus; and a reporting section that stores the respective identification information of the processing sections and, instead of the processing sections, that reports the identification information to the another information processing apparatus in response to a request for reporting the identification information, the request being issued from the another information processing apparatus. |
| US09542679B2 |
Implementation method for an identification system using dynamic barcode
The implementation method for an identification system using dynamic barcode entails description for a system that comprises a smartphone, a barcode information access device on the merchant side, and a server of an identification agency. The implementation method described includes downloading a mobile application (app) for smartphone, and utilizing the app to upload identification information to server of the identification agency. When a user needs to be identified during a transaction, the aforementioned app is used to display two barcodes on the smartphone: one barcode represents the user's identification, and the other is a dynamic one that corresponds to the user's identification information and changes after a given time period. When both barcode information are read by barcode reader and send to the server of the identification agency, the said agency could easily compare its own information with the dynamically generated barcode information, which helps to distinguish whether the user is the original registrant. |
| US09542670B2 |
Information management systems with time zone information, including event scheduling processes
Information management systems with time zone information, including event scheduling processes are disclosed. One aspect of the invention is directed toward a computer-implemented scheduling method that can include identifying a difference between a participant time zone and a user time zone, reviewing availability information for the participant and/or one or more selected time preference periods for the participant, and selecting a time range for an event. The method can further include reviewing one or more selected time preference periods for the user. Another aspect of the invention is directed toward a computer-implemented method for associating time zone information with a contact in an information management program application that includes selecting a contact, analyzing contact information associated with the contact, and determining a time zone for the contact based on the analysis of the contact information. |
| US09542668B2 |
Systems and methods for clustering electronic messages
System and methods are provided for receiving selection, by a user, of a subset of message clusters in a plurality of message clusters. Each message cluster is associated with a corresponding set of clustering rules. Each respective electronic message, addressed to and/or from the user, in a plurality of electronic messages is assigned to one or more of the clusters in the subset of clusters in accordance with the sets of clustering rules associated with the subset of clusters. The set of clustering rules for a first cluster in the subset of clusters (i) prevents some messages in the plurality of messages from being assigned to the first cluster and (ii) assigns messages to the first cluster without regard to content relatedness between messages in the plurality of messages and messages already in the first cluster. Messages in the first cluster are formatted for display as a single cluster graphic. |
| US09542666B2 |
Computer-implemented system and methods for distributing content pursuant to audit-based processes
Systems and methods are disclosed for distributing content pursuant to audit-based processes. Audit content in runtime workpapers may be dynamically constructed in response to industry-driven and response-driven rules using information from one or more of the distributed content libraries. Dynamic updates may also be provided for generated runtime workpapers constructed from the distributed content. The system and method may also provide drilldown functionality for enabling a user to view a source workpaper for a specified data value which has flowed into the generated dynamic workpaper and/or tip functionality to provide a user with additional guidance based on the status and data associated with the generated workpaper. |
| US09542664B2 |
Stock monitoring
A stock monitoring system, for monitoring items of stock in one or more storerooms, includes a portable device including a first processor and a first wireless transceiver for short-range communication. The first processor is operable for receiving a user ID of a second user via the first wireless transceiver and transmitting to the remote system via a second wireless transceiver, at least item data, associated with the user ID. An intermediate unit includes a second processor and a reader and a wireless transmitter adapted for short-range communication. Upon reading the user ID from an ID card of the second user by the reader, the user ID is transmitted via the wireless transmitter, e.g. for a predetermined period. The first processor receives a user ID of a second user via the first wireless transceiver. A method, portable device and intermediate unit are also disclosed. |
| US09542663B2 |
Multi-tag identification devices, variable-power standoff readers for same, and related systems
Systems, apparatuses, methods, and software for monitoring compliance of sanitizees (e.g., health care workers, food service workers, sanitization/janitorial workers etc.) with sanitization protocols to be followed for encounters with sanitization-protocol targets (e.g., patients, food-preparation areas, health care facilities/appurtenances, restrooms, etc.). In one example, a system includes sanitization verification systems located close to the targets and mobile node devices issued to the sanitizees. Each verification system can be configured to test the efficacy of sanitization procedures performed by the sanitizees prior to encountering a target, to provide authorizations, via the node devices, to the sanitizees to proceed with target encounters, and to open monitoring sessions during which the node devices record information concerning interactions with the targets. The node devices are configured to annunciate sanitization statuses of the sanitizees throughout a work period as the sanitizees continually interact with verification stations and encounter targets. |
| US09542660B2 |
Work process collaboration management
A collaboration message is received at a computer system network node of a computer network that operates in a decentralized arrangement such that network nodes comprise work process sources and destinations, and the collaboration messages convey process state updates among the collaborators. There is no central authority though which all process messages and state updates must pass and which thereby may create a system bottleneck and limit system growth. The computer system is scalable and system operation remains efficient with increasing numbers of network nodes. |
| US09542658B2 |
System and method for identifying power usage issues
A system and method analyzes resource consumption without requiring sensors at every device for which consumption is analyzed. Data rates used to provide resource use information may be increased or decreased based on user actions. |
| US09542653B1 |
Vehicle prediction and association tool based on license plate recognition
LPR instances around physical locations and license plate numbers associated with a person of interest are analyzed to predict the relative likelihood of locating the person of interest at a particular location. An LPR information query includes an indication of a physical location and a license plate number associated with a person of interest. The relative likelihood of locating a person of interest at a particular location at a future point in time is determined based on the LPR instances received. In one example, the relative likelihood of locating the person of interest is based on the relative value of clusters of LPR instances around physical locations associated with the person of interest. Additional license plate numbers are associated with a person of interest based on their appearance within a search zone and time window of LPR instances of a license plate number already associated with a person of interest. |
| US09542652B2 |
Posterior probability pursuit for entity disambiguation
Various technologies described herein pertain to disambiguation of a mention of an ambiguous entity in a document. A set of candidate entities can be retrieved from an entity knowledge base based upon the mention of the ambiguous entity, where each of the candidate entities has a respective entity feature representation. Moreover, a document feature representation can be generated based upon features of the document and the respective entity feature representations of the candidate entities. A processor can be caused to select a subset of features from the document feature representation based upon a measure of how discriminative the features from the document feature representation are for disambiguating the mention of the ambiguous entity. A disambiguated result for the mention of the ambiguous entity can be determined based upon the subset of the features. The disambiguated result can be an unknown entity or one of the candidate entities. |
| US09542651B2 |
Fuzzy inference deduction using rules and hierarchy-based item assignments
Some embodiments disclosed herein relate to generating fuzzy inferences of procedure types based on fuzzy logic. Membership functions can be used to relate item variables to a degree of correspondence to various item types. Fuzzy rules can specify processing to be conducted using membership values produced by evaluations of membership functions. An output of the processing can include an inference that a content object corresponding to the item variables relates to one or more procedure types. Further, some embodiments disclosed herein relate to querying hierarchical data structures to identify related items. A hierarchical data structure can associate each of a set of procedure types with one or more item types and/or item identifiers or characteristics. |
| US09542650B2 |
Analyzing behavior in light of social time
A relational event history is determined based on a data set, the relational event history including a set of relational events that occurred in time among a set of actors. Data is populated in a probability model based on the relational event history, where the probability model is formulated as a series of conditional probabilities that correspond to a set of sequential decisions by an actor for each relational event, where the probability model includes one or more statistical parameters and corresponding statistics, and where at least one of the one or more statistics is determined using a decay function. A baseline communications behavior for the relational event history is determined based on the populated probability model, and, based on a second set of values for the statistical parameters, departures within the relational event history from the baseline communications behavior are determined. |
| US09542648B2 |
Intelligent contextually aware digital assistants
One embodiment of the present invention provides a system for providing context-based web services for a user. During operation, the system receives a sentence as input from a user. The system performs natural language processing on the sentence to determine one or more parameters. The system retrieves data from a foreground knowledge graph containing contextual data for the user and from a background knowledge graph containing background information corresponding to the parameters. The system determines a set of arguments based on the parameters and/or data from the foreground knowledge graph and/or data from the background knowledge graph. The system then selects an action module based on results of the natural language processing and/or the set of arguments. The system passes the arguments to the action module. The action module then uses the arguments to respond to a question or interact with web services to perform an action for the user. |
| US09542647B1 |
Method and system for an ontology, including a representation of unified medical language system (UMLS) using simple knowledge organization system (SKOS)
Embodiments of an informatics platform where collected data can be normalized, integrated and mapped to a knowledge source, such as medical vocabulary systems are disclosed. One example of such a knowledge source is Unified Medical Language System (UMLS) which is a knowledge source for biomedical applications. Embodiments as depicted herein may provided a method to convert the desired information from UMLS into an ontology representation to allow for its use in conjunction with an informatics system. |
| US09542644B2 |
Methods and apparatus for modulating the training of a neural device
Methods and apparatus are provided for training a neural device having an artificial nervous system by modulating at least one training parameter during the training. One example method for training a neural device having an artificial nervous system generally includes observing the neural device in a training environment and modulating at least one training parameter based at least in part on the observing. For example, the training apparatus described herein may modify the neural device's internal learning mechanisms (e.g., spike rate, learning rate, neuromodulators, sensor sensitivity, etc.) and/or the training environment's stimuli (e.g., move a flame closer to the device, make the scene darker, etc.). In this manner, the speed with which the neural device is trained (i.e., the training rate) may be significantly increased compared to conventional neural device training systems. |
| US09542641B2 |
Systems and methods for fault diagnosis in molecular networks
The present disclosure provides advantageous systems and methods for identifying molecular vulnerabilities in biological pathways and networks. The present disclosure generally involves conceptualizing a disease/disorder at the molecular level as a faulty physiological system, wherein one or more molecules in the complex intracellular signaling network are dysfunctional. This is accomplished by modeling a given physiological system as a digital logic circuit. More particularly, in exemplarily embodiments, binary logic equations are derived by analyzing the interactions between the input and output nodes of a target biological system. These equations are then used to produce a digital circuit representation for the system. Once a digital circuit representation is created, this circuit may advantageously be analyzed, using fault analysis techniques, in order to determine the vulnerability levels of the molecules of the targeted system. |
| US09542639B1 |
RFID transponder with rectifier and voltage limiter
The present invention relates to a transponder, which comprises an antenna and a multi-stage rectifier. The antenna is connected to an input of the multi-stage rectifier having m rectifier stages, and a shunt limiter is connected to an output of the rectifier and connected to an nth stage of the multi-stage rectifier, wherein n |
| US09542634B2 |
Method for the production of a portable data support
A method for the production of a portable data carrier having an integrated circuit and a contact field galvanically connected to the integrated circuit. In an area defined by the contact field, the portable data carrier is shaped and the contact field is embodied such that a direct contacting of the contact field by a contacting component embodied in accordance with the USB standard is possible. The portable data carrier in its final form is produced in chip card technology. Alternatively, an element is produced in chip card technology, which element features the integrated circuit and the contact filed, and data and/or program code required for the operation of the portable data carrier are loaded into the integrated circuit. Subsequently the element is permanently connected to a carrier. |
| US09542633B2 |
Membrane and method for the production thereof
A membrane which is provided with a membrane surface that represents the functional region of the membrane and which is provided with a tab that projects beyond the membrane surface is described. The membrane and the tab are constructed from a number of layers, wherein at least one of the layers consists of an elastomer. Arranged in the tab is an electronic data carrier. The tab has an upper and a lower layer. The data carrier is enclosed by the layers of the tab and the upper and the lower layer. |
| US09542632B2 |
IC card, portable electronic device, and reader/writer
An IC card of an embodiment is provided with a receiver to receive a first command transmitted from an external device, a determining processor to determine whether or not the first command is a switching request command to request switching the IC card from a passive mode to an active mode, a switching processor to switch oneself from the passive mode to the active mode, when the first command is the switching request command, an identification information acquiring processor to acquire identification information of other IC card existing in a communicable range of the external device from the switching request command, a command generating processor to generate a second command which includes the identification information acquired by the identification information acquiring processor so as to make the other IC card execute processing, and a command transmitter to transmit the second command to the other IC card. |
| US09542631B2 |
Dual frequency HF-UHF identification device, in particular of the passive type
The dual frequency RF identification device comprises an HF antenna for receiving an HF electromagnetic field, an HF interface, an UHF antenna for receiving an UHF electromagnetic field, an UHF interface, non-volatile memory means formed by a first non-volatile memory and a second non-volatile memory. The first non-volatile memory can be in an active state without the second non-volatile memory being powered and consumes substantially more power than this second non-volatile memory. The first non-volatile memory comprises all data needed for a device configuration allowing this device to carry out at least a communication mode of an UHF protocol, this communication mode having access to the first non-volatile memory but not to the second non-volatile memory. The first non-volatile memory further comprises all attributes needed for a configuration of this communication mode. |
| US09542630B2 |
Method of securely reading data from a transponder
The invention discloses a method of reading data (dat) from a first transponder (TAG1) into a transceiver (REA). Said (dat) are only transmitted from the first transponder (TAG1) to the transceiver (REA) when a second transponder (TAG2) is present within the RFID communication range of the transceiver (REA) and if a positive authentication procedure between the two transponders (TAG1, TAG2) within the RFID communication range of the transceiver (REA) takes place. The second transponder (TAG2) is preferably a stationary transponder (TAG2), whereas the first transponder (TAG1) may be a mobile transponder. The invention further relates to transponders (TAG1, TAG2) as well as to a transceiver (REA) used in such a method of reading data (dat). Furthermore, the invention relates to a poster (POS), to which a first transponder (TAG1) is attached, and to a poster wall (WAL) for attaching such a poster (POS) and a second transponder (TAG2). |
| US09542629B2 |
Image processing apparatus, image processing method, and program
An image processing apparatus according to the present invention includes an image forming unit configured to form an image, a measuring unit configured to measure the formed image, a control unit configured to control execution of a single-color calibration to be performed to correct reproduction characteristics of a single-color formed by the image forming unit based on a measuring result of a single-color image formed with a single-color recording agent and execution of a multi-color calibration to be performed to correct reproduction characteristics of a multi-color image formed by the image forming unit based on a measuring result of a multi-color formed with a plurality of recording agents, and a selection unit configured to select whether to cause the control unit to perform the multi-color calibration after completing the single-color calibration or cause the control unit to perform any one of the single-color calibration and the multi-color calibration. |
| US09542628B2 |
Image forming apparatus, non-transitory computer-readable storage medium storing computer-readable instructions, and printing apparatus
An image forming apparatus including an image forming unit and a controller causing the image forming unit to perform printing in printing periods after respective non-printing periods occurring alternately with the printing periods, determining a number of sheets to be printed in each of the printing periods in accordance with a number of sheets remaining to be printed in a print job, wherein, when printing periods include a first printing period and a second printing period, determining a number of sheets to be printed in the first printing period and determining a number of sheets to be printed in the second printing period which is in relation to the determined number of sheets to be printed in the first printing period, and determining a length of each of the non-printing periods in accordance with the determined number of sheets to be printed in each of the printing periods. |